1*53880e38SVijendar Mukunda /* SPDX-License-Identifier: GPL-2.0+ */ 2*53880e38SVijendar Mukunda /* 3*53880e38SVijendar Mukunda * AMD ACP 6.x Register Documentation 4*53880e38SVijendar Mukunda * 5*53880e38SVijendar Mukunda * Copyright 2021 Advanced Micro Devices, Inc. 6*53880e38SVijendar Mukunda */ 7*53880e38SVijendar Mukunda 8*53880e38SVijendar Mukunda #ifndef _acp6x_OFFSET_HEADER 9*53880e38SVijendar Mukunda #define _acp6x_OFFSET_HEADER 10*53880e38SVijendar Mukunda 11*53880e38SVijendar Mukunda /* Registers from ACP_DMA block */ 12*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_0 0x1240000 13*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_1 0x1240004 14*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_2 0x1240008 15*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_3 0x124000C 16*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_4 0x1240010 17*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_5 0x1240014 18*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_6 0x1240018 19*53880e38SVijendar Mukunda #define ACP_DMA_CNTL_7 0x124001C 20*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_0 0x1240020 21*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_1 0x1240024 22*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_2 0x1240028 23*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_3 0x124002C 24*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_4 0x1240030 25*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_5 0x1240034 26*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_6 0x1240038 27*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_STRT_IDX_7 0x124003C 28*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_0 0x1240040 29*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_1 0x1240044 30*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_2 0x1240048 31*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_3 0x124004C 32*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_4 0x1240050 33*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_5 0x1240054 34*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_6 0x1240058 35*53880e38SVijendar Mukunda #define ACP_DMA_DSCR_CNT_7 0x124005C 36*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_0 0x1240060 37*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_1 0x1240064 38*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_2 0x1240068 39*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_3 0x124006C 40*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_4 0x1240070 41*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_5 0x1240074 42*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_6 0x1240078 43*53880e38SVijendar Mukunda #define ACP_DMA_PRIO_7 0x124007C 44*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_0 0x1240080 45*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_1 0x1240084 46*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_2 0x1240088 47*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_3 0x124008C 48*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_4 0x1240090 49*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_5 0x1240094 50*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_6 0x1240098 51*53880e38SVijendar Mukunda #define ACP_DMA_CUR_DSCR_7 0x124009C 52*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_0 0x12400A0 53*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_1 0x12400A4 54*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_2 0x12400A8 55*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_3 0x12400AC 56*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_4 0x12400B0 57*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_5 0x12400B4 58*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_6 0x12400B8 59*53880e38SVijendar Mukunda #define ACP_DMA_CUR_TRANS_CNT_7 0x12400BC 60*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_0 0x12400C0 61*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_1 0x12400C4 62*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_2 0x12400C8 63*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_3 0x12400CC 64*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_4 0x12400D0 65*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_5 0x12400D4 66*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_6 0x12400D8 67*53880e38SVijendar Mukunda #define ACP_DMA_ERR_STS_7 0x12400DC 68*53880e38SVijendar Mukunda #define ACP_DMA_DESC_BASE_ADDR 0x12400E0 69*53880e38SVijendar Mukunda #define ACP_DMA_DESC_MAX_NUM_DSCR 0x12400E4 70*53880e38SVijendar Mukunda #define ACP_DMA_CH_STS 0x12400E8 71*53880e38SVijendar Mukunda #define ACP_DMA_CH_GROUP 0x12400EC 72*53880e38SVijendar Mukunda #define ACP_DMA_CH_RST_STS 0x12400F0 73*53880e38SVijendar Mukunda 74*53880e38SVijendar Mukunda /* Registers from ACP_AXI2AXIATU block */ 75*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x1240C00 76*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x1240C04 77*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x1240C08 78*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x1240C0C 79*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x1240C10 80*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x1240C14 81*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x1240C18 82*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x1240C1C 83*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x1240C20 84*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x1240C24 85*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x1240C28 86*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x1240C2C 87*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x1240C30 88*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x1240C34 89*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x1240C38 90*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x1240C3C 91*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_CTRL 0x1240C40 92*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x1240C44 93*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x1240C48 94*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x1240C4C 95*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x1240C50 96*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x1240C54 97*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x1240C58 98*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x1240C5C 99*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x1240C60 100*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x1240C64 101*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x1240C68 102*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x1240C6C 103*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x1240C70 104*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x1240C74 105*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x1240C78 106*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x1240C7C 107*53880e38SVijendar Mukunda #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x1240C80 108*53880e38SVijendar Mukunda 109*53880e38SVijendar Mukunda /* Registers from ACP_CLKRST block */ 110*53880e38SVijendar Mukunda #define ACP_SOFT_RESET 0x1241000 111*53880e38SVijendar Mukunda #define ACP_CONTROL 0x1241004 112*53880e38SVijendar Mukunda #define ACP_STATUS 0x1241008 113*53880e38SVijendar Mukunda #define ACP_DYNAMIC_CG_MASTER_CONTROL 0x1241010 114*53880e38SVijendar Mukunda #define ACP_ZSC_DSP_CTRL 0x1241014 115*53880e38SVijendar Mukunda #define ACP_ZSC_STS 0x1241018 116*53880e38SVijendar Mukunda #define ACP_PGFSM_CONTROL 0x1241024 117*53880e38SVijendar Mukunda #define ACP_PGFSM_STATUS 0x1241028 118*53880e38SVijendar Mukunda #define ACP_CLKMUX_SEL 0x124102C 119*53880e38SVijendar Mukunda 120*53880e38SVijendar Mukunda /* Registers from ACP_AON block */ 121*53880e38SVijendar Mukunda #define ACP_PME_EN 0x1241400 122*53880e38SVijendar Mukunda #define ACP_DEVICE_STATE 0x1241404 123*53880e38SVijendar Mukunda #define AZ_DEVICE_STATE 0x1241408 124*53880e38SVijendar Mukunda #define ACP_PIN_CONFIG 0x1241440 125*53880e38SVijendar Mukunda #define ACP_PAD_PULLUP_CTRL 0x1241444 126*53880e38SVijendar Mukunda #define ACP_PAD_PULLDOWN_CTRL 0x1241448 127*53880e38SVijendar Mukunda #define ACP_PAD_DRIVE_STRENGTH_CTRL 0x124144C 128*53880e38SVijendar Mukunda #define ACP_PAD_SCHMEN_CTRL 0x1241450 129*53880e38SVijendar Mukunda #define ACP_SW_PAD_KEEPER_EN 0x1241454 130*53880e38SVijendar Mukunda #define ACP_SW_WAKE_EN 0x1241458 131*53880e38SVijendar Mukunda #define ACP_I2S_WAKE_EN 0x124145C 132*53880e38SVijendar Mukunda #define ACP_SW1_WAKE_EN 0x1241460 133*53880e38SVijendar Mukunda 134*53880e38SVijendar Mukunda /* Registers from ACP_P1_MISC block */ 135*53880e38SVijendar Mukunda #define ACP_EXTERNAL_INTR_ENB 0x1241A00 136*53880e38SVijendar Mukunda #define ACP_EXTERNAL_INTR_CNTL 0x1241A04 137*53880e38SVijendar Mukunda #define ACP_EXTERNAL_INTR_CNTL1 0x1241A08 138*53880e38SVijendar Mukunda #define ACP_EXTERNAL_INTR_STAT 0x1241A0C 139*53880e38SVijendar Mukunda #define ACP_EXTERNAL_INTR_STAT1 0x1241A10 140*53880e38SVijendar Mukunda #define ACP_ERROR_STATUS 0x1241A4C 141*53880e38SVijendar Mukunda #define ACP_P1_SW_I2S_ERROR_REASON 0x1241A50 142*53880e38SVijendar Mukunda #define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x1241A6C 143*53880e38SVijendar Mukunda #define ACP_P1_SW_I2S_TX_DMA_POS 0x1241A70 144*53880e38SVijendar Mukunda #define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x1241A74 145*53880e38SVijendar Mukunda #define ACP_P1_SW_I2S_RX_DMA_POS 0x1241A78 146*53880e38SVijendar Mukunda #define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x1241A7C 147*53880e38SVijendar Mukunda #define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x1241A80 148*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_BASE_ADDR 0x1241A84 149*53880e38SVijendar Mukunda #define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x1241A88 150*53880e38SVijendar Mukunda #define ACP_P1_SW_BT_TX_DMA_POS 0x1241A8C 151*53880e38SVijendar Mukunda #define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x1241A90 152*53880e38SVijendar Mukunda #define ACP_P1_SW_HS_TX_DMA_POS 0x1241A94 153*53880e38SVijendar Mukunda #define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x1241A98 154*53880e38SVijendar Mukunda #define ACP_P1_SW_BT_RX_DMA_POS 0x1241A9C 155*53880e38SVijendar Mukunda #define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x1241AA0 156*53880e38SVijendar Mukunda #define ACP_P1_SW_HS_RX_DMA_POS 0x1241AA4 157*53880e38SVijendar Mukunda 158*53880e38SVijendar Mukunda /* Registers from ACP_AUDIO_BUFFERS block */ 159*53880e38SVijendar Mukunda #define ACP_I2S_RX_RINGBUFADDR 0x1242000 160*53880e38SVijendar Mukunda #define ACP_I2S_RX_RINGBUFSIZE 0x1242004 161*53880e38SVijendar Mukunda #define ACP_I2S_RX_LINKPOSITIONCNTR 0x1242008 162*53880e38SVijendar Mukunda #define ACP_I2S_RX_FIFOADDR 0x124200C 163*53880e38SVijendar Mukunda #define ACP_I2S_RX_FIFOSIZE 0x1242010 164*53880e38SVijendar Mukunda #define ACP_I2S_RX_DMA_SIZE 0x1242014 165*53880e38SVijendar Mukunda #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1242018 166*53880e38SVijendar Mukunda #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x124201C 167*53880e38SVijendar Mukunda #define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x1242020 168*53880e38SVijendar Mukunda #define ACP_I2S_TX_RINGBUFADDR 0x1242024 169*53880e38SVijendar Mukunda #define ACP_I2S_TX_RINGBUFSIZE 0x1242028 170*53880e38SVijendar Mukunda #define ACP_I2S_TX_LINKPOSITIONCNTR 0x124202C 171*53880e38SVijendar Mukunda #define ACP_I2S_TX_FIFOADDR 0x1242030 172*53880e38SVijendar Mukunda #define ACP_I2S_TX_FIFOSIZE 0x1242034 173*53880e38SVijendar Mukunda #define ACP_I2S_TX_DMA_SIZE 0x1242038 174*53880e38SVijendar Mukunda #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x124203C 175*53880e38SVijendar Mukunda #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1242040 176*53880e38SVijendar Mukunda #define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x1242044 177*53880e38SVijendar Mukunda #define ACP_BT_RX_RINGBUFADDR 0x1242048 178*53880e38SVijendar Mukunda #define ACP_BT_RX_RINGBUFSIZE 0x124204C 179*53880e38SVijendar Mukunda #define ACP_BT_RX_LINKPOSITIONCNTR 0x1242050 180*53880e38SVijendar Mukunda #define ACP_BT_RX_FIFOADDR 0x1242054 181*53880e38SVijendar Mukunda #define ACP_BT_RX_FIFOSIZE 0x1242058 182*53880e38SVijendar Mukunda #define ACP_BT_RX_DMA_SIZE 0x124205C 183*53880e38SVijendar Mukunda #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1242060 184*53880e38SVijendar Mukunda #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x1242064 185*53880e38SVijendar Mukunda #define ACP_BT_RX_INTR_WATERMARK_SIZE 0x1242068 186*53880e38SVijendar Mukunda #define ACP_BT_TX_RINGBUFADDR 0x124206C 187*53880e38SVijendar Mukunda #define ACP_BT_TX_RINGBUFSIZE 0x1242070 188*53880e38SVijendar Mukunda #define ACP_BT_TX_LINKPOSITIONCNTR 0x1242074 189*53880e38SVijendar Mukunda #define ACP_BT_TX_FIFOADDR 0x1242078 190*53880e38SVijendar Mukunda #define ACP_BT_TX_FIFOSIZE 0x124207C 191*53880e38SVijendar Mukunda #define ACP_BT_TX_DMA_SIZE 0x1242080 192*53880e38SVijendar Mukunda #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1242084 193*53880e38SVijendar Mukunda #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x1242088 194*53880e38SVijendar Mukunda #define ACP_BT_TX_INTR_WATERMARK_SIZE 0x124208C 195*53880e38SVijendar Mukunda #define ACP_HS_RX_RINGBUFADDR 0x1242090 196*53880e38SVijendar Mukunda #define ACP_HS_RX_RINGBUFSIZE 0x1242094 197*53880e38SVijendar Mukunda #define ACP_HS_RX_LINKPOSITIONCNTR 0x1242098 198*53880e38SVijendar Mukunda #define ACP_HS_RX_FIFOADDR 0x124209C 199*53880e38SVijendar Mukunda #define ACP_HS_RX_FIFOSIZE 0x12420A0 200*53880e38SVijendar Mukunda #define ACP_HS_RX_DMA_SIZE 0x12420A4 201*53880e38SVijendar Mukunda #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x12420A8 202*53880e38SVijendar Mukunda #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x12420AC 203*53880e38SVijendar Mukunda #define ACP_HS_RX_INTR_WATERMARK_SIZE 0x12420B0 204*53880e38SVijendar Mukunda #define ACP_HS_TX_RINGBUFADDR 0x12420B4 205*53880e38SVijendar Mukunda #define ACP_HS_TX_RINGBUFSIZE 0x12420B8 206*53880e38SVijendar Mukunda #define ACP_HS_TX_LINKPOSITIONCNTR 0x12420BC 207*53880e38SVijendar Mukunda #define ACP_HS_TX_FIFOADDR 0x12420C0 208*53880e38SVijendar Mukunda #define ACP_HS_TX_FIFOSIZE 0x12420C4 209*53880e38SVijendar Mukunda #define ACP_HS_TX_DMA_SIZE 0x12420C8 210*53880e38SVijendar Mukunda #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x12420CC 211*53880e38SVijendar Mukunda #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x12420D0 212*53880e38SVijendar Mukunda #define ACP_HS_TX_INTR_WATERMARK_SIZE 0x12420D4 213*53880e38SVijendar Mukunda 214*53880e38SVijendar Mukunda /* Registers from ACP_I2S_TDM block */ 215*53880e38SVijendar Mukunda #define ACP_I2STDM_IER 0x1242400 216*53880e38SVijendar Mukunda #define ACP_I2STDM_IRER 0x1242404 217*53880e38SVijendar Mukunda #define ACP_I2STDM_RXFRMT 0x1242408 218*53880e38SVijendar Mukunda #define ACP_I2STDM_ITER 0x124240C 219*53880e38SVijendar Mukunda #define ACP_I2STDM_TXFRMT 0x1242410 220*53880e38SVijendar Mukunda #define ACP_I2STDM0_MSTRCLKGEN 0x1242414 221*53880e38SVijendar Mukunda #define ACP_I2STDM1_MSTRCLKGEN 0x1242418 222*53880e38SVijendar Mukunda #define ACP_I2STDM2_MSTRCLKGEN 0x124241C 223*53880e38SVijendar Mukunda #define ACP_I2STDM_REFCLKGEN 0x1242420 224*53880e38SVijendar Mukunda 225*53880e38SVijendar Mukunda /* Registers from ACP_BT_TDM block */ 226*53880e38SVijendar Mukunda #define ACP_BTTDM_IER 0x1242800 227*53880e38SVijendar Mukunda #define ACP_BTTDM_IRER 0x1242804 228*53880e38SVijendar Mukunda #define ACP_BTTDM_RXFRMT 0x1242808 229*53880e38SVijendar Mukunda #define ACP_BTTDM_ITER 0x124280C 230*53880e38SVijendar Mukunda #define ACP_BTTDM_TXFRMT 0x1242810 231*53880e38SVijendar Mukunda #define ACP_HSTDM_IER 0x1242814 232*53880e38SVijendar Mukunda #define ACP_HSTDM_IRER 0x1242818 233*53880e38SVijendar Mukunda #define ACP_HSTDM_RXFRMT 0x124281C 234*53880e38SVijendar Mukunda #define ACP_HSTDM_ITER 0x1242820 235*53880e38SVijendar Mukunda #define ACP_HSTDM_TXFRMT 0x1242824 236*53880e38SVijendar Mukunda 237*53880e38SVijendar Mukunda /* Registers from ACP_WOV block */ 238*53880e38SVijendar Mukunda #define ACP_WOV_PDM_ENABLE 0x1242C04 239*53880e38SVijendar Mukunda #define ACP_WOV_PDM_DMA_ENABLE 0x1242C08 240*53880e38SVijendar Mukunda #define ACP_WOV_RX_RINGBUFADDR 0x1242C0C 241*53880e38SVijendar Mukunda #define ACP_WOV_RX_RINGBUFSIZE 0x1242C10 242*53880e38SVijendar Mukunda #define ACP_WOV_RX_LINKPOSITIONCNTR 0x1242C14 243*53880e38SVijendar Mukunda #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x1242C18 244*53880e38SVijendar Mukunda #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x1242C1C 245*53880e38SVijendar Mukunda #define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x1242C20 246*53880e38SVijendar Mukunda #define ACP_WOV_PDM_FIFO_FLUSH 0x1242C24 247*53880e38SVijendar Mukunda #define ACP_WOV_PDM_NO_OF_CHANNELS 0x1242C28 248*53880e38SVijendar Mukunda #define ACP_WOV_PDM_DECIMATION_FACTOR 0x1242C2C 249*53880e38SVijendar Mukunda #define ACP_WOV_PDM_VAD_CTRL 0x1242C30 250*53880e38SVijendar Mukunda #define ACP_WOV_WAKE 0x1242C54 251*53880e38SVijendar Mukunda #define ACP_WOV_BUFFER_STATUS 0x1242C58 252*53880e38SVijendar Mukunda #define ACP_WOV_MISC_CTRL 0x1242C5C 253*53880e38SVijendar Mukunda #define ACP_WOV_CLK_CTRL 0x1242C60 254*53880e38SVijendar Mukunda #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x1242C64 255*53880e38SVijendar Mukunda #define ACP_WOV_ERROR_STATUS_REGISTER 0x1242C68 256*53880e38SVijendar Mukunda #define ACP_PDM_CLKDIV 0x1242C6C 257*53880e38SVijendar Mukunda 258*53880e38SVijendar Mukunda /* Registers from ACP_P1_AUDIO_BUFFERS block */ 259*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_RINGBUFADDR 0x1243A00 260*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_RINGBUFSIZE 0x1243A04 261*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x1243A08 262*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_FIFOADDR 0x1243A0C 263*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_FIFOSIZE 0x1243A10 264*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_DMA_SIZE 0x1243A14 265*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x1243A18 266*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x1243A1C 267*53880e38SVijendar Mukunda #define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x1243A20 268*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_RINGBUFADDR 0x1243A24 269*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_RINGBUFSIZE 0x1243A28 270*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x1243A2C 271*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_FIFOADDR 0x1243A30 272*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_FIFOSIZE 0x1243A34 273*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_DMA_SIZE 0x1243A38 274*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x1243A3C 275*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x1243A40 276*53880e38SVijendar Mukunda #define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x1243A44 277*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_RINGBUFADDR 0x1243A48 278*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_RINGBUFSIZE 0x1243A4C 279*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x1243A50 280*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_FIFOADDR 0x1243A54 281*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_FIFOSIZE 0x1243A58 282*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_DMA_SIZE 0x1243A5C 283*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x1243A60 284*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x1243A64 285*53880e38SVijendar Mukunda #define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x1243A68 286*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_RINGBUFADDR 0x1243A6C 287*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_RINGBUFSIZE 0x1243A70 288*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x1243A74 289*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_FIFOADDR 0x1243A78 290*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_FIFOSIZE 0x1243A7C 291*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_DMA_SIZE 0x1243A80 292*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x1243A84 293*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x1243A88 294*53880e38SVijendar Mukunda #define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x1243A8C 295*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_RINGBUFADDR 0x1243A90 296*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_RINGBUFSIZE 0x1243A94 297*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x1243A98 298*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_FIFOADDR 0x1243A9C 299*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_FIFOSIZE 0x1243AA0 300*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_DMA_SIZE 0x1243AA4 301*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x1243AA8 302*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x1243AAC 303*53880e38SVijendar Mukunda #define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x1243AB0 304*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_RINGBUFADDR 0x1243AB4 305*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_RINGBUFSIZE 0x1243AB8 306*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x1243ABC 307*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_FIFOADDR 0x1243AC0 308*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_FIFOSIZE 0x1243AC4 309*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_DMA_SIZE 0x1243AC8 310*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x1243ACC 311*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x1243AD0 312*53880e38SVijendar Mukunda #define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x1243AD4 313*53880e38SVijendar Mukunda 314*53880e38SVijendar Mukunda /* Registers from ACP_SCRATCH block */ 315*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_0 0x1250000 316*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_1 0x1250004 317*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_2 0x1250008 318*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_3 0x125000C 319*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_4 0x1250010 320*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_5 0x1250014 321*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_6 0x1250018 322*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_7 0x125001C 323*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_8 0x1250020 324*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_9 0x1250024 325*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_10 0x1250028 326*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_11 0x125002C 327*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_12 0x1250030 328*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_13 0x1250034 329*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_14 0x1250038 330*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_15 0x125003C 331*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_16 0x1250040 332*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_17 0x1250044 333*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_18 0x1250048 334*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_19 0x125004C 335*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_20 0x1250050 336*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_21 0x1250054 337*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_22 0x1250058 338*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_23 0x125005C 339*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_24 0x1250060 340*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_25 0x1250064 341*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_26 0x1250068 342*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_27 0x125006C 343*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_28 0x1250070 344*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_29 0x1250074 345*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_30 0x1250078 346*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_31 0x125007C 347*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_32 0x1250080 348*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_33 0x1250084 349*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_34 0x1250088 350*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_35 0x125008C 351*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_36 0x1250090 352*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_37 0x1250094 353*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_38 0x1250098 354*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_39 0x125009C 355*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_40 0x12500A0 356*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_41 0x12500A4 357*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_42 0x12500A8 358*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_43 0x12500AC 359*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_44 0x12500B0 360*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_45 0x12500B4 361*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_46 0x12500B8 362*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_47 0x12500BC 363*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_48 0x12500C0 364*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_49 0x12500C4 365*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_50 0x12500C8 366*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_51 0x12500CC 367*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_52 0x12500D0 368*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_53 0x12500D4 369*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_54 0x12500D8 370*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_55 0x12500DC 371*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_56 0x12500E0 372*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_57 0x12500E4 373*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_58 0x12500E8 374*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_59 0x12500EC 375*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_60 0x12500F0 376*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_61 0x12500F4 377*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_62 0x12500F8 378*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_63 0x12500FC 379*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_64 0x1250100 380*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_65 0x1250104 381*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_66 0x1250108 382*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_67 0x125010C 383*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_68 0x1250110 384*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_69 0x1250114 385*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_70 0x1250118 386*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_71 0x125011C 387*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_72 0x1250120 388*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_73 0x1250124 389*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_74 0x1250128 390*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_75 0x125012C 391*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_76 0x1250130 392*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_77 0x1250134 393*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_78 0x1250138 394*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_79 0x125013C 395*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_80 0x1250140 396*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_81 0x1250144 397*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_82 0x1250148 398*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_83 0x125014C 399*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_84 0x1250150 400*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_85 0x1250154 401*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_86 0x1250158 402*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_87 0x125015C 403*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_88 0x1250160 404*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_89 0x1250164 405*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_90 0x1250168 406*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_91 0x125016C 407*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_92 0x1250170 408*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_93 0x1250174 409*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_94 0x1250178 410*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_95 0x125017C 411*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_96 0x1250180 412*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_97 0x1250184 413*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_98 0x1250188 414*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_99 0x125018C 415*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_100 0x1250190 416*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_101 0x1250194 417*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_102 0x1250198 418*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_103 0x125019C 419*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_104 0x12501A0 420*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_105 0x12501A4 421*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_106 0x12501A8 422*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_107 0x12501AC 423*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_108 0x12501B0 424*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_109 0x12501B4 425*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_110 0x12501B8 426*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_111 0x12501BC 427*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_112 0x12501C0 428*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_113 0x12501C4 429*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_114 0x12501C8 430*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_115 0x12501CC 431*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_116 0x12501D0 432*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_117 0x12501D4 433*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_118 0x12501D8 434*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_119 0x12501DC 435*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_120 0x12501E0 436*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_121 0x12501E4 437*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_122 0x12501E8 438*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_123 0x12501EC 439*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_124 0x12501F0 440*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_125 0x12501F4 441*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_126 0x12501F8 442*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_127 0x12501FC 443*53880e38SVijendar Mukunda #define ACP_SCRATCH_REG_128 0x1250200 444*53880e38SVijendar Mukunda #endif 445