1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ALSA SoC PCM Driver 4 * 5 * Copyright 2016 Advanced Micro Devices, Inc. 6 */ 7 8 #include "chip_offset_byte.h" 9 #include <sound/pcm.h> 10 #define I2S_SP_INSTANCE 0x01 11 #define I2S_BT_INSTANCE 0x02 12 13 #define TDM_ENABLE 1 14 #define TDM_DISABLE 0 15 16 #define ACP3x_DEVS 4 17 #define ACP3x_PHY_BASE_ADDRESS 0x1240000 18 #define ACP3x_I2S_MODE 0 19 #define ACP3x_REG_START 0x1240000 20 #define ACP3x_REG_END 0x1250200 21 #define ACP3x_I2STDM_REG_START 0x1242400 22 #define ACP3x_I2STDM_REG_END 0x1242410 23 #define ACP3x_BT_TDM_REG_START 0x1242800 24 #define ACP3x_BT_TDM_REG_END 0x1242810 25 #define I2S_MODE 0x04 26 #define I2S_RX_THRESHOLD 27 27 #define I2S_TX_THRESHOLD 28 28 #define BT_TX_THRESHOLD 26 29 #define BT_RX_THRESHOLD 25 30 #define ACP_ERR_INTR_MASK 29 31 #define ACP3x_POWER_ON 0x00 32 #define ACP3x_POWER_ON_IN_PROGRESS 0x01 33 #define ACP3x_POWER_OFF 0x02 34 #define ACP3x_POWER_OFF_IN_PROGRESS 0x03 35 #define ACP3x_SOFT_RESET__SoftResetAudDone_MASK 0x00010001 36 37 #define ACP_SRAM_PTE_OFFSET 0x02050000 38 #define ACP_SRAM_SP_PB_PTE_OFFSET 0x0 39 #define ACP_SRAM_SP_CP_PTE_OFFSET 0x100 40 #define ACP_SRAM_BT_PB_PTE_OFFSET 0x200 41 #define ACP_SRAM_BT_CP_PTE_OFFSET 0x300 42 #define PAGE_SIZE_4K_ENABLE 0x2 43 #define I2S_SP_TX_MEM_WINDOW_START 0x4000000 44 #define I2S_SP_RX_MEM_WINDOW_START 0x4020000 45 #define I2S_BT_TX_MEM_WINDOW_START 0x4040000 46 #define I2S_BT_RX_MEM_WINDOW_START 0x4060000 47 48 #define SP_PB_FIFO_ADDR_OFFSET 0x500 49 #define SP_CAPT_FIFO_ADDR_OFFSET 0x700 50 #define BT_PB_FIFO_ADDR_OFFSET 0x900 51 #define BT_CAPT_FIFO_ADDR_OFFSET 0xB00 52 #define PLAYBACK_MIN_NUM_PERIODS 2 53 #define PLAYBACK_MAX_NUM_PERIODS 8 54 #define PLAYBACK_MAX_PERIOD_SIZE 8192 55 #define PLAYBACK_MIN_PERIOD_SIZE 1024 56 #define CAPTURE_MIN_NUM_PERIODS 2 57 #define CAPTURE_MAX_NUM_PERIODS 8 58 #define CAPTURE_MAX_PERIOD_SIZE 8192 59 #define CAPTURE_MIN_PERIOD_SIZE 1024 60 61 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 62 #define MIN_BUFFER MAX_BUFFER 63 #define FIFO_SIZE 0x100 64 #define DMA_SIZE 0x40 65 #define FRM_LEN 0x100 66 67 #define SLOT_WIDTH_8 0x08 68 #define SLOT_WIDTH_16 0x10 69 #define SLOT_WIDTH_24 0x18 70 #define SLOT_WIDTH_32 0x20 71 #define ACP_PGFSM_CNTL_POWER_ON_MASK 0x01 72 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0x00 73 #define ACP_PGFSM_STATUS_MASK 0x03 74 #define ACP_POWERED_ON 0x00 75 #define ACP_POWER_ON_IN_PROGRESS 0x01 76 #define ACP_POWERED_OFF 0x02 77 #define ACP_POWER_OFF_IN_PROGRESS 0x03 78 79 struct acp3x_platform_info { 80 u16 play_i2s_instance; 81 u16 cap_i2s_instance; 82 u16 capture_channel; 83 }; 84 85 struct i2s_dev_data { 86 bool tdm_mode; 87 unsigned int i2s_irq; 88 u16 i2s_instance; 89 u32 tdm_fmt; 90 u32 substream_type; 91 void __iomem *acp3x_base; 92 struct snd_pcm_substream *play_stream; 93 struct snd_pcm_substream *capture_stream; 94 struct snd_pcm_substream *i2ssp_play_stream; 95 struct snd_pcm_substream *i2ssp_capture_stream; 96 }; 97 98 struct i2s_stream_instance { 99 u16 num_pages; 100 u16 i2s_instance; 101 u16 capture_channel; 102 u16 direction; 103 u16 channels; 104 u32 xfer_resolution; 105 u32 val; 106 dma_addr_t dma_addr; 107 u64 bytescount; 108 void __iomem *acp3x_base; 109 }; 110 111 static inline u32 rv_readl(void __iomem *base_addr) 112 { 113 return readl(base_addr - ACP3x_PHY_BASE_ADDRESS); 114 } 115 116 static inline void rv_writel(u32 val, void __iomem *base_addr) 117 { 118 writel(val, base_addr - ACP3x_PHY_BASE_ADDRESS); 119 } 120 121 static inline u64 acp_get_byte_count(struct i2s_stream_instance *rtd, 122 int direction) 123 { 124 u64 byte_count; 125 126 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 127 switch (rtd->i2s_instance) { 128 case I2S_BT_INSTANCE: 129 byte_count = rv_readl(rtd->acp3x_base + 130 mmACP_BT_TX_LINEARPOSITIONCNTR_HIGH); 131 byte_count |= rv_readl(rtd->acp3x_base + 132 mmACP_BT_TX_LINEARPOSITIONCNTR_LOW); 133 break; 134 case I2S_SP_INSTANCE: 135 default: 136 byte_count = rv_readl(rtd->acp3x_base + 137 mmACP_I2S_TX_LINEARPOSITIONCNTR_HIGH); 138 byte_count |= rv_readl(rtd->acp3x_base + 139 mmACP_I2S_TX_LINEARPOSITIONCNTR_LOW); 140 } 141 142 } else { 143 switch (rtd->i2s_instance) { 144 case I2S_BT_INSTANCE: 145 byte_count = rv_readl(rtd->acp3x_base + 146 mmACP_BT_RX_LINEARPOSITIONCNTR_HIGH); 147 byte_count |= rv_readl(rtd->acp3x_base + 148 mmACP_BT_RX_LINEARPOSITIONCNTR_LOW); 149 break; 150 case I2S_SP_INSTANCE: 151 default: 152 byte_count = rv_readl(rtd->acp3x_base + 153 mmACP_I2S_RX_LINEARPOSITIONCNTR_HIGH); 154 byte_count |= rv_readl(rtd->acp3x_base + 155 mmACP_I2S_RX_LINEARPOSITIONCNTR_LOW); 156 } 157 } 158 return byte_count; 159 } 160