1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // AMD ALSA SoC PCM Driver 4 // 5 //Copyright 2016 Advanced Micro Devices, Inc. 6 7 #include <linux/platform_device.h> 8 #include <linux/module.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/pm_runtime.h> 12 #include <sound/pcm.h> 13 #include <sound/pcm_params.h> 14 #include <sound/soc.h> 15 #include <sound/soc-dai.h> 16 17 #include "acp3x.h" 18 19 #define DRV_NAME "acp3x-i2s-audio" 20 21 struct i2s_dev_data { 22 bool tdm_mode; 23 unsigned int i2s_irq; 24 u32 tdm_fmt; 25 void __iomem *acp3x_base; 26 struct snd_pcm_substream *play_stream; 27 struct snd_pcm_substream *capture_stream; 28 }; 29 30 struct i2s_stream_instance { 31 u16 num_pages; 32 u16 channels; 33 u32 xfer_resolution; 34 struct page *pg; 35 void __iomem *acp3x_base; 36 }; 37 38 static const struct snd_pcm_hardware acp3x_pcm_hardware_playback = { 39 .info = SNDRV_PCM_INFO_INTERLEAVED | 40 SNDRV_PCM_INFO_BLOCK_TRANSFER | 41 SNDRV_PCM_INFO_BATCH | 42 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 43 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 44 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | 45 SNDRV_PCM_FMTBIT_S32_LE, 46 .channels_min = 2, 47 .channels_max = 8, 48 .rates = SNDRV_PCM_RATE_8000_96000, 49 .rate_min = 8000, 50 .rate_max = 96000, 51 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 52 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 53 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 54 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 55 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 56 }; 57 58 static const struct snd_pcm_hardware acp3x_pcm_hardware_capture = { 59 .info = SNDRV_PCM_INFO_INTERLEAVED | 60 SNDRV_PCM_INFO_BLOCK_TRANSFER | 61 SNDRV_PCM_INFO_BATCH | 62 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 63 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 64 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S24_LE | 65 SNDRV_PCM_FMTBIT_S32_LE, 66 .channels_min = 2, 67 .channels_max = 2, 68 .rates = SNDRV_PCM_RATE_8000_48000, 69 .rate_min = 8000, 70 .rate_max = 48000, 71 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 72 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 73 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 74 .periods_min = CAPTURE_MIN_NUM_PERIODS, 75 .periods_max = CAPTURE_MAX_NUM_PERIODS, 76 }; 77 78 static int acp3x_power_on(void __iomem *acp3x_base, bool on) 79 { 80 u16 val, mask; 81 u32 timeout; 82 83 if (on == true) { 84 val = 1; 85 mask = ACP3x_POWER_ON; 86 } else { 87 val = 0; 88 mask = ACP3x_POWER_OFF; 89 } 90 91 rv_writel(val, acp3x_base + mmACP_PGFSM_CONTROL); 92 timeout = 0; 93 while (true) { 94 val = rv_readl(acp3x_base + mmACP_PGFSM_STATUS); 95 if ((val & ACP3x_POWER_OFF_IN_PROGRESS) == mask) 96 break; 97 if (timeout > 100) { 98 pr_err("ACP3x power state change failure\n"); 99 return -ENODEV; 100 } 101 timeout++; 102 cpu_relax(); 103 } 104 return 0; 105 } 106 107 static int acp3x_reset(void __iomem *acp3x_base) 108 { 109 u32 val, timeout; 110 111 rv_writel(1, acp3x_base + mmACP_SOFT_RESET); 112 timeout = 0; 113 while (true) { 114 val = rv_readl(acp3x_base + mmACP_SOFT_RESET); 115 if ((val & ACP3x_SOFT_RESET__SoftResetAudDone_MASK) || 116 timeout > 100) { 117 if (val & ACP3x_SOFT_RESET__SoftResetAudDone_MASK) 118 break; 119 return -ENODEV; 120 } 121 timeout++; 122 cpu_relax(); 123 } 124 125 rv_writel(0, acp3x_base + mmACP_SOFT_RESET); 126 timeout = 0; 127 while (true) { 128 val = rv_readl(acp3x_base + mmACP_SOFT_RESET); 129 if (!val || timeout > 100) { 130 if (!val) 131 break; 132 return -ENODEV; 133 } 134 timeout++; 135 cpu_relax(); 136 } 137 return 0; 138 } 139 140 static int acp3x_init(void __iomem *acp3x_base) 141 { 142 int ret; 143 144 /* power on */ 145 ret = acp3x_power_on(acp3x_base, true); 146 if (ret) { 147 pr_err("ACP3x power on failed\n"); 148 return ret; 149 } 150 /* Reset */ 151 ret = acp3x_reset(acp3x_base); 152 if (ret) { 153 pr_err("ACP3x reset failed\n"); 154 return ret; 155 } 156 return 0; 157 } 158 159 static int acp3x_deinit(void __iomem *acp3x_base) 160 { 161 int ret; 162 163 /* Reset */ 164 ret = acp3x_reset(acp3x_base); 165 if (ret) { 166 pr_err("ACP3x reset failed\n"); 167 return ret; 168 } 169 /* power off */ 170 ret = acp3x_power_on(acp3x_base, false); 171 if (ret) { 172 pr_err("ACP3x power off failed\n"); 173 return ret; 174 } 175 return 0; 176 } 177 178 static irqreturn_t i2s_irq_handler(int irq, void *dev_id) 179 { 180 u16 play_flag, cap_flag; 181 u32 val; 182 struct i2s_dev_data *rv_i2s_data = dev_id; 183 184 if (!rv_i2s_data) 185 return IRQ_NONE; 186 187 play_flag = 0; 188 cap_flag = 0; 189 val = rv_readl(rv_i2s_data->acp3x_base + mmACP_EXTERNAL_INTR_STAT); 190 if ((val & BIT(BT_TX_THRESHOLD)) && rv_i2s_data->play_stream) { 191 rv_writel(BIT(BT_TX_THRESHOLD), rv_i2s_data->acp3x_base + 192 mmACP_EXTERNAL_INTR_STAT); 193 snd_pcm_period_elapsed(rv_i2s_data->play_stream); 194 play_flag = 1; 195 } 196 197 if ((val & BIT(BT_RX_THRESHOLD)) && rv_i2s_data->capture_stream) { 198 rv_writel(BIT(BT_RX_THRESHOLD), rv_i2s_data->acp3x_base + 199 mmACP_EXTERNAL_INTR_STAT); 200 snd_pcm_period_elapsed(rv_i2s_data->capture_stream); 201 cap_flag = 1; 202 } 203 204 if (play_flag | cap_flag) 205 return IRQ_HANDLED; 206 else 207 return IRQ_NONE; 208 } 209 210 static void config_acp3x_dma(struct i2s_stream_instance *rtd, int direction) 211 { 212 u16 page_idx; 213 u64 addr; 214 u32 low, high, val, acp_fifo_addr; 215 struct page *pg = rtd->pg; 216 217 /* 8 scratch registers used to map one 64 bit address */ 218 if (direction == SNDRV_PCM_STREAM_PLAYBACK) 219 val = 0; 220 else 221 val = rtd->num_pages * 8; 222 223 /* Group Enable */ 224 rv_writel(ACP_SRAM_PTE_OFFSET | BIT(31), rtd->acp3x_base + 225 mmACPAXI2AXI_ATU_BASE_ADDR_GRP_1); 226 rv_writel(PAGE_SIZE_4K_ENABLE, rtd->acp3x_base + 227 mmACPAXI2AXI_ATU_PAGE_SIZE_GRP_1); 228 229 for (page_idx = 0; page_idx < rtd->num_pages; page_idx++) { 230 /* Load the low address of page int ACP SRAM through SRBM */ 231 addr = page_to_phys(pg); 232 low = lower_32_bits(addr); 233 high = upper_32_bits(addr); 234 235 rv_writel(low, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val); 236 high |= BIT(31); 237 rv_writel(high, rtd->acp3x_base + mmACP_SCRATCH_REG_0 + val 238 + 4); 239 /* Move to next physically contiguos page */ 240 val += 8; 241 pg++; 242 } 243 244 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 245 /* Config ringbuffer */ 246 rv_writel(MEM_WINDOW_START, rtd->acp3x_base + 247 mmACP_BT_TX_RINGBUFADDR); 248 rv_writel(MAX_BUFFER, rtd->acp3x_base + 249 mmACP_BT_TX_RINGBUFSIZE); 250 rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_TX_DMA_SIZE); 251 252 /* Config audio fifo */ 253 acp_fifo_addr = ACP_SRAM_PTE_OFFSET + (rtd->num_pages * 8) 254 + PLAYBACK_FIFO_ADDR_OFFSET; 255 rv_writel(acp_fifo_addr, rtd->acp3x_base + 256 mmACP_BT_TX_FIFOADDR); 257 rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_TX_FIFOSIZE); 258 } else { 259 /* Config ringbuffer */ 260 rv_writel(MEM_WINDOW_START + MAX_BUFFER, rtd->acp3x_base + 261 mmACP_BT_RX_RINGBUFADDR); 262 rv_writel(MAX_BUFFER, rtd->acp3x_base + 263 mmACP_BT_RX_RINGBUFSIZE); 264 rv_writel(DMA_SIZE, rtd->acp3x_base + mmACP_BT_RX_DMA_SIZE); 265 266 /* Config audio fifo */ 267 acp_fifo_addr = ACP_SRAM_PTE_OFFSET + 268 (rtd->num_pages * 8) + CAPTURE_FIFO_ADDR_OFFSET; 269 rv_writel(acp_fifo_addr, rtd->acp3x_base + 270 mmACP_BT_RX_FIFOADDR); 271 rv_writel(FIFO_SIZE, rtd->acp3x_base + mmACP_BT_RX_FIFOSIZE); 272 } 273 274 /* Enable watermark/period interrupt to host */ 275 rv_writel(BIT(BT_TX_THRESHOLD) | BIT(BT_RX_THRESHOLD), 276 rtd->acp3x_base + mmACP_EXTERNAL_INTR_CNTL); 277 } 278 279 static int acp3x_dma_open(struct snd_pcm_substream *substream) 280 { 281 int ret = 0; 282 283 struct snd_pcm_runtime *runtime = substream->runtime; 284 struct snd_soc_pcm_runtime *prtd = substream->private_data; 285 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 286 DRV_NAME); 287 struct i2s_dev_data *adata = dev_get_drvdata(component->dev); 288 289 struct i2s_stream_instance *i2s_data = kzalloc(sizeof(struct i2s_stream_instance), 290 GFP_KERNEL); 291 if (!i2s_data) 292 return -EINVAL; 293 294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 295 runtime->hw = acp3x_pcm_hardware_playback; 296 else 297 runtime->hw = acp3x_pcm_hardware_capture; 298 299 ret = snd_pcm_hw_constraint_integer(runtime, 300 SNDRV_PCM_HW_PARAM_PERIODS); 301 if (ret < 0) { 302 dev_err(component->dev, "set integer constraint failed\n"); 303 kfree(i2s_data); 304 return ret; 305 } 306 307 if (!adata->play_stream && !adata->capture_stream) 308 rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB); 309 310 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 311 adata->play_stream = substream; 312 else 313 adata->capture_stream = substream; 314 315 i2s_data->acp3x_base = adata->acp3x_base; 316 runtime->private_data = i2s_data; 317 return 0; 318 } 319 320 static int acp3x_dma_hw_params(struct snd_pcm_substream *substream, 321 struct snd_pcm_hw_params *params) 322 { 323 int status; 324 u64 size; 325 struct page *pg; 326 struct snd_pcm_runtime *runtime = substream->runtime; 327 struct i2s_stream_instance *rtd = runtime->private_data; 328 329 if (!rtd) 330 return -EINVAL; 331 332 size = params_buffer_bytes(params); 333 status = snd_pcm_lib_malloc_pages(substream, size); 334 if (status < 0) 335 return status; 336 337 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 338 pg = virt_to_page(substream->dma_buffer.area); 339 if (pg) { 340 rtd->pg = pg; 341 rtd->num_pages = (PAGE_ALIGN(size) >> PAGE_SHIFT); 342 config_acp3x_dma(rtd, substream->stream); 343 status = 0; 344 } else { 345 status = -ENOMEM; 346 } 347 return status; 348 } 349 350 static snd_pcm_uframes_t acp3x_dma_pointer(struct snd_pcm_substream *substream) 351 { 352 u32 pos = 0; 353 struct i2s_stream_instance *rtd = substream->runtime->private_data; 354 355 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 356 pos = rv_readl(rtd->acp3x_base + 357 mmACP_BT_TX_LINKPOSITIONCNTR); 358 else 359 pos = rv_readl(rtd->acp3x_base + 360 mmACP_BT_RX_LINKPOSITIONCNTR); 361 362 if (pos >= MAX_BUFFER) 363 pos = 0; 364 365 return bytes_to_frames(substream->runtime, pos); 366 } 367 368 static int acp3x_dma_new(struct snd_soc_pcm_runtime *rtd) 369 { 370 return snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 371 SNDRV_DMA_TYPE_DEV, 372 rtd->pcm->card->dev, 373 MIN_BUFFER, 374 MAX_BUFFER); 375 } 376 377 static int acp3x_dma_hw_free(struct snd_pcm_substream *substream) 378 { 379 return snd_pcm_lib_free_pages(substream); 380 } 381 382 static int acp3x_dma_mmap(struct snd_pcm_substream *substream, 383 struct vm_area_struct *vma) 384 { 385 return snd_pcm_lib_default_mmap(substream, vma); 386 } 387 388 static int acp3x_dma_close(struct snd_pcm_substream *substream) 389 { 390 struct snd_soc_pcm_runtime *prtd = substream->private_data; 391 struct i2s_stream_instance *rtd = substream->runtime->private_data; 392 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 393 DRV_NAME); 394 struct i2s_dev_data *adata = dev_get_drvdata(component->dev); 395 396 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 397 adata->play_stream = NULL; 398 else 399 adata->capture_stream = NULL; 400 401 /* Disable ACP irq, when the current stream is being closed and 402 * another stream is also not active. 403 */ 404 if (!adata->play_stream && !adata->capture_stream) 405 rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB); 406 kfree(rtd); 407 return 0; 408 } 409 410 static struct snd_pcm_ops acp3x_dma_ops = { 411 .open = acp3x_dma_open, 412 .close = acp3x_dma_close, 413 .ioctl = snd_pcm_lib_ioctl, 414 .hw_params = acp3x_dma_hw_params, 415 .hw_free = acp3x_dma_hw_free, 416 .pointer = acp3x_dma_pointer, 417 .mmap = acp3x_dma_mmap, 418 }; 419 420 421 static int acp3x_dai_i2s_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 422 { 423 424 struct i2s_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai); 425 426 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 427 case SND_SOC_DAIFMT_I2S: 428 adata->tdm_mode = false; 429 break; 430 case SND_SOC_DAIFMT_DSP_A: 431 adata->tdm_mode = true; 432 break; 433 default: 434 return -EINVAL; 435 } 436 437 return 0; 438 } 439 440 static int acp3x_dai_set_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask, 441 u32 rx_mask, int slots, int slot_width) 442 { 443 u32 val = 0; 444 u16 slot_len; 445 446 struct i2s_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai); 447 448 switch (slot_width) { 449 case SLOT_WIDTH_8: 450 slot_len = 8; 451 break; 452 case SLOT_WIDTH_16: 453 slot_len = 16; 454 break; 455 case SLOT_WIDTH_24: 456 slot_len = 24; 457 break; 458 case SLOT_WIDTH_32: 459 slot_len = 0; 460 break; 461 default: 462 return -EINVAL; 463 } 464 465 val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER); 466 rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_ITER); 467 val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER); 468 rv_writel((val | 0x2), adata->acp3x_base + mmACP_BTTDM_IRER); 469 470 val = (FRM_LEN | (slots << 15) | (slot_len << 18)); 471 rv_writel(val, adata->acp3x_base + mmACP_BTTDM_TXFRMT); 472 rv_writel(val, adata->acp3x_base + mmACP_BTTDM_RXFRMT); 473 474 adata->tdm_fmt = val; 475 return 0; 476 } 477 478 static int acp3x_dai_i2s_hwparams(struct snd_pcm_substream *substream, 479 struct snd_pcm_hw_params *params, 480 struct snd_soc_dai *dai) 481 { 482 u32 val = 0; 483 struct i2s_stream_instance *rtd = substream->runtime->private_data; 484 485 switch (params_format(params)) { 486 case SNDRV_PCM_FORMAT_U8: 487 case SNDRV_PCM_FORMAT_S8: 488 rtd->xfer_resolution = 0x0; 489 break; 490 case SNDRV_PCM_FORMAT_S16_LE: 491 rtd->xfer_resolution = 0x02; 492 break; 493 case SNDRV_PCM_FORMAT_S24_LE: 494 rtd->xfer_resolution = 0x04; 495 break; 496 case SNDRV_PCM_FORMAT_S32_LE: 497 rtd->xfer_resolution = 0x05; 498 break; 499 default: 500 return -EINVAL; 501 } 502 val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER); 503 val = val | (rtd->xfer_resolution << 3); 504 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 505 rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER); 506 else 507 rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER); 508 509 return 0; 510 } 511 512 static int acp3x_dai_i2s_trigger(struct snd_pcm_substream *substream, 513 int cmd, struct snd_soc_dai *dai) 514 { 515 int ret = 0; 516 struct i2s_stream_instance *rtd = substream->runtime->private_data; 517 u32 val, period_bytes; 518 519 period_bytes = frames_to_bytes(substream->runtime, 520 substream->runtime->period_size); 521 switch (cmd) { 522 case SNDRV_PCM_TRIGGER_START: 523 case SNDRV_PCM_TRIGGER_RESUME: 524 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 525 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 526 rv_writel(period_bytes, rtd->acp3x_base + 527 mmACP_BT_TX_INTR_WATERMARK_SIZE); 528 val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER); 529 val = val | BIT(0); 530 rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER); 531 } else { 532 rv_writel(period_bytes, rtd->acp3x_base + 533 mmACP_BT_RX_INTR_WATERMARK_SIZE); 534 val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER); 535 val = val | BIT(0); 536 rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER); 537 } 538 rv_writel(1, rtd->acp3x_base + mmACP_BTTDM_IER); 539 break; 540 case SNDRV_PCM_TRIGGER_STOP: 541 case SNDRV_PCM_TRIGGER_SUSPEND: 542 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 543 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 544 val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_ITER); 545 val = val & ~BIT(0); 546 rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_ITER); 547 } else { 548 val = rv_readl(rtd->acp3x_base + mmACP_BTTDM_IRER); 549 val = val & ~BIT(0); 550 rv_writel(val, rtd->acp3x_base + mmACP_BTTDM_IRER); 551 } 552 rv_writel(0, rtd->acp3x_base + mmACP_BTTDM_IER); 553 break; 554 default: 555 ret = -EINVAL; 556 break; 557 } 558 559 return ret; 560 } 561 562 struct snd_soc_dai_ops acp3x_dai_i2s_ops = { 563 .hw_params = acp3x_dai_i2s_hwparams, 564 .trigger = acp3x_dai_i2s_trigger, 565 .set_fmt = acp3x_dai_i2s_set_fmt, 566 .set_tdm_slot = acp3x_dai_set_tdm_slot, 567 }; 568 569 static struct snd_soc_dai_driver acp3x_i2s_dai_driver = { 570 .playback = { 571 .rates = SNDRV_PCM_RATE_8000_96000, 572 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 573 SNDRV_PCM_FMTBIT_U8 | 574 SNDRV_PCM_FMTBIT_S24_LE | 575 SNDRV_PCM_FMTBIT_S32_LE, 576 .channels_min = 2, 577 .channels_max = 8, 578 579 .rate_min = 8000, 580 .rate_max = 96000, 581 }, 582 .capture = { 583 .rates = SNDRV_PCM_RATE_8000_48000, 584 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | 585 SNDRV_PCM_FMTBIT_U8 | 586 SNDRV_PCM_FMTBIT_S24_LE | 587 SNDRV_PCM_FMTBIT_S32_LE, 588 .channels_min = 2, 589 .channels_max = 2, 590 .rate_min = 8000, 591 .rate_max = 48000, 592 }, 593 .ops = &acp3x_dai_i2s_ops, 594 }; 595 596 static const struct snd_soc_component_driver acp3x_i2s_component = { 597 .name = DRV_NAME, 598 .ops = &acp3x_dma_ops, 599 .pcm_new = acp3x_dma_new, 600 }; 601 602 static int acp3x_audio_probe(struct platform_device *pdev) 603 { 604 int status; 605 struct resource *res; 606 struct i2s_dev_data *adata; 607 unsigned int irqflags; 608 609 if (!pdev->dev.platform_data) { 610 dev_err(&pdev->dev, "platform_data not retrieved\n"); 611 return -ENODEV; 612 } 613 irqflags = *((unsigned int *)(pdev->dev.platform_data)); 614 615 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 616 if (!res) { 617 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 618 return -ENODEV; 619 } 620 621 adata = devm_kzalloc(&pdev->dev, sizeof(*adata), GFP_KERNEL); 622 if (!adata) 623 return -ENOMEM; 624 625 adata->acp3x_base = devm_ioremap(&pdev->dev, res->start, 626 resource_size(res)); 627 628 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 629 if (!res) { 630 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 631 return -ENODEV; 632 } 633 634 adata->i2s_irq = res->start; 635 adata->play_stream = NULL; 636 adata->capture_stream = NULL; 637 638 dev_set_drvdata(&pdev->dev, adata); 639 /* Initialize ACP */ 640 status = acp3x_init(adata->acp3x_base); 641 if (status) 642 return -ENODEV; 643 status = devm_snd_soc_register_component(&pdev->dev, 644 &acp3x_i2s_component, 645 &acp3x_i2s_dai_driver, 1); 646 if (status) { 647 dev_err(&pdev->dev, "Fail to register acp i2s dai\n"); 648 goto dev_err; 649 } 650 status = devm_request_irq(&pdev->dev, adata->i2s_irq, i2s_irq_handler, 651 irqflags, "ACP3x_I2S_IRQ", adata); 652 if (status) { 653 dev_err(&pdev->dev, "ACP3x I2S IRQ request failed\n"); 654 goto dev_err; 655 } 656 657 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 658 pm_runtime_use_autosuspend(&pdev->dev); 659 pm_runtime_enable(&pdev->dev); 660 return 0; 661 dev_err: 662 status = acp3x_deinit(adata->acp3x_base); 663 if (status) 664 dev_err(&pdev->dev, "ACP de-init failed\n"); 665 else 666 dev_info(&pdev->dev, "ACP de-initialized\n"); 667 /*ignore device status and return driver probe error*/ 668 return -ENODEV; 669 } 670 671 static int acp3x_audio_remove(struct platform_device *pdev) 672 { 673 int ret; 674 struct i2s_dev_data *adata = dev_get_drvdata(&pdev->dev); 675 676 ret = acp3x_deinit(adata->acp3x_base); 677 if (ret) 678 dev_err(&pdev->dev, "ACP de-init failed\n"); 679 else 680 dev_info(&pdev->dev, "ACP de-initialized\n"); 681 682 pm_runtime_disable(&pdev->dev); 683 return 0; 684 } 685 686 static int acp3x_resume(struct device *dev) 687 { 688 int status; 689 u32 val; 690 struct i2s_dev_data *adata = dev_get_drvdata(dev); 691 692 status = acp3x_init(adata->acp3x_base); 693 if (status) 694 return -ENODEV; 695 696 if (adata->play_stream && adata->play_stream->runtime) { 697 struct i2s_stream_instance *rtd = 698 adata->play_stream->runtime->private_data; 699 config_acp3x_dma(rtd, SNDRV_PCM_STREAM_PLAYBACK); 700 rv_writel((rtd->xfer_resolution << 3), 701 rtd->acp3x_base + mmACP_BTTDM_ITER); 702 if (adata->tdm_mode == true) { 703 rv_writel(adata->tdm_fmt, adata->acp3x_base + 704 mmACP_BTTDM_TXFRMT); 705 val = rv_readl(adata->acp3x_base + mmACP_BTTDM_ITER); 706 rv_writel((val | 0x2), adata->acp3x_base + 707 mmACP_BTTDM_ITER); 708 } 709 } 710 711 if (adata->capture_stream && adata->capture_stream->runtime) { 712 struct i2s_stream_instance *rtd = 713 adata->capture_stream->runtime->private_data; 714 config_acp3x_dma(rtd, SNDRV_PCM_STREAM_CAPTURE); 715 rv_writel((rtd->xfer_resolution << 3), 716 rtd->acp3x_base + mmACP_BTTDM_IRER); 717 if (adata->tdm_mode == true) { 718 rv_writel(adata->tdm_fmt, adata->acp3x_base + 719 mmACP_BTTDM_RXFRMT); 720 val = rv_readl(adata->acp3x_base + mmACP_BTTDM_IRER); 721 rv_writel((val | 0x2), adata->acp3x_base + 722 mmACP_BTTDM_IRER); 723 } 724 } 725 726 rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB); 727 return 0; 728 } 729 730 731 static int acp3x_pcm_runtime_suspend(struct device *dev) 732 { 733 int status; 734 struct i2s_dev_data *adata = dev_get_drvdata(dev); 735 736 status = acp3x_deinit(adata->acp3x_base); 737 if (status) 738 dev_err(dev, "ACP de-init failed\n"); 739 else 740 dev_info(dev, "ACP de-initialized\n"); 741 742 rv_writel(0, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB); 743 744 return 0; 745 } 746 747 static int acp3x_pcm_runtime_resume(struct device *dev) 748 { 749 int status; 750 struct i2s_dev_data *adata = dev_get_drvdata(dev); 751 752 status = acp3x_init(adata->acp3x_base); 753 if (status) 754 return -ENODEV; 755 rv_writel(1, adata->acp3x_base + mmACP_EXTERNAL_INTR_ENB); 756 return 0; 757 } 758 759 static const struct dev_pm_ops acp3x_pm_ops = { 760 .runtime_suspend = acp3x_pcm_runtime_suspend, 761 .runtime_resume = acp3x_pcm_runtime_resume, 762 .resume = acp3x_resume, 763 }; 764 765 static struct platform_driver acp3x_dma_driver = { 766 .probe = acp3x_audio_probe, 767 .remove = acp3x_audio_remove, 768 .driver = { 769 .name = "acp3x_rv_i2s", 770 .pm = &acp3x_pm_ops, 771 }, 772 }; 773 774 module_platform_driver(acp3x_dma_driver); 775 776 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 777 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 778 MODULE_DESCRIPTION("AMD ACP 3.x PCM Driver"); 779 MODULE_LICENSE("GPL v2"); 780 MODULE_ALIAS("platform:" DRV_NAME); 781