1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ALSA SoC PDM Driver 4 * 5 * Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved. 6 */ 7 8 #include <sound/acp63_chip_offset_byte.h> 9 10 #define ACP_DEVICE_ID 0x15E2 11 #define ACP63_REG_START 0x1240000 12 #define ACP63_REG_END 0x1250200 13 #define ACP63_DEVS 3 14 #define ACP63_PDM_MODE 1 15 16 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 17 #define ACP_PGFSM_CNTL_POWER_ON_MASK 1 18 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0 19 #define ACP_PGFSM_STATUS_MASK 3 20 #define ACP_POWERED_ON 0 21 #define ACP_POWER_ON_IN_PROGRESS 1 22 #define ACP_POWERED_OFF 2 23 #define ACP_POWER_OFF_IN_PROGRESS 3 24 25 #define ACP_ERROR_MASK 0x20000000 26 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF 27 #define PDM_DMA_STAT 0x10 28 29 #define PDM_DMA_INTR_MASK 0x10000 30 #define ACP_ERROR_STAT 29 31 #define PDM_DECIMATION_FACTOR 2 32 #define ACP_PDM_CLK_FREQ_MASK 7 33 #define ACP_WOV_MISC_CTRL_MASK 0x10 34 #define ACP_PDM_ENABLE 1 35 #define ACP_PDM_DISABLE 0 36 #define ACP_PDM_DMA_EN_STATUS 2 37 #define TWO_CH 2 38 #define DELAY_US 5 39 #define ACP_COUNTER 20000 40 41 #define ACP_SRAM_PTE_OFFSET 0x03800000 42 #define PAGE_SIZE_4K_ENABLE 2 43 #define PDM_PTE_OFFSET 0 44 #define PDM_MEM_WINDOW_START 0x4000000 45 46 #define CAPTURE_MIN_NUM_PERIODS 4 47 #define CAPTURE_MAX_NUM_PERIODS 4 48 #define CAPTURE_MAX_PERIOD_SIZE 8192 49 #define CAPTURE_MIN_PERIOD_SIZE 4096 50 51 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) 52 #define MIN_BUFFER MAX_BUFFER 53 54 /* time in ms for runtime suspend delay */ 55 #define ACP_SUSPEND_DELAY_MS 2000 56 57 enum acp_config { 58 ACP_CONFIG_0 = 0, 59 ACP_CONFIG_1, 60 ACP_CONFIG_2, 61 ACP_CONFIG_3, 62 ACP_CONFIG_4, 63 ACP_CONFIG_5, 64 ACP_CONFIG_6, 65 ACP_CONFIG_7, 66 ACP_CONFIG_8, 67 ACP_CONFIG_9, 68 ACP_CONFIG_10, 69 ACP_CONFIG_11, 70 ACP_CONFIG_12, 71 ACP_CONFIG_13, 72 ACP_CONFIG_14, 73 ACP_CONFIG_15, 74 }; 75 76 struct pdm_stream_instance { 77 u16 num_pages; 78 u16 channels; 79 dma_addr_t dma_addr; 80 u64 bytescount; 81 void __iomem *acp63_base; 82 }; 83 84 struct pdm_dev_data { 85 u32 pdm_irq; 86 void __iomem *acp63_base; 87 struct snd_pcm_substream *capture_stream; 88 }; 89 90 static inline u32 acp63_readl(void __iomem *base_addr) 91 { 92 return readl(base_addr); 93 } 94 95 static inline void acp63_writel(u32 val, void __iomem *base_addr) 96 { 97 writel(val, base_addr); 98 } 99 100 struct acp63_dev_data { 101 void __iomem *acp63_base; 102 struct resource *res; 103 bool acp63_audio_mode; 104 struct platform_device *pdev[ACP63_DEVS]; 105 }; 106