1 /*
2  * ACP_2_2 Register documentation
3  *
4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef ACP_2_2_SH_MASK_H
25 #define ACP_2_2_SH_MASK_H
26 
27 #define ACP_DMA_CNTL_0__DMAChRst_MASK 0x1
28 #define ACP_DMA_CNTL_0__DMAChRst__SHIFT 0x0
29 #define ACP_DMA_CNTL_0__DMAChRun_MASK 0x2
30 #define ACP_DMA_CNTL_0__DMAChRun__SHIFT 0x1
31 #define ACP_DMA_CNTL_0__DMAChIOCEn_MASK 0x4
32 #define ACP_DMA_CNTL_0__DMAChIOCEn__SHIFT 0x2
33 #define ACP_DMA_CNTL_0__Circular_DMA_En_MASK 0x8
34 #define ACP_DMA_CNTL_0__Circular_DMA_En__SHIFT 0x3
35 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn_MASK 0x10
36 #define ACP_DMA_CNTL_0__DMAChGracefulRstEn__SHIFT 0x4
37 #define ACP_DMA_CNTL_1__DMAChRst_MASK 0x1
38 #define ACP_DMA_CNTL_1__DMAChRst__SHIFT 0x0
39 #define ACP_DMA_CNTL_1__DMAChRun_MASK 0x2
40 #define ACP_DMA_CNTL_1__DMAChRun__SHIFT 0x1
41 #define ACP_DMA_CNTL_1__DMAChIOCEn_MASK 0x4
42 #define ACP_DMA_CNTL_1__DMAChIOCEn__SHIFT 0x2
43 #define ACP_DMA_CNTL_1__Circular_DMA_En_MASK 0x8
44 #define ACP_DMA_CNTL_1__Circular_DMA_En__SHIFT 0x3
45 #define ACP_DMA_CNTL_1__DMAChGracefulRstEn_MASK 0x10
46 #define ACP_DMA_CNTL_1__DMAChGracefulRstEn__SHIFT 0x4
47 #define ACP_DMA_CNTL_2__DMAChRst_MASK 0x1
48 #define ACP_DMA_CNTL_2__DMAChRst__SHIFT 0x0
49 #define ACP_DMA_CNTL_2__DMAChRun_MASK 0x2
50 #define ACP_DMA_CNTL_2__DMAChRun__SHIFT 0x1
51 #define ACP_DMA_CNTL_2__DMAChIOCEn_MASK 0x4
52 #define ACP_DMA_CNTL_2__DMAChIOCEn__SHIFT 0x2
53 #define ACP_DMA_CNTL_2__Circular_DMA_En_MASK 0x8
54 #define ACP_DMA_CNTL_2__Circular_DMA_En__SHIFT 0x3
55 #define ACP_DMA_CNTL_2__DMAChGracefulRstEn_MASK 0x10
56 #define ACP_DMA_CNTL_2__DMAChGracefulRstEn__SHIFT 0x4
57 #define ACP_DMA_CNTL_3__DMAChRst_MASK 0x1
58 #define ACP_DMA_CNTL_3__DMAChRst__SHIFT 0x0
59 #define ACP_DMA_CNTL_3__DMAChRun_MASK 0x2
60 #define ACP_DMA_CNTL_3__DMAChRun__SHIFT 0x1
61 #define ACP_DMA_CNTL_3__DMAChIOCEn_MASK 0x4
62 #define ACP_DMA_CNTL_3__DMAChIOCEn__SHIFT 0x2
63 #define ACP_DMA_CNTL_3__Circular_DMA_En_MASK 0x8
64 #define ACP_DMA_CNTL_3__Circular_DMA_En__SHIFT 0x3
65 #define ACP_DMA_CNTL_3__DMAChGracefulRstEn_MASK 0x10
66 #define ACP_DMA_CNTL_3__DMAChGracefulRstEn__SHIFT 0x4
67 #define ACP_DMA_CNTL_4__DMAChRst_MASK 0x1
68 #define ACP_DMA_CNTL_4__DMAChRst__SHIFT 0x0
69 #define ACP_DMA_CNTL_4__DMAChRun_MASK 0x2
70 #define ACP_DMA_CNTL_4__DMAChRun__SHIFT 0x1
71 #define ACP_DMA_CNTL_4__DMAChIOCEn_MASK 0x4
72 #define ACP_DMA_CNTL_4__DMAChIOCEn__SHIFT 0x2
73 #define ACP_DMA_CNTL_4__Circular_DMA_En_MASK 0x8
74 #define ACP_DMA_CNTL_4__Circular_DMA_En__SHIFT 0x3
75 #define ACP_DMA_CNTL_4__DMAChGracefulRstEn_MASK 0x10
76 #define ACP_DMA_CNTL_4__DMAChGracefulRstEn__SHIFT 0x4
77 #define ACP_DMA_CNTL_5__DMAChRst_MASK 0x1
78 #define ACP_DMA_CNTL_5__DMAChRst__SHIFT 0x0
79 #define ACP_DMA_CNTL_5__DMAChRun_MASK 0x2
80 #define ACP_DMA_CNTL_5__DMAChRun__SHIFT 0x1
81 #define ACP_DMA_CNTL_5__DMAChIOCEn_MASK 0x4
82 #define ACP_DMA_CNTL_5__DMAChIOCEn__SHIFT 0x2
83 #define ACP_DMA_CNTL_5__Circular_DMA_En_MASK 0x8
84 #define ACP_DMA_CNTL_5__Circular_DMA_En__SHIFT 0x3
85 #define ACP_DMA_CNTL_5__DMAChGracefulRstEn_MASK 0x10
86 #define ACP_DMA_CNTL_5__DMAChGracefulRstEn__SHIFT 0x4
87 #define ACP_DMA_CNTL_6__DMAChRst_MASK 0x1
88 #define ACP_DMA_CNTL_6__DMAChRst__SHIFT 0x0
89 #define ACP_DMA_CNTL_6__DMAChRun_MASK 0x2
90 #define ACP_DMA_CNTL_6__DMAChRun__SHIFT 0x1
91 #define ACP_DMA_CNTL_6__DMAChIOCEn_MASK 0x4
92 #define ACP_DMA_CNTL_6__DMAChIOCEn__SHIFT 0x2
93 #define ACP_DMA_CNTL_6__Circular_DMA_En_MASK 0x8
94 #define ACP_DMA_CNTL_6__Circular_DMA_En__SHIFT 0x3
95 #define ACP_DMA_CNTL_6__DMAChGracefulRstEn_MASK 0x10
96 #define ACP_DMA_CNTL_6__DMAChGracefulRstEn__SHIFT 0x4
97 #define ACP_DMA_CNTL_7__DMAChRst_MASK 0x1
98 #define ACP_DMA_CNTL_7__DMAChRst__SHIFT 0x0
99 #define ACP_DMA_CNTL_7__DMAChRun_MASK 0x2
100 #define ACP_DMA_CNTL_7__DMAChRun__SHIFT 0x1
101 #define ACP_DMA_CNTL_7__DMAChIOCEn_MASK 0x4
102 #define ACP_DMA_CNTL_7__DMAChIOCEn__SHIFT 0x2
103 #define ACP_DMA_CNTL_7__Circular_DMA_En_MASK 0x8
104 #define ACP_DMA_CNTL_7__Circular_DMA_En__SHIFT 0x3
105 #define ACP_DMA_CNTL_7__DMAChGracefulRstEn_MASK 0x10
106 #define ACP_DMA_CNTL_7__DMAChGracefulRstEn__SHIFT 0x4
107 #define ACP_DMA_CNTL_8__DMAChRst_MASK 0x1
108 #define ACP_DMA_CNTL_8__DMAChRst__SHIFT 0x0
109 #define ACP_DMA_CNTL_8__DMAChRun_MASK 0x2
110 #define ACP_DMA_CNTL_8__DMAChRun__SHIFT 0x1
111 #define ACP_DMA_CNTL_8__DMAChIOCEn_MASK 0x4
112 #define ACP_DMA_CNTL_8__DMAChIOCEn__SHIFT 0x2
113 #define ACP_DMA_CNTL_8__Circular_DMA_En_MASK 0x8
114 #define ACP_DMA_CNTL_8__Circular_DMA_En__SHIFT 0x3
115 #define ACP_DMA_CNTL_8__DMAChGracefulRstEn_MASK 0x10
116 #define ACP_DMA_CNTL_8__DMAChGracefulRstEn__SHIFT 0x4
117 #define ACP_DMA_CNTL_9__DMAChRst_MASK 0x1
118 #define ACP_DMA_CNTL_9__DMAChRst__SHIFT 0x0
119 #define ACP_DMA_CNTL_9__DMAChRun_MASK 0x2
120 #define ACP_DMA_CNTL_9__DMAChRun__SHIFT 0x1
121 #define ACP_DMA_CNTL_9__DMAChIOCEn_MASK 0x4
122 #define ACP_DMA_CNTL_9__DMAChIOCEn__SHIFT 0x2
123 #define ACP_DMA_CNTL_9__Circular_DMA_En_MASK 0x8
124 #define ACP_DMA_CNTL_9__Circular_DMA_En__SHIFT 0x3
125 #define ACP_DMA_CNTL_9__DMAChGracefulRstEn_MASK 0x10
126 #define ACP_DMA_CNTL_9__DMAChGracefulRstEn__SHIFT 0x4
127 #define ACP_DMA_CNTL_10__DMAChRst_MASK 0x1
128 #define ACP_DMA_CNTL_10__DMAChRst__SHIFT 0x0
129 #define ACP_DMA_CNTL_10__DMAChRun_MASK 0x2
130 #define ACP_DMA_CNTL_10__DMAChRun__SHIFT 0x1
131 #define ACP_DMA_CNTL_10__DMAChIOCEn_MASK 0x4
132 #define ACP_DMA_CNTL_10__DMAChIOCEn__SHIFT 0x2
133 #define ACP_DMA_CNTL_10__Circular_DMA_En_MASK 0x8
134 #define ACP_DMA_CNTL_10__Circular_DMA_En__SHIFT 0x3
135 #define ACP_DMA_CNTL_10__DMAChGracefulRstEn_MASK 0x10
136 #define ACP_DMA_CNTL_10__DMAChGracefulRstEn__SHIFT 0x4
137 #define ACP_DMA_CNTL_11__DMAChRst_MASK 0x1
138 #define ACP_DMA_CNTL_11__DMAChRst__SHIFT 0x0
139 #define ACP_DMA_CNTL_11__DMAChRun_MASK 0x2
140 #define ACP_DMA_CNTL_11__DMAChRun__SHIFT 0x1
141 #define ACP_DMA_CNTL_11__DMAChIOCEn_MASK 0x4
142 #define ACP_DMA_CNTL_11__DMAChIOCEn__SHIFT 0x2
143 #define ACP_DMA_CNTL_11__Circular_DMA_En_MASK 0x8
144 #define ACP_DMA_CNTL_11__Circular_DMA_En__SHIFT 0x3
145 #define ACP_DMA_CNTL_11__DMAChGracefulRstEn_MASK 0x10
146 #define ACP_DMA_CNTL_11__DMAChGracefulRstEn__SHIFT 0x4
147 #define ACP_DMA_CNTL_12__DMAChRst_MASK 0x1
148 #define ACP_DMA_CNTL_12__DMAChRst__SHIFT 0x0
149 #define ACP_DMA_CNTL_12__DMAChRun_MASK 0x2
150 #define ACP_DMA_CNTL_12__DMAChRun__SHIFT 0x1
151 #define ACP_DMA_CNTL_12__DMAChIOCEn_MASK 0x4
152 #define ACP_DMA_CNTL_12__DMAChIOCEn__SHIFT 0x2
153 #define ACP_DMA_CNTL_12__Circular_DMA_En_MASK 0x8
154 #define ACP_DMA_CNTL_12__Circular_DMA_En__SHIFT 0x3
155 #define ACP_DMA_CNTL_12__DMAChGracefulRstEn_MASK 0x10
156 #define ACP_DMA_CNTL_12__DMAChGracefulRstEn__SHIFT 0x4
157 #define ACP_DMA_CNTL_13__DMAChRst_MASK 0x1
158 #define ACP_DMA_CNTL_13__DMAChRst__SHIFT 0x0
159 #define ACP_DMA_CNTL_13__DMAChRun_MASK 0x2
160 #define ACP_DMA_CNTL_13__DMAChRun__SHIFT 0x1
161 #define ACP_DMA_CNTL_13__DMAChIOCEn_MASK 0x4
162 #define ACP_DMA_CNTL_13__DMAChIOCEn__SHIFT 0x2
163 #define ACP_DMA_CNTL_13__Circular_DMA_En_MASK 0x8
164 #define ACP_DMA_CNTL_13__Circular_DMA_En__SHIFT 0x3
165 #define ACP_DMA_CNTL_13__DMAChGracefulRstEn_MASK 0x10
166 #define ACP_DMA_CNTL_13__DMAChGracefulRstEn__SHIFT 0x4
167 #define ACP_DMA_CNTL_14__DMAChRst_MASK 0x1
168 #define ACP_DMA_CNTL_14__DMAChRst__SHIFT 0x0
169 #define ACP_DMA_CNTL_14__DMAChRun_MASK 0x2
170 #define ACP_DMA_CNTL_14__DMAChRun__SHIFT 0x1
171 #define ACP_DMA_CNTL_14__DMAChIOCEn_MASK 0x4
172 #define ACP_DMA_CNTL_14__DMAChIOCEn__SHIFT 0x2
173 #define ACP_DMA_CNTL_14__Circular_DMA_En_MASK 0x8
174 #define ACP_DMA_CNTL_14__Circular_DMA_En__SHIFT 0x3
175 #define ACP_DMA_CNTL_14__DMAChGracefulRstEn_MASK 0x10
176 #define ACP_DMA_CNTL_14__DMAChGracefulRstEn__SHIFT 0x4
177 #define ACP_DMA_CNTL_15__DMAChRst_MASK 0x1
178 #define ACP_DMA_CNTL_15__DMAChRst__SHIFT 0x0
179 #define ACP_DMA_CNTL_15__DMAChRun_MASK 0x2
180 #define ACP_DMA_CNTL_15__DMAChRun__SHIFT 0x1
181 #define ACP_DMA_CNTL_15__DMAChIOCEn_MASK 0x4
182 #define ACP_DMA_CNTL_15__DMAChIOCEn__SHIFT 0x2
183 #define ACP_DMA_CNTL_15__Circular_DMA_En_MASK 0x8
184 #define ACP_DMA_CNTL_15__Circular_DMA_En__SHIFT 0x3
185 #define ACP_DMA_CNTL_15__DMAChGracefulRstEn_MASK 0x10
186 #define ACP_DMA_CNTL_15__DMAChGracefulRstEn__SHIFT 0x4
187 #define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 0x3ff
188 #define ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx__SHIFT 0x0
189 #define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx_MASK 0x3ff
190 #define ACP_DMA_DSCR_STRT_IDX_1__DMAChDscrStrtIdx__SHIFT 0x0
191 #define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx_MASK 0x3ff
192 #define ACP_DMA_DSCR_STRT_IDX_2__DMAChDscrStrtIdx__SHIFT 0x0
193 #define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx_MASK 0x3ff
194 #define ACP_DMA_DSCR_STRT_IDX_3__DMAChDscrStrtIdx__SHIFT 0x0
195 #define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx_MASK 0x3ff
196 #define ACP_DMA_DSCR_STRT_IDX_4__DMAChDscrStrtIdx__SHIFT 0x0
197 #define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx_MASK 0x3ff
198 #define ACP_DMA_DSCR_STRT_IDX_5__DMAChDscrStrtIdx__SHIFT 0x0
199 #define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx_MASK 0x3ff
200 #define ACP_DMA_DSCR_STRT_IDX_6__DMAChDscrStrtIdx__SHIFT 0x0
201 #define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx_MASK 0x3ff
202 #define ACP_DMA_DSCR_STRT_IDX_7__DMAChDscrStrtIdx__SHIFT 0x0
203 #define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx_MASK 0x3ff
204 #define ACP_DMA_DSCR_STRT_IDX_8__DMAChDscrStrtIdx__SHIFT 0x0
205 #define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx_MASK 0x3ff
206 #define ACP_DMA_DSCR_STRT_IDX_9__DMAChDscrStrtIdx__SHIFT 0x0
207 #define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx_MASK 0x3ff
208 #define ACP_DMA_DSCR_STRT_IDX_10__DMAChDscrStrtIdx__SHIFT 0x0
209 #define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx_MASK 0x3ff
210 #define ACP_DMA_DSCR_STRT_IDX_11__DMAChDscrStrtIdx__SHIFT 0x0
211 #define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx_MASK 0x3ff
212 #define ACP_DMA_DSCR_STRT_IDX_12__DMAChDscrStrtIdx__SHIFT 0x0
213 #define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx_MASK 0x3ff
214 #define ACP_DMA_DSCR_STRT_IDX_13__DMAChDscrStrtIdx__SHIFT 0x0
215 #define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx_MASK 0x3ff
216 #define ACP_DMA_DSCR_STRT_IDX_14__DMAChDscrStrtIdx__SHIFT 0x0
217 #define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx_MASK 0x3ff
218 #define ACP_DMA_DSCR_STRT_IDX_15__DMAChDscrStrtIdx__SHIFT 0x0
219 #define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK 0x3ff
220 #define ACP_DMA_DSCR_CNT_0__DMAChDscrCnt__SHIFT 0x0
221 #define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt_MASK 0x3ff
222 #define ACP_DMA_DSCR_CNT_1__DMAChDscrCnt__SHIFT 0x0
223 #define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt_MASK 0x3ff
224 #define ACP_DMA_DSCR_CNT_2__DMAChDscrCnt__SHIFT 0x0
225 #define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt_MASK 0x3ff
226 #define ACP_DMA_DSCR_CNT_3__DMAChDscrCnt__SHIFT 0x0
227 #define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt_MASK 0x3ff
228 #define ACP_DMA_DSCR_CNT_4__DMAChDscrCnt__SHIFT 0x0
229 #define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt_MASK 0x3ff
230 #define ACP_DMA_DSCR_CNT_5__DMAChDscrCnt__SHIFT 0x0
231 #define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt_MASK 0x3ff
232 #define ACP_DMA_DSCR_CNT_6__DMAChDscrCnt__SHIFT 0x0
233 #define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt_MASK 0x3ff
234 #define ACP_DMA_DSCR_CNT_7__DMAChDscrCnt__SHIFT 0x0
235 #define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt_MASK 0x3ff
236 #define ACP_DMA_DSCR_CNT_8__DMAChDscrCnt__SHIFT 0x0
237 #define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt_MASK 0x3ff
238 #define ACP_DMA_DSCR_CNT_9__DMAChDscrCnt__SHIFT 0x0
239 #define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt_MASK 0x3ff
240 #define ACP_DMA_DSCR_CNT_10__DMAChDscrCnt__SHIFT 0x0
241 #define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt_MASK 0x3ff
242 #define ACP_DMA_DSCR_CNT_11__DMAChDscrCnt__SHIFT 0x0
243 #define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt_MASK 0x3ff
244 #define ACP_DMA_DSCR_CNT_12__DMAChDscrCnt__SHIFT 0x0
245 #define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt_MASK 0x3ff
246 #define ACP_DMA_DSCR_CNT_13__DMAChDscrCnt__SHIFT 0x0
247 #define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt_MASK 0x3ff
248 #define ACP_DMA_DSCR_CNT_14__DMAChDscrCnt__SHIFT 0x0
249 #define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt_MASK 0x3ff
250 #define ACP_DMA_DSCR_CNT_15__DMAChDscrCnt__SHIFT 0x0
251 #define ACP_DMA_PRIO_0__DMAChPrioLvl_MASK 0x1
252 #define ACP_DMA_PRIO_0__DMAChPrioLvl__SHIFT 0x0
253 #define ACP_DMA_PRIO_1__DMAChPrioLvl_MASK 0x1
254 #define ACP_DMA_PRIO_1__DMAChPrioLvl__SHIFT 0x0
255 #define ACP_DMA_PRIO_2__DMAChPrioLvl_MASK 0x1
256 #define ACP_DMA_PRIO_2__DMAChPrioLvl__SHIFT 0x0
257 #define ACP_DMA_PRIO_3__DMAChPrioLvl_MASK 0x1
258 #define ACP_DMA_PRIO_3__DMAChPrioLvl__SHIFT 0x0
259 #define ACP_DMA_PRIO_4__DMAChPrioLvl_MASK 0x1
260 #define ACP_DMA_PRIO_4__DMAChPrioLvl__SHIFT 0x0
261 #define ACP_DMA_PRIO_5__DMAChPrioLvl_MASK 0x1
262 #define ACP_DMA_PRIO_5__DMAChPrioLvl__SHIFT 0x0
263 #define ACP_DMA_PRIO_6__DMAChPrioLvl_MASK 0x1
264 #define ACP_DMA_PRIO_6__DMAChPrioLvl__SHIFT 0x0
265 #define ACP_DMA_PRIO_7__DMAChPrioLvl_MASK 0x1
266 #define ACP_DMA_PRIO_7__DMAChPrioLvl__SHIFT 0x0
267 #define ACP_DMA_PRIO_8__DMAChPrioLvl_MASK 0x1
268 #define ACP_DMA_PRIO_8__DMAChPrioLvl__SHIFT 0x0
269 #define ACP_DMA_PRIO_9__DMAChPrioLvl_MASK 0x1
270 #define ACP_DMA_PRIO_9__DMAChPrioLvl__SHIFT 0x0
271 #define ACP_DMA_PRIO_10__DMAChPrioLvl_MASK 0x1
272 #define ACP_DMA_PRIO_10__DMAChPrioLvl__SHIFT 0x0
273 #define ACP_DMA_PRIO_11__DMAChPrioLvl_MASK 0x1
274 #define ACP_DMA_PRIO_11__DMAChPrioLvl__SHIFT 0x0
275 #define ACP_DMA_PRIO_12__DMAChPrioLvl_MASK 0x1
276 #define ACP_DMA_PRIO_12__DMAChPrioLvl__SHIFT 0x0
277 #define ACP_DMA_PRIO_13__DMAChPrioLvl_MASK 0x1
278 #define ACP_DMA_PRIO_13__DMAChPrioLvl__SHIFT 0x0
279 #define ACP_DMA_PRIO_14__DMAChPrioLvl_MASK 0x1
280 #define ACP_DMA_PRIO_14__DMAChPrioLvl__SHIFT 0x0
281 #define ACP_DMA_PRIO_15__DMAChPrioLvl_MASK 0x1
282 #define ACP_DMA_PRIO_15__DMAChPrioLvl__SHIFT 0x0
283 #define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx_MASK 0x3ff
284 #define ACP_DMA_CUR_DSCR_0__DMAChCurDscrIdx__SHIFT 0x0
285 #define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx_MASK 0x3ff
286 #define ACP_DMA_CUR_DSCR_1__DMAChCurDscrIdx__SHIFT 0x0
287 #define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx_MASK 0x3ff
288 #define ACP_DMA_CUR_DSCR_2__DMAChCurDscrIdx__SHIFT 0x0
289 #define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx_MASK 0x3ff
290 #define ACP_DMA_CUR_DSCR_3__DMAChCurDscrIdx__SHIFT 0x0
291 #define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx_MASK 0x3ff
292 #define ACP_DMA_CUR_DSCR_4__DMAChCurDscrIdx__SHIFT 0x0
293 #define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx_MASK 0x3ff
294 #define ACP_DMA_CUR_DSCR_5__DMAChCurDscrIdx__SHIFT 0x0
295 #define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx_MASK 0x3ff
296 #define ACP_DMA_CUR_DSCR_6__DMAChCurDscrIdx__SHIFT 0x0
297 #define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx_MASK 0x3ff
298 #define ACP_DMA_CUR_DSCR_7__DMAChCurDscrIdx__SHIFT 0x0
299 #define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx_MASK 0x3ff
300 #define ACP_DMA_CUR_DSCR_8__DMAChCurDscrIdx__SHIFT 0x0
301 #define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx_MASK 0x3ff
302 #define ACP_DMA_CUR_DSCR_9__DMAChCurDscrIdx__SHIFT 0x0
303 #define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx_MASK 0x3ff
304 #define ACP_DMA_CUR_DSCR_10__DMAChCurDscrIdx__SHIFT 0x0
305 #define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx_MASK 0x3ff
306 #define ACP_DMA_CUR_DSCR_11__DMAChCurDscrIdx__SHIFT 0x0
307 #define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx_MASK 0x3ff
308 #define ACP_DMA_CUR_DSCR_12__DMAChCurDscrIdx__SHIFT 0x0
309 #define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx_MASK 0x3ff
310 #define ACP_DMA_CUR_DSCR_13__DMAChCurDscrIdx__SHIFT 0x0
311 #define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx_MASK 0x3ff
312 #define ACP_DMA_CUR_DSCR_14__DMAChCurDscrIdx__SHIFT 0x0
313 #define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx_MASK 0x3ff
314 #define ACP_DMA_CUR_DSCR_15__DMAChCurDscrIdx__SHIFT 0x0
315 #define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt_MASK 0x1ffff
316 #define ACP_DMA_CUR_TRANS_CNT_0__DMAChCurTransCnt__SHIFT 0x0
317 #define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt_MASK 0x1ffff
318 #define ACP_DMA_CUR_TRANS_CNT_1__DMAChCurTransCnt__SHIFT 0x0
319 #define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt_MASK 0x1ffff
320 #define ACP_DMA_CUR_TRANS_CNT_2__DMAChCurTransCnt__SHIFT 0x0
321 #define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt_MASK 0x1ffff
322 #define ACP_DMA_CUR_TRANS_CNT_3__DMAChCurTransCnt__SHIFT 0x0
323 #define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt_MASK 0x1ffff
324 #define ACP_DMA_CUR_TRANS_CNT_4__DMAChCurTransCnt__SHIFT 0x0
325 #define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt_MASK 0x1ffff
326 #define ACP_DMA_CUR_TRANS_CNT_5__DMAChCurTransCnt__SHIFT 0x0
327 #define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt_MASK 0x1ffff
328 #define ACP_DMA_CUR_TRANS_CNT_6__DMAChCurTransCnt__SHIFT 0x0
329 #define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt_MASK 0x1ffff
330 #define ACP_DMA_CUR_TRANS_CNT_7__DMAChCurTransCnt__SHIFT 0x0
331 #define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt_MASK 0x1ffff
332 #define ACP_DMA_CUR_TRANS_CNT_8__DMAChCurTransCnt__SHIFT 0x0
333 #define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt_MASK 0x1ffff
334 #define ACP_DMA_CUR_TRANS_CNT_9__DMAChCurTransCnt__SHIFT 0x0
335 #define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt_MASK 0x1ffff
336 #define ACP_DMA_CUR_TRANS_CNT_10__DMAChCurTransCnt__SHIFT 0x0
337 #define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt_MASK 0x1ffff
338 #define ACP_DMA_CUR_TRANS_CNT_11__DMAChCurTransCnt__SHIFT 0x0
339 #define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt_MASK 0x1ffff
340 #define ACP_DMA_CUR_TRANS_CNT_12__DMAChCurTransCnt__SHIFT 0x0
341 #define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt_MASK 0x1ffff
342 #define ACP_DMA_CUR_TRANS_CNT_13__DMAChCurTransCnt__SHIFT 0x0
343 #define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt_MASK 0x1ffff
344 #define ACP_DMA_CUR_TRANS_CNT_14__DMAChCurTransCnt__SHIFT 0x0
345 #define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt_MASK 0x1ffff
346 #define ACP_DMA_CUR_TRANS_CNT_15__DMAChCurTransCnt__SHIFT 0x0
347 #define ACP_DMA_ERR_STS_0__DMAChTermErr_MASK 0x1
348 #define ACP_DMA_ERR_STS_0__DMAChTermErr__SHIFT 0x0
349 #define ACP_DMA_ERR_STS_0__DMAChErrCode_MASK 0x1e
350 #define ACP_DMA_ERR_STS_0__DMAChErrCode__SHIFT 0x1
351 #define ACP_DMA_ERR_STS_1__DMAChTermErr_MASK 0x1
352 #define ACP_DMA_ERR_STS_1__DMAChTermErr__SHIFT 0x0
353 #define ACP_DMA_ERR_STS_1__DMAChErrCode_MASK 0x1e
354 #define ACP_DMA_ERR_STS_1__DMAChErrCode__SHIFT 0x1
355 #define ACP_DMA_ERR_STS_2__DMAChTermErr_MASK 0x1
356 #define ACP_DMA_ERR_STS_2__DMAChTermErr__SHIFT 0x0
357 #define ACP_DMA_ERR_STS_2__DMAChErrCode_MASK 0x1e
358 #define ACP_DMA_ERR_STS_2__DMAChErrCode__SHIFT 0x1
359 #define ACP_DMA_ERR_STS_3__DMAChTermErr_MASK 0x1
360 #define ACP_DMA_ERR_STS_3__DMAChTermErr__SHIFT 0x0
361 #define ACP_DMA_ERR_STS_3__DMAChErrCode_MASK 0x1e
362 #define ACP_DMA_ERR_STS_3__DMAChErrCode__SHIFT 0x1
363 #define ACP_DMA_ERR_STS_4__DMAChTermErr_MASK 0x1
364 #define ACP_DMA_ERR_STS_4__DMAChTermErr__SHIFT 0x0
365 #define ACP_DMA_ERR_STS_4__DMAChErrCode_MASK 0x1e
366 #define ACP_DMA_ERR_STS_4__DMAChErrCode__SHIFT 0x1
367 #define ACP_DMA_ERR_STS_5__DMAChTermErr_MASK 0x1
368 #define ACP_DMA_ERR_STS_5__DMAChTermErr__SHIFT 0x0
369 #define ACP_DMA_ERR_STS_5__DMAChErrCode_MASK 0x1e
370 #define ACP_DMA_ERR_STS_5__DMAChErrCode__SHIFT 0x1
371 #define ACP_DMA_ERR_STS_6__DMAChTermErr_MASK 0x1
372 #define ACP_DMA_ERR_STS_6__DMAChTermErr__SHIFT 0x0
373 #define ACP_DMA_ERR_STS_6__DMAChErrCode_MASK 0x1e
374 #define ACP_DMA_ERR_STS_6__DMAChErrCode__SHIFT 0x1
375 #define ACP_DMA_ERR_STS_7__DMAChTermErr_MASK 0x1
376 #define ACP_DMA_ERR_STS_7__DMAChTermErr__SHIFT 0x0
377 #define ACP_DMA_ERR_STS_7__DMAChErrCode_MASK 0x1e
378 #define ACP_DMA_ERR_STS_7__DMAChErrCode__SHIFT 0x1
379 #define ACP_DMA_ERR_STS_8__DMAChTermErr_MASK 0x1
380 #define ACP_DMA_ERR_STS_8__DMAChTermErr__SHIFT 0x0
381 #define ACP_DMA_ERR_STS_8__DMAChErrCode_MASK 0x1e
382 #define ACP_DMA_ERR_STS_8__DMAChErrCode__SHIFT 0x1
383 #define ACP_DMA_ERR_STS_9__DMAChTermErr_MASK 0x1
384 #define ACP_DMA_ERR_STS_9__DMAChTermErr__SHIFT 0x0
385 #define ACP_DMA_ERR_STS_9__DMAChErrCode_MASK 0x1e
386 #define ACP_DMA_ERR_STS_9__DMAChErrCode__SHIFT 0x1
387 #define ACP_DMA_ERR_STS_10__DMAChTermErr_MASK 0x1
388 #define ACP_DMA_ERR_STS_10__DMAChTermErr__SHIFT 0x0
389 #define ACP_DMA_ERR_STS_10__DMAChErrCode_MASK 0x1e
390 #define ACP_DMA_ERR_STS_10__DMAChErrCode__SHIFT 0x1
391 #define ACP_DMA_ERR_STS_11__DMAChTermErr_MASK 0x1
392 #define ACP_DMA_ERR_STS_11__DMAChTermErr__SHIFT 0x0
393 #define ACP_DMA_ERR_STS_11__DMAChErrCode_MASK 0x1e
394 #define ACP_DMA_ERR_STS_11__DMAChErrCode__SHIFT 0x1
395 #define ACP_DMA_ERR_STS_12__DMAChTermErr_MASK 0x1
396 #define ACP_DMA_ERR_STS_12__DMAChTermErr__SHIFT 0x0
397 #define ACP_DMA_ERR_STS_12__DMAChErrCode_MASK 0x1e
398 #define ACP_DMA_ERR_STS_12__DMAChErrCode__SHIFT 0x1
399 #define ACP_DMA_ERR_STS_13__DMAChTermErr_MASK 0x1
400 #define ACP_DMA_ERR_STS_13__DMAChTermErr__SHIFT 0x0
401 #define ACP_DMA_ERR_STS_13__DMAChErrCode_MASK 0x1e
402 #define ACP_DMA_ERR_STS_13__DMAChErrCode__SHIFT 0x1
403 #define ACP_DMA_ERR_STS_14__DMAChTermErr_MASK 0x1
404 #define ACP_DMA_ERR_STS_14__DMAChTermErr__SHIFT 0x0
405 #define ACP_DMA_ERR_STS_14__DMAChErrCode_MASK 0x1e
406 #define ACP_DMA_ERR_STS_14__DMAChErrCode__SHIFT 0x1
407 #define ACP_DMA_ERR_STS_15__DMAChTermErr_MASK 0x1
408 #define ACP_DMA_ERR_STS_15__DMAChTermErr__SHIFT 0x0
409 #define ACP_DMA_ERR_STS_15__DMAChErrCode_MASK 0x1e
410 #define ACP_DMA_ERR_STS_15__DMAChErrCode__SHIFT 0x1
411 #define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr_MASK 0xffffffff
412 #define ACP_DMA_DESC_BASE_ADDR__DescriptorBaseAddr__SHIFT 0x0
413 #define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr_MASK 0xf
414 #define ACP_DMA_DESC_MAX_NUM_DSCR__MaximumNumberDescr__SHIFT 0x0
415 #define ACP_DMA_CH_STS__DMAChSts_MASK 0xffff
416 #define ACP_DMA_CH_STS__DMAChSts__SHIFT 0x0
417 #define ACP_DMA_CH_GROUP__DMAChanelGrouping_MASK 0x1
418 #define ACP_DMA_CH_GROUP__DMAChanelGrouping__SHIFT 0x0
419 #define ACP_DSP0_CACHE_OFFSET0__Offset_MASK 0xfffffff
420 #define ACP_DSP0_CACHE_OFFSET0__Offset__SHIFT 0x0
421 #define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
422 #define ACP_DSP0_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
423 #define ACP_DSP0_CACHE_SIZE0__Size_MASK 0xffffff
424 #define ACP_DSP0_CACHE_SIZE0__Size__SHIFT 0x0
425 #define ACP_DSP0_CACHE_SIZE0__PageEnable_MASK 0x80000000
426 #define ACP_DSP0_CACHE_SIZE0__PageEnable__SHIFT 0x1f
427 #define ACP_DSP0_CACHE_OFFSET1__Offset_MASK 0xfffffff
428 #define ACP_DSP0_CACHE_OFFSET1__Offset__SHIFT 0x0
429 #define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
430 #define ACP_DSP0_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
431 #define ACP_DSP0_CACHE_SIZE1__Size_MASK 0xffffff
432 #define ACP_DSP0_CACHE_SIZE1__Size__SHIFT 0x0
433 #define ACP_DSP0_CACHE_SIZE1__PageEnable_MASK 0x80000000
434 #define ACP_DSP0_CACHE_SIZE1__PageEnable__SHIFT 0x1f
435 #define ACP_DSP0_CACHE_OFFSET2__Offset_MASK 0xfffffff
436 #define ACP_DSP0_CACHE_OFFSET2__Offset__SHIFT 0x0
437 #define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000
438 #define ACP_DSP0_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f
439 #define ACP_DSP0_CACHE_SIZE2__Size_MASK 0xffffff
440 #define ACP_DSP0_CACHE_SIZE2__Size__SHIFT 0x0
441 #define ACP_DSP0_CACHE_SIZE2__PageEnable_MASK 0x80000000
442 #define ACP_DSP0_CACHE_SIZE2__PageEnable__SHIFT 0x1f
443 #define ACP_DSP0_CACHE_OFFSET3__Offset_MASK 0xfffffff
444 #define ACP_DSP0_CACHE_OFFSET3__Offset__SHIFT 0x0
445 #define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000
446 #define ACP_DSP0_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f
447 #define ACP_DSP0_CACHE_SIZE3__Size_MASK 0xffffff
448 #define ACP_DSP0_CACHE_SIZE3__Size__SHIFT 0x0
449 #define ACP_DSP0_CACHE_SIZE3__PageEnable_MASK 0x80000000
450 #define ACP_DSP0_CACHE_SIZE3__PageEnable__SHIFT 0x1f
451 #define ACP_DSP0_CACHE_OFFSET4__Offset_MASK 0xfffffff
452 #define ACP_DSP0_CACHE_OFFSET4__Offset__SHIFT 0x0
453 #define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000
454 #define ACP_DSP0_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f
455 #define ACP_DSP0_CACHE_SIZE4__Size_MASK 0xffffff
456 #define ACP_DSP0_CACHE_SIZE4__Size__SHIFT 0x0
457 #define ACP_DSP0_CACHE_SIZE4__PageEnable_MASK 0x80000000
458 #define ACP_DSP0_CACHE_SIZE4__PageEnable__SHIFT 0x1f
459 #define ACP_DSP0_CACHE_OFFSET5__Offset_MASK 0xfffffff
460 #define ACP_DSP0_CACHE_OFFSET5__Offset__SHIFT 0x0
461 #define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000
462 #define ACP_DSP0_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f
463 #define ACP_DSP0_CACHE_SIZE5__Size_MASK 0xffffff
464 #define ACP_DSP0_CACHE_SIZE5__Size__SHIFT 0x0
465 #define ACP_DSP0_CACHE_SIZE5__PageEnable_MASK 0x80000000
466 #define ACP_DSP0_CACHE_SIZE5__PageEnable__SHIFT 0x1f
467 #define ACP_DSP0_CACHE_OFFSET6__Offset_MASK 0xfffffff
468 #define ACP_DSP0_CACHE_OFFSET6__Offset__SHIFT 0x0
469 #define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000
470 #define ACP_DSP0_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f
471 #define ACP_DSP0_CACHE_SIZE6__Size_MASK 0xffffff
472 #define ACP_DSP0_CACHE_SIZE6__Size__SHIFT 0x0
473 #define ACP_DSP0_CACHE_SIZE6__PageEnable_MASK 0x80000000
474 #define ACP_DSP0_CACHE_SIZE6__PageEnable__SHIFT 0x1f
475 #define ACP_DSP0_CACHE_OFFSET7__Offset_MASK 0xfffffff
476 #define ACP_DSP0_CACHE_OFFSET7__Offset__SHIFT 0x0
477 #define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000
478 #define ACP_DSP0_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f
479 #define ACP_DSP0_CACHE_SIZE7__Size_MASK 0xffffff
480 #define ACP_DSP0_CACHE_SIZE7__Size__SHIFT 0x0
481 #define ACP_DSP0_CACHE_SIZE7__PageEnable_MASK 0x80000000
482 #define ACP_DSP0_CACHE_SIZE7__PageEnable__SHIFT 0x1f
483 #define ACP_DSP0_CACHE_OFFSET8__Offset_MASK 0xfffffff
484 #define ACP_DSP0_CACHE_OFFSET8__Offset__SHIFT 0x0
485 #define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000
486 #define ACP_DSP0_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f
487 #define ACP_DSP0_CACHE_SIZE8__Size_MASK 0xffffff
488 #define ACP_DSP0_CACHE_SIZE8__Size__SHIFT 0x0
489 #define ACP_DSP0_CACHE_SIZE8__PageEnable_MASK 0x80000000
490 #define ACP_DSP0_CACHE_SIZE8__PageEnable__SHIFT 0x1f
491 #define ACP_DSP0_NONCACHE_OFFSET0__Offset_MASK 0xfffffff
492 #define ACP_DSP0_NONCACHE_OFFSET0__Offset__SHIFT 0x0
493 #define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
494 #define ACP_DSP0_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
495 #define ACP_DSP0_NONCACHE_SIZE0__Size_MASK 0xffffff
496 #define ACP_DSP0_NONCACHE_SIZE0__Size__SHIFT 0x0
497 #define ACP_DSP0_NONCACHE_SIZE0__PageEnable_MASK 0x80000000
498 #define ACP_DSP0_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f
499 #define ACP_DSP0_NONCACHE_OFFSET1__Offset_MASK 0xfffffff
500 #define ACP_DSP0_NONCACHE_OFFSET1__Offset__SHIFT 0x0
501 #define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
502 #define ACP_DSP0_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
503 #define ACP_DSP0_NONCACHE_SIZE1__Size_MASK 0xffffff
504 #define ACP_DSP0_NONCACHE_SIZE1__Size__SHIFT 0x0
505 #define ACP_DSP0_NONCACHE_SIZE1__PageEnable_MASK 0x80000000
506 #define ACP_DSP0_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f
507 #define ACP_DSP0_DEBUG_PC__DebugPC_MASK 0xffffffff
508 #define ACP_DSP0_DEBUG_PC__DebugPC__SHIFT 0x0
509 #define ACP_DSP0_NMI_SEL__NMISel_MASK 0x1
510 #define ACP_DSP0_NMI_SEL__NMISel__SHIFT 0x0
511 #define ACP_DSP0_CLKRST_CNTL__ClkEn_MASK 0x1
512 #define ACP_DSP0_CLKRST_CNTL__ClkEn__SHIFT 0x0
513 #define ACP_DSP0_CLKRST_CNTL__SoftResetDSP_MASK 0x2
514 #define ACP_DSP0_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1
515 #define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4
516 #define ACP_DSP0_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2
517 #define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8
518 #define ACP_DSP0_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3
519 #define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10
520 #define ACP_DSP0_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4
521 #define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status_MASK 0x20
522 #define ACP_DSP0_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5
523 #define ACP_DSP0_RUNSTALL__RunStallCntl_MASK 0x1
524 #define ACP_DSP0_RUNSTALL__RunStallCntl__SHIFT 0x0
525 #define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1
526 #define ACP_DSP0_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0
527 #define ACP_DSP0_WAIT_MODE__WaitMode_MASK 0x1
528 #define ACP_DSP0_WAIT_MODE__WaitMode__SHIFT 0x0
529 #define ACP_DSP0_VECT_SEL__StaticVectorSel_MASK 0x1
530 #define ACP_DSP0_VECT_SEL__StaticVectorSel__SHIFT 0x0
531 #define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff
532 #define ACP_DSP0_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0
533 #define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff
534 #define ACP_DSP0_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0
535 #define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff
536 #define ACP_DSP0_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0
537 #define ACP_DSP1_CACHE_OFFSET0__Offset_MASK 0xfffffff
538 #define ACP_DSP1_CACHE_OFFSET0__Offset__SHIFT 0x0
539 #define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
540 #define ACP_DSP1_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
541 #define ACP_DSP1_CACHE_SIZE0__Size_MASK 0xffffff
542 #define ACP_DSP1_CACHE_SIZE0__Size__SHIFT 0x0
543 #define ACP_DSP1_CACHE_SIZE0__PageEnable_MASK 0x80000000
544 #define ACP_DSP1_CACHE_SIZE0__PageEnable__SHIFT 0x1f
545 #define ACP_DSP1_CACHE_OFFSET1__Offset_MASK 0xfffffff
546 #define ACP_DSP1_CACHE_OFFSET1__Offset__SHIFT 0x0
547 #define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
548 #define ACP_DSP1_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
549 #define ACP_DSP1_CACHE_SIZE1__Size_MASK 0xffffff
550 #define ACP_DSP1_CACHE_SIZE1__Size__SHIFT 0x0
551 #define ACP_DSP1_CACHE_SIZE1__PageEnable_MASK 0x80000000
552 #define ACP_DSP1_CACHE_SIZE1__PageEnable__SHIFT 0x1f
553 #define ACP_DSP1_CACHE_OFFSET2__Offset_MASK 0xfffffff
554 #define ACP_DSP1_CACHE_OFFSET2__Offset__SHIFT 0x0
555 #define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000
556 #define ACP_DSP1_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f
557 #define ACP_DSP1_CACHE_SIZE2__Size_MASK 0xffffff
558 #define ACP_DSP1_CACHE_SIZE2__Size__SHIFT 0x0
559 #define ACP_DSP1_CACHE_SIZE2__PageEnable_MASK 0x80000000
560 #define ACP_DSP1_CACHE_SIZE2__PageEnable__SHIFT 0x1f
561 #define ACP_DSP1_CACHE_OFFSET3__Offset_MASK 0xfffffff
562 #define ACP_DSP1_CACHE_OFFSET3__Offset__SHIFT 0x0
563 #define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000
564 #define ACP_DSP1_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f
565 #define ACP_DSP1_CACHE_SIZE3__Size_MASK 0xffffff
566 #define ACP_DSP1_CACHE_SIZE3__Size__SHIFT 0x0
567 #define ACP_DSP1_CACHE_SIZE3__PageEnable_MASK 0x80000000
568 #define ACP_DSP1_CACHE_SIZE3__PageEnable__SHIFT 0x1f
569 #define ACP_DSP1_CACHE_OFFSET4__Offset_MASK 0xfffffff
570 #define ACP_DSP1_CACHE_OFFSET4__Offset__SHIFT 0x0
571 #define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000
572 #define ACP_DSP1_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f
573 #define ACP_DSP1_CACHE_SIZE4__Size_MASK 0xffffff
574 #define ACP_DSP1_CACHE_SIZE4__Size__SHIFT 0x0
575 #define ACP_DSP1_CACHE_SIZE4__PageEnable_MASK 0x80000000
576 #define ACP_DSP1_CACHE_SIZE4__PageEnable__SHIFT 0x1f
577 #define ACP_DSP1_CACHE_OFFSET5__Offset_MASK 0xfffffff
578 #define ACP_DSP1_CACHE_OFFSET5__Offset__SHIFT 0x0
579 #define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000
580 #define ACP_DSP1_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f
581 #define ACP_DSP1_CACHE_SIZE5__Size_MASK 0xffffff
582 #define ACP_DSP1_CACHE_SIZE5__Size__SHIFT 0x0
583 #define ACP_DSP1_CACHE_SIZE5__PageEnable_MASK 0x80000000
584 #define ACP_DSP1_CACHE_SIZE5__PageEnable__SHIFT 0x1f
585 #define ACP_DSP1_CACHE_OFFSET6__Offset_MASK 0xfffffff
586 #define ACP_DSP1_CACHE_OFFSET6__Offset__SHIFT 0x0
587 #define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000
588 #define ACP_DSP1_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f
589 #define ACP_DSP1_CACHE_SIZE6__Size_MASK 0xffffff
590 #define ACP_DSP1_CACHE_SIZE6__Size__SHIFT 0x0
591 #define ACP_DSP1_CACHE_SIZE6__PageEnable_MASK 0x80000000
592 #define ACP_DSP1_CACHE_SIZE6__PageEnable__SHIFT 0x1f
593 #define ACP_DSP1_CACHE_OFFSET7__Offset_MASK 0xfffffff
594 #define ACP_DSP1_CACHE_OFFSET7__Offset__SHIFT 0x0
595 #define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000
596 #define ACP_DSP1_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f
597 #define ACP_DSP1_CACHE_SIZE7__Size_MASK 0xffffff
598 #define ACP_DSP1_CACHE_SIZE7__Size__SHIFT 0x0
599 #define ACP_DSP1_CACHE_SIZE7__PageEnable_MASK 0x80000000
600 #define ACP_DSP1_CACHE_SIZE7__PageEnable__SHIFT 0x1f
601 #define ACP_DSP1_CACHE_OFFSET8__Offset_MASK 0xfffffff
602 #define ACP_DSP1_CACHE_OFFSET8__Offset__SHIFT 0x0
603 #define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000
604 #define ACP_DSP1_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f
605 #define ACP_DSP1_CACHE_SIZE8__Size_MASK 0xffffff
606 #define ACP_DSP1_CACHE_SIZE8__Size__SHIFT 0x0
607 #define ACP_DSP1_CACHE_SIZE8__PageEnable_MASK 0x80000000
608 #define ACP_DSP1_CACHE_SIZE8__PageEnable__SHIFT 0x1f
609 #define ACP_DSP1_NONCACHE_OFFSET0__Offset_MASK 0xfffffff
610 #define ACP_DSP1_NONCACHE_OFFSET0__Offset__SHIFT 0x0
611 #define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
612 #define ACP_DSP1_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
613 #define ACP_DSP1_NONCACHE_SIZE0__Size_MASK 0xffffff
614 #define ACP_DSP1_NONCACHE_SIZE0__Size__SHIFT 0x0
615 #define ACP_DSP1_NONCACHE_SIZE0__PageEnable_MASK 0x80000000
616 #define ACP_DSP1_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f
617 #define ACP_DSP1_NONCACHE_OFFSET1__Offset_MASK 0xfffffff
618 #define ACP_DSP1_NONCACHE_OFFSET1__Offset__SHIFT 0x0
619 #define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
620 #define ACP_DSP1_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
621 #define ACP_DSP1_NONCACHE_SIZE1__Size_MASK 0xffffff
622 #define ACP_DSP1_NONCACHE_SIZE1__Size__SHIFT 0x0
623 #define ACP_DSP1_NONCACHE_SIZE1__PageEnable_MASK 0x80000000
624 #define ACP_DSP1_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f
625 #define ACP_DSP1_DEBUG_PC__DebugPC_MASK 0xffffffff
626 #define ACP_DSP1_DEBUG_PC__DebugPC__SHIFT 0x0
627 #define ACP_DSP1_NMI_SEL__NMISel_MASK 0x1
628 #define ACP_DSP1_NMI_SEL__NMISel__SHIFT 0x0
629 #define ACP_DSP1_CLKRST_CNTL__ClkEn_MASK 0x1
630 #define ACP_DSP1_CLKRST_CNTL__ClkEn__SHIFT 0x0
631 #define ACP_DSP1_CLKRST_CNTL__SoftResetDSP_MASK 0x2
632 #define ACP_DSP1_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1
633 #define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4
634 #define ACP_DSP1_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2
635 #define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8
636 #define ACP_DSP1_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3
637 #define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10
638 #define ACP_DSP1_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4
639 #define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status_MASK 0x20
640 #define ACP_DSP1_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5
641 #define ACP_DSP1_RUNSTALL__RunStallCntl_MASK 0x1
642 #define ACP_DSP1_RUNSTALL__RunStallCntl__SHIFT 0x0
643 #define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1
644 #define ACP_DSP1_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0
645 #define ACP_DSP1_WAIT_MODE__WaitMode_MASK 0x1
646 #define ACP_DSP1_WAIT_MODE__WaitMode__SHIFT 0x0
647 #define ACP_DSP1_VECT_SEL__StaticVectorSel_MASK 0x1
648 #define ACP_DSP1_VECT_SEL__StaticVectorSel__SHIFT 0x0
649 #define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff
650 #define ACP_DSP1_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0
651 #define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff
652 #define ACP_DSP1_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0
653 #define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff
654 #define ACP_DSP1_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0
655 #define ACP_DSP2_CACHE_OFFSET0__Offset_MASK 0xfffffff
656 #define ACP_DSP2_CACHE_OFFSET0__Offset__SHIFT 0x0
657 #define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
658 #define ACP_DSP2_CACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
659 #define ACP_DSP2_CACHE_SIZE0__Size_MASK 0xffffff
660 #define ACP_DSP2_CACHE_SIZE0__Size__SHIFT 0x0
661 #define ACP_DSP2_CACHE_SIZE0__PageEnable_MASK 0x80000000
662 #define ACP_DSP2_CACHE_SIZE0__PageEnable__SHIFT 0x1f
663 #define ACP_DSP2_CACHE_OFFSET1__Offset_MASK 0xfffffff
664 #define ACP_DSP2_CACHE_OFFSET1__Offset__SHIFT 0x0
665 #define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
666 #define ACP_DSP2_CACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
667 #define ACP_DSP2_CACHE_SIZE1__Size_MASK 0xffffff
668 #define ACP_DSP2_CACHE_SIZE1__Size__SHIFT 0x0
669 #define ACP_DSP2_CACHE_SIZE1__PageEnable_MASK 0x80000000
670 #define ACP_DSP2_CACHE_SIZE1__PageEnable__SHIFT 0x1f
671 #define ACP_DSP2_CACHE_OFFSET2__Offset_MASK 0xfffffff
672 #define ACP_DSP2_CACHE_OFFSET2__Offset__SHIFT 0x0
673 #define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel_MASK 0x80000000
674 #define ACP_DSP2_CACHE_OFFSET2__OnionGarlicSel__SHIFT 0x1f
675 #define ACP_DSP2_CACHE_SIZE2__Size_MASK 0xffffff
676 #define ACP_DSP2_CACHE_SIZE2__Size__SHIFT 0x0
677 #define ACP_DSP2_CACHE_SIZE2__PageEnable_MASK 0x80000000
678 #define ACP_DSP2_CACHE_SIZE2__PageEnable__SHIFT 0x1f
679 #define ACP_DSP2_CACHE_OFFSET3__Offset_MASK 0xfffffff
680 #define ACP_DSP2_CACHE_OFFSET3__Offset__SHIFT 0x0
681 #define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel_MASK 0x80000000
682 #define ACP_DSP2_CACHE_OFFSET3__OnionGarlicSel__SHIFT 0x1f
683 #define ACP_DSP2_CACHE_SIZE3__Size_MASK 0xffffff
684 #define ACP_DSP2_CACHE_SIZE3__Size__SHIFT 0x0
685 #define ACP_DSP2_CACHE_SIZE3__PageEnable_MASK 0x80000000
686 #define ACP_DSP2_CACHE_SIZE3__PageEnable__SHIFT 0x1f
687 #define ACP_DSP2_CACHE_OFFSET4__Offset_MASK 0xfffffff
688 #define ACP_DSP2_CACHE_OFFSET4__Offset__SHIFT 0x0
689 #define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel_MASK 0x80000000
690 #define ACP_DSP2_CACHE_OFFSET4__OnionGarlicSel__SHIFT 0x1f
691 #define ACP_DSP2_CACHE_SIZE4__Size_MASK 0xffffff
692 #define ACP_DSP2_CACHE_SIZE4__Size__SHIFT 0x0
693 #define ACP_DSP2_CACHE_SIZE4__PageEnable_MASK 0x80000000
694 #define ACP_DSP2_CACHE_SIZE4__PageEnable__SHIFT 0x1f
695 #define ACP_DSP2_CACHE_OFFSET5__Offset_MASK 0xfffffff
696 #define ACP_DSP2_CACHE_OFFSET5__Offset__SHIFT 0x0
697 #define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel_MASK 0x80000000
698 #define ACP_DSP2_CACHE_OFFSET5__OnionGarlicSel__SHIFT 0x1f
699 #define ACP_DSP2_CACHE_SIZE5__Size_MASK 0xffffff
700 #define ACP_DSP2_CACHE_SIZE5__Size__SHIFT 0x0
701 #define ACP_DSP2_CACHE_SIZE5__PageEnable_MASK 0x80000000
702 #define ACP_DSP2_CACHE_SIZE5__PageEnable__SHIFT 0x1f
703 #define ACP_DSP2_CACHE_OFFSET6__Offset_MASK 0xfffffff
704 #define ACP_DSP2_CACHE_OFFSET6__Offset__SHIFT 0x0
705 #define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel_MASK 0x80000000
706 #define ACP_DSP2_CACHE_OFFSET6__OnionGarlicSel__SHIFT 0x1f
707 #define ACP_DSP2_CACHE_SIZE6__Size_MASK 0xffffff
708 #define ACP_DSP2_CACHE_SIZE6__Size__SHIFT 0x0
709 #define ACP_DSP2_CACHE_SIZE6__PageEnable_MASK 0x80000000
710 #define ACP_DSP2_CACHE_SIZE6__PageEnable__SHIFT 0x1f
711 #define ACP_DSP2_CACHE_OFFSET7__Offset_MASK 0xfffffff
712 #define ACP_DSP2_CACHE_OFFSET7__Offset__SHIFT 0x0
713 #define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel_MASK 0x80000000
714 #define ACP_DSP2_CACHE_OFFSET7__OnionGarlicSel__SHIFT 0x1f
715 #define ACP_DSP2_CACHE_SIZE7__Size_MASK 0xffffff
716 #define ACP_DSP2_CACHE_SIZE7__Size__SHIFT 0x0
717 #define ACP_DSP2_CACHE_SIZE7__PageEnable_MASK 0x80000000
718 #define ACP_DSP2_CACHE_SIZE7__PageEnable__SHIFT 0x1f
719 #define ACP_DSP2_CACHE_OFFSET8__Offset_MASK 0xfffffff
720 #define ACP_DSP2_CACHE_OFFSET8__Offset__SHIFT 0x0
721 #define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel_MASK 0x80000000
722 #define ACP_DSP2_CACHE_OFFSET8__OnionGarlicSel__SHIFT 0x1f
723 #define ACP_DSP2_CACHE_SIZE8__Size_MASK 0xffffff
724 #define ACP_DSP2_CACHE_SIZE8__Size__SHIFT 0x0
725 #define ACP_DSP2_CACHE_SIZE8__PageEnable_MASK 0x80000000
726 #define ACP_DSP2_CACHE_SIZE8__PageEnable__SHIFT 0x1f
727 #define ACP_DSP2_NONCACHE_OFFSET0__Offset_MASK 0xfffffff
728 #define ACP_DSP2_NONCACHE_OFFSET0__Offset__SHIFT 0x0
729 #define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel_MASK 0x80000000
730 #define ACP_DSP2_NONCACHE_OFFSET0__OnionGarlicSel__SHIFT 0x1f
731 #define ACP_DSP2_NONCACHE_SIZE0__Size_MASK 0xffffff
732 #define ACP_DSP2_NONCACHE_SIZE0__Size__SHIFT 0x0
733 #define ACP_DSP2_NONCACHE_SIZE0__PageEnable_MASK 0x80000000
734 #define ACP_DSP2_NONCACHE_SIZE0__PageEnable__SHIFT 0x1f
735 #define ACP_DSP2_NONCACHE_OFFSET1__Offset_MASK 0xfffffff
736 #define ACP_DSP2_NONCACHE_OFFSET1__Offset__SHIFT 0x0
737 #define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel_MASK 0x80000000
738 #define ACP_DSP2_NONCACHE_OFFSET1__OnionGarlicSel__SHIFT 0x1f
739 #define ACP_DSP2_NONCACHE_SIZE1__Size_MASK 0xffffff
740 #define ACP_DSP2_NONCACHE_SIZE1__Size__SHIFT 0x0
741 #define ACP_DSP2_NONCACHE_SIZE1__PageEnable_MASK 0x80000000
742 #define ACP_DSP2_NONCACHE_SIZE1__PageEnable__SHIFT 0x1f
743 #define ACP_DSP2_DEBUG_PC__DebugPC_MASK 0xffffffff
744 #define ACP_DSP2_DEBUG_PC__DebugPC__SHIFT 0x0
745 #define ACP_DSP2_NMI_SEL__NMISel_MASK 0x1
746 #define ACP_DSP2_NMI_SEL__NMISel__SHIFT 0x0
747 #define ACP_DSP2_CLKRST_CNTL__ClkEn_MASK 0x1
748 #define ACP_DSP2_CLKRST_CNTL__ClkEn__SHIFT 0x0
749 #define ACP_DSP2_CLKRST_CNTL__SoftResetDSP_MASK 0x2
750 #define ACP_DSP2_CLKRST_CNTL__SoftResetDSP__SHIFT 0x1
751 #define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode_MASK 0x4
752 #define ACP_DSP2_CLKRST_CNTL__InternalSoftResetMode__SHIFT 0x2
753 #define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode_MASK 0x8
754 #define ACP_DSP2_CLKRST_CNTL__ExternalSoftResetMode__SHIFT 0x3
755 #define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone_MASK 0x10
756 #define ACP_DSP2_CLKRST_CNTL__SoftResetDSPDone__SHIFT 0x4
757 #define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status_MASK 0x20
758 #define ACP_DSP2_CLKRST_CNTL__Clk_ON_Status__SHIFT 0x5
759 #define ACP_DSP2_RUNSTALL__RunStallCntl_MASK 0x1
760 #define ACP_DSP2_RUNSTALL__RunStallCntl__SHIFT 0x0
761 #define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST_MASK 0x1
762 #define ACP_DSP2_OCD_HALT_ON_RST__OCD_HALT_ON_RST__SHIFT 0x0
763 #define ACP_DSP2_WAIT_MODE__WaitMode_MASK 0x1
764 #define ACP_DSP2_WAIT_MODE__WaitMode__SHIFT 0x0
765 #define ACP_DSP2_VECT_SEL__StaticVectorSel_MASK 0x1
766 #define ACP_DSP2_VECT_SEL__StaticVectorSel__SHIFT 0x0
767 #define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1_MASK 0xffffffff
768 #define ACP_DSP2_DEBUG_REG1__ACP_DSP_DEBUG_REG1__SHIFT 0x0
769 #define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2_MASK 0xffffffff
770 #define ACP_DSP2_DEBUG_REG2__ACP_DSP_DEBUG_REG2__SHIFT 0x0
771 #define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3_MASK 0xffffffff
772 #define ACP_DSP2_DEBUG_REG3__ACP_DSP_DEBUG_REG3__SHIFT 0x0
773 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap_MASK 0x3
774 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBDataSwap__SHIFT 0x0
775 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4
776 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2
777 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18
778 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3
779 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60
780 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5
781 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb_MASK 0x80
782 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallEnb__SHIFT 0x7
783 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb_MASK 0x100
784 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8
785 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200
786 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9
787 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb_MASK 0x400
788 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa
789 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800
790 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb
791 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode_MASK 0x2000
792 #define ACP_AXI2DAGB_ONION_CNTL__AXI2DAGBStallMode__SHIFT 0xd
793 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000
794 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19
795 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
796 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
797 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000
798 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d
799 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000
800 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e
801 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000
802 #define ACP_AXI2DAGB_ONION_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f
803 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000
804 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19
805 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
806 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
807 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000
808 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d
809 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000
810 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e
811 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000
812 #define ACP_AXI2DAGB_ONION_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f
813 #define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1
814 #define ACP_DAGB_Onion_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0
815 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
816 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
817 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
818 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
819 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
820 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
821 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
822 #define ACP_DAGB_Onion_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
823 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
824 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
825 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
826 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
827 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
828 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
829 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
830 #define ACP_DAGB_Onion_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
831 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap_MASK 0x3
832 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBDataSwap__SHIFT 0x0
833 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq_MASK 0x4
834 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultRdReq__SHIFT 0x2
835 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq_MASK 0x18
836 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBEnbMultWrReq__SHIFT 0x3
837 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst_MASK 0x60
838 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBMaxReadBurst__SHIFT 0x5
839 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb_MASK 0x80
840 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallEnb__SHIFT 0x7
841 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb_MASK 0x100
842 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBNackChkEnb__SHIFT 0x8
843 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb_MASK 0x200
844 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBAdrWinViolChkEnb__SHIFT 0x9
845 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb_MASK 0x400
846 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgEnb__SHIFT 0xa
847 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult_MASK 0x1800
848 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBUrgCntMult__SHIFT 0xb
849 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode_MASK 0x2000
850 #define ACP_AXI2DAGB_GARLIC_CNTL__AXI2DAGBStallMode__SHIFT 0xd
851 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver_MASK 0x2000000
852 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolOver__SHIFT 0x19
853 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
854 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
855 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol_MASK 0x20000000
856 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBAdrWinViol__SHIFT 0x1d
857 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver_MASK 0x40000000
858 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackOver__SHIFT 0x1e
859 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal_MASK 0x80000000
860 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_WR__AXI2DAGBNackVal__SHIFT 0x1f
861 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver_MASK 0x2000000
862 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolOver__SHIFT 0x19
863 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource_MASK 0x1c000000
864 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViolSource__SHIFT 0x1a
865 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol_MASK 0x20000000
866 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBAdrWinViol__SHIFT 0x1d
867 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver_MASK 0x40000000
868 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackOver__SHIFT 0x1e
869 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal_MASK 0x80000000
870 #define ACP_AXI2DAGB_GARLIC_ERR_STATUS_RD__AXI2DAGBNackVal__SHIFT 0x1f
871 #define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr_MASK 0x1
872 #define ACP_DAGB_Garlic_TransPerf_Counter_Control__EnbDAGBTransPerfCntr__SHIFT 0x0
873 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
874 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
875 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
876 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
877 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
878 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
879 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
880 #define ACP_DAGB_Garlic_Wr_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
881 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime_MASK 0x1ffff
882 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__CurDAGBTransPerfCntrTime__SHIFT 0x0
883 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr_MASK 0x80000000
884 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Current__ClrCurDAGBTransPerfCntr__SHIFT 0x1f
885 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime_MASK 0x1ffff
886 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__PeakDAGBTransPerfCntrTime__SHIFT 0x0
887 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr_MASK 0x80000000
888 #define ACP_DAGB_Garlic_Rd_TransPerf_Counter_Peak__ClrPeakDAGBTransPerfCntr__SHIFT 0x1f
889 #define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize_MASK 0x3
890 #define ACP_DAGB_PAGE_SIZE_GRP_1__AXI2DAGBPageSize__SHIFT 0x0
891 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr_MASK 0xfffffff
892 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBBaseAddr__SHIFT 0x0
893 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK 0x20000000
894 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel__SHIFT 0x1d
895 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK 0x40000000
896 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel__SHIFT 0x1e
897 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK 0x80000000
898 #define ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable__SHIFT 0x1f
899 #define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize_MASK 0x3
900 #define ACP_DAGB_PAGE_SIZE_GRP_2__AXI2DAGBPageSize__SHIFT 0x0
901 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr_MASK 0xfffffff
902 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBBaseAddr__SHIFT 0x0
903 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel_MASK 0x20000000
904 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBSnoopSel__SHIFT 0x1d
905 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel_MASK 0x40000000
906 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBTargetMemSel__SHIFT 0x1e
907 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable_MASK 0x80000000
908 #define ACP_DAGB_BASE_ADDR_GRP_2__AXI2DAGBGrpEnable__SHIFT 0x1f
909 #define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize_MASK 0x3
910 #define ACP_DAGB_PAGE_SIZE_GRP_3__AXI2DAGBPageSize__SHIFT 0x0
911 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr_MASK 0xfffffff
912 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBBaseAddr__SHIFT 0x0
913 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel_MASK 0x20000000
914 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBSnoopSel__SHIFT 0x1d
915 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel_MASK 0x40000000
916 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBTargetMemSel__SHIFT 0x1e
917 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable_MASK 0x80000000
918 #define ACP_DAGB_BASE_ADDR_GRP_3__AXI2DAGBGrpEnable__SHIFT 0x1f
919 #define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize_MASK 0x3
920 #define ACP_DAGB_PAGE_SIZE_GRP_4__AXI2DAGBPageSize__SHIFT 0x0
921 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr_MASK 0xfffffff
922 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBBaseAddr__SHIFT 0x0
923 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel_MASK 0x20000000
924 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBSnoopSel__SHIFT 0x1d
925 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel_MASK 0x40000000
926 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBTargetMemSel__SHIFT 0x1e
927 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable_MASK 0x80000000
928 #define ACP_DAGB_BASE_ADDR_GRP_4__AXI2DAGBGrpEnable__SHIFT 0x1f
929 #define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize_MASK 0x3
930 #define ACP_DAGB_PAGE_SIZE_GRP_5__AXI2DAGBPageSize__SHIFT 0x0
931 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr_MASK 0xfffffff
932 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBBaseAddr__SHIFT 0x0
933 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel_MASK 0x20000000
934 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBSnoopSel__SHIFT 0x1d
935 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel_MASK 0x40000000
936 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBTargetMemSel__SHIFT 0x1e
937 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable_MASK 0x80000000
938 #define ACP_DAGB_BASE_ADDR_GRP_5__AXI2DAGBGrpEnable__SHIFT 0x1f
939 #define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize_MASK 0x3
940 #define ACP_DAGB_PAGE_SIZE_GRP_6__AXI2DAGBPageSize__SHIFT 0x0
941 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr_MASK 0xfffffff
942 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBBaseAddr__SHIFT 0x0
943 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel_MASK 0x20000000
944 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBSnoopSel__SHIFT 0x1d
945 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel_MASK 0x40000000
946 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBTargetMemSel__SHIFT 0x1e
947 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable_MASK 0x80000000
948 #define ACP_DAGB_BASE_ADDR_GRP_6__AXI2DAGBGrpEnable__SHIFT 0x1f
949 #define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize_MASK 0x3
950 #define ACP_DAGB_PAGE_SIZE_GRP_7__AXI2DAGBPageSize__SHIFT 0x0
951 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr_MASK 0xfffffff
952 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBBaseAddr__SHIFT 0x0
953 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel_MASK 0x20000000
954 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBSnoopSel__SHIFT 0x1d
955 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel_MASK 0x40000000
956 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBTargetMemSel__SHIFT 0x1e
957 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable_MASK 0x80000000
958 #define ACP_DAGB_BASE_ADDR_GRP_7__AXI2DAGBGrpEnable__SHIFT 0x1f
959 #define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize_MASK 0x3
960 #define ACP_DAGB_PAGE_SIZE_GRP_8__AXI2DAGBPageSize__SHIFT 0x0
961 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr_MASK 0xfffffff
962 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBBaseAddr__SHIFT 0x0
963 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel_MASK 0x20000000
964 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBSnoopSel__SHIFT 0x1d
965 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel_MASK 0x40000000
966 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBTargetMemSel__SHIFT 0x1e
967 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable_MASK 0x80000000
968 #define ACP_DAGB_BASE_ADDR_GRP_8__AXI2DAGBGrpEnable__SHIFT 0x1f
969 #define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate_MASK 0x1
970 #define ACP_DAGB_ATU_CTRL__AXI2DAGBCacheInvalidate__SHIFT 0x0
971 #define ACP_CONTROL__ClkEn_MASK 0x1
972 #define ACP_CONTROL__ClkEn__SHIFT 0x0
973 #define ACP_CONTROL__JtagEn_MASK 0x400
974 #define ACP_CONTROL__JtagEn__SHIFT 0xa
975 #define ACP_STATUS__ClkOn_MASK 0x1
976 #define ACP_STATUS__ClkOn__SHIFT 0x0
977 #define ACP_STATUS__ACPRefClkSpd_MASK 0x2
978 #define ACP_STATUS__ACPRefClkSpd__SHIFT 0x1
979 #define ACP_STATUS__SMUStutterLastEdge_MASK 0x4
980 #define ACP_STATUS__SMUStutterLastEdge__SHIFT 0x2
981 #define ACP_STATUS__MCStutterLastEdge_MASK 0x8
982 #define ACP_STATUS__MCStutterLastEdge__SHIFT 0x3
983 #define ACP_SOFT_RESET__SoftResetAud_MASK 0x100
984 #define ACP_SOFT_RESET__SoftResetAud__SHIFT 0x8
985 #define ACP_SOFT_RESET__SoftResetDMA_MASK 0x200
986 #define ACP_SOFT_RESET__SoftResetDMA__SHIFT 0x9
987 #define ACP_SOFT_RESET__InternalSoftResetMode_MASK 0x4000
988 #define ACP_SOFT_RESET__InternalSoftResetMode__SHIFT 0xe
989 #define ACP_SOFT_RESET__ExternalSoftResetMode_MASK 0x8000
990 #define ACP_SOFT_RESET__ExternalSoftResetMode__SHIFT 0xf
991 #define ACP_SOFT_RESET__SoftResetAudDone_MASK 0x1000000
992 #define ACP_SOFT_RESET__SoftResetAudDone__SHIFT 0x18
993 #define ACP_SOFT_RESET__SoftResetDMADone_MASK 0x2000000
994 #define ACP_SOFT_RESET__SoftResetDMADone__SHIFT 0x19
995 #define ACP_PwrMgmt_CNTL__SCLKSleepCntl_MASK 0x3
996 #define ACP_PwrMgmt_CNTL__SCLKSleepCntl__SHIFT 0x0
997 #define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter_MASK 0xffff
998 #define ACP_CAC_INDICATOR_CONTROL__ACP_Cac_Indicator_Counter__SHIFT 0x0
999 #define ACP_SMU_MAILBOX__ACP_SMU_Mailbox_MASK 0xffffffff
1000 #define ACP_SMU_MAILBOX__ACP_SMU_Mailbox__SHIFT 0x0
1001 #define ACP_FUTURE_REG_SCLK_0__ACPFutureReg_MASK 0xffffffff
1002 #define ACP_FUTURE_REG_SCLK_0__ACPFutureReg__SHIFT 0x0
1003 #define ACP_FUTURE_REG_SCLK_1__ACPFutureReg_MASK 0xffffffff
1004 #define ACP_FUTURE_REG_SCLK_1__ACPFutureReg__SHIFT 0x0
1005 #define ACP_FUTURE_REG_SCLK_2__ACPFutureReg_MASK 0xffffffff
1006 #define ACP_FUTURE_REG_SCLK_2__ACPFutureReg__SHIFT 0x0
1007 #define ACP_FUTURE_REG_SCLK_3__ACPFutureReg_MASK 0xffffffff
1008 #define ACP_FUTURE_REG_SCLK_3__ACPFutureReg__SHIFT 0x0
1009 #define ACP_FUTURE_REG_SCLK_4__ACPFutureReg_MASK 0xffffffff
1010 #define ACP_FUTURE_REG_SCLK_4__ACPFutureReg__SHIFT 0x0
1011 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable_MASK 0x1
1012 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_ask_cnt_enable__SHIFT 0x0
1013 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable_MASK 0x2
1014 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_go_cnt_enable__SHIFT 0x1
1015 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable_MASK 0x4
1016 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_exp_respcnt_enable__SHIFT 0x2
1017 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable_MASK 0x8
1018 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_wr_actual_respcnt_enable__SHIFT 0x3
1019 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable_MASK 0x10
1020 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_ask_cnt_enable__SHIFT 0x4
1021 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable_MASK 0x20
1022 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_go_cnt_enable__SHIFT 0x5
1023 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable_MASK 0x40
1024 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_exp_respcnt_enable__SHIFT 0x6
1025 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable_MASK 0x80
1026 #define ACP_DAGB_DEBUG_CNT_ENABLE__garlic_rd_actual_respcnt_enable__SHIFT 0x7
1027 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable_MASK 0x100
1028 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_ask_cnt_enable__SHIFT 0x8
1029 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable_MASK 0x200
1030 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_go_cnt_enable__SHIFT 0x9
1031 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable_MASK 0x400
1032 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_exp_respcnt_enable__SHIFT 0xa
1033 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable_MASK 0x800
1034 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_wr_actual_respcnt_enable__SHIFT 0xb
1035 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable_MASK 0x1000
1036 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_ask_cnt_enable__SHIFT 0xc
1037 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable_MASK 0x2000
1038 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_go_cnt_enable__SHIFT 0xd
1039 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable_MASK 0x4000
1040 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_exp_respcnt_enable__SHIFT 0xe
1041 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable_MASK 0x8000
1042 #define ACP_DAGB_DEBUG_CNT_ENABLE__onion_rd_actual_respcnt_enable__SHIFT 0xf
1043 #define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt_MASK 0xffff
1044 #define ACP_DAGBG_WR_ASK_CNT__garlic_wr_only_ask_cnt__SHIFT 0x0
1045 #define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt_MASK 0xffff
1046 #define ACP_DAGBG_WR_GO_CNT__garlic_wr_only_go_cnt__SHIFT 0x0
1047 #define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt_MASK 0xffff
1048 #define ACP_DAGBG_WR_EXP_RESP_CNT__garlic_wr_exp_resp_cnt__SHIFT 0x0
1049 #define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt_MASK 0xffff
1050 #define ACP_DAGBG_WR_ACTUAL_RESP_CNT__garlic_wr_actual_resp_cnt__SHIFT 0x0
1051 #define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt_MASK 0xffff
1052 #define ACP_DAGBG_RD_ASK_CNT__garlic_rd_only_ask_cnt__SHIFT 0x0
1053 #define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt_MASK 0xffff
1054 #define ACP_DAGBG_RD_GO_CNT__garlic_rd_only_go_cnt__SHIFT 0x0
1055 #define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt_MASK 0xffff
1056 #define ACP_DAGBG_RD_EXP_RESP_CNT__garlic_rd_exp_resp_cnt__SHIFT 0x0
1057 #define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt_MASK 0xffff
1058 #define ACP_DAGBG_RD_ACTUAL_RESP_CNT__garlic_rd_actual_resp_cnt__SHIFT 0x0
1059 #define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt_MASK 0xffff
1060 #define ACP_DAGBO_WR_ASK_CNT__onion_wr_only_ask_cnt__SHIFT 0x0
1061 #define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt_MASK 0xffff
1062 #define ACP_DAGBO_WR_GO_CNT__onion_wr_only_go_cnt__SHIFT 0x0
1063 #define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt_MASK 0xffff
1064 #define ACP_DAGBO_WR_EXP_RESP_CNT__onion_wr_exp_resp_cnt__SHIFT 0x0
1065 #define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt_MASK 0xffff
1066 #define ACP_DAGBO_WR_ACTUAL_RESP_CNT__onion_wr_actual_resp_cnt__SHIFT 0x0
1067 #define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt_MASK 0xffff
1068 #define ACP_DAGBO_RD_ASK_CNT__onion_rd_only_ask_cnt__SHIFT 0x0
1069 #define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt_MASK 0xffff
1070 #define ACP_DAGBO_RD_GO_CNT__onion_rd_only_go_cnt__SHIFT 0x0
1071 #define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt_MASK 0xffff
1072 #define ACP_DAGBO_RD_EXP_RESP_CNT__onion_rd_exp_resp_cnt__SHIFT 0x0
1073 #define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt_MASK 0xffff
1074 #define ACP_DAGBO_RD_ACTUAL_RESP_CNT__onion_rd_actual_resp_cnt__SHIFT 0x0
1075 #define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl_MASK 0xf
1076 #define ACP_BRB_CONTROL__BRB_BlockSharedRAMArbCntrl__SHIFT 0x0
1077 #define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb_MASK 0x1
1078 #define ACP_EXTERNAL_INTR_ENB__ACPExtIntrEnb__SHIFT 0x0
1079 #define ACP_EXTERNAL_INTR_CNTL__ACPErrMask_MASK 0x1
1080 #define ACP_EXTERNAL_INTR_CNTL__ACPErrMask__SHIFT 0x0
1081 #define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask_MASK 0x2
1082 #define ACP_EXTERNAL_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1
1083 #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4
1084 #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2
1085 #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8
1086 #define ACP_EXTERNAL_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3
1087 #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask_MASK 0x10
1088 #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4
1089 #define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask_MASK 0x40
1090 #define ACP_EXTERNAL_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6
1091 #define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask_MASK 0x100
1092 #define ACP_EXTERNAL_INTR_CNTL__DSP0TimeoutMask__SHIFT 0x8
1093 #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask_MASK 0x200
1094 #define ACP_EXTERNAL_INTR_CNTL__DSP1TimeoutMask__SHIFT 0x9
1095 #define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask_MASK 0x400
1096 #define ACP_EXTERNAL_INTR_CNTL__DSP2TimeoutMask__SHIFT 0xa
1097 #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x800
1098 #define ACP_EXTERNAL_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xb
1099 #define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK 0xffff0000
1100 #define ACP_EXTERNAL_INTR_CNTL__DMAIOCMask__SHIFT 0x10
1101 #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr_MASK 0x1
1102 #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErr__SHIFT 0x0
1103 #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource_MASK 0xe
1104 #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSource__SHIFT 0x1
1105 #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver_MASK 0x10
1106 #define ACP_ERROR_SOURCE_STS__ACPRegUdefADDRErrSourceOver__SHIFT 0x4
1107 #define ACP_ERROR_SOURCE_STS__BRBAddrErr_MASK 0x20
1108 #define ACP_ERROR_SOURCE_STS__BRBAddrErr__SHIFT 0x5
1109 #define ACP_ERROR_SOURCE_STS__BRBAddrErrSource_MASK 0x3c0
1110 #define ACP_ERROR_SOURCE_STS__BRBAddrErrSource__SHIFT 0x6
1111 #define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver_MASK 0x400
1112 #define ACP_ERROR_SOURCE_STS__BRBAddrErrSourceOver__SHIFT 0xa
1113 #define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr_MASK 0x800
1114 #define ACP_ERROR_SOURCE_STS__I2SMicOverFlowErr__SHIFT 0xb
1115 #define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr_MASK 0x1000
1116 #define ACP_ERROR_SOURCE_STS__I2SSpeaker0OverFlowErr__SHIFT 0xc
1117 #define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr_MASK 0x2000
1118 #define ACP_ERROR_SOURCE_STS__I2SSpeaker1OverFlowErr__SHIFT 0xd
1119 #define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr_MASK 0x4000
1120 #define ACP_ERROR_SOURCE_STS__I2SBTRxFifoOverFlowErr__SHIFT 0xe
1121 #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr_MASK 0x8000
1122 #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErr__SHIFT 0xf
1123 #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource_MASK 0x70000
1124 #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSource__SHIFT 0x10
1125 #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver_MASK 0x80000
1126 #define ACP_ERROR_SOURCE_STS__DSPAdrTransRangeErrSourceOver__SHIFT 0x13
1127 #define ACP_ERROR_SOURCE_STS__DAGBErr_MASK 0x100000
1128 #define ACP_ERROR_SOURCE_STS__DAGBErr__SHIFT 0x14
1129 #define ACP_ERROR_SOURCE_STS__DAGBErrSource_MASK 0x1e00000
1130 #define ACP_ERROR_SOURCE_STS__DAGBErrSource__SHIFT 0x15
1131 #define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver_MASK 0x2000000
1132 #define ACP_ERROR_SOURCE_STS__DAGBErrSourceOver__SHIFT 0x19
1133 #define ACP_ERROR_SOURCE_STS__DMATermOnErr_MASK 0x4000000
1134 #define ACP_ERROR_SOURCE_STS__DMATermOnErr__SHIFT 0x1a
1135 #define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr_MASK 0x10000000
1136 #define ACP_ERROR_SOURCE_STS__I2SBTTxFifoOverFlowErr__SHIFT 0x1c
1137 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0_MASK 0x1
1138 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP0__SHIFT 0x0
1139 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1_MASK 0x2
1140 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP1__SHIFT 0x1
1141 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2_MASK 0x4
1142 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntHostDSP2__SHIFT 0x2
1143 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0_MASK 0x100
1144 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP0__SHIFT 0x8
1145 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1_MASK 0x200
1146 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP1__SHIFT 0x9
1147 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2_MASK 0x400
1148 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSPnDSP2__SHIFT 0xa
1149 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host_MASK 0x10000
1150 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP0Host__SHIFT 0x10
1151 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host_MASK 0x20000
1152 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP1Host__SHIFT 0x11
1153 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host_MASK 0x40000
1154 #define ACP_DSP_SW_INTR_TRIG__TrigSWIntDSP2Host__SHIFT 0x12
1155 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0_MASK 0x1
1156 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP0__SHIFT 0x0
1157 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1_MASK 0x2
1158 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP1__SHIFT 0x1
1159 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2_MASK 0x4
1160 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntHostDSP2__SHIFT 0x2
1161 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0_MASK 0x100
1162 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP0__SHIFT 0x8
1163 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1_MASK 0x200
1164 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP1__SHIFT 0x9
1165 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2_MASK 0x400
1166 #define ACP_DSP_SW_INTR_CNTL__EnbSWIntDSPnDSP2__SHIFT 0xa
1167 #define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask_MASK 0x10000
1168 #define ACP_DSP_SW_INTR_CNTL__EnbKernelIntrDSP0Mask__SHIFT 0x10
1169 #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask_MASK 0x20000
1170 #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP1Mask__SHIFT 0x11
1171 #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask_MASK 0x40000
1172 #define ACP_DSP_SW_INTR_CNTL__EmbKernelIntrDSP2Mask__SHIFT 0x12
1173 #define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue_MASK 0x3ffff
1174 #define ACP_DAGBG_TIMEOUT_CNTL__DAGBGTimeoutValue__SHIFT 0x0
1175 #define ACP_DAGBG_TIMEOUT_CNTL__CntEn_MASK 0x80000000
1176 #define ACP_DAGBG_TIMEOUT_CNTL__CntEn__SHIFT 0x1f
1177 #define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue_MASK 0x3ffff
1178 #define ACP_DAGBO_TIMEOUT_CNTL__DAGBOTimeoutValue__SHIFT 0x0
1179 #define ACP_DAGBO_TIMEOUT_CNTL__CntEn_MASK 0x80000000
1180 #define ACP_DAGBO_TIMEOUT_CNTL__CntEn__SHIFT 0x1f
1181 #define ACP_EXTERNAL_INTR_STAT__ACPErrStat_MASK 0x1
1182 #define ACP_EXTERNAL_INTR_STAT__ACPErrStat__SHIFT 0x0
1183 #define ACP_EXTERNAL_INTR_STAT__ACPErrAck_MASK 0x1
1184 #define ACP_EXTERNAL_INTR_STAT__ACPErrAck__SHIFT 0x0
1185 #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat_MASK 0x2
1186 #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1
1187 #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck_MASK 0x2
1188 #define ACP_EXTERNAL_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1
1189 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4
1190 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2
1191 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4
1192 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2
1193 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8
1194 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3
1195 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8
1196 #define ACP_EXTERNAL_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3
1197 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat_MASK 0x10
1198 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4
1199 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck_MASK 0x10
1200 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4
1201 #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat_MASK 0x40
1202 #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrStat__SHIFT 0x6
1203 #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck_MASK 0x40
1204 #define ACP_EXTERNAL_INTR_STAT__AzaliaIntrAck__SHIFT 0x6
1205 #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat_MASK 0x100
1206 #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutStat__SHIFT 0x8
1207 #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck_MASK 0x100
1208 #define ACP_EXTERNAL_INTR_STAT__DSP0TimeoutAck__SHIFT 0x8
1209 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat_MASK 0x200
1210 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutStat__SHIFT 0x9
1211 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck_MASK 0x200
1212 #define ACP_EXTERNAL_INTR_STAT__DSP1TimeoutAck__SHIFT 0x9
1213 #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat_MASK 0x400
1214 #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutStat__SHIFT 0xa
1215 #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck_MASK 0x400
1216 #define ACP_EXTERNAL_INTR_STAT__DSP2TimeoutAck__SHIFT 0xa
1217 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat_MASK 0x800
1218 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xb
1219 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck_MASK 0x800
1220 #define ACP_EXTERNAL_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xb
1221 #define ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK 0xffff0000
1222 #define ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT 0x10
1223 #define ACP_EXTERNAL_INTR_STAT__DMAIOCAck_MASK 0xffff0000
1224 #define ACP_EXTERNAL_INTR_STAT__DMAIOCAck__SHIFT 0x10
1225 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat_MASK 0x1
1226 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Stat__SHIFT 0x0
1227 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack_MASK 0x1
1228 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP0Ack__SHIFT 0x0
1229 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat_MASK 0x2
1230 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Stat__SHIFT 0x1
1231 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack_MASK 0x2
1232 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP1Ack__SHIFT 0x1
1233 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat_MASK 0x4
1234 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Stat__SHIFT 0x2
1235 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack_MASK 0x4
1236 #define ACP_DSP_SW_INTR_STAT__SWIntHostDSP2Ack__SHIFT 0x2
1237 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat_MASK 0x100
1238 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Stat__SHIFT 0x8
1239 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack_MASK 0x100
1240 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP0Ack__SHIFT 0x8
1241 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat_MASK 0x200
1242 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Stat__SHIFT 0x9
1243 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack_MASK 0x200
1244 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP1Ack__SHIFT 0x9
1245 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat_MASK 0x400
1246 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Stat__SHIFT 0xa
1247 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack_MASK 0x400
1248 #define ACP_DSP_SW_INTR_STAT__SWIntDSPnDSP2Ack__SHIFT 0xa
1249 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat_MASK 0x10000
1250 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Stat__SHIFT 0x10
1251 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack_MASK 0x10000
1252 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP0Ack__SHIFT 0x10
1253 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat_MASK 0x20000
1254 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Stat__SHIFT 0x11
1255 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack_MASK 0x20000
1256 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP1Ack__SHIFT 0x11
1257 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat_MASK 0x40000
1258 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Stat__SHIFT 0x12
1259 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack_MASK 0x40000
1260 #define ACP_DSP_SW_INTR_STAT__SWKernelIntrDSP2Ack__SHIFT 0x12
1261 #define ACP_DSP0_INTR_CNTL__ACPErrMask_MASK 0x1
1262 #define ACP_DSP0_INTR_CNTL__ACPErrMask__SHIFT 0x0
1263 #define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask_MASK 0x2
1264 #define ACP_DSP0_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1
1265 #define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4
1266 #define ACP_DSP0_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2
1267 #define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8
1268 #define ACP_DSP0_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3
1269 #define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask_MASK 0x10
1270 #define ACP_DSP0_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4
1271 #define ACP_DSP0_INTR_CNTL__AzaliaIntrMask_MASK 0x40
1272 #define ACP_DSP0_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6
1273 #define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100
1274 #define ACP_DSP0_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8
1275 #define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask_MASK 0x200
1276 #define ACP_DSP0_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9
1277 #define ACP_DSP0_INTR_CNTL__MCStutterStatusMask_MASK 0x400
1278 #define ACP_DSP0_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa
1279 #define ACP_DSP0_INTR_CNTL__DSPExtTimerMask_MASK 0x800
1280 #define ACP_DSP0_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb
1281 #define ACP_DSP0_INTR_CNTL__DSPSemRespMask_MASK 0x1000
1282 #define ACP_DSP0_INTR_CNTL__DSPSemRespMask__SHIFT 0xc
1283 #define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000
1284 #define ACP_DSP0_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd
1285 #define ACP_DSP0_INTR_CNTL__DMAIOCMask_MASK 0xffff0000
1286 #define ACP_DSP0_INTR_CNTL__DMAIOCMask__SHIFT 0x10
1287 #define ACP_DSP0_INTR_STAT__ACPErrStat_MASK 0x1
1288 #define ACP_DSP0_INTR_STAT__ACPErrStat__SHIFT 0x0
1289 #define ACP_DSP0_INTR_STAT__ACPErrAck_MASK 0x1
1290 #define ACP_DSP0_INTR_STAT__ACPErrAck__SHIFT 0x0
1291 #define ACP_DSP0_INTR_STAT__I2SMicDataAvStat_MASK 0x2
1292 #define ACP_DSP0_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1
1293 #define ACP_DSP0_INTR_STAT__I2SMicDataAvAck_MASK 0x2
1294 #define ACP_DSP0_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1
1295 #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4
1296 #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2
1297 #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4
1298 #define ACP_DSP0_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2
1299 #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8
1300 #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3
1301 #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8
1302 #define ACP_DSP0_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3
1303 #define ACP_DSP0_INTR_STAT__I2SBTDataAvStat_MASK 0x10
1304 #define ACP_DSP0_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4
1305 #define ACP_DSP0_INTR_STAT__I2SBTDataAvAck_MASK 0x10
1306 #define ACP_DSP0_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4
1307 #define ACP_DSP0_INTR_STAT__AzaliaIntrStat_MASK 0x40
1308 #define ACP_DSP0_INTR_STAT__AzaliaIntrStat__SHIFT 0x6
1309 #define ACP_DSP0_INTR_STAT__AzaliaIntrAck_MASK 0x40
1310 #define ACP_DSP0_INTR_STAT__AzaliaIntrAck__SHIFT 0x6
1311 #define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat_MASK 0x100
1312 #define ACP_DSP0_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8
1313 #define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck_MASK 0x100
1314 #define ACP_DSP0_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8
1315 #define ACP_DSP0_INTR_STAT__SMUStutterStatusStat_MASK 0x200
1316 #define ACP_DSP0_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9
1317 #define ACP_DSP0_INTR_STAT__SMUStutterStatusAck_MASK 0x200
1318 #define ACP_DSP0_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9
1319 #define ACP_DSP0_INTR_STAT__MCStutterStatusStat_MASK 0x400
1320 #define ACP_DSP0_INTR_STAT__MCStutterStatusStat__SHIFT 0xa
1321 #define ACP_DSP0_INTR_STAT__MCStutterStatusAck_MASK 0x400
1322 #define ACP_DSP0_INTR_STAT__MCStutterStatusAck__SHIFT 0xa
1323 #define ACP_DSP0_INTR_STAT__DSPExtTimerStat_MASK 0x800
1324 #define ACP_DSP0_INTR_STAT__DSPExtTimerStat__SHIFT 0xb
1325 #define ACP_DSP0_INTR_STAT__DSPExtTimerAck_MASK 0x800
1326 #define ACP_DSP0_INTR_STAT__DSPExtTimerAck__SHIFT 0xb
1327 #define ACP_DSP0_INTR_STAT__DSPSemRespStat_MASK 0x1000
1328 #define ACP_DSP0_INTR_STAT__DSPSemRespStat__SHIFT 0xc
1329 #define ACP_DSP0_INTR_STAT__DSPSemRespAck_MASK 0x1000
1330 #define ACP_DSP0_INTR_STAT__DSPSemRespAck__SHIFT 0xc
1331 #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000
1332 #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd
1333 #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000
1334 #define ACP_DSP0_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd
1335 #define ACP_DSP0_INTR_STAT__DMAIOCStat_MASK 0xffff0000
1336 #define ACP_DSP0_INTR_STAT__DMAIOCStat__SHIFT 0x10
1337 #define ACP_DSP0_INTR_STAT__DMAIOCAck_MASK 0xffff0000
1338 #define ACP_DSP0_INTR_STAT__DMAIOCAck__SHIFT 0x10
1339 #define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue_MASK 0x3ffff
1340 #define ACP_DSP0_TIMEOUT_CNTL__DSP0TimeoutValue__SHIFT 0x0
1341 #define ACP_DSP0_TIMEOUT_CNTL__CntEn_MASK 0x80000000
1342 #define ACP_DSP0_TIMEOUT_CNTL__CntEn__SHIFT 0x1f
1343 #define ACP_DSP1_INTR_CNTL__ACPErrMask_MASK 0x1
1344 #define ACP_DSP1_INTR_CNTL__ACPErrMask__SHIFT 0x0
1345 #define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask_MASK 0x2
1346 #define ACP_DSP1_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1
1347 #define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4
1348 #define ACP_DSP1_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2
1349 #define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8
1350 #define ACP_DSP1_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3
1351 #define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask_MASK 0x10
1352 #define ACP_DSP1_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4
1353 #define ACP_DSP1_INTR_CNTL__AzaliaIntrMask_MASK 0x40
1354 #define ACP_DSP1_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6
1355 #define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100
1356 #define ACP_DSP1_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8
1357 #define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask_MASK 0x200
1358 #define ACP_DSP1_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9
1359 #define ACP_DSP1_INTR_CNTL__MCStutterStatusMask_MASK 0x400
1360 #define ACP_DSP1_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa
1361 #define ACP_DSP1_INTR_CNTL__DSPExtTimerMask_MASK 0x800
1362 #define ACP_DSP1_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb
1363 #define ACP_DSP1_INTR_CNTL__DSPSemRespMask_MASK 0x1000
1364 #define ACP_DSP1_INTR_CNTL__DSPSemRespMask__SHIFT 0xc
1365 #define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000
1366 #define ACP_DSP1_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd
1367 #define ACP_DSP1_INTR_CNTL__DMAIOCMask_MASK 0xffff0000
1368 #define ACP_DSP1_INTR_CNTL__DMAIOCMask__SHIFT 0x10
1369 #define ACP_DSP1_INTR_STAT__ACPErrStat_MASK 0x1
1370 #define ACP_DSP1_INTR_STAT__ACPErrStat__SHIFT 0x0
1371 #define ACP_DSP1_INTR_STAT__ACPErrAck_MASK 0x1
1372 #define ACP_DSP1_INTR_STAT__ACPErrAck__SHIFT 0x0
1373 #define ACP_DSP1_INTR_STAT__I2SMicDataAvStat_MASK 0x2
1374 #define ACP_DSP1_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1
1375 #define ACP_DSP1_INTR_STAT__I2SMicDataAvAck_MASK 0x2
1376 #define ACP_DSP1_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1
1377 #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4
1378 #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2
1379 #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4
1380 #define ACP_DSP1_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2
1381 #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8
1382 #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3
1383 #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8
1384 #define ACP_DSP1_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3
1385 #define ACP_DSP1_INTR_STAT__I2SBTDataAvStat_MASK 0x10
1386 #define ACP_DSP1_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4
1387 #define ACP_DSP1_INTR_STAT__I2SBTDataAvAck_MASK 0x10
1388 #define ACP_DSP1_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4
1389 #define ACP_DSP1_INTR_STAT__AzaliaIntrStat_MASK 0x40
1390 #define ACP_DSP1_INTR_STAT__AzaliaIntrStat__SHIFT 0x6
1391 #define ACP_DSP1_INTR_STAT__AzaliaIntrAck_MASK 0x40
1392 #define ACP_DSP1_INTR_STAT__AzaliaIntrAck__SHIFT 0x6
1393 #define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat_MASK 0x100
1394 #define ACP_DSP1_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8
1395 #define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck_MASK 0x100
1396 #define ACP_DSP1_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8
1397 #define ACP_DSP1_INTR_STAT__SMUStutterStatusStat_MASK 0x200
1398 #define ACP_DSP1_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9
1399 #define ACP_DSP1_INTR_STAT__SMUStutterStatusAck_MASK 0x200
1400 #define ACP_DSP1_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9
1401 #define ACP_DSP1_INTR_STAT__MCStutterStatusStat_MASK 0x400
1402 #define ACP_DSP1_INTR_STAT__MCStutterStatusStat__SHIFT 0xa
1403 #define ACP_DSP1_INTR_STAT__MCStutterStatusAck_MASK 0x400
1404 #define ACP_DSP1_INTR_STAT__MCStutterStatusAck__SHIFT 0xa
1405 #define ACP_DSP1_INTR_STAT__DSPExtTimerStat_MASK 0x800
1406 #define ACP_DSP1_INTR_STAT__DSPExtTimerStat__SHIFT 0xb
1407 #define ACP_DSP1_INTR_STAT__DSPExtTimerAck_MASK 0x800
1408 #define ACP_DSP1_INTR_STAT__DSPExtTimerAck__SHIFT 0xb
1409 #define ACP_DSP1_INTR_STAT__DSPSemRespStat_MASK 0x1000
1410 #define ACP_DSP1_INTR_STAT__DSPSemRespStat__SHIFT 0xc
1411 #define ACP_DSP1_INTR_STAT__DSPSemRespAck_MASK 0x1000
1412 #define ACP_DSP1_INTR_STAT__DSPSemRespAck__SHIFT 0xc
1413 #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000
1414 #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd
1415 #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000
1416 #define ACP_DSP1_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd
1417 #define ACP_DSP1_INTR_STAT__DMAIOCStat_MASK 0xffff0000
1418 #define ACP_DSP1_INTR_STAT__DMAIOCStat__SHIFT 0x10
1419 #define ACP_DSP1_INTR_STAT__DMAIOCAck_MASK 0xffff0000
1420 #define ACP_DSP1_INTR_STAT__DMAIOCAck__SHIFT 0x10
1421 #define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue_MASK 0x3ffff
1422 #define ACP_DSP1_TIMEOUT_CNTL__DSP1TimeoutValue__SHIFT 0x0
1423 #define ACP_DSP1_TIMEOUT_CNTL__CntEn_MASK 0x80000000
1424 #define ACP_DSP1_TIMEOUT_CNTL__CntEn__SHIFT 0x1f
1425 #define ACP_DSP2_INTR_CNTL__ACPErrMask_MASK 0x1
1426 #define ACP_DSP2_INTR_CNTL__ACPErrMask__SHIFT 0x0
1427 #define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask_MASK 0x2
1428 #define ACP_DSP2_INTR_CNTL__I2SMicDataAvMask__SHIFT 0x1
1429 #define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask_MASK 0x4
1430 #define ACP_DSP2_INTR_CNTL__I2SSpkr0DataEmptyMask__SHIFT 0x2
1431 #define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask_MASK 0x8
1432 #define ACP_DSP2_INTR_CNTL__I2SSpkr1DataEmptyMask__SHIFT 0x3
1433 #define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask_MASK 0x10
1434 #define ACP_DSP2_INTR_CNTL__I2SBTDataAvMask__SHIFT 0x4
1435 #define ACP_DSP2_INTR_CNTL__AzaliaIntrMask_MASK 0x40
1436 #define ACP_DSP2_INTR_CNTL__AzaliaIntrMask__SHIFT 0x6
1437 #define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask_MASK 0x100
1438 #define ACP_DSP2_INTR_CNTL__SMUMailboxWriteMask__SHIFT 0x8
1439 #define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask_MASK 0x200
1440 #define ACP_DSP2_INTR_CNTL__SMUStutterStatusMask__SHIFT 0x9
1441 #define ACP_DSP2_INTR_CNTL__MCStutterStatusMask_MASK 0x400
1442 #define ACP_DSP2_INTR_CNTL__MCStutterStatusMask__SHIFT 0xa
1443 #define ACP_DSP2_INTR_CNTL__DSPExtTimerMask_MASK 0x800
1444 #define ACP_DSP2_INTR_CNTL__DSPExtTimerMask__SHIFT 0xb
1445 #define ACP_DSP2_INTR_CNTL__DSPSemRespMask_MASK 0x1000
1446 #define ACP_DSP2_INTR_CNTL__DSPSemRespMask__SHIFT 0xc
1447 #define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask_MASK 0x2000
1448 #define ACP_DSP2_INTR_CNTL__I2SBTDataEmptyMask__SHIFT 0xd
1449 #define ACP_DSP2_INTR_CNTL__DMAIOCMask_MASK 0xffff0000
1450 #define ACP_DSP2_INTR_CNTL__DMAIOCMask__SHIFT 0x10
1451 #define ACP_DSP2_INTR_STAT__ACPErrStat_MASK 0x1
1452 #define ACP_DSP2_INTR_STAT__ACPErrStat__SHIFT 0x0
1453 #define ACP_DSP2_INTR_STAT__ACPErrAck_MASK 0x1
1454 #define ACP_DSP2_INTR_STAT__ACPErrAck__SHIFT 0x0
1455 #define ACP_DSP2_INTR_STAT__I2SMicDataAvStat_MASK 0x2
1456 #define ACP_DSP2_INTR_STAT__I2SMicDataAvStat__SHIFT 0x1
1457 #define ACP_DSP2_INTR_STAT__I2SMicDataAvAck_MASK 0x2
1458 #define ACP_DSP2_INTR_STAT__I2SMicDataAvAck__SHIFT 0x1
1459 #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat_MASK 0x4
1460 #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyStat__SHIFT 0x2
1461 #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck_MASK 0x4
1462 #define ACP_DSP2_INTR_STAT__I2SSpkr0DataEmptyAck__SHIFT 0x2
1463 #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat_MASK 0x8
1464 #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyStat__SHIFT 0x3
1465 #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck_MASK 0x8
1466 #define ACP_DSP2_INTR_STAT__I2SSpkr1DataEmptyAck__SHIFT 0x3
1467 #define ACP_DSP2_INTR_STAT__I2SBTDataAvStat_MASK 0x10
1468 #define ACP_DSP2_INTR_STAT__I2SBTDataAvStat__SHIFT 0x4
1469 #define ACP_DSP2_INTR_STAT__I2SBTDataAvAck_MASK 0x10
1470 #define ACP_DSP2_INTR_STAT__I2SBTDataAvAck__SHIFT 0x4
1471 #define ACP_DSP2_INTR_STAT__AzaliaIntrStat_MASK 0x40
1472 #define ACP_DSP2_INTR_STAT__AzaliaIntrStat__SHIFT 0x6
1473 #define ACP_DSP2_INTR_STAT__AzaliaIntrAck_MASK 0x40
1474 #define ACP_DSP2_INTR_STAT__AzaliaIntrAck__SHIFT 0x6
1475 #define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat_MASK 0x100
1476 #define ACP_DSP2_INTR_STAT__SMUMailboxWriteStat__SHIFT 0x8
1477 #define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck_MASK 0x100
1478 #define ACP_DSP2_INTR_STAT__SMUMailboxWriteAck__SHIFT 0x8
1479 #define ACP_DSP2_INTR_STAT__SMUStutterStatusStat_MASK 0x200
1480 #define ACP_DSP2_INTR_STAT__SMUStutterStatusStat__SHIFT 0x9
1481 #define ACP_DSP2_INTR_STAT__SMUStutterStatusAck_MASK 0x200
1482 #define ACP_DSP2_INTR_STAT__SMUStutterStatusAck__SHIFT 0x9
1483 #define ACP_DSP2_INTR_STAT__MCStutterStatusStat_MASK 0x400
1484 #define ACP_DSP2_INTR_STAT__MCStutterStatusStat__SHIFT 0xa
1485 #define ACP_DSP2_INTR_STAT__MCStutterStatusAck_MASK 0x400
1486 #define ACP_DSP2_INTR_STAT__MCStutterStatusAck__SHIFT 0xa
1487 #define ACP_DSP2_INTR_STAT__DSPExtTimerStat_MASK 0x800
1488 #define ACP_DSP2_INTR_STAT__DSPExtTimerStat__SHIFT 0xb
1489 #define ACP_DSP2_INTR_STAT__DSPExtTimerAck_MASK 0x800
1490 #define ACP_DSP2_INTR_STAT__DSPExtTimerAck__SHIFT 0xb
1491 #define ACP_DSP2_INTR_STAT__DSPSemRespStat_MASK 0x1000
1492 #define ACP_DSP2_INTR_STAT__DSPSemRespStat__SHIFT 0xc
1493 #define ACP_DSP2_INTR_STAT__DSPSemRespAck_MASK 0x1000
1494 #define ACP_DSP2_INTR_STAT__DSPSemRespAck__SHIFT 0xc
1495 #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat_MASK 0x2000
1496 #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyStat__SHIFT 0xd
1497 #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck_MASK 0x2000
1498 #define ACP_DSP2_INTR_STAT__I2SBTDataEmptyAck__SHIFT 0xd
1499 #define ACP_DSP2_INTR_STAT__DMAIOCStat_MASK 0xffff0000
1500 #define ACP_DSP2_INTR_STAT__DMAIOCStat__SHIFT 0x10
1501 #define ACP_DSP2_INTR_STAT__DMAIOCAck_MASK 0xffff0000
1502 #define ACP_DSP2_INTR_STAT__DMAIOCAck__SHIFT 0x10
1503 #define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue_MASK 0x3ffff
1504 #define ACP_DSP2_TIMEOUT_CNTL__DSP2TimeoutValue__SHIFT 0x0
1505 #define ACP_DSP2_TIMEOUT_CNTL__CntEn_MASK 0x80000000
1506 #define ACP_DSP2_TIMEOUT_CNTL__CntEn__SHIFT 0x1f
1507 #define ACP_DSP0_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff
1508 #define ACP_DSP0_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0
1509 #define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000
1510 #define ACP_DSP0_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e
1511 #define ACP_DSP1_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff
1512 #define ACP_DSP1_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0
1513 #define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000
1514 #define ACP_DSP1_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e
1515 #define ACP_DSP2_EXT_TIMER_CNTL__TimerCount_MASK 0xffffff
1516 #define ACP_DSP2_EXT_TIMER_CNTL__TimerCount__SHIFT 0x0
1517 #define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl_MASK 0xc0000000
1518 #define ACP_DSP2_EXT_TIMER_CNTL__TimerCntl__SHIFT 0x1e
1519 #define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg_MASK 0x1
1520 #define ACP_AXI2DAGB_SEM_0__AXI2DAGBGblSemReg__SHIFT 0x0
1521 #define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg_MASK 0x1
1522 #define ACP_AXI2DAGB_SEM_1__AXI2DAGBGblSemReg__SHIFT 0x0
1523 #define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg_MASK 0x1
1524 #define ACP_AXI2DAGB_SEM_2__AXI2DAGBGblSemReg__SHIFT 0x0
1525 #define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg_MASK 0x1
1526 #define ACP_AXI2DAGB_SEM_3__AXI2DAGBGblSemReg__SHIFT 0x0
1527 #define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg_MASK 0x1
1528 #define ACP_AXI2DAGB_SEM_4__AXI2DAGBGblSemReg__SHIFT 0x0
1529 #define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg_MASK 0x1
1530 #define ACP_AXI2DAGB_SEM_5__AXI2DAGBGblSemReg__SHIFT 0x0
1531 #define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg_MASK 0x1
1532 #define ACP_AXI2DAGB_SEM_6__AXI2DAGBGblSemReg__SHIFT 0x0
1533 #define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg_MASK 0x1
1534 #define ACP_AXI2DAGB_SEM_7__AXI2DAGBGblSemReg__SHIFT 0x0
1535 #define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg_MASK 0x1
1536 #define ACP_AXI2DAGB_SEM_8__AXI2DAGBGblSemReg__SHIFT 0x0
1537 #define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg_MASK 0x1
1538 #define ACP_AXI2DAGB_SEM_9__AXI2DAGBGblSemReg__SHIFT 0x0
1539 #define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg_MASK 0x1
1540 #define ACP_AXI2DAGB_SEM_10__AXI2DAGBGblSemReg__SHIFT 0x0
1541 #define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg_MASK 0x1
1542 #define ACP_AXI2DAGB_SEM_11__AXI2DAGBGblSemReg__SHIFT 0x0
1543 #define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg_MASK 0x1
1544 #define ACP_AXI2DAGB_SEM_12__AXI2DAGBGblSemReg__SHIFT 0x0
1545 #define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg_MASK 0x1
1546 #define ACP_AXI2DAGB_SEM_13__AXI2DAGBGblSemReg__SHIFT 0x0
1547 #define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg_MASK 0x1
1548 #define ACP_AXI2DAGB_SEM_14__AXI2DAGBGblSemReg__SHIFT 0x0
1549 #define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg_MASK 0x1
1550 #define ACP_AXI2DAGB_SEM_15__AXI2DAGBGblSemReg__SHIFT 0x0
1551 #define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg_MASK 0x1
1552 #define ACP_AXI2DAGB_SEM_16__AXI2DAGBGblSemReg__SHIFT 0x0
1553 #define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg_MASK 0x1
1554 #define ACP_AXI2DAGB_SEM_17__AXI2DAGBGblSemReg__SHIFT 0x0
1555 #define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg_MASK 0x1
1556 #define ACP_AXI2DAGB_SEM_18__AXI2DAGBGblSemReg__SHIFT 0x0
1557 #define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg_MASK 0x1
1558 #define ACP_AXI2DAGB_SEM_19__AXI2DAGBGblSemReg__SHIFT 0x0
1559 #define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg_MASK 0x1
1560 #define ACP_AXI2DAGB_SEM_20__AXI2DAGBGblSemReg__SHIFT 0x0
1561 #define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg_MASK 0x1
1562 #define ACP_AXI2DAGB_SEM_21__AXI2DAGBGblSemReg__SHIFT 0x0
1563 #define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg_MASK 0x1
1564 #define ACP_AXI2DAGB_SEM_22__AXI2DAGBGblSemReg__SHIFT 0x0
1565 #define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg_MASK 0x1
1566 #define ACP_AXI2DAGB_SEM_23__AXI2DAGBGblSemReg__SHIFT 0x0
1567 #define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg_MASK 0x1
1568 #define ACP_AXI2DAGB_SEM_24__AXI2DAGBGblSemReg__SHIFT 0x0
1569 #define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg_MASK 0x1
1570 #define ACP_AXI2DAGB_SEM_25__AXI2DAGBGblSemReg__SHIFT 0x0
1571 #define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg_MASK 0x1
1572 #define ACP_AXI2DAGB_SEM_26__AXI2DAGBGblSemReg__SHIFT 0x0
1573 #define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg_MASK 0x1
1574 #define ACP_AXI2DAGB_SEM_27__AXI2DAGBGblSemReg__SHIFT 0x0
1575 #define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg_MASK 0x1
1576 #define ACP_AXI2DAGB_SEM_28__AXI2DAGBGblSemReg__SHIFT 0x0
1577 #define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg_MASK 0x1
1578 #define ACP_AXI2DAGB_SEM_29__AXI2DAGBGblSemReg__SHIFT 0x0
1579 #define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg_MASK 0x1
1580 #define ACP_AXI2DAGB_SEM_30__AXI2DAGBGblSemReg__SHIFT 0x0
1581 #define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg_MASK 0x1
1582 #define ACP_AXI2DAGB_SEM_31__AXI2DAGBGblSemReg__SHIFT 0x0
1583 #define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg_MASK 0x1
1584 #define ACP_AXI2DAGB_SEM_32__AXI2DAGBGblSemReg__SHIFT 0x0
1585 #define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg_MASK 0x1
1586 #define ACP_AXI2DAGB_SEM_33__AXI2DAGBGblSemReg__SHIFT 0x0
1587 #define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg_MASK 0x1
1588 #define ACP_AXI2DAGB_SEM_34__AXI2DAGBGblSemReg__SHIFT 0x0
1589 #define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg_MASK 0x1
1590 #define ACP_AXI2DAGB_SEM_35__AXI2DAGBGblSemReg__SHIFT 0x0
1591 #define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg_MASK 0x1
1592 #define ACP_AXI2DAGB_SEM_36__AXI2DAGBGblSemReg__SHIFT 0x0
1593 #define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg_MASK 0x1
1594 #define ACP_AXI2DAGB_SEM_37__AXI2DAGBGblSemReg__SHIFT 0x0
1595 #define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg_MASK 0x1
1596 #define ACP_AXI2DAGB_SEM_38__AXI2DAGBGblSemReg__SHIFT 0x0
1597 #define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg_MASK 0x1
1598 #define ACP_AXI2DAGB_SEM_39__AXI2DAGBGblSemReg__SHIFT 0x0
1599 #define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg_MASK 0x1
1600 #define ACP_AXI2DAGB_SEM_40__AXI2DAGBGblSemReg__SHIFT 0x0
1601 #define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg_MASK 0x1
1602 #define ACP_AXI2DAGB_SEM_41__AXI2DAGBGblSemReg__SHIFT 0x0
1603 #define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg_MASK 0x1
1604 #define ACP_AXI2DAGB_SEM_42__AXI2DAGBGblSemReg__SHIFT 0x0
1605 #define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg_MASK 0x1
1606 #define ACP_AXI2DAGB_SEM_43__AXI2DAGBGblSemReg__SHIFT 0x0
1607 #define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg_MASK 0x1
1608 #define ACP_AXI2DAGB_SEM_44__AXI2DAGBGblSemReg__SHIFT 0x0
1609 #define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg_MASK 0x1
1610 #define ACP_AXI2DAGB_SEM_45__AXI2DAGBGblSemReg__SHIFT 0x0
1611 #define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg_MASK 0x1
1612 #define ACP_AXI2DAGB_SEM_46__AXI2DAGBGblSemReg__SHIFT 0x0
1613 #define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg_MASK 0x1
1614 #define ACP_AXI2DAGB_SEM_47__AXI2DAGBGblSemReg__SHIFT 0x0
1615 #define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr_MASK 0xff
1616 #define ACP_SRBM_Client_Base_Addr__SRBM_Client_base_addr__SHIFT 0x0
1617 #define ACP_SRBM_Client_RDDATA__ReadData_MASK 0xffffffff
1618 #define ACP_SRBM_Client_RDDATA__ReadData__SHIFT 0x0
1619 #define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts_MASK 0x1
1620 #define ACP_SRBM_Cycle_Sts__SRBM_Client_Sts__SHIFT 0x0
1621 #define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr_MASK 0x7ffffff
1622 #define ACP_SRBM_Targ_Idx_Addr__SRBM_Targ_Idx_addr__SHIFT 0x0
1623 #define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data_MASK 0xffffffff
1624 #define ACP_SRBM_Targ_Idx_Data__SRBM_Targ_Idx_Data__SHIFT 0x0
1625 #define ACP_SEMA_ADDR_LOW__ADDR_9_3_MASK 0x7f
1626 #define ACP_SEMA_ADDR_LOW__ADDR_9_3__SHIFT 0x0
1627 #define ACP_SEMA_ADDR_HIGH__ADDR_39_10_MASK 0x3fffffff
1628 #define ACP_SEMA_ADDR_HIGH__ADDR_39_10__SHIFT 0x0
1629 #define ACP_SEMA_CMD__REQ_CMD_MASK 0xf
1630 #define ACP_SEMA_CMD__REQ_CMD__SHIFT 0x0
1631 #define ACP_SEMA_CMD__WR_PHASE_MASK 0x30
1632 #define ACP_SEMA_CMD__WR_PHASE__SHIFT 0x4
1633 #define ACP_SEMA_CMD__VMID_EN_MASK 0x80
1634 #define ACP_SEMA_CMD__VMID_EN__SHIFT 0x7
1635 #define ACP_SEMA_CMD__VMID_MASK 0xf00
1636 #define ACP_SEMA_CMD__VMID__SHIFT 0x8
1637 #define ACP_SEMA_CMD__ATC_MASK 0x1000
1638 #define ACP_SEMA_CMD__ATC__SHIFT 0xc
1639 #define ACP_SEMA_STS__REQ_STS_MASK 0x3
1640 #define ACP_SEMA_STS__REQ_STS__SHIFT 0x0
1641 #define ACP_SEMA_STS__REQ_RESP_AVAIL_MASK 0x100
1642 #define ACP_SEMA_STS__REQ_RESP_AVAIL__SHIFT 0x8
1643 #define ACP_SEMA_REQ__ISSUE_POLL_REQ_MASK 0x1
1644 #define ACP_SEMA_REQ__ISSUE_POLL_REQ__SHIFT 0x0
1645 #define ACP_FW_STATUS__RUN_MASK 0x1
1646 #define ACP_FW_STATUS__RUN__SHIFT 0x0
1647 #define ACP_FUTURE_REG_ACLK_0__ACPFutureReg_MASK 0xffffffff
1648 #define ACP_FUTURE_REG_ACLK_0__ACPFutureReg__SHIFT 0x0
1649 #define ACP_FUTURE_REG_ACLK_1__ACPFutureReg_MASK 0xffffffff
1650 #define ACP_FUTURE_REG_ACLK_1__ACPFutureReg__SHIFT 0x0
1651 #define ACP_FUTURE_REG_ACLK_2__ACPFutureReg_MASK 0xffffffff
1652 #define ACP_FUTURE_REG_ACLK_2__ACPFutureReg__SHIFT 0x0
1653 #define ACP_FUTURE_REG_ACLK_3__ACPFutureReg_MASK 0xffffffff
1654 #define ACP_FUTURE_REG_ACLK_3__ACPFutureReg__SHIFT 0x0
1655 #define ACP_FUTURE_REG_ACLK_4__ACPFutureReg_MASK 0xffffffff
1656 #define ACP_FUTURE_REG_ACLK_4__ACPFutureReg__SHIFT 0x0
1657 #define ACP_TIMER__ACP_Timer_count_MASK 0xffffffff
1658 #define ACP_TIMER__ACP_Timer_count__SHIFT 0x0
1659 #define ACP_TIMER_CNTL__ACP_Timer_control_MASK 0x1
1660 #define ACP_TIMER_CNTL__ACP_Timer_control__SHIFT 0x0
1661 #define ACP_DSP0_TIMER__ACP_DSP0_timer_MASK 0xffffff
1662 #define ACP_DSP0_TIMER__ACP_DSP0_timer__SHIFT 0x0
1663 #define ACP_DSP1_TIMER__ACP_DSP1_timer_MASK 0xffffff
1664 #define ACP_DSP1_TIMER__ACP_DSP1_timer__SHIFT 0x0
1665 #define ACP_DSP2_TIMER__ACP_DSP2_timer_MASK 0xffffff
1666 #define ACP_DSP2_TIMER__ACP_DSP2_timer__SHIFT 0x0
1667 #define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high_MASK 0xffffffff
1668 #define ACP_I2S_TRANSMIT_BYTE_CNT_HIGH__i2s_sp_tx_byte_cnt_high__SHIFT 0x0
1669 #define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low_MASK 0xffffffff
1670 #define ACP_I2S_TRANSMIT_BYTE_CNT_LOW__i2s_sp_tx_byte_cnt_low__SHIFT 0x0
1671 #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high_MASK 0xffffffff
1672 #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH__i2s_bt_tx_byte_cnt_high__SHIFT 0x0
1673 #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low_MASK 0xffffffff
1674 #define ACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW__i2s_bt_tx_byte_cnt_low__SHIFT 0x0
1675 #define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high_MASK 0xffffffff
1676 #define ACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH__i2s_bt_rx_byte_cnt_high__SHIFT 0x0
1677 #define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low_MASK 0xffffffff
1678 #define ACP_I2S_BT_RECEIVE_BYTE_CNT_LOW__i2s_bt_rx_byte_cnt_low__SHIFT 0x0
1679 #define ACP_DSP0_CS_STATE__DSP0_CS_state_MASK 0x1
1680 #define ACP_DSP0_CS_STATE__DSP0_CS_state__SHIFT 0x0
1681 #define ACP_DSP1_CS_STATE__DSP1_CS_state_MASK 0x1
1682 #define ACP_DSP1_CS_STATE__DSP1_CS_state__SHIFT 0x0
1683 #define ACP_DSP2_CS_STATE__DSP2_CS_state_MASK 0x1
1684 #define ACP_DSP2_CS_STATE__DSP2_CS_state__SHIFT 0x0
1685 #define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR_MASK 0x7ffff
1686 #define ACP_SCRATCH_REG_BASE_ADDR__SCRATCH_REG_BASE_ADDR__SHIFT 0x0
1687 #define CC_ACP_EFUSE__DSP0_DISABLE_MASK 0x2
1688 #define CC_ACP_EFUSE__DSP0_DISABLE__SHIFT 0x1
1689 #define CC_ACP_EFUSE__DSP1_DISABLE_MASK 0x4
1690 #define CC_ACP_EFUSE__DSP1_DISABLE__SHIFT 0x2
1691 #define CC_ACP_EFUSE__DSP2_DISABLE_MASK 0x8
1692 #define CC_ACP_EFUSE__DSP2_DISABLE__SHIFT 0x3
1693 #define CC_ACP_EFUSE__ACP_DISABLE_MASK 0x10
1694 #define CC_ACP_EFUSE__ACP_DISABLE__SHIFT 0x4
1695 #define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF_MASK 0x1
1696 #define ACP_PGFSM_RETAIN_REG__ACP_P1_ON_OFF__SHIFT 0x0
1697 #define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF_MASK 0x2
1698 #define ACP_PGFSM_RETAIN_REG__ACP_P2_ON_OFF__SHIFT 0x1
1699 #define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF_MASK 0x4
1700 #define ACP_PGFSM_RETAIN_REG__ACP_DSP0_ON_OFF__SHIFT 0x2
1701 #define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF_MASK 0x8
1702 #define ACP_PGFSM_RETAIN_REG__ACP_DSP1_ON_OFF__SHIFT 0x3
1703 #define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF_MASK 0x10
1704 #define ACP_PGFSM_RETAIN_REG__ACP_DSP2_ON_OFF__SHIFT 0x4
1705 #define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF_MASK 0x20
1706 #define ACP_PGFSM_RETAIN_REG__ACP_AZ_ON_OFF__SHIFT 0x5
1707 #define ACP_PGFSM_CONFIG_REG__FSM_ADDR_MASK 0xff
1708 #define ACP_PGFSM_CONFIG_REG__FSM_ADDR__SHIFT 0x0
1709 #define ACP_PGFSM_CONFIG_REG__Power_Down_MASK 0x100
1710 #define ACP_PGFSM_CONFIG_REG__Power_Down__SHIFT 0x8
1711 #define ACP_PGFSM_CONFIG_REG__Power_Up_MASK 0x200
1712 #define ACP_PGFSM_CONFIG_REG__Power_Up__SHIFT 0x9
1713 #define ACP_PGFSM_CONFIG_REG__P1_Select_MASK 0x400
1714 #define ACP_PGFSM_CONFIG_REG__P1_Select__SHIFT 0xa
1715 #define ACP_PGFSM_CONFIG_REG__P2_Select_MASK 0x800
1716 #define ACP_PGFSM_CONFIG_REG__P2_Select__SHIFT 0xb
1717 #define ACP_PGFSM_CONFIG_REG__Wr_MASK 0x1000
1718 #define ACP_PGFSM_CONFIG_REG__Wr__SHIFT 0xc
1719 #define ACP_PGFSM_CONFIG_REG__Rd_MASK 0x2000
1720 #define ACP_PGFSM_CONFIG_REG__Rd__SHIFT 0xd
1721 #define ACP_PGFSM_CONFIG_REG__RdData_Reset_MASK 0x4000
1722 #define ACP_PGFSM_CONFIG_REG__RdData_Reset__SHIFT 0xe
1723 #define ACP_PGFSM_CONFIG_REG__Short_Format_MASK 0x8000
1724 #define ACP_PGFSM_CONFIG_REG__Short_Format__SHIFT 0xf
1725 #define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG_MASK 0x3ff0000
1726 #define ACP_PGFSM_CONFIG_REG__BPM_CG_MG_FGCG__SHIFT 0x10
1727 #define ACP_PGFSM_CONFIG_REG__SRBM_override_MASK 0x4000000
1728 #define ACP_PGFSM_CONFIG_REG__SRBM_override__SHIFT 0x1a
1729 #define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr_MASK 0x8000000
1730 #define ACP_PGFSM_CONFIG_REG__Rsvd_BPM_Addr__SHIFT 0x1b
1731 #define ACP_PGFSM_CONFIG_REG__REG_ADDR_MASK 0xf0000000
1732 #define ACP_PGFSM_CONFIG_REG__REG_ADDR__SHIFT 0x1c
1733 #define ACP_PGFSM_WRITE_REG__Write_value_MASK 0xffffffff
1734 #define ACP_PGFSM_WRITE_REG__Write_value__SHIFT 0x0
1735 #define ACP_PGFSM_READ_REG_0__Read_value_MASK 0xffffff
1736 #define ACP_PGFSM_READ_REG_0__Read_value__SHIFT 0x0
1737 #define ACP_PGFSM_READ_REG_1__Read_value_MASK 0xffffff
1738 #define ACP_PGFSM_READ_REG_1__Read_value__SHIFT 0x0
1739 #define ACP_PGFSM_READ_REG_2__Read_value_MASK 0xffffff
1740 #define ACP_PGFSM_READ_REG_2__Read_value__SHIFT 0x0
1741 #define ACP_PGFSM_READ_REG_3__Read_value_MASK 0xffffff
1742 #define ACP_PGFSM_READ_REG_3__Read_value__SHIFT 0x0
1743 #define ACP_PGFSM_READ_REG_4__Read_value_MASK 0xffffff
1744 #define ACP_PGFSM_READ_REG_4__Read_value__SHIFT 0x0
1745 #define ACP_PGFSM_READ_REG_5__Read_value_MASK 0xffffff
1746 #define ACP_PGFSM_READ_REG_5__Read_value__SHIFT 0x0
1747 #define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS_MASK 0x1
1748 #define ACP_IP_PGFSM_ENABLE__ACP_IP_ACCESS__SHIFT 0x0
1749 #define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG_MASK 0x3
1750 #define ACP_I2S_PIN_CONFIG__ACP_I2S_PIN_CONFIG__SHIFT 0x0
1751 #define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT_MASK 0x1
1752 #define ACP_AZALIA_I2S_SELECT__AZ_I2S_SELECT__SHIFT 0x0
1753 #define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package_MASK 0x1
1754 #define ACP_CHIP_PKG_FOR_PAD_ISOLATION__external_fch_package__SHIFT 0x0
1755 #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable_MASK 0x7ff
1756 #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pullup_disable__SHIFT 0x0
1757 #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable_MASK 0x7ff0000
1758 #define ACP_AUDIO_PAD_PULLUP_PULLDOWN_CTRL__ACP_AUDIO_PAD_pulldown_enable__SHIFT 0x10
1759 #define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL_MASK 0x1
1760 #define ACP_BT_UART_PAD_SEL__ACP_BT_UART_PAD_SEL__SHIFT 0x0
1761 #define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG_MASK 0xffffffff
1762 #define ACP_SCRATCH_REG_0__ACP_SCRATCH_REG__SHIFT 0x0
1763 #define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG_MASK 0xffffffff
1764 #define ACP_SCRATCH_REG_1__ACP_SCRATCH_REG__SHIFT 0x0
1765 #define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG_MASK 0xffffffff
1766 #define ACP_SCRATCH_REG_2__ACP_SCRATCH_REG__SHIFT 0x0
1767 #define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG_MASK 0xffffffff
1768 #define ACP_SCRATCH_REG_3__ACP_SCRATCH_REG__SHIFT 0x0
1769 #define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG_MASK 0xffffffff
1770 #define ACP_SCRATCH_REG_4__ACP_SCRATCH_REG__SHIFT 0x0
1771 #define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG_MASK 0xffffffff
1772 #define ACP_SCRATCH_REG_5__ACP_SCRATCH_REG__SHIFT 0x0
1773 #define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG_MASK 0xffffffff
1774 #define ACP_SCRATCH_REG_6__ACP_SCRATCH_REG__SHIFT 0x0
1775 #define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG_MASK 0xffffffff
1776 #define ACP_SCRATCH_REG_7__ACP_SCRATCH_REG__SHIFT 0x0
1777 #define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG_MASK 0xffffffff
1778 #define ACP_SCRATCH_REG_8__ACP_SCRATCH_REG__SHIFT 0x0
1779 #define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG_MASK 0xffffffff
1780 #define ACP_SCRATCH_REG_9__ACP_SCRATCH_REG__SHIFT 0x0
1781 #define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG_MASK 0xffffffff
1782 #define ACP_SCRATCH_REG_10__ACP_SCRATCH_REG__SHIFT 0x0
1783 #define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG_MASK 0xffffffff
1784 #define ACP_SCRATCH_REG_11__ACP_SCRATCH_REG__SHIFT 0x0
1785 #define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG_MASK 0xffffffff
1786 #define ACP_SCRATCH_REG_12__ACP_SCRATCH_REG__SHIFT 0x0
1787 #define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG_MASK 0xffffffff
1788 #define ACP_SCRATCH_REG_13__ACP_SCRATCH_REG__SHIFT 0x0
1789 #define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG_MASK 0xffffffff
1790 #define ACP_SCRATCH_REG_14__ACP_SCRATCH_REG__SHIFT 0x0
1791 #define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG_MASK 0xffffffff
1792 #define ACP_SCRATCH_REG_15__ACP_SCRATCH_REG__SHIFT 0x0
1793 #define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG_MASK 0xffffffff
1794 #define ACP_SCRATCH_REG_16__ACP_SCRATCH_REG__SHIFT 0x0
1795 #define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG_MASK 0xffffffff
1796 #define ACP_SCRATCH_REG_17__ACP_SCRATCH_REG__SHIFT 0x0
1797 #define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG_MASK 0xffffffff
1798 #define ACP_SCRATCH_REG_18__ACP_SCRATCH_REG__SHIFT 0x0
1799 #define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG_MASK 0xffffffff
1800 #define ACP_SCRATCH_REG_19__ACP_SCRATCH_REG__SHIFT 0x0
1801 #define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG_MASK 0xffffffff
1802 #define ACP_SCRATCH_REG_20__ACP_SCRATCH_REG__SHIFT 0x0
1803 #define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG_MASK 0xffffffff
1804 #define ACP_SCRATCH_REG_21__ACP_SCRATCH_REG__SHIFT 0x0
1805 #define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG_MASK 0xffffffff
1806 #define ACP_SCRATCH_REG_22__ACP_SCRATCH_REG__SHIFT 0x0
1807 #define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG_MASK 0xffffffff
1808 #define ACP_SCRATCH_REG_23__ACP_SCRATCH_REG__SHIFT 0x0
1809 #define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG_MASK 0xffffffff
1810 #define ACP_SCRATCH_REG_24__ACP_SCRATCH_REG__SHIFT 0x0
1811 #define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG_MASK 0xffffffff
1812 #define ACP_SCRATCH_REG_25__ACP_SCRATCH_REG__SHIFT 0x0
1813 #define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG_MASK 0xffffffff
1814 #define ACP_SCRATCH_REG_26__ACP_SCRATCH_REG__SHIFT 0x0
1815 #define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG_MASK 0xffffffff
1816 #define ACP_SCRATCH_REG_27__ACP_SCRATCH_REG__SHIFT 0x0
1817 #define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG_MASK 0xffffffff
1818 #define ACP_SCRATCH_REG_28__ACP_SCRATCH_REG__SHIFT 0x0
1819 #define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG_MASK 0xffffffff
1820 #define ACP_SCRATCH_REG_29__ACP_SCRATCH_REG__SHIFT 0x0
1821 #define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG_MASK 0xffffffff
1822 #define ACP_SCRATCH_REG_30__ACP_SCRATCH_REG__SHIFT 0x0
1823 #define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG_MASK 0xffffffff
1824 #define ACP_SCRATCH_REG_31__ACP_SCRATCH_REG__SHIFT 0x0
1825 #define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG_MASK 0xffffffff
1826 #define ACP_SCRATCH_REG_32__ACP_SCRATCH_REG__SHIFT 0x0
1827 #define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG_MASK 0xffffffff
1828 #define ACP_SCRATCH_REG_33__ACP_SCRATCH_REG__SHIFT 0x0
1829 #define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG_MASK 0xffffffff
1830 #define ACP_SCRATCH_REG_34__ACP_SCRATCH_REG__SHIFT 0x0
1831 #define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG_MASK 0xffffffff
1832 #define ACP_SCRATCH_REG_35__ACP_SCRATCH_REG__SHIFT 0x0
1833 #define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG_MASK 0xffffffff
1834 #define ACP_SCRATCH_REG_36__ACP_SCRATCH_REG__SHIFT 0x0
1835 #define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG_MASK 0xffffffff
1836 #define ACP_SCRATCH_REG_37__ACP_SCRATCH_REG__SHIFT 0x0
1837 #define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG_MASK 0xffffffff
1838 #define ACP_SCRATCH_REG_38__ACP_SCRATCH_REG__SHIFT 0x0
1839 #define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG_MASK 0xffffffff
1840 #define ACP_SCRATCH_REG_39__ACP_SCRATCH_REG__SHIFT 0x0
1841 #define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG_MASK 0xffffffff
1842 #define ACP_SCRATCH_REG_40__ACP_SCRATCH_REG__SHIFT 0x0
1843 #define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG_MASK 0xffffffff
1844 #define ACP_SCRATCH_REG_41__ACP_SCRATCH_REG__SHIFT 0x0
1845 #define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG_MASK 0xffffffff
1846 #define ACP_SCRATCH_REG_42__ACP_SCRATCH_REG__SHIFT 0x0
1847 #define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG_MASK 0xffffffff
1848 #define ACP_SCRATCH_REG_43__ACP_SCRATCH_REG__SHIFT 0x0
1849 #define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG_MASK 0xffffffff
1850 #define ACP_SCRATCH_REG_44__ACP_SCRATCH_REG__SHIFT 0x0
1851 #define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG_MASK 0xffffffff
1852 #define ACP_SCRATCH_REG_45__ACP_SCRATCH_REG__SHIFT 0x0
1853 #define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG_MASK 0xffffffff
1854 #define ACP_SCRATCH_REG_46__ACP_SCRATCH_REG__SHIFT 0x0
1855 #define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG_MASK 0xffffffff
1856 #define ACP_SCRATCH_REG_47__ACP_SCRATCH_REG__SHIFT 0x0
1857 #define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable_MASK 0x1
1858 #define ACP_VOICE_WAKEUP_ENABLE__voice_wakeup_enable__SHIFT 0x0
1859 #define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status_MASK 0x1
1860 #define ACP_VOICE_WAKEUP_STATUS__voice_wakeup_status__SHIFT 0x0
1861 #define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold_MASK 0xffffffff
1862 #define I2S_VOICE_WAKEUP_LOWER_THRESHOLD__i2s_voice_wakeup_lower_threshold__SHIFT 0x0
1863 #define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold_MASK 0xffffffff
1864 #define I2S_VOICE_WAKEUP_HIGHER_THRESHOLD__i2s_voice_wakeup_higher_threshold__SHIFT 0x0
1865 #define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples_MASK 0xffff
1866 #define I2S_VOICE_WAKEUP_NO_OF_SAMPLES__i2s_voice_wakeup_no_of_samples__SHIFT 0x0
1867 #define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks_MASK 0xffff
1868 #define I2S_VOICE_WAKEUP_NO_OF_PEAKS__i2s_voice_wakeup_no_of_peaks__SHIFT 0x0
1869 #define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks_MASK 0xffffffff
1870 #define I2S_VOICE_WAKEUP_DURATION_OF_N_PEAKS__i2s_voice_wakeup_duration_of_n_peaks__SHIFT 0x0
1871 #define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en_MASK 0x1
1872 #define I2S_VOICE_WAKEUP_BITCLK_TOGGLE_DETECTION__i2s_voice_wakeup_bitclk_toggle_wakeup_en__SHIFT 0x0
1873 #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req_MASK 0x1
1874 #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_req__SHIFT 0x0
1875 #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack_MASK 0x2
1876 #define I2S_VOICE_WAKEUP_DATA_PATH_SWITCH__i2s_voice_wakeup_data_path_switch_ack__SHIFT 0x1
1877 #define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer_MASK 0xffffffff
1878 #define I2S_VOICE_WAKEUP_DATA_POINTER__i2s_voice_wakeup_data_pointer__SHIFT 0x0
1879 #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid_MASK 0x1
1880 #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_valid__SHIFT 0x0
1881 #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match_MASK 0x2
1882 #define I2S_VOICE_WAKEUP_AUTH_MATCH__i2s_voice_wakeup_authentication_match__SHIFT 0x1
1883 #define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap_MASK 0x1
1884 #define I2S_VOICE_WAKEUP_8KB_WRAP__i2s_voice_wakeup_8kb_wrap__SHIFT 0x0
1885 #define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high_MASK 0xffffffff
1886 #define ACP_I2S_RECEIVED_BYTE_CNT_HIGH__i2s_mic_rx_byte_cnt_high__SHIFT 0x0
1887 #define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low_MASK 0xffffffff
1888 #define ACP_I2S_RECEIVED_BYTE_CNT_LOW__i2s_mic_rx_byte_cnt_low__SHIFT 0x0
1889 #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high_MASK 0xffffffff
1890 #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_HIGH__i2s_micsp_tx_byte_cnt_high__SHIFT 0x0
1891 #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low_MASK 0xffffffff
1892 #define ACP_I2S_MICSP_TRANSMIT_BYTE_CNT_LOW__i2s_micsp_tx_byte_cnt_low__SHIFT 0x0
1893 #define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML_MASK 0xffffffff
1894 #define ACP_MEM_SHUT_DOWN_REQ_LO__ACP_ShutDownReq_RAML__SHIFT 0x0
1895 #define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH_MASK 0xffff
1896 #define ACP_MEM_SHUT_DOWN_REQ_HI__ACP_ShutDownReq_RAMH__SHIFT 0x0
1897 #define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML_MASK 0xffffffff
1898 #define ACP_MEM_SHUT_DOWN_STS_LO__ACP_ShutDownSts_RAML__SHIFT 0x0
1899 #define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH_MASK 0xffff
1900 #define ACP_MEM_SHUT_DOWN_STS_HI__ACP_ShutDownSts_RAMH__SHIFT 0x0
1901 #define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML_MASK 0xffffffff
1902 #define ACP_MEM_DEEP_SLEEP_REQ_LO__ACP_DeepSleepReq_RAML__SHIFT 0x0
1903 #define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH_MASK 0xffff
1904 #define ACP_MEM_DEEP_SLEEP_REQ_HI__ACP_DeepSleepReq_RAMH__SHIFT 0x0
1905 #define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML_MASK 0xffffffff
1906 #define ACP_MEM_DEEP_SLEEP_STS_LO__ACP_DeepSleepSts_RAML__SHIFT 0x0
1907 #define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH_MASK 0xffff
1908 #define ACP_MEM_DEEP_SLEEP_STS_HI__ACP_DeepSleepSts_RAMH__SHIFT 0x0
1909 #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo_MASK 0xffffffff
1910 #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_LO__acp_mem_wakeup_from_shut_down_lo__SHIFT 0x0
1911 #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi_MASK 0xffff
1912 #define ACP_MEM_WAKEUP_FROM_SHUT_DOWN_HI__acp_mem_wakeup_from_shut_down_hi__SHIFT 0x0
1913 #define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo_MASK 0xffffffff
1914 #define ACP_MEM_WAKEUP_FROM_SLEEP_LO__acp_mem_wakeup_from_sleep_lo__SHIFT 0x0
1915 #define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi_MASK 0xffff
1916 #define ACP_MEM_WAKEUP_FROM_SLEEP_HI__acp_mem_wakeup_from_sleep_hi__SHIFT 0x0
1917 #define ACP_I2SSP_IER__I2SSP_IEN_MASK 0x1
1918 #define ACP_I2SSP_IER__I2SSP_IEN__SHIFT 0x0
1919 #define ACP_I2SSP_IRER__I2SSP_RXEN_MASK 0x1
1920 #define ACP_I2SSP_IRER__I2SSP_RXEN__SHIFT 0x0
1921 #define ACP_I2SSP_ITER__I2SSP_TXEN_MASK 0x1
1922 #define ACP_I2SSP_ITER__I2SSP_TXEN__SHIFT 0x0
1923 #define ACP_I2SSP_CER__I2SSP_CLKEN_MASK 0x1
1924 #define ACP_I2SSP_CER__I2SSP_CLKEN__SHIFT 0x0
1925 #define ACP_I2SSP_CCR__I2SSP_SCLKG_MASK 0x7
1926 #define ACP_I2SSP_CCR__I2SSP_SCLKG__SHIFT 0x0
1927 #define ACP_I2SSP_CCR__I2SSP_WSS_MASK 0x18
1928 #define ACP_I2SSP_CCR__I2SSP_WSS__SHIFT 0x3
1929 #define ACP_I2SSP_RXFFR__I2SSP_RXFFR_MASK 0x1
1930 #define ACP_I2SSP_RXFFR__I2SSP_RXFFR__SHIFT 0x0
1931 #define ACP_I2SSP_TXFFR__I2SSP_TXFFR_MASK 0x1
1932 #define ACP_I2SSP_TXFFR__I2SSP_TXFFR__SHIFT 0x0
1933 #define ACP_I2SSP_LRBR0__I2SSP_LRBR0_MASK 0xffffffff
1934 #define ACP_I2SSP_LRBR0__I2SSP_LRBR0__SHIFT 0x0
1935 #define ACP_I2SSP_RRBR0__I2SSP_RRBR0_MASK 0xffffffff
1936 #define ACP_I2SSP_RRBR0__I2SSP_RRBR0__SHIFT 0x0
1937 #define ACP_I2SSP_RER0__I2SSP_RXCHEN0_MASK 0x1
1938 #define ACP_I2SSP_RER0__I2SSP_RXCHEN0__SHIFT 0x0
1939 #define ACP_I2SSP_TER0__I2SSP_TXCHEN0_MASK 0x1
1940 #define ACP_I2SSP_TER0__I2SSP_TXCHEN0__SHIFT 0x0
1941 #define ACP_I2SSP_RCR0__I2SSP_WLEN_MASK 0x7
1942 #define ACP_I2SSP_RCR0__I2SSP_WLEN__SHIFT 0x0
1943 #define ACP_I2SSP_TCR0__I2SSP_WLEN_MASK 0x7
1944 #define ACP_I2SSP_TCR0__I2SSP_WLEN__SHIFT 0x0
1945 #define ACP_I2SSP_ISR0__I2SSP_RXDA_MASK 0x1
1946 #define ACP_I2SSP_ISR0__I2SSP_RXDA__SHIFT 0x0
1947 #define ACP_I2SSP_ISR0__I2SSP_RXFO_MASK 0x2
1948 #define ACP_I2SSP_ISR0__I2SSP_RXFO__SHIFT 0x1
1949 #define ACP_I2SSP_ISR0__I2SSP_TXFE_MASK 0x10
1950 #define ACP_I2SSP_ISR0__I2SSP_TXFE__SHIFT 0x4
1951 #define ACP_I2SSP_ISR0__I2SSP_TXFO_MASK 0x20
1952 #define ACP_I2SSP_ISR0__I2SSP_TXFO__SHIFT 0x5
1953 #define ACP_I2SSP_IMR0__I2SSP_RXDAM_MASK 0x1
1954 #define ACP_I2SSP_IMR0__I2SSP_RXDAM__SHIFT 0x0
1955 #define ACP_I2SSP_IMR0__I2SSP_RXFOM_MASK 0x2
1956 #define ACP_I2SSP_IMR0__I2SSP_RXFOM__SHIFT 0x1
1957 #define ACP_I2SSP_IMR0__I2SSP_TXFEM_MASK 0x10
1958 #define ACP_I2SSP_IMR0__I2SSP_TXFEM__SHIFT 0x4
1959 #define ACP_I2SSP_IMR0__I2SSP_TXFOM_MASK 0x20
1960 #define ACP_I2SSP_IMR0__I2SSP_TXFOM__SHIFT 0x5
1961 #define ACP_I2SSP_ROR0__I2SSP_RXCHO_MASK 0x1
1962 #define ACP_I2SSP_ROR0__I2SSP_RXCHO__SHIFT 0x0
1963 #define ACP_I2SSP_TOR0__I2SSP_TXCHO_MASK 0x1
1964 #define ACP_I2SSP_TOR0__I2SSP_TXCHO__SHIFT 0x0
1965 #define ACP_I2SSP_RFCR0__I2SSP_RXCHDT_MASK 0xf
1966 #define ACP_I2SSP_RFCR0__I2SSP_RXCHDT__SHIFT 0x0
1967 #define ACP_I2SSP_TFCR0__I2SSP_TXCHET_MASK 0xf
1968 #define ACP_I2SSP_TFCR0__I2SSP_TXCHET__SHIFT 0x0
1969 #define ACP_I2SSP_RFF0__I2SSP_RXCHFR_MASK 0x1
1970 #define ACP_I2SSP_RFF0__I2SSP_RXCHFR__SHIFT 0x0
1971 #define ACP_I2SSP_TFF0__I2SSP_TXCHFR_MASK 0x1
1972 #define ACP_I2SSP_TFF0__I2SSP_TXCHFR__SHIFT 0x0
1973 #define ACP_I2SSP_RXDMA__I2SSP_RXDMA_MASK 0xffffffff
1974 #define ACP_I2SSP_RXDMA__I2SSP_RXDMA__SHIFT 0x0
1975 #define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA_MASK 0x1
1976 #define ACP_I2SSP_RRXDMA__I2SSP_RRXDMA__SHIFT 0x0
1977 #define ACP_I2SSP_TXDMA__I2SSP_TXDMA_MASK 0xffffffff
1978 #define ACP_I2SSP_TXDMA__I2SSP_TXDMA__SHIFT 0x0
1979 #define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA_MASK 0x1
1980 #define ACP_I2SSP_RTXDMA__I2SSP_RTXDMA__SHIFT 0x0
1981 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0_MASK 0x7
1982 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_0__SHIFT 0x0
1983 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1_MASK 0x38
1984 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_1__SHIFT 0x3
1985 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2_MASK 0x380
1986 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_2__SHIFT 0x7
1987 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3_MASK 0x1c00
1988 #define ACP_I2SSP_COMP_PARAM_2__I2SSP_RX_WPRDSIZE_3__SHIFT 0xa
1989 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH_MASK 0x3
1990 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_APB_DATA_WIDTH__SHIFT 0x0
1991 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL_MASK 0xc
1992 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2
1993 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN_MASK 0x10
1994 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_MODE_EN__SHIFT 0x4
1995 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK_MASK 0x20
1996 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TRANSMITTER_BLOCK__SHIFT 0x5
1997 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK_MASK 0x40
1998 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RECEIVER_BLOCK__SHIFT 0x6
1999 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES_MASK 0x180
2000 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_RX_CHANNLES__SHIFT 0x7
2001 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES_MASK 0x600
2002 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_CHANNLES__SHIFT 0x9
2003 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0_MASK 0x70000
2004 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_0__SHIFT 0x10
2005 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1_MASK 0x380000
2006 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_1__SHIFT 0x13
2007 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2_MASK 0x1c00000
2008 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_2__SHIFT 0x16
2009 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3_MASK 0xe000000
2010 #define ACP_I2SSP_COMP_PARAM_1__I2SSP_TX_WORDSIZE_3__SHIFT 0x19
2011 #define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH_MASK 0xffffffff
2012 #define ACP_I2SSP_COMP_VERSION__I2SSP_APB_DATA_WIDTH__SHIFT 0x0
2013 #define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE_MASK 0xffffffff
2014 #define ACP_I2SSP_COMP_TYPE__I2SSP_COMP_TYPE__SHIFT 0x0
2015 #define ACP_I2SMICSP_IER__I2SMICSP_IEN_MASK 0x1
2016 #define ACP_I2SMICSP_IER__I2SMICSP_IEN__SHIFT 0x0
2017 #define ACP_I2SMICSP_IRER__I2SMICSP_RXEN_MASK 0x1
2018 #define ACP_I2SMICSP_IRER__I2SMICSP_RXEN__SHIFT 0x0
2019 #define ACP_I2SMICSP_ITER__I2SMICSP_TXEN_MASK 0x1
2020 #define ACP_I2SMICSP_ITER__I2SMICSP_TXEN__SHIFT 0x0
2021 #define ACP_I2SMICSP_CER__I2SMICSP_CLKEN_MASK 0x1
2022 #define ACP_I2SMICSP_CER__I2SMICSP_CLKEN__SHIFT 0x0
2023 #define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG_MASK 0x7
2024 #define ACP_I2SMICSP_CCR__I2SMICSP_SCLKG__SHIFT 0x0
2025 #define ACP_I2SMICSP_CCR__I2SMICSP_WSS_MASK 0x18
2026 #define ACP_I2SMICSP_CCR__I2SMICSP_WSS__SHIFT 0x3
2027 #define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR_MASK 0x1
2028 #define ACP_I2SMICSP_RXFFR__I2SMICSP_RXFFR__SHIFT 0x0
2029 #define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR_MASK 0x1
2030 #define ACP_I2SMICSP_TXFFR__I2SMICSP_TXFFR__SHIFT 0x0
2031 #define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0_MASK 0xffffffff
2032 #define ACP_I2SMICSP_LRBR0__I2SMICSP_LRBR0__SHIFT 0x0
2033 #define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0_MASK 0xffffffff
2034 #define ACP_I2SMICSP_RRBR0__I2SMICSP_RRBR0__SHIFT 0x0
2035 #define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0_MASK 0x1
2036 #define ACP_I2SMICSP_RER0__I2SMICSP_RXCHEN0__SHIFT 0x0
2037 #define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0_MASK 0x1
2038 #define ACP_I2SMICSP_TER0__I2SMICSP_TXCHEN0__SHIFT 0x0
2039 #define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN_MASK 0x7
2040 #define ACP_I2SMICSP_RCR0__I2SMICSP_WLEN__SHIFT 0x0
2041 #define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN_MASK 0x7
2042 #define ACP_I2SMICSP_TCR0__I2SMICSP_WLEN__SHIFT 0x0
2043 #define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA_MASK 0x1
2044 #define ACP_I2SMICSP_ISR0__I2SMICSP_RXDA__SHIFT 0x0
2045 #define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO_MASK 0x2
2046 #define ACP_I2SMICSP_ISR0__I2SMICSP_RXFO__SHIFT 0x1
2047 #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE_MASK 0x10
2048 #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFE__SHIFT 0x4
2049 #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO_MASK 0x20
2050 #define ACP_I2SMICSP_ISR0__I2SMICSP_TXFO__SHIFT 0x5
2051 #define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM_MASK 0x1
2052 #define ACP_I2SMICSP_IMR0__I2SMICSP_RXDAM__SHIFT 0x0
2053 #define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM_MASK 0x2
2054 #define ACP_I2SMICSP_IMR0__I2SMICSP_RXFOM__SHIFT 0x1
2055 #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM_MASK 0x10
2056 #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFEM__SHIFT 0x4
2057 #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM_MASK 0x20
2058 #define ACP_I2SMICSP_IMR0__I2SMICSP_TXFOM__SHIFT 0x5
2059 #define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO_MASK 0x1
2060 #define ACP_I2SMICSP_ROR0__I2SMICSP_RXCHO__SHIFT 0x0
2061 #define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO_MASK 0x1
2062 #define ACP_I2SMICSP_TOR0__I2SMICSP_TXCHO__SHIFT 0x0
2063 #define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT_MASK 0xf
2064 #define ACP_I2SMICSP_RFCR0__I2SMICSP_RXCHDT__SHIFT 0x0
2065 #define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET_MASK 0xf
2066 #define ACP_I2SMICSP_TFCR0__I2SMICSP_TXCHET__SHIFT 0x0
2067 #define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR_MASK 0x1
2068 #define ACP_I2SMICSP_RFF0__I2SMICSP_RXCHFR__SHIFT 0x0
2069 #define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR_MASK 0x1
2070 #define ACP_I2SMICSP_TFF0__I2SMICSP_TXCHFR__SHIFT 0x0
2071 #define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1_MASK 0xffffffff
2072 #define ACP_I2SMICSP_LRBR1__I2SMICSP_LRBR1__SHIFT 0x0
2073 #define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1_MASK 0xffffffff
2074 #define ACP_I2SMICSP_RRBR1__I2SMICSP_RRBR1__SHIFT 0x0
2075 #define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1_MASK 0x1
2076 #define ACP_I2SMICSP_RER1__I2SMICSP_RXCHEN1__SHIFT 0x0
2077 #define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1_MASK 0x1
2078 #define ACP_I2SMICSP_TER1__I2SMICSP_TXCHEN1__SHIFT 0x0
2079 #define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN_MASK 0x7
2080 #define ACP_I2SMICSP_RCR1__I2SMICSP_WLEN__SHIFT 0x0
2081 #define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN_MASK 0x7
2082 #define ACP_I2SMICSP_TCR1__I2SMICSP_WLEN__SHIFT 0x0
2083 #define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA_MASK 0x1
2084 #define ACP_I2SMICSP_ISR1__I2SMICSP_RXDA__SHIFT 0x0
2085 #define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO_MASK 0x2
2086 #define ACP_I2SMICSP_ISR1__I2SMICSP_RXFO__SHIFT 0x1
2087 #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE_MASK 0x10
2088 #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFE__SHIFT 0x4
2089 #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO_MASK 0x20
2090 #define ACP_I2SMICSP_ISR1__I2SMICSP_TXFO__SHIFT 0x5
2091 #define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK 0x1
2092 #define ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM__SHIFT 0x0
2093 #define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK 0x2
2094 #define ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM__SHIFT 0x1
2095 #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM_MASK 0x10
2096 #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFEM__SHIFT 0x4
2097 #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM_MASK 0x20
2098 #define ACP_I2SMICSP_IMR1__I2SMICSP_TXFOM__SHIFT 0x5
2099 #define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO_MASK 0x1
2100 #define ACP_I2SMICSP_ROR1__I2SMICSP_RXCHO__SHIFT 0x0
2101 #define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO_MASK 0x1
2102 #define ACP_I2SMICSP_TOR1__I2SMICSP_TXCHO__SHIFT 0x0
2103 #define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT_MASK 0xf
2104 #define ACP_I2SMICSP_RFCR1__I2SMICSP_RXCHDT__SHIFT 0x0
2105 #define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET_MASK 0xf
2106 #define ACP_I2SMICSP_TFCR1__I2SMICSP_TXCHET__SHIFT 0x0
2107 #define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR_MASK 0x1
2108 #define ACP_I2SMICSP_RFF1__I2SMICSP_RXCHFR__SHIFT 0x0
2109 #define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR_MASK 0x1
2110 #define ACP_I2SMICSP_TFF1__I2SMICSP_TXCHFR__SHIFT 0x0
2111 #define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA_MASK 0xffffffff
2112 #define ACP_I2SMICSP_RXDMA__I2SMICSP_RXDMA__SHIFT 0x0
2113 #define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA_MASK 0x1
2114 #define ACP_I2SMICSP_RRXDMA__I2SMICSP_RRXDMA__SHIFT 0x0
2115 #define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA_MASK 0xffffffff
2116 #define ACP_I2SMICSP_TXDMA__I2SMICSP_TXDMA__SHIFT 0x0
2117 #define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA_MASK 0x1
2118 #define ACP_I2SMICSP_RTXDMA__I2SMICSP_RTXDMA__SHIFT 0x0
2119 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0_MASK 0x7
2120 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_0__SHIFT 0x0
2121 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1_MASK 0x38
2122 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_1__SHIFT 0x3
2123 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2_MASK 0x380
2124 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_2__SHIFT 0x7
2125 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3_MASK 0x1c00
2126 #define ACP_I2SMICSP_COMP_PARAM_2__I2SMICSP_RX_WPRDSIZE_3__SHIFT 0xa
2127 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH_MASK 0x3
2128 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0
2129 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL_MASK 0xc
2130 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_FIFO_DEPTH_GLOBAL__SHIFT 0x2
2131 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN_MASK 0x10
2132 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_MODE_EN__SHIFT 0x4
2133 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK_MASK 0x20
2134 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TRANSMITTER_BLOCK__SHIFT 0x5
2135 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK_MASK 0x40
2136 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RECEIVER_BLOCK__SHIFT 0x6
2137 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES_MASK 0x180
2138 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_RX_CHANNLES__SHIFT 0x7
2139 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES_MASK 0x600
2140 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_CHANNLES__SHIFT 0x9
2141 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0_MASK 0x70000
2142 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_0__SHIFT 0x10
2143 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1_MASK 0x380000
2144 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_1__SHIFT 0x13
2145 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2_MASK 0x1c00000
2146 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_2__SHIFT 0x16
2147 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3_MASK 0xe000000
2148 #define ACP_I2SMICSP_COMP_PARAM_1__I2SMICSP_TX_WORDSIZE_3__SHIFT 0x19
2149 #define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH_MASK 0xffffffff
2150 #define ACP_I2SMICSP_COMP_VERSION__I2SMICSP_APB_DATA_WIDTH__SHIFT 0x0
2151 #define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE_MASK 0xffffffff
2152 #define ACP_I2SMICSP_COMP_TYPE__I2SMICSP_COMP_TYPE__SHIFT 0x0
2153 #define ACP_I2SBT_IER__I2SBT_IEN_MASK 0x1
2154 #define ACP_I2SBT_IER__I2SBT_IEN__SHIFT 0x0
2155 #define ACP_I2SBT_IRER__I2SBT_RXEN_MASK 0x1
2156 #define ACP_I2SBT_IRER__I2SBT_RXEN__SHIFT 0x0
2157 #define ACP_I2SBT_ITER__I2SBT_TXEN_MASK 0x1
2158 #define ACP_I2SBT_ITER__I2SBT_TXEN__SHIFT 0x0
2159 #define ACP_I2SBT_CER__I2SBT_CLKEN_MASK 0x1
2160 #define ACP_I2SBT_CER__I2SBT_CLKEN__SHIFT 0x0
2161 #define ACP_I2SBT_CCR__I2SBT_SCLKG_MASK 0x7
2162 #define ACP_I2SBT_CCR__I2SBT_SCLKG__SHIFT 0x0
2163 #define ACP_I2SBT_CCR__I2SBT_WSS_MASK 0x18
2164 #define ACP_I2SBT_CCR__I2SBT_WSS__SHIFT 0x3
2165 #define ACP_I2SBT_RXFFR__I2SBT_RXFFR_MASK 0x1
2166 #define ACP_I2SBT_RXFFR__I2SBT_RXFFR__SHIFT 0x0
2167 #define ACP_I2SBT_TXFFR__I2SBT_TXFFR_MASK 0x1
2168 #define ACP_I2SBT_TXFFR__I2SBT_TXFFR__SHIFT 0x0
2169 #define ACP_I2SBT_LRBR0__I2SBT_LRBR0_MASK 0xffffffff
2170 #define ACP_I2SBT_LRBR0__I2SBT_LRBR0__SHIFT 0x0
2171 #define ACP_I2SBT_RRBR0__I2SBT_RRBR0_MASK 0xffffffff
2172 #define ACP_I2SBT_RRBR0__I2SBT_RRBR0__SHIFT 0x0
2173 #define ACP_I2SBT_RER0__I2SBT_RXCHEN0_MASK 0x1
2174 #define ACP_I2SBT_RER0__I2SBT_RXCHEN0__SHIFT 0x0
2175 #define ACP_I2SBT_TER0__I2SBT_TXCHEN0_MASK 0x1
2176 #define ACP_I2SBT_TER0__I2SBT_TXCHEN0__SHIFT 0x0
2177 #define ACP_I2SBT_RCR0__I2SBT_WLEN_MASK 0x7
2178 #define ACP_I2SBT_RCR0__I2SBT_WLEN__SHIFT 0x0
2179 #define ACP_I2SBT_TCR0__I2SBT_WLEN_MASK 0x7
2180 #define ACP_I2SBT_TCR0__I2SBT_WLEN__SHIFT 0x0
2181 #define ACP_I2SBT_ISR0__I2SBT_RXDA_MASK 0x1
2182 #define ACP_I2SBT_ISR0__I2SBT_RXDA__SHIFT 0x0
2183 #define ACP_I2SBT_ISR0__I2SBT_RXFO_MASK 0x2
2184 #define ACP_I2SBT_ISR0__I2SBT_RXFO__SHIFT 0x1
2185 #define ACP_I2SBT_ISR0__I2SBT_TXFE_MASK 0x10
2186 #define ACP_I2SBT_ISR0__I2SBT_TXFE__SHIFT 0x4
2187 #define ACP_I2SBT_ISR0__I2SBT_TXFO_MASK 0x20
2188 #define ACP_I2SBT_ISR0__I2SBT_TXFO__SHIFT 0x5
2189 #define ACP_I2SBT_IMR0__I2SBT_RXDAM_MASK 0x1
2190 #define ACP_I2SBT_IMR0__I2SBT_RXDAM__SHIFT 0x0
2191 #define ACP_I2SBT_IMR0__I2SBT_RXFOM_MASK 0x2
2192 #define ACP_I2SBT_IMR0__I2SBT_RXFOM__SHIFT 0x1
2193 #define ACP_I2SBT_IMR0__I2SBT_TXFEM_MASK 0x10
2194 #define ACP_I2SBT_IMR0__I2SBT_TXFEM__SHIFT 0x4
2195 #define ACP_I2SBT_IMR0__I2SBT_TXFOM_MASK 0x20
2196 #define ACP_I2SBT_IMR0__I2SBT_TXFOM__SHIFT 0x5
2197 #define ACP_I2SBT_ROR0__I2SBT_RXCHO_MASK 0x1
2198 #define ACP_I2SBT_ROR0__I2SBT_RXCHO__SHIFT 0x0
2199 #define ACP_I2SBT_TOR0__I2SBT_TXCHO_MASK 0x1
2200 #define ACP_I2SBT_TOR0__I2SBT_TXCHO__SHIFT 0x0
2201 #define ACP_I2SBT_RFCR0__I2SBT_RXCHDT_MASK 0xf
2202 #define ACP_I2SBT_RFCR0__I2SBT_RXCHDT__SHIFT 0x0
2203 #define ACP_I2SBT_TFCR0__I2SBT_TXCHET_MASK 0xf
2204 #define ACP_I2SBT_TFCR0__I2SBT_TXCHET__SHIFT 0x0
2205 #define ACP_I2SBT_RFF0__I2SBT_RXCHFR_MASK 0x1
2206 #define ACP_I2SBT_RFF0__I2SBT_RXCHFR__SHIFT 0x0
2207 #define ACP_I2SBT_TFF0__I2SBT_TXCHFR_MASK 0x1
2208 #define ACP_I2SBT_TFF0__I2SBT_TXCHFR__SHIFT 0x0
2209 #define ACP_I2SBT_LRBR1__I2SBT_LRBR1_MASK 0xffffffff
2210 #define ACP_I2SBT_LRBR1__I2SBT_LRBR1__SHIFT 0x0
2211 #define ACP_I2SBT_RRBR1__I2SBT_RRBR1_MASK 0xffffffff
2212 #define ACP_I2SBT_RRBR1__I2SBT_RRBR1__SHIFT 0x0
2213 #define ACP_I2SBT_RER1__I2SBT_RXCHEN1_MASK 0x1
2214 #define ACP_I2SBT_RER1__I2SBT_RXCHEN1__SHIFT 0x0
2215 #define ACP_I2SBT_TER1__I2SBT_TXCHEN1_MASK 0x1
2216 #define ACP_I2SBT_TER1__I2SBT_TXCHEN1__SHIFT 0x0
2217 #define ACP_I2SBT_RCR1__I2SBT_WLEN_MASK 0x7
2218 #define ACP_I2SBT_RCR1__I2SBT_WLEN__SHIFT 0x0
2219 #define ACP_I2SBT_TCR1__I2SBT_WLEN_MASK 0x7
2220 #define ACP_I2SBT_TCR1__I2SBT_WLEN__SHIFT 0x0
2221 #define ACP_I2SBT_ISR1__I2SBT_RXDA_MASK 0x1
2222 #define ACP_I2SBT_ISR1__I2SBT_RXDA__SHIFT 0x0
2223 #define ACP_I2SBT_ISR1__I2SBT_RXFO_MASK 0x2
2224 #define ACP_I2SBT_ISR1__I2SBT_RXFO__SHIFT 0x1
2225 #define ACP_I2SBT_ISR1__I2SBT_TXFE_MASK 0x10
2226 #define ACP_I2SBT_ISR1__I2SBT_TXFE__SHIFT 0x4
2227 #define ACP_I2SBT_ISR1__I2SBT_TXFO_MASK 0x20
2228 #define ACP_I2SBT_ISR1__I2SBT_TXFO__SHIFT 0x5
2229 #define ACP_I2SBT_IMR1__I2SBT_RXDAM_MASK 0x1
2230 #define ACP_I2SBT_IMR1__I2SBT_RXDAM__SHIFT 0x0
2231 #define ACP_I2SBT_IMR1__I2SBT_RXFOM_MASK 0x2
2232 #define ACP_I2SBT_IMR1__I2SBT_RXFOM__SHIFT 0x1
2233 #define ACP_I2SBT_IMR1__I2SBT_TXFEM_MASK 0x10
2234 #define ACP_I2SBT_IMR1__I2SBT_TXFEM__SHIFT 0x4
2235 #define ACP_I2SBT_IMR1__I2SBT_TXFOM_MASK 0x20
2236 #define ACP_I2SBT_IMR1__I2SBT_TXFOM__SHIFT 0x5
2237 #define ACP_I2SBT_ROR1__I2SBT_RXCHO_MASK 0x1
2238 #define ACP_I2SBT_ROR1__I2SBT_RXCHO__SHIFT 0x0
2239 #define ACP_I2SBT_TOR1__I2SBT_TXCHO_MASK 0x1
2240 #define ACP_I2SBT_TOR1__I2SBT_TXCHO__SHIFT 0x0
2241 #define ACP_I2SBT_RFCR1__I2SBT_RXCHDT_MASK 0xf
2242 #define ACP_I2SBT_RFCR1__I2SBT_RXCHDT__SHIFT 0x0
2243 #define ACP_I2SBT_TFCR1__I2SBT_TXCHET_MASK 0xf
2244 #define ACP_I2SBT_TFCR1__I2SBT_TXCHET__SHIFT 0x0
2245 #define ACP_I2SBT_RFF1__I2SBT_RXCHFR_MASK 0x1
2246 #define ACP_I2SBT_RFF1__I2SBT_RXCHFR__SHIFT 0x0
2247 #define ACP_I2SBT_TFF1__I2SBT_TXCHFR_MASK 0x1
2248 #define ACP_I2SBT_TFF1__I2SBT_TXCHFR__SHIFT 0x0
2249 #define ACP_I2SBT_RXDMA__I2SBT_RXDMA_MASK 0xffffffff
2250 #define ACP_I2SBT_RXDMA__I2SBT_RXDMA__SHIFT 0x0
2251 #define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA_MASK 0x1
2252 #define ACP_I2SBT_RRXDMA__I2SBT_RRXDMA__SHIFT 0x0
2253 #define ACP_I2SBT_TXDMA__I2SBT_TXDMA_MASK 0xffffffff
2254 #define ACP_I2SBT_TXDMA__I2SBT_TXDMA__SHIFT 0x0
2255 #define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA_MASK 0x1
2256 #define ACP_I2SBT_RTXDMA__I2SBT_RTXDMA__SHIFT 0x0
2257 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0_MASK 0x7
2258 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_0__SHIFT 0x0
2259 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1_MASK 0x38
2260 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_1__SHIFT 0x3
2261 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2_MASK 0x380
2262 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_2__SHIFT 0x7
2263 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3_MASK 0x1c00
2264 #define ACP_I2SBT_COMP_PARAM_2__I2SBT_RX_WPRDSIZE_3__SHIFT 0xa
2265 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH_MASK 0x3
2266 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_APB_DATA_WIDTH__SHIFT 0x0
2267 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL_MASK 0xc
2268 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_FIFO_DEPTH_GLOBAL__SHIFT 0x2
2269 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN_MASK 0x10
2270 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_MODE_EN__SHIFT 0x4
2271 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK_MASK 0x20
2272 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TRANSMITTER_BLOCK__SHIFT 0x5
2273 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK_MASK 0x40
2274 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RECEIVER_BLOCK__SHIFT 0x6
2275 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES_MASK 0x180
2276 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_RX_CHANNLES__SHIFT 0x7
2277 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES_MASK 0x600
2278 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_CHANNLES__SHIFT 0x9
2279 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0_MASK 0x70000
2280 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_0__SHIFT 0x10
2281 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1_MASK 0x380000
2282 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_1__SHIFT 0x13
2283 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2_MASK 0x1c00000
2284 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_2__SHIFT 0x16
2285 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3_MASK 0xe000000
2286 #define ACP_I2SBT_COMP_PARAM_1__I2SBT_TX_WORDSIZE_3__SHIFT 0x19
2287 #define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH_MASK 0xffffffff
2288 #define ACP_I2SBT_COMP_VERSION__I2SBT_APB_DATA_WIDTH__SHIFT 0x0
2289 #define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE_MASK 0xffffffff
2290 #define ACP_I2SBT_COMP_TYPE__I2SBT_COMP_TYPE__SHIFT 0x0
2291 
2292 #endif /* ACP_2_2_SH_MASK_H */
2293