1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license. When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7  *
8  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9  */
10 
11 #ifndef _ACP_IP_OFFSET_HEADER
12 #define _ACP_IP_OFFSET_HEADER
13 
14 #define ACPAXI2AXI_ATU_CTRL                           0xC40
15 #define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5                0xC20
16 #define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5                0xC24
17 
18 #define ACP_PGFSM_CONTROL			0x141C
19 #define ACP_PGFSM_STATUS                        0x1420
20 #define ACP_SOFT_RESET                          0x1000
21 #define ACP_CONTROL                             0x1004
22 
23 #define ACP_EXTERNAL_INTR_REG_ADDR(adata, offset, ctrl) \
24 	(adata->acp_base + adata->rsrc->irq_reg_offset + offset + (ctrl * 0x04))
25 
26 #define ACP_EXTERNAL_INTR_ENB(adata) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x0, 0x0)
27 #define ACP_EXTERNAL_INTR_CNTL(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, 0x4, ctrl)
28 #define ACP_EXTERNAL_INTR_STAT(adata, ctrl) ACP_EXTERNAL_INTR_REG_ADDR(adata, \
29 	(0x4 + (adata->rsrc->no_of_ctrls * 0x04)), ctrl)
30 
31 /* Registers from ACP_AUDIO_BUFFERS block */
32 
33 #define ACP_I2S_RX_RINGBUFADDR                        0x2000
34 #define ACP_I2S_RX_RINGBUFSIZE                        0x2004
35 #define ACP_I2S_RX_LINKPOSITIONCNTR                   0x2008
36 #define ACP_I2S_RX_FIFOADDR                           0x200C
37 #define ACP_I2S_RX_FIFOSIZE                           0x2010
38 #define ACP_I2S_RX_DMA_SIZE                           0x2014
39 #define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH            0x2018
40 #define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW             0x201C
41 #define ACP_I2S_RX_INTR_WATERMARK_SIZE                0x2020
42 #define ACP_I2S_TX_RINGBUFADDR                        0x2024
43 #define ACP_I2S_TX_RINGBUFSIZE                        0x2028
44 #define ACP_I2S_TX_LINKPOSITIONCNTR                   0x202C
45 #define ACP_I2S_TX_FIFOADDR                           0x2030
46 #define ACP_I2S_TX_FIFOSIZE                           0x2034
47 #define ACP_I2S_TX_DMA_SIZE                           0x2038
48 #define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH            0x203C
49 #define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW             0x2040
50 #define ACP_I2S_TX_INTR_WATERMARK_SIZE                0x2044
51 #define ACP_BT_RX_RINGBUFADDR                         0x2048
52 #define ACP_BT_RX_RINGBUFSIZE                         0x204C
53 #define ACP_BT_RX_LINKPOSITIONCNTR                    0x2050
54 #define ACP_BT_RX_FIFOADDR                            0x2054
55 #define ACP_BT_RX_FIFOSIZE                            0x2058
56 #define ACP_BT_RX_DMA_SIZE                            0x205C
57 #define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH             0x2060
58 #define ACP_BT_RX_LINEARPOSITIONCNTR_LOW              0x2064
59 #define ACP_BT_RX_INTR_WATERMARK_SIZE                 0x2068
60 #define ACP_BT_TX_RINGBUFADDR                         0x206C
61 #define ACP_BT_TX_RINGBUFSIZE                         0x2070
62 #define ACP_BT_TX_LINKPOSITIONCNTR                    0x2074
63 #define ACP_BT_TX_FIFOADDR                            0x2078
64 #define ACP_BT_TX_FIFOSIZE                            0x207C
65 #define ACP_BT_TX_DMA_SIZE                            0x2080
66 #define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH             0x2084
67 #define ACP_BT_TX_LINEARPOSITIONCNTR_LOW              0x2088
68 #define ACP_BT_TX_INTR_WATERMARK_SIZE                 0x208C
69 #define ACP_HS_RX_RINGBUFADDR			      0x3A90
70 #define ACP_HS_RX_RINGBUFSIZE			      0x3A94
71 #define ACP_HS_RX_LINKPOSITIONCNTR		      0x3A98
72 #define ACP_HS_RX_FIFOADDR			      0x3A9C
73 #define ACP_HS_RX_FIFOSIZE			      0x3AA0
74 #define ACP_HS_RX_DMA_SIZE			      0x3AA4
75 #define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH	      0x3AA8
76 #define ACP_HS_RX_LINEARPOSITIONCNTR_LOW	      0x3AAC
77 #define ACP_HS_RX_INTR_WATERMARK_SIZE		      0x3AB0
78 #define ACP_HS_TX_RINGBUFADDR			      0x3AB4
79 #define ACP_HS_TX_RINGBUFSIZE			      0x3AB8
80 #define ACP_HS_TX_LINKPOSITIONCNTR		      0x3ABC
81 #define ACP_HS_TX_FIFOADDR			      0x3AC0
82 #define ACP_HS_TX_FIFOSIZE			      0x3AC4
83 #define ACP_HS_TX_DMA_SIZE			      0x3AC8
84 #define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH	      0x3ACC
85 #define ACP_HS_TX_LINEARPOSITIONCNTR_LOW	      0x3AD0
86 #define ACP_HS_TX_INTR_WATERMARK_SIZE		      0x3AD4
87 
88 #define ACP_I2STDM_IER                                0x2400
89 #define ACP_I2STDM_IRER                               0x2404
90 #define ACP_I2STDM_RXFRMT                             0x2408
91 #define ACP_I2STDM_ITER                               0x240C
92 #define ACP_I2STDM_TXFRMT                             0x2410
93 
94 /* Registers from ACP_BT_TDM block */
95 
96 #define ACP_BTTDM_IER                                 0x2800
97 #define ACP_BTTDM_IRER                                0x2804
98 #define ACP_BTTDM_RXFRMT                              0x2808
99 #define ACP_BTTDM_ITER                                0x280C
100 #define ACP_BTTDM_TXFRMT                              0x2810
101 
102 /* Registers from ACP_HS_TDM block */
103 #define ACP_HSTDM_IER                                 0x2814
104 #define ACP_HSTDM_IRER                                0x2818
105 #define ACP_HSTDM_RXFRMT                              0x281C
106 #define ACP_HSTDM_ITER                                0x2820
107 #define ACP_HSTDM_TXFRMT                              0x2824
108 
109 /* Registers from ACP_WOV_PDM block */
110 
111 #define ACP_WOV_PDM_ENABLE                            0x2C04
112 #define ACP_WOV_PDM_DMA_ENABLE                        0x2C08
113 #define ACP_WOV_RX_RINGBUFADDR                        0x2C0C
114 #define ACP_WOV_RX_RINGBUFSIZE                        0x2C10
115 #define ACP_WOV_RX_LINKPOSITIONCNTR                   0x2C14
116 #define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH            0x2C18
117 #define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW             0x2C1C
118 #define ACP_WOV_RX_INTR_WATERMARK_SIZE                0x2C20
119 #define ACP_WOV_PDM_FIFO_FLUSH                        0x2C24
120 #define ACP_WOV_PDM_NO_OF_CHANNELS                    0x2C28
121 #define ACP_WOV_PDM_DECIMATION_FACTOR                 0x2C2C
122 #define ACP_WOV_PDM_VAD_CTRL                          0x2C30
123 #define ACP_WOV_BUFFER_STATUS                         0x2C58
124 #define ACP_WOV_MISC_CTRL                             0x2C5C
125 #define ACP_WOV_CLK_CTRL                              0x2C60
126 #define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN             0x2C64
127 #define ACP_WOV_ERROR_STATUS_REGISTER                 0x2C68
128 
129 #define ACP_I2STDM0_MSTRCLKGEN			      0x2414
130 #define ACP_I2STDM1_MSTRCLKGEN			      0x2418
131 #define ACP_I2STDM2_MSTRCLKGEN			      0x241C
132 #endif
133