1 /* 2 * AMD ALSA SoC PCM Driver for ACP 2.x 3 * 4 * Copyright 2014-2015 Advanced Micro Devices, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/io.h> 19 #include <linux/sizes.h> 20 #include <linux/pm_runtime.h> 21 22 #include <sound/soc.h> 23 #include <drm/amd_asic_type.h> 24 #include "acp.h" 25 26 #define DRV_NAME "acp_audio_dma" 27 28 #define PLAYBACK_MIN_NUM_PERIODS 2 29 #define PLAYBACK_MAX_NUM_PERIODS 2 30 #define PLAYBACK_MAX_PERIOD_SIZE 16384 31 #define PLAYBACK_MIN_PERIOD_SIZE 1024 32 #define CAPTURE_MIN_NUM_PERIODS 2 33 #define CAPTURE_MAX_NUM_PERIODS 2 34 #define CAPTURE_MAX_PERIOD_SIZE 16384 35 #define CAPTURE_MIN_PERIOD_SIZE 1024 36 37 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 38 #define MIN_BUFFER MAX_BUFFER 39 40 #define ST_PLAYBACK_MAX_PERIOD_SIZE 8192 41 #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 42 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 43 #define ST_MIN_BUFFER ST_MAX_BUFFER 44 45 #define DRV_NAME "acp_audio_dma" 46 47 static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 48 .info = SNDRV_PCM_INFO_INTERLEAVED | 49 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 50 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 51 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 52 .formats = SNDRV_PCM_FMTBIT_S16_LE | 53 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 54 .channels_min = 1, 55 .channels_max = 8, 56 .rates = SNDRV_PCM_RATE_8000_96000, 57 .rate_min = 8000, 58 .rate_max = 96000, 59 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 60 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 61 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 62 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 63 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 64 }; 65 66 static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 67 .info = SNDRV_PCM_INFO_INTERLEAVED | 68 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 69 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 70 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 71 .formats = SNDRV_PCM_FMTBIT_S16_LE | 72 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 73 .channels_min = 1, 74 .channels_max = 2, 75 .rates = SNDRV_PCM_RATE_8000_48000, 76 .rate_min = 8000, 77 .rate_max = 48000, 78 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 79 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 80 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 81 .periods_min = CAPTURE_MIN_NUM_PERIODS, 82 .periods_max = CAPTURE_MAX_NUM_PERIODS, 83 }; 84 85 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 86 .info = SNDRV_PCM_INFO_INTERLEAVED | 87 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 88 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 89 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 90 .formats = SNDRV_PCM_FMTBIT_S16_LE | 91 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 92 .channels_min = 1, 93 .channels_max = 8, 94 .rates = SNDRV_PCM_RATE_8000_96000, 95 .rate_min = 8000, 96 .rate_max = 96000, 97 .buffer_bytes_max = ST_MAX_BUFFER, 98 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 99 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 100 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 101 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 102 }; 103 104 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 105 .info = SNDRV_PCM_INFO_INTERLEAVED | 106 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 107 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 108 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 109 .formats = SNDRV_PCM_FMTBIT_S16_LE | 110 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 111 .channels_min = 1, 112 .channels_max = 2, 113 .rates = SNDRV_PCM_RATE_8000_48000, 114 .rate_min = 8000, 115 .rate_max = 48000, 116 .buffer_bytes_max = ST_MAX_BUFFER, 117 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 118 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 119 .periods_min = CAPTURE_MIN_NUM_PERIODS, 120 .periods_max = CAPTURE_MAX_NUM_PERIODS, 121 }; 122 123 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 124 { 125 return readl(acp_mmio + (reg * 4)); 126 } 127 128 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 129 { 130 writel(val, acp_mmio + (reg * 4)); 131 } 132 133 /* Configure a given dma channel parameters - enable/disable, 134 * number of descriptors, priority 135 */ 136 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 137 u16 dscr_strt_idx, u16 num_dscrs, 138 enum acp_dma_priority_level priority_level) 139 { 140 u32 dma_ctrl; 141 142 /* disable the channel run field */ 143 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 144 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 145 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 146 147 /* program a DMA channel with first descriptor to be processed. */ 148 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 149 & dscr_strt_idx), 150 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 151 152 /* program a DMA channel with the number of descriptors to be 153 * processed in the transfer 154 */ 155 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 156 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 157 158 /* set DMA channel priority */ 159 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 160 } 161 162 /* Initialize a dma descriptor in SRAM based on descritor information passed */ 163 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 164 u16 descr_idx, 165 acp_dma_dscr_transfer_t *descr_info) 166 { 167 u32 sram_offset; 168 169 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 170 171 /* program the source base address. */ 172 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 173 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 174 /* program the destination base address. */ 175 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 176 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 177 178 /* program the number of bytes to be transferred for this descriptor. */ 179 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 180 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 181 } 182 183 /* Initialize the DMA descriptor information for transfer between 184 * system memory <-> ACP SRAM 185 */ 186 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 187 u32 size, int direction, u32 pte_offset, 188 u16 ch, u32 sram_bank, 189 u16 dma_dscr_idx, u32 asic_type) 190 { 191 u16 i; 192 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 193 194 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 195 dmadscr[i].xfer_val = 0; 196 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 197 dma_dscr_idx = dma_dscr_idx + i; 198 dmadscr[i].dest = sram_bank + (i * (size/2)); 199 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 200 + (pte_offset * SZ_4K) + (i * (size/2)); 201 switch (asic_type) { 202 case CHIP_STONEY: 203 dmadscr[i].xfer_val |= 204 (ACP_DMA_ATTRIBUTES_DAGB_GARLIC_TO_SHAREDMEM << 16) | 205 (size / 2); 206 break; 207 default: 208 dmadscr[i].xfer_val |= 209 (ACP_DMA_ATTRIBUTES_DAGB_ONION_TO_SHAREDMEM << 16) | 210 (size / 2); 211 } 212 } else { 213 dma_dscr_idx = dma_dscr_idx + i; 214 dmadscr[i].src = sram_bank + (i * (size/2)); 215 dmadscr[i].dest = 216 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 217 (pte_offset * SZ_4K) + (i * (size/2)); 218 switch (asic_type) { 219 case CHIP_STONEY: 220 dmadscr[i].xfer_val |= 221 BIT(22) | 222 (ACP_DMA_ATTRIBUTES_SHARED_MEM_TO_DAGB_GARLIC << 16) | 223 (size / 2); 224 break; 225 default: 226 dmadscr[i].xfer_val |= 227 BIT(22) | 228 (ACP_DMA_ATTRIBUTES_SHAREDMEM_TO_DAGB_ONION << 16) | 229 (size / 2); 230 } 231 } 232 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 233 &dmadscr[i]); 234 } 235 config_acp_dma_channel(acp_mmio, ch, 236 dma_dscr_idx - 1, 237 NUM_DSCRS_PER_CHANNEL, 238 ACP_DMA_PRIORITY_LEVEL_NORMAL); 239 } 240 241 /* Initialize the DMA descriptor information for transfer between 242 * ACP SRAM <-> I2S 243 */ 244 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 245 int direction, u32 sram_bank, 246 u16 destination, u16 ch, 247 u16 dma_dscr_idx, u32 asic_type) 248 { 249 250 u16 i; 251 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 252 253 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 254 dmadscr[i].xfer_val = 0; 255 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 256 dma_dscr_idx = dma_dscr_idx + i; 257 dmadscr[i].src = sram_bank + (i * (size/2)); 258 /* dmadscr[i].dest is unused by hardware. */ 259 dmadscr[i].dest = 0; 260 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 261 (size / 2); 262 } else { 263 dma_dscr_idx = dma_dscr_idx + i; 264 /* dmadscr[i].src is unused by hardware. */ 265 dmadscr[i].src = 0; 266 dmadscr[i].dest = 267 sram_bank + (i * (size / 2)); 268 dmadscr[i].xfer_val |= BIT(22) | 269 (destination << 16) | (size / 2); 270 } 271 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 272 &dmadscr[i]); 273 } 274 /* Configure the DMA channel with the above descriptore */ 275 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 276 NUM_DSCRS_PER_CHANNEL, 277 ACP_DMA_PRIORITY_LEVEL_NORMAL); 278 } 279 280 /* Create page table entries in ACP SRAM for the allocated memory */ 281 static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, 282 u16 num_of_pages, u32 pte_offset) 283 { 284 u16 page_idx; 285 u64 addr; 286 u32 low; 287 u32 high; 288 u32 offset; 289 290 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 291 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 292 /* Load the low address of page int ACP SRAM through SRBM */ 293 acp_reg_write((offset + (page_idx * 8)), 294 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 295 addr = page_to_phys(pg); 296 297 low = lower_32_bits(addr); 298 high = upper_32_bits(addr); 299 300 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 301 302 /* Load the High address of page int ACP SRAM through SRBM */ 303 acp_reg_write((offset + (page_idx * 8) + 4), 304 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 305 306 /* page enable in ACP */ 307 high |= BIT(31); 308 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 309 310 /* Move to next physically contiguos page */ 311 pg++; 312 } 313 } 314 315 static void config_acp_dma(void __iomem *acp_mmio, 316 struct audio_substream_data *audio_config, 317 u32 asic_type) 318 { 319 u32 pte_offset, sram_bank; 320 u16 ch1, ch2, destination, dma_dscr_idx; 321 322 if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) { 323 pte_offset = ACP_PLAYBACK_PTE_OFFSET; 324 ch1 = SYSRAM_TO_ACP_CH_NUM; 325 ch2 = ACP_TO_I2S_DMA_CH_NUM; 326 sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS; 327 destination = TO_ACP_I2S_1; 328 329 } else { 330 pte_offset = ACP_CAPTURE_PTE_OFFSET; 331 ch1 = SYSRAM_TO_ACP_CH_NUM; 332 ch2 = ACP_TO_I2S_DMA_CH_NUM; 333 switch (asic_type) { 334 case CHIP_STONEY: 335 sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS; 336 break; 337 default: 338 sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS; 339 } 340 destination = FROM_ACP_I2S_1; 341 } 342 343 acp_pte_config(acp_mmio, audio_config->pg, audio_config->num_of_pages, 344 pte_offset); 345 if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) 346 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; 347 else 348 dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 349 350 /* Configure System memory <-> ACP SRAM DMA descriptors */ 351 set_acp_sysmem_dma_descriptors(acp_mmio, audio_config->size, 352 audio_config->direction, pte_offset, 353 ch1, sram_bank, dma_dscr_idx, asic_type); 354 355 if (audio_config->direction == SNDRV_PCM_STREAM_PLAYBACK) 356 dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13; 357 else 358 dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15; 359 /* Configure ACP SRAM <-> I2S DMA descriptors */ 360 set_acp_to_i2s_dma_descriptors(acp_mmio, audio_config->size, 361 audio_config->direction, sram_bank, 362 destination, ch2, dma_dscr_idx, 363 asic_type); 364 } 365 366 /* Start a given DMA channel transfer */ 367 static void acp_dma_start(void __iomem *acp_mmio, 368 u16 ch_num, bool is_circular) 369 { 370 u32 dma_ctrl; 371 372 /* read the dma control register and disable the channel run field */ 373 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 374 375 /* Invalidating the DAGB cache */ 376 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 377 378 /* configure the DMA channel and start the DMA transfer 379 * set dmachrun bit to start the transfer and enable the 380 * interrupt on completion of the dma transfer 381 */ 382 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 383 384 switch (ch_num) { 385 case ACP_TO_I2S_DMA_CH_NUM: 386 case ACP_TO_SYSRAM_CH_NUM: 387 case I2S_TO_ACP_DMA_CH_NUM: 388 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 389 break; 390 default: 391 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 392 break; 393 } 394 395 /* enable for ACP SRAM to/from I2S DMA channel */ 396 if (is_circular == true) 397 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 398 else 399 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 400 401 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 402 } 403 404 /* Stop a given DMA channel transfer */ 405 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 406 { 407 u32 dma_ctrl; 408 u32 dma_ch_sts; 409 u32 count = ACP_DMA_RESET_TIME; 410 411 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 412 413 /* clear the dma control register fields before writing zero 414 * in reset bit 415 */ 416 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 417 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 418 419 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 420 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 421 422 if (dma_ch_sts & BIT(ch_num)) { 423 /* set the reset bit for this channel to stop the dma 424 * transfer 425 */ 426 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 427 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 428 } 429 430 /* check the channel status bit for some time and return the status */ 431 while (true) { 432 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 433 if (!(dma_ch_sts & BIT(ch_num))) { 434 /* clear the reset flag after successfully stopping 435 * the dma transfer and break from the loop 436 */ 437 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 438 439 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 440 + ch_num); 441 break; 442 } 443 if (--count == 0) { 444 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 445 return -ETIMEDOUT; 446 } 447 udelay(100); 448 } 449 return 0; 450 } 451 452 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 453 bool power_on) 454 { 455 u32 val, req_reg, sts_reg, sts_reg_mask; 456 u32 loops = 1000; 457 458 if (bank < 32) { 459 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 460 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 461 sts_reg_mask = 0xFFFFFFFF; 462 463 } else { 464 bank -= 32; 465 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 466 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 467 sts_reg_mask = 0x0000FFFF; 468 } 469 470 val = acp_reg_read(acp_mmio, req_reg); 471 if (val & (1 << bank)) { 472 /* bank is in off state */ 473 if (power_on == true) 474 /* request to on */ 475 val &= ~(1 << bank); 476 else 477 /* request to off */ 478 return; 479 } else { 480 /* bank is in on state */ 481 if (power_on == false) 482 /* request to off */ 483 val |= 1 << bank; 484 else 485 /* request to on */ 486 return; 487 } 488 acp_reg_write(val, acp_mmio, req_reg); 489 490 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 491 if (!loops--) { 492 pr_err("ACP SRAM bank %d state change failed\n", bank); 493 break; 494 } 495 cpu_relax(); 496 } 497 } 498 499 /* Initialize and bring ACP hardware to default state. */ 500 static int acp_init(void __iomem *acp_mmio, u32 asic_type) 501 { 502 u16 bank; 503 u32 val, count, sram_pte_offset; 504 505 /* Assert Soft reset of ACP */ 506 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 507 508 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 509 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 510 511 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 512 while (true) { 513 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 514 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 515 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 516 break; 517 if (--count == 0) { 518 pr_err("Failed to reset ACP\n"); 519 return -ETIMEDOUT; 520 } 521 udelay(100); 522 } 523 524 /* Enable clock to ACP and wait until the clock is enabled */ 525 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 526 val = val | ACP_CONTROL__ClkEn_MASK; 527 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 528 529 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 530 531 while (true) { 532 val = acp_reg_read(acp_mmio, mmACP_STATUS); 533 if (val & (u32) 0x1) 534 break; 535 if (--count == 0) { 536 pr_err("Failed to reset ACP\n"); 537 return -ETIMEDOUT; 538 } 539 udelay(100); 540 } 541 542 /* Deassert the SOFT RESET flags */ 543 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 544 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 545 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 546 547 /* initiailize Onion control DAGB register */ 548 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 549 mmACP_AXI2DAGB_ONION_CNTL); 550 551 /* initiailize Garlic control DAGB registers */ 552 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 553 mmACP_AXI2DAGB_GARLIC_CNTL); 554 555 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 556 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 557 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 558 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 559 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 560 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 561 mmACP_DAGB_PAGE_SIZE_GRP_1); 562 563 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 564 mmACP_DMA_DESC_BASE_ADDR); 565 566 /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 567 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 568 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 569 acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 570 571 /* When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 572 * Now, turn off all of them. This can't be done in 'poweron' of 573 * ACP pm domain, as this requires ACP to be initialized. 574 * For Stoney, Memory gating is disabled,i.e SRAM Banks 575 * won't be turned off. The default state for SRAM banks is ON. 576 * Setting SRAM bank state code skipped for STONEY platform. 577 */ 578 if (asic_type != CHIP_STONEY) { 579 for (bank = 1; bank < 48; bank++) 580 acp_set_sram_bank_state(acp_mmio, bank, false); 581 } 582 return 0; 583 } 584 585 /* Deinitialize ACP */ 586 static int acp_deinit(void __iomem *acp_mmio) 587 { 588 u32 val; 589 u32 count; 590 591 /* Assert Soft reset of ACP */ 592 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 593 594 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 595 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 596 597 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 598 while (true) { 599 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 600 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 601 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 602 break; 603 if (--count == 0) { 604 pr_err("Failed to reset ACP\n"); 605 return -ETIMEDOUT; 606 } 607 udelay(100); 608 } 609 /** Disable ACP clock */ 610 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 611 val &= ~ACP_CONTROL__ClkEn_MASK; 612 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 613 614 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 615 616 while (true) { 617 val = acp_reg_read(acp_mmio, mmACP_STATUS); 618 if (!(val & (u32) 0x1)) 619 break; 620 if (--count == 0) { 621 pr_err("Failed to reset ACP\n"); 622 return -ETIMEDOUT; 623 } 624 udelay(100); 625 } 626 return 0; 627 } 628 629 /* ACP DMA irq handler routine for playback, capture usecases */ 630 static irqreturn_t dma_irq_handler(int irq, void *arg) 631 { 632 u16 dscr_idx; 633 u32 intr_flag, ext_intr_status; 634 struct audio_drv_data *irq_data; 635 void __iomem *acp_mmio; 636 struct device *dev = arg; 637 bool valid_irq = false; 638 639 irq_data = dev_get_drvdata(dev); 640 acp_mmio = irq_data->acp_mmio; 641 642 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 643 intr_flag = (((ext_intr_status & 644 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 645 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 646 647 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 648 valid_irq = true; 649 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_13) == 650 PLAYBACK_START_DMA_DESCR_CH13) 651 dscr_idx = PLAYBACK_END_DMA_DESCR_CH12; 652 else 653 dscr_idx = PLAYBACK_START_DMA_DESCR_CH12; 654 config_acp_dma_channel(acp_mmio, SYSRAM_TO_ACP_CH_NUM, dscr_idx, 655 1, 0); 656 acp_dma_start(acp_mmio, SYSRAM_TO_ACP_CH_NUM, false); 657 658 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 659 660 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 661 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 662 } 663 664 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 665 valid_irq = true; 666 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_15) == 667 CAPTURE_START_DMA_DESCR_CH15) 668 dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 669 else 670 dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 671 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 672 1, 0); 673 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 674 675 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 676 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 677 } 678 679 if ((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) != 0) { 680 valid_irq = true; 681 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 682 acp_reg_write((intr_flag & BIT(ACP_TO_SYSRAM_CH_NUM)) << 16, 683 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 684 } 685 686 if (valid_irq) 687 return IRQ_HANDLED; 688 else 689 return IRQ_NONE; 690 } 691 692 static int acp_dma_open(struct snd_pcm_substream *substream) 693 { 694 u16 bank; 695 int ret = 0; 696 struct snd_pcm_runtime *runtime = substream->runtime; 697 struct snd_soc_pcm_runtime *prtd = substream->private_data; 698 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME); 699 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 700 struct audio_substream_data *adata = 701 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 702 if (adata == NULL) 703 return -ENOMEM; 704 705 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 706 switch (intr_data->asic_type) { 707 case CHIP_STONEY: 708 runtime->hw = acp_st_pcm_hardware_playback; 709 break; 710 default: 711 runtime->hw = acp_pcm_hardware_playback; 712 } 713 } else { 714 switch (intr_data->asic_type) { 715 case CHIP_STONEY: 716 runtime->hw = acp_st_pcm_hardware_capture; 717 break; 718 default: 719 runtime->hw = acp_pcm_hardware_capture; 720 } 721 } 722 723 ret = snd_pcm_hw_constraint_integer(runtime, 724 SNDRV_PCM_HW_PARAM_PERIODS); 725 if (ret < 0) { 726 dev_err(component->dev, "set integer constraint failed\n"); 727 kfree(adata); 728 return ret; 729 } 730 731 adata->acp_mmio = intr_data->acp_mmio; 732 runtime->private_data = adata; 733 734 /* Enable ACP irq, when neither playback or capture streams are 735 * active by the time when a new stream is being opened. 736 * This enablement is not required for another stream, if current 737 * stream is not closed 738 */ 739 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream) 740 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 741 742 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 743 intr_data->play_i2ssp_stream = substream; 744 /* For Stoney, Memory gating is disabled,i.e SRAM Banks 745 * won't be turned off. The default state for SRAM banks is ON. 746 * Setting SRAM bank state code skipped for STONEY platform. 747 */ 748 if (intr_data->asic_type != CHIP_STONEY) { 749 for (bank = 1; bank <= 4; bank++) 750 acp_set_sram_bank_state(intr_data->acp_mmio, 751 bank, true); 752 } 753 } else { 754 intr_data->capture_i2ssp_stream = substream; 755 if (intr_data->asic_type != CHIP_STONEY) { 756 for (bank = 5; bank <= 8; bank++) 757 acp_set_sram_bank_state(intr_data->acp_mmio, 758 bank, true); 759 } 760 } 761 762 return 0; 763 } 764 765 static int acp_dma_hw_params(struct snd_pcm_substream *substream, 766 struct snd_pcm_hw_params *params) 767 { 768 int status; 769 uint64_t size; 770 u32 val = 0; 771 struct page *pg; 772 struct snd_pcm_runtime *runtime; 773 struct audio_substream_data *rtd; 774 struct snd_soc_pcm_runtime *prtd = substream->private_data; 775 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME); 776 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 777 778 runtime = substream->runtime; 779 rtd = runtime->private_data; 780 781 if (WARN_ON(!rtd)) 782 return -EINVAL; 783 784 if (adata->asic_type == CHIP_STONEY) { 785 val = acp_reg_read(adata->acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN); 786 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 787 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 788 else 789 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 790 acp_reg_write(val, adata->acp_mmio, mmACP_I2S_16BIT_RESOLUTION_EN); 791 } 792 size = params_buffer_bytes(params); 793 status = snd_pcm_lib_malloc_pages(substream, size); 794 if (status < 0) 795 return status; 796 797 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 798 pg = virt_to_page(substream->dma_buffer.area); 799 800 if (pg != NULL) { 801 acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 802 /* Save for runtime private data */ 803 rtd->pg = pg; 804 rtd->order = get_order(size); 805 806 /* Fill the page table entries in ACP SRAM */ 807 rtd->pg = pg; 808 rtd->size = size; 809 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 810 rtd->direction = substream->stream; 811 812 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 813 status = 0; 814 } else { 815 status = -ENOMEM; 816 } 817 return status; 818 } 819 820 static int acp_dma_hw_free(struct snd_pcm_substream *substream) 821 { 822 return snd_pcm_lib_free_pages(substream); 823 } 824 825 static u64 acp_get_byte_count(void __iomem *acp_mmio, int stream) 826 { 827 union acp_dma_count playback_dma_count; 828 union acp_dma_count capture_dma_count; 829 u64 bytescount = 0; 830 831 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 832 playback_dma_count.bcount.high = acp_reg_read(acp_mmio, 833 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH); 834 playback_dma_count.bcount.low = acp_reg_read(acp_mmio, 835 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW); 836 bytescount = playback_dma_count.bytescount; 837 } else { 838 capture_dma_count.bcount.high = acp_reg_read(acp_mmio, 839 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH); 840 capture_dma_count.bcount.low = acp_reg_read(acp_mmio, 841 mmACP_I2S_RECEIVED_BYTE_CNT_LOW); 842 bytescount = capture_dma_count.bytescount; 843 } 844 return bytescount; 845 } 846 847 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 848 { 849 u32 buffersize; 850 u32 pos = 0; 851 u64 bytescount = 0; 852 853 struct snd_pcm_runtime *runtime = substream->runtime; 854 struct audio_substream_data *rtd = runtime->private_data; 855 856 if (!rtd) 857 return -EINVAL; 858 859 buffersize = frames_to_bytes(runtime, runtime->buffer_size); 860 bytescount = acp_get_byte_count(rtd->acp_mmio, substream->stream); 861 862 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 863 if (bytescount > rtd->i2ssp_renderbytescount) 864 bytescount = bytescount - rtd->i2ssp_renderbytescount; 865 } else { 866 if (bytescount > rtd->i2ssp_capturebytescount) 867 bytescount = bytescount - rtd->i2ssp_capturebytescount; 868 } 869 pos = do_div(bytescount, buffersize); 870 return bytes_to_frames(runtime, pos); 871 } 872 873 static int acp_dma_mmap(struct snd_pcm_substream *substream, 874 struct vm_area_struct *vma) 875 { 876 return snd_pcm_lib_default_mmap(substream, vma); 877 } 878 879 static int acp_dma_prepare(struct snd_pcm_substream *substream) 880 { 881 struct snd_pcm_runtime *runtime = substream->runtime; 882 struct audio_substream_data *rtd = runtime->private_data; 883 884 if (!rtd) 885 return -EINVAL; 886 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 887 config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM, 888 PLAYBACK_START_DMA_DESCR_CH12, 889 NUM_DSCRS_PER_CHANNEL, 0); 890 config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM, 891 PLAYBACK_START_DMA_DESCR_CH13, 892 NUM_DSCRS_PER_CHANNEL, 0); 893 } else { 894 config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM, 895 CAPTURE_START_DMA_DESCR_CH14, 896 NUM_DSCRS_PER_CHANNEL, 0); 897 config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM, 898 CAPTURE_START_DMA_DESCR_CH15, 899 NUM_DSCRS_PER_CHANNEL, 0); 900 } 901 return 0; 902 } 903 904 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 905 { 906 int ret; 907 u32 loops = 4000; 908 u64 bytescount = 0; 909 910 struct snd_pcm_runtime *runtime = substream->runtime; 911 struct snd_soc_pcm_runtime *prtd = substream->private_data; 912 struct audio_substream_data *rtd = runtime->private_data; 913 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME); 914 915 if (!rtd) 916 return -EINVAL; 917 switch (cmd) { 918 case SNDRV_PCM_TRIGGER_START: 919 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 920 case SNDRV_PCM_TRIGGER_RESUME: 921 bytescount = acp_get_byte_count(rtd->acp_mmio, 922 substream->stream); 923 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 924 if (rtd->i2ssp_renderbytescount == 0) 925 rtd->i2ssp_renderbytescount = bytescount; 926 acp_dma_start(rtd->acp_mmio, 927 SYSRAM_TO_ACP_CH_NUM, false); 928 while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) & 929 BIT(SYSRAM_TO_ACP_CH_NUM)) { 930 if (!loops--) { 931 dev_err(component->dev, 932 "acp dma start timeout\n"); 933 return -ETIMEDOUT; 934 } 935 cpu_relax(); 936 } 937 938 acp_dma_start(rtd->acp_mmio, 939 ACP_TO_I2S_DMA_CH_NUM, true); 940 941 } else { 942 if (rtd->i2ssp_capturebytescount == 0) 943 rtd->i2ssp_capturebytescount = bytescount; 944 acp_dma_start(rtd->acp_mmio, 945 I2S_TO_ACP_DMA_CH_NUM, true); 946 } 947 ret = 0; 948 break; 949 case SNDRV_PCM_TRIGGER_STOP: 950 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 951 case SNDRV_PCM_TRIGGER_SUSPEND: 952 /* Need to stop only circular DMA channels : 953 * ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular 954 * channels will stopped automatically after its transfer 955 * completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM 956 */ 957 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 958 ret = acp_dma_stop(rtd->acp_mmio, 959 SYSRAM_TO_ACP_CH_NUM); 960 ret = acp_dma_stop(rtd->acp_mmio, 961 ACP_TO_I2S_DMA_CH_NUM); 962 rtd->i2ssp_renderbytescount = 0; 963 } else { 964 ret = acp_dma_stop(rtd->acp_mmio, 965 I2S_TO_ACP_DMA_CH_NUM); 966 ret = acp_dma_stop(rtd->acp_mmio, 967 ACP_TO_SYSRAM_CH_NUM); 968 rtd->i2ssp_capturebytescount = 0; 969 } 970 break; 971 default: 972 ret = -EINVAL; 973 974 } 975 return ret; 976 } 977 978 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 979 { 980 int ret; 981 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, DRV_NAME); 982 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 983 984 switch (adata->asic_type) { 985 case CHIP_STONEY: 986 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 987 SNDRV_DMA_TYPE_DEV, 988 NULL, ST_MIN_BUFFER, 989 ST_MAX_BUFFER); 990 break; 991 default: 992 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 993 SNDRV_DMA_TYPE_DEV, 994 NULL, MIN_BUFFER, 995 MAX_BUFFER); 996 break; 997 } 998 if (ret < 0) 999 dev_err(component->dev, 1000 "buffer preallocation failer error:%d\n", ret); 1001 return ret; 1002 } 1003 1004 static int acp_dma_close(struct snd_pcm_substream *substream) 1005 { 1006 u16 bank; 1007 struct snd_pcm_runtime *runtime = substream->runtime; 1008 struct audio_substream_data *rtd = runtime->private_data; 1009 struct snd_soc_pcm_runtime *prtd = substream->private_data; 1010 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, DRV_NAME); 1011 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1012 1013 kfree(rtd); 1014 1015 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1016 adata->play_i2ssp_stream = NULL; 1017 /* For Stoney, Memory gating is disabled,i.e SRAM Banks 1018 * won't be turned off. The default state for SRAM banks is ON. 1019 * Setting SRAM bank state code skipped for STONEY platform. 1020 * added condition checks for Carrizo platform only 1021 */ 1022 if (adata->asic_type != CHIP_STONEY) { 1023 for (bank = 1; bank <= 4; bank++) 1024 acp_set_sram_bank_state(adata->acp_mmio, bank, 1025 false); 1026 } 1027 } else { 1028 adata->capture_i2ssp_stream = NULL; 1029 if (adata->asic_type != CHIP_STONEY) { 1030 for (bank = 5; bank <= 8; bank++) 1031 acp_set_sram_bank_state(adata->acp_mmio, bank, 1032 false); 1033 } 1034 } 1035 1036 /* Disable ACP irq, when the current stream is being closed and 1037 * another stream is also not active. 1038 */ 1039 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream) 1040 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1041 1042 return 0; 1043 } 1044 1045 static const struct snd_pcm_ops acp_dma_ops = { 1046 .open = acp_dma_open, 1047 .close = acp_dma_close, 1048 .ioctl = snd_pcm_lib_ioctl, 1049 .hw_params = acp_dma_hw_params, 1050 .hw_free = acp_dma_hw_free, 1051 .trigger = acp_dma_trigger, 1052 .pointer = acp_dma_pointer, 1053 .mmap = acp_dma_mmap, 1054 .prepare = acp_dma_prepare, 1055 }; 1056 1057 static struct snd_soc_component_driver acp_asoc_platform = { 1058 .name = DRV_NAME, 1059 .ops = &acp_dma_ops, 1060 .pcm_new = acp_dma_new, 1061 }; 1062 1063 static int acp_audio_probe(struct platform_device *pdev) 1064 { 1065 int status; 1066 struct audio_drv_data *audio_drv_data; 1067 struct resource *res; 1068 const u32 *pdata = pdev->dev.platform_data; 1069 1070 if (!pdata) { 1071 dev_err(&pdev->dev, "Missing platform data\n"); 1072 return -ENODEV; 1073 } 1074 1075 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 1076 GFP_KERNEL); 1077 if (audio_drv_data == NULL) 1078 return -ENOMEM; 1079 1080 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1081 audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 1082 if (IS_ERR(audio_drv_data->acp_mmio)) 1083 return PTR_ERR(audio_drv_data->acp_mmio); 1084 1085 /* The following members gets populated in device 'open' 1086 * function. Till then interrupts are disabled in 'acp_init' 1087 * and device doesn't generate any interrupts. 1088 */ 1089 1090 audio_drv_data->play_i2ssp_stream = NULL; 1091 audio_drv_data->capture_i2ssp_stream = NULL; 1092 1093 audio_drv_data->asic_type = *pdata; 1094 1095 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1096 if (!res) { 1097 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 1098 return -ENODEV; 1099 } 1100 1101 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 1102 0, "ACP_IRQ", &pdev->dev); 1103 if (status) { 1104 dev_err(&pdev->dev, "ACP IRQ request failed\n"); 1105 return status; 1106 } 1107 1108 dev_set_drvdata(&pdev->dev, audio_drv_data); 1109 1110 /* Initialize the ACP */ 1111 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 1112 if (status) { 1113 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 1114 return status; 1115 } 1116 1117 status = devm_snd_soc_register_component(&pdev->dev, 1118 &acp_asoc_platform, NULL, 0); 1119 if (status != 0) { 1120 dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 1121 return status; 1122 } 1123 1124 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 1125 pm_runtime_use_autosuspend(&pdev->dev); 1126 pm_runtime_enable(&pdev->dev); 1127 1128 return status; 1129 } 1130 1131 static int acp_audio_remove(struct platform_device *pdev) 1132 { 1133 int status; 1134 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 1135 1136 status = acp_deinit(adata->acp_mmio); 1137 if (status) 1138 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 1139 pm_runtime_disable(&pdev->dev); 1140 1141 return 0; 1142 } 1143 1144 static int acp_pcm_resume(struct device *dev) 1145 { 1146 u16 bank; 1147 int status; 1148 struct audio_drv_data *adata = dev_get_drvdata(dev); 1149 1150 status = acp_init(adata->acp_mmio, adata->asic_type); 1151 if (status) { 1152 dev_err(dev, "ACP Init failed status:%d\n", status); 1153 return status; 1154 } 1155 1156 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 1157 /* For Stoney, Memory gating is disabled,i.e SRAM Banks 1158 * won't be turned off. The default state for SRAM banks is ON. 1159 * Setting SRAM bank state code skipped for STONEY platform. 1160 */ 1161 if (adata->asic_type != CHIP_STONEY) { 1162 for (bank = 1; bank <= 4; bank++) 1163 acp_set_sram_bank_state(adata->acp_mmio, bank, 1164 true); 1165 } 1166 config_acp_dma(adata->acp_mmio, 1167 adata->play_i2ssp_stream->runtime->private_data, 1168 adata->asic_type); 1169 } 1170 if (adata->capture_i2ssp_stream && adata->capture_i2ssp_stream->runtime) { 1171 if (adata->asic_type != CHIP_STONEY) { 1172 for (bank = 5; bank <= 8; bank++) 1173 acp_set_sram_bank_state(adata->acp_mmio, bank, 1174 true); 1175 } 1176 config_acp_dma(adata->acp_mmio, 1177 adata->capture_i2ssp_stream->runtime->private_data, 1178 adata->asic_type); 1179 } 1180 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1181 return 0; 1182 } 1183 1184 static int acp_pcm_runtime_suspend(struct device *dev) 1185 { 1186 int status; 1187 struct audio_drv_data *adata = dev_get_drvdata(dev); 1188 1189 status = acp_deinit(adata->acp_mmio); 1190 if (status) 1191 dev_err(dev, "ACP Deinit failed status:%d\n", status); 1192 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1193 return 0; 1194 } 1195 1196 static int acp_pcm_runtime_resume(struct device *dev) 1197 { 1198 int status; 1199 struct audio_drv_data *adata = dev_get_drvdata(dev); 1200 1201 status = acp_init(adata->acp_mmio, adata->asic_type); 1202 if (status) { 1203 dev_err(dev, "ACP Init failed status:%d\n", status); 1204 return status; 1205 } 1206 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1207 return 0; 1208 } 1209 1210 static const struct dev_pm_ops acp_pm_ops = { 1211 .resume = acp_pcm_resume, 1212 .runtime_suspend = acp_pcm_runtime_suspend, 1213 .runtime_resume = acp_pcm_runtime_resume, 1214 }; 1215 1216 static struct platform_driver acp_dma_driver = { 1217 .probe = acp_audio_probe, 1218 .remove = acp_audio_remove, 1219 .driver = { 1220 .name = DRV_NAME, 1221 .pm = &acp_pm_ops, 1222 }, 1223 }; 1224 1225 module_platform_driver(acp_dma_driver); 1226 1227 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1228 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 1229 MODULE_DESCRIPTION("AMD ACP PCM Driver"); 1230 MODULE_LICENSE("GPL v2"); 1231 MODULE_ALIAS("platform:"DRV_NAME); 1232