1 /* 2 * AMD ALSA SoC PCM Driver for ACP 2.x 3 * 4 * Copyright 2014-2015 Advanced Micro Devices, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/delay.h> 18 #include <linux/io.h> 19 #include <linux/sizes.h> 20 #include <linux/pm_runtime.h> 21 22 #include <sound/soc.h> 23 #include <drm/amd_asic_type.h> 24 #include "acp.h" 25 26 #define DRV_NAME "acp_audio_dma" 27 28 #define PLAYBACK_MIN_NUM_PERIODS 2 29 #define PLAYBACK_MAX_NUM_PERIODS 2 30 #define PLAYBACK_MAX_PERIOD_SIZE 16384 31 #define PLAYBACK_MIN_PERIOD_SIZE 1024 32 #define CAPTURE_MIN_NUM_PERIODS 2 33 #define CAPTURE_MAX_NUM_PERIODS 2 34 #define CAPTURE_MAX_PERIOD_SIZE 16384 35 #define CAPTURE_MIN_PERIOD_SIZE 1024 36 37 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 38 #define MIN_BUFFER MAX_BUFFER 39 40 #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 41 #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 42 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 43 #define ST_MIN_BUFFER ST_MAX_BUFFER 44 45 #define DRV_NAME "acp_audio_dma" 46 bool bt_uart_enable = true; 47 EXPORT_SYMBOL(bt_uart_enable); 48 49 static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 50 .info = SNDRV_PCM_INFO_INTERLEAVED | 51 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 52 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 53 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 54 .formats = SNDRV_PCM_FMTBIT_S16_LE | 55 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 56 .channels_min = 1, 57 .channels_max = 8, 58 .rates = SNDRV_PCM_RATE_8000_96000, 59 .rate_min = 8000, 60 .rate_max = 96000, 61 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 62 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 63 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 64 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 65 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 66 }; 67 68 static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 69 .info = SNDRV_PCM_INFO_INTERLEAVED | 70 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 71 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 72 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 73 .formats = SNDRV_PCM_FMTBIT_S16_LE | 74 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 75 .channels_min = 1, 76 .channels_max = 2, 77 .rates = SNDRV_PCM_RATE_8000_48000, 78 .rate_min = 8000, 79 .rate_max = 48000, 80 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 81 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 82 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 83 .periods_min = CAPTURE_MIN_NUM_PERIODS, 84 .periods_max = CAPTURE_MAX_NUM_PERIODS, 85 }; 86 87 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 88 .info = SNDRV_PCM_INFO_INTERLEAVED | 89 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 90 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 91 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 92 .formats = SNDRV_PCM_FMTBIT_S16_LE | 93 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 94 .channels_min = 1, 95 .channels_max = 8, 96 .rates = SNDRV_PCM_RATE_8000_96000, 97 .rate_min = 8000, 98 .rate_max = 96000, 99 .buffer_bytes_max = ST_MAX_BUFFER, 100 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 101 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 102 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 103 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 104 }; 105 106 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 107 .info = SNDRV_PCM_INFO_INTERLEAVED | 108 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 109 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 110 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 111 .formats = SNDRV_PCM_FMTBIT_S16_LE | 112 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 113 .channels_min = 1, 114 .channels_max = 2, 115 .rates = SNDRV_PCM_RATE_8000_48000, 116 .rate_min = 8000, 117 .rate_max = 48000, 118 .buffer_bytes_max = ST_MAX_BUFFER, 119 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 120 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 121 .periods_min = CAPTURE_MIN_NUM_PERIODS, 122 .periods_max = CAPTURE_MAX_NUM_PERIODS, 123 }; 124 125 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 126 { 127 return readl(acp_mmio + (reg * 4)); 128 } 129 130 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 131 { 132 writel(val, acp_mmio + (reg * 4)); 133 } 134 135 /* 136 * Configure a given dma channel parameters - enable/disable, 137 * number of descriptors, priority 138 */ 139 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 140 u16 dscr_strt_idx, u16 num_dscrs, 141 enum acp_dma_priority_level priority_level) 142 { 143 u32 dma_ctrl; 144 145 /* disable the channel run field */ 146 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 147 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 148 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 149 150 /* program a DMA channel with first descriptor to be processed. */ 151 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 152 & dscr_strt_idx), 153 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 154 155 /* 156 * program a DMA channel with the number of descriptors to be 157 * processed in the transfer 158 */ 159 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 160 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 161 162 /* set DMA channel priority */ 163 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 164 } 165 166 /* Initialize a dma descriptor in SRAM based on descritor information passed */ 167 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 168 u16 descr_idx, 169 acp_dma_dscr_transfer_t *descr_info) 170 { 171 u32 sram_offset; 172 173 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 174 175 /* program the source base address. */ 176 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 177 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 178 /* program the destination base address. */ 179 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 180 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 181 182 /* program the number of bytes to be transferred for this descriptor. */ 183 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 184 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 185 } 186 187 /* 188 * Initialize the DMA descriptor information for transfer between 189 * system memory <-> ACP SRAM 190 */ 191 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 192 u32 size, int direction, 193 u32 pte_offset, u16 ch, 194 u32 sram_bank, u16 dma_dscr_idx, 195 u32 asic_type) 196 { 197 u16 i; 198 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 199 200 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 201 dmadscr[i].xfer_val = 0; 202 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 203 dma_dscr_idx = dma_dscr_idx + i; 204 dmadscr[i].dest = sram_bank + (i * (size / 2)); 205 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 206 + (pte_offset * SZ_4K) + (i * (size / 2)); 207 switch (asic_type) { 208 case CHIP_STONEY: 209 dmadscr[i].xfer_val |= 210 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 211 (size / 2); 212 break; 213 default: 214 dmadscr[i].xfer_val |= 215 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 216 (size / 2); 217 } 218 } else { 219 dma_dscr_idx = dma_dscr_idx + i; 220 dmadscr[i].src = sram_bank + (i * (size / 2)); 221 dmadscr[i].dest = 222 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 223 (pte_offset * SZ_4K) + (i * (size / 2)); 224 switch (asic_type) { 225 case CHIP_STONEY: 226 dmadscr[i].xfer_val |= 227 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 228 (size / 2); 229 break; 230 default: 231 dmadscr[i].xfer_val |= 232 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 233 (size / 2); 234 } 235 } 236 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 237 &dmadscr[i]); 238 } 239 config_acp_dma_channel(acp_mmio, ch, 240 dma_dscr_idx - 1, 241 NUM_DSCRS_PER_CHANNEL, 242 ACP_DMA_PRIORITY_LEVEL_NORMAL); 243 } 244 245 /* 246 * Initialize the DMA descriptor information for transfer between 247 * ACP SRAM <-> I2S 248 */ 249 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 250 int direction, u32 sram_bank, 251 u16 destination, u16 ch, 252 u16 dma_dscr_idx, u32 asic_type) 253 { 254 u16 i; 255 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 256 257 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 258 dmadscr[i].xfer_val = 0; 259 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 260 dma_dscr_idx = dma_dscr_idx + i; 261 dmadscr[i].src = sram_bank + (i * (size / 2)); 262 /* dmadscr[i].dest is unused by hardware. */ 263 dmadscr[i].dest = 0; 264 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 265 (size / 2); 266 } else { 267 dma_dscr_idx = dma_dscr_idx + i; 268 /* dmadscr[i].src is unused by hardware. */ 269 dmadscr[i].src = 0; 270 dmadscr[i].dest = 271 sram_bank + (i * (size / 2)); 272 dmadscr[i].xfer_val |= BIT(22) | 273 (destination << 16) | (size / 2); 274 } 275 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 276 &dmadscr[i]); 277 } 278 /* Configure the DMA channel with the above descriptore */ 279 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 280 NUM_DSCRS_PER_CHANNEL, 281 ACP_DMA_PRIORITY_LEVEL_NORMAL); 282 } 283 284 /* Create page table entries in ACP SRAM for the allocated memory */ 285 static void acp_pte_config(void __iomem *acp_mmio, struct page *pg, 286 u16 num_of_pages, u32 pte_offset) 287 { 288 u16 page_idx; 289 u64 addr; 290 u32 low; 291 u32 high; 292 u32 offset; 293 294 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 295 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 296 /* Load the low address of page int ACP SRAM through SRBM */ 297 acp_reg_write((offset + (page_idx * 8)), 298 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 299 addr = page_to_phys(pg); 300 301 low = lower_32_bits(addr); 302 high = upper_32_bits(addr); 303 304 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 305 306 /* Load the High address of page int ACP SRAM through SRBM */ 307 acp_reg_write((offset + (page_idx * 8) + 4), 308 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 309 310 /* page enable in ACP */ 311 high |= BIT(31); 312 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 313 314 /* Move to next physically contiguos page */ 315 pg++; 316 } 317 } 318 319 static void config_acp_dma(void __iomem *acp_mmio, 320 struct audio_substream_data *rtd, 321 u32 asic_type) 322 { 323 u16 ch_acp_sysmem, ch_acp_i2s; 324 325 acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages, 326 rtd->pte_offset); 327 328 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 329 ch_acp_sysmem = rtd->ch1; 330 ch_acp_i2s = rtd->ch2; 331 } else { 332 ch_acp_i2s = rtd->ch1; 333 ch_acp_sysmem = rtd->ch2; 334 } 335 /* Configure System memory <-> ACP SRAM DMA descriptors */ 336 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 337 rtd->direction, rtd->pte_offset, 338 ch_acp_sysmem, rtd->sram_bank, 339 rtd->dma_dscr_idx_1, asic_type); 340 /* Configure ACP SRAM <-> I2S DMA descriptors */ 341 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 342 rtd->direction, rtd->sram_bank, 343 rtd->destination, ch_acp_i2s, 344 rtd->dma_dscr_idx_2, asic_type); 345 } 346 347 static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, 348 u16 cap_channel) 349 { 350 u32 val, ch_reg, imr_reg, res_reg; 351 352 switch (cap_channel) { 353 case CAP_CHANNEL1: 354 ch_reg = mmACP_I2SMICSP_RER1; 355 res_reg = mmACP_I2SMICSP_RCR1; 356 imr_reg = mmACP_I2SMICSP_IMR1; 357 break; 358 case CAP_CHANNEL0: 359 default: 360 ch_reg = mmACP_I2SMICSP_RER0; 361 res_reg = mmACP_I2SMICSP_RCR0; 362 imr_reg = mmACP_I2SMICSP_IMR0; 363 break; 364 } 365 val = acp_reg_read(acp_mmio, 366 mmACP_I2S_16BIT_RESOLUTION_EN); 367 if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { 368 acp_reg_write(0x0, acp_mmio, ch_reg); 369 /* Set 16bit resolution on capture */ 370 acp_reg_write(0x2, acp_mmio, res_reg); 371 } 372 val = acp_reg_read(acp_mmio, imr_reg); 373 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 374 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 375 acp_reg_write(val, acp_mmio, imr_reg); 376 acp_reg_write(0x1, acp_mmio, ch_reg); 377 } 378 379 static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, 380 u16 cap_channel) 381 { 382 u32 val, ch_reg, imr_reg; 383 384 switch (cap_channel) { 385 case CAP_CHANNEL1: 386 imr_reg = mmACP_I2SMICSP_IMR1; 387 ch_reg = mmACP_I2SMICSP_RER1; 388 break; 389 case CAP_CHANNEL0: 390 default: 391 imr_reg = mmACP_I2SMICSP_IMR0; 392 ch_reg = mmACP_I2SMICSP_RER0; 393 break; 394 } 395 val = acp_reg_read(acp_mmio, imr_reg); 396 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 397 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 398 acp_reg_write(val, acp_mmio, imr_reg); 399 acp_reg_write(0x0, acp_mmio, ch_reg); 400 } 401 402 /* Start a given DMA channel transfer */ 403 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular) 404 { 405 u32 dma_ctrl; 406 407 /* read the dma control register and disable the channel run field */ 408 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 409 410 /* Invalidating the DAGB cache */ 411 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 412 413 /* 414 * configure the DMA channel and start the DMA transfer 415 * set dmachrun bit to start the transfer and enable the 416 * interrupt on completion of the dma transfer 417 */ 418 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 419 420 switch (ch_num) { 421 case ACP_TO_I2S_DMA_CH_NUM: 422 case I2S_TO_ACP_DMA_CH_NUM: 423 case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: 424 case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: 425 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 426 break; 427 default: 428 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 429 break; 430 } 431 432 /* enable for ACP to SRAM DMA channel */ 433 if (is_circular == true) 434 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 435 else 436 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 437 438 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 439 } 440 441 /* Stop a given DMA channel transfer */ 442 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 443 { 444 u32 dma_ctrl; 445 u32 dma_ch_sts; 446 u32 count = ACP_DMA_RESET_TIME; 447 448 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 449 450 /* 451 * clear the dma control register fields before writing zero 452 * in reset bit 453 */ 454 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 455 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 456 457 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 458 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 459 460 if (dma_ch_sts & BIT(ch_num)) { 461 /* 462 * set the reset bit for this channel to stop the dma 463 * transfer 464 */ 465 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 466 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 467 } 468 469 /* check the channel status bit for some time and return the status */ 470 while (true) { 471 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 472 if (!(dma_ch_sts & BIT(ch_num))) { 473 /* 474 * clear the reset flag after successfully stopping 475 * the dma transfer and break from the loop 476 */ 477 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 478 479 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 480 + ch_num); 481 break; 482 } 483 if (--count == 0) { 484 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 485 return -ETIMEDOUT; 486 } 487 udelay(100); 488 } 489 return 0; 490 } 491 492 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 493 bool power_on) 494 { 495 u32 val, req_reg, sts_reg, sts_reg_mask; 496 u32 loops = 1000; 497 498 if (bank < 32) { 499 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 500 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 501 sts_reg_mask = 0xFFFFFFFF; 502 503 } else { 504 bank -= 32; 505 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 506 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 507 sts_reg_mask = 0x0000FFFF; 508 } 509 510 val = acp_reg_read(acp_mmio, req_reg); 511 if (val & (1 << bank)) { 512 /* bank is in off state */ 513 if (power_on == true) 514 /* request to on */ 515 val &= ~(1 << bank); 516 else 517 /* request to off */ 518 return; 519 } else { 520 /* bank is in on state */ 521 if (power_on == false) 522 /* request to off */ 523 val |= 1 << bank; 524 else 525 /* request to on */ 526 return; 527 } 528 acp_reg_write(val, acp_mmio, req_reg); 529 530 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 531 if (!loops--) { 532 pr_err("ACP SRAM bank %d state change failed\n", bank); 533 break; 534 } 535 cpu_relax(); 536 } 537 } 538 539 /* Initialize and bring ACP hardware to default state. */ 540 static int acp_init(void __iomem *acp_mmio, u32 asic_type) 541 { 542 u16 bank; 543 u32 val, count, sram_pte_offset; 544 545 /* Assert Soft reset of ACP */ 546 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 547 548 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 549 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 550 551 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 552 while (true) { 553 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 554 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 555 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 556 break; 557 if (--count == 0) { 558 pr_err("Failed to reset ACP\n"); 559 return -ETIMEDOUT; 560 } 561 udelay(100); 562 } 563 564 /* Enable clock to ACP and wait until the clock is enabled */ 565 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 566 val = val | ACP_CONTROL__ClkEn_MASK; 567 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 568 569 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 570 571 while (true) { 572 val = acp_reg_read(acp_mmio, mmACP_STATUS); 573 if (val & (u32)0x1) 574 break; 575 if (--count == 0) { 576 pr_err("Failed to reset ACP\n"); 577 return -ETIMEDOUT; 578 } 579 udelay(100); 580 } 581 582 /* Deassert the SOFT RESET flags */ 583 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 584 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 585 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 586 587 /* For BT instance change pins from UART to BT */ 588 if (!bt_uart_enable) { 589 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); 590 val |= ACP_BT_UART_PAD_SELECT_MASK; 591 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); 592 } 593 594 /* initiailize Onion control DAGB register */ 595 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 596 mmACP_AXI2DAGB_ONION_CNTL); 597 598 /* initiailize Garlic control DAGB registers */ 599 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 600 mmACP_AXI2DAGB_GARLIC_CNTL); 601 602 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 603 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 604 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 605 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 606 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 607 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 608 mmACP_DAGB_PAGE_SIZE_GRP_1); 609 610 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 611 mmACP_DMA_DESC_BASE_ADDR); 612 613 /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 614 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 615 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 616 acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 617 618 /* 619 * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 620 * Now, turn off all of them. This can't be done in 'poweron' of 621 * ACP pm domain, as this requires ACP to be initialized. 622 * For Stoney, Memory gating is disabled,i.e SRAM Banks 623 * won't be turned off. The default state for SRAM banks is ON. 624 * Setting SRAM bank state code skipped for STONEY platform. 625 */ 626 if (asic_type != CHIP_STONEY) { 627 for (bank = 1; bank < 48; bank++) 628 acp_set_sram_bank_state(acp_mmio, bank, false); 629 } 630 return 0; 631 } 632 633 /* Deinitialize ACP */ 634 static int acp_deinit(void __iomem *acp_mmio) 635 { 636 u32 val; 637 u32 count; 638 639 /* Assert Soft reset of ACP */ 640 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 641 642 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 643 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 644 645 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 646 while (true) { 647 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 648 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 649 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 650 break; 651 if (--count == 0) { 652 pr_err("Failed to reset ACP\n"); 653 return -ETIMEDOUT; 654 } 655 udelay(100); 656 } 657 /* Disable ACP clock */ 658 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 659 val &= ~ACP_CONTROL__ClkEn_MASK; 660 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 661 662 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 663 664 while (true) { 665 val = acp_reg_read(acp_mmio, mmACP_STATUS); 666 if (!(val & (u32)0x1)) 667 break; 668 if (--count == 0) { 669 pr_err("Failed to reset ACP\n"); 670 return -ETIMEDOUT; 671 } 672 udelay(100); 673 } 674 return 0; 675 } 676 677 /* ACP DMA irq handler routine for playback, capture usecases */ 678 static irqreturn_t dma_irq_handler(int irq, void *arg) 679 { 680 u16 dscr_idx; 681 u32 intr_flag, ext_intr_status; 682 struct audio_drv_data *irq_data; 683 void __iomem *acp_mmio; 684 struct device *dev = arg; 685 bool valid_irq = false; 686 687 irq_data = dev_get_drvdata(dev); 688 acp_mmio = irq_data->acp_mmio; 689 690 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 691 intr_flag = (((ext_intr_status & 692 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 693 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 694 695 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 696 valid_irq = true; 697 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 698 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 699 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 700 } 701 702 if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { 703 valid_irq = true; 704 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); 705 acp_reg_write((intr_flag & 706 BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, 707 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 708 } 709 710 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 711 valid_irq = true; 712 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) == 713 CAPTURE_START_DMA_DESCR_CH15) 714 dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 715 else 716 dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 717 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 718 1, 0); 719 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 720 721 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 722 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 723 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 724 } 725 726 if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { 727 valid_irq = true; 728 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) == 729 CAPTURE_START_DMA_DESCR_CH11) 730 dscr_idx = CAPTURE_END_DMA_DESCR_CH10; 731 else 732 dscr_idx = CAPTURE_START_DMA_DESCR_CH10; 733 config_acp_dma_channel(acp_mmio, 734 ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 735 dscr_idx, 1, 0); 736 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 737 false); 738 739 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); 740 acp_reg_write((intr_flag & 741 BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, 742 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 743 } 744 745 if (valid_irq) 746 return IRQ_HANDLED; 747 else 748 return IRQ_NONE; 749 } 750 751 static int acp_dma_open(struct snd_pcm_substream *substream) 752 { 753 u16 bank; 754 int ret = 0; 755 struct snd_pcm_runtime *runtime = substream->runtime; 756 struct snd_soc_pcm_runtime *prtd = substream->private_data; 757 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 758 DRV_NAME); 759 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 760 struct audio_substream_data *adata = 761 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 762 if (!adata) 763 return -ENOMEM; 764 765 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 766 switch (intr_data->asic_type) { 767 case CHIP_STONEY: 768 runtime->hw = acp_st_pcm_hardware_playback; 769 break; 770 default: 771 runtime->hw = acp_pcm_hardware_playback; 772 } 773 } else { 774 switch (intr_data->asic_type) { 775 case CHIP_STONEY: 776 runtime->hw = acp_st_pcm_hardware_capture; 777 break; 778 default: 779 runtime->hw = acp_pcm_hardware_capture; 780 } 781 } 782 783 ret = snd_pcm_hw_constraint_integer(runtime, 784 SNDRV_PCM_HW_PARAM_PERIODS); 785 if (ret < 0) { 786 dev_err(component->dev, "set integer constraint failed\n"); 787 kfree(adata); 788 return ret; 789 } 790 791 adata->acp_mmio = intr_data->acp_mmio; 792 runtime->private_data = adata; 793 794 /* 795 * Enable ACP irq, when neither playback or capture streams are 796 * active by the time when a new stream is being opened. 797 * This enablement is not required for another stream, if current 798 * stream is not closed 799 */ 800 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && 801 !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) 802 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 803 804 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 805 /* 806 * For Stoney, Memory gating is disabled,i.e SRAM Banks 807 * won't be turned off. The default state for SRAM banks is ON. 808 * Setting SRAM bank state code skipped for STONEY platform. 809 */ 810 if (intr_data->asic_type != CHIP_STONEY) { 811 for (bank = 1; bank <= 4; bank++) 812 acp_set_sram_bank_state(intr_data->acp_mmio, 813 bank, true); 814 } 815 } else { 816 if (intr_data->asic_type != CHIP_STONEY) { 817 for (bank = 5; bank <= 8; bank++) 818 acp_set_sram_bank_state(intr_data->acp_mmio, 819 bank, true); 820 } 821 } 822 823 return 0; 824 } 825 826 static int acp_dma_hw_params(struct snd_pcm_substream *substream, 827 struct snd_pcm_hw_params *params) 828 { 829 int status; 830 uint64_t size; 831 u32 val = 0; 832 struct page *pg; 833 struct snd_pcm_runtime *runtime; 834 struct audio_substream_data *rtd; 835 struct snd_soc_pcm_runtime *prtd = substream->private_data; 836 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 837 DRV_NAME); 838 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 839 struct snd_soc_card *card = prtd->card; 840 struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); 841 842 runtime = substream->runtime; 843 rtd = runtime->private_data; 844 845 if (WARN_ON(!rtd)) 846 return -EINVAL; 847 848 if (pinfo) { 849 rtd->i2s_instance = pinfo->i2s_instance; 850 rtd->capture_channel = pinfo->capture_channel; 851 } 852 if (adata->asic_type == CHIP_STONEY) { 853 val = acp_reg_read(adata->acp_mmio, 854 mmACP_I2S_16BIT_RESOLUTION_EN); 855 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 856 switch (rtd->i2s_instance) { 857 case I2S_BT_INSTANCE: 858 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 859 break; 860 case I2S_SP_INSTANCE: 861 default: 862 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 863 } 864 } else { 865 switch (rtd->i2s_instance) { 866 case I2S_BT_INSTANCE: 867 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 868 break; 869 case I2S_SP_INSTANCE: 870 default: 871 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 872 } 873 } 874 acp_reg_write(val, adata->acp_mmio, 875 mmACP_I2S_16BIT_RESOLUTION_EN); 876 } 877 878 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 879 switch (rtd->i2s_instance) { 880 case I2S_BT_INSTANCE: 881 rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; 882 rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; 883 rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; 884 rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; 885 rtd->destination = TO_BLUETOOTH; 886 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; 887 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; 888 rtd->byte_cnt_high_reg_offset = 889 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; 890 rtd->byte_cnt_low_reg_offset = 891 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; 892 adata->play_i2sbt_stream = substream; 893 break; 894 case I2S_SP_INSTANCE: 895 default: 896 switch (adata->asic_type) { 897 case CHIP_STONEY: 898 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 899 break; 900 default: 901 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 902 } 903 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 904 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 905 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 906 rtd->destination = TO_ACP_I2S_1; 907 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 908 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 909 rtd->byte_cnt_high_reg_offset = 910 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 911 rtd->byte_cnt_low_reg_offset = 912 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 913 adata->play_i2ssp_stream = substream; 914 } 915 } else { 916 switch (rtd->i2s_instance) { 917 case I2S_BT_INSTANCE: 918 rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; 919 rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; 920 rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; 921 rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; 922 rtd->destination = FROM_BLUETOOTH; 923 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; 924 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; 925 rtd->byte_cnt_high_reg_offset = 926 mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; 927 rtd->byte_cnt_low_reg_offset = 928 mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; 929 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11; 930 adata->capture_i2sbt_stream = substream; 931 break; 932 case I2S_SP_INSTANCE: 933 default: 934 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 935 rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; 936 rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; 937 switch (adata->asic_type) { 938 case CHIP_STONEY: 939 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 940 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 941 break; 942 default: 943 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 944 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 945 } 946 rtd->destination = FROM_ACP_I2S_1; 947 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 948 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 949 rtd->byte_cnt_high_reg_offset = 950 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 951 rtd->byte_cnt_low_reg_offset = 952 mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 953 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15; 954 adata->capture_i2ssp_stream = substream; 955 } 956 } 957 958 size = params_buffer_bytes(params); 959 status = snd_pcm_lib_malloc_pages(substream, size); 960 if (status < 0) 961 return status; 962 963 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 964 pg = virt_to_page(substream->dma_buffer.area); 965 966 if (pg) { 967 acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 968 /* Save for runtime private data */ 969 rtd->pg = pg; 970 rtd->order = get_order(size); 971 972 /* Fill the page table entries in ACP SRAM */ 973 rtd->pg = pg; 974 rtd->size = size; 975 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 976 rtd->direction = substream->stream; 977 978 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 979 status = 0; 980 } else { 981 status = -ENOMEM; 982 } 983 return status; 984 } 985 986 static int acp_dma_hw_free(struct snd_pcm_substream *substream) 987 { 988 return snd_pcm_lib_free_pages(substream); 989 } 990 991 static u64 acp_get_byte_count(struct audio_substream_data *rtd) 992 { 993 union acp_dma_count byte_count; 994 995 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 996 rtd->byte_cnt_high_reg_offset); 997 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 998 rtd->byte_cnt_low_reg_offset); 999 return byte_count.bytescount; 1000 } 1001 1002 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 1003 { 1004 u32 buffersize; 1005 u32 pos = 0; 1006 u64 bytescount = 0; 1007 u16 dscr; 1008 u32 period_bytes, delay; 1009 1010 struct snd_pcm_runtime *runtime = substream->runtime; 1011 struct audio_substream_data *rtd = runtime->private_data; 1012 1013 if (!rtd) 1014 return -EINVAL; 1015 1016 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1017 period_bytes = frames_to_bytes(runtime, runtime->period_size); 1018 dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr); 1019 if (dscr == rtd->dma_dscr_idx_1) 1020 pos = period_bytes; 1021 else 1022 pos = 0; 1023 bytescount = acp_get_byte_count(rtd); 1024 if (bytescount > rtd->bytescount) 1025 bytescount -= rtd->bytescount; 1026 delay = do_div(bytescount, period_bytes); 1027 runtime->delay = bytes_to_frames(runtime, delay); 1028 } else { 1029 buffersize = frames_to_bytes(runtime, runtime->buffer_size); 1030 bytescount = acp_get_byte_count(rtd); 1031 if (bytescount > rtd->bytescount) 1032 bytescount -= rtd->bytescount; 1033 pos = do_div(bytescount, buffersize); 1034 } 1035 return bytes_to_frames(runtime, pos); 1036 } 1037 1038 static int acp_dma_mmap(struct snd_pcm_substream *substream, 1039 struct vm_area_struct *vma) 1040 { 1041 return snd_pcm_lib_default_mmap(substream, vma); 1042 } 1043 1044 static int acp_dma_prepare(struct snd_pcm_substream *substream) 1045 { 1046 struct snd_pcm_runtime *runtime = substream->runtime; 1047 struct audio_substream_data *rtd = runtime->private_data; 1048 u16 ch_acp_sysmem, ch_acp_i2s; 1049 1050 if (!rtd) 1051 return -EINVAL; 1052 1053 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 1054 ch_acp_sysmem = rtd->ch1; 1055 ch_acp_i2s = rtd->ch2; 1056 } else { 1057 ch_acp_i2s = rtd->ch1; 1058 ch_acp_sysmem = rtd->ch2; 1059 } 1060 config_acp_dma_channel(rtd->acp_mmio, 1061 ch_acp_sysmem, 1062 rtd->dma_dscr_idx_1, 1063 NUM_DSCRS_PER_CHANNEL, 0); 1064 config_acp_dma_channel(rtd->acp_mmio, 1065 ch_acp_i2s, 1066 rtd->dma_dscr_idx_2, 1067 NUM_DSCRS_PER_CHANNEL, 0); 1068 return 0; 1069 } 1070 1071 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 1072 { 1073 int ret; 1074 1075 struct snd_pcm_runtime *runtime = substream->runtime; 1076 struct audio_substream_data *rtd = runtime->private_data; 1077 1078 if (!rtd) 1079 return -EINVAL; 1080 switch (cmd) { 1081 case SNDRV_PCM_TRIGGER_START: 1082 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1083 case SNDRV_PCM_TRIGGER_RESUME: 1084 rtd->bytescount = acp_get_byte_count(rtd); 1085 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1086 if (rtd->capture_channel == CAP_CHANNEL0) { 1087 acp_dma_cap_channel_disable(rtd->acp_mmio, 1088 CAP_CHANNEL1); 1089 acp_dma_cap_channel_enable(rtd->acp_mmio, 1090 CAP_CHANNEL0); 1091 } 1092 if (rtd->capture_channel == CAP_CHANNEL1) { 1093 acp_dma_cap_channel_disable(rtd->acp_mmio, 1094 CAP_CHANNEL0); 1095 acp_dma_cap_channel_enable(rtd->acp_mmio, 1096 CAP_CHANNEL1); 1097 } 1098 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1099 } else { 1100 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1101 acp_dma_start(rtd->acp_mmio, rtd->ch2, true); 1102 } 1103 ret = 0; 1104 break; 1105 case SNDRV_PCM_TRIGGER_STOP: 1106 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1107 case SNDRV_PCM_TRIGGER_SUSPEND: 1108 acp_dma_stop(rtd->acp_mmio, rtd->ch2); 1109 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 1110 break; 1111 default: 1112 ret = -EINVAL; 1113 } 1114 return ret; 1115 } 1116 1117 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 1118 { 1119 int ret; 1120 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, 1121 DRV_NAME); 1122 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1123 1124 switch (adata->asic_type) { 1125 case CHIP_STONEY: 1126 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 1127 SNDRV_DMA_TYPE_DEV, 1128 NULL, ST_MIN_BUFFER, 1129 ST_MAX_BUFFER); 1130 break; 1131 default: 1132 ret = snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 1133 SNDRV_DMA_TYPE_DEV, 1134 NULL, MIN_BUFFER, 1135 MAX_BUFFER); 1136 break; 1137 } 1138 if (ret < 0) 1139 dev_err(component->dev, 1140 "buffer preallocation failure error:%d\n", ret); 1141 return ret; 1142 } 1143 1144 static int acp_dma_close(struct snd_pcm_substream *substream) 1145 { 1146 u16 bank; 1147 struct snd_pcm_runtime *runtime = substream->runtime; 1148 struct audio_substream_data *rtd = runtime->private_data; 1149 struct snd_soc_pcm_runtime *prtd = substream->private_data; 1150 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 1151 DRV_NAME); 1152 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1153 1154 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1155 switch (rtd->i2s_instance) { 1156 case I2S_BT_INSTANCE: 1157 adata->play_i2sbt_stream = NULL; 1158 break; 1159 case I2S_SP_INSTANCE: 1160 default: 1161 adata->play_i2ssp_stream = NULL; 1162 /* 1163 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1164 * won't be turned off. The default state for SRAM banks 1165 * is ON.Setting SRAM bank state code skipped for STONEY 1166 * platform. Added condition checks for Carrizo platform 1167 * only. 1168 */ 1169 if (adata->asic_type != CHIP_STONEY) { 1170 for (bank = 1; bank <= 4; bank++) 1171 acp_set_sram_bank_state(adata->acp_mmio, 1172 bank, false); 1173 } 1174 } 1175 } else { 1176 switch (rtd->i2s_instance) { 1177 case I2S_BT_INSTANCE: 1178 adata->capture_i2sbt_stream = NULL; 1179 break; 1180 case I2S_SP_INSTANCE: 1181 default: 1182 adata->capture_i2ssp_stream = NULL; 1183 if (adata->asic_type != CHIP_STONEY) { 1184 for (bank = 5; bank <= 8; bank++) 1185 acp_set_sram_bank_state(adata->acp_mmio, 1186 bank, false); 1187 } 1188 } 1189 } 1190 1191 /* 1192 * Disable ACP irq, when the current stream is being closed and 1193 * another stream is also not active. 1194 */ 1195 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && 1196 !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) 1197 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1198 kfree(rtd); 1199 return 0; 1200 } 1201 1202 static const struct snd_pcm_ops acp_dma_ops = { 1203 .open = acp_dma_open, 1204 .close = acp_dma_close, 1205 .ioctl = snd_pcm_lib_ioctl, 1206 .hw_params = acp_dma_hw_params, 1207 .hw_free = acp_dma_hw_free, 1208 .trigger = acp_dma_trigger, 1209 .pointer = acp_dma_pointer, 1210 .mmap = acp_dma_mmap, 1211 .prepare = acp_dma_prepare, 1212 }; 1213 1214 static const struct snd_soc_component_driver acp_asoc_platform = { 1215 .name = DRV_NAME, 1216 .ops = &acp_dma_ops, 1217 .pcm_new = acp_dma_new, 1218 }; 1219 1220 static int acp_audio_probe(struct platform_device *pdev) 1221 { 1222 int status; 1223 struct audio_drv_data *audio_drv_data; 1224 struct resource *res; 1225 const u32 *pdata = pdev->dev.platform_data; 1226 1227 if (!pdata) { 1228 dev_err(&pdev->dev, "Missing platform data\n"); 1229 return -ENODEV; 1230 } 1231 1232 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 1233 GFP_KERNEL); 1234 if (!audio_drv_data) 1235 return -ENOMEM; 1236 1237 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1238 audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 1239 if (IS_ERR(audio_drv_data->acp_mmio)) 1240 return PTR_ERR(audio_drv_data->acp_mmio); 1241 1242 /* 1243 * The following members gets populated in device 'open' 1244 * function. Till then interrupts are disabled in 'acp_init' 1245 * and device doesn't generate any interrupts. 1246 */ 1247 1248 audio_drv_data->play_i2ssp_stream = NULL; 1249 audio_drv_data->capture_i2ssp_stream = NULL; 1250 audio_drv_data->play_i2sbt_stream = NULL; 1251 audio_drv_data->capture_i2sbt_stream = NULL; 1252 1253 audio_drv_data->asic_type = *pdata; 1254 1255 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1256 if (!res) { 1257 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 1258 return -ENODEV; 1259 } 1260 1261 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 1262 0, "ACP_IRQ", &pdev->dev); 1263 if (status) { 1264 dev_err(&pdev->dev, "ACP IRQ request failed\n"); 1265 return status; 1266 } 1267 1268 dev_set_drvdata(&pdev->dev, audio_drv_data); 1269 1270 /* Initialize the ACP */ 1271 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 1272 if (status) { 1273 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 1274 return status; 1275 } 1276 1277 status = devm_snd_soc_register_component(&pdev->dev, 1278 &acp_asoc_platform, NULL, 0); 1279 if (status != 0) { 1280 dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 1281 return status; 1282 } 1283 1284 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 1285 pm_runtime_use_autosuspend(&pdev->dev); 1286 pm_runtime_enable(&pdev->dev); 1287 1288 return status; 1289 } 1290 1291 static int acp_audio_remove(struct platform_device *pdev) 1292 { 1293 int status; 1294 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 1295 1296 status = acp_deinit(adata->acp_mmio); 1297 if (status) 1298 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 1299 pm_runtime_disable(&pdev->dev); 1300 1301 return 0; 1302 } 1303 1304 static int acp_pcm_resume(struct device *dev) 1305 { 1306 u16 bank; 1307 int status; 1308 struct audio_substream_data *rtd; 1309 struct audio_drv_data *adata = dev_get_drvdata(dev); 1310 1311 status = acp_init(adata->acp_mmio, adata->asic_type); 1312 if (status) { 1313 dev_err(dev, "ACP Init failed status:%d\n", status); 1314 return status; 1315 } 1316 1317 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 1318 /* 1319 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1320 * won't be turned off. The default state for SRAM banks is ON. 1321 * Setting SRAM bank state code skipped for STONEY platform. 1322 */ 1323 if (adata->asic_type != CHIP_STONEY) { 1324 for (bank = 1; bank <= 4; bank++) 1325 acp_set_sram_bank_state(adata->acp_mmio, bank, 1326 true); 1327 } 1328 rtd = adata->play_i2ssp_stream->runtime->private_data; 1329 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1330 } 1331 if (adata->capture_i2ssp_stream && 1332 adata->capture_i2ssp_stream->runtime) { 1333 if (adata->asic_type != CHIP_STONEY) { 1334 for (bank = 5; bank <= 8; bank++) 1335 acp_set_sram_bank_state(adata->acp_mmio, bank, 1336 true); 1337 } 1338 rtd = adata->capture_i2ssp_stream->runtime->private_data; 1339 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1340 } 1341 if (adata->asic_type != CHIP_CARRIZO) { 1342 if (adata->play_i2sbt_stream && 1343 adata->play_i2sbt_stream->runtime) { 1344 rtd = adata->play_i2sbt_stream->runtime->private_data; 1345 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1346 } 1347 if (adata->capture_i2sbt_stream && 1348 adata->capture_i2sbt_stream->runtime) { 1349 rtd = adata->capture_i2sbt_stream->runtime->private_data; 1350 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1351 } 1352 } 1353 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1354 return 0; 1355 } 1356 1357 static int acp_pcm_runtime_suspend(struct device *dev) 1358 { 1359 int status; 1360 struct audio_drv_data *adata = dev_get_drvdata(dev); 1361 1362 status = acp_deinit(adata->acp_mmio); 1363 if (status) 1364 dev_err(dev, "ACP Deinit failed status:%d\n", status); 1365 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1366 return 0; 1367 } 1368 1369 static int acp_pcm_runtime_resume(struct device *dev) 1370 { 1371 int status; 1372 struct audio_drv_data *adata = dev_get_drvdata(dev); 1373 1374 status = acp_init(adata->acp_mmio, adata->asic_type); 1375 if (status) { 1376 dev_err(dev, "ACP Init failed status:%d\n", status); 1377 return status; 1378 } 1379 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1380 return 0; 1381 } 1382 1383 static const struct dev_pm_ops acp_pm_ops = { 1384 .resume = acp_pcm_resume, 1385 .runtime_suspend = acp_pcm_runtime_suspend, 1386 .runtime_resume = acp_pcm_runtime_resume, 1387 }; 1388 1389 static struct platform_driver acp_dma_driver = { 1390 .probe = acp_audio_probe, 1391 .remove = acp_audio_remove, 1392 .driver = { 1393 .name = DRV_NAME, 1394 .pm = &acp_pm_ops, 1395 }, 1396 }; 1397 1398 module_platform_driver(acp_dma_driver); 1399 1400 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1401 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 1402 MODULE_DESCRIPTION("AMD ACP PCM Driver"); 1403 MODULE_LICENSE("GPL v2"); 1404 MODULE_ALIAS("platform:"DRV_NAME); 1405