1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AMD ALSA SoC PCM Driver for ACP 2.x 4 * 5 * Copyright 2014-2015 Advanced Micro Devices, Inc. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/sizes.h> 13 #include <linux/pm_runtime.h> 14 15 #include <sound/soc.h> 16 #include <drm/amd_asic_type.h> 17 #include "acp.h" 18 19 #define DRV_NAME "acp_audio_dma" 20 21 #define PLAYBACK_MIN_NUM_PERIODS 2 22 #define PLAYBACK_MAX_NUM_PERIODS 2 23 #define PLAYBACK_MAX_PERIOD_SIZE 16384 24 #define PLAYBACK_MIN_PERIOD_SIZE 1024 25 #define CAPTURE_MIN_NUM_PERIODS 2 26 #define CAPTURE_MAX_NUM_PERIODS 2 27 #define CAPTURE_MAX_PERIOD_SIZE 16384 28 #define CAPTURE_MIN_PERIOD_SIZE 1024 29 30 #define MAX_BUFFER (PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 31 #define MIN_BUFFER MAX_BUFFER 32 33 #define ST_PLAYBACK_MAX_PERIOD_SIZE 4096 34 #define ST_CAPTURE_MAX_PERIOD_SIZE ST_PLAYBACK_MAX_PERIOD_SIZE 35 #define ST_MAX_BUFFER (ST_PLAYBACK_MAX_PERIOD_SIZE * PLAYBACK_MAX_NUM_PERIODS) 36 #define ST_MIN_BUFFER ST_MAX_BUFFER 37 38 #define DRV_NAME "acp_audio_dma" 39 bool bt_uart_enable = true; 40 EXPORT_SYMBOL(bt_uart_enable); 41 42 static const struct snd_pcm_hardware acp_pcm_hardware_playback = { 43 .info = SNDRV_PCM_INFO_INTERLEAVED | 44 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 45 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 46 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 47 .formats = SNDRV_PCM_FMTBIT_S16_LE | 48 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 49 .channels_min = 1, 50 .channels_max = 8, 51 .rates = SNDRV_PCM_RATE_8000_96000, 52 .rate_min = 8000, 53 .rate_max = 96000, 54 .buffer_bytes_max = PLAYBACK_MAX_NUM_PERIODS * PLAYBACK_MAX_PERIOD_SIZE, 55 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 56 .period_bytes_max = PLAYBACK_MAX_PERIOD_SIZE, 57 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 58 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 59 }; 60 61 static const struct snd_pcm_hardware acp_pcm_hardware_capture = { 62 .info = SNDRV_PCM_INFO_INTERLEAVED | 63 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 64 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 65 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 66 .formats = SNDRV_PCM_FMTBIT_S16_LE | 67 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 68 .channels_min = 1, 69 .channels_max = 2, 70 .rates = SNDRV_PCM_RATE_8000_48000, 71 .rate_min = 8000, 72 .rate_max = 48000, 73 .buffer_bytes_max = CAPTURE_MAX_NUM_PERIODS * CAPTURE_MAX_PERIOD_SIZE, 74 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 75 .period_bytes_max = CAPTURE_MAX_PERIOD_SIZE, 76 .periods_min = CAPTURE_MIN_NUM_PERIODS, 77 .periods_max = CAPTURE_MAX_NUM_PERIODS, 78 }; 79 80 static const struct snd_pcm_hardware acp_st_pcm_hardware_playback = { 81 .info = SNDRV_PCM_INFO_INTERLEAVED | 82 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 83 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 84 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 85 .formats = SNDRV_PCM_FMTBIT_S16_LE | 86 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 87 .channels_min = 1, 88 .channels_max = 8, 89 .rates = SNDRV_PCM_RATE_8000_96000, 90 .rate_min = 8000, 91 .rate_max = 96000, 92 .buffer_bytes_max = ST_MAX_BUFFER, 93 .period_bytes_min = PLAYBACK_MIN_PERIOD_SIZE, 94 .period_bytes_max = ST_PLAYBACK_MAX_PERIOD_SIZE, 95 .periods_min = PLAYBACK_MIN_NUM_PERIODS, 96 .periods_max = PLAYBACK_MAX_NUM_PERIODS, 97 }; 98 99 static const struct snd_pcm_hardware acp_st_pcm_hardware_capture = { 100 .info = SNDRV_PCM_INFO_INTERLEAVED | 101 SNDRV_PCM_INFO_BLOCK_TRANSFER | SNDRV_PCM_INFO_MMAP | 102 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_BATCH | 103 SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME, 104 .formats = SNDRV_PCM_FMTBIT_S16_LE | 105 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE, 106 .channels_min = 1, 107 .channels_max = 2, 108 .rates = SNDRV_PCM_RATE_8000_48000, 109 .rate_min = 8000, 110 .rate_max = 48000, 111 .buffer_bytes_max = ST_MAX_BUFFER, 112 .period_bytes_min = CAPTURE_MIN_PERIOD_SIZE, 113 .period_bytes_max = ST_CAPTURE_MAX_PERIOD_SIZE, 114 .periods_min = CAPTURE_MIN_NUM_PERIODS, 115 .periods_max = CAPTURE_MAX_NUM_PERIODS, 116 }; 117 118 static u32 acp_reg_read(void __iomem *acp_mmio, u32 reg) 119 { 120 return readl(acp_mmio + (reg * 4)); 121 } 122 123 static void acp_reg_write(u32 val, void __iomem *acp_mmio, u32 reg) 124 { 125 writel(val, acp_mmio + (reg * 4)); 126 } 127 128 /* 129 * Configure a given dma channel parameters - enable/disable, 130 * number of descriptors, priority 131 */ 132 static void config_acp_dma_channel(void __iomem *acp_mmio, u8 ch_num, 133 u16 dscr_strt_idx, u16 num_dscrs, 134 enum acp_dma_priority_level priority_level) 135 { 136 u32 dma_ctrl; 137 138 /* disable the channel run field */ 139 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 140 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 141 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 142 143 /* program a DMA channel with first descriptor to be processed. */ 144 acp_reg_write((ACP_DMA_DSCR_STRT_IDX_0__DMAChDscrStrtIdx_MASK 145 & dscr_strt_idx), 146 acp_mmio, mmACP_DMA_DSCR_STRT_IDX_0 + ch_num); 147 148 /* 149 * program a DMA channel with the number of descriptors to be 150 * processed in the transfer 151 */ 152 acp_reg_write(ACP_DMA_DSCR_CNT_0__DMAChDscrCnt_MASK & num_dscrs, 153 acp_mmio, mmACP_DMA_DSCR_CNT_0 + ch_num); 154 155 /* set DMA channel priority */ 156 acp_reg_write(priority_level, acp_mmio, mmACP_DMA_PRIO_0 + ch_num); 157 } 158 159 /* Initialize a dma descriptor in SRAM based on descritor information passed */ 160 static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, 161 u16 descr_idx, 162 acp_dma_dscr_transfer_t *descr_info) 163 { 164 u32 sram_offset; 165 166 sram_offset = (descr_idx * sizeof(acp_dma_dscr_transfer_t)); 167 168 /* program the source base address. */ 169 acp_reg_write(sram_offset, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 170 acp_reg_write(descr_info->src, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 171 /* program the destination base address. */ 172 acp_reg_write(sram_offset + 4, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 173 acp_reg_write(descr_info->dest, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 174 175 /* program the number of bytes to be transferred for this descriptor. */ 176 acp_reg_write(sram_offset + 8, acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 177 acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 178 } 179 180 static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) 181 { 182 u32 dma_ctrl; 183 int ret; 184 185 /* clear the reset bit */ 186 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 187 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 188 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 189 /* check the reset bit before programming configuration registers */ 190 ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), 191 dma_ctrl, 192 !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), 193 100, ACP_DMA_RESET_TIME); 194 if (ret < 0) 195 pr_err("Failed to clear reset of channel : %d\n", ch_num); 196 } 197 198 /* 199 * Initialize the DMA descriptor information for transfer between 200 * system memory <-> ACP SRAM 201 */ 202 static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, 203 u32 size, int direction, 204 u32 pte_offset, u16 ch, 205 u32 sram_bank, u16 dma_dscr_idx, 206 u32 asic_type) 207 { 208 u16 i; 209 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 210 211 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 212 dmadscr[i].xfer_val = 0; 213 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 214 dma_dscr_idx = dma_dscr_idx + i; 215 dmadscr[i].dest = sram_bank + (i * (size / 2)); 216 dmadscr[i].src = ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS 217 + (pte_offset * SZ_4K) + (i * (size / 2)); 218 switch (asic_type) { 219 case CHIP_STONEY: 220 dmadscr[i].xfer_val |= 221 (ACP_DMA_ATTR_DAGB_GARLIC_TO_SHAREDMEM << 16) | 222 (size / 2); 223 break; 224 default: 225 dmadscr[i].xfer_val |= 226 (ACP_DMA_ATTR_DAGB_ONION_TO_SHAREDMEM << 16) | 227 (size / 2); 228 } 229 } else { 230 dma_dscr_idx = dma_dscr_idx + i; 231 dmadscr[i].src = sram_bank + (i * (size / 2)); 232 dmadscr[i].dest = 233 ACP_INTERNAL_APERTURE_WINDOW_0_ADDRESS + 234 (pte_offset * SZ_4K) + (i * (size / 2)); 235 switch (asic_type) { 236 case CHIP_STONEY: 237 dmadscr[i].xfer_val |= 238 (ACP_DMA_ATTR_SHARED_MEM_TO_DAGB_GARLIC << 16) | 239 (size / 2); 240 break; 241 default: 242 dmadscr[i].xfer_val |= 243 (ACP_DMA_ATTR_SHAREDMEM_TO_DAGB_ONION << 16) | 244 (size / 2); 245 } 246 } 247 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 248 &dmadscr[i]); 249 } 250 pre_config_reset(acp_mmio, ch); 251 config_acp_dma_channel(acp_mmio, ch, 252 dma_dscr_idx - 1, 253 NUM_DSCRS_PER_CHANNEL, 254 ACP_DMA_PRIORITY_LEVEL_NORMAL); 255 } 256 257 /* 258 * Initialize the DMA descriptor information for transfer between 259 * ACP SRAM <-> I2S 260 */ 261 static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, 262 int direction, u32 sram_bank, 263 u16 destination, u16 ch, 264 u16 dma_dscr_idx, u32 asic_type) 265 { 266 u16 i; 267 acp_dma_dscr_transfer_t dmadscr[NUM_DSCRS_PER_CHANNEL]; 268 269 for (i = 0; i < NUM_DSCRS_PER_CHANNEL; i++) { 270 dmadscr[i].xfer_val = 0; 271 if (direction == SNDRV_PCM_STREAM_PLAYBACK) { 272 dma_dscr_idx = dma_dscr_idx + i; 273 dmadscr[i].src = sram_bank + (i * (size / 2)); 274 /* dmadscr[i].dest is unused by hardware. */ 275 dmadscr[i].dest = 0; 276 dmadscr[i].xfer_val |= BIT(22) | (destination << 16) | 277 (size / 2); 278 } else { 279 dma_dscr_idx = dma_dscr_idx + i; 280 /* dmadscr[i].src is unused by hardware. */ 281 dmadscr[i].src = 0; 282 dmadscr[i].dest = 283 sram_bank + (i * (size / 2)); 284 dmadscr[i].xfer_val |= BIT(22) | 285 (destination << 16) | (size / 2); 286 } 287 config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, 288 &dmadscr[i]); 289 } 290 pre_config_reset(acp_mmio, ch); 291 /* Configure the DMA channel with the above descriptore */ 292 config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, 293 NUM_DSCRS_PER_CHANNEL, 294 ACP_DMA_PRIORITY_LEVEL_NORMAL); 295 } 296 297 /* Create page table entries in ACP SRAM for the allocated memory */ 298 static void acp_pte_config(void __iomem *acp_mmio, dma_addr_t addr, 299 u16 num_of_pages, u32 pte_offset) 300 { 301 u16 page_idx; 302 u32 low; 303 u32 high; 304 u32 offset; 305 306 offset = ACP_DAGB_GRP_SRBM_SRAM_BASE_OFFSET + (pte_offset * 8); 307 for (page_idx = 0; page_idx < (num_of_pages); page_idx++) { 308 /* Load the low address of page int ACP SRAM through SRBM */ 309 acp_reg_write((offset + (page_idx * 8)), 310 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 311 312 low = lower_32_bits(addr); 313 high = upper_32_bits(addr); 314 315 acp_reg_write(low, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 316 317 /* Load the High address of page int ACP SRAM through SRBM */ 318 acp_reg_write((offset + (page_idx * 8) + 4), 319 acp_mmio, mmACP_SRBM_Targ_Idx_Addr); 320 321 /* page enable in ACP */ 322 high |= BIT(31); 323 acp_reg_write(high, acp_mmio, mmACP_SRBM_Targ_Idx_Data); 324 325 /* Move to next physically contiguos page */ 326 addr += PAGE_SIZE; 327 } 328 } 329 330 static void config_acp_dma(void __iomem *acp_mmio, 331 struct audio_substream_data *rtd, 332 u32 asic_type) 333 { 334 u16 ch_acp_sysmem, ch_acp_i2s; 335 336 acp_pte_config(acp_mmio, rtd->dma_addr, rtd->num_of_pages, 337 rtd->pte_offset); 338 339 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 340 ch_acp_sysmem = rtd->ch1; 341 ch_acp_i2s = rtd->ch2; 342 } else { 343 ch_acp_i2s = rtd->ch1; 344 ch_acp_sysmem = rtd->ch2; 345 } 346 /* Configure System memory <-> ACP SRAM DMA descriptors */ 347 set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size, 348 rtd->direction, rtd->pte_offset, 349 ch_acp_sysmem, rtd->sram_bank, 350 rtd->dma_dscr_idx_1, asic_type); 351 /* Configure ACP SRAM <-> I2S DMA descriptors */ 352 set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size, 353 rtd->direction, rtd->sram_bank, 354 rtd->destination, ch_acp_i2s, 355 rtd->dma_dscr_idx_2, asic_type); 356 } 357 358 static void acp_dma_cap_channel_enable(void __iomem *acp_mmio, 359 u16 cap_channel) 360 { 361 u32 val, ch_reg, imr_reg, res_reg; 362 363 switch (cap_channel) { 364 case CAP_CHANNEL1: 365 ch_reg = mmACP_I2SMICSP_RER1; 366 res_reg = mmACP_I2SMICSP_RCR1; 367 imr_reg = mmACP_I2SMICSP_IMR1; 368 break; 369 case CAP_CHANNEL0: 370 default: 371 ch_reg = mmACP_I2SMICSP_RER0; 372 res_reg = mmACP_I2SMICSP_RCR0; 373 imr_reg = mmACP_I2SMICSP_IMR0; 374 break; 375 } 376 val = acp_reg_read(acp_mmio, 377 mmACP_I2S_16BIT_RESOLUTION_EN); 378 if (val & ACP_I2S_MIC_16BIT_RESOLUTION_EN) { 379 acp_reg_write(0x0, acp_mmio, ch_reg); 380 /* Set 16bit resolution on capture */ 381 acp_reg_write(0x2, acp_mmio, res_reg); 382 } 383 val = acp_reg_read(acp_mmio, imr_reg); 384 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 385 val &= ~ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 386 acp_reg_write(val, acp_mmio, imr_reg); 387 acp_reg_write(0x1, acp_mmio, ch_reg); 388 } 389 390 static void acp_dma_cap_channel_disable(void __iomem *acp_mmio, 391 u16 cap_channel) 392 { 393 u32 val, ch_reg, imr_reg; 394 395 switch (cap_channel) { 396 case CAP_CHANNEL1: 397 imr_reg = mmACP_I2SMICSP_IMR1; 398 ch_reg = mmACP_I2SMICSP_RER1; 399 break; 400 case CAP_CHANNEL0: 401 default: 402 imr_reg = mmACP_I2SMICSP_IMR0; 403 ch_reg = mmACP_I2SMICSP_RER0; 404 break; 405 } 406 val = acp_reg_read(acp_mmio, imr_reg); 407 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXDAM_MASK; 408 val |= ACP_I2SMICSP_IMR1__I2SMICSP_RXFOM_MASK; 409 acp_reg_write(val, acp_mmio, imr_reg); 410 acp_reg_write(0x0, acp_mmio, ch_reg); 411 } 412 413 /* Start a given DMA channel transfer */ 414 static void acp_dma_start(void __iomem *acp_mmio, u16 ch_num, bool is_circular) 415 { 416 u32 dma_ctrl; 417 418 /* read the dma control register and disable the channel run field */ 419 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 420 421 /* Invalidating the DAGB cache */ 422 acp_reg_write(1, acp_mmio, mmACP_DAGB_ATU_CTRL); 423 424 /* 425 * configure the DMA channel and start the DMA transfer 426 * set dmachrun bit to start the transfer and enable the 427 * interrupt on completion of the dma transfer 428 */ 429 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRun_MASK; 430 431 switch (ch_num) { 432 case ACP_TO_I2S_DMA_CH_NUM: 433 case I2S_TO_ACP_DMA_CH_NUM: 434 case ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM: 435 case I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM: 436 dma_ctrl |= ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 437 break; 438 default: 439 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 440 break; 441 } 442 443 /* enable for ACP to SRAM DMA channel */ 444 if (is_circular == true) 445 dma_ctrl |= ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 446 else 447 dma_ctrl &= ~ACP_DMA_CNTL_0__Circular_DMA_En_MASK; 448 449 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 450 } 451 452 /* Stop a given DMA channel transfer */ 453 static int acp_dma_stop(void __iomem *acp_mmio, u8 ch_num) 454 { 455 u32 dma_ctrl; 456 u32 dma_ch_sts; 457 u32 count = ACP_DMA_RESET_TIME; 458 459 dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 460 461 /* 462 * clear the dma control register fields before writing zero 463 * in reset bit 464 */ 465 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRun_MASK; 466 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChIOCEn_MASK; 467 468 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 469 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 470 471 if (dma_ch_sts & BIT(ch_num)) { 472 /* 473 * set the reset bit for this channel to stop the dma 474 * transfer 475 */ 476 dma_ctrl |= ACP_DMA_CNTL_0__DMAChRst_MASK; 477 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); 478 } 479 480 /* check the channel status bit for some time and return the status */ 481 while (true) { 482 dma_ch_sts = acp_reg_read(acp_mmio, mmACP_DMA_CH_STS); 483 if (!(dma_ch_sts & BIT(ch_num))) { 484 /* 485 * clear the reset flag after successfully stopping 486 * the dma transfer and break from the loop 487 */ 488 dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; 489 490 acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 491 + ch_num); 492 break; 493 } 494 if (--count == 0) { 495 pr_err("Failed to stop ACP DMA channel : %d\n", ch_num); 496 return -ETIMEDOUT; 497 } 498 udelay(100); 499 } 500 return 0; 501 } 502 503 static void acp_set_sram_bank_state(void __iomem *acp_mmio, u16 bank, 504 bool power_on) 505 { 506 u32 val, req_reg, sts_reg, sts_reg_mask; 507 u32 loops = 1000; 508 509 if (bank < 32) { 510 req_reg = mmACP_MEM_SHUT_DOWN_REQ_LO; 511 sts_reg = mmACP_MEM_SHUT_DOWN_STS_LO; 512 sts_reg_mask = 0xFFFFFFFF; 513 514 } else { 515 bank -= 32; 516 req_reg = mmACP_MEM_SHUT_DOWN_REQ_HI; 517 sts_reg = mmACP_MEM_SHUT_DOWN_STS_HI; 518 sts_reg_mask = 0x0000FFFF; 519 } 520 521 val = acp_reg_read(acp_mmio, req_reg); 522 if (val & (1 << bank)) { 523 /* bank is in off state */ 524 if (power_on == true) 525 /* request to on */ 526 val &= ~(1 << bank); 527 else 528 /* request to off */ 529 return; 530 } else { 531 /* bank is in on state */ 532 if (power_on == false) 533 /* request to off */ 534 val |= 1 << bank; 535 else 536 /* request to on */ 537 return; 538 } 539 acp_reg_write(val, acp_mmio, req_reg); 540 541 while (acp_reg_read(acp_mmio, sts_reg) != sts_reg_mask) { 542 if (!loops--) { 543 pr_err("ACP SRAM bank %d state change failed\n", bank); 544 break; 545 } 546 cpu_relax(); 547 } 548 } 549 550 /* Initialize and bring ACP hardware to default state. */ 551 static int acp_init(void __iomem *acp_mmio, u32 asic_type) 552 { 553 u16 bank; 554 u32 val, count, sram_pte_offset; 555 556 /* Assert Soft reset of ACP */ 557 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 558 559 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 560 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 561 562 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 563 while (true) { 564 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 565 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 566 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 567 break; 568 if (--count == 0) { 569 pr_err("Failed to reset ACP\n"); 570 return -ETIMEDOUT; 571 } 572 udelay(100); 573 } 574 575 /* Enable clock to ACP and wait until the clock is enabled */ 576 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 577 val = val | ACP_CONTROL__ClkEn_MASK; 578 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 579 580 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 581 582 while (true) { 583 val = acp_reg_read(acp_mmio, mmACP_STATUS); 584 if (val & (u32)0x1) 585 break; 586 if (--count == 0) { 587 pr_err("Failed to reset ACP\n"); 588 return -ETIMEDOUT; 589 } 590 udelay(100); 591 } 592 593 /* Deassert the SOFT RESET flags */ 594 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 595 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 596 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 597 598 /* For BT instance change pins from UART to BT */ 599 if (!bt_uart_enable) { 600 val = acp_reg_read(acp_mmio, mmACP_BT_UART_PAD_SEL); 601 val |= ACP_BT_UART_PAD_SELECT_MASK; 602 acp_reg_write(val, acp_mmio, mmACP_BT_UART_PAD_SEL); 603 } 604 605 /* initiailize Onion control DAGB register */ 606 acp_reg_write(ACP_ONION_CNTL_DEFAULT, acp_mmio, 607 mmACP_AXI2DAGB_ONION_CNTL); 608 609 /* initiailize Garlic control DAGB registers */ 610 acp_reg_write(ACP_GARLIC_CNTL_DEFAULT, acp_mmio, 611 mmACP_AXI2DAGB_GARLIC_CNTL); 612 613 sram_pte_offset = ACP_DAGB_GRP_SRAM_BASE_ADDRESS | 614 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBSnoopSel_MASK | 615 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBTargetMemSel_MASK | 616 ACP_DAGB_BASE_ADDR_GRP_1__AXI2DAGBGrpEnable_MASK; 617 acp_reg_write(sram_pte_offset, acp_mmio, mmACP_DAGB_BASE_ADDR_GRP_1); 618 acp_reg_write(ACP_PAGE_SIZE_4K_ENABLE, acp_mmio, 619 mmACP_DAGB_PAGE_SIZE_GRP_1); 620 621 acp_reg_write(ACP_SRAM_BASE_ADDRESS, acp_mmio, 622 mmACP_DMA_DESC_BASE_ADDR); 623 624 /* Num of descriptiors in SRAM 0x4, means 256 descriptors;(64 * 4) */ 625 acp_reg_write(0x4, acp_mmio, mmACP_DMA_DESC_MAX_NUM_DSCR); 626 acp_reg_write(ACP_EXTERNAL_INTR_CNTL__DMAIOCMask_MASK, 627 acp_mmio, mmACP_EXTERNAL_INTR_CNTL); 628 629 /* 630 * When ACP_TILE_P1 is turned on, all SRAM banks get turned on. 631 * Now, turn off all of them. This can't be done in 'poweron' of 632 * ACP pm domain, as this requires ACP to be initialized. 633 * For Stoney, Memory gating is disabled,i.e SRAM Banks 634 * won't be turned off. The default state for SRAM banks is ON. 635 * Setting SRAM bank state code skipped for STONEY platform. 636 */ 637 if (asic_type != CHIP_STONEY) { 638 for (bank = 1; bank < 48; bank++) 639 acp_set_sram_bank_state(acp_mmio, bank, false); 640 } 641 return 0; 642 } 643 644 /* Deinitialize ACP */ 645 static int acp_deinit(void __iomem *acp_mmio) 646 { 647 u32 val; 648 u32 count; 649 650 /* Assert Soft reset of ACP */ 651 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 652 653 val |= ACP_SOFT_RESET__SoftResetAud_MASK; 654 acp_reg_write(val, acp_mmio, mmACP_SOFT_RESET); 655 656 count = ACP_SOFT_RESET_DONE_TIME_OUT_VALUE; 657 while (true) { 658 val = acp_reg_read(acp_mmio, mmACP_SOFT_RESET); 659 if (ACP_SOFT_RESET__SoftResetAudDone_MASK == 660 (val & ACP_SOFT_RESET__SoftResetAudDone_MASK)) 661 break; 662 if (--count == 0) { 663 pr_err("Failed to reset ACP\n"); 664 return -ETIMEDOUT; 665 } 666 udelay(100); 667 } 668 /* Disable ACP clock */ 669 val = acp_reg_read(acp_mmio, mmACP_CONTROL); 670 val &= ~ACP_CONTROL__ClkEn_MASK; 671 acp_reg_write(val, acp_mmio, mmACP_CONTROL); 672 673 count = ACP_CLOCK_EN_TIME_OUT_VALUE; 674 675 while (true) { 676 val = acp_reg_read(acp_mmio, mmACP_STATUS); 677 if (!(val & (u32)0x1)) 678 break; 679 if (--count == 0) { 680 pr_err("Failed to reset ACP\n"); 681 return -ETIMEDOUT; 682 } 683 udelay(100); 684 } 685 return 0; 686 } 687 688 /* ACP DMA irq handler routine for playback, capture usecases */ 689 static irqreturn_t dma_irq_handler(int irq, void *arg) 690 { 691 u16 dscr_idx; 692 u32 intr_flag, ext_intr_status; 693 struct audio_drv_data *irq_data; 694 void __iomem *acp_mmio; 695 struct device *dev = arg; 696 bool valid_irq = false; 697 698 irq_data = dev_get_drvdata(dev); 699 acp_mmio = irq_data->acp_mmio; 700 701 ext_intr_status = acp_reg_read(acp_mmio, mmACP_EXTERNAL_INTR_STAT); 702 intr_flag = (((ext_intr_status & 703 ACP_EXTERNAL_INTR_STAT__DMAIOCStat_MASK) >> 704 ACP_EXTERNAL_INTR_STAT__DMAIOCStat__SHIFT)); 705 706 if ((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) != 0) { 707 valid_irq = true; 708 snd_pcm_period_elapsed(irq_data->play_i2ssp_stream); 709 acp_reg_write((intr_flag & BIT(ACP_TO_I2S_DMA_CH_NUM)) << 16, 710 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 711 } 712 713 if ((intr_flag & BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) != 0) { 714 valid_irq = true; 715 snd_pcm_period_elapsed(irq_data->play_i2sbt_stream); 716 acp_reg_write((intr_flag & 717 BIT(ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM)) << 16, 718 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 719 } 720 721 if ((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) != 0) { 722 valid_irq = true; 723 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_14) == 724 CAPTURE_START_DMA_DESCR_CH15) 725 dscr_idx = CAPTURE_END_DMA_DESCR_CH14; 726 else 727 dscr_idx = CAPTURE_START_DMA_DESCR_CH14; 728 config_acp_dma_channel(acp_mmio, ACP_TO_SYSRAM_CH_NUM, dscr_idx, 729 1, 0); 730 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_CH_NUM, false); 731 732 snd_pcm_period_elapsed(irq_data->capture_i2ssp_stream); 733 acp_reg_write((intr_flag & BIT(I2S_TO_ACP_DMA_CH_NUM)) << 16, 734 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 735 } 736 737 if ((intr_flag & BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) != 0) { 738 valid_irq = true; 739 if (acp_reg_read(acp_mmio, mmACP_DMA_CUR_DSCR_10) == 740 CAPTURE_START_DMA_DESCR_CH11) 741 dscr_idx = CAPTURE_END_DMA_DESCR_CH10; 742 else 743 dscr_idx = CAPTURE_START_DMA_DESCR_CH10; 744 config_acp_dma_channel(acp_mmio, 745 ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 746 dscr_idx, 1, 0); 747 acp_dma_start(acp_mmio, ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM, 748 false); 749 750 snd_pcm_period_elapsed(irq_data->capture_i2sbt_stream); 751 acp_reg_write((intr_flag & 752 BIT(I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM)) << 16, 753 acp_mmio, mmACP_EXTERNAL_INTR_STAT); 754 } 755 756 if (valid_irq) 757 return IRQ_HANDLED; 758 else 759 return IRQ_NONE; 760 } 761 762 static int acp_dma_open(struct snd_pcm_substream *substream) 763 { 764 u16 bank; 765 int ret = 0; 766 struct snd_pcm_runtime *runtime = substream->runtime; 767 struct snd_soc_pcm_runtime *prtd = substream->private_data; 768 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 769 DRV_NAME); 770 struct audio_drv_data *intr_data = dev_get_drvdata(component->dev); 771 struct audio_substream_data *adata = 772 kzalloc(sizeof(struct audio_substream_data), GFP_KERNEL); 773 if (!adata) 774 return -ENOMEM; 775 776 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 777 switch (intr_data->asic_type) { 778 case CHIP_STONEY: 779 runtime->hw = acp_st_pcm_hardware_playback; 780 break; 781 default: 782 runtime->hw = acp_pcm_hardware_playback; 783 } 784 } else { 785 switch (intr_data->asic_type) { 786 case CHIP_STONEY: 787 runtime->hw = acp_st_pcm_hardware_capture; 788 break; 789 default: 790 runtime->hw = acp_pcm_hardware_capture; 791 } 792 } 793 794 ret = snd_pcm_hw_constraint_integer(runtime, 795 SNDRV_PCM_HW_PARAM_PERIODS); 796 if (ret < 0) { 797 dev_err(component->dev, "set integer constraint failed\n"); 798 kfree(adata); 799 return ret; 800 } 801 802 adata->acp_mmio = intr_data->acp_mmio; 803 runtime->private_data = adata; 804 805 /* 806 * Enable ACP irq, when neither playback or capture streams are 807 * active by the time when a new stream is being opened. 808 * This enablement is not required for another stream, if current 809 * stream is not closed 810 */ 811 if (!intr_data->play_i2ssp_stream && !intr_data->capture_i2ssp_stream && 812 !intr_data->play_i2sbt_stream && !intr_data->capture_i2sbt_stream) 813 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 814 815 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 816 /* 817 * For Stoney, Memory gating is disabled,i.e SRAM Banks 818 * won't be turned off. The default state for SRAM banks is ON. 819 * Setting SRAM bank state code skipped for STONEY platform. 820 */ 821 if (intr_data->asic_type != CHIP_STONEY) { 822 for (bank = 1; bank <= 4; bank++) 823 acp_set_sram_bank_state(intr_data->acp_mmio, 824 bank, true); 825 } 826 } else { 827 if (intr_data->asic_type != CHIP_STONEY) { 828 for (bank = 5; bank <= 8; bank++) 829 acp_set_sram_bank_state(intr_data->acp_mmio, 830 bank, true); 831 } 832 } 833 834 return 0; 835 } 836 837 static int acp_dma_hw_params(struct snd_pcm_substream *substream, 838 struct snd_pcm_hw_params *params) 839 { 840 int status; 841 uint64_t size; 842 u32 val = 0; 843 struct snd_pcm_runtime *runtime; 844 struct audio_substream_data *rtd; 845 struct snd_soc_pcm_runtime *prtd = substream->private_data; 846 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 847 DRV_NAME); 848 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 849 struct snd_soc_card *card = prtd->card; 850 struct acp_platform_info *pinfo = snd_soc_card_get_drvdata(card); 851 852 runtime = substream->runtime; 853 rtd = runtime->private_data; 854 855 if (WARN_ON(!rtd)) 856 return -EINVAL; 857 858 if (pinfo) { 859 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 860 rtd->i2s_instance = pinfo->play_i2s_instance; 861 } else { 862 rtd->i2s_instance = pinfo->cap_i2s_instance; 863 rtd->capture_channel = pinfo->capture_channel; 864 } 865 } 866 if (adata->asic_type == CHIP_STONEY) { 867 val = acp_reg_read(adata->acp_mmio, 868 mmACP_I2S_16BIT_RESOLUTION_EN); 869 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 870 switch (rtd->i2s_instance) { 871 case I2S_BT_INSTANCE: 872 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 873 break; 874 case I2S_SP_INSTANCE: 875 default: 876 val |= ACP_I2S_SP_16BIT_RESOLUTION_EN; 877 } 878 } else { 879 switch (rtd->i2s_instance) { 880 case I2S_BT_INSTANCE: 881 val |= ACP_I2S_BT_16BIT_RESOLUTION_EN; 882 break; 883 case I2S_SP_INSTANCE: 884 default: 885 val |= ACP_I2S_MIC_16BIT_RESOLUTION_EN; 886 } 887 } 888 acp_reg_write(val, adata->acp_mmio, 889 mmACP_I2S_16BIT_RESOLUTION_EN); 890 } 891 892 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 893 switch (rtd->i2s_instance) { 894 case I2S_BT_INSTANCE: 895 rtd->pte_offset = ACP_ST_BT_PLAYBACK_PTE_OFFSET; 896 rtd->ch1 = SYSRAM_TO_ACP_BT_INSTANCE_CH_NUM; 897 rtd->ch2 = ACP_TO_I2S_DMA_BT_INSTANCE_CH_NUM; 898 rtd->sram_bank = ACP_SRAM_BANK_3_ADDRESS; 899 rtd->destination = TO_BLUETOOTH; 900 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH8; 901 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH9; 902 rtd->byte_cnt_high_reg_offset = 903 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_HIGH; 904 rtd->byte_cnt_low_reg_offset = 905 mmACP_I2S_BT_TRANSMIT_BYTE_CNT_LOW; 906 adata->play_i2sbt_stream = substream; 907 break; 908 case I2S_SP_INSTANCE: 909 default: 910 switch (adata->asic_type) { 911 case CHIP_STONEY: 912 rtd->pte_offset = ACP_ST_PLAYBACK_PTE_OFFSET; 913 break; 914 default: 915 rtd->pte_offset = ACP_PLAYBACK_PTE_OFFSET; 916 } 917 rtd->ch1 = SYSRAM_TO_ACP_CH_NUM; 918 rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM; 919 rtd->sram_bank = ACP_SRAM_BANK_1_ADDRESS; 920 rtd->destination = TO_ACP_I2S_1; 921 rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12; 922 rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13; 923 rtd->byte_cnt_high_reg_offset = 924 mmACP_I2S_TRANSMIT_BYTE_CNT_HIGH; 925 rtd->byte_cnt_low_reg_offset = 926 mmACP_I2S_TRANSMIT_BYTE_CNT_LOW; 927 adata->play_i2ssp_stream = substream; 928 } 929 } else { 930 switch (rtd->i2s_instance) { 931 case I2S_BT_INSTANCE: 932 rtd->pte_offset = ACP_ST_BT_CAPTURE_PTE_OFFSET; 933 rtd->ch1 = I2S_TO_ACP_DMA_BT_INSTANCE_CH_NUM; 934 rtd->ch2 = ACP_TO_SYSRAM_BT_INSTANCE_CH_NUM; 935 rtd->sram_bank = ACP_SRAM_BANK_4_ADDRESS; 936 rtd->destination = FROM_BLUETOOTH; 937 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH10; 938 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH11; 939 rtd->byte_cnt_high_reg_offset = 940 mmACP_I2S_BT_RECEIVE_BYTE_CNT_HIGH; 941 rtd->byte_cnt_low_reg_offset = 942 mmACP_I2S_BT_RECEIVE_BYTE_CNT_LOW; 943 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_11; 944 adata->capture_i2sbt_stream = substream; 945 break; 946 case I2S_SP_INSTANCE: 947 default: 948 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 949 rtd->ch1 = I2S_TO_ACP_DMA_CH_NUM; 950 rtd->ch2 = ACP_TO_SYSRAM_CH_NUM; 951 switch (adata->asic_type) { 952 case CHIP_STONEY: 953 rtd->pte_offset = ACP_ST_CAPTURE_PTE_OFFSET; 954 rtd->sram_bank = ACP_SRAM_BANK_2_ADDRESS; 955 break; 956 default: 957 rtd->pte_offset = ACP_CAPTURE_PTE_OFFSET; 958 rtd->sram_bank = ACP_SRAM_BANK_5_ADDRESS; 959 } 960 rtd->destination = FROM_ACP_I2S_1; 961 rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14; 962 rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15; 963 rtd->byte_cnt_high_reg_offset = 964 mmACP_I2S_RECEIVED_BYTE_CNT_HIGH; 965 rtd->byte_cnt_low_reg_offset = 966 mmACP_I2S_RECEIVED_BYTE_CNT_LOW; 967 rtd->dma_curr_dscr = mmACP_DMA_CUR_DSCR_15; 968 adata->capture_i2ssp_stream = substream; 969 } 970 } 971 972 size = params_buffer_bytes(params); 973 status = snd_pcm_lib_malloc_pages(substream, size); 974 if (status < 0) 975 return status; 976 977 memset(substream->runtime->dma_area, 0, params_buffer_bytes(params)); 978 979 if (substream->dma_buffer.area) { 980 acp_set_sram_bank_state(rtd->acp_mmio, 0, true); 981 /* Save for runtime private data */ 982 rtd->dma_addr = substream->dma_buffer.addr; 983 rtd->order = get_order(size); 984 985 /* Fill the page table entries in ACP SRAM */ 986 rtd->size = size; 987 rtd->num_of_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; 988 rtd->direction = substream->stream; 989 990 config_acp_dma(rtd->acp_mmio, rtd, adata->asic_type); 991 status = 0; 992 } else { 993 status = -ENOMEM; 994 } 995 return status; 996 } 997 998 static int acp_dma_hw_free(struct snd_pcm_substream *substream) 999 { 1000 return snd_pcm_lib_free_pages(substream); 1001 } 1002 1003 static u64 acp_get_byte_count(struct audio_substream_data *rtd) 1004 { 1005 union acp_dma_count byte_count; 1006 1007 byte_count.bcount.high = acp_reg_read(rtd->acp_mmio, 1008 rtd->byte_cnt_high_reg_offset); 1009 byte_count.bcount.low = acp_reg_read(rtd->acp_mmio, 1010 rtd->byte_cnt_low_reg_offset); 1011 return byte_count.bytescount; 1012 } 1013 1014 static snd_pcm_uframes_t acp_dma_pointer(struct snd_pcm_substream *substream) 1015 { 1016 u32 buffersize; 1017 u32 pos = 0; 1018 u64 bytescount = 0; 1019 u16 dscr; 1020 u32 period_bytes, delay; 1021 1022 struct snd_pcm_runtime *runtime = substream->runtime; 1023 struct audio_substream_data *rtd = runtime->private_data; 1024 1025 if (!rtd) 1026 return -EINVAL; 1027 1028 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1029 period_bytes = frames_to_bytes(runtime, runtime->period_size); 1030 bytescount = acp_get_byte_count(rtd); 1031 if (bytescount >= rtd->bytescount) 1032 bytescount -= rtd->bytescount; 1033 if (bytescount < period_bytes) { 1034 pos = 0; 1035 } else { 1036 dscr = acp_reg_read(rtd->acp_mmio, rtd->dma_curr_dscr); 1037 if (dscr == rtd->dma_dscr_idx_1) 1038 pos = period_bytes; 1039 else 1040 pos = 0; 1041 } 1042 if (bytescount > 0) { 1043 delay = do_div(bytescount, period_bytes); 1044 runtime->delay = bytes_to_frames(runtime, delay); 1045 } 1046 } else { 1047 buffersize = frames_to_bytes(runtime, runtime->buffer_size); 1048 bytescount = acp_get_byte_count(rtd); 1049 if (bytescount > rtd->bytescount) 1050 bytescount -= rtd->bytescount; 1051 pos = do_div(bytescount, buffersize); 1052 } 1053 return bytes_to_frames(runtime, pos); 1054 } 1055 1056 static int acp_dma_mmap(struct snd_pcm_substream *substream, 1057 struct vm_area_struct *vma) 1058 { 1059 return snd_pcm_lib_default_mmap(substream, vma); 1060 } 1061 1062 static int acp_dma_prepare(struct snd_pcm_substream *substream) 1063 { 1064 struct snd_pcm_runtime *runtime = substream->runtime; 1065 struct audio_substream_data *rtd = runtime->private_data; 1066 u16 ch_acp_sysmem, ch_acp_i2s; 1067 1068 if (!rtd) 1069 return -EINVAL; 1070 1071 if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) { 1072 ch_acp_sysmem = rtd->ch1; 1073 ch_acp_i2s = rtd->ch2; 1074 } else { 1075 ch_acp_i2s = rtd->ch1; 1076 ch_acp_sysmem = rtd->ch2; 1077 } 1078 config_acp_dma_channel(rtd->acp_mmio, 1079 ch_acp_sysmem, 1080 rtd->dma_dscr_idx_1, 1081 NUM_DSCRS_PER_CHANNEL, 0); 1082 config_acp_dma_channel(rtd->acp_mmio, 1083 ch_acp_i2s, 1084 rtd->dma_dscr_idx_2, 1085 NUM_DSCRS_PER_CHANNEL, 0); 1086 return 0; 1087 } 1088 1089 static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd) 1090 { 1091 int ret; 1092 1093 struct snd_pcm_runtime *runtime = substream->runtime; 1094 struct audio_substream_data *rtd = runtime->private_data; 1095 1096 if (!rtd) 1097 return -EINVAL; 1098 switch (cmd) { 1099 case SNDRV_PCM_TRIGGER_START: 1100 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1101 case SNDRV_PCM_TRIGGER_RESUME: 1102 rtd->bytescount = acp_get_byte_count(rtd); 1103 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 1104 if (rtd->capture_channel == CAP_CHANNEL0) { 1105 acp_dma_cap_channel_disable(rtd->acp_mmio, 1106 CAP_CHANNEL1); 1107 acp_dma_cap_channel_enable(rtd->acp_mmio, 1108 CAP_CHANNEL0); 1109 } 1110 if (rtd->capture_channel == CAP_CHANNEL1) { 1111 acp_dma_cap_channel_disable(rtd->acp_mmio, 1112 CAP_CHANNEL0); 1113 acp_dma_cap_channel_enable(rtd->acp_mmio, 1114 CAP_CHANNEL1); 1115 } 1116 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1117 } else { 1118 acp_dma_start(rtd->acp_mmio, rtd->ch1, true); 1119 acp_dma_start(rtd->acp_mmio, rtd->ch2, true); 1120 } 1121 ret = 0; 1122 break; 1123 case SNDRV_PCM_TRIGGER_STOP: 1124 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1125 case SNDRV_PCM_TRIGGER_SUSPEND: 1126 acp_dma_stop(rtd->acp_mmio, rtd->ch2); 1127 ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1); 1128 break; 1129 default: 1130 ret = -EINVAL; 1131 } 1132 return ret; 1133 } 1134 1135 static int acp_dma_new(struct snd_soc_pcm_runtime *rtd) 1136 { 1137 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, 1138 DRV_NAME); 1139 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1140 struct device *parent = component->dev->parent; 1141 1142 switch (adata->asic_type) { 1143 case CHIP_STONEY: 1144 snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 1145 SNDRV_DMA_TYPE_DEV, 1146 parent, 1147 ST_MIN_BUFFER, 1148 ST_MAX_BUFFER); 1149 break; 1150 default: 1151 snd_pcm_lib_preallocate_pages_for_all(rtd->pcm, 1152 SNDRV_DMA_TYPE_DEV, 1153 parent, 1154 MIN_BUFFER, 1155 MAX_BUFFER); 1156 break; 1157 } 1158 return 0; 1159 } 1160 1161 static int acp_dma_close(struct snd_pcm_substream *substream) 1162 { 1163 u16 bank; 1164 struct snd_pcm_runtime *runtime = substream->runtime; 1165 struct audio_substream_data *rtd = runtime->private_data; 1166 struct snd_soc_pcm_runtime *prtd = substream->private_data; 1167 struct snd_soc_component *component = snd_soc_rtdcom_lookup(prtd, 1168 DRV_NAME); 1169 struct audio_drv_data *adata = dev_get_drvdata(component->dev); 1170 1171 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1172 switch (rtd->i2s_instance) { 1173 case I2S_BT_INSTANCE: 1174 adata->play_i2sbt_stream = NULL; 1175 break; 1176 case I2S_SP_INSTANCE: 1177 default: 1178 adata->play_i2ssp_stream = NULL; 1179 /* 1180 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1181 * won't be turned off. The default state for SRAM banks 1182 * is ON.Setting SRAM bank state code skipped for STONEY 1183 * platform. Added condition checks for Carrizo platform 1184 * only. 1185 */ 1186 if (adata->asic_type != CHIP_STONEY) { 1187 for (bank = 1; bank <= 4; bank++) 1188 acp_set_sram_bank_state(adata->acp_mmio, 1189 bank, false); 1190 } 1191 } 1192 } else { 1193 switch (rtd->i2s_instance) { 1194 case I2S_BT_INSTANCE: 1195 adata->capture_i2sbt_stream = NULL; 1196 break; 1197 case I2S_SP_INSTANCE: 1198 default: 1199 adata->capture_i2ssp_stream = NULL; 1200 if (adata->asic_type != CHIP_STONEY) { 1201 for (bank = 5; bank <= 8; bank++) 1202 acp_set_sram_bank_state(adata->acp_mmio, 1203 bank, false); 1204 } 1205 } 1206 } 1207 1208 /* 1209 * Disable ACP irq, when the current stream is being closed and 1210 * another stream is also not active. 1211 */ 1212 if (!adata->play_i2ssp_stream && !adata->capture_i2ssp_stream && 1213 !adata->play_i2sbt_stream && !adata->capture_i2sbt_stream) 1214 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1215 kfree(rtd); 1216 return 0; 1217 } 1218 1219 static const struct snd_pcm_ops acp_dma_ops = { 1220 .open = acp_dma_open, 1221 .close = acp_dma_close, 1222 .ioctl = snd_pcm_lib_ioctl, 1223 .hw_params = acp_dma_hw_params, 1224 .hw_free = acp_dma_hw_free, 1225 .trigger = acp_dma_trigger, 1226 .pointer = acp_dma_pointer, 1227 .mmap = acp_dma_mmap, 1228 .prepare = acp_dma_prepare, 1229 }; 1230 1231 static const struct snd_soc_component_driver acp_asoc_platform = { 1232 .name = DRV_NAME, 1233 .ops = &acp_dma_ops, 1234 .pcm_new = acp_dma_new, 1235 }; 1236 1237 static int acp_audio_probe(struct platform_device *pdev) 1238 { 1239 int status; 1240 struct audio_drv_data *audio_drv_data; 1241 struct resource *res; 1242 const u32 *pdata = pdev->dev.platform_data; 1243 1244 if (!pdata) { 1245 dev_err(&pdev->dev, "Missing platform data\n"); 1246 return -ENODEV; 1247 } 1248 1249 audio_drv_data = devm_kzalloc(&pdev->dev, sizeof(struct audio_drv_data), 1250 GFP_KERNEL); 1251 if (!audio_drv_data) 1252 return -ENOMEM; 1253 1254 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1255 audio_drv_data->acp_mmio = devm_ioremap_resource(&pdev->dev, res); 1256 if (IS_ERR(audio_drv_data->acp_mmio)) 1257 return PTR_ERR(audio_drv_data->acp_mmio); 1258 1259 /* 1260 * The following members gets populated in device 'open' 1261 * function. Till then interrupts are disabled in 'acp_init' 1262 * and device doesn't generate any interrupts. 1263 */ 1264 1265 audio_drv_data->play_i2ssp_stream = NULL; 1266 audio_drv_data->capture_i2ssp_stream = NULL; 1267 audio_drv_data->play_i2sbt_stream = NULL; 1268 audio_drv_data->capture_i2sbt_stream = NULL; 1269 1270 audio_drv_data->asic_type = *pdata; 1271 1272 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1273 if (!res) { 1274 dev_err(&pdev->dev, "IORESOURCE_IRQ FAILED\n"); 1275 return -ENODEV; 1276 } 1277 1278 status = devm_request_irq(&pdev->dev, res->start, dma_irq_handler, 1279 0, "ACP_IRQ", &pdev->dev); 1280 if (status) { 1281 dev_err(&pdev->dev, "ACP IRQ request failed\n"); 1282 return status; 1283 } 1284 1285 dev_set_drvdata(&pdev->dev, audio_drv_data); 1286 1287 /* Initialize the ACP */ 1288 status = acp_init(audio_drv_data->acp_mmio, audio_drv_data->asic_type); 1289 if (status) { 1290 dev_err(&pdev->dev, "ACP Init failed status:%d\n", status); 1291 return status; 1292 } 1293 1294 status = devm_snd_soc_register_component(&pdev->dev, 1295 &acp_asoc_platform, NULL, 0); 1296 if (status != 0) { 1297 dev_err(&pdev->dev, "Fail to register ALSA platform device\n"); 1298 return status; 1299 } 1300 1301 pm_runtime_set_autosuspend_delay(&pdev->dev, 10000); 1302 pm_runtime_use_autosuspend(&pdev->dev); 1303 pm_runtime_enable(&pdev->dev); 1304 1305 return status; 1306 } 1307 1308 static int acp_audio_remove(struct platform_device *pdev) 1309 { 1310 int status; 1311 struct audio_drv_data *adata = dev_get_drvdata(&pdev->dev); 1312 1313 status = acp_deinit(adata->acp_mmio); 1314 if (status) 1315 dev_err(&pdev->dev, "ACP Deinit failed status:%d\n", status); 1316 pm_runtime_disable(&pdev->dev); 1317 1318 return 0; 1319 } 1320 1321 static int acp_pcm_resume(struct device *dev) 1322 { 1323 u16 bank; 1324 int status; 1325 struct audio_substream_data *rtd; 1326 struct audio_drv_data *adata = dev_get_drvdata(dev); 1327 1328 status = acp_init(adata->acp_mmio, adata->asic_type); 1329 if (status) { 1330 dev_err(dev, "ACP Init failed status:%d\n", status); 1331 return status; 1332 } 1333 1334 if (adata->play_i2ssp_stream && adata->play_i2ssp_stream->runtime) { 1335 /* 1336 * For Stoney, Memory gating is disabled,i.e SRAM Banks 1337 * won't be turned off. The default state for SRAM banks is ON. 1338 * Setting SRAM bank state code skipped for STONEY platform. 1339 */ 1340 if (adata->asic_type != CHIP_STONEY) { 1341 for (bank = 1; bank <= 4; bank++) 1342 acp_set_sram_bank_state(adata->acp_mmio, bank, 1343 true); 1344 } 1345 rtd = adata->play_i2ssp_stream->runtime->private_data; 1346 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1347 } 1348 if (adata->capture_i2ssp_stream && 1349 adata->capture_i2ssp_stream->runtime) { 1350 if (adata->asic_type != CHIP_STONEY) { 1351 for (bank = 5; bank <= 8; bank++) 1352 acp_set_sram_bank_state(adata->acp_mmio, bank, 1353 true); 1354 } 1355 rtd = adata->capture_i2ssp_stream->runtime->private_data; 1356 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1357 } 1358 if (adata->asic_type != CHIP_CARRIZO) { 1359 if (adata->play_i2sbt_stream && 1360 adata->play_i2sbt_stream->runtime) { 1361 rtd = adata->play_i2sbt_stream->runtime->private_data; 1362 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1363 } 1364 if (adata->capture_i2sbt_stream && 1365 adata->capture_i2sbt_stream->runtime) { 1366 rtd = adata->capture_i2sbt_stream->runtime->private_data; 1367 config_acp_dma(adata->acp_mmio, rtd, adata->asic_type); 1368 } 1369 } 1370 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1371 return 0; 1372 } 1373 1374 static int acp_pcm_runtime_suspend(struct device *dev) 1375 { 1376 int status; 1377 struct audio_drv_data *adata = dev_get_drvdata(dev); 1378 1379 status = acp_deinit(adata->acp_mmio); 1380 if (status) 1381 dev_err(dev, "ACP Deinit failed status:%d\n", status); 1382 acp_reg_write(0, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1383 return 0; 1384 } 1385 1386 static int acp_pcm_runtime_resume(struct device *dev) 1387 { 1388 int status; 1389 struct audio_drv_data *adata = dev_get_drvdata(dev); 1390 1391 status = acp_init(adata->acp_mmio, adata->asic_type); 1392 if (status) { 1393 dev_err(dev, "ACP Init failed status:%d\n", status); 1394 return status; 1395 } 1396 acp_reg_write(1, adata->acp_mmio, mmACP_EXTERNAL_INTR_ENB); 1397 return 0; 1398 } 1399 1400 static const struct dev_pm_ops acp_pm_ops = { 1401 .resume = acp_pcm_resume, 1402 .runtime_suspend = acp_pcm_runtime_suspend, 1403 .runtime_resume = acp_pcm_runtime_resume, 1404 }; 1405 1406 static struct platform_driver acp_dma_driver = { 1407 .probe = acp_audio_probe, 1408 .remove = acp_audio_remove, 1409 .driver = { 1410 .name = DRV_NAME, 1411 .pm = &acp_pm_ops, 1412 }, 1413 }; 1414 1415 module_platform_driver(acp_dma_driver); 1416 1417 MODULE_AUTHOR("Vijendar.Mukunda@amd.com"); 1418 MODULE_AUTHOR("Maruthi.Bayyavarapu@amd.com"); 1419 MODULE_DESCRIPTION("AMD ACP PCM Driver"); 1420 MODULE_LICENSE("GPL v2"); 1421 MODULE_ALIAS("platform:"DRV_NAME); 1422