1 /* 2 * Audio support for PS3 3 * Copyright (C) 2007 Sony Computer Entertainment Inc. 4 * Copyright 2006, 2007 Sony Corporation 5 * All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License 9 * as published by the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 */ 20 21 /* 22 * interrupt / configure registers 23 */ 24 25 #define PS3_AUDIO_INTR_0 (0x00000100) 26 #define PS3_AUDIO_INTR_EN_0 (0x00000140) 27 #define PS3_AUDIO_CONFIG (0x00000200) 28 29 /* 30 * DMAC registers 31 * n:0..9 32 */ 33 #define PS3_AUDIO_DMAC_REGBASE(x) (0x0000210 + 0x20 * (x)) 34 35 #define PS3_AUDIO_KICK(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x00) 36 #define PS3_AUDIO_SOURCE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x04) 37 #define PS3_AUDIO_DEST(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x08) 38 #define PS3_AUDIO_DMASIZE(n) (PS3_AUDIO_DMAC_REGBASE(n) + 0x0C) 39 40 /* 41 * mute control 42 */ 43 #define PS3_AUDIO_AX_MCTRL (0x00004000) 44 #define PS3_AUDIO_AX_ISBP (0x00004004) 45 #define PS3_AUDIO_AX_AOBP (0x00004008) 46 #define PS3_AUDIO_AX_IC (0x00004010) 47 #define PS3_AUDIO_AX_IE (0x00004014) 48 #define PS3_AUDIO_AX_IS (0x00004018) 49 50 /* 51 * three wire serial 52 * n:0..3 53 */ 54 #define PS3_AUDIO_AO_MCTRL (0x00006000) 55 #define PS3_AUDIO_AO_3WMCTRL (0x00006004) 56 57 #define PS3_AUDIO_AO_3WCTRL(n) (0x00006200 + 0x200 * (n)) 58 59 /* 60 * S/PDIF 61 * n:0..1 62 * x:0..11 63 * y:0..5 64 */ 65 #define PS3_AUDIO_AO_SPD_REGBASE(n) (0x00007200 + 0x200 * (n)) 66 67 #define PS3_AUDIO_AO_SPDCTRL(n) \ 68 (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x00) 69 #define PS3_AUDIO_AO_SPDUB(n, x) \ 70 (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x04 + 0x04 * (x)) 71 #define PS3_AUDIO_AO_SPDCS(n, y) \ 72 (PS3_AUDIO_AO_SPD_REGBASE(n) + 0x34 + 0x04 * (y)) 73 74 75 /* 76 PS3_AUDIO_INTR_0 register tells an interrupt handler which audio 77 DMA channel triggered the interrupt. The interrupt status for a channel 78 can be cleared by writing a '1' to the corresponding bit. A new interrupt 79 cannot be generated until the previous interrupt has been cleared. 80 81 Note that the status reported by PS3_AUDIO_INTR_0 is independent of the 82 value of PS3_AUDIO_INTR_EN_0. 83 84 31 24 23 16 15 8 7 0 85 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 86 |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_0 87 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 88 */ 89 #define PS3_AUDIO_INTR_0_CHAN(n) (1 << ((n) * 2)) 90 #define PS3_AUDIO_INTR_0_CHAN9 PS3_AUDIO_INTR_0_CHAN(9) 91 #define PS3_AUDIO_INTR_0_CHAN8 PS3_AUDIO_INTR_0_CHAN(8) 92 #define PS3_AUDIO_INTR_0_CHAN7 PS3_AUDIO_INTR_0_CHAN(7) 93 #define PS3_AUDIO_INTR_0_CHAN6 PS3_AUDIO_INTR_0_CHAN(6) 94 #define PS3_AUDIO_INTR_0_CHAN5 PS3_AUDIO_INTR_0_CHAN(5) 95 #define PS3_AUDIO_INTR_0_CHAN4 PS3_AUDIO_INTR_0_CHAN(4) 96 #define PS3_AUDIO_INTR_0_CHAN3 PS3_AUDIO_INTR_0_CHAN(3) 97 #define PS3_AUDIO_INTR_0_CHAN2 PS3_AUDIO_INTR_0_CHAN(2) 98 #define PS3_AUDIO_INTR_0_CHAN1 PS3_AUDIO_INTR_0_CHAN(1) 99 #define PS3_AUDIO_INTR_0_CHAN0 PS3_AUDIO_INTR_0_CHAN(0) 100 101 /* 102 The PS3_AUDIO_INTR_EN_0 register specifies which DMA channels can generate 103 an interrupt to the PU. Each bit of PS3_AUDIO_INTR_EN_0 is ANDed with the 104 corresponding bit in PS3_AUDIO_INTR_0. The resulting bits are OR'd together 105 to generate the Audio interrupt. 106 107 31 24 23 16 15 8 7 0 108 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 109 |0 0 0 0 0 0 0 0 0 0 0 0 0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C|0|C| INTR_EN_0 110 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 111 112 Bit assignments are same as PS3_AUDIO_INTR_0 113 */ 114 115 /* 116 PS3_AUDIO_CONFIG 117 31 24 23 16 15 8 7 0 118 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 119 |0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 0|0 0 0 0 0 0 0 C|0 0 0 0 0 0 0 0| CONFIG 120 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 121 122 */ 123 124 /* The CLEAR field cancels all pending transfers, and stops any running DMA 125 transfers. Any interrupts associated with the canceled transfers 126 will occur as if the transfer had finished. 127 Since this bit is designed to recover from DMA related issues 128 which are caused by unpredictable situations, it is preferred to wait 129 for normal DMA transfer end without using this bit. 130 */ 131 #define PS3_AUDIO_CONFIG_CLEAR (1 << 8) /* RWIVF */ 132 133 /* 134 PS3_AUDIO_AX_MCTRL: Audio Port Mute Control Register 135 136 31 24 23 16 15 8 7 0 137 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 138 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|A|A|0 0 0 0 0 0 0|S|S|A|A|A|A| AX_MCTRL 139 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 140 */ 141 142 /* 3 Wire Audio Serial Output Channel Mutes (0..3) */ 143 #define PS3_AUDIO_AX_MCTRL_ASOMT(n) (1 << (3 - (n))) /* RWIVF */ 144 #define PS3_AUDIO_AX_MCTRL_ASO3MT (1 << 0) /* RWIVF */ 145 #define PS3_AUDIO_AX_MCTRL_ASO2MT (1 << 1) /* RWIVF */ 146 #define PS3_AUDIO_AX_MCTRL_ASO1MT (1 << 2) /* RWIVF */ 147 #define PS3_AUDIO_AX_MCTRL_ASO0MT (1 << 3) /* RWIVF */ 148 149 /* S/PDIF mutes (0,1)*/ 150 #define PS3_AUDIO_AX_MCTRL_SPOMT(n) (1 << (5 - (n))) /* RWIVF */ 151 #define PS3_AUDIO_AX_MCTRL_SPO1MT (1 << 4) /* RWIVF */ 152 #define PS3_AUDIO_AX_MCTRL_SPO0MT (1 << 5) /* RWIVF */ 153 154 /* All 3 Wire Serial Outputs Mute */ 155 #define PS3_AUDIO_AX_MCTRL_AASOMT (1 << 13) /* RWIVF */ 156 157 /* All S/PDIF Mute */ 158 #define PS3_AUDIO_AX_MCTRL_ASPOMT (1 << 14) /* RWIVF */ 159 160 /* All Audio Outputs Mute */ 161 #define PS3_AUDIO_AX_MCTRL_AAOMT (1 << 15) /* RWIVF */ 162 163 /* 164 S/PDIF Outputs Buffer Read/Write Pointer Register 165 166 31 24 23 16 15 8 7 0 167 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 168 |0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B|0 0 0 0 0 0 0 0|0|SPO0B|0|SPO1B| AX_ISBP 169 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 170 171 */ 172 /* 173 S/PDIF Output Channel Read Buffer Numbers 174 Buffer number is value of field. 175 Indicates current read access buffer ID from Audio Data 176 Transfer controller of S/PDIF Output 177 */ 178 179 #define PS3_AUDIO_AX_ISBP_SPOBRN_MASK(n) (0x7 << 4 * (1 - (n))) /* R-IUF */ 180 #define PS3_AUDIO_AX_ISBP_SPO1BRN_MASK (0x7 << 0) /* R-IUF */ 181 #define PS3_AUDIO_AX_ISBP_SPO0BRN_MASK (0x7 << 4) /* R-IUF */ 182 183 /* 184 S/PDIF Output Channel Buffer Write Numbers 185 Indicates current write access buffer ID from bus master. 186 */ 187 #define PS3_AUDIO_AX_ISBP_SPOBWN_MASK(n) (0x7 << 4 * (5 - (n))) /* R-IUF */ 188 #define PS3_AUDIO_AX_ISBP_SPO1BWN_MASK (0x7 << 16) /* R-IUF */ 189 #define PS3_AUDIO_AX_ISBP_SPO0BWN_MASK (0x7 << 20) /* R-IUF */ 190 191 /* 192 3 Wire Audio Serial Outputs Buffer Read/Write 193 Pointer Register 194 Buffer number is value of field 195 196 31 24 23 16 15 8 7 0 197 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 198 |0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B|0|ASO0B|0|ASO1B|0|ASO2B|0|ASO3B| AX_AOBP 199 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 200 */ 201 202 /* 203 3 Wire Audio Serial Output Channel Buffer Read Numbers 204 Indicates current read access buffer Id from Audio Data Transfer 205 Controller of 3 Wire Audio Serial Output Channels 206 */ 207 #define PS3_AUDIO_AX_AOBP_ASOBRN_MASK(n) (0x7 << 4 * (3 - (n))) /* R-IUF */ 208 209 #define PS3_AUDIO_AX_AOBP_ASO3BRN_MASK (0x7 << 0) /* R-IUF */ 210 #define PS3_AUDIO_AX_AOBP_ASO2BRN_MASK (0x7 << 4) /* R-IUF */ 211 #define PS3_AUDIO_AX_AOBP_ASO1BRN_MASK (0x7 << 8) /* R-IUF */ 212 #define PS3_AUDIO_AX_AOBP_ASO0BRN_MASK (0x7 << 12) /* R-IUF */ 213 214 /* 215 3 Wire Audio Serial Output Channel Buffer Write Numbers 216 Indicates current write access buffer ID from bus master. 217 */ 218 #define PS3_AUDIO_AX_AOBP_ASOBWN_MASK(n) (0x7 << 4 * (7 - (n))) /* R-IUF */ 219 220 #define PS3_AUDIO_AX_AOBP_ASO3BWN_MASK (0x7 << 16) /* R-IUF */ 221 #define PS3_AUDIO_AX_AOBP_ASO2BWN_MASK (0x7 << 20) /* R-IUF */ 222 #define PS3_AUDIO_AX_AOBP_ASO1BWN_MASK (0x7 << 24) /* R-IUF */ 223 #define PS3_AUDIO_AX_AOBP_ASO0BWN_MASK (0x7 << 28) /* R-IUF */ 224 225 226 227 /* 228 Audio Port Interrupt Condition Register 229 For the fields in this register, the following values apply: 230 0 = Interrupt is generated every interrupt event. 231 1 = Interrupt is generated every 2 interrupt events. 232 2 = Interrupt is generated every 4 interrupt events. 233 3 = Reserved 234 235 236 31 24 23 16 15 8 7 0 237 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 238 |0 0 0 0 0 0 0 0|0 0|SPO|0 0|SPO|0 0|AAS|0 0 0 0 0 0 0 0 0 0 0 0| AX_IC 239 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 240 */ 241 /* 242 All 3-Wire Audio Serial Outputs Interrupt Mode 243 Configures the Interrupt and Signal Notification 244 condition of all 3-wire Audio Serial Outputs. 245 */ 246 #define PS3_AUDIO_AX_IC_AASOIMD_MASK (0x3 << 12) /* RWIVF */ 247 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY1 (0x0 << 12) /* RWI-V */ 248 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY2 (0x1 << 12) /* RW--V */ 249 #define PS3_AUDIO_AX_IC_AASOIMD_EVERY4 (0x2 << 12) /* RW--V */ 250 251 /* 252 S/PDIF Output Channel Interrupt Modes 253 Configures the Interrupt and signal Notification 254 conditions of S/PDIF output channels. 255 */ 256 #define PS3_AUDIO_AX_IC_SPO1IMD_MASK (0x3 << 16) /* RWIVF */ 257 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY1 (0x0 << 16) /* RWI-V */ 258 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY2 (0x1 << 16) /* RW--V */ 259 #define PS3_AUDIO_AX_IC_SPO1IMD_EVERY4 (0x2 << 16) /* RW--V */ 260 261 #define PS3_AUDIO_AX_IC_SPO0IMD_MASK (0x3 << 20) /* RWIVF */ 262 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY1 (0x0 << 20) /* RWI-V */ 263 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY2 (0x1 << 20) /* RW--V */ 264 #define PS3_AUDIO_AX_IC_SPO0IMD_EVERY4 (0x2 << 20) /* RW--V */ 265 266 /* 267 Audio Port interrupt Enable Register 268 Configures whether to enable or disable each Interrupt Generation. 269 270 271 31 24 23 16 15 8 7 0 272 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 273 |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IE 274 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 275 276 */ 277 278 /* 279 3 Wire Audio Serial Output Channel Buffer Underflow 280 Interrupt Enables 281 Select enable/disable of Buffer Underflow Interrupts for 282 3-Wire Audio Serial Output Channels 283 DISABLED=Interrupt generation disabled. 284 */ 285 #define PS3_AUDIO_AX_IE_ASOBUIE(n) (1 << (3 - (n))) /* RWIVF */ 286 #define PS3_AUDIO_AX_IE_ASO3BUIE (1 << 0) /* RWIVF */ 287 #define PS3_AUDIO_AX_IE_ASO2BUIE (1 << 1) /* RWIVF */ 288 #define PS3_AUDIO_AX_IE_ASO1BUIE (1 << 2) /* RWIVF */ 289 #define PS3_AUDIO_AX_IE_ASO0BUIE (1 << 3) /* RWIVF */ 290 291 /* S/PDIF Output Channel Buffer Underflow Interrupt Enables */ 292 293 #define PS3_AUDIO_AX_IE_SPOBUIE(n) (1 << (7 - (n))) /* RWIVF */ 294 #define PS3_AUDIO_AX_IE_SPO1BUIE (1 << 6) /* RWIVF */ 295 #define PS3_AUDIO_AX_IE_SPO0BUIE (1 << 7) /* RWIVF */ 296 297 /* S/PDIF Output Channel One Block Transfer Completion Interrupt Enables */ 298 299 #define PS3_AUDIO_AX_IE_SPOBTCIE(n) (1 << (11 - (n))) /* RWIVF */ 300 #define PS3_AUDIO_AX_IE_SPO1BTCIE (1 << 10) /* RWIVF */ 301 #define PS3_AUDIO_AX_IE_SPO0BTCIE (1 << 11) /* RWIVF */ 302 303 /* 3-Wire Audio Serial Output Channel Buffer Empty Interrupt Enables */ 304 305 #define PS3_AUDIO_AX_IE_ASOBEIE(n) (1 << (19 - (n))) /* RWIVF */ 306 #define PS3_AUDIO_AX_IE_ASO3BEIE (1 << 16) /* RWIVF */ 307 #define PS3_AUDIO_AX_IE_ASO2BEIE (1 << 17) /* RWIVF */ 308 #define PS3_AUDIO_AX_IE_ASO1BEIE (1 << 18) /* RWIVF */ 309 #define PS3_AUDIO_AX_IE_ASO0BEIE (1 << 19) /* RWIVF */ 310 311 /* S/PDIF Output Channel Buffer Empty Interrupt Enables */ 312 313 #define PS3_AUDIO_AX_IE_SPOBEIE(n) (1 << (23 - (n))) /* RWIVF */ 314 #define PS3_AUDIO_AX_IE_SPO1BEIE (1 << 22) /* RWIVF */ 315 #define PS3_AUDIO_AX_IE_SPO0BEIE (1 << 23) /* RWIVF */ 316 317 /* 318 Audio Port Interrupt Status Register 319 Indicates Interrupt status, which interrupt has occurred, and can clear 320 each interrupt in this register. 321 Writing 1b to a field containing 1b clears field and de-asserts interrupt. 322 Writing 0b to a field has no effect. 323 Field vaules are the following: 324 0 - Interrupt hasn't occurred. 325 1 - Interrupt has occurred. 326 327 328 31 24 23 16 15 8 7 0 329 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 330 |0 0 0 0 0 0 0 0|S|S|0 0|A|A|A|A|0 0 0 0|S|S|0 0|S|S|0 0|A|A|A|A| AX_IS 331 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 332 333 Bit assignment are same as AX_IE 334 */ 335 336 /* 337 Audio Output Master Control Register 338 Configures Master Clock and other master Audio Output Settings 339 340 341 31 24 23 16 15 8 7 0 342 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 343 |0|SCKSE|0|SCKSE| MR0 | MR1 |MCL|MCL|0 0 0 0|0 0 0 0 0 0 0 0| AO_MCTRL 344 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 345 */ 346 347 /* 348 MCLK Output Control 349 Controls mclko[1] output. 350 0 - Disable output (fixed at High) 351 1 - Output clock produced by clock selected 352 with scksel1 by mr1 353 2 - Reserved 354 3 - Reserved 355 */ 356 357 #define PS3_AUDIO_AO_MCTRL_MCLKC1_MASK (0x3 << 12) /* RWIVF */ 358 #define PS3_AUDIO_AO_MCTRL_MCLKC1_DISABLED (0x0 << 12) /* RWI-V */ 359 #define PS3_AUDIO_AO_MCTRL_MCLKC1_ENABLED (0x1 << 12) /* RW--V */ 360 #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD2 (0x2 << 12) /* RW--V */ 361 #define PS3_AUDIO_AO_MCTRL_MCLKC1_RESVD3 (0x3 << 12) /* RW--V */ 362 363 /* 364 MCLK Output Control 365 Controls mclko[0] output. 366 0 - Disable output (fixed at High) 367 1 - Output clock produced by clock selected 368 with SCKSEL0 by MR0 369 2 - Reserved 370 3 - Reserved 371 */ 372 #define PS3_AUDIO_AO_MCTRL_MCLKC0_MASK (0x3 << 14) /* RWIVF */ 373 #define PS3_AUDIO_AO_MCTRL_MCLKC0_DISABLED (0x0 << 14) /* RWI-V */ 374 #define PS3_AUDIO_AO_MCTRL_MCLKC0_ENABLED (0x1 << 14) /* RW--V */ 375 #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD2 (0x2 << 14) /* RW--V */ 376 #define PS3_AUDIO_AO_MCTRL_MCLKC0_RESVD3 (0x3 << 14) /* RW--V */ 377 /* 378 Master Clock Rate 1 379 Sets the divide ration of Master Clock1 (clock output from 380 mclko[1] for the input clock selected by scksel1. 381 */ 382 #define PS3_AUDIO_AO_MCTRL_MR1_MASK (0xf << 16) 383 #define PS3_AUDIO_AO_MCTRL_MR1_DEFAULT (0x0 << 16) /* RWI-V */ 384 /* 385 Master Clock Rate 0 386 Sets the divide ratio of Master Clock0 (clock output from 387 mclko[0] for the input clock selected by scksel0). 388 */ 389 #define PS3_AUDIO_AO_MCTRL_MR0_MASK (0xf << 20) /* RWIVF */ 390 #define PS3_AUDIO_AO_MCTRL_MR0_DEFAULT (0x0 << 20) /* RWI-V */ 391 /* 392 System Clock Select 0/1 393 Selects the system clock to be used as Master Clock 0/1 394 Input the system clock that is appropriate for the sampling 395 rate. 396 */ 397 #define PS3_AUDIO_AO_MCTRL_SCKSEL1_MASK (0x7 << 24) /* RWIVF */ 398 #define PS3_AUDIO_AO_MCTRL_SCKSEL1_DEFAULT (0x2 << 24) /* RWI-V */ 399 400 #define PS3_AUDIO_AO_MCTRL_SCKSEL0_MASK (0x7 << 28) /* RWIVF */ 401 #define PS3_AUDIO_AO_MCTRL_SCKSEL0_DEFAULT (0x2 << 28) /* RWI-V */ 402 403 404 /* 405 3-Wire Audio Output Master Control Register 406 Configures clock, 3-Wire Audio Serial Output Enable, and 407 other 3-Wire Audio Serial Output Master Settings 408 409 410 31 24 23 16 15 8 7 0 411 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 412 |A|A|A|A|0 0 0|A| ASOSR |0 0 0 0|A|A|A|A|A|A|0|1|0 0 0 0 0 0 0 0| AO_3WMCTRL 413 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 414 */ 415 416 417 /* 418 LRCKO Polarity 419 0 - Reserved 420 1 - default 421 */ 422 #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK (1 << 8) /* RWIVF */ 423 #define PS3_AUDIO_AO_3WMCTRL_ASOPLRCK_DEFAULT (1 << 8) /* RW--V */ 424 425 /* LRCK Output Disable */ 426 427 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD (1 << 10) /* RWIVF */ 428 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_ENABLED (0 << 10) /* RW--V */ 429 #define PS3_AUDIO_AO_3WMCTRL_ASOLRCKD_DISABLED (1 << 10) /* RWI-V */ 430 431 /* Bit Clock Output Disable */ 432 433 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD (1 << 11) /* RWIVF */ 434 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_ENABLED (0 << 11) /* RW--V */ 435 #define PS3_AUDIO_AO_3WMCTRL_ASOBCLKD_DISABLED (1 << 11) /* RWI-V */ 436 437 /* 438 3-Wire Audio Serial Output Channel 0-3 Operational 439 Status. Each bit becomes 1 after each 3-Wire Audio 440 Serial Output Channel N is in action by setting 1 to 441 asoen. 442 Each bit becomes 0 after each 3-Wire Audio Serial Output 443 Channel N is out of action by setting 0 to asoen. 444 */ 445 #define PS3_AUDIO_AO_3WMCTRL_ASORUN(n) (1 << (15 - (n))) /* R-IVF */ 446 #define PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(n) (0 << (15 - (n))) /* R-I-V */ 447 #define PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(n) (1 << (15 - (n))) /* R---V */ 448 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0 \ 449 PS3_AUDIO_AO_3WMCTRL_ASORUN(0) 450 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_STOPPED \ 451 PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(0) 452 #define PS3_AUDIO_AO_3WMCTRL_ASORUN0_RUNNING \ 453 PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(0) 454 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1 \ 455 PS3_AUDIO_AO_3WMCTRL_ASORUN(1) 456 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_STOPPED \ 457 PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(1) 458 #define PS3_AUDIO_AO_3WMCTRL_ASORUN1_RUNNING \ 459 PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(1) 460 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2 \ 461 PS3_AUDIO_AO_3WMCTRL_ASORUN(2) 462 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_STOPPED \ 463 PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(2) 464 #define PS3_AUDIO_AO_3WMCTRL_ASORUN2_RUNNING \ 465 PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(2) 466 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3 \ 467 PS3_AUDIO_AO_3WMCTRL_ASORUN(3) 468 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_STOPPED \ 469 PS3_AUDIO_AO_3WMCTRL_ASORUN_STOPPED(3) 470 #define PS3_AUDIO_AO_3WMCTRL_ASORUN3_RUNNING \ 471 PS3_AUDIO_AO_3WMCTRL_ASORUN_RUNNING(3) 472 473 /* 474 Sampling Rate 475 Specifies the divide ratio of the bit clock (clock output 476 from bclko) used by the 3-wire Audio Output Clock, which 477 is applied to the master clock selected by mcksel. 478 Data output is synchronized with this clock. 479 */ 480 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_MASK (0xf << 20) /* RWIVF */ 481 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV2 (0x1 << 20) /* RWI-V */ 482 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV4 (0x2 << 20) /* RW--V */ 483 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV8 (0x4 << 20) /* RW--V */ 484 #define PS3_AUDIO_AO_3WMCTRL_ASOSR_DIV12 (0x6 << 20) /* RW--V */ 485 486 /* 487 Master Clock Select 488 0 - Master Clock 0 489 1 - Master Clock 1 490 */ 491 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL (1 << 24) /* RWIVF */ 492 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK0 (0 << 24) /* RWI-V */ 493 #define PS3_AUDIO_AO_3WMCTRL_ASOMCKSEL_CLK1 (1 << 24) /* RW--V */ 494 495 /* 496 Enables and disables 4ch 3-Wire Audio Serial Output 497 operation. Each Bit from 0 to 3 corresponds to an 498 output channel, which means that each output channel 499 can be enabled or disabled individually. When 500 multiple channels are enabled at the same time, output 501 operations are performed in synchronization. 502 Bit 0 - Output Channel 0 (SDOUT[0]) 503 Bit 1 - Output Channel 1 (SDOUT[1]) 504 Bit 2 - Output Channel 2 (SDOUT[2]) 505 Bit 3 - Output Channel 3 (SDOUT[3]) 506 */ 507 #define PS3_AUDIO_AO_3WMCTRL_ASOEN(n) (1 << (31 - (n))) /* RWIVF */ 508 #define PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(n) (0 << (31 - (n))) /* RWI-V */ 509 #define PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(n) (1 << (31 - (n))) /* RW--V */ 510 511 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0 \ 512 PS3_AUDIO_AO_3WMCTRL_ASOEN(0) /* RWIVF */ 513 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_DISABLED \ 514 PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(0) /* RWI-V */ 515 #define PS3_AUDIO_AO_3WMCTRL_ASOEN0_ENABLED \ 516 PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(0) /* RW--V */ 517 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0 \ 518 PS3_AUDIO_AO_3WMCTRL_ASOEN(1) /* RWIVF */ 519 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_DISABLED \ 520 PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(1) /* RWI-V */ 521 #define PS3_AUDIO_A1_3WMCTRL_ASOEN0_ENABLED \ 522 PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(1) /* RW--V */ 523 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0 \ 524 PS3_AUDIO_AO_3WMCTRL_ASOEN(2) /* RWIVF */ 525 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_DISABLED \ 526 PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(2) /* RWI-V */ 527 #define PS3_AUDIO_A2_3WMCTRL_ASOEN0_ENABLED \ 528 PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(2) /* RW--V */ 529 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0 \ 530 PS3_AUDIO_AO_3WMCTRL_ASOEN(3) /* RWIVF */ 531 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_DISABLED \ 532 PS3_AUDIO_AO_3WMCTRL_ASOEN_DISABLED(3) /* RWI-V */ 533 #define PS3_AUDIO_A3_3WMCTRL_ASOEN0_ENABLED \ 534 PS3_AUDIO_AO_3WMCTRL_ASOEN_ENABLED(3) /* RW--V */ 535 536 /* 537 3-Wire Audio Serial output Channel 0-3 Control Register 538 Configures settings for 3-Wire Serial Audio Output Channel 0-3 539 540 541 31 24 23 16 15 8 7 0 542 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 543 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|A|0 0 0 0|A|0|ASO|0 0 0|0|0|0|0|0| AO_3WCTRL 544 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 545 546 */ 547 /* 548 Data Bit Mode 549 Specifies the number of data bits 550 0 - 16 bits 551 1 - reserved 552 2 - 20 bits 553 3 - 24 bits 554 */ 555 #define PS3_AUDIO_AO_3WCTRL_ASODB_MASK (0x3 << 8) /* RWIVF */ 556 #define PS3_AUDIO_AO_3WCTRL_ASODB_16BIT (0x0 << 8) /* RWI-V */ 557 #define PS3_AUDIO_AO_3WCTRL_ASODB_RESVD (0x1 << 8) /* RWI-V */ 558 #define PS3_AUDIO_AO_3WCTRL_ASODB_20BIT (0x2 << 8) /* RW--V */ 559 #define PS3_AUDIO_AO_3WCTRL_ASODB_24BIT (0x3 << 8) /* RW--V */ 560 /* 561 Data Format Mode 562 Specifies the data format where (LSB side or MSB) the data(in 20 bit 563 or 24 bit resolution mode) is put in a 32 bit field. 564 0 - Data put on LSB side 565 1 - Data put on MSB side 566 */ 567 #define PS3_AUDIO_AO_3WCTRL_ASODF (1 << 11) /* RWIVF */ 568 #define PS3_AUDIO_AO_3WCTRL_ASODF_LSB (0 << 11) /* RWI-V */ 569 #define PS3_AUDIO_AO_3WCTRL_ASODF_MSB (1 << 11) /* RW--V */ 570 /* 571 Buffer Reset 572 Performs buffer reset. Writing 1 to this bit initializes the 573 corresponding 3-Wire Audio Output buffers(both L and R). 574 */ 575 #define PS3_AUDIO_AO_3WCTRL_ASOBRST (1 << 16) /* CWIVF */ 576 #define PS3_AUDIO_AO_3WCTRL_ASOBRST_IDLE (0 << 16) /* -WI-V */ 577 #define PS3_AUDIO_AO_3WCTRL_ASOBRST_RESET (1 << 16) /* -W--T */ 578 579 /* 580 S/PDIF Audio Output Channel 0/1 Control Register 581 Configures settings for S/PDIF Audio Output Channel 0/1. 582 583 31 24 23 16 15 8 7 0 584 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 585 |S|0 0 0|S|0 0|S| SPOSR |0 0|SPO|0 0 0 0|S|0|SPO|0 0 0 0 0 0 0|S| AO_SPDCTRL 586 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 587 */ 588 /* 589 Buffer reset. Writing 1 to this bit initializes the 590 corresponding S/PDIF output buffer pointer. 591 */ 592 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST (1 << 0) /* CWIVF */ 593 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_IDLE (0 << 0) /* -WI-V */ 594 #define PS3_AUDIO_AO_SPDCTRL_SPOBRST_RESET (1 << 0) /* -W--T */ 595 596 /* 597 Data Bit Mode 598 Specifies number of data bits 599 0 - 16 bits 600 1 - Reserved 601 2 - 20 bits 602 3 - 24 bits 603 */ 604 #define PS3_AUDIO_AO_SPDCTRL_SPODB_MASK (0x3 << 8) /* RWIVF */ 605 #define PS3_AUDIO_AO_SPDCTRL_SPODB_16BIT (0x0 << 8) /* RWI-V */ 606 #define PS3_AUDIO_AO_SPDCTRL_SPODB_RESVD (0x1 << 8) /* RW--V */ 607 #define PS3_AUDIO_AO_SPDCTRL_SPODB_20BIT (0x2 << 8) /* RW--V */ 608 #define PS3_AUDIO_AO_SPDCTRL_SPODB_24BIT (0x3 << 8) /* RW--V */ 609 /* 610 Data format Mode 611 Specifies the data format, where (LSB side or MSB) 612 the data(in 20 or 24 bit resolution) is put in the 613 32 bit field. 614 0 - LSB Side 615 1 - MSB Side 616 */ 617 #define PS3_AUDIO_AO_SPDCTRL_SPODF (1 << 11) /* RWIVF */ 618 #define PS3_AUDIO_AO_SPDCTRL_SPODF_LSB (0 << 11) /* RWI-V */ 619 #define PS3_AUDIO_AO_SPDCTRL_SPODF_MSB (1 << 11) /* RW--V */ 620 /* 621 Source Select 622 Specifies the source of the S/PDIF output. When 0, output 623 operation is controlled by 3wen[0] of AO_3WMCTRL register. 624 The SR must have the same setting as the a0_3wmctrl reg. 625 0 - 3-Wire Audio OUT Ch0 Buffer 626 1 - S/PDIF buffer 627 */ 628 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_MASK (0x3 << 16) /* RWIVF */ 629 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_3WEN (0x0 << 16) /* RWI-V */ 630 #define PS3_AUDIO_AO_SPDCTRL_SPOSS_SPDIF (0x1 << 16) /* RW--V */ 631 /* 632 Sampling Rate 633 Specifies the divide ratio of the bit clock (clock output 634 from bclko) used by the S/PDIF Output Clock, which 635 is applied to the master clock selected by mcksel. 636 */ 637 #define PS3_AUDIO_AO_SPDCTRL_SPOSR (0xf << 20) /* RWIVF */ 638 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV2 (0x1 << 20) /* RWI-V */ 639 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV4 (0x2 << 20) /* RW--V */ 640 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV8 (0x4 << 20) /* RW--V */ 641 #define PS3_AUDIO_AO_SPDCTRL_SPOSR_DIV12 (0x6 << 20) /* RW--V */ 642 /* 643 Master Clock Select 644 0 - Master Clock 0 645 1 - Master Clock 1 646 */ 647 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL (1 << 24) /* RWIVF */ 648 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK0 (0 << 24) /* RWI-V */ 649 #define PS3_AUDIO_AO_SPDCTRL_SPOMCKSEL_CLK1 (1 << 24) /* RW--V */ 650 651 /* 652 S/PDIF Output Channel Operational Status 653 This bit becomes 1 after S/PDIF Output Channel is in 654 action by setting 1 to spoen. This bit becomes 0 655 after S/PDIF Output Channel is out of action by setting 656 0 to spoen. 657 */ 658 #define PS3_AUDIO_AO_SPDCTRL_SPORUN (1 << 27) /* R-IVF */ 659 #define PS3_AUDIO_AO_SPDCTRL_SPORUN_STOPPED (0 << 27) /* R-I-V */ 660 #define PS3_AUDIO_AO_SPDCTRL_SPORUN_RUNNING (1 << 27) /* R---V */ 661 662 /* 663 S/PDIF Audio Output Channel Output Enable 664 Enables and disables output operation. This bit is used 665 only when sposs = 1 666 */ 667 #define PS3_AUDIO_AO_SPDCTRL_SPOEN (1 << 31) /* RWIVF */ 668 #define PS3_AUDIO_AO_SPDCTRL_SPOEN_DISABLED (0 << 31) /* RWI-V */ 669 #define PS3_AUDIO_AO_SPDCTRL_SPOEN_ENABLED (1 << 31) /* RW--V */ 670 671 /* 672 S/PDIF Audio Output Channel Channel Status 673 Setting Registers. 674 Configures channel status bit settings for each block 675 (192 bits). 676 Output is performed from the MSB(AO_SPDCS0 register bit 31). 677 The same value is added for subframes within the same frame. 678 31 24 23 16 15 8 7 0 679 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 680 | SPOCS | AO_SPDCS 681 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 682 683 S/PDIF Audio Output Channel User Bit Setting 684 Configures user bit settings for each block (384 bits). 685 Output is performed from the MSB(ao_spdub0 register bit 31). 686 687 688 31 24 23 16 15 8 7 0 689 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 690 | SPOUB | AO_SPDUB 691 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 692 */ 693 /***************************************************************************** 694 * 695 * DMAC register 696 * 697 *****************************************************************************/ 698 /* 699 The PS3_AUDIO_KICK register is used to initiate a DMA transfer and monitor 700 its status 701 702 31 24 23 16 15 8 7 0 703 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 704 |0 0 0 0 0|STATU|0 0 0| EVENT |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0|R| KICK 705 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 706 */ 707 /* 708 The REQUEST field is written to ACTIVE to initiate a DMA request when EVENT 709 occurs. 710 It will return to the DONE state when the request is completed. 711 The registers for a DMA channel should only be written if REQUEST is IDLE. 712 */ 713 714 #define PS3_AUDIO_KICK_REQUEST (1 << 0) /* RWIVF */ 715 #define PS3_AUDIO_KICK_REQUEST_IDLE (0 << 0) /* RWI-V */ 716 #define PS3_AUDIO_KICK_REQUEST_ACTIVE (1 << 0) /* -W--T */ 717 718 /* 719 *The EVENT field is used to set the event in which 720 *the DMA request becomes active. 721 */ 722 #define PS3_AUDIO_KICK_EVENT_MASK (0x1f << 16) /* RWIVF */ 723 #define PS3_AUDIO_KICK_EVENT_ALWAYS (0x00 << 16) /* RWI-V */ 724 #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_EMPTY (0x01 << 16) /* RW--V */ 725 #define PS3_AUDIO_KICK_EVENT_SERIALOUT0_UNDERFLOW (0x02 << 16) /* RW--V */ 726 #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_EMPTY (0x03 << 16) /* RW--V */ 727 #define PS3_AUDIO_KICK_EVENT_SERIALOUT1_UNDERFLOW (0x04 << 16) /* RW--V */ 728 #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_EMPTY (0x05 << 16) /* RW--V */ 729 #define PS3_AUDIO_KICK_EVENT_SERIALOUT2_UNDERFLOW (0x06 << 16) /* RW--V */ 730 #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_EMPTY (0x07 << 16) /* RW--V */ 731 #define PS3_AUDIO_KICK_EVENT_SERIALOUT3_UNDERFLOW (0x08 << 16) /* RW--V */ 732 #define PS3_AUDIO_KICK_EVENT_SPDIF0_BLOCKTRANSFERCOMPLETE \ 733 (0x09 << 16) /* RW--V */ 734 #define PS3_AUDIO_KICK_EVENT_SPDIF0_UNDERFLOW (0x0A << 16) /* RW--V */ 735 #define PS3_AUDIO_KICK_EVENT_SPDIF0_EMPTY (0x0B << 16) /* RW--V */ 736 #define PS3_AUDIO_KICK_EVENT_SPDIF1_BLOCKTRANSFERCOMPLETE \ 737 (0x0C << 16) /* RW--V */ 738 #define PS3_AUDIO_KICK_EVENT_SPDIF1_UNDERFLOW (0x0D << 16) /* RW--V */ 739 #define PS3_AUDIO_KICK_EVENT_SPDIF1_EMPTY (0x0E << 16) /* RW--V */ 740 741 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA(n) \ 742 ((0x13 + (n)) << 16) /* RW--V */ 743 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA0 (0x13 << 16) /* RW--V */ 744 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA1 (0x14 << 16) /* RW--V */ 745 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA2 (0x15 << 16) /* RW--V */ 746 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA3 (0x16 << 16) /* RW--V */ 747 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA4 (0x17 << 16) /* RW--V */ 748 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA5 (0x18 << 16) /* RW--V */ 749 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA6 (0x19 << 16) /* RW--V */ 750 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA7 (0x1A << 16) /* RW--V */ 751 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA8 (0x1B << 16) /* RW--V */ 752 #define PS3_AUDIO_KICK_EVENT_AUDIO_DMA9 (0x1C << 16) /* RW--V */ 753 754 /* 755 The STATUS field can be used to monitor the progress of a DMA request. 756 DONE indicates the previous request has completed. 757 EVENT indicates that the DMA engine is waiting for the EVENT to occur. 758 PENDING indicates that the DMA engine has not started processing this 759 request, but the EVENT has occurred. 760 DMA indicates that the data transfer is in progress. 761 NOTIFY indicates that the notifier signalling end of transfer is being written. 762 CLEAR indicated that the previous transfer was cleared. 763 ERROR indicates the previous transfer requested an unsupported 764 source/destination combination. 765 */ 766 767 #define PS3_AUDIO_KICK_STATUS_MASK (0x7 << 24) /* R-IVF */ 768 #define PS3_AUDIO_KICK_STATUS_DONE (0x0 << 24) /* R-I-V */ 769 #define PS3_AUDIO_KICK_STATUS_EVENT (0x1 << 24) /* R---V */ 770 #define PS3_AUDIO_KICK_STATUS_PENDING (0x2 << 24) /* R---V */ 771 #define PS3_AUDIO_KICK_STATUS_DMA (0x3 << 24) /* R---V */ 772 #define PS3_AUDIO_KICK_STATUS_NOTIFY (0x4 << 24) /* R---V */ 773 #define PS3_AUDIO_KICK_STATUS_CLEAR (0x5 << 24) /* R---V */ 774 #define PS3_AUDIO_KICK_STATUS_ERROR (0x6 << 24) /* R---V */ 775 776 /* 777 The PS3_AUDIO_SOURCE register specifies the source address for transfers. 778 779 780 31 24 23 16 15 8 7 0 781 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 782 | START |0 0 0 0 0|TAR| SOURCE 783 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 784 */ 785 786 /* 787 The Audio DMA engine uses 128-byte transfers, thus the address must be aligned 788 to a 128 byte boundary. The low seven bits are assumed to be 0. 789 */ 790 791 #define PS3_AUDIO_SOURCE_START_MASK (0x01FFFFFF << 7) /* RWIUF */ 792 793 /* 794 The TARGET field specifies the memory space containing the source address. 795 */ 796 797 #define PS3_AUDIO_SOURCE_TARGET_MASK (3 << 0) /* RWIVF */ 798 #define PS3_AUDIO_SOURCE_TARGET_SYSTEM_MEMORY (2 << 0) /* RW--V */ 799 800 /* 801 The PS3_AUDIO_DEST register specifies the destination address for transfers. 802 803 804 31 24 23 16 15 8 7 0 805 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 806 | START |0 0 0 0 0|TAR| DEST 807 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 808 */ 809 810 /* 811 The Audio DMA engine uses 128-byte transfers, thus the address must be aligned 812 to a 128 byte boundary. The low seven bits are assumed to be 0. 813 */ 814 815 #define PS3_AUDIO_DEST_START_MASK (0x01FFFFFF << 7) /* RWIUF */ 816 817 /* 818 The TARGET field specifies the memory space containing the destination address 819 AUDIOFIFO = Audio WriteData FIFO, 820 */ 821 822 #define PS3_AUDIO_DEST_TARGET_MASK (3 << 0) /* RWIVF */ 823 #define PS3_AUDIO_DEST_TARGET_AUDIOFIFO (1 << 0) /* RW--V */ 824 825 /* 826 PS3_AUDIO_DMASIZE specifies the number of 128-byte blocks + 1 to transfer. 827 So a value of 0 means 128-bytes will get transferred. 828 829 830 31 24 23 16 15 8 7 0 831 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 832 |0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0| BLOCKS | DMASIZE 833 +-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-|-+-+-+-+-+-+-+-+ 834 */ 835 836 837 #define PS3_AUDIO_DMASIZE_BLOCKS_MASK (0x7f << 0) /* RWIUF */ 838 839 /* 840 * source/destination address for internal fifos 841 */ 842 #define PS3_AUDIO_AO_3W_LDATA(n) (0x1000 + (0x100 * (n))) 843 #define PS3_AUDIO_AO_3W_RDATA(n) (0x1080 + (0x100 * (n))) 844 845 #define PS3_AUDIO_AO_SPD_DATA(n) (0x2000 + (0x400 * (n))) 846 847 848 /* 849 * field attiribute 850 * 851 * Read 852 * ' ' = Other Information 853 * '-' = Field is part of a write-only register 854 * 'C' = Value read is always the same, constant value line follows (C) 855 * 'R' = Value is read 856 * 857 * Write 858 * ' ' = Other Information 859 * '-' = Must not be written (D), value ignored when written (R,A,F) 860 * 'W' = Can be written 861 * 862 * Internal State 863 * ' ' = Other Information 864 * '-' = No internal state 865 * 'X' = Internal state, initial value is unknown 866 * 'I' = Internal state, initial value is known and follows (I) 867 * 868 * Declaration/Size 869 * ' ' = Other Information 870 * '-' = Does Not Apply 871 * 'V' = Type is void 872 * 'U' = Type is unsigned integer 873 * 'S' = Type is signed integer 874 * 'F' = Type is IEEE floating point 875 * '1' = Byte size (008) 876 * '2' = Short size (016) 877 * '3' = Three byte size (024) 878 * '4' = Word size (032) 879 * '8' = Double size (064) 880 * 881 * Define Indicator 882 * ' ' = Other Information 883 * 'D' = Device 884 * 'M' = Memory 885 * 'R' = Register 886 * 'A' = Array of Registers 887 * 'F' = Field 888 * 'V' = Value 889 * 'T' = Task 890 */ 891 892