1 /* 2 * Driver for Digigram VX222 V2/Mic soundcards 3 * 4 * VX222-specific low-level routines 5 * 6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/firmware.h> 26 #include <linux/mutex.h> 27 28 #include <sound/core.h> 29 #include <sound/control.h> 30 #include <sound/tlv.h> 31 #include <asm/io.h> 32 #include "vx222.h" 33 34 35 static int vx2_reg_offset[VX_REG_MAX] = { 36 [VX_ICR] = 0x00, 37 [VX_CVR] = 0x04, 38 [VX_ISR] = 0x08, 39 [VX_IVR] = 0x0c, 40 [VX_RXH] = 0x14, 41 [VX_RXM] = 0x18, 42 [VX_RXL] = 0x1c, 43 [VX_DMA] = 0x10, 44 [VX_CDSP] = 0x20, 45 [VX_CFG] = 0x24, 46 [VX_RUER] = 0x28, 47 [VX_DATA] = 0x2c, 48 [VX_STATUS] = 0x30, 49 [VX_LOFREQ] = 0x34, 50 [VX_HIFREQ] = 0x38, 51 [VX_CSUER] = 0x3c, 52 [VX_SELMIC] = 0x40, 53 [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate 54 [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate 55 [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate 56 [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET 57 [VX_CNTRL] = 0x50, // VX_CNTRL_REGISTER_OFFSET 58 [VX_GPIOC] = 0x54, // VX_GPIOC (new with PLX9030) 59 }; 60 61 static int vx2_reg_index[VX_REG_MAX] = { 62 [VX_ICR] = 1, 63 [VX_CVR] = 1, 64 [VX_ISR] = 1, 65 [VX_IVR] = 1, 66 [VX_RXH] = 1, 67 [VX_RXM] = 1, 68 [VX_RXL] = 1, 69 [VX_DMA] = 1, 70 [VX_CDSP] = 1, 71 [VX_CFG] = 1, 72 [VX_RUER] = 1, 73 [VX_DATA] = 1, 74 [VX_STATUS] = 1, 75 [VX_LOFREQ] = 1, 76 [VX_HIFREQ] = 1, 77 [VX_CSUER] = 1, 78 [VX_SELMIC] = 1, 79 [VX_COMPOT] = 1, 80 [VX_SCOMPR] = 1, 81 [VX_GLIMIT] = 1, 82 [VX_INTCSR] = 0, /* on the PLX */ 83 [VX_CNTRL] = 0, /* on the PLX */ 84 [VX_GPIOC] = 0, /* on the PLX */ 85 }; 86 87 static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg) 88 { 89 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 90 return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg]; 91 } 92 93 /** 94 * snd_vx_inb - read a byte from the register 95 * @offset: register enum 96 */ 97 static unsigned char vx2_inb(struct vx_core *chip, int offset) 98 { 99 return inb(vx2_reg_addr(chip, offset)); 100 } 101 102 /** 103 * snd_vx_outb - write a byte on the register 104 * @offset: the register offset 105 * @val: the value to write 106 */ 107 static void vx2_outb(struct vx_core *chip, int offset, unsigned char val) 108 { 109 outb(val, vx2_reg_addr(chip, offset)); 110 /* 111 dev_dbg(chip->card->dev, "outb: %x -> %x\n", val, vx2_reg_addr(chip, offset)); 112 */ 113 } 114 115 /** 116 * snd_vx_inl - read a 32bit word from the register 117 * @offset: register enum 118 */ 119 static unsigned int vx2_inl(struct vx_core *chip, int offset) 120 { 121 return inl(vx2_reg_addr(chip, offset)); 122 } 123 124 /** 125 * snd_vx_outl - write a 32bit word on the register 126 * @offset: the register enum 127 * @val: the value to write 128 */ 129 static void vx2_outl(struct vx_core *chip, int offset, unsigned int val) 130 { 131 /* 132 dev_dbg(chip->card->dev, "outl: %x -> %x\n", val, vx2_reg_addr(chip, offset)); 133 */ 134 outl(val, vx2_reg_addr(chip, offset)); 135 } 136 137 /* 138 * redefine macros to call directly 139 */ 140 #undef vx_inb 141 #define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg) 142 #undef vx_outb 143 #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val) 144 #undef vx_inl 145 #define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg) 146 #undef vx_outl 147 #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val) 148 149 150 /* 151 * vx_reset_dsp - reset the DSP 152 */ 153 154 #define XX_DSP_RESET_WAIT_TIME 2 /* ms */ 155 156 static void vx2_reset_dsp(struct vx_core *_chip) 157 { 158 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 159 160 /* set the reset dsp bit to 0 */ 161 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); 162 163 mdelay(XX_DSP_RESET_WAIT_TIME); 164 165 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK; 166 /* set the reset dsp bit to 1 */ 167 vx_outl(chip, CDSP, chip->regCDSP); 168 } 169 170 171 static int vx2_test_xilinx(struct vx_core *_chip) 172 { 173 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 174 unsigned int data; 175 176 dev_dbg(_chip->card->dev, "testing xilinx...\n"); 177 /* This test uses several write/read sequences on TEST0 and TEST1 bits 178 * to figure out whever or not the xilinx was correctly loaded 179 */ 180 181 /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */ 182 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK); 183 vx_inl(chip, ISR); 184 data = vx_inl(chip, STATUS); 185 if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) { 186 dev_dbg(_chip->card->dev, "bad!\n"); 187 return -ENODEV; 188 } 189 190 /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */ 191 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK); 192 vx_inl(chip, ISR); 193 data = vx_inl(chip, STATUS); 194 if (! (data & VX_STATUS_VAL_TEST0_MASK)) { 195 dev_dbg(_chip->card->dev, "bad! #2\n"); 196 return -ENODEV; 197 } 198 199 if (_chip->type == VX_TYPE_BOARD) { 200 /* not implemented on VX_2_BOARDS */ 201 /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */ 202 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK); 203 vx_inl(chip, ISR); 204 data = vx_inl(chip, STATUS); 205 if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) { 206 dev_dbg(_chip->card->dev, "bad! #3\n"); 207 return -ENODEV; 208 } 209 210 /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */ 211 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK); 212 vx_inl(chip, ISR); 213 data = vx_inl(chip, STATUS); 214 if (! (data & VX_STATUS_VAL_TEST1_MASK)) { 215 dev_dbg(_chip->card->dev, "bad! #4\n"); 216 return -ENODEV; 217 } 218 } 219 dev_dbg(_chip->card->dev, "ok, xilinx fine.\n"); 220 return 0; 221 } 222 223 224 /** 225 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode. 226 * @do_write: 0 = read, 1 = set up for DMA write 227 */ 228 static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write) 229 { 230 /* Interrupt mode and HREQ pin enabled for host transmit data transfers 231 * (in case of the use of the pseudo-dma facility). 232 */ 233 vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); 234 235 /* Reset the pseudo-dma register (in case of the use of the 236 * pseudo-dma facility). 237 */ 238 vx_outl(chip, RESET_DMA, 0); 239 } 240 241 /* 242 * vx_release_pseudo_dma - disable the pseudo-DMA mode 243 */ 244 static inline void vx2_release_pseudo_dma(struct vx_core *chip) 245 { 246 /* HREQ pin disabled. */ 247 vx_outl(chip, ICR, 0); 248 } 249 250 251 252 /* pseudo-dma write */ 253 static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, 254 struct vx_pipe *pipe, int count) 255 { 256 unsigned long port = vx2_reg_addr(chip, VX_DMA); 257 int offset = pipe->hw_ptr; 258 u32 *addr = (u32 *)(runtime->dma_area + offset); 259 260 if (snd_BUG_ON(count % 4)) 261 return; 262 263 vx2_setup_pseudo_dma(chip, 1); 264 265 /* Transfer using pseudo-dma. 266 */ 267 if (offset + count > pipe->buffer_bytes) { 268 int length = pipe->buffer_bytes - offset; 269 count -= length; 270 length >>= 2; /* in 32bit words */ 271 /* Transfer using pseudo-dma. */ 272 while (length-- > 0) { 273 outl(cpu_to_le32(*addr), port); 274 addr++; 275 } 276 addr = (u32 *)runtime->dma_area; 277 pipe->hw_ptr = 0; 278 } 279 pipe->hw_ptr += count; 280 count >>= 2; /* in 32bit words */ 281 /* Transfer using pseudo-dma. */ 282 while (count-- > 0) { 283 outl(cpu_to_le32(*addr), port); 284 addr++; 285 } 286 287 vx2_release_pseudo_dma(chip); 288 } 289 290 291 /* pseudo dma read */ 292 static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, 293 struct vx_pipe *pipe, int count) 294 { 295 int offset = pipe->hw_ptr; 296 u32 *addr = (u32 *)(runtime->dma_area + offset); 297 unsigned long port = vx2_reg_addr(chip, VX_DMA); 298 299 if (snd_BUG_ON(count % 4)) 300 return; 301 302 vx2_setup_pseudo_dma(chip, 0); 303 /* Transfer using pseudo-dma. 304 */ 305 if (offset + count > pipe->buffer_bytes) { 306 int length = pipe->buffer_bytes - offset; 307 count -= length; 308 length >>= 2; /* in 32bit words */ 309 /* Transfer using pseudo-dma. */ 310 while (length-- > 0) 311 *addr++ = le32_to_cpu(inl(port)); 312 addr = (u32 *)runtime->dma_area; 313 pipe->hw_ptr = 0; 314 } 315 pipe->hw_ptr += count; 316 count >>= 2; /* in 32bit words */ 317 /* Transfer using pseudo-dma. */ 318 while (count-- > 0) 319 *addr++ = le32_to_cpu(inl(port)); 320 321 vx2_release_pseudo_dma(chip); 322 } 323 324 #define VX_XILINX_RESET_MASK 0x40000000 325 #define VX_USERBIT0_MASK 0x00000004 326 #define VX_USERBIT1_MASK 0x00000020 327 #define VX_CNTRL_REGISTER_VALUE 0x00172012 328 329 /* 330 * transfer counts bits to PLX 331 */ 332 static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data) 333 { 334 unsigned int i; 335 336 for (i = 0; i < counts; i++) { 337 unsigned int val; 338 339 /* set the clock bit to 0. */ 340 val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK; 341 vx2_outl(chip, port, val); 342 vx2_inl(chip, port); 343 udelay(1); 344 345 if (data & (1 << i)) 346 val |= VX_USERBIT1_MASK; 347 else 348 val &= ~VX_USERBIT1_MASK; 349 vx2_outl(chip, port, val); 350 vx2_inl(chip, port); 351 352 /* set the clock bit to 1. */ 353 val |= VX_USERBIT0_MASK; 354 vx2_outl(chip, port, val); 355 vx2_inl(chip, port); 356 udelay(1); 357 } 358 return 0; 359 } 360 361 /* 362 * load the xilinx image 363 */ 364 static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx) 365 { 366 unsigned int i; 367 unsigned int port; 368 const unsigned char *image; 369 370 /* XILINX reset (wait at least 1 millisecond between reset on and off). */ 371 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK); 372 vx_inl(chip, CNTRL); 373 msleep(10); 374 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE); 375 vx_inl(chip, CNTRL); 376 msleep(10); 377 378 if (chip->type == VX_TYPE_BOARD) 379 port = VX_CNTRL; 380 else 381 port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */ 382 383 image = xilinx->data; 384 for (i = 0; i < xilinx->size; i++, image++) { 385 if (put_xilinx_data(chip, port, 8, *image) < 0) 386 return -EINVAL; 387 /* don't take too much time in this loop... */ 388 cond_resched(); 389 } 390 put_xilinx_data(chip, port, 4, 0xff); /* end signature */ 391 392 msleep(200); 393 394 /* test after loading (is buggy with VX222) */ 395 if (chip->type != VX_TYPE_BOARD) { 396 /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */ 397 i = vx_inl(chip, GPIOC); 398 if (i & 0x0100) 399 return 0; 400 dev_err(chip->card->dev, 401 "xilinx test failed after load, GPIOC=0x%x\n", i); 402 return -EINVAL; 403 } 404 405 return 0; 406 } 407 408 409 /* 410 * load the boot/dsp images 411 */ 412 static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp) 413 { 414 int err; 415 416 switch (index) { 417 case 1: 418 /* xilinx image */ 419 if ((err = vx2_load_xilinx_binary(vx, dsp)) < 0) 420 return err; 421 if ((err = vx2_test_xilinx(vx)) < 0) 422 return err; 423 return 0; 424 case 2: 425 /* DSP boot */ 426 return snd_vx_dsp_boot(vx, dsp); 427 case 3: 428 /* DSP image */ 429 return snd_vx_dsp_load(vx, dsp); 430 default: 431 snd_BUG(); 432 return -EINVAL; 433 } 434 } 435 436 437 /* 438 * vx_test_and_ack - test and acknowledge interrupt 439 * 440 * called from irq hander, too 441 * 442 * spinlock held! 443 */ 444 static int vx2_test_and_ack(struct vx_core *chip) 445 { 446 /* not booted yet? */ 447 if (! (chip->chip_status & VX_STAT_XILINX_LOADED)) 448 return -ENXIO; 449 450 if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK)) 451 return -EIO; 452 453 /* ok, interrupts generated, now ack it */ 454 /* set ACQUIT bit up and down */ 455 vx_outl(chip, STATUS, 0); 456 /* useless read just to spend some time and maintain 457 * the ACQUIT signal up for a while ( a bus cycle ) 458 */ 459 vx_inl(chip, STATUS); 460 /* ack */ 461 vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK); 462 /* useless read just to spend some time and maintain 463 * the ACQUIT signal up for a while ( a bus cycle ) */ 464 vx_inl(chip, STATUS); 465 /* clear */ 466 vx_outl(chip, STATUS, 0); 467 468 return 0; 469 } 470 471 472 /* 473 * vx_validate_irq - enable/disable IRQ 474 */ 475 static void vx2_validate_irq(struct vx_core *_chip, int enable) 476 { 477 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 478 479 /* Set the interrupt enable bit to 1 in CDSP register */ 480 if (enable) { 481 /* Set the PCI interrupt enable bit to 1.*/ 482 vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK); 483 chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK; 484 } else { 485 /* Set the PCI interrupt enable bit to 0. */ 486 vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK); 487 chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK; 488 } 489 vx_outl(chip, CDSP, chip->regCDSP); 490 } 491 492 493 /* 494 * write an AKM codec data (24bit) 495 */ 496 static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data) 497 { 498 unsigned int i; 499 500 vx_inl(chip, HIFREQ); 501 502 /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */ 503 for (i = 0; i < 24; i++, data <<= 1) 504 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); 505 /* Terminate access to codec registers */ 506 vx_inl(chip, RUER); 507 } 508 509 510 #define AKM_CODEC_POWER_CONTROL_CMD 0xA007 511 #define AKM_CODEC_RESET_ON_CMD 0xA100 512 #define AKM_CODEC_RESET_OFF_CMD 0xA103 513 #define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240 514 #define AKM_CODEC_MUTE_CMD 0xA38D 515 #define AKM_CODEC_UNMUTE_CMD 0xA30D 516 #define AKM_CODEC_LEFT_LEVEL_CMD 0xA400 517 #define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500 518 519 static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = { 520 0x7f, // [000] = +0.000 dB -> AKM(0x7f) = +0.000 dB error(+0.000 dB) 521 0x7d, // [001] = -0.500 dB -> AKM(0x7d) = -0.572 dB error(-0.072 dB) 522 0x7c, // [002] = -1.000 dB -> AKM(0x7c) = -0.873 dB error(+0.127 dB) 523 0x7a, // [003] = -1.500 dB -> AKM(0x7a) = -1.508 dB error(-0.008 dB) 524 0x79, // [004] = -2.000 dB -> AKM(0x79) = -1.844 dB error(+0.156 dB) 525 0x77, // [005] = -2.500 dB -> AKM(0x77) = -2.557 dB error(-0.057 dB) 526 0x76, // [006] = -3.000 dB -> AKM(0x76) = -2.937 dB error(+0.063 dB) 527 0x75, // [007] = -3.500 dB -> AKM(0x75) = -3.334 dB error(+0.166 dB) 528 0x73, // [008] = -4.000 dB -> AKM(0x73) = -4.188 dB error(-0.188 dB) 529 0x72, // [009] = -4.500 dB -> AKM(0x72) = -4.648 dB error(-0.148 dB) 530 0x71, // [010] = -5.000 dB -> AKM(0x71) = -5.134 dB error(-0.134 dB) 531 0x70, // [011] = -5.500 dB -> AKM(0x70) = -5.649 dB error(-0.149 dB) 532 0x6f, // [012] = -6.000 dB -> AKM(0x6f) = -6.056 dB error(-0.056 dB) 533 0x6d, // [013] = -6.500 dB -> AKM(0x6d) = -6.631 dB error(-0.131 dB) 534 0x6c, // [014] = -7.000 dB -> AKM(0x6c) = -6.933 dB error(+0.067 dB) 535 0x6a, // [015] = -7.500 dB -> AKM(0x6a) = -7.571 dB error(-0.071 dB) 536 0x69, // [016] = -8.000 dB -> AKM(0x69) = -7.909 dB error(+0.091 dB) 537 0x67, // [017] = -8.500 dB -> AKM(0x67) = -8.626 dB error(-0.126 dB) 538 0x66, // [018] = -9.000 dB -> AKM(0x66) = -9.008 dB error(-0.008 dB) 539 0x65, // [019] = -9.500 dB -> AKM(0x65) = -9.407 dB error(+0.093 dB) 540 0x64, // [020] = -10.000 dB -> AKM(0x64) = -9.826 dB error(+0.174 dB) 541 0x62, // [021] = -10.500 dB -> AKM(0x62) = -10.730 dB error(-0.230 dB) 542 0x61, // [022] = -11.000 dB -> AKM(0x61) = -11.219 dB error(-0.219 dB) 543 0x60, // [023] = -11.500 dB -> AKM(0x60) = -11.738 dB error(-0.238 dB) 544 0x5f, // [024] = -12.000 dB -> AKM(0x5f) = -12.149 dB error(-0.149 dB) 545 0x5e, // [025] = -12.500 dB -> AKM(0x5e) = -12.434 dB error(+0.066 dB) 546 0x5c, // [026] = -13.000 dB -> AKM(0x5c) = -13.033 dB error(-0.033 dB) 547 0x5b, // [027] = -13.500 dB -> AKM(0x5b) = -13.350 dB error(+0.150 dB) 548 0x59, // [028] = -14.000 dB -> AKM(0x59) = -14.018 dB error(-0.018 dB) 549 0x58, // [029] = -14.500 dB -> AKM(0x58) = -14.373 dB error(+0.127 dB) 550 0x56, // [030] = -15.000 dB -> AKM(0x56) = -15.130 dB error(-0.130 dB) 551 0x55, // [031] = -15.500 dB -> AKM(0x55) = -15.534 dB error(-0.034 dB) 552 0x54, // [032] = -16.000 dB -> AKM(0x54) = -15.958 dB error(+0.042 dB) 553 0x53, // [033] = -16.500 dB -> AKM(0x53) = -16.404 dB error(+0.096 dB) 554 0x52, // [034] = -17.000 dB -> AKM(0x52) = -16.874 dB error(+0.126 dB) 555 0x51, // [035] = -17.500 dB -> AKM(0x51) = -17.371 dB error(+0.129 dB) 556 0x50, // [036] = -18.000 dB -> AKM(0x50) = -17.898 dB error(+0.102 dB) 557 0x4e, // [037] = -18.500 dB -> AKM(0x4e) = -18.605 dB error(-0.105 dB) 558 0x4d, // [038] = -19.000 dB -> AKM(0x4d) = -18.905 dB error(+0.095 dB) 559 0x4b, // [039] = -19.500 dB -> AKM(0x4b) = -19.538 dB error(-0.038 dB) 560 0x4a, // [040] = -20.000 dB -> AKM(0x4a) = -19.872 dB error(+0.128 dB) 561 0x48, // [041] = -20.500 dB -> AKM(0x48) = -20.583 dB error(-0.083 dB) 562 0x47, // [042] = -21.000 dB -> AKM(0x47) = -20.961 dB error(+0.039 dB) 563 0x46, // [043] = -21.500 dB -> AKM(0x46) = -21.356 dB error(+0.144 dB) 564 0x44, // [044] = -22.000 dB -> AKM(0x44) = -22.206 dB error(-0.206 dB) 565 0x43, // [045] = -22.500 dB -> AKM(0x43) = -22.664 dB error(-0.164 dB) 566 0x42, // [046] = -23.000 dB -> AKM(0x42) = -23.147 dB error(-0.147 dB) 567 0x41, // [047] = -23.500 dB -> AKM(0x41) = -23.659 dB error(-0.159 dB) 568 0x40, // [048] = -24.000 dB -> AKM(0x40) = -24.203 dB error(-0.203 dB) 569 0x3f, // [049] = -24.500 dB -> AKM(0x3f) = -24.635 dB error(-0.135 dB) 570 0x3e, // [050] = -25.000 dB -> AKM(0x3e) = -24.935 dB error(+0.065 dB) 571 0x3c, // [051] = -25.500 dB -> AKM(0x3c) = -25.569 dB error(-0.069 dB) 572 0x3b, // [052] = -26.000 dB -> AKM(0x3b) = -25.904 dB error(+0.096 dB) 573 0x39, // [053] = -26.500 dB -> AKM(0x39) = -26.615 dB error(-0.115 dB) 574 0x38, // [054] = -27.000 dB -> AKM(0x38) = -26.994 dB error(+0.006 dB) 575 0x37, // [055] = -27.500 dB -> AKM(0x37) = -27.390 dB error(+0.110 dB) 576 0x36, // [056] = -28.000 dB -> AKM(0x36) = -27.804 dB error(+0.196 dB) 577 0x34, // [057] = -28.500 dB -> AKM(0x34) = -28.699 dB error(-0.199 dB) 578 0x33, // [058] = -29.000 dB -> AKM(0x33) = -29.183 dB error(-0.183 dB) 579 0x32, // [059] = -29.500 dB -> AKM(0x32) = -29.696 dB error(-0.196 dB) 580 0x31, // [060] = -30.000 dB -> AKM(0x31) = -30.241 dB error(-0.241 dB) 581 0x31, // [061] = -30.500 dB -> AKM(0x31) = -30.241 dB error(+0.259 dB) 582 0x30, // [062] = -31.000 dB -> AKM(0x30) = -30.823 dB error(+0.177 dB) 583 0x2e, // [063] = -31.500 dB -> AKM(0x2e) = -31.610 dB error(-0.110 dB) 584 0x2d, // [064] = -32.000 dB -> AKM(0x2d) = -31.945 dB error(+0.055 dB) 585 0x2b, // [065] = -32.500 dB -> AKM(0x2b) = -32.659 dB error(-0.159 dB) 586 0x2a, // [066] = -33.000 dB -> AKM(0x2a) = -33.038 dB error(-0.038 dB) 587 0x29, // [067] = -33.500 dB -> AKM(0x29) = -33.435 dB error(+0.065 dB) 588 0x28, // [068] = -34.000 dB -> AKM(0x28) = -33.852 dB error(+0.148 dB) 589 0x27, // [069] = -34.500 dB -> AKM(0x27) = -34.289 dB error(+0.211 dB) 590 0x25, // [070] = -35.000 dB -> AKM(0x25) = -35.235 dB error(-0.235 dB) 591 0x24, // [071] = -35.500 dB -> AKM(0x24) = -35.750 dB error(-0.250 dB) 592 0x24, // [072] = -36.000 dB -> AKM(0x24) = -35.750 dB error(+0.250 dB) 593 0x23, // [073] = -36.500 dB -> AKM(0x23) = -36.297 dB error(+0.203 dB) 594 0x22, // [074] = -37.000 dB -> AKM(0x22) = -36.881 dB error(+0.119 dB) 595 0x21, // [075] = -37.500 dB -> AKM(0x21) = -37.508 dB error(-0.008 dB) 596 0x20, // [076] = -38.000 dB -> AKM(0x20) = -38.183 dB error(-0.183 dB) 597 0x1f, // [077] = -38.500 dB -> AKM(0x1f) = -38.726 dB error(-0.226 dB) 598 0x1e, // [078] = -39.000 dB -> AKM(0x1e) = -39.108 dB error(-0.108 dB) 599 0x1d, // [079] = -39.500 dB -> AKM(0x1d) = -39.507 dB error(-0.007 dB) 600 0x1c, // [080] = -40.000 dB -> AKM(0x1c) = -39.926 dB error(+0.074 dB) 601 0x1b, // [081] = -40.500 dB -> AKM(0x1b) = -40.366 dB error(+0.134 dB) 602 0x1a, // [082] = -41.000 dB -> AKM(0x1a) = -40.829 dB error(+0.171 dB) 603 0x19, // [083] = -41.500 dB -> AKM(0x19) = -41.318 dB error(+0.182 dB) 604 0x18, // [084] = -42.000 dB -> AKM(0x18) = -41.837 dB error(+0.163 dB) 605 0x17, // [085] = -42.500 dB -> AKM(0x17) = -42.389 dB error(+0.111 dB) 606 0x16, // [086] = -43.000 dB -> AKM(0x16) = -42.978 dB error(+0.022 dB) 607 0x15, // [087] = -43.500 dB -> AKM(0x15) = -43.610 dB error(-0.110 dB) 608 0x14, // [088] = -44.000 dB -> AKM(0x14) = -44.291 dB error(-0.291 dB) 609 0x14, // [089] = -44.500 dB -> AKM(0x14) = -44.291 dB error(+0.209 dB) 610 0x13, // [090] = -45.000 dB -> AKM(0x13) = -45.031 dB error(-0.031 dB) 611 0x12, // [091] = -45.500 dB -> AKM(0x12) = -45.840 dB error(-0.340 dB) 612 0x12, // [092] = -46.000 dB -> AKM(0x12) = -45.840 dB error(+0.160 dB) 613 0x11, // [093] = -46.500 dB -> AKM(0x11) = -46.731 dB error(-0.231 dB) 614 0x11, // [094] = -47.000 dB -> AKM(0x11) = -46.731 dB error(+0.269 dB) 615 0x10, // [095] = -47.500 dB -> AKM(0x10) = -47.725 dB error(-0.225 dB) 616 0x10, // [096] = -48.000 dB -> AKM(0x10) = -47.725 dB error(+0.275 dB) 617 0x0f, // [097] = -48.500 dB -> AKM(0x0f) = -48.553 dB error(-0.053 dB) 618 0x0e, // [098] = -49.000 dB -> AKM(0x0e) = -49.152 dB error(-0.152 dB) 619 0x0d, // [099] = -49.500 dB -> AKM(0x0d) = -49.796 dB error(-0.296 dB) 620 0x0d, // [100] = -50.000 dB -> AKM(0x0d) = -49.796 dB error(+0.204 dB) 621 0x0c, // [101] = -50.500 dB -> AKM(0x0c) = -50.491 dB error(+0.009 dB) 622 0x0b, // [102] = -51.000 dB -> AKM(0x0b) = -51.247 dB error(-0.247 dB) 623 0x0b, // [103] = -51.500 dB -> AKM(0x0b) = -51.247 dB error(+0.253 dB) 624 0x0a, // [104] = -52.000 dB -> AKM(0x0a) = -52.075 dB error(-0.075 dB) 625 0x0a, // [105] = -52.500 dB -> AKM(0x0a) = -52.075 dB error(+0.425 dB) 626 0x09, // [106] = -53.000 dB -> AKM(0x09) = -52.990 dB error(+0.010 dB) 627 0x09, // [107] = -53.500 dB -> AKM(0x09) = -52.990 dB error(+0.510 dB) 628 0x08, // [108] = -54.000 dB -> AKM(0x08) = -54.013 dB error(-0.013 dB) 629 0x08, // [109] = -54.500 dB -> AKM(0x08) = -54.013 dB error(+0.487 dB) 630 0x07, // [110] = -55.000 dB -> AKM(0x07) = -55.173 dB error(-0.173 dB) 631 0x07, // [111] = -55.500 dB -> AKM(0x07) = -55.173 dB error(+0.327 dB) 632 0x06, // [112] = -56.000 dB -> AKM(0x06) = -56.512 dB error(-0.512 dB) 633 0x06, // [113] = -56.500 dB -> AKM(0x06) = -56.512 dB error(-0.012 dB) 634 0x06, // [114] = -57.000 dB -> AKM(0x06) = -56.512 dB error(+0.488 dB) 635 0x05, // [115] = -57.500 dB -> AKM(0x05) = -58.095 dB error(-0.595 dB) 636 0x05, // [116] = -58.000 dB -> AKM(0x05) = -58.095 dB error(-0.095 dB) 637 0x05, // [117] = -58.500 dB -> AKM(0x05) = -58.095 dB error(+0.405 dB) 638 0x05, // [118] = -59.000 dB -> AKM(0x05) = -58.095 dB error(+0.905 dB) 639 0x04, // [119] = -59.500 dB -> AKM(0x04) = -60.034 dB error(-0.534 dB) 640 0x04, // [120] = -60.000 dB -> AKM(0x04) = -60.034 dB error(-0.034 dB) 641 0x04, // [121] = -60.500 dB -> AKM(0x04) = -60.034 dB error(+0.466 dB) 642 0x04, // [122] = -61.000 dB -> AKM(0x04) = -60.034 dB error(+0.966 dB) 643 0x03, // [123] = -61.500 dB -> AKM(0x03) = -62.532 dB error(-1.032 dB) 644 0x03, // [124] = -62.000 dB -> AKM(0x03) = -62.532 dB error(-0.532 dB) 645 0x03, // [125] = -62.500 dB -> AKM(0x03) = -62.532 dB error(-0.032 dB) 646 0x03, // [126] = -63.000 dB -> AKM(0x03) = -62.532 dB error(+0.468 dB) 647 0x03, // [127] = -63.500 dB -> AKM(0x03) = -62.532 dB error(+0.968 dB) 648 0x03, // [128] = -64.000 dB -> AKM(0x03) = -62.532 dB error(+1.468 dB) 649 0x02, // [129] = -64.500 dB -> AKM(0x02) = -66.054 dB error(-1.554 dB) 650 0x02, // [130] = -65.000 dB -> AKM(0x02) = -66.054 dB error(-1.054 dB) 651 0x02, // [131] = -65.500 dB -> AKM(0x02) = -66.054 dB error(-0.554 dB) 652 0x02, // [132] = -66.000 dB -> AKM(0x02) = -66.054 dB error(-0.054 dB) 653 0x02, // [133] = -66.500 dB -> AKM(0x02) = -66.054 dB error(+0.446 dB) 654 0x02, // [134] = -67.000 dB -> AKM(0x02) = -66.054 dB error(+0.946 dB) 655 0x02, // [135] = -67.500 dB -> AKM(0x02) = -66.054 dB error(+1.446 dB) 656 0x02, // [136] = -68.000 dB -> AKM(0x02) = -66.054 dB error(+1.946 dB) 657 0x02, // [137] = -68.500 dB -> AKM(0x02) = -66.054 dB error(+2.446 dB) 658 0x02, // [138] = -69.000 dB -> AKM(0x02) = -66.054 dB error(+2.946 dB) 659 0x01, // [139] = -69.500 dB -> AKM(0x01) = -72.075 dB error(-2.575 dB) 660 0x01, // [140] = -70.000 dB -> AKM(0x01) = -72.075 dB error(-2.075 dB) 661 0x01, // [141] = -70.500 dB -> AKM(0x01) = -72.075 dB error(-1.575 dB) 662 0x01, // [142] = -71.000 dB -> AKM(0x01) = -72.075 dB error(-1.075 dB) 663 0x01, // [143] = -71.500 dB -> AKM(0x01) = -72.075 dB error(-0.575 dB) 664 0x01, // [144] = -72.000 dB -> AKM(0x01) = -72.075 dB error(-0.075 dB) 665 0x01, // [145] = -72.500 dB -> AKM(0x01) = -72.075 dB error(+0.425 dB) 666 0x01, // [146] = -73.000 dB -> AKM(0x01) = -72.075 dB error(+0.925 dB) 667 0x00}; // [147] = -73.500 dB -> AKM(0x00) = mute error(+infini) 668 669 /* 670 * pseudo-codec write entry 671 */ 672 static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data) 673 { 674 unsigned int val; 675 676 if (reg == XX_CODEC_DAC_CONTROL_REGISTER) { 677 vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD); 678 return; 679 } 680 681 /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need 682 a look up table, as there is no linear matching between the driver codec values 683 and the real dBu value 684 */ 685 if (snd_BUG_ON(data >= sizeof(vx2_akm_gains_lut))) 686 return; 687 688 switch (reg) { 689 case XX_CODEC_LEVEL_LEFT_REGISTER: 690 val = AKM_CODEC_LEFT_LEVEL_CMD; 691 break; 692 case XX_CODEC_LEVEL_RIGHT_REGISTER: 693 val = AKM_CODEC_RIGHT_LEVEL_CMD; 694 break; 695 default: 696 snd_BUG(); 697 return; 698 } 699 val |= vx2_akm_gains_lut[data]; 700 701 vx2_write_codec_reg(chip, val); 702 } 703 704 705 /* 706 * write codec bit for old VX222 board 707 */ 708 static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data) 709 { 710 int i; 711 712 /* activate access to codec registers */ 713 vx_inl(chip, HIFREQ); 714 715 for (i = 0; i < 24; i++, data <<= 1) 716 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); 717 718 /* Terminate access to codec registers */ 719 vx_inl(chip, RUER); 720 } 721 722 723 /* 724 * reset codec bit 725 */ 726 static void vx2_reset_codec(struct vx_core *_chip) 727 { 728 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 729 730 /* Set the reset CODEC bit to 0. */ 731 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); 732 vx_inl(chip, CDSP); 733 msleep(10); 734 /* Set the reset CODEC bit to 1. */ 735 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK; 736 vx_outl(chip, CDSP, chip->regCDSP); 737 vx_inl(chip, CDSP); 738 if (_chip->type == VX_TYPE_BOARD) { 739 msleep(1); 740 return; 741 } 742 743 msleep(5); /* additionnel wait time for AKM's */ 744 745 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */ 746 747 vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */ 748 vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */ 749 vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */ 750 751 if (_chip->type == VX_TYPE_MIC) { 752 /* set up the micro input selector */ 753 chip->regSELMIC = MICRO_SELECT_INPUT_NORM | 754 MICRO_SELECT_PREAMPLI_G_0 | 755 MICRO_SELECT_NOISE_T_52DB; 756 757 /* reset phantom power supply */ 758 chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM; 759 760 vx_outl(_chip, SELMIC, chip->regSELMIC); 761 } 762 } 763 764 765 /* 766 * change the audio source 767 */ 768 static void vx2_change_audio_source(struct vx_core *_chip, int src) 769 { 770 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 771 772 switch (src) { 773 case VX_AUDIO_SRC_DIGITAL: 774 chip->regCFG |= VX_CFG_DATAIN_SEL_MASK; 775 break; 776 default: 777 chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK; 778 break; 779 } 780 vx_outl(chip, CFG, chip->regCFG); 781 } 782 783 784 /* 785 * set the clock source 786 */ 787 static void vx2_set_clock_source(struct vx_core *_chip, int source) 788 { 789 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 790 791 if (source == INTERNAL_QUARTZ) 792 chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK; 793 else 794 chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK; 795 vx_outl(chip, CFG, chip->regCFG); 796 } 797 798 /* 799 * reset the board 800 */ 801 static void vx2_reset_board(struct vx_core *_chip, int cold_reset) 802 { 803 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 804 805 /* initialize the register values */ 806 chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ; 807 chip->regCFG = 0; 808 } 809 810 811 812 /* 813 * input level controls for VX222 Mic 814 */ 815 816 /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318), 817 * 318 = 210 + 36 + 36 + 36 (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli) 818 * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset ! 819 */ 820 #define V2_MICRO_LEVEL_RANGE (318 - 255) 821 822 static void vx2_set_input_level(struct snd_vx222 *chip) 823 { 824 int i, miclevel, preamp; 825 unsigned int data; 826 827 miclevel = chip->mic_level; 828 miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */ 829 preamp = 0; 830 while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */ 831 preamp++; /* raise pre ampli + 18dB */ 832 miclevel -= (18 * 2); /* lower level 18 dB (*2 because of 0.5 dB steps !) */ 833 } 834 if (snd_BUG_ON(preamp >= 4)) 835 return; 836 837 /* set pre-amp level */ 838 chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK; 839 chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK; 840 vx_outl(chip, SELMIC, chip->regSELMIC); 841 842 data = (unsigned int)miclevel << 16 | 843 (unsigned int)chip->input_level[1] << 8 | 844 (unsigned int)chip->input_level[0]; 845 vx_inl(chip, DATA); /* Activate input level programming */ 846 847 /* We have to send 32 bits (4 x 8 bits) */ 848 for (i = 0; i < 32; i++, data <<= 1) 849 vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0)); 850 851 vx_inl(chip, RUER); /* Terminate input level programming */ 852 } 853 854 855 #define MIC_LEVEL_MAX 0xff 856 857 static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0); 858 859 /* 860 * controls API for input levels 861 */ 862 863 /* input levels */ 864 static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 865 { 866 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 867 uinfo->count = 2; 868 uinfo->value.integer.min = 0; 869 uinfo->value.integer.max = MIC_LEVEL_MAX; 870 return 0; 871 } 872 873 static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 874 { 875 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 876 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 877 mutex_lock(&_chip->mixer_mutex); 878 ucontrol->value.integer.value[0] = chip->input_level[0]; 879 ucontrol->value.integer.value[1] = chip->input_level[1]; 880 mutex_unlock(&_chip->mixer_mutex); 881 return 0; 882 } 883 884 static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 885 { 886 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 887 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 888 if (ucontrol->value.integer.value[0] < 0 || 889 ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) 890 return -EINVAL; 891 if (ucontrol->value.integer.value[1] < 0 || 892 ucontrol->value.integer.value[1] > MIC_LEVEL_MAX) 893 return -EINVAL; 894 mutex_lock(&_chip->mixer_mutex); 895 if (chip->input_level[0] != ucontrol->value.integer.value[0] || 896 chip->input_level[1] != ucontrol->value.integer.value[1]) { 897 chip->input_level[0] = ucontrol->value.integer.value[0]; 898 chip->input_level[1] = ucontrol->value.integer.value[1]; 899 vx2_set_input_level(chip); 900 mutex_unlock(&_chip->mixer_mutex); 901 return 1; 902 } 903 mutex_unlock(&_chip->mixer_mutex); 904 return 0; 905 } 906 907 /* mic level */ 908 static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 909 { 910 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 911 uinfo->count = 1; 912 uinfo->value.integer.min = 0; 913 uinfo->value.integer.max = MIC_LEVEL_MAX; 914 return 0; 915 } 916 917 static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 918 { 919 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 920 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 921 ucontrol->value.integer.value[0] = chip->mic_level; 922 return 0; 923 } 924 925 static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 926 { 927 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 928 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 929 if (ucontrol->value.integer.value[0] < 0 || 930 ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) 931 return -EINVAL; 932 mutex_lock(&_chip->mixer_mutex); 933 if (chip->mic_level != ucontrol->value.integer.value[0]) { 934 chip->mic_level = ucontrol->value.integer.value[0]; 935 vx2_set_input_level(chip); 936 mutex_unlock(&_chip->mixer_mutex); 937 return 1; 938 } 939 mutex_unlock(&_chip->mixer_mutex); 940 return 0; 941 } 942 943 static struct snd_kcontrol_new vx_control_input_level = { 944 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 945 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 946 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 947 .name = "Capture Volume", 948 .info = vx_input_level_info, 949 .get = vx_input_level_get, 950 .put = vx_input_level_put, 951 .tlv = { .p = db_scale_mic }, 952 }; 953 954 static struct snd_kcontrol_new vx_control_mic_level = { 955 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 956 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 957 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 958 .name = "Mic Capture Volume", 959 .info = vx_mic_level_info, 960 .get = vx_mic_level_get, 961 .put = vx_mic_level_put, 962 .tlv = { .p = db_scale_mic }, 963 }; 964 965 /* 966 * FIXME: compressor/limiter implementation is missing yet... 967 */ 968 969 static int vx2_add_mic_controls(struct vx_core *_chip) 970 { 971 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 972 int err; 973 974 if (_chip->type != VX_TYPE_MIC) 975 return 0; 976 977 /* mute input levels */ 978 chip->input_level[0] = chip->input_level[1] = 0; 979 chip->mic_level = 0; 980 vx2_set_input_level(chip); 981 982 /* controls */ 983 if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip))) < 0) 984 return err; 985 if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip))) < 0) 986 return err; 987 988 return 0; 989 } 990 991 992 /* 993 * callbacks 994 */ 995 struct snd_vx_ops vx222_ops = { 996 .in8 = vx2_inb, 997 .in32 = vx2_inl, 998 .out8 = vx2_outb, 999 .out32 = vx2_outl, 1000 .test_and_ack = vx2_test_and_ack, 1001 .validate_irq = vx2_validate_irq, 1002 .akm_write = vx2_write_akm, 1003 .reset_codec = vx2_reset_codec, 1004 .change_audio_source = vx2_change_audio_source, 1005 .set_clock_source = vx2_set_clock_source, 1006 .load_dsp = vx2_load_dsp, 1007 .reset_dsp = vx2_reset_dsp, 1008 .reset_board = vx2_reset_board, 1009 .dma_write = vx2_dma_write, 1010 .dma_read = vx2_dma_read, 1011 .add_controls = vx2_add_mic_controls, 1012 }; 1013 1014 /* for old VX222 board */ 1015 struct snd_vx_ops vx222_old_ops = { 1016 .in8 = vx2_inb, 1017 .in32 = vx2_inl, 1018 .out8 = vx2_outb, 1019 .out32 = vx2_outl, 1020 .test_and_ack = vx2_test_and_ack, 1021 .validate_irq = vx2_validate_irq, 1022 .write_codec = vx2_old_write_codec_bit, 1023 .reset_codec = vx2_reset_codec, 1024 .change_audio_source = vx2_change_audio_source, 1025 .set_clock_source = vx2_set_clock_source, 1026 .load_dsp = vx2_load_dsp, 1027 .reset_dsp = vx2_reset_dsp, 1028 .reset_board = vx2_reset_board, 1029 .dma_write = vx2_dma_write, 1030 .dma_read = vx2_dma_read, 1031 }; 1032 1033