1 /* 2 * Driver for Digigram VX222 V2/Mic soundcards 3 * 4 * VX222-specific low-level routines 5 * 6 * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/device.h> 25 #include <linux/firmware.h> 26 #include <linux/mutex.h> 27 28 #include <sound/core.h> 29 #include <sound/control.h> 30 #include <sound/tlv.h> 31 #include <asm/io.h> 32 #include "vx222.h" 33 34 35 static int vx2_reg_offset[VX_REG_MAX] = { 36 [VX_ICR] = 0x00, 37 [VX_CVR] = 0x04, 38 [VX_ISR] = 0x08, 39 [VX_IVR] = 0x0c, 40 [VX_RXH] = 0x14, 41 [VX_RXM] = 0x18, 42 [VX_RXL] = 0x1c, 43 [VX_DMA] = 0x10, 44 [VX_CDSP] = 0x20, 45 [VX_CFG] = 0x24, 46 [VX_RUER] = 0x28, 47 [VX_DATA] = 0x2c, 48 [VX_STATUS] = 0x30, 49 [VX_LOFREQ] = 0x34, 50 [VX_HIFREQ] = 0x38, 51 [VX_CSUER] = 0x3c, 52 [VX_SELMIC] = 0x40, 53 [VX_COMPOT] = 0x44, // Write: POTENTIOMETER ; Read: COMPRESSION LEVEL activate 54 [VX_SCOMPR] = 0x48, // Read: COMPRESSION THRESHOLD activate 55 [VX_GLIMIT] = 0x4c, // Read: LEVEL LIMITATION activate 56 [VX_INTCSR] = 0x4c, // VX_INTCSR_REGISTER_OFFSET 57 [VX_CNTRL] = 0x50, // VX_CNTRL_REGISTER_OFFSET 58 [VX_GPIOC] = 0x54, // VX_GPIOC (new with PLX9030) 59 }; 60 61 static int vx2_reg_index[VX_REG_MAX] = { 62 [VX_ICR] = 1, 63 [VX_CVR] = 1, 64 [VX_ISR] = 1, 65 [VX_IVR] = 1, 66 [VX_RXH] = 1, 67 [VX_RXM] = 1, 68 [VX_RXL] = 1, 69 [VX_DMA] = 1, 70 [VX_CDSP] = 1, 71 [VX_CFG] = 1, 72 [VX_RUER] = 1, 73 [VX_DATA] = 1, 74 [VX_STATUS] = 1, 75 [VX_LOFREQ] = 1, 76 [VX_HIFREQ] = 1, 77 [VX_CSUER] = 1, 78 [VX_SELMIC] = 1, 79 [VX_COMPOT] = 1, 80 [VX_SCOMPR] = 1, 81 [VX_GLIMIT] = 1, 82 [VX_INTCSR] = 0, /* on the PLX */ 83 [VX_CNTRL] = 0, /* on the PLX */ 84 [VX_GPIOC] = 0, /* on the PLX */ 85 }; 86 87 static inline unsigned long vx2_reg_addr(struct vx_core *_chip, int reg) 88 { 89 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 90 return chip->port[vx2_reg_index[reg]] + vx2_reg_offset[reg]; 91 } 92 93 /** 94 * snd_vx_inb - read a byte from the register 95 * @offset: register enum 96 */ 97 static unsigned char vx2_inb(struct vx_core *chip, int offset) 98 { 99 return inb(vx2_reg_addr(chip, offset)); 100 } 101 102 /** 103 * snd_vx_outb - write a byte on the register 104 * @offset: the register offset 105 * @val: the value to write 106 */ 107 static void vx2_outb(struct vx_core *chip, int offset, unsigned char val) 108 { 109 outb(val, vx2_reg_addr(chip, offset)); 110 //printk("outb: %x -> %x\n", val, vx2_reg_addr(chip, offset)); 111 } 112 113 /** 114 * snd_vx_inl - read a 32bit word from the register 115 * @offset: register enum 116 */ 117 static unsigned int vx2_inl(struct vx_core *chip, int offset) 118 { 119 return inl(vx2_reg_addr(chip, offset)); 120 } 121 122 /** 123 * snd_vx_outl - write a 32bit word on the register 124 * @offset: the register enum 125 * @val: the value to write 126 */ 127 static void vx2_outl(struct vx_core *chip, int offset, unsigned int val) 128 { 129 // printk("outl: %x -> %x\n", val, vx2_reg_addr(chip, offset)); 130 outl(val, vx2_reg_addr(chip, offset)); 131 } 132 133 /* 134 * redefine macros to call directly 135 */ 136 #undef vx_inb 137 #define vx_inb(chip,reg) vx2_inb((struct vx_core*)(chip), VX_##reg) 138 #undef vx_outb 139 #define vx_outb(chip,reg,val) vx2_outb((struct vx_core*)(chip), VX_##reg, val) 140 #undef vx_inl 141 #define vx_inl(chip,reg) vx2_inl((struct vx_core*)(chip), VX_##reg) 142 #undef vx_outl 143 #define vx_outl(chip,reg,val) vx2_outl((struct vx_core*)(chip), VX_##reg, val) 144 145 146 /* 147 * vx_reset_dsp - reset the DSP 148 */ 149 150 #define XX_DSP_RESET_WAIT_TIME 2 /* ms */ 151 152 static void vx2_reset_dsp(struct vx_core *_chip) 153 { 154 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 155 156 /* set the reset dsp bit to 0 */ 157 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_DSP_RESET_MASK); 158 159 mdelay(XX_DSP_RESET_WAIT_TIME); 160 161 chip->regCDSP |= VX_CDSP_DSP_RESET_MASK; 162 /* set the reset dsp bit to 1 */ 163 vx_outl(chip, CDSP, chip->regCDSP); 164 } 165 166 167 static int vx2_test_xilinx(struct vx_core *_chip) 168 { 169 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 170 unsigned int data; 171 172 snd_printdd("testing xilinx...\n"); 173 /* This test uses several write/read sequences on TEST0 and TEST1 bits 174 * to figure out whever or not the xilinx was correctly loaded 175 */ 176 177 /* We write 1 on CDSP.TEST0. We should get 0 on STATUS.TEST0. */ 178 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST0_MASK); 179 vx_inl(chip, ISR); 180 data = vx_inl(chip, STATUS); 181 if ((data & VX_STATUS_VAL_TEST0_MASK) == VX_STATUS_VAL_TEST0_MASK) { 182 snd_printdd("bad!\n"); 183 return -ENODEV; 184 } 185 186 /* We write 0 on CDSP.TEST0. We should get 1 on STATUS.TEST0. */ 187 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST0_MASK); 188 vx_inl(chip, ISR); 189 data = vx_inl(chip, STATUS); 190 if (! (data & VX_STATUS_VAL_TEST0_MASK)) { 191 snd_printdd("bad! #2\n"); 192 return -ENODEV; 193 } 194 195 if (_chip->type == VX_TYPE_BOARD) { 196 /* not implemented on VX_2_BOARDS */ 197 /* We write 1 on CDSP.TEST1. We should get 0 on STATUS.TEST1. */ 198 vx_outl(chip, CDSP, chip->regCDSP | VX_CDSP_TEST1_MASK); 199 vx_inl(chip, ISR); 200 data = vx_inl(chip, STATUS); 201 if ((data & VX_STATUS_VAL_TEST1_MASK) == VX_STATUS_VAL_TEST1_MASK) { 202 snd_printdd("bad! #3\n"); 203 return -ENODEV; 204 } 205 206 /* We write 0 on CDSP.TEST1. We should get 1 on STATUS.TEST1. */ 207 vx_outl(chip, CDSP, chip->regCDSP & ~VX_CDSP_TEST1_MASK); 208 vx_inl(chip, ISR); 209 data = vx_inl(chip, STATUS); 210 if (! (data & VX_STATUS_VAL_TEST1_MASK)) { 211 snd_printdd("bad! #4\n"); 212 return -ENODEV; 213 } 214 } 215 snd_printdd("ok, xilinx fine.\n"); 216 return 0; 217 } 218 219 220 /** 221 * vx_setup_pseudo_dma - set up the pseudo dma read/write mode. 222 * @do_write: 0 = read, 1 = set up for DMA write 223 */ 224 static void vx2_setup_pseudo_dma(struct vx_core *chip, int do_write) 225 { 226 /* Interrupt mode and HREQ pin enabled for host transmit data transfers 227 * (in case of the use of the pseudo-dma facility). 228 */ 229 vx_outl(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); 230 231 /* Reset the pseudo-dma register (in case of the use of the 232 * pseudo-dma facility). 233 */ 234 vx_outl(chip, RESET_DMA, 0); 235 } 236 237 /* 238 * vx_release_pseudo_dma - disable the pseudo-DMA mode 239 */ 240 static inline void vx2_release_pseudo_dma(struct vx_core *chip) 241 { 242 /* HREQ pin disabled. */ 243 vx_outl(chip, ICR, 0); 244 } 245 246 247 248 /* pseudo-dma write */ 249 static void vx2_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, 250 struct vx_pipe *pipe, int count) 251 { 252 unsigned long port = vx2_reg_addr(chip, VX_DMA); 253 int offset = pipe->hw_ptr; 254 u32 *addr = (u32 *)(runtime->dma_area + offset); 255 256 snd_assert(count % 4 == 0, return); 257 258 vx2_setup_pseudo_dma(chip, 1); 259 260 /* Transfer using pseudo-dma. 261 */ 262 if (offset + count > pipe->buffer_bytes) { 263 int length = pipe->buffer_bytes - offset; 264 count -= length; 265 length >>= 2; /* in 32bit words */ 266 /* Transfer using pseudo-dma. */ 267 while (length-- > 0) { 268 outl(cpu_to_le32(*addr), port); 269 addr++; 270 } 271 addr = (u32 *)runtime->dma_area; 272 pipe->hw_ptr = 0; 273 } 274 pipe->hw_ptr += count; 275 count >>= 2; /* in 32bit words */ 276 /* Transfer using pseudo-dma. */ 277 while (count-- > 0) { 278 outl(cpu_to_le32(*addr), port); 279 addr++; 280 } 281 282 vx2_release_pseudo_dma(chip); 283 } 284 285 286 /* pseudo dma read */ 287 static void vx2_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, 288 struct vx_pipe *pipe, int count) 289 { 290 int offset = pipe->hw_ptr; 291 u32 *addr = (u32 *)(runtime->dma_area + offset); 292 unsigned long port = vx2_reg_addr(chip, VX_DMA); 293 294 snd_assert(count % 4 == 0, return); 295 296 vx2_setup_pseudo_dma(chip, 0); 297 /* Transfer using pseudo-dma. 298 */ 299 if (offset + count > pipe->buffer_bytes) { 300 int length = pipe->buffer_bytes - offset; 301 count -= length; 302 length >>= 2; /* in 32bit words */ 303 /* Transfer using pseudo-dma. */ 304 while (length-- > 0) 305 *addr++ = le32_to_cpu(inl(port)); 306 addr = (u32 *)runtime->dma_area; 307 pipe->hw_ptr = 0; 308 } 309 pipe->hw_ptr += count; 310 count >>= 2; /* in 32bit words */ 311 /* Transfer using pseudo-dma. */ 312 while (count-- > 0) 313 *addr++ = le32_to_cpu(inl(port)); 314 315 vx2_release_pseudo_dma(chip); 316 } 317 318 #define VX_XILINX_RESET_MASK 0x40000000 319 #define VX_USERBIT0_MASK 0x00000004 320 #define VX_USERBIT1_MASK 0x00000020 321 #define VX_CNTRL_REGISTER_VALUE 0x00172012 322 323 /* 324 * transfer counts bits to PLX 325 */ 326 static int put_xilinx_data(struct vx_core *chip, unsigned int port, unsigned int counts, unsigned char data) 327 { 328 unsigned int i; 329 330 for (i = 0; i < counts; i++) { 331 unsigned int val; 332 333 /* set the clock bit to 0. */ 334 val = VX_CNTRL_REGISTER_VALUE & ~VX_USERBIT0_MASK; 335 vx2_outl(chip, port, val); 336 vx2_inl(chip, port); 337 udelay(1); 338 339 if (data & (1 << i)) 340 val |= VX_USERBIT1_MASK; 341 else 342 val &= ~VX_USERBIT1_MASK; 343 vx2_outl(chip, port, val); 344 vx2_inl(chip, port); 345 346 /* set the clock bit to 1. */ 347 val |= VX_USERBIT0_MASK; 348 vx2_outl(chip, port, val); 349 vx2_inl(chip, port); 350 udelay(1); 351 } 352 return 0; 353 } 354 355 /* 356 * load the xilinx image 357 */ 358 static int vx2_load_xilinx_binary(struct vx_core *chip, const struct firmware *xilinx) 359 { 360 unsigned int i; 361 unsigned int port; 362 unsigned char *image; 363 364 /* XILINX reset (wait at least 1 milisecond between reset on and off). */ 365 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE | VX_XILINX_RESET_MASK); 366 vx_inl(chip, CNTRL); 367 msleep(10); 368 vx_outl(chip, CNTRL, VX_CNTRL_REGISTER_VALUE); 369 vx_inl(chip, CNTRL); 370 msleep(10); 371 372 if (chip->type == VX_TYPE_BOARD) 373 port = VX_CNTRL; 374 else 375 port = VX_GPIOC; /* VX222 V2 and VX222_MIC_BOARD with new PLX9030 use this register */ 376 377 image = xilinx->data; 378 for (i = 0; i < xilinx->size; i++, image++) { 379 if (put_xilinx_data(chip, port, 8, *image) < 0) 380 return -EINVAL; 381 /* don't take too much time in this loop... */ 382 cond_resched(); 383 } 384 put_xilinx_data(chip, port, 4, 0xff); /* end signature */ 385 386 msleep(200); 387 388 /* test after loading (is buggy with VX222) */ 389 if (chip->type != VX_TYPE_BOARD) { 390 /* Test if load successful: test bit 8 of register GPIOC (VX222: use CNTRL) ! */ 391 i = vx_inl(chip, GPIOC); 392 if (i & 0x0100) 393 return 0; 394 snd_printk(KERN_ERR "vx222: xilinx test failed after load, GPIOC=0x%x\n", i); 395 return -EINVAL; 396 } 397 398 return 0; 399 } 400 401 402 /* 403 * load the boot/dsp images 404 */ 405 static int vx2_load_dsp(struct vx_core *vx, int index, const struct firmware *dsp) 406 { 407 int err; 408 409 switch (index) { 410 case 1: 411 /* xilinx image */ 412 if ((err = vx2_load_xilinx_binary(vx, dsp)) < 0) 413 return err; 414 if ((err = vx2_test_xilinx(vx)) < 0) 415 return err; 416 return 0; 417 case 2: 418 /* DSP boot */ 419 return snd_vx_dsp_boot(vx, dsp); 420 case 3: 421 /* DSP image */ 422 return snd_vx_dsp_load(vx, dsp); 423 default: 424 snd_BUG(); 425 return -EINVAL; 426 } 427 } 428 429 430 /* 431 * vx_test_and_ack - test and acknowledge interrupt 432 * 433 * called from irq hander, too 434 * 435 * spinlock held! 436 */ 437 static int vx2_test_and_ack(struct vx_core *chip) 438 { 439 /* not booted yet? */ 440 if (! (chip->chip_status & VX_STAT_XILINX_LOADED)) 441 return -ENXIO; 442 443 if (! (vx_inl(chip, STATUS) & VX_STATUS_MEMIRQ_MASK)) 444 return -EIO; 445 446 /* ok, interrupts generated, now ack it */ 447 /* set ACQUIT bit up and down */ 448 vx_outl(chip, STATUS, 0); 449 /* useless read just to spend some time and maintain 450 * the ACQUIT signal up for a while ( a bus cycle ) 451 */ 452 vx_inl(chip, STATUS); 453 /* ack */ 454 vx_outl(chip, STATUS, VX_STATUS_MEMIRQ_MASK); 455 /* useless read just to spend some time and maintain 456 * the ACQUIT signal up for a while ( a bus cycle ) */ 457 vx_inl(chip, STATUS); 458 /* clear */ 459 vx_outl(chip, STATUS, 0); 460 461 return 0; 462 } 463 464 465 /* 466 * vx_validate_irq - enable/disable IRQ 467 */ 468 static void vx2_validate_irq(struct vx_core *_chip, int enable) 469 { 470 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 471 472 /* Set the interrupt enable bit to 1 in CDSP register */ 473 if (enable) { 474 /* Set the PCI interrupt enable bit to 1.*/ 475 vx_outl(chip, INTCSR, VX_INTCSR_VALUE|VX_PCI_INTERRUPT_MASK); 476 chip->regCDSP |= VX_CDSP_VALID_IRQ_MASK; 477 } else { 478 /* Set the PCI interrupt enable bit to 0. */ 479 vx_outl(chip, INTCSR, VX_INTCSR_VALUE&~VX_PCI_INTERRUPT_MASK); 480 chip->regCDSP &= ~VX_CDSP_VALID_IRQ_MASK; 481 } 482 vx_outl(chip, CDSP, chip->regCDSP); 483 } 484 485 486 /* 487 * write an AKM codec data (24bit) 488 */ 489 static void vx2_write_codec_reg(struct vx_core *chip, unsigned int data) 490 { 491 unsigned int i; 492 493 vx_inl(chip, HIFREQ); 494 495 /* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */ 496 for (i = 0; i < 24; i++, data <<= 1) 497 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); 498 /* Terminate access to codec registers */ 499 vx_inl(chip, RUER); 500 } 501 502 503 #define AKM_CODEC_POWER_CONTROL_CMD 0xA007 504 #define AKM_CODEC_RESET_ON_CMD 0xA100 505 #define AKM_CODEC_RESET_OFF_CMD 0xA103 506 #define AKM_CODEC_CLOCK_FORMAT_CMD 0xA240 507 #define AKM_CODEC_MUTE_CMD 0xA38D 508 #define AKM_CODEC_UNMUTE_CMD 0xA30D 509 #define AKM_CODEC_LEFT_LEVEL_CMD 0xA400 510 #define AKM_CODEC_RIGHT_LEVEL_CMD 0xA500 511 512 static const u8 vx2_akm_gains_lut[VX2_AKM_LEVEL_MAX+1] = { 513 0x7f, // [000] = +0.000 dB -> AKM(0x7f) = +0.000 dB error(+0.000 dB) 514 0x7d, // [001] = -0.500 dB -> AKM(0x7d) = -0.572 dB error(-0.072 dB) 515 0x7c, // [002] = -1.000 dB -> AKM(0x7c) = -0.873 dB error(+0.127 dB) 516 0x7a, // [003] = -1.500 dB -> AKM(0x7a) = -1.508 dB error(-0.008 dB) 517 0x79, // [004] = -2.000 dB -> AKM(0x79) = -1.844 dB error(+0.156 dB) 518 0x77, // [005] = -2.500 dB -> AKM(0x77) = -2.557 dB error(-0.057 dB) 519 0x76, // [006] = -3.000 dB -> AKM(0x76) = -2.937 dB error(+0.063 dB) 520 0x75, // [007] = -3.500 dB -> AKM(0x75) = -3.334 dB error(+0.166 dB) 521 0x73, // [008] = -4.000 dB -> AKM(0x73) = -4.188 dB error(-0.188 dB) 522 0x72, // [009] = -4.500 dB -> AKM(0x72) = -4.648 dB error(-0.148 dB) 523 0x71, // [010] = -5.000 dB -> AKM(0x71) = -5.134 dB error(-0.134 dB) 524 0x70, // [011] = -5.500 dB -> AKM(0x70) = -5.649 dB error(-0.149 dB) 525 0x6f, // [012] = -6.000 dB -> AKM(0x6f) = -6.056 dB error(-0.056 dB) 526 0x6d, // [013] = -6.500 dB -> AKM(0x6d) = -6.631 dB error(-0.131 dB) 527 0x6c, // [014] = -7.000 dB -> AKM(0x6c) = -6.933 dB error(+0.067 dB) 528 0x6a, // [015] = -7.500 dB -> AKM(0x6a) = -7.571 dB error(-0.071 dB) 529 0x69, // [016] = -8.000 dB -> AKM(0x69) = -7.909 dB error(+0.091 dB) 530 0x67, // [017] = -8.500 dB -> AKM(0x67) = -8.626 dB error(-0.126 dB) 531 0x66, // [018] = -9.000 dB -> AKM(0x66) = -9.008 dB error(-0.008 dB) 532 0x65, // [019] = -9.500 dB -> AKM(0x65) = -9.407 dB error(+0.093 dB) 533 0x64, // [020] = -10.000 dB -> AKM(0x64) = -9.826 dB error(+0.174 dB) 534 0x62, // [021] = -10.500 dB -> AKM(0x62) = -10.730 dB error(-0.230 dB) 535 0x61, // [022] = -11.000 dB -> AKM(0x61) = -11.219 dB error(-0.219 dB) 536 0x60, // [023] = -11.500 dB -> AKM(0x60) = -11.738 dB error(-0.238 dB) 537 0x5f, // [024] = -12.000 dB -> AKM(0x5f) = -12.149 dB error(-0.149 dB) 538 0x5e, // [025] = -12.500 dB -> AKM(0x5e) = -12.434 dB error(+0.066 dB) 539 0x5c, // [026] = -13.000 dB -> AKM(0x5c) = -13.033 dB error(-0.033 dB) 540 0x5b, // [027] = -13.500 dB -> AKM(0x5b) = -13.350 dB error(+0.150 dB) 541 0x59, // [028] = -14.000 dB -> AKM(0x59) = -14.018 dB error(-0.018 dB) 542 0x58, // [029] = -14.500 dB -> AKM(0x58) = -14.373 dB error(+0.127 dB) 543 0x56, // [030] = -15.000 dB -> AKM(0x56) = -15.130 dB error(-0.130 dB) 544 0x55, // [031] = -15.500 dB -> AKM(0x55) = -15.534 dB error(-0.034 dB) 545 0x54, // [032] = -16.000 dB -> AKM(0x54) = -15.958 dB error(+0.042 dB) 546 0x53, // [033] = -16.500 dB -> AKM(0x53) = -16.404 dB error(+0.096 dB) 547 0x52, // [034] = -17.000 dB -> AKM(0x52) = -16.874 dB error(+0.126 dB) 548 0x51, // [035] = -17.500 dB -> AKM(0x51) = -17.371 dB error(+0.129 dB) 549 0x50, // [036] = -18.000 dB -> AKM(0x50) = -17.898 dB error(+0.102 dB) 550 0x4e, // [037] = -18.500 dB -> AKM(0x4e) = -18.605 dB error(-0.105 dB) 551 0x4d, // [038] = -19.000 dB -> AKM(0x4d) = -18.905 dB error(+0.095 dB) 552 0x4b, // [039] = -19.500 dB -> AKM(0x4b) = -19.538 dB error(-0.038 dB) 553 0x4a, // [040] = -20.000 dB -> AKM(0x4a) = -19.872 dB error(+0.128 dB) 554 0x48, // [041] = -20.500 dB -> AKM(0x48) = -20.583 dB error(-0.083 dB) 555 0x47, // [042] = -21.000 dB -> AKM(0x47) = -20.961 dB error(+0.039 dB) 556 0x46, // [043] = -21.500 dB -> AKM(0x46) = -21.356 dB error(+0.144 dB) 557 0x44, // [044] = -22.000 dB -> AKM(0x44) = -22.206 dB error(-0.206 dB) 558 0x43, // [045] = -22.500 dB -> AKM(0x43) = -22.664 dB error(-0.164 dB) 559 0x42, // [046] = -23.000 dB -> AKM(0x42) = -23.147 dB error(-0.147 dB) 560 0x41, // [047] = -23.500 dB -> AKM(0x41) = -23.659 dB error(-0.159 dB) 561 0x40, // [048] = -24.000 dB -> AKM(0x40) = -24.203 dB error(-0.203 dB) 562 0x3f, // [049] = -24.500 dB -> AKM(0x3f) = -24.635 dB error(-0.135 dB) 563 0x3e, // [050] = -25.000 dB -> AKM(0x3e) = -24.935 dB error(+0.065 dB) 564 0x3c, // [051] = -25.500 dB -> AKM(0x3c) = -25.569 dB error(-0.069 dB) 565 0x3b, // [052] = -26.000 dB -> AKM(0x3b) = -25.904 dB error(+0.096 dB) 566 0x39, // [053] = -26.500 dB -> AKM(0x39) = -26.615 dB error(-0.115 dB) 567 0x38, // [054] = -27.000 dB -> AKM(0x38) = -26.994 dB error(+0.006 dB) 568 0x37, // [055] = -27.500 dB -> AKM(0x37) = -27.390 dB error(+0.110 dB) 569 0x36, // [056] = -28.000 dB -> AKM(0x36) = -27.804 dB error(+0.196 dB) 570 0x34, // [057] = -28.500 dB -> AKM(0x34) = -28.699 dB error(-0.199 dB) 571 0x33, // [058] = -29.000 dB -> AKM(0x33) = -29.183 dB error(-0.183 dB) 572 0x32, // [059] = -29.500 dB -> AKM(0x32) = -29.696 dB error(-0.196 dB) 573 0x31, // [060] = -30.000 dB -> AKM(0x31) = -30.241 dB error(-0.241 dB) 574 0x31, // [061] = -30.500 dB -> AKM(0x31) = -30.241 dB error(+0.259 dB) 575 0x30, // [062] = -31.000 dB -> AKM(0x30) = -30.823 dB error(+0.177 dB) 576 0x2e, // [063] = -31.500 dB -> AKM(0x2e) = -31.610 dB error(-0.110 dB) 577 0x2d, // [064] = -32.000 dB -> AKM(0x2d) = -31.945 dB error(+0.055 dB) 578 0x2b, // [065] = -32.500 dB -> AKM(0x2b) = -32.659 dB error(-0.159 dB) 579 0x2a, // [066] = -33.000 dB -> AKM(0x2a) = -33.038 dB error(-0.038 dB) 580 0x29, // [067] = -33.500 dB -> AKM(0x29) = -33.435 dB error(+0.065 dB) 581 0x28, // [068] = -34.000 dB -> AKM(0x28) = -33.852 dB error(+0.148 dB) 582 0x27, // [069] = -34.500 dB -> AKM(0x27) = -34.289 dB error(+0.211 dB) 583 0x25, // [070] = -35.000 dB -> AKM(0x25) = -35.235 dB error(-0.235 dB) 584 0x24, // [071] = -35.500 dB -> AKM(0x24) = -35.750 dB error(-0.250 dB) 585 0x24, // [072] = -36.000 dB -> AKM(0x24) = -35.750 dB error(+0.250 dB) 586 0x23, // [073] = -36.500 dB -> AKM(0x23) = -36.297 dB error(+0.203 dB) 587 0x22, // [074] = -37.000 dB -> AKM(0x22) = -36.881 dB error(+0.119 dB) 588 0x21, // [075] = -37.500 dB -> AKM(0x21) = -37.508 dB error(-0.008 dB) 589 0x20, // [076] = -38.000 dB -> AKM(0x20) = -38.183 dB error(-0.183 dB) 590 0x1f, // [077] = -38.500 dB -> AKM(0x1f) = -38.726 dB error(-0.226 dB) 591 0x1e, // [078] = -39.000 dB -> AKM(0x1e) = -39.108 dB error(-0.108 dB) 592 0x1d, // [079] = -39.500 dB -> AKM(0x1d) = -39.507 dB error(-0.007 dB) 593 0x1c, // [080] = -40.000 dB -> AKM(0x1c) = -39.926 dB error(+0.074 dB) 594 0x1b, // [081] = -40.500 dB -> AKM(0x1b) = -40.366 dB error(+0.134 dB) 595 0x1a, // [082] = -41.000 dB -> AKM(0x1a) = -40.829 dB error(+0.171 dB) 596 0x19, // [083] = -41.500 dB -> AKM(0x19) = -41.318 dB error(+0.182 dB) 597 0x18, // [084] = -42.000 dB -> AKM(0x18) = -41.837 dB error(+0.163 dB) 598 0x17, // [085] = -42.500 dB -> AKM(0x17) = -42.389 dB error(+0.111 dB) 599 0x16, // [086] = -43.000 dB -> AKM(0x16) = -42.978 dB error(+0.022 dB) 600 0x15, // [087] = -43.500 dB -> AKM(0x15) = -43.610 dB error(-0.110 dB) 601 0x14, // [088] = -44.000 dB -> AKM(0x14) = -44.291 dB error(-0.291 dB) 602 0x14, // [089] = -44.500 dB -> AKM(0x14) = -44.291 dB error(+0.209 dB) 603 0x13, // [090] = -45.000 dB -> AKM(0x13) = -45.031 dB error(-0.031 dB) 604 0x12, // [091] = -45.500 dB -> AKM(0x12) = -45.840 dB error(-0.340 dB) 605 0x12, // [092] = -46.000 dB -> AKM(0x12) = -45.840 dB error(+0.160 dB) 606 0x11, // [093] = -46.500 dB -> AKM(0x11) = -46.731 dB error(-0.231 dB) 607 0x11, // [094] = -47.000 dB -> AKM(0x11) = -46.731 dB error(+0.269 dB) 608 0x10, // [095] = -47.500 dB -> AKM(0x10) = -47.725 dB error(-0.225 dB) 609 0x10, // [096] = -48.000 dB -> AKM(0x10) = -47.725 dB error(+0.275 dB) 610 0x0f, // [097] = -48.500 dB -> AKM(0x0f) = -48.553 dB error(-0.053 dB) 611 0x0e, // [098] = -49.000 dB -> AKM(0x0e) = -49.152 dB error(-0.152 dB) 612 0x0d, // [099] = -49.500 dB -> AKM(0x0d) = -49.796 dB error(-0.296 dB) 613 0x0d, // [100] = -50.000 dB -> AKM(0x0d) = -49.796 dB error(+0.204 dB) 614 0x0c, // [101] = -50.500 dB -> AKM(0x0c) = -50.491 dB error(+0.009 dB) 615 0x0b, // [102] = -51.000 dB -> AKM(0x0b) = -51.247 dB error(-0.247 dB) 616 0x0b, // [103] = -51.500 dB -> AKM(0x0b) = -51.247 dB error(+0.253 dB) 617 0x0a, // [104] = -52.000 dB -> AKM(0x0a) = -52.075 dB error(-0.075 dB) 618 0x0a, // [105] = -52.500 dB -> AKM(0x0a) = -52.075 dB error(+0.425 dB) 619 0x09, // [106] = -53.000 dB -> AKM(0x09) = -52.990 dB error(+0.010 dB) 620 0x09, // [107] = -53.500 dB -> AKM(0x09) = -52.990 dB error(+0.510 dB) 621 0x08, // [108] = -54.000 dB -> AKM(0x08) = -54.013 dB error(-0.013 dB) 622 0x08, // [109] = -54.500 dB -> AKM(0x08) = -54.013 dB error(+0.487 dB) 623 0x07, // [110] = -55.000 dB -> AKM(0x07) = -55.173 dB error(-0.173 dB) 624 0x07, // [111] = -55.500 dB -> AKM(0x07) = -55.173 dB error(+0.327 dB) 625 0x06, // [112] = -56.000 dB -> AKM(0x06) = -56.512 dB error(-0.512 dB) 626 0x06, // [113] = -56.500 dB -> AKM(0x06) = -56.512 dB error(-0.012 dB) 627 0x06, // [114] = -57.000 dB -> AKM(0x06) = -56.512 dB error(+0.488 dB) 628 0x05, // [115] = -57.500 dB -> AKM(0x05) = -58.095 dB error(-0.595 dB) 629 0x05, // [116] = -58.000 dB -> AKM(0x05) = -58.095 dB error(-0.095 dB) 630 0x05, // [117] = -58.500 dB -> AKM(0x05) = -58.095 dB error(+0.405 dB) 631 0x05, // [118] = -59.000 dB -> AKM(0x05) = -58.095 dB error(+0.905 dB) 632 0x04, // [119] = -59.500 dB -> AKM(0x04) = -60.034 dB error(-0.534 dB) 633 0x04, // [120] = -60.000 dB -> AKM(0x04) = -60.034 dB error(-0.034 dB) 634 0x04, // [121] = -60.500 dB -> AKM(0x04) = -60.034 dB error(+0.466 dB) 635 0x04, // [122] = -61.000 dB -> AKM(0x04) = -60.034 dB error(+0.966 dB) 636 0x03, // [123] = -61.500 dB -> AKM(0x03) = -62.532 dB error(-1.032 dB) 637 0x03, // [124] = -62.000 dB -> AKM(0x03) = -62.532 dB error(-0.532 dB) 638 0x03, // [125] = -62.500 dB -> AKM(0x03) = -62.532 dB error(-0.032 dB) 639 0x03, // [126] = -63.000 dB -> AKM(0x03) = -62.532 dB error(+0.468 dB) 640 0x03, // [127] = -63.500 dB -> AKM(0x03) = -62.532 dB error(+0.968 dB) 641 0x03, // [128] = -64.000 dB -> AKM(0x03) = -62.532 dB error(+1.468 dB) 642 0x02, // [129] = -64.500 dB -> AKM(0x02) = -66.054 dB error(-1.554 dB) 643 0x02, // [130] = -65.000 dB -> AKM(0x02) = -66.054 dB error(-1.054 dB) 644 0x02, // [131] = -65.500 dB -> AKM(0x02) = -66.054 dB error(-0.554 dB) 645 0x02, // [132] = -66.000 dB -> AKM(0x02) = -66.054 dB error(-0.054 dB) 646 0x02, // [133] = -66.500 dB -> AKM(0x02) = -66.054 dB error(+0.446 dB) 647 0x02, // [134] = -67.000 dB -> AKM(0x02) = -66.054 dB error(+0.946 dB) 648 0x02, // [135] = -67.500 dB -> AKM(0x02) = -66.054 dB error(+1.446 dB) 649 0x02, // [136] = -68.000 dB -> AKM(0x02) = -66.054 dB error(+1.946 dB) 650 0x02, // [137] = -68.500 dB -> AKM(0x02) = -66.054 dB error(+2.446 dB) 651 0x02, // [138] = -69.000 dB -> AKM(0x02) = -66.054 dB error(+2.946 dB) 652 0x01, // [139] = -69.500 dB -> AKM(0x01) = -72.075 dB error(-2.575 dB) 653 0x01, // [140] = -70.000 dB -> AKM(0x01) = -72.075 dB error(-2.075 dB) 654 0x01, // [141] = -70.500 dB -> AKM(0x01) = -72.075 dB error(-1.575 dB) 655 0x01, // [142] = -71.000 dB -> AKM(0x01) = -72.075 dB error(-1.075 dB) 656 0x01, // [143] = -71.500 dB -> AKM(0x01) = -72.075 dB error(-0.575 dB) 657 0x01, // [144] = -72.000 dB -> AKM(0x01) = -72.075 dB error(-0.075 dB) 658 0x01, // [145] = -72.500 dB -> AKM(0x01) = -72.075 dB error(+0.425 dB) 659 0x01, // [146] = -73.000 dB -> AKM(0x01) = -72.075 dB error(+0.925 dB) 660 0x00}; // [147] = -73.500 dB -> AKM(0x00) = mute error(+infini) 661 662 /* 663 * pseudo-codec write entry 664 */ 665 static void vx2_write_akm(struct vx_core *chip, int reg, unsigned int data) 666 { 667 unsigned int val; 668 669 if (reg == XX_CODEC_DAC_CONTROL_REGISTER) { 670 vx2_write_codec_reg(chip, data ? AKM_CODEC_MUTE_CMD : AKM_CODEC_UNMUTE_CMD); 671 return; 672 } 673 674 /* `data' is a value between 0x0 and VX2_AKM_LEVEL_MAX = 0x093, in the case of the AKM codecs, we need 675 a look up table, as there is no linear matching between the driver codec values 676 and the real dBu value 677 */ 678 snd_assert(data < sizeof(vx2_akm_gains_lut), return); 679 680 switch (reg) { 681 case XX_CODEC_LEVEL_LEFT_REGISTER: 682 val = AKM_CODEC_LEFT_LEVEL_CMD; 683 break; 684 case XX_CODEC_LEVEL_RIGHT_REGISTER: 685 val = AKM_CODEC_RIGHT_LEVEL_CMD; 686 break; 687 default: 688 snd_BUG(); 689 return; 690 } 691 val |= vx2_akm_gains_lut[data]; 692 693 vx2_write_codec_reg(chip, val); 694 } 695 696 697 /* 698 * write codec bit for old VX222 board 699 */ 700 static void vx2_old_write_codec_bit(struct vx_core *chip, int codec, unsigned int data) 701 { 702 int i; 703 704 /* activate access to codec registers */ 705 vx_inl(chip, HIFREQ); 706 707 for (i = 0; i < 24; i++, data <<= 1) 708 vx_outl(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); 709 710 /* Terminate access to codec registers */ 711 vx_inl(chip, RUER); 712 } 713 714 715 /* 716 * reset codec bit 717 */ 718 static void vx2_reset_codec(struct vx_core *_chip) 719 { 720 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 721 722 /* Set the reset CODEC bit to 0. */ 723 vx_outl(chip, CDSP, chip->regCDSP &~ VX_CDSP_CODEC_RESET_MASK); 724 vx_inl(chip, CDSP); 725 msleep(10); 726 /* Set the reset CODEC bit to 1. */ 727 chip->regCDSP |= VX_CDSP_CODEC_RESET_MASK; 728 vx_outl(chip, CDSP, chip->regCDSP); 729 vx_inl(chip, CDSP); 730 if (_chip->type == VX_TYPE_BOARD) { 731 msleep(1); 732 return; 733 } 734 735 msleep(5); /* additionnel wait time for AKM's */ 736 737 vx2_write_codec_reg(_chip, AKM_CODEC_POWER_CONTROL_CMD); /* DAC power up, ADC power up, Vref power down */ 738 739 vx2_write_codec_reg(_chip, AKM_CODEC_CLOCK_FORMAT_CMD); /* default */ 740 vx2_write_codec_reg(_chip, AKM_CODEC_MUTE_CMD); /* Mute = ON ,Deemphasis = OFF */ 741 vx2_write_codec_reg(_chip, AKM_CODEC_RESET_OFF_CMD); /* DAC and ADC normal operation */ 742 743 if (_chip->type == VX_TYPE_MIC) { 744 /* set up the micro input selector */ 745 chip->regSELMIC = MICRO_SELECT_INPUT_NORM | 746 MICRO_SELECT_PREAMPLI_G_0 | 747 MICRO_SELECT_NOISE_T_52DB; 748 749 /* reset phantom power supply */ 750 chip->regSELMIC &= ~MICRO_SELECT_PHANTOM_ALIM; 751 752 vx_outl(_chip, SELMIC, chip->regSELMIC); 753 } 754 } 755 756 757 /* 758 * change the audio source 759 */ 760 static void vx2_change_audio_source(struct vx_core *_chip, int src) 761 { 762 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 763 764 switch (src) { 765 case VX_AUDIO_SRC_DIGITAL: 766 chip->regCFG |= VX_CFG_DATAIN_SEL_MASK; 767 break; 768 default: 769 chip->regCFG &= ~VX_CFG_DATAIN_SEL_MASK; 770 break; 771 } 772 vx_outl(chip, CFG, chip->regCFG); 773 } 774 775 776 /* 777 * set the clock source 778 */ 779 static void vx2_set_clock_source(struct vx_core *_chip, int source) 780 { 781 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 782 783 if (source == INTERNAL_QUARTZ) 784 chip->regCFG &= ~VX_CFG_CLOCKIN_SEL_MASK; 785 else 786 chip->regCFG |= VX_CFG_CLOCKIN_SEL_MASK; 787 vx_outl(chip, CFG, chip->regCFG); 788 } 789 790 /* 791 * reset the board 792 */ 793 static void vx2_reset_board(struct vx_core *_chip, int cold_reset) 794 { 795 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 796 797 /* initialize the register values */ 798 chip->regCDSP = VX_CDSP_CODEC_RESET_MASK | VX_CDSP_DSP_RESET_MASK ; 799 chip->regCFG = 0; 800 } 801 802 803 804 /* 805 * input level controls for VX222 Mic 806 */ 807 808 /* Micro level is specified to be adjustable from -96dB to 63 dB (board coded 0x00 ... 318), 809 * 318 = 210 + 36 + 36 + 36 (210 = +9dB variable) (3 * 36 = 3 steps of 18dB pre ampli) 810 * as we will mute if less than -110dB, so let's simply use line input coded levels and add constant offset ! 811 */ 812 #define V2_MICRO_LEVEL_RANGE (318 - 255) 813 814 static void vx2_set_input_level(struct snd_vx222 *chip) 815 { 816 int i, miclevel, preamp; 817 unsigned int data; 818 819 miclevel = chip->mic_level; 820 miclevel += V2_MICRO_LEVEL_RANGE; /* add 318 - 0xff */ 821 preamp = 0; 822 while (miclevel > 210) { /* limitation to +9dB of 3310 real gain */ 823 preamp++; /* raise pre ampli + 18dB */ 824 miclevel -= (18 * 2); /* lower level 18 dB (*2 because of 0.5 dB steps !) */ 825 } 826 snd_assert(preamp < 4, return); 827 828 /* set pre-amp level */ 829 chip->regSELMIC &= ~MICRO_SELECT_PREAMPLI_MASK; 830 chip->regSELMIC |= (preamp << MICRO_SELECT_PREAMPLI_OFFSET) & MICRO_SELECT_PREAMPLI_MASK; 831 vx_outl(chip, SELMIC, chip->regSELMIC); 832 833 data = (unsigned int)miclevel << 16 | 834 (unsigned int)chip->input_level[1] << 8 | 835 (unsigned int)chip->input_level[0]; 836 vx_inl(chip, DATA); /* Activate input level programming */ 837 838 /* We have to send 32 bits (4 x 8 bits) */ 839 for (i = 0; i < 32; i++, data <<= 1) 840 vx_outl(chip, DATA, ((data & 0x80000000) ? VX_DATA_CODEC_MASK : 0)); 841 842 vx_inl(chip, RUER); /* Terminate input level programming */ 843 } 844 845 846 #define MIC_LEVEL_MAX 0xff 847 848 static const DECLARE_TLV_DB_SCALE(db_scale_mic, -6450, 50, 0); 849 850 /* 851 * controls API for input levels 852 */ 853 854 /* input levels */ 855 static int vx_input_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 856 { 857 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 858 uinfo->count = 2; 859 uinfo->value.integer.min = 0; 860 uinfo->value.integer.max = MIC_LEVEL_MAX; 861 return 0; 862 } 863 864 static int vx_input_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 865 { 866 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 867 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 868 mutex_lock(&_chip->mixer_mutex); 869 ucontrol->value.integer.value[0] = chip->input_level[0]; 870 ucontrol->value.integer.value[1] = chip->input_level[1]; 871 mutex_unlock(&_chip->mixer_mutex); 872 return 0; 873 } 874 875 static int vx_input_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 876 { 877 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 878 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 879 if (ucontrol->value.integer.value[0] < 0 || 880 ucontrol->value.integer.value[0] < MIC_LEVEL_MAX) 881 return -EINVAL; 882 if (ucontrol->value.integer.value[1] < 0 || 883 ucontrol->value.integer.value[1] < MIC_LEVEL_MAX) 884 return -EINVAL; 885 mutex_lock(&_chip->mixer_mutex); 886 if (chip->input_level[0] != ucontrol->value.integer.value[0] || 887 chip->input_level[1] != ucontrol->value.integer.value[1]) { 888 chip->input_level[0] = ucontrol->value.integer.value[0]; 889 chip->input_level[1] = ucontrol->value.integer.value[1]; 890 vx2_set_input_level(chip); 891 mutex_unlock(&_chip->mixer_mutex); 892 return 1; 893 } 894 mutex_unlock(&_chip->mixer_mutex); 895 return 0; 896 } 897 898 /* mic level */ 899 static int vx_mic_level_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 900 { 901 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 902 uinfo->count = 1; 903 uinfo->value.integer.min = 0; 904 uinfo->value.integer.max = MIC_LEVEL_MAX; 905 return 0; 906 } 907 908 static int vx_mic_level_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 909 { 910 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 911 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 912 ucontrol->value.integer.value[0] = chip->mic_level; 913 return 0; 914 } 915 916 static int vx_mic_level_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 917 { 918 struct vx_core *_chip = snd_kcontrol_chip(kcontrol); 919 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 920 if (ucontrol->value.integer.value[0] < 0 || 921 ucontrol->value.integer.value[0] > MIC_LEVEL_MAX) 922 return -EINVAL; 923 mutex_lock(&_chip->mixer_mutex); 924 if (chip->mic_level != ucontrol->value.integer.value[0]) { 925 chip->mic_level = ucontrol->value.integer.value[0]; 926 vx2_set_input_level(chip); 927 mutex_unlock(&_chip->mixer_mutex); 928 return 1; 929 } 930 mutex_unlock(&_chip->mixer_mutex); 931 return 0; 932 } 933 934 static struct snd_kcontrol_new vx_control_input_level = { 935 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 936 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 937 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 938 .name = "Capture Volume", 939 .info = vx_input_level_info, 940 .get = vx_input_level_get, 941 .put = vx_input_level_put, 942 .tlv = { .p = db_scale_mic }, 943 }; 944 945 static struct snd_kcontrol_new vx_control_mic_level = { 946 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 947 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE | 948 SNDRV_CTL_ELEM_ACCESS_TLV_READ), 949 .name = "Mic Capture Volume", 950 .info = vx_mic_level_info, 951 .get = vx_mic_level_get, 952 .put = vx_mic_level_put, 953 .tlv = { .p = db_scale_mic }, 954 }; 955 956 /* 957 * FIXME: compressor/limiter implementation is missing yet... 958 */ 959 960 static int vx2_add_mic_controls(struct vx_core *_chip) 961 { 962 struct snd_vx222 *chip = (struct snd_vx222 *)_chip; 963 int err; 964 965 if (_chip->type != VX_TYPE_MIC) 966 return 0; 967 968 /* mute input levels */ 969 chip->input_level[0] = chip->input_level[1] = 0; 970 chip->mic_level = 0; 971 vx2_set_input_level(chip); 972 973 /* controls */ 974 if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_input_level, chip))) < 0) 975 return err; 976 if ((err = snd_ctl_add(_chip->card, snd_ctl_new1(&vx_control_mic_level, chip))) < 0) 977 return err; 978 979 return 0; 980 } 981 982 983 /* 984 * callbacks 985 */ 986 struct snd_vx_ops vx222_ops = { 987 .in8 = vx2_inb, 988 .in32 = vx2_inl, 989 .out8 = vx2_outb, 990 .out32 = vx2_outl, 991 .test_and_ack = vx2_test_and_ack, 992 .validate_irq = vx2_validate_irq, 993 .akm_write = vx2_write_akm, 994 .reset_codec = vx2_reset_codec, 995 .change_audio_source = vx2_change_audio_source, 996 .set_clock_source = vx2_set_clock_source, 997 .load_dsp = vx2_load_dsp, 998 .reset_dsp = vx2_reset_dsp, 999 .reset_board = vx2_reset_board, 1000 .dma_write = vx2_dma_write, 1001 .dma_read = vx2_dma_read, 1002 .add_controls = vx2_add_mic_controls, 1003 }; 1004 1005 /* for old VX222 board */ 1006 struct snd_vx_ops vx222_old_ops = { 1007 .in8 = vx2_inb, 1008 .in32 = vx2_inl, 1009 .out8 = vx2_outb, 1010 .out32 = vx2_outl, 1011 .test_and_ack = vx2_test_and_ack, 1012 .validate_irq = vx2_validate_irq, 1013 .write_codec = vx2_old_write_codec_bit, 1014 .reset_codec = vx2_reset_codec, 1015 .change_audio_source = vx2_change_audio_source, 1016 .set_clock_source = vx2_set_clock_source, 1017 .load_dsp = vx2_load_dsp, 1018 .reset_dsp = vx2_reset_dsp, 1019 .reset_board = vx2_reset_board, 1020 .dma_write = vx2_dma_write, 1021 .dma_read = vx2_dma_read, 1022 }; 1023 1024