1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 42 /* ************* Register Documentation ******************************************************* 43 * 44 * Work in progress! Documentation is based on the code in this file. 45 * 46 * --------- HDSPM_controlRegister --------- 47 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 48 * :||||.||||:||||.||||:||||.||||:||||.||||: 49 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 50 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 51 * :||||.||||:||||.||||:||||.||||:||||.||||: 52 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 53 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits 54 * : . : . : . : . x: HDSPM_Start / enables audio IO 55 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave 56 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency 57 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512, 58 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192 59 * :x . : . : . x:xx . : HDSPM_FrequencyMask 60 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=?? 61 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed 62 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed 63 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask : 64 * : . : . x: . : . : HDSPM_SyncRef0 65 * : . : . x : . : . : HDSPM_SyncRef1 66 * : . : . : x . : . : <AES32> HDSPM_SyncRef2 67 * : . x : . : . : . : <AES32> HDSPM_SyncRef3 68 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn 69 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn? 70 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT 71 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax 72 * : . : . :x . : . : <MADI> HDSPM_InputSelect1 73 * : . : .x : . : . : <MADI> HDSPM_clr_tms 74 * : . : . : . x : . : <MADI> HDSPM_TX_64ch 75 * : . : . : . x : . : <AES32> HDSPM_Emphasis 76 * : . : . : .x : . : <MADI> HDSPM_AutoInp 77 * : . : . x : . : . : <MADI> HDSPM_SMUX 78 * : . : .x : . : . : <MADI> HDSPM_clr_tms 79 * : . : x. : . : . : <MADI> HDSPM_taxi_reset 80 * : . x: . : . : . : <MADI> HDSPM_LineOut 81 * : . x: . : . : . : <AES32> ?????????????????? 82 * : . : x. : . : . : <AES32> HDSPM_WCK48 83 * : . : . : .x : . : <AES32> HDSPM_Dolby 84 * : . : x . : . : . : HDSPM_Midi0InterruptEnable 85 * : . :x . : . : . : HDSPM_Midi1InterruptEnable 86 * : . : x . : . : . : HDSPM_Midi2InterruptEnable 87 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable 88 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire 89 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire 90 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire 91 * : . : . : . x : . : <AES32> HDSPM_Professional 92 * : x . : . : . : . : HDSPM_wclk_sel 93 * : . : . : . : . : 94 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 95 * :||||.||||:||||.||||:||||.||||:||||.||||: 96 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 97 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 98 * :||||.||||:||||.||||:||||.||||:||||.||||: 99 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit 100 * 101 * 102 * 103 * AIO / RayDAT only 104 * 105 * ------------ HDSPM_WR_SETTINGS ---------- 106 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 107 * :1098.7654:3210.9876:5432.1098:7654.3210: 108 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 109 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 110 * :||||.||||:||||.||||:||||.||||:||||.||||: 111 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 112 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave 113 * : . : . : . : . x : HDSPM_c0_SyncRef0 114 * : . : . : . : . x : HDSPM_c0_SyncRef1 115 * : . : . : . : .x : HDSPM_c0_SyncRef2 116 * : . : . : . : x. : HDSPM_c0_SyncRef3 117 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask: 118 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4, 119 * : . : . : . : . : 9:TCO, 10:SyncIn 120 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT, 121 * : . : . : . : . : 9:TCO, 10:SyncIn 122 * : . : . : . : . : 123 * : . : . : . : . : 124 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 125 * :1098.7654:3210.9876:5432.1098:7654.3210: 126 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 127 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 128 * :||||.||||:||||.||||:||||.||||:||||.||||: 129 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 130 * 131 */ 132 #include <linux/init.h> 133 #include <linux/delay.h> 134 #include <linux/interrupt.h> 135 #include <linux/module.h> 136 #include <linux/slab.h> 137 #include <linux/pci.h> 138 #include <linux/math64.h> 139 #include <linux/io.h> 140 141 #include <sound/core.h> 142 #include <sound/control.h> 143 #include <sound/pcm.h> 144 #include <sound/pcm_params.h> 145 #include <sound/info.h> 146 #include <sound/asoundef.h> 147 #include <sound/rawmidi.h> 148 #include <sound/hwdep.h> 149 #include <sound/initval.h> 150 151 #include <sound/hdspm.h> 152 153 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 154 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 155 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 156 157 module_param_array(index, int, NULL, 0444); 158 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 159 160 module_param_array(id, charp, NULL, 0444); 161 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 162 163 module_param_array(enable, bool, NULL, 0444); 164 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 165 166 167 MODULE_AUTHOR 168 ( 169 "Winfried Ritsch <ritsch_AT_iem.at>, " 170 "Paul Davis <paul@linuxaudiosystems.com>, " 171 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 172 "Remy Bruno <remy.bruno@trinnov.com>, " 173 "Florian Faber <faberman@linuxproaudio.org>, " 174 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 175 ); 176 MODULE_DESCRIPTION("RME HDSPM"); 177 MODULE_LICENSE("GPL"); 178 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 179 180 /* --- Write registers. --- 181 These are defined as byte-offsets from the iobase value. */ 182 183 #define HDSPM_WR_SETTINGS 0 184 #define HDSPM_outputBufferAddress 32 185 #define HDSPM_inputBufferAddress 36 186 #define HDSPM_controlRegister 64 187 #define HDSPM_interruptConfirmation 96 188 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 189 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */ 190 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 191 #define HDSPM_midiDataOut1 356 192 #define HDSPM_eeprom_wr 384 /* for AES32 */ 193 194 /* DMA enable for 64 channels, only Bit 0 is relevant */ 195 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 196 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 197 198 /* 16 page addresses for each of the 64 channels DMA buffer in and out 199 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 200 #define HDSPM_pageAddressBufferOut 8192 201 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 202 203 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 204 205 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 206 207 /* --- Read registers. --- 208 These are defined as byte-offsets from the iobase value */ 209 #define HDSPM_statusRegister 0 210 /*#define HDSPM_statusRegister2 96 */ 211 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 212 * offset 192, for AES32 *and* MADI 213 * => need to check that offset 192 is working on MADI */ 214 #define HDSPM_statusRegister2 192 215 #define HDSPM_timecodeRegister 128 216 217 /* AIO, RayDAT */ 218 #define HDSPM_RD_STATUS_0 0 219 #define HDSPM_RD_STATUS_1 64 220 #define HDSPM_RD_STATUS_2 128 221 #define HDSPM_RD_STATUS_3 192 222 223 #define HDSPM_RD_TCO 256 224 #define HDSPM_RD_PLL_FREQ 512 225 #define HDSPM_WR_TCO 128 226 227 #define HDSPM_TCO1_TCO_lock 0x00000001 228 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 229 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 230 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 231 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 232 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 233 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 234 235 #define HDSPM_TCO1_set_TC 0x00000100 236 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 237 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 238 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 239 240 #define HDSPM_TCO2_TC_run 0x00010000 241 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 242 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 243 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 244 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 245 #define HDSPM_TCO2_set_jam_sync 0x00200000 246 #define HDSPM_TCO2_set_flywheel 0x00400000 247 248 #define HDSPM_TCO2_set_01_4 0x01000000 249 #define HDSPM_TCO2_set_pull_down 0x02000000 250 #define HDSPM_TCO2_set_pull_up 0x04000000 251 #define HDSPM_TCO2_set_freq 0x08000000 252 #define HDSPM_TCO2_set_term_75R 0x10000000 253 #define HDSPM_TCO2_set_input_LSB 0x20000000 254 #define HDSPM_TCO2_set_input_MSB 0x40000000 255 #define HDSPM_TCO2_set_freq_from_app 0x80000000 256 257 258 #define HDSPM_midiDataOut0 352 259 #define HDSPM_midiDataOut1 356 260 #define HDSPM_midiDataOut2 368 261 262 #define HDSPM_midiDataIn0 360 263 #define HDSPM_midiDataIn1 364 264 #define HDSPM_midiDataIn2 372 265 #define HDSPM_midiDataIn3 376 266 267 /* status is data bytes in MIDI-FIFO (0-128) */ 268 #define HDSPM_midiStatusOut0 384 269 #define HDSPM_midiStatusOut1 388 270 #define HDSPM_midiStatusOut2 400 271 272 #define HDSPM_midiStatusIn0 392 273 #define HDSPM_midiStatusIn1 396 274 #define HDSPM_midiStatusIn2 404 275 #define HDSPM_midiStatusIn3 408 276 277 278 /* the meters are regular i/o-mapped registers, but offset 279 considerably from the rest. the peak registers are reset 280 when read; the least-significant 4 bits are full-scale counters; 281 the actual peak value is in the most-significant 24 bits. 282 */ 283 284 #define HDSPM_MADI_INPUT_PEAK 4096 285 #define HDSPM_MADI_PLAYBACK_PEAK 4352 286 #define HDSPM_MADI_OUTPUT_PEAK 4608 287 288 #define HDSPM_MADI_INPUT_RMS_L 6144 289 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 290 #define HDSPM_MADI_OUTPUT_RMS_L 6656 291 292 #define HDSPM_MADI_INPUT_RMS_H 7168 293 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 294 #define HDSPM_MADI_OUTPUT_RMS_H 7680 295 296 /* --- Control Register bits --------- */ 297 #define HDSPM_Start (1<<0) /* start engine */ 298 299 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 300 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 301 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 302 303 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 304 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 305 register [RayDAT, AIO] */ 306 307 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 308 309 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 310 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 311 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 312 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 313 314 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 315 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 316 56channelMODE=0 */ /* MADI ONLY*/ 317 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 318 319 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 320 0=off, 1=on */ /* MADI ONLY */ 321 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 322 323 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 324 * -- MADI ONLY 325 */ 326 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 327 328 #define HDSPM_SyncRef2 (1<<13) 329 #define HDSPM_SyncRef3 (1<<25) 330 331 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 332 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 333 AES additional bits in 334 lower 5 Audiodatabits ??? */ 335 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 336 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 337 338 #define HDSPM_Midi0InterruptEnable 0x0400000 339 #define HDSPM_Midi1InterruptEnable 0x0800000 340 #define HDSPM_Midi2InterruptEnable 0x0200000 341 #define HDSPM_Midi3InterruptEnable 0x4000000 342 343 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 344 #define HDSPe_FLOAT_FORMAT 0x2000000 345 346 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 347 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 348 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 349 350 #define HDSPM_wclk_sel (1<<30) 351 352 /* additional control register bits for AIO*/ 353 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 354 #define HDSPM_c0_Input0 0x1000 355 #define HDSPM_c0_Input1 0x2000 356 #define HDSPM_c0_Spdif_Opt 0x4000 357 #define HDSPM_c0_Pro 0x8000 358 #define HDSPM_c0_clr_tms 0x10000 359 #define HDSPM_c0_AEB1 0x20000 360 #define HDSPM_c0_AEB2 0x40000 361 #define HDSPM_c0_LineOut 0x80000 362 #define HDSPM_c0_AD_GAIN0 0x100000 363 #define HDSPM_c0_AD_GAIN1 0x200000 364 #define HDSPM_c0_DA_GAIN0 0x400000 365 #define HDSPM_c0_DA_GAIN1 0x800000 366 #define HDSPM_c0_PH_GAIN0 0x1000000 367 #define HDSPM_c0_PH_GAIN1 0x2000000 368 #define HDSPM_c0_Sym6db 0x4000000 369 370 371 /* --- bit helper defines */ 372 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 373 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 374 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 375 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 376 #define HDSPM_InputOptical 0 377 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 378 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 379 HDSPM_SyncRef2|HDSPM_SyncRef3) 380 381 #define HDSPM_c0_SyncRef0 0x2 382 #define HDSPM_c0_SyncRef1 0x4 383 #define HDSPM_c0_SyncRef2 0x8 384 #define HDSPM_c0_SyncRef3 0x10 385 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 386 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 387 388 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 389 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 390 #define HDSPM_SYNC_FROM_TCO 2 391 #define HDSPM_SYNC_FROM_SYNC_IN 3 392 393 #define HDSPM_Frequency32KHz HDSPM_Frequency0 394 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 395 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 396 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 397 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 398 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 399 HDSPM_Frequency0) 400 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 401 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 402 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 403 HDSPM_Frequency0) 404 405 406 /* Synccheck Status */ 407 #define HDSPM_SYNC_CHECK_NO_LOCK 0 408 #define HDSPM_SYNC_CHECK_LOCK 1 409 #define HDSPM_SYNC_CHECK_SYNC 2 410 411 /* AutoSync References - used by "autosync_ref" control switch */ 412 #define HDSPM_AUTOSYNC_FROM_WORD 0 413 #define HDSPM_AUTOSYNC_FROM_MADI 1 414 #define HDSPM_AUTOSYNC_FROM_TCO 2 415 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 416 #define HDSPM_AUTOSYNC_FROM_NONE 4 417 418 /* Possible sources of MADI input */ 419 #define HDSPM_OPTICAL 0 /* optical */ 420 #define HDSPM_COAXIAL 1 /* BNC */ 421 422 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 423 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 424 425 #define hdspm_encode_in(x) (((x)&0x3)<<14) 426 #define hdspm_decode_in(x) (((x)>>14)&0x3) 427 428 /* --- control2 register bits --- */ 429 #define HDSPM_TMS (1<<0) 430 #define HDSPM_TCK (1<<1) 431 #define HDSPM_TDI (1<<2) 432 #define HDSPM_JTAG (1<<3) 433 #define HDSPM_PWDN (1<<4) 434 #define HDSPM_PROGRAM (1<<5) 435 #define HDSPM_CONFIG_MODE_0 (1<<6) 436 #define HDSPM_CONFIG_MODE_1 (1<<7) 437 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 438 #define HDSPM_BIGENDIAN_MODE (1<<9) 439 #define HDSPM_RD_MULTIPLE (1<<10) 440 441 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 442 that do not conflict with specific bits for AES32 seem to be valid also 443 for the AES32 444 */ 445 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 446 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 447 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 448 * (like inp0) 449 */ 450 451 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 452 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 453 454 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/ 455 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/ 456 457 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */ 458 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */ 459 460 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 461 /* since 64byte accurate, last 6 bits are not used */ 462 463 464 465 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 466 467 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 468 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 469 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 470 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 471 472 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 473 * Interrupt 474 */ 475 #define HDSPM_tco_detect 0x08000000 476 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */ 477 478 #define HDSPM_s2_tco_detect 0x00000040 479 #define HDSPM_s2_AEBO_D 0x00000080 480 #define HDSPM_s2_AEBI_D 0x00000100 481 482 483 #define HDSPM_midi0IRQPending 0x40000000 484 #define HDSPM_midi1IRQPending 0x80000000 485 #define HDSPM_midi2IRQPending 0x20000000 486 #define HDSPM_midi2IRQPendingAES 0x00000020 487 #define HDSPM_midi3IRQPending 0x00200000 488 489 /* --- status bit helpers */ 490 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 491 HDSPM_madiFreq2|HDSPM_madiFreq3) 492 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 493 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 494 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 495 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 496 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 497 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 498 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 499 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 500 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 501 502 /* Status2 Register bits */ /* MADI ONLY */ 503 504 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 505 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 506 #define HDSPM_version2 (1<<2) 507 508 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 509 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 510 511 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 512 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 513 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 514 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 515 516 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 517 #define HDSPM_SyncRef1 0x20000 518 519 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 520 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 521 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 522 523 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 524 525 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 526 HDSPM_wc_freq3) 527 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 528 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 529 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 530 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 531 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 532 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 533 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 534 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 535 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 536 537 #define HDSPM_status1_F_0 0x0400000 538 #define HDSPM_status1_F_1 0x0800000 539 #define HDSPM_status1_F_2 0x1000000 540 #define HDSPM_status1_F_3 0x2000000 541 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 542 543 544 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 545 HDSPM_SelSyncRef2) 546 #define HDSPM_SelSyncRef_WORD 0 547 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 548 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 549 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 550 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 551 HDSPM_SelSyncRef2) 552 553 /* 554 For AES32, bits for status, status2 and timecode are different 555 */ 556 /* status */ 557 #define HDSPM_AES32_wcLock 0x0200000 558 #define HDSPM_AES32_wcSync 0x0100000 559 #define HDSPM_AES32_wcFreq_bit 22 560 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 561 HDSPM_bit2freq */ 562 #define HDSPM_AES32_syncref_bit 16 563 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 564 565 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 566 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 567 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 568 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 569 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 570 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 571 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 572 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 573 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 574 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9 575 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10 576 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11 577 578 /* status2 */ 579 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 580 #define HDSPM_LockAES 0x80 581 #define HDSPM_LockAES1 0x80 582 #define HDSPM_LockAES2 0x40 583 #define HDSPM_LockAES3 0x20 584 #define HDSPM_LockAES4 0x10 585 #define HDSPM_LockAES5 0x8 586 #define HDSPM_LockAES6 0x4 587 #define HDSPM_LockAES7 0x2 588 #define HDSPM_LockAES8 0x1 589 /* 590 Timecode 591 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 592 AES i+1 593 bits 3210 594 0001 32kHz 595 0010 44.1kHz 596 0011 48kHz 597 0100 64kHz 598 0101 88.2kHz 599 0110 96kHz 600 0111 128kHz 601 1000 176.4kHz 602 1001 192kHz 603 NB: Timecode register doesn't seem to work on AES32 card revision 230 604 */ 605 606 /* Mixer Values */ 607 #define UNITY_GAIN 32768 /* = 65536/2 */ 608 #define MINUS_INFINITY_GAIN 0 609 610 /* Number of channels for different Speed Modes */ 611 #define MADI_SS_CHANNELS 64 612 #define MADI_DS_CHANNELS 32 613 #define MADI_QS_CHANNELS 16 614 615 #define RAYDAT_SS_CHANNELS 36 616 #define RAYDAT_DS_CHANNELS 20 617 #define RAYDAT_QS_CHANNELS 12 618 619 #define AIO_IN_SS_CHANNELS 14 620 #define AIO_IN_DS_CHANNELS 10 621 #define AIO_IN_QS_CHANNELS 8 622 #define AIO_OUT_SS_CHANNELS 16 623 #define AIO_OUT_DS_CHANNELS 12 624 #define AIO_OUT_QS_CHANNELS 10 625 626 #define AES32_CHANNELS 16 627 628 /* the size of a substream (1 mono data stream) */ 629 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 630 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 631 632 /* the size of the area we need to allocate for DMA transfers. the 633 size is the same regardless of the number of channels, and 634 also the latency to use. 635 for one direction !!! 636 */ 637 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 638 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 639 640 #define HDSPM_RAYDAT_REV 211 641 #define HDSPM_AIO_REV 212 642 #define HDSPM_MADIFACE_REV 213 643 644 /* speed factor modes */ 645 #define HDSPM_SPEED_SINGLE 0 646 #define HDSPM_SPEED_DOUBLE 1 647 #define HDSPM_SPEED_QUAD 2 648 649 /* names for speed modes */ 650 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 651 652 static const char *const texts_autosync_aes_tco[] = { "Word Clock", 653 "AES1", "AES2", "AES3", "AES4", 654 "AES5", "AES6", "AES7", "AES8", 655 "TCO", "Sync In" 656 }; 657 static const char *const texts_autosync_aes[] = { "Word Clock", 658 "AES1", "AES2", "AES3", "AES4", 659 "AES5", "AES6", "AES7", "AES8", 660 "Sync In" 661 }; 662 static const char *const texts_autosync_madi_tco[] = { "Word Clock", 663 "MADI", "TCO", "Sync In" }; 664 static const char *const texts_autosync_madi[] = { "Word Clock", 665 "MADI", "Sync In" }; 666 667 static const char *const texts_autosync_raydat_tco[] = { 668 "Word Clock", 669 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 670 "AES", "SPDIF", "TCO", "Sync In" 671 }; 672 static const char *const texts_autosync_raydat[] = { 673 "Word Clock", 674 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 675 "AES", "SPDIF", "Sync In" 676 }; 677 static const char *const texts_autosync_aio_tco[] = { 678 "Word Clock", 679 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 680 }; 681 static const char *const texts_autosync_aio[] = { "Word Clock", 682 "ADAT", "AES", "SPDIF", "Sync In" }; 683 684 static const char *const texts_freq[] = { 685 "No Lock", 686 "32 kHz", 687 "44.1 kHz", 688 "48 kHz", 689 "64 kHz", 690 "88.2 kHz", 691 "96 kHz", 692 "128 kHz", 693 "176.4 kHz", 694 "192 kHz" 695 }; 696 697 static char *texts_ports_madi[] = { 698 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 699 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 700 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 701 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 702 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 703 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 704 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 705 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 706 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 707 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 708 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 709 }; 710 711 712 static char *texts_ports_raydat_ss[] = { 713 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 714 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 715 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 716 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 717 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 718 "ADAT4.7", "ADAT4.8", 719 "AES.L", "AES.R", 720 "SPDIF.L", "SPDIF.R" 721 }; 722 723 static char *texts_ports_raydat_ds[] = { 724 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 725 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 726 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 727 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 728 "AES.L", "AES.R", 729 "SPDIF.L", "SPDIF.R" 730 }; 731 732 static char *texts_ports_raydat_qs[] = { 733 "ADAT1.1", "ADAT1.2", 734 "ADAT2.1", "ADAT2.2", 735 "ADAT3.1", "ADAT3.2", 736 "ADAT4.1", "ADAT4.2", 737 "AES.L", "AES.R", 738 "SPDIF.L", "SPDIF.R" 739 }; 740 741 742 static char *texts_ports_aio_in_ss[] = { 743 "Analogue.L", "Analogue.R", 744 "AES.L", "AES.R", 745 "SPDIF.L", "SPDIF.R", 746 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 747 "ADAT.7", "ADAT.8", 748 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 749 }; 750 751 static char *texts_ports_aio_out_ss[] = { 752 "Analogue.L", "Analogue.R", 753 "AES.L", "AES.R", 754 "SPDIF.L", "SPDIF.R", 755 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 756 "ADAT.7", "ADAT.8", 757 "Phone.L", "Phone.R", 758 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 759 }; 760 761 static char *texts_ports_aio_in_ds[] = { 762 "Analogue.L", "Analogue.R", 763 "AES.L", "AES.R", 764 "SPDIF.L", "SPDIF.R", 765 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 766 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 767 }; 768 769 static char *texts_ports_aio_out_ds[] = { 770 "Analogue.L", "Analogue.R", 771 "AES.L", "AES.R", 772 "SPDIF.L", "SPDIF.R", 773 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 774 "Phone.L", "Phone.R", 775 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 776 }; 777 778 static char *texts_ports_aio_in_qs[] = { 779 "Analogue.L", "Analogue.R", 780 "AES.L", "AES.R", 781 "SPDIF.L", "SPDIF.R", 782 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 783 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 784 }; 785 786 static char *texts_ports_aio_out_qs[] = { 787 "Analogue.L", "Analogue.R", 788 "AES.L", "AES.R", 789 "SPDIF.L", "SPDIF.R", 790 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 791 "Phone.L", "Phone.R", 792 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 793 }; 794 795 static char *texts_ports_aes32[] = { 796 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 797 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 798 "AES.15", "AES.16" 799 }; 800 801 /* These tables map the ALSA channels 1..N to the channels that we 802 need to use in order to find the relevant channel buffer. RME 803 refers to this kind of mapping as between "the ADAT channel and 804 the DMA channel." We index it using the logical audio channel, 805 and the value is the DMA channel (i.e. channel buffer number) 806 where the data for that channel can be read/written from/to. 807 */ 808 809 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 810 0, 1, 2, 3, 4, 5, 6, 7, 811 8, 9, 10, 11, 12, 13, 14, 15, 812 16, 17, 18, 19, 20, 21, 22, 23, 813 24, 25, 26, 27, 28, 29, 30, 31, 814 32, 33, 34, 35, 36, 37, 38, 39, 815 40, 41, 42, 43, 44, 45, 46, 47, 816 48, 49, 50, 51, 52, 53, 54, 55, 817 56, 57, 58, 59, 60, 61, 62, 63 818 }; 819 820 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 821 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 822 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 823 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 824 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 825 0, 1, /* AES */ 826 2, 3, /* SPDIF */ 827 -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1, 831 }; 832 833 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 834 4, 5, 6, 7, /* ADAT 1 */ 835 8, 9, 10, 11, /* ADAT 2 */ 836 12, 13, 14, 15, /* ADAT 3 */ 837 16, 17, 18, 19, /* ADAT 4 */ 838 0, 1, /* AES */ 839 2, 3, /* SPDIF */ 840 -1, -1, -1, -1, 841 -1, -1, -1, -1, -1, -1, -1, -1, 842 -1, -1, -1, -1, -1, -1, -1, -1, 843 -1, -1, -1, -1, -1, -1, -1, -1, 844 -1, -1, -1, -1, -1, -1, -1, -1, 845 -1, -1, -1, -1, -1, -1, -1, -1, 846 }; 847 848 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 849 4, 5, /* ADAT 1 */ 850 6, 7, /* ADAT 2 */ 851 8, 9, /* ADAT 3 */ 852 10, 11, /* ADAT 4 */ 853 0, 1, /* AES */ 854 2, 3, /* SPDIF */ 855 -1, -1, -1, -1, 856 -1, -1, -1, -1, -1, -1, -1, -1, 857 -1, -1, -1, -1, -1, -1, -1, -1, 858 -1, -1, -1, -1, -1, -1, -1, -1, 859 -1, -1, -1, -1, -1, -1, -1, -1, 860 -1, -1, -1, -1, -1, -1, -1, -1, 861 -1, -1, -1, -1, -1, -1, -1, -1, 862 }; 863 864 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 865 0, 1, /* line in */ 866 8, 9, /* aes in, */ 867 10, 11, /* spdif in */ 868 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 869 2, 3, 4, 5, /* AEB */ 870 -1, -1, -1, -1, -1, -1, 871 -1, -1, -1, -1, -1, -1, -1, -1, 872 -1, -1, -1, -1, -1, -1, -1, -1, 873 -1, -1, -1, -1, -1, -1, -1, -1, 874 -1, -1, -1, -1, -1, -1, -1, -1, 875 -1, -1, -1, -1, -1, -1, -1, -1, 876 }; 877 878 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 879 0, 1, /* line out */ 880 8, 9, /* aes out */ 881 10, 11, /* spdif out */ 882 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 883 6, 7, /* phone out */ 884 2, 3, 4, 5, /* AEB */ 885 -1, -1, -1, -1, 886 -1, -1, -1, -1, -1, -1, -1, -1, 887 -1, -1, -1, -1, -1, -1, -1, -1, 888 -1, -1, -1, -1, -1, -1, -1, -1, 889 -1, -1, -1, -1, -1, -1, -1, -1, 890 -1, -1, -1, -1, -1, -1, -1, -1, 891 }; 892 893 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 894 0, 1, /* line in */ 895 8, 9, /* aes in */ 896 10, 11, /* spdif in */ 897 12, 14, 16, 18, /* adat in */ 898 2, 3, 4, 5, /* AEB */ 899 -1, -1, 900 -1, -1, -1, -1, -1, -1, -1, -1, 901 -1, -1, -1, -1, -1, -1, -1, -1, 902 -1, -1, -1, -1, -1, -1, -1, -1, 903 -1, -1, -1, -1, -1, -1, -1, -1, 904 -1, -1, -1, -1, -1, -1, -1, -1, 905 -1, -1, -1, -1, -1, -1, -1, -1 906 }; 907 908 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 909 0, 1, /* line out */ 910 8, 9, /* aes out */ 911 10, 11, /* spdif out */ 912 12, 14, 16, 18, /* adat out */ 913 6, 7, /* phone out */ 914 2, 3, 4, 5, /* AEB */ 915 -1, -1, -1, -1, -1, -1, -1, -1, 916 -1, -1, -1, -1, -1, -1, -1, -1, 917 -1, -1, -1, -1, -1, -1, -1, -1, 918 -1, -1, -1, -1, -1, -1, -1, -1, 919 -1, -1, -1, -1, -1, -1, -1, -1, 920 -1, -1, -1, -1, -1, -1, -1, -1 921 }; 922 923 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 924 0, 1, /* line in */ 925 8, 9, /* aes in */ 926 10, 11, /* spdif in */ 927 12, 16, /* adat in */ 928 2, 3, 4, 5, /* AEB */ 929 -1, -1, -1, -1, 930 -1, -1, -1, -1, -1, -1, -1, -1, 931 -1, -1, -1, -1, -1, -1, -1, -1, 932 -1, -1, -1, -1, -1, -1, -1, -1, 933 -1, -1, -1, -1, -1, -1, -1, -1, 934 -1, -1, -1, -1, -1, -1, -1, -1, 935 -1, -1, -1, -1, -1, -1, -1, -1 936 }; 937 938 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 939 0, 1, /* line out */ 940 8, 9, /* aes out */ 941 10, 11, /* spdif out */ 942 12, 16, /* adat out */ 943 6, 7, /* phone out */ 944 2, 3, 4, 5, /* AEB */ 945 -1, -1, 946 -1, -1, -1, -1, -1, -1, -1, -1, 947 -1, -1, -1, -1, -1, -1, -1, -1, 948 -1, -1, -1, -1, -1, -1, -1, -1, 949 -1, -1, -1, -1, -1, -1, -1, -1, 950 -1, -1, -1, -1, -1, -1, -1, -1, 951 -1, -1, -1, -1, -1, -1, -1, -1 952 }; 953 954 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 955 0, 1, 2, 3, 4, 5, 6, 7, 956 8, 9, 10, 11, 12, 13, 14, 15, 957 -1, -1, -1, -1, -1, -1, -1, -1, 958 -1, -1, -1, -1, -1, -1, -1, -1, 959 -1, -1, -1, -1, -1, -1, -1, -1, 960 -1, -1, -1, -1, -1, -1, -1, -1, 961 -1, -1, -1, -1, -1, -1, -1, -1, 962 -1, -1, -1, -1, -1, -1, -1, -1 963 }; 964 965 struct hdspm_midi { 966 struct hdspm *hdspm; 967 int id; 968 struct snd_rawmidi *rmidi; 969 struct snd_rawmidi_substream *input; 970 struct snd_rawmidi_substream *output; 971 char istimer; /* timer in use */ 972 struct timer_list timer; 973 spinlock_t lock; 974 int pending; 975 int dataIn; 976 int statusIn; 977 int dataOut; 978 int statusOut; 979 int ie; 980 int irq; 981 }; 982 983 struct hdspm_tco { 984 int input; /* 0: LTC, 1:Video, 2: WC*/ 985 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */ 986 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */ 987 int samplerate; /* 0=44.1, 1=48, 2= freq from app */ 988 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/ 989 int term; /* 0 = off, 1 = on */ 990 }; 991 992 struct hdspm { 993 spinlock_t lock; 994 /* only one playback and/or capture stream */ 995 struct snd_pcm_substream *capture_substream; 996 struct snd_pcm_substream *playback_substream; 997 998 char *card_name; /* for procinfo */ 999 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 1000 1001 uint8_t io_type; 1002 1003 int monitor_outs; /* set up monitoring outs init flag */ 1004 1005 u32 control_register; /* cached value */ 1006 u32 control2_register; /* cached value */ 1007 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */ 1008 1009 struct hdspm_midi midi[4]; 1010 struct tasklet_struct midi_tasklet; 1011 1012 size_t period_bytes; 1013 unsigned char ss_in_channels; 1014 unsigned char ds_in_channels; 1015 unsigned char qs_in_channels; 1016 unsigned char ss_out_channels; 1017 unsigned char ds_out_channels; 1018 unsigned char qs_out_channels; 1019 1020 unsigned char max_channels_in; 1021 unsigned char max_channels_out; 1022 1023 signed char *channel_map_in; 1024 signed char *channel_map_out; 1025 1026 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 1027 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 1028 1029 char **port_names_in; 1030 char **port_names_out; 1031 1032 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 1033 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 1034 1035 unsigned char *playback_buffer; /* suitably aligned address */ 1036 unsigned char *capture_buffer; /* suitably aligned address */ 1037 1038 pid_t capture_pid; /* process id which uses capture */ 1039 pid_t playback_pid; /* process id which uses capture */ 1040 int running; /* running status */ 1041 1042 int last_external_sample_rate; /* samplerate mystic ... */ 1043 int last_internal_sample_rate; 1044 int system_sample_rate; 1045 1046 int dev; /* Hardware vars... */ 1047 int irq; 1048 unsigned long port; 1049 void __iomem *iobase; 1050 1051 int irq_count; /* for debug */ 1052 int midiPorts; 1053 1054 struct snd_card *card; /* one card */ 1055 struct snd_pcm *pcm; /* has one pcm */ 1056 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 1057 struct pci_dev *pci; /* and an pci info */ 1058 1059 /* Mixer vars */ 1060 /* fast alsa mixer */ 1061 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 1062 /* but input to much, so not used */ 1063 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 1064 /* full mixer accessible over mixer ioctl or hwdep-device */ 1065 struct hdspm_mixer *mixer; 1066 1067 struct hdspm_tco *tco; /* NULL if no TCO detected */ 1068 1069 const char *const *texts_autosync; 1070 int texts_autosync_items; 1071 1072 cycles_t last_interrupt; 1073 1074 unsigned int serial; 1075 1076 struct hdspm_peak_rms peak_rms; 1077 }; 1078 1079 1080 static const struct pci_device_id snd_hdspm_ids[] = { 1081 { 1082 .vendor = PCI_VENDOR_ID_XILINX, 1083 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 1084 .subvendor = PCI_ANY_ID, 1085 .subdevice = PCI_ANY_ID, 1086 .class = 0, 1087 .class_mask = 0, 1088 .driver_data = 0}, 1089 {0,} 1090 }; 1091 1092 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 1093 1094 /* prototypes */ 1095 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 1096 struct hdspm *hdspm); 1097 static int snd_hdspm_create_pcm(struct snd_card *card, 1098 struct hdspm *hdspm); 1099 1100 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 1101 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 1102 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 1103 static int hdspm_autosync_ref(struct hdspm *hdspm); 1104 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out); 1105 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 1106 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1107 static void hdspm_set_sgbuf(struct hdspm *hdspm, 1108 struct snd_pcm_substream *substream, 1109 unsigned int reg, int channels); 1110 1111 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx); 1112 static int hdspm_wc_sync_check(struct hdspm *hdspm); 1113 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1114 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1115 1116 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index); 1117 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm); 1118 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm); 1119 1120 1121 1122 static inline int HDSPM_bit2freq(int n) 1123 { 1124 static const int bit2freq_tab[] = { 1125 0, 32000, 44100, 48000, 64000, 88200, 1126 96000, 128000, 176400, 192000 }; 1127 if (n < 1 || n > 9) 1128 return 0; 1129 return bit2freq_tab[n]; 1130 } 1131 1132 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1133 { 1134 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1135 } 1136 1137 1138 /* Write/read to/from HDSPM with Adresses in Bytes 1139 not words but only 32Bit writes are allowed */ 1140 1141 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1142 unsigned int val) 1143 { 1144 writel(val, hdspm->iobase + reg); 1145 } 1146 1147 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1148 { 1149 return readl(hdspm->iobase + reg); 1150 } 1151 1152 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1153 mixer is write only on hardware so we have to cache him for read 1154 each fader is a u32, but uses only the first 16 bit */ 1155 1156 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1157 unsigned int in) 1158 { 1159 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1160 return 0; 1161 1162 return hdspm->mixer->ch[chan].in[in]; 1163 } 1164 1165 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1166 unsigned int pb) 1167 { 1168 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1169 return 0; 1170 return hdspm->mixer->ch[chan].pb[pb]; 1171 } 1172 1173 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1174 unsigned int in, unsigned short data) 1175 { 1176 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1177 return -1; 1178 1179 hdspm_write(hdspm, 1180 HDSPM_MADI_mixerBase + 1181 ((in + 128 * chan) * sizeof(u32)), 1182 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1183 return 0; 1184 } 1185 1186 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1187 unsigned int pb, unsigned short data) 1188 { 1189 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1190 return -1; 1191 1192 hdspm_write(hdspm, 1193 HDSPM_MADI_mixerBase + 1194 ((64 + pb + 128 * chan) * sizeof(u32)), 1195 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1196 return 0; 1197 } 1198 1199 1200 /* enable DMA for specific channels, now available for DSP-MADI */ 1201 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1202 { 1203 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1204 } 1205 1206 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1207 { 1208 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1209 } 1210 1211 /* check if same process is writing and reading */ 1212 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1213 { 1214 unsigned long flags; 1215 int ret = 1; 1216 1217 spin_lock_irqsave(&hdspm->lock, flags); 1218 if ((hdspm->playback_pid != hdspm->capture_pid) && 1219 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1220 ret = 0; 1221 } 1222 spin_unlock_irqrestore(&hdspm->lock, flags); 1223 return ret; 1224 } 1225 1226 /* round arbitary sample rates to commonly known rates */ 1227 static int hdspm_round_frequency(int rate) 1228 { 1229 if (rate < 38050) 1230 return 32000; 1231 if (rate < 46008) 1232 return 44100; 1233 else 1234 return 48000; 1235 } 1236 1237 /* QS and DS rates normally can not be detected 1238 * automatically by the card. Only exception is MADI 1239 * in 96k frame mode. 1240 * 1241 * So if we read SS values (32 .. 48k), check for 1242 * user-provided DS/QS bits in the control register 1243 * and multiply the base frequency accordingly. 1244 */ 1245 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1246 { 1247 if (rate <= 48000) { 1248 if (hdspm->control_register & HDSPM_QuadSpeed) 1249 return rate * 4; 1250 else if (hdspm->control_register & 1251 HDSPM_DoubleSpeed) 1252 return rate * 2; 1253 } 1254 return rate; 1255 } 1256 1257 /* check for external sample rate, returns the sample rate in Hz*/ 1258 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1259 { 1260 unsigned int status, status2; 1261 int syncref, rate = 0, rate_bits; 1262 1263 switch (hdspm->io_type) { 1264 case AES32: 1265 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1266 status = hdspm_read(hdspm, HDSPM_statusRegister); 1267 1268 syncref = hdspm_autosync_ref(hdspm); 1269 switch (syncref) { 1270 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 1271 /* Check WC sync and get sample rate */ 1272 if (hdspm_wc_sync_check(hdspm)) 1273 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm)); 1274 break; 1275 1276 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 1277 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 1278 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 1279 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 1280 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 1281 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 1282 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 1283 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 1284 /* Check AES sync and get sample rate */ 1285 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)) 1286 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm, 1287 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)); 1288 break; 1289 1290 1291 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 1292 /* Check TCO sync and get sample rate */ 1293 if (hdspm_tco_sync_check(hdspm)) 1294 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm)); 1295 break; 1296 default: 1297 return 0; 1298 } /* end switch(syncref) */ 1299 break; 1300 1301 case MADIface: 1302 status = hdspm_read(hdspm, HDSPM_statusRegister); 1303 1304 if (!(status & HDSPM_madiLock)) { 1305 rate = 0; /* no lock */ 1306 } else { 1307 switch (status & (HDSPM_status1_freqMask)) { 1308 case HDSPM_status1_F_0*1: 1309 rate = 32000; break; 1310 case HDSPM_status1_F_0*2: 1311 rate = 44100; break; 1312 case HDSPM_status1_F_0*3: 1313 rate = 48000; break; 1314 case HDSPM_status1_F_0*4: 1315 rate = 64000; break; 1316 case HDSPM_status1_F_0*5: 1317 rate = 88200; break; 1318 case HDSPM_status1_F_0*6: 1319 rate = 96000; break; 1320 case HDSPM_status1_F_0*7: 1321 rate = 128000; break; 1322 case HDSPM_status1_F_0*8: 1323 rate = 176400; break; 1324 case HDSPM_status1_F_0*9: 1325 rate = 192000; break; 1326 default: 1327 rate = 0; break; 1328 } 1329 } 1330 1331 break; 1332 1333 case MADI: 1334 case AIO: 1335 case RayDAT: 1336 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1337 status = hdspm_read(hdspm, HDSPM_statusRegister); 1338 rate = 0; 1339 1340 /* if wordclock has synced freq and wordclock is valid */ 1341 if ((status2 & HDSPM_wcLock) != 0 && 1342 (status2 & HDSPM_SelSyncRef0) == 0) { 1343 1344 rate_bits = status2 & HDSPM_wcFreqMask; 1345 1346 1347 switch (rate_bits) { 1348 case HDSPM_wcFreq32: 1349 rate = 32000; 1350 break; 1351 case HDSPM_wcFreq44_1: 1352 rate = 44100; 1353 break; 1354 case HDSPM_wcFreq48: 1355 rate = 48000; 1356 break; 1357 case HDSPM_wcFreq64: 1358 rate = 64000; 1359 break; 1360 case HDSPM_wcFreq88_2: 1361 rate = 88200; 1362 break; 1363 case HDSPM_wcFreq96: 1364 rate = 96000; 1365 break; 1366 case HDSPM_wcFreq128: 1367 rate = 128000; 1368 break; 1369 case HDSPM_wcFreq176_4: 1370 rate = 176400; 1371 break; 1372 case HDSPM_wcFreq192: 1373 rate = 192000; 1374 break; 1375 default: 1376 rate = 0; 1377 break; 1378 } 1379 } 1380 1381 /* if rate detected and Syncref is Word than have it, 1382 * word has priority to MADI 1383 */ 1384 if (rate != 0 && 1385 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1386 return hdspm_rate_multiplier(hdspm, rate); 1387 1388 /* maybe a madi input (which is taken if sel sync is madi) */ 1389 if (status & HDSPM_madiLock) { 1390 rate_bits = status & HDSPM_madiFreqMask; 1391 1392 switch (rate_bits) { 1393 case HDSPM_madiFreq32: 1394 rate = 32000; 1395 break; 1396 case HDSPM_madiFreq44_1: 1397 rate = 44100; 1398 break; 1399 case HDSPM_madiFreq48: 1400 rate = 48000; 1401 break; 1402 case HDSPM_madiFreq64: 1403 rate = 64000; 1404 break; 1405 case HDSPM_madiFreq88_2: 1406 rate = 88200; 1407 break; 1408 case HDSPM_madiFreq96: 1409 rate = 96000; 1410 break; 1411 case HDSPM_madiFreq128: 1412 rate = 128000; 1413 break; 1414 case HDSPM_madiFreq176_4: 1415 rate = 176400; 1416 break; 1417 case HDSPM_madiFreq192: 1418 rate = 192000; 1419 break; 1420 default: 1421 rate = 0; 1422 break; 1423 } 1424 1425 } /* endif HDSPM_madiLock */ 1426 1427 /* check sample rate from TCO or SYNC_IN */ 1428 { 1429 bool is_valid_input = 0; 1430 bool has_sync = 0; 1431 1432 syncref = hdspm_autosync_ref(hdspm); 1433 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1434 is_valid_input = 1; 1435 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1436 hdspm_tco_sync_check(hdspm)); 1437 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1438 is_valid_input = 1; 1439 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1440 hdspm_sync_in_sync_check(hdspm)); 1441 } 1442 1443 if (is_valid_input && has_sync) { 1444 rate = hdspm_round_frequency( 1445 hdspm_get_pll_freq(hdspm)); 1446 } 1447 } 1448 1449 rate = hdspm_rate_multiplier(hdspm, rate); 1450 1451 break; 1452 } 1453 1454 return rate; 1455 } 1456 1457 /* return latency in samples per period */ 1458 static int hdspm_get_latency(struct hdspm *hdspm) 1459 { 1460 int n; 1461 1462 n = hdspm_decode_latency(hdspm->control_register); 1463 1464 /* Special case for new RME cards with 32 samples period size. 1465 * The three latency bits in the control register 1466 * (HDSP_LatencyMask) encode latency values of 64 samples as 1467 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1468 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1469 * it corresponds to 32 samples. 1470 */ 1471 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1472 n = -1; 1473 1474 return 1 << (n + 6); 1475 } 1476 1477 /* Latency function */ 1478 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1479 { 1480 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1481 } 1482 1483 1484 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1485 { 1486 int position; 1487 1488 position = hdspm_read(hdspm, HDSPM_statusRegister); 1489 1490 switch (hdspm->io_type) { 1491 case RayDAT: 1492 case AIO: 1493 position &= HDSPM_BufferPositionMask; 1494 position /= 4; /* Bytes per sample */ 1495 break; 1496 default: 1497 position = (position & HDSPM_BufferID) ? 1498 (hdspm->period_bytes / 4) : 0; 1499 } 1500 1501 return position; 1502 } 1503 1504 1505 static inline void hdspm_start_audio(struct hdspm * s) 1506 { 1507 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1508 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1509 } 1510 1511 static inline void hdspm_stop_audio(struct hdspm * s) 1512 { 1513 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1514 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1515 } 1516 1517 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1518 static void hdspm_silence_playback(struct hdspm *hdspm) 1519 { 1520 int i; 1521 int n = hdspm->period_bytes; 1522 void *buf = hdspm->playback_buffer; 1523 1524 if (!buf) 1525 return; 1526 1527 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1528 memset(buf, 0, n); 1529 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1530 } 1531 } 1532 1533 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1534 { 1535 int n; 1536 1537 spin_lock_irq(&s->lock); 1538 1539 if (32 == frames) { 1540 /* Special case for new RME cards like RayDAT/AIO which 1541 * support period sizes of 32 samples. Since latency is 1542 * encoded in the three bits of HDSP_LatencyMask, we can only 1543 * have values from 0 .. 7. While 0 still means 64 samples and 1544 * 6 represents 4096 samples on all cards, 7 represents 8192 1545 * on older cards and 32 samples on new cards. 1546 * 1547 * In other words, period size in samples is calculated by 1548 * 2^(n+6) with n ranging from 0 .. 7. 1549 */ 1550 n = 7; 1551 } else { 1552 frames >>= 7; 1553 n = 0; 1554 while (frames) { 1555 n++; 1556 frames >>= 1; 1557 } 1558 } 1559 1560 s->control_register &= ~HDSPM_LatencyMask; 1561 s->control_register |= hdspm_encode_latency(n); 1562 1563 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1564 1565 hdspm_compute_period_size(s); 1566 1567 spin_unlock_irq(&s->lock); 1568 1569 return 0; 1570 } 1571 1572 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1573 { 1574 u64 freq_const; 1575 1576 if (period == 0) 1577 return 0; 1578 1579 switch (hdspm->io_type) { 1580 case MADI: 1581 case AES32: 1582 freq_const = 110069313433624ULL; 1583 break; 1584 case RayDAT: 1585 case AIO: 1586 freq_const = 104857600000000ULL; 1587 break; 1588 case MADIface: 1589 freq_const = 131072000000000ULL; 1590 break; 1591 default: 1592 snd_BUG(); 1593 return 0; 1594 } 1595 1596 return div_u64(freq_const, period); 1597 } 1598 1599 1600 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1601 { 1602 u64 n; 1603 1604 if (snd_BUG_ON(rate <= 0)) 1605 return; 1606 1607 if (rate >= 112000) 1608 rate /= 4; 1609 else if (rate >= 56000) 1610 rate /= 2; 1611 1612 switch (hdspm->io_type) { 1613 case MADIface: 1614 n = 131072000000000ULL; /* 125 MHz */ 1615 break; 1616 case MADI: 1617 case AES32: 1618 n = 110069313433624ULL; /* 105 MHz */ 1619 break; 1620 case RayDAT: 1621 case AIO: 1622 n = 104857600000000ULL; /* 100 MHz */ 1623 break; 1624 default: 1625 snd_BUG(); 1626 return; 1627 } 1628 1629 n = div_u64(n, rate); 1630 /* n should be less than 2^32 for being written to FREQ register */ 1631 snd_BUG_ON(n >> 32); 1632 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1633 } 1634 1635 /* dummy set rate lets see what happens */ 1636 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1637 { 1638 int current_rate; 1639 int rate_bits; 1640 int not_set = 0; 1641 int current_speed, target_speed; 1642 1643 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1644 it (e.g. during module initialization). 1645 */ 1646 1647 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1648 1649 /* SLAVE --- */ 1650 if (called_internally) { 1651 1652 /* request from ctl or card initialization 1653 just make a warning an remember setting 1654 for future master mode switching */ 1655 1656 dev_warn(hdspm->card->dev, 1657 "Warning: device is not running as a clock master.\n"); 1658 not_set = 1; 1659 } else { 1660 1661 /* hw_param request while in AutoSync mode */ 1662 int external_freq = 1663 hdspm_external_sample_rate(hdspm); 1664 1665 if (hdspm_autosync_ref(hdspm) == 1666 HDSPM_AUTOSYNC_FROM_NONE) { 1667 1668 dev_warn(hdspm->card->dev, 1669 "Detected no External Sync\n"); 1670 not_set = 1; 1671 1672 } else if (rate != external_freq) { 1673 1674 dev_warn(hdspm->card->dev, 1675 "Warning: No AutoSync source for requested rate\n"); 1676 not_set = 1; 1677 } 1678 } 1679 } 1680 1681 current_rate = hdspm->system_sample_rate; 1682 1683 /* Changing between Singe, Double and Quad speed is not 1684 allowed if any substreams are open. This is because such a change 1685 causes a shift in the location of the DMA buffers and a reduction 1686 in the number of available buffers. 1687 1688 Note that a similar but essentially insoluble problem exists for 1689 externally-driven rate changes. All we can do is to flag rate 1690 changes in the read/write routines. 1691 */ 1692 1693 if (current_rate <= 48000) 1694 current_speed = HDSPM_SPEED_SINGLE; 1695 else if (current_rate <= 96000) 1696 current_speed = HDSPM_SPEED_DOUBLE; 1697 else 1698 current_speed = HDSPM_SPEED_QUAD; 1699 1700 if (rate <= 48000) 1701 target_speed = HDSPM_SPEED_SINGLE; 1702 else if (rate <= 96000) 1703 target_speed = HDSPM_SPEED_DOUBLE; 1704 else 1705 target_speed = HDSPM_SPEED_QUAD; 1706 1707 switch (rate) { 1708 case 32000: 1709 rate_bits = HDSPM_Frequency32KHz; 1710 break; 1711 case 44100: 1712 rate_bits = HDSPM_Frequency44_1KHz; 1713 break; 1714 case 48000: 1715 rate_bits = HDSPM_Frequency48KHz; 1716 break; 1717 case 64000: 1718 rate_bits = HDSPM_Frequency64KHz; 1719 break; 1720 case 88200: 1721 rate_bits = HDSPM_Frequency88_2KHz; 1722 break; 1723 case 96000: 1724 rate_bits = HDSPM_Frequency96KHz; 1725 break; 1726 case 128000: 1727 rate_bits = HDSPM_Frequency128KHz; 1728 break; 1729 case 176400: 1730 rate_bits = HDSPM_Frequency176_4KHz; 1731 break; 1732 case 192000: 1733 rate_bits = HDSPM_Frequency192KHz; 1734 break; 1735 default: 1736 return -EINVAL; 1737 } 1738 1739 if (current_speed != target_speed 1740 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1741 dev_err(hdspm->card->dev, 1742 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n", 1743 hdspm_speed_names[current_speed], 1744 hdspm_speed_names[target_speed], 1745 hdspm->capture_pid, hdspm->playback_pid); 1746 return -EBUSY; 1747 } 1748 1749 hdspm->control_register &= ~HDSPM_FrequencyMask; 1750 hdspm->control_register |= rate_bits; 1751 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1752 1753 /* For AES32, need to set DDS value in FREQ register 1754 For MADI, also apparently */ 1755 hdspm_set_dds_value(hdspm, rate); 1756 1757 if (AES32 == hdspm->io_type && rate != current_rate) 1758 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1759 1760 hdspm->system_sample_rate = rate; 1761 1762 if (rate <= 48000) { 1763 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1764 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1765 hdspm->max_channels_in = hdspm->ss_in_channels; 1766 hdspm->max_channels_out = hdspm->ss_out_channels; 1767 hdspm->port_names_in = hdspm->port_names_in_ss; 1768 hdspm->port_names_out = hdspm->port_names_out_ss; 1769 } else if (rate <= 96000) { 1770 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1771 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1772 hdspm->max_channels_in = hdspm->ds_in_channels; 1773 hdspm->max_channels_out = hdspm->ds_out_channels; 1774 hdspm->port_names_in = hdspm->port_names_in_ds; 1775 hdspm->port_names_out = hdspm->port_names_out_ds; 1776 } else { 1777 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1778 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1779 hdspm->max_channels_in = hdspm->qs_in_channels; 1780 hdspm->max_channels_out = hdspm->qs_out_channels; 1781 hdspm->port_names_in = hdspm->port_names_in_qs; 1782 hdspm->port_names_out = hdspm->port_names_out_qs; 1783 } 1784 1785 if (not_set != 0) 1786 return -1; 1787 1788 return 0; 1789 } 1790 1791 /* mainly for init to 0 on load */ 1792 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1793 { 1794 int i, j; 1795 unsigned int gain; 1796 1797 if (sgain > UNITY_GAIN) 1798 gain = UNITY_GAIN; 1799 else if (sgain < 0) 1800 gain = 0; 1801 else 1802 gain = sgain; 1803 1804 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1805 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1806 hdspm_write_in_gain(hdspm, i, j, gain); 1807 hdspm_write_pb_gain(hdspm, i, j, gain); 1808 } 1809 } 1810 1811 /*---------------------------------------------------------------------------- 1812 MIDI 1813 ----------------------------------------------------------------------------*/ 1814 1815 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1816 int id) 1817 { 1818 /* the hardware already does the relevant bit-mask with 0xff */ 1819 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1820 } 1821 1822 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1823 int val) 1824 { 1825 /* the hardware already does the relevant bit-mask with 0xff */ 1826 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1827 } 1828 1829 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1830 { 1831 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1832 } 1833 1834 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1835 { 1836 int fifo_bytes_used; 1837 1838 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1839 1840 if (fifo_bytes_used < 128) 1841 return 128 - fifo_bytes_used; 1842 else 1843 return 0; 1844 } 1845 1846 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1847 { 1848 while (snd_hdspm_midi_input_available (hdspm, id)) 1849 snd_hdspm_midi_read_byte (hdspm, id); 1850 } 1851 1852 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1853 { 1854 unsigned long flags; 1855 int n_pending; 1856 int to_write; 1857 int i; 1858 unsigned char buf[128]; 1859 1860 /* Output is not interrupt driven */ 1861 1862 spin_lock_irqsave (&hmidi->lock, flags); 1863 if (hmidi->output && 1864 !snd_rawmidi_transmit_empty (hmidi->output)) { 1865 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1866 hmidi->id); 1867 if (n_pending > 0) { 1868 if (n_pending > (int)sizeof (buf)) 1869 n_pending = sizeof (buf); 1870 1871 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1872 n_pending); 1873 if (to_write > 0) { 1874 for (i = 0; i < to_write; ++i) 1875 snd_hdspm_midi_write_byte (hmidi->hdspm, 1876 hmidi->id, 1877 buf[i]); 1878 } 1879 } 1880 } 1881 spin_unlock_irqrestore (&hmidi->lock, flags); 1882 return 0; 1883 } 1884 1885 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1886 { 1887 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1888 * input FIFO size 1889 */ 1890 unsigned long flags; 1891 int n_pending; 1892 int i; 1893 1894 spin_lock_irqsave (&hmidi->lock, flags); 1895 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1896 if (n_pending > 0) { 1897 if (hmidi->input) { 1898 if (n_pending > (int)sizeof (buf)) 1899 n_pending = sizeof (buf); 1900 for (i = 0; i < n_pending; ++i) 1901 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1902 hmidi->id); 1903 if (n_pending) 1904 snd_rawmidi_receive (hmidi->input, buf, 1905 n_pending); 1906 } else { 1907 /* flush the MIDI input FIFO */ 1908 while (n_pending--) 1909 snd_hdspm_midi_read_byte (hmidi->hdspm, 1910 hmidi->id); 1911 } 1912 } 1913 hmidi->pending = 0; 1914 spin_unlock_irqrestore(&hmidi->lock, flags); 1915 1916 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1917 hmidi->hdspm->control_register |= hmidi->ie; 1918 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1919 hmidi->hdspm->control_register); 1920 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1921 1922 return snd_hdspm_midi_output_write (hmidi); 1923 } 1924 1925 static void 1926 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1927 { 1928 struct hdspm *hdspm; 1929 struct hdspm_midi *hmidi; 1930 unsigned long flags; 1931 1932 hmidi = substream->rmidi->private_data; 1933 hdspm = hmidi->hdspm; 1934 1935 spin_lock_irqsave (&hdspm->lock, flags); 1936 if (up) { 1937 if (!(hdspm->control_register & hmidi->ie)) { 1938 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1939 hdspm->control_register |= hmidi->ie; 1940 } 1941 } else { 1942 hdspm->control_register &= ~hmidi->ie; 1943 } 1944 1945 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1946 spin_unlock_irqrestore (&hdspm->lock, flags); 1947 } 1948 1949 static void snd_hdspm_midi_output_timer(struct timer_list *t) 1950 { 1951 struct hdspm_midi *hmidi = from_timer(hmidi, t, timer); 1952 unsigned long flags; 1953 1954 snd_hdspm_midi_output_write(hmidi); 1955 spin_lock_irqsave (&hmidi->lock, flags); 1956 1957 /* this does not bump hmidi->istimer, because the 1958 kernel automatically removed the timer when it 1959 expired, and we are now adding it back, thus 1960 leaving istimer wherever it was set before. 1961 */ 1962 1963 if (hmidi->istimer) 1964 mod_timer(&hmidi->timer, 1 + jiffies); 1965 1966 spin_unlock_irqrestore (&hmidi->lock, flags); 1967 } 1968 1969 static void 1970 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1971 { 1972 struct hdspm_midi *hmidi; 1973 unsigned long flags; 1974 1975 hmidi = substream->rmidi->private_data; 1976 spin_lock_irqsave (&hmidi->lock, flags); 1977 if (up) { 1978 if (!hmidi->istimer) { 1979 timer_setup(&hmidi->timer, 1980 snd_hdspm_midi_output_timer, 0); 1981 mod_timer(&hmidi->timer, 1 + jiffies); 1982 hmidi->istimer++; 1983 } 1984 } else { 1985 if (hmidi->istimer && --hmidi->istimer <= 0) 1986 del_timer (&hmidi->timer); 1987 } 1988 spin_unlock_irqrestore (&hmidi->lock, flags); 1989 if (up) 1990 snd_hdspm_midi_output_write(hmidi); 1991 } 1992 1993 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1994 { 1995 struct hdspm_midi *hmidi; 1996 1997 hmidi = substream->rmidi->private_data; 1998 spin_lock_irq (&hmidi->lock); 1999 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 2000 hmidi->input = substream; 2001 spin_unlock_irq (&hmidi->lock); 2002 2003 return 0; 2004 } 2005 2006 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 2007 { 2008 struct hdspm_midi *hmidi; 2009 2010 hmidi = substream->rmidi->private_data; 2011 spin_lock_irq (&hmidi->lock); 2012 hmidi->output = substream; 2013 spin_unlock_irq (&hmidi->lock); 2014 2015 return 0; 2016 } 2017 2018 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 2019 { 2020 struct hdspm_midi *hmidi; 2021 2022 snd_hdspm_midi_input_trigger (substream, 0); 2023 2024 hmidi = substream->rmidi->private_data; 2025 spin_lock_irq (&hmidi->lock); 2026 hmidi->input = NULL; 2027 spin_unlock_irq (&hmidi->lock); 2028 2029 return 0; 2030 } 2031 2032 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 2033 { 2034 struct hdspm_midi *hmidi; 2035 2036 snd_hdspm_midi_output_trigger (substream, 0); 2037 2038 hmidi = substream->rmidi->private_data; 2039 spin_lock_irq (&hmidi->lock); 2040 hmidi->output = NULL; 2041 spin_unlock_irq (&hmidi->lock); 2042 2043 return 0; 2044 } 2045 2046 static const struct snd_rawmidi_ops snd_hdspm_midi_output = 2047 { 2048 .open = snd_hdspm_midi_output_open, 2049 .close = snd_hdspm_midi_output_close, 2050 .trigger = snd_hdspm_midi_output_trigger, 2051 }; 2052 2053 static const struct snd_rawmidi_ops snd_hdspm_midi_input = 2054 { 2055 .open = snd_hdspm_midi_input_open, 2056 .close = snd_hdspm_midi_input_close, 2057 .trigger = snd_hdspm_midi_input_trigger, 2058 }; 2059 2060 static int snd_hdspm_create_midi(struct snd_card *card, 2061 struct hdspm *hdspm, int id) 2062 { 2063 int err; 2064 char buf[64]; 2065 2066 hdspm->midi[id].id = id; 2067 hdspm->midi[id].hdspm = hdspm; 2068 spin_lock_init (&hdspm->midi[id].lock); 2069 2070 if (0 == id) { 2071 if (MADIface == hdspm->io_type) { 2072 /* MIDI-over-MADI on HDSPe MADIface */ 2073 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 2074 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 2075 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 2076 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 2077 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 2078 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 2079 } else { 2080 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 2081 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 2082 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 2083 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 2084 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 2085 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 2086 } 2087 } else if (1 == id) { 2088 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 2089 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 2090 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 2091 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 2092 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 2093 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 2094 } else if ((2 == id) && (MADI == hdspm->io_type)) { 2095 /* MIDI-over-MADI on HDSPe MADI */ 2096 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2097 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2098 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 2099 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 2100 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2101 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 2102 } else if (2 == id) { 2103 /* TCO MTC, read only */ 2104 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2105 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2106 hdspm->midi[2].dataOut = -1; 2107 hdspm->midi[2].statusOut = -1; 2108 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2109 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 2110 } else if (3 == id) { 2111 /* TCO MTC on HDSPe MADI */ 2112 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 2113 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 2114 hdspm->midi[3].dataOut = -1; 2115 hdspm->midi[3].statusOut = -1; 2116 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 2117 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 2118 } 2119 2120 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 2121 (MADIface == hdspm->io_type)))) { 2122 if ((id == 0) && (MADIface == hdspm->io_type)) { 2123 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2124 card->shortname); 2125 } else if ((id == 2) && (MADI == hdspm->io_type)) { 2126 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2127 card->shortname); 2128 } else { 2129 snprintf(buf, sizeof(buf), "%s MIDI %d", 2130 card->shortname, id+1); 2131 } 2132 err = snd_rawmidi_new(card, buf, id, 1, 1, 2133 &hdspm->midi[id].rmidi); 2134 if (err < 0) 2135 return err; 2136 2137 snprintf(hdspm->midi[id].rmidi->name, 2138 sizeof(hdspm->midi[id].rmidi->name), 2139 "%s MIDI %d", card->id, id+1); 2140 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2141 2142 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2143 SNDRV_RAWMIDI_STREAM_OUTPUT, 2144 &snd_hdspm_midi_output); 2145 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2146 SNDRV_RAWMIDI_STREAM_INPUT, 2147 &snd_hdspm_midi_input); 2148 2149 hdspm->midi[id].rmidi->info_flags |= 2150 SNDRV_RAWMIDI_INFO_OUTPUT | 2151 SNDRV_RAWMIDI_INFO_INPUT | 2152 SNDRV_RAWMIDI_INFO_DUPLEX; 2153 } else { 2154 /* TCO MTC, read only */ 2155 snprintf(buf, sizeof(buf), "%s MTC %d", 2156 card->shortname, id+1); 2157 err = snd_rawmidi_new(card, buf, id, 1, 1, 2158 &hdspm->midi[id].rmidi); 2159 if (err < 0) 2160 return err; 2161 2162 snprintf(hdspm->midi[id].rmidi->name, 2163 sizeof(hdspm->midi[id].rmidi->name), 2164 "%s MTC %d", card->id, id+1); 2165 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2166 2167 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2168 SNDRV_RAWMIDI_STREAM_INPUT, 2169 &snd_hdspm_midi_input); 2170 2171 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2172 } 2173 2174 return 0; 2175 } 2176 2177 2178 static void hdspm_midi_tasklet(unsigned long arg) 2179 { 2180 struct hdspm *hdspm = (struct hdspm *)arg; 2181 int i = 0; 2182 2183 while (i < hdspm->midiPorts) { 2184 if (hdspm->midi[i].pending) 2185 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2186 2187 i++; 2188 } 2189 } 2190 2191 2192 /*----------------------------------------------------------------------------- 2193 Status Interface 2194 ----------------------------------------------------------------------------*/ 2195 2196 /* get the system sample rate which is set */ 2197 2198 2199 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2200 { 2201 unsigned int period, rate; 2202 2203 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2204 rate = hdspm_calc_dds_value(hdspm, period); 2205 2206 return rate; 2207 } 2208 2209 /* 2210 * Calculate the real sample rate from the 2211 * current DDS value. 2212 */ 2213 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2214 { 2215 unsigned int rate; 2216 2217 rate = hdspm_get_pll_freq(hdspm); 2218 2219 if (rate > 207000) { 2220 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2221 if (0 == hdspm_system_clock_mode(hdspm)) { 2222 /* master mode, return internal sample rate */ 2223 rate = hdspm->system_sample_rate; 2224 } else { 2225 /* slave mode, return external sample rate */ 2226 rate = hdspm_external_sample_rate(hdspm); 2227 if (!rate) 2228 rate = hdspm->system_sample_rate; 2229 } 2230 } 2231 2232 return rate; 2233 } 2234 2235 2236 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2237 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2238 .name = xname, \ 2239 .index = xindex, \ 2240 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2241 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2242 .info = snd_hdspm_info_system_sample_rate, \ 2243 .put = snd_hdspm_put_system_sample_rate, \ 2244 .get = snd_hdspm_get_system_sample_rate \ 2245 } 2246 2247 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2248 struct snd_ctl_elem_info *uinfo) 2249 { 2250 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2251 uinfo->count = 1; 2252 uinfo->value.integer.min = 27000; 2253 uinfo->value.integer.max = 207000; 2254 uinfo->value.integer.step = 1; 2255 return 0; 2256 } 2257 2258 2259 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2260 struct snd_ctl_elem_value * 2261 ucontrol) 2262 { 2263 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2264 2265 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2266 return 0; 2267 } 2268 2269 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2270 struct snd_ctl_elem_value * 2271 ucontrol) 2272 { 2273 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2274 int rate = ucontrol->value.integer.value[0]; 2275 2276 if (rate < 27000 || rate > 207000) 2277 return -EINVAL; 2278 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]); 2279 return 0; 2280 } 2281 2282 2283 /* 2284 * Returns the WordClock sample rate class for the given card. 2285 */ 2286 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2287 { 2288 int status; 2289 2290 switch (hdspm->io_type) { 2291 case RayDAT: 2292 case AIO: 2293 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2294 return (status >> 16) & 0xF; 2295 break; 2296 case AES32: 2297 status = hdspm_read(hdspm, HDSPM_statusRegister); 2298 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF; 2299 default: 2300 break; 2301 } 2302 2303 2304 return 0; 2305 } 2306 2307 2308 /* 2309 * Returns the TCO sample rate class for the given card. 2310 */ 2311 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2312 { 2313 int status; 2314 2315 if (hdspm->tco) { 2316 switch (hdspm->io_type) { 2317 case RayDAT: 2318 case AIO: 2319 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2320 return (status >> 20) & 0xF; 2321 break; 2322 case AES32: 2323 status = hdspm_read(hdspm, HDSPM_statusRegister); 2324 return (status >> 1) & 0xF; 2325 default: 2326 break; 2327 } 2328 } 2329 2330 return 0; 2331 } 2332 2333 2334 /* 2335 * Returns the SYNC_IN sample rate class for the given card. 2336 */ 2337 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2338 { 2339 int status; 2340 2341 if (hdspm->tco) { 2342 switch (hdspm->io_type) { 2343 case RayDAT: 2344 case AIO: 2345 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2346 return (status >> 12) & 0xF; 2347 break; 2348 default: 2349 break; 2350 } 2351 } 2352 2353 return 0; 2354 } 2355 2356 /* 2357 * Returns the AES sample rate class for the given card. 2358 */ 2359 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index) 2360 { 2361 int timecode; 2362 2363 switch (hdspm->io_type) { 2364 case AES32: 2365 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 2366 return (timecode >> (4*index)) & 0xF; 2367 break; 2368 default: 2369 break; 2370 } 2371 return 0; 2372 } 2373 2374 /* 2375 * Returns the sample rate class for input source <idx> for 2376 * 'new style' cards like the AIO and RayDAT. 2377 */ 2378 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2379 { 2380 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2381 2382 return (status >> (idx*4)) & 0xF; 2383 } 2384 2385 #define ENUMERATED_CTL_INFO(info, texts) \ 2386 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts) 2387 2388 2389 /* Helper function to query the external sample rate and return the 2390 * corresponding enum to be returned to userspace. 2391 */ 2392 static int hdspm_external_rate_to_enum(struct hdspm *hdspm) 2393 { 2394 int rate = hdspm_external_sample_rate(hdspm); 2395 int i, selected_rate = 0; 2396 for (i = 1; i < 10; i++) 2397 if (HDSPM_bit2freq(i) == rate) { 2398 selected_rate = i; 2399 break; 2400 } 2401 return selected_rate; 2402 } 2403 2404 2405 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2406 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2407 .name = xname, \ 2408 .private_value = xindex, \ 2409 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2410 .info = snd_hdspm_info_autosync_sample_rate, \ 2411 .get = snd_hdspm_get_autosync_sample_rate \ 2412 } 2413 2414 2415 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2416 struct snd_ctl_elem_info *uinfo) 2417 { 2418 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2419 return 0; 2420 } 2421 2422 2423 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2424 struct snd_ctl_elem_value * 2425 ucontrol) 2426 { 2427 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2428 2429 switch (hdspm->io_type) { 2430 case RayDAT: 2431 switch (kcontrol->private_value) { 2432 case 0: 2433 ucontrol->value.enumerated.item[0] = 2434 hdspm_get_wc_sample_rate(hdspm); 2435 break; 2436 case 7: 2437 ucontrol->value.enumerated.item[0] = 2438 hdspm_get_tco_sample_rate(hdspm); 2439 break; 2440 case 8: 2441 ucontrol->value.enumerated.item[0] = 2442 hdspm_get_sync_in_sample_rate(hdspm); 2443 break; 2444 default: 2445 ucontrol->value.enumerated.item[0] = 2446 hdspm_get_s1_sample_rate(hdspm, 2447 kcontrol->private_value-1); 2448 } 2449 break; 2450 2451 case AIO: 2452 switch (kcontrol->private_value) { 2453 case 0: /* WC */ 2454 ucontrol->value.enumerated.item[0] = 2455 hdspm_get_wc_sample_rate(hdspm); 2456 break; 2457 case 4: /* TCO */ 2458 ucontrol->value.enumerated.item[0] = 2459 hdspm_get_tco_sample_rate(hdspm); 2460 break; 2461 case 5: /* SYNC_IN */ 2462 ucontrol->value.enumerated.item[0] = 2463 hdspm_get_sync_in_sample_rate(hdspm); 2464 break; 2465 default: 2466 ucontrol->value.enumerated.item[0] = 2467 hdspm_get_s1_sample_rate(hdspm, 2468 kcontrol->private_value-1); 2469 } 2470 break; 2471 2472 case AES32: 2473 2474 switch (kcontrol->private_value) { 2475 case 0: /* WC */ 2476 ucontrol->value.enumerated.item[0] = 2477 hdspm_get_wc_sample_rate(hdspm); 2478 break; 2479 case 9: /* TCO */ 2480 ucontrol->value.enumerated.item[0] = 2481 hdspm_get_tco_sample_rate(hdspm); 2482 break; 2483 case 10: /* SYNC_IN */ 2484 ucontrol->value.enumerated.item[0] = 2485 hdspm_get_sync_in_sample_rate(hdspm); 2486 break; 2487 case 11: /* External Rate */ 2488 ucontrol->value.enumerated.item[0] = 2489 hdspm_external_rate_to_enum(hdspm); 2490 break; 2491 default: /* AES1 to AES8 */ 2492 ucontrol->value.enumerated.item[0] = 2493 hdspm_get_aes_sample_rate(hdspm, 2494 kcontrol->private_value - 2495 HDSPM_AES32_AUTOSYNC_FROM_AES1); 2496 break; 2497 } 2498 break; 2499 2500 case MADI: 2501 case MADIface: 2502 ucontrol->value.enumerated.item[0] = 2503 hdspm_external_rate_to_enum(hdspm); 2504 break; 2505 default: 2506 break; 2507 } 2508 2509 return 0; 2510 } 2511 2512 2513 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2514 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2515 .name = xname, \ 2516 .index = xindex, \ 2517 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2518 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2519 .info = snd_hdspm_info_system_clock_mode, \ 2520 .get = snd_hdspm_get_system_clock_mode, \ 2521 .put = snd_hdspm_put_system_clock_mode, \ 2522 } 2523 2524 2525 /* 2526 * Returns the system clock mode for the given card. 2527 * @returns 0 - master, 1 - slave 2528 */ 2529 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2530 { 2531 switch (hdspm->io_type) { 2532 case AIO: 2533 case RayDAT: 2534 if (hdspm->settings_register & HDSPM_c0Master) 2535 return 0; 2536 break; 2537 2538 default: 2539 if (hdspm->control_register & HDSPM_ClockModeMaster) 2540 return 0; 2541 } 2542 2543 return 1; 2544 } 2545 2546 2547 /* 2548 * Sets the system clock mode. 2549 * @param mode 0 - master, 1 - slave 2550 */ 2551 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2552 { 2553 hdspm_set_toggle_setting(hdspm, 2554 (hdspm_is_raydat_or_aio(hdspm)) ? 2555 HDSPM_c0Master : HDSPM_ClockModeMaster, 2556 (0 == mode)); 2557 } 2558 2559 2560 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2561 struct snd_ctl_elem_info *uinfo) 2562 { 2563 static const char *const texts[] = { "Master", "AutoSync" }; 2564 ENUMERATED_CTL_INFO(uinfo, texts); 2565 return 0; 2566 } 2567 2568 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2569 struct snd_ctl_elem_value *ucontrol) 2570 { 2571 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2572 2573 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2574 return 0; 2575 } 2576 2577 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2578 struct snd_ctl_elem_value *ucontrol) 2579 { 2580 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2581 int val; 2582 2583 if (!snd_hdspm_use_is_exclusive(hdspm)) 2584 return -EBUSY; 2585 2586 val = ucontrol->value.enumerated.item[0]; 2587 if (val < 0) 2588 val = 0; 2589 else if (val > 1) 2590 val = 1; 2591 2592 hdspm_set_system_clock_mode(hdspm, val); 2593 2594 return 0; 2595 } 2596 2597 2598 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2599 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2600 .name = xname, \ 2601 .index = xindex, \ 2602 .info = snd_hdspm_info_clock_source, \ 2603 .get = snd_hdspm_get_clock_source, \ 2604 .put = snd_hdspm_put_clock_source \ 2605 } 2606 2607 2608 static int hdspm_clock_source(struct hdspm * hdspm) 2609 { 2610 switch (hdspm->system_sample_rate) { 2611 case 32000: return 0; 2612 case 44100: return 1; 2613 case 48000: return 2; 2614 case 64000: return 3; 2615 case 88200: return 4; 2616 case 96000: return 5; 2617 case 128000: return 6; 2618 case 176400: return 7; 2619 case 192000: return 8; 2620 } 2621 2622 return -1; 2623 } 2624 2625 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2626 { 2627 int rate; 2628 switch (mode) { 2629 case 0: 2630 rate = 32000; break; 2631 case 1: 2632 rate = 44100; break; 2633 case 2: 2634 rate = 48000; break; 2635 case 3: 2636 rate = 64000; break; 2637 case 4: 2638 rate = 88200; break; 2639 case 5: 2640 rate = 96000; break; 2641 case 6: 2642 rate = 128000; break; 2643 case 7: 2644 rate = 176400; break; 2645 case 8: 2646 rate = 192000; break; 2647 default: 2648 rate = 48000; 2649 } 2650 hdspm_set_rate(hdspm, rate, 1); 2651 return 0; 2652 } 2653 2654 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2655 struct snd_ctl_elem_info *uinfo) 2656 { 2657 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1); 2658 } 2659 2660 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2661 struct snd_ctl_elem_value *ucontrol) 2662 { 2663 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2664 2665 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2666 return 0; 2667 } 2668 2669 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2670 struct snd_ctl_elem_value *ucontrol) 2671 { 2672 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2673 int change; 2674 int val; 2675 2676 if (!snd_hdspm_use_is_exclusive(hdspm)) 2677 return -EBUSY; 2678 val = ucontrol->value.enumerated.item[0]; 2679 if (val < 0) 2680 val = 0; 2681 if (val > 9) 2682 val = 9; 2683 spin_lock_irq(&hdspm->lock); 2684 if (val != hdspm_clock_source(hdspm)) 2685 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2686 else 2687 change = 0; 2688 spin_unlock_irq(&hdspm->lock); 2689 return change; 2690 } 2691 2692 2693 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2694 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2695 .name = xname, \ 2696 .index = xindex, \ 2697 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2698 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2699 .info = snd_hdspm_info_pref_sync_ref, \ 2700 .get = snd_hdspm_get_pref_sync_ref, \ 2701 .put = snd_hdspm_put_pref_sync_ref \ 2702 } 2703 2704 2705 /* 2706 * Returns the current preferred sync reference setting. 2707 * The semantics of the return value are depending on the 2708 * card, please see the comments for clarification. 2709 */ 2710 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2711 { 2712 switch (hdspm->io_type) { 2713 case AES32: 2714 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2715 case 0: return 0; /* WC */ 2716 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2717 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2718 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2719 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2720 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2721 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2722 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2723 return 7; /* AES 7 */ 2724 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2725 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2726 } 2727 break; 2728 2729 case MADI: 2730 case MADIface: 2731 if (hdspm->tco) { 2732 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2733 case 0: return 0; /* WC */ 2734 case HDSPM_SyncRef0: return 1; /* MADI */ 2735 case HDSPM_SyncRef1: return 2; /* TCO */ 2736 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2737 return 3; /* SYNC_IN */ 2738 } 2739 } else { 2740 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2741 case 0: return 0; /* WC */ 2742 case HDSPM_SyncRef0: return 1; /* MADI */ 2743 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2744 return 2; /* SYNC_IN */ 2745 } 2746 } 2747 break; 2748 2749 case RayDAT: 2750 if (hdspm->tco) { 2751 switch ((hdspm->settings_register & 2752 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2753 case 0: return 0; /* WC */ 2754 case 3: return 1; /* ADAT 1 */ 2755 case 4: return 2; /* ADAT 2 */ 2756 case 5: return 3; /* ADAT 3 */ 2757 case 6: return 4; /* ADAT 4 */ 2758 case 1: return 5; /* AES */ 2759 case 2: return 6; /* SPDIF */ 2760 case 9: return 7; /* TCO */ 2761 case 10: return 8; /* SYNC_IN */ 2762 } 2763 } else { 2764 switch ((hdspm->settings_register & 2765 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2766 case 0: return 0; /* WC */ 2767 case 3: return 1; /* ADAT 1 */ 2768 case 4: return 2; /* ADAT 2 */ 2769 case 5: return 3; /* ADAT 3 */ 2770 case 6: return 4; /* ADAT 4 */ 2771 case 1: return 5; /* AES */ 2772 case 2: return 6; /* SPDIF */ 2773 case 10: return 7; /* SYNC_IN */ 2774 } 2775 } 2776 2777 break; 2778 2779 case AIO: 2780 if (hdspm->tco) { 2781 switch ((hdspm->settings_register & 2782 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2783 case 0: return 0; /* WC */ 2784 case 3: return 1; /* ADAT */ 2785 case 1: return 2; /* AES */ 2786 case 2: return 3; /* SPDIF */ 2787 case 9: return 4; /* TCO */ 2788 case 10: return 5; /* SYNC_IN */ 2789 } 2790 } else { 2791 switch ((hdspm->settings_register & 2792 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2793 case 0: return 0; /* WC */ 2794 case 3: return 1; /* ADAT */ 2795 case 1: return 2; /* AES */ 2796 case 2: return 3; /* SPDIF */ 2797 case 10: return 4; /* SYNC_IN */ 2798 } 2799 } 2800 2801 break; 2802 } 2803 2804 return -1; 2805 } 2806 2807 2808 /* 2809 * Set the preferred sync reference to <pref>. The semantics 2810 * of <pref> are depending on the card type, see the comments 2811 * for clarification. 2812 */ 2813 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2814 { 2815 int p = 0; 2816 2817 switch (hdspm->io_type) { 2818 case AES32: 2819 hdspm->control_register &= ~HDSPM_SyncRefMask; 2820 switch (pref) { 2821 case 0: /* WC */ 2822 break; 2823 case 1: /* AES 1 */ 2824 hdspm->control_register |= HDSPM_SyncRef0; 2825 break; 2826 case 2: /* AES 2 */ 2827 hdspm->control_register |= HDSPM_SyncRef1; 2828 break; 2829 case 3: /* AES 3 */ 2830 hdspm->control_register |= 2831 HDSPM_SyncRef1+HDSPM_SyncRef0; 2832 break; 2833 case 4: /* AES 4 */ 2834 hdspm->control_register |= HDSPM_SyncRef2; 2835 break; 2836 case 5: /* AES 5 */ 2837 hdspm->control_register |= 2838 HDSPM_SyncRef2+HDSPM_SyncRef0; 2839 break; 2840 case 6: /* AES 6 */ 2841 hdspm->control_register |= 2842 HDSPM_SyncRef2+HDSPM_SyncRef1; 2843 break; 2844 case 7: /* AES 7 */ 2845 hdspm->control_register |= 2846 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2847 break; 2848 case 8: /* AES 8 */ 2849 hdspm->control_register |= HDSPM_SyncRef3; 2850 break; 2851 case 9: /* TCO */ 2852 hdspm->control_register |= 2853 HDSPM_SyncRef3+HDSPM_SyncRef0; 2854 break; 2855 default: 2856 return -1; 2857 } 2858 2859 break; 2860 2861 case MADI: 2862 case MADIface: 2863 hdspm->control_register &= ~HDSPM_SyncRefMask; 2864 if (hdspm->tco) { 2865 switch (pref) { 2866 case 0: /* WC */ 2867 break; 2868 case 1: /* MADI */ 2869 hdspm->control_register |= HDSPM_SyncRef0; 2870 break; 2871 case 2: /* TCO */ 2872 hdspm->control_register |= HDSPM_SyncRef1; 2873 break; 2874 case 3: /* SYNC_IN */ 2875 hdspm->control_register |= 2876 HDSPM_SyncRef0+HDSPM_SyncRef1; 2877 break; 2878 default: 2879 return -1; 2880 } 2881 } else { 2882 switch (pref) { 2883 case 0: /* WC */ 2884 break; 2885 case 1: /* MADI */ 2886 hdspm->control_register |= HDSPM_SyncRef0; 2887 break; 2888 case 2: /* SYNC_IN */ 2889 hdspm->control_register |= 2890 HDSPM_SyncRef0+HDSPM_SyncRef1; 2891 break; 2892 default: 2893 return -1; 2894 } 2895 } 2896 2897 break; 2898 2899 case RayDAT: 2900 if (hdspm->tco) { 2901 switch (pref) { 2902 case 0: p = 0; break; /* WC */ 2903 case 1: p = 3; break; /* ADAT 1 */ 2904 case 2: p = 4; break; /* ADAT 2 */ 2905 case 3: p = 5; break; /* ADAT 3 */ 2906 case 4: p = 6; break; /* ADAT 4 */ 2907 case 5: p = 1; break; /* AES */ 2908 case 6: p = 2; break; /* SPDIF */ 2909 case 7: p = 9; break; /* TCO */ 2910 case 8: p = 10; break; /* SYNC_IN */ 2911 default: return -1; 2912 } 2913 } else { 2914 switch (pref) { 2915 case 0: p = 0; break; /* WC */ 2916 case 1: p = 3; break; /* ADAT 1 */ 2917 case 2: p = 4; break; /* ADAT 2 */ 2918 case 3: p = 5; break; /* ADAT 3 */ 2919 case 4: p = 6; break; /* ADAT 4 */ 2920 case 5: p = 1; break; /* AES */ 2921 case 6: p = 2; break; /* SPDIF */ 2922 case 7: p = 10; break; /* SYNC_IN */ 2923 default: return -1; 2924 } 2925 } 2926 break; 2927 2928 case AIO: 2929 if (hdspm->tco) { 2930 switch (pref) { 2931 case 0: p = 0; break; /* WC */ 2932 case 1: p = 3; break; /* ADAT */ 2933 case 2: p = 1; break; /* AES */ 2934 case 3: p = 2; break; /* SPDIF */ 2935 case 4: p = 9; break; /* TCO */ 2936 case 5: p = 10; break; /* SYNC_IN */ 2937 default: return -1; 2938 } 2939 } else { 2940 switch (pref) { 2941 case 0: p = 0; break; /* WC */ 2942 case 1: p = 3; break; /* ADAT */ 2943 case 2: p = 1; break; /* AES */ 2944 case 3: p = 2; break; /* SPDIF */ 2945 case 4: p = 10; break; /* SYNC_IN */ 2946 default: return -1; 2947 } 2948 } 2949 break; 2950 } 2951 2952 switch (hdspm->io_type) { 2953 case RayDAT: 2954 case AIO: 2955 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2956 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2957 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2958 break; 2959 2960 case MADI: 2961 case MADIface: 2962 case AES32: 2963 hdspm_write(hdspm, HDSPM_controlRegister, 2964 hdspm->control_register); 2965 } 2966 2967 return 0; 2968 } 2969 2970 2971 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2972 struct snd_ctl_elem_info *uinfo) 2973 { 2974 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2975 2976 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync); 2977 2978 return 0; 2979 } 2980 2981 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2982 struct snd_ctl_elem_value *ucontrol) 2983 { 2984 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2985 int psf = hdspm_pref_sync_ref(hdspm); 2986 2987 if (psf >= 0) { 2988 ucontrol->value.enumerated.item[0] = psf; 2989 return 0; 2990 } 2991 2992 return -1; 2993 } 2994 2995 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2996 struct snd_ctl_elem_value *ucontrol) 2997 { 2998 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2999 int val, change = 0; 3000 3001 if (!snd_hdspm_use_is_exclusive(hdspm)) 3002 return -EBUSY; 3003 3004 val = ucontrol->value.enumerated.item[0]; 3005 3006 if (val < 0) 3007 val = 0; 3008 else if (val >= hdspm->texts_autosync_items) 3009 val = hdspm->texts_autosync_items-1; 3010 3011 spin_lock_irq(&hdspm->lock); 3012 if (val != hdspm_pref_sync_ref(hdspm)) 3013 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 3014 3015 spin_unlock_irq(&hdspm->lock); 3016 return change; 3017 } 3018 3019 3020 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 3021 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3022 .name = xname, \ 3023 .index = xindex, \ 3024 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 3025 .info = snd_hdspm_info_autosync_ref, \ 3026 .get = snd_hdspm_get_autosync_ref, \ 3027 } 3028 3029 static int hdspm_autosync_ref(struct hdspm *hdspm) 3030 { 3031 /* This looks at the autosync selected sync reference */ 3032 if (AES32 == hdspm->io_type) { 3033 3034 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 3035 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF; 3036 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) && 3037 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) { 3038 return syncref; 3039 } 3040 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 3041 3042 } else if (MADI == hdspm->io_type) { 3043 3044 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3045 switch (status2 & HDSPM_SelSyncRefMask) { 3046 case HDSPM_SelSyncRef_WORD: 3047 return HDSPM_AUTOSYNC_FROM_WORD; 3048 case HDSPM_SelSyncRef_MADI: 3049 return HDSPM_AUTOSYNC_FROM_MADI; 3050 case HDSPM_SelSyncRef_TCO: 3051 return HDSPM_AUTOSYNC_FROM_TCO; 3052 case HDSPM_SelSyncRef_SyncIn: 3053 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 3054 case HDSPM_SelSyncRef_NVALID: 3055 return HDSPM_AUTOSYNC_FROM_NONE; 3056 default: 3057 return HDSPM_AUTOSYNC_FROM_NONE; 3058 } 3059 3060 } 3061 return 0; 3062 } 3063 3064 3065 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 3066 struct snd_ctl_elem_info *uinfo) 3067 { 3068 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3069 3070 if (AES32 == hdspm->io_type) { 3071 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3", 3072 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"}; 3073 3074 ENUMERATED_CTL_INFO(uinfo, texts); 3075 } else if (MADI == hdspm->io_type) { 3076 static const char *const texts[] = {"Word Clock", "MADI", "TCO", 3077 "Sync In", "None" }; 3078 3079 ENUMERATED_CTL_INFO(uinfo, texts); 3080 } 3081 return 0; 3082 } 3083 3084 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 3085 struct snd_ctl_elem_value *ucontrol) 3086 { 3087 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3088 3089 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 3090 return 0; 3091 } 3092 3093 3094 3095 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \ 3096 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3097 .name = xname, \ 3098 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3099 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3100 .info = snd_hdspm_info_tco_video_input_format, \ 3101 .get = snd_hdspm_get_tco_video_input_format, \ 3102 } 3103 3104 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 3105 struct snd_ctl_elem_info *uinfo) 3106 { 3107 static const char *const texts[] = {"No video", "NTSC", "PAL"}; 3108 ENUMERATED_CTL_INFO(uinfo, texts); 3109 return 0; 3110 } 3111 3112 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 3113 struct snd_ctl_elem_value *ucontrol) 3114 { 3115 u32 status; 3116 int ret = 0; 3117 3118 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3119 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3120 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3121 HDSPM_TCO1_Video_Input_Format_PAL)) { 3122 case HDSPM_TCO1_Video_Input_Format_NTSC: 3123 /* ntsc */ 3124 ret = 1; 3125 break; 3126 case HDSPM_TCO1_Video_Input_Format_PAL: 3127 /* pal */ 3128 ret = 2; 3129 break; 3130 default: 3131 /* no video */ 3132 ret = 0; 3133 break; 3134 } 3135 ucontrol->value.enumerated.item[0] = ret; 3136 return 0; 3137 } 3138 3139 3140 3141 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \ 3142 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3143 .name = xname, \ 3144 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3145 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3146 .info = snd_hdspm_info_tco_ltc_frames, \ 3147 .get = snd_hdspm_get_tco_ltc_frames, \ 3148 } 3149 3150 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3151 struct snd_ctl_elem_info *uinfo) 3152 { 3153 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3154 "30 fps"}; 3155 ENUMERATED_CTL_INFO(uinfo, texts); 3156 return 0; 3157 } 3158 3159 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3160 { 3161 u32 status; 3162 int ret = 0; 3163 3164 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3165 if (status & HDSPM_TCO1_LTC_Input_valid) { 3166 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3167 HDSPM_TCO1_LTC_Format_MSB)) { 3168 case 0: 3169 /* 24 fps */ 3170 ret = fps_24; 3171 break; 3172 case HDSPM_TCO1_LTC_Format_LSB: 3173 /* 25 fps */ 3174 ret = fps_25; 3175 break; 3176 case HDSPM_TCO1_LTC_Format_MSB: 3177 /* 29.97 fps */ 3178 ret = fps_2997; 3179 break; 3180 default: 3181 /* 30 fps */ 3182 ret = fps_30; 3183 break; 3184 } 3185 } 3186 3187 return ret; 3188 } 3189 3190 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3191 struct snd_ctl_elem_value *ucontrol) 3192 { 3193 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3194 3195 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3196 return 0; 3197 } 3198 3199 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3200 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3201 .name = xname, \ 3202 .private_value = xindex, \ 3203 .info = snd_hdspm_info_toggle_setting, \ 3204 .get = snd_hdspm_get_toggle_setting, \ 3205 .put = snd_hdspm_put_toggle_setting \ 3206 } 3207 3208 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3209 { 3210 u32 reg; 3211 3212 if (hdspm_is_raydat_or_aio(hdspm)) 3213 reg = hdspm->settings_register; 3214 else 3215 reg = hdspm->control_register; 3216 3217 return (reg & regmask) ? 1 : 0; 3218 } 3219 3220 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3221 { 3222 u32 *reg; 3223 u32 target_reg; 3224 3225 if (hdspm_is_raydat_or_aio(hdspm)) { 3226 reg = &(hdspm->settings_register); 3227 target_reg = HDSPM_WR_SETTINGS; 3228 } else { 3229 reg = &(hdspm->control_register); 3230 target_reg = HDSPM_controlRegister; 3231 } 3232 3233 if (out) 3234 *reg |= regmask; 3235 else 3236 *reg &= ~regmask; 3237 3238 hdspm_write(hdspm, target_reg, *reg); 3239 3240 return 0; 3241 } 3242 3243 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3244 3245 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3246 struct snd_ctl_elem_value *ucontrol) 3247 { 3248 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3249 u32 regmask = kcontrol->private_value; 3250 3251 spin_lock_irq(&hdspm->lock); 3252 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3253 spin_unlock_irq(&hdspm->lock); 3254 return 0; 3255 } 3256 3257 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3258 struct snd_ctl_elem_value *ucontrol) 3259 { 3260 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3261 u32 regmask = kcontrol->private_value; 3262 int change; 3263 unsigned int val; 3264 3265 if (!snd_hdspm_use_is_exclusive(hdspm)) 3266 return -EBUSY; 3267 val = ucontrol->value.integer.value[0] & 1; 3268 spin_lock_irq(&hdspm->lock); 3269 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3270 hdspm_set_toggle_setting(hdspm, regmask, val); 3271 spin_unlock_irq(&hdspm->lock); 3272 return change; 3273 } 3274 3275 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3276 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3277 .name = xname, \ 3278 .index = xindex, \ 3279 .info = snd_hdspm_info_input_select, \ 3280 .get = snd_hdspm_get_input_select, \ 3281 .put = snd_hdspm_put_input_select \ 3282 } 3283 3284 static int hdspm_input_select(struct hdspm * hdspm) 3285 { 3286 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3287 } 3288 3289 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3290 { 3291 if (out) 3292 hdspm->control_register |= HDSPM_InputSelect0; 3293 else 3294 hdspm->control_register &= ~HDSPM_InputSelect0; 3295 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3296 3297 return 0; 3298 } 3299 3300 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3301 struct snd_ctl_elem_info *uinfo) 3302 { 3303 static const char *const texts[] = { "optical", "coaxial" }; 3304 ENUMERATED_CTL_INFO(uinfo, texts); 3305 return 0; 3306 } 3307 3308 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3309 struct snd_ctl_elem_value *ucontrol) 3310 { 3311 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3312 3313 spin_lock_irq(&hdspm->lock); 3314 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3315 spin_unlock_irq(&hdspm->lock); 3316 return 0; 3317 } 3318 3319 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3320 struct snd_ctl_elem_value *ucontrol) 3321 { 3322 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3323 int change; 3324 unsigned int val; 3325 3326 if (!snd_hdspm_use_is_exclusive(hdspm)) 3327 return -EBUSY; 3328 val = ucontrol->value.integer.value[0] & 1; 3329 spin_lock_irq(&hdspm->lock); 3330 change = (int) val != hdspm_input_select(hdspm); 3331 hdspm_set_input_select(hdspm, val); 3332 spin_unlock_irq(&hdspm->lock); 3333 return change; 3334 } 3335 3336 3337 #define HDSPM_DS_WIRE(xname, xindex) \ 3338 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3339 .name = xname, \ 3340 .index = xindex, \ 3341 .info = snd_hdspm_info_ds_wire, \ 3342 .get = snd_hdspm_get_ds_wire, \ 3343 .put = snd_hdspm_put_ds_wire \ 3344 } 3345 3346 static int hdspm_ds_wire(struct hdspm * hdspm) 3347 { 3348 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3349 } 3350 3351 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3352 { 3353 if (ds) 3354 hdspm->control_register |= HDSPM_DS_DoubleWire; 3355 else 3356 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3357 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3358 3359 return 0; 3360 } 3361 3362 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3363 struct snd_ctl_elem_info *uinfo) 3364 { 3365 static const char *const texts[] = { "Single", "Double" }; 3366 ENUMERATED_CTL_INFO(uinfo, texts); 3367 return 0; 3368 } 3369 3370 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3371 struct snd_ctl_elem_value *ucontrol) 3372 { 3373 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3374 3375 spin_lock_irq(&hdspm->lock); 3376 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3377 spin_unlock_irq(&hdspm->lock); 3378 return 0; 3379 } 3380 3381 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3382 struct snd_ctl_elem_value *ucontrol) 3383 { 3384 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3385 int change; 3386 unsigned int val; 3387 3388 if (!snd_hdspm_use_is_exclusive(hdspm)) 3389 return -EBUSY; 3390 val = ucontrol->value.integer.value[0] & 1; 3391 spin_lock_irq(&hdspm->lock); 3392 change = (int) val != hdspm_ds_wire(hdspm); 3393 hdspm_set_ds_wire(hdspm, val); 3394 spin_unlock_irq(&hdspm->lock); 3395 return change; 3396 } 3397 3398 3399 #define HDSPM_QS_WIRE(xname, xindex) \ 3400 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3401 .name = xname, \ 3402 .index = xindex, \ 3403 .info = snd_hdspm_info_qs_wire, \ 3404 .get = snd_hdspm_get_qs_wire, \ 3405 .put = snd_hdspm_put_qs_wire \ 3406 } 3407 3408 static int hdspm_qs_wire(struct hdspm * hdspm) 3409 { 3410 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3411 return 1; 3412 if (hdspm->control_register & HDSPM_QS_QuadWire) 3413 return 2; 3414 return 0; 3415 } 3416 3417 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3418 { 3419 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3420 switch (mode) { 3421 case 0: 3422 break; 3423 case 1: 3424 hdspm->control_register |= HDSPM_QS_DoubleWire; 3425 break; 3426 case 2: 3427 hdspm->control_register |= HDSPM_QS_QuadWire; 3428 break; 3429 } 3430 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3431 3432 return 0; 3433 } 3434 3435 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3436 struct snd_ctl_elem_info *uinfo) 3437 { 3438 static const char *const texts[] = { "Single", "Double", "Quad" }; 3439 ENUMERATED_CTL_INFO(uinfo, texts); 3440 return 0; 3441 } 3442 3443 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3444 struct snd_ctl_elem_value *ucontrol) 3445 { 3446 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3447 3448 spin_lock_irq(&hdspm->lock); 3449 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3450 spin_unlock_irq(&hdspm->lock); 3451 return 0; 3452 } 3453 3454 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3455 struct snd_ctl_elem_value *ucontrol) 3456 { 3457 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3458 int change; 3459 int val; 3460 3461 if (!snd_hdspm_use_is_exclusive(hdspm)) 3462 return -EBUSY; 3463 val = ucontrol->value.integer.value[0]; 3464 if (val < 0) 3465 val = 0; 3466 if (val > 2) 3467 val = 2; 3468 spin_lock_irq(&hdspm->lock); 3469 change = val != hdspm_qs_wire(hdspm); 3470 hdspm_set_qs_wire(hdspm, val); 3471 spin_unlock_irq(&hdspm->lock); 3472 return change; 3473 } 3474 3475 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \ 3476 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3477 .name = xname, \ 3478 .private_value = xindex, \ 3479 .info = snd_hdspm_info_tristate, \ 3480 .get = snd_hdspm_get_tristate, \ 3481 .put = snd_hdspm_put_tristate \ 3482 } 3483 3484 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask) 3485 { 3486 u32 reg = hdspm->settings_register & (regmask * 3); 3487 return reg / regmask; 3488 } 3489 3490 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask) 3491 { 3492 hdspm->settings_register &= ~(regmask * 3); 3493 hdspm->settings_register |= (regmask * mode); 3494 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 3495 3496 return 0; 3497 } 3498 3499 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol, 3500 struct snd_ctl_elem_info *uinfo) 3501 { 3502 u32 regmask = kcontrol->private_value; 3503 3504 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" }; 3505 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" }; 3506 3507 switch (regmask) { 3508 case HDSPM_c0_Input0: 3509 ENUMERATED_CTL_INFO(uinfo, texts_spdif); 3510 break; 3511 default: 3512 ENUMERATED_CTL_INFO(uinfo, texts_levels); 3513 break; 3514 } 3515 return 0; 3516 } 3517 3518 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol, 3519 struct snd_ctl_elem_value *ucontrol) 3520 { 3521 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3522 u32 regmask = kcontrol->private_value; 3523 3524 spin_lock_irq(&hdspm->lock); 3525 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask); 3526 spin_unlock_irq(&hdspm->lock); 3527 return 0; 3528 } 3529 3530 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol, 3531 struct snd_ctl_elem_value *ucontrol) 3532 { 3533 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3534 u32 regmask = kcontrol->private_value; 3535 int change; 3536 int val; 3537 3538 if (!snd_hdspm_use_is_exclusive(hdspm)) 3539 return -EBUSY; 3540 val = ucontrol->value.integer.value[0]; 3541 if (val < 0) 3542 val = 0; 3543 if (val > 2) 3544 val = 2; 3545 3546 spin_lock_irq(&hdspm->lock); 3547 change = val != hdspm_tristate(hdspm, regmask); 3548 hdspm_set_tristate(hdspm, val, regmask); 3549 spin_unlock_irq(&hdspm->lock); 3550 return change; 3551 } 3552 3553 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3554 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3555 .name = xname, \ 3556 .index = xindex, \ 3557 .info = snd_hdspm_info_madi_speedmode, \ 3558 .get = snd_hdspm_get_madi_speedmode, \ 3559 .put = snd_hdspm_put_madi_speedmode \ 3560 } 3561 3562 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3563 { 3564 if (hdspm->control_register & HDSPM_QuadSpeed) 3565 return 2; 3566 if (hdspm->control_register & HDSPM_DoubleSpeed) 3567 return 1; 3568 return 0; 3569 } 3570 3571 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3572 { 3573 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3574 switch (mode) { 3575 case 0: 3576 break; 3577 case 1: 3578 hdspm->control_register |= HDSPM_DoubleSpeed; 3579 break; 3580 case 2: 3581 hdspm->control_register |= HDSPM_QuadSpeed; 3582 break; 3583 } 3584 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3585 3586 return 0; 3587 } 3588 3589 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3590 struct snd_ctl_elem_info *uinfo) 3591 { 3592 static const char *const texts[] = { "Single", "Double", "Quad" }; 3593 ENUMERATED_CTL_INFO(uinfo, texts); 3594 return 0; 3595 } 3596 3597 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3598 struct snd_ctl_elem_value *ucontrol) 3599 { 3600 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3601 3602 spin_lock_irq(&hdspm->lock); 3603 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3604 spin_unlock_irq(&hdspm->lock); 3605 return 0; 3606 } 3607 3608 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3609 struct snd_ctl_elem_value *ucontrol) 3610 { 3611 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3612 int change; 3613 int val; 3614 3615 if (!snd_hdspm_use_is_exclusive(hdspm)) 3616 return -EBUSY; 3617 val = ucontrol->value.integer.value[0]; 3618 if (val < 0) 3619 val = 0; 3620 if (val > 2) 3621 val = 2; 3622 spin_lock_irq(&hdspm->lock); 3623 change = val != hdspm_madi_speedmode(hdspm); 3624 hdspm_set_madi_speedmode(hdspm, val); 3625 spin_unlock_irq(&hdspm->lock); 3626 return change; 3627 } 3628 3629 #define HDSPM_MIXER(xname, xindex) \ 3630 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3631 .name = xname, \ 3632 .index = xindex, \ 3633 .device = 0, \ 3634 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3635 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3636 .info = snd_hdspm_info_mixer, \ 3637 .get = snd_hdspm_get_mixer, \ 3638 .put = snd_hdspm_put_mixer \ 3639 } 3640 3641 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3642 struct snd_ctl_elem_info *uinfo) 3643 { 3644 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3645 uinfo->count = 3; 3646 uinfo->value.integer.min = 0; 3647 uinfo->value.integer.max = 65535; 3648 uinfo->value.integer.step = 1; 3649 return 0; 3650 } 3651 3652 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3653 struct snd_ctl_elem_value *ucontrol) 3654 { 3655 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3656 int source; 3657 int destination; 3658 3659 source = ucontrol->value.integer.value[0]; 3660 if (source < 0) 3661 source = 0; 3662 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3663 source = 2 * HDSPM_MAX_CHANNELS - 1; 3664 3665 destination = ucontrol->value.integer.value[1]; 3666 if (destination < 0) 3667 destination = 0; 3668 else if (destination >= HDSPM_MAX_CHANNELS) 3669 destination = HDSPM_MAX_CHANNELS - 1; 3670 3671 spin_lock_irq(&hdspm->lock); 3672 if (source >= HDSPM_MAX_CHANNELS) 3673 ucontrol->value.integer.value[2] = 3674 hdspm_read_pb_gain(hdspm, destination, 3675 source - HDSPM_MAX_CHANNELS); 3676 else 3677 ucontrol->value.integer.value[2] = 3678 hdspm_read_in_gain(hdspm, destination, source); 3679 3680 spin_unlock_irq(&hdspm->lock); 3681 3682 return 0; 3683 } 3684 3685 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3686 struct snd_ctl_elem_value *ucontrol) 3687 { 3688 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3689 int change; 3690 int source; 3691 int destination; 3692 int gain; 3693 3694 if (!snd_hdspm_use_is_exclusive(hdspm)) 3695 return -EBUSY; 3696 3697 source = ucontrol->value.integer.value[0]; 3698 destination = ucontrol->value.integer.value[1]; 3699 3700 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3701 return -1; 3702 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3703 return -1; 3704 3705 gain = ucontrol->value.integer.value[2]; 3706 3707 spin_lock_irq(&hdspm->lock); 3708 3709 if (source >= HDSPM_MAX_CHANNELS) 3710 change = gain != hdspm_read_pb_gain(hdspm, destination, 3711 source - 3712 HDSPM_MAX_CHANNELS); 3713 else 3714 change = gain != hdspm_read_in_gain(hdspm, destination, 3715 source); 3716 3717 if (change) { 3718 if (source >= HDSPM_MAX_CHANNELS) 3719 hdspm_write_pb_gain(hdspm, destination, 3720 source - HDSPM_MAX_CHANNELS, 3721 gain); 3722 else 3723 hdspm_write_in_gain(hdspm, destination, source, 3724 gain); 3725 } 3726 spin_unlock_irq(&hdspm->lock); 3727 3728 return change; 3729 } 3730 3731 /* The simple mixer control(s) provide gain control for the 3732 basic 1:1 mappings of playback streams to output 3733 streams. 3734 */ 3735 3736 #define HDSPM_PLAYBACK_MIXER \ 3737 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3738 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3739 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3740 .info = snd_hdspm_info_playback_mixer, \ 3741 .get = snd_hdspm_get_playback_mixer, \ 3742 .put = snd_hdspm_put_playback_mixer \ 3743 } 3744 3745 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3746 struct snd_ctl_elem_info *uinfo) 3747 { 3748 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3749 uinfo->count = 1; 3750 uinfo->value.integer.min = 0; 3751 uinfo->value.integer.max = 64; 3752 uinfo->value.integer.step = 1; 3753 return 0; 3754 } 3755 3756 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3757 struct snd_ctl_elem_value *ucontrol) 3758 { 3759 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3760 int channel; 3761 3762 channel = ucontrol->id.index - 1; 3763 3764 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3765 return -EINVAL; 3766 3767 spin_lock_irq(&hdspm->lock); 3768 ucontrol->value.integer.value[0] = 3769 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3770 spin_unlock_irq(&hdspm->lock); 3771 3772 return 0; 3773 } 3774 3775 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3776 struct snd_ctl_elem_value *ucontrol) 3777 { 3778 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3779 int change; 3780 int channel; 3781 int gain; 3782 3783 if (!snd_hdspm_use_is_exclusive(hdspm)) 3784 return -EBUSY; 3785 3786 channel = ucontrol->id.index - 1; 3787 3788 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3789 return -EINVAL; 3790 3791 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3792 3793 spin_lock_irq(&hdspm->lock); 3794 change = 3795 gain != hdspm_read_pb_gain(hdspm, channel, 3796 channel); 3797 if (change) 3798 hdspm_write_pb_gain(hdspm, channel, channel, 3799 gain); 3800 spin_unlock_irq(&hdspm->lock); 3801 return change; 3802 } 3803 3804 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3805 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3806 .name = xname, \ 3807 .private_value = xindex, \ 3808 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3809 .info = snd_hdspm_info_sync_check, \ 3810 .get = snd_hdspm_get_sync_check \ 3811 } 3812 3813 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3814 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3815 .name = xname, \ 3816 .private_value = xindex, \ 3817 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3818 .info = snd_hdspm_tco_info_lock_check, \ 3819 .get = snd_hdspm_get_sync_check \ 3820 } 3821 3822 3823 3824 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3825 struct snd_ctl_elem_info *uinfo) 3826 { 3827 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3828 ENUMERATED_CTL_INFO(uinfo, texts); 3829 return 0; 3830 } 3831 3832 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3833 struct snd_ctl_elem_info *uinfo) 3834 { 3835 static const char *const texts[] = { "No Lock", "Lock" }; 3836 ENUMERATED_CTL_INFO(uinfo, texts); 3837 return 0; 3838 } 3839 3840 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3841 { 3842 int status, status2; 3843 3844 switch (hdspm->io_type) { 3845 case AES32: 3846 status = hdspm_read(hdspm, HDSPM_statusRegister); 3847 if (status & HDSPM_AES32_wcLock) { 3848 if (status & HDSPM_AES32_wcSync) 3849 return 2; 3850 else 3851 return 1; 3852 } 3853 return 0; 3854 break; 3855 3856 case MADI: 3857 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3858 if (status2 & HDSPM_wcLock) { 3859 if (status2 & HDSPM_wcSync) 3860 return 2; 3861 else 3862 return 1; 3863 } 3864 return 0; 3865 break; 3866 3867 case RayDAT: 3868 case AIO: 3869 status = hdspm_read(hdspm, HDSPM_statusRegister); 3870 3871 if (status & 0x2000000) 3872 return 2; 3873 else if (status & 0x1000000) 3874 return 1; 3875 return 0; 3876 3877 break; 3878 3879 case MADIface: 3880 break; 3881 } 3882 3883 3884 return 3; 3885 } 3886 3887 3888 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3889 { 3890 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3891 if (status & HDSPM_madiLock) { 3892 if (status & HDSPM_madiSync) 3893 return 2; 3894 else 3895 return 1; 3896 } 3897 return 0; 3898 } 3899 3900 3901 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3902 { 3903 int status, lock, sync; 3904 3905 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3906 3907 lock = (status & (0x1<<idx)) ? 1 : 0; 3908 sync = (status & (0x100<<idx)) ? 1 : 0; 3909 3910 if (lock && sync) 3911 return 2; 3912 else if (lock) 3913 return 1; 3914 return 0; 3915 } 3916 3917 3918 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3919 { 3920 int status, lock = 0, sync = 0; 3921 3922 switch (hdspm->io_type) { 3923 case RayDAT: 3924 case AIO: 3925 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3926 lock = (status & 0x400) ? 1 : 0; 3927 sync = (status & 0x800) ? 1 : 0; 3928 break; 3929 3930 case MADI: 3931 status = hdspm_read(hdspm, HDSPM_statusRegister); 3932 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3933 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3934 break; 3935 3936 case AES32: 3937 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3938 lock = (status & 0x100000) ? 1 : 0; 3939 sync = (status & 0x200000) ? 1 : 0; 3940 break; 3941 3942 case MADIface: 3943 break; 3944 } 3945 3946 if (lock && sync) 3947 return 2; 3948 else if (lock) 3949 return 1; 3950 3951 return 0; 3952 } 3953 3954 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3955 { 3956 int status2, lock, sync; 3957 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3958 3959 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3960 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3961 3962 if (sync) 3963 return 2; 3964 else if (lock) 3965 return 1; 3966 return 0; 3967 } 3968 3969 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3970 { 3971 u32 status; 3972 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3973 3974 return (status & mask) ? 1 : 0; 3975 } 3976 3977 3978 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3979 { 3980 int status; 3981 3982 if (hdspm->tco) { 3983 switch (hdspm->io_type) { 3984 case MADI: 3985 status = hdspm_read(hdspm, HDSPM_statusRegister); 3986 if (status & HDSPM_tcoLockMadi) { 3987 if (status & HDSPM_tcoSync) 3988 return 2; 3989 else 3990 return 1; 3991 } 3992 return 0; 3993 case AES32: 3994 status = hdspm_read(hdspm, HDSPM_statusRegister); 3995 if (status & HDSPM_tcoLockAes) { 3996 if (status & HDSPM_tcoSync) 3997 return 2; 3998 else 3999 return 1; 4000 } 4001 return 0; 4002 case RayDAT: 4003 case AIO: 4004 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 4005 4006 if (status & 0x8000000) 4007 return 2; /* Sync */ 4008 if (status & 0x4000000) 4009 return 1; /* Lock */ 4010 return 0; /* No signal */ 4011 4012 default: 4013 break; 4014 } 4015 } 4016 4017 return 3; /* N/A */ 4018 } 4019 4020 4021 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 4022 struct snd_ctl_elem_value *ucontrol) 4023 { 4024 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4025 int val = -1; 4026 4027 switch (hdspm->io_type) { 4028 case RayDAT: 4029 switch (kcontrol->private_value) { 4030 case 0: /* WC */ 4031 val = hdspm_wc_sync_check(hdspm); break; 4032 case 7: /* TCO */ 4033 val = hdspm_tco_sync_check(hdspm); break; 4034 case 8: /* SYNC IN */ 4035 val = hdspm_sync_in_sync_check(hdspm); break; 4036 default: 4037 val = hdspm_s1_sync_check(hdspm, 4038 kcontrol->private_value-1); 4039 } 4040 break; 4041 4042 case AIO: 4043 switch (kcontrol->private_value) { 4044 case 0: /* WC */ 4045 val = hdspm_wc_sync_check(hdspm); break; 4046 case 4: /* TCO */ 4047 val = hdspm_tco_sync_check(hdspm); break; 4048 case 5: /* SYNC IN */ 4049 val = hdspm_sync_in_sync_check(hdspm); break; 4050 default: 4051 val = hdspm_s1_sync_check(hdspm, 4052 kcontrol->private_value-1); 4053 } 4054 break; 4055 4056 case MADI: 4057 switch (kcontrol->private_value) { 4058 case 0: /* WC */ 4059 val = hdspm_wc_sync_check(hdspm); break; 4060 case 1: /* MADI */ 4061 val = hdspm_madi_sync_check(hdspm); break; 4062 case 2: /* TCO */ 4063 val = hdspm_tco_sync_check(hdspm); break; 4064 case 3: /* SYNC_IN */ 4065 val = hdspm_sync_in_sync_check(hdspm); break; 4066 } 4067 break; 4068 4069 case MADIface: 4070 val = hdspm_madi_sync_check(hdspm); /* MADI */ 4071 break; 4072 4073 case AES32: 4074 switch (kcontrol->private_value) { 4075 case 0: /* WC */ 4076 val = hdspm_wc_sync_check(hdspm); break; 4077 case 9: /* TCO */ 4078 val = hdspm_tco_sync_check(hdspm); break; 4079 case 10 /* SYNC IN */: 4080 val = hdspm_sync_in_sync_check(hdspm); break; 4081 default: /* AES1 to AES8 */ 4082 val = hdspm_aes_sync_check(hdspm, 4083 kcontrol->private_value-1); 4084 } 4085 break; 4086 4087 } 4088 4089 if (hdspm->tco) { 4090 switch (kcontrol->private_value) { 4091 case 11: 4092 /* Check TCO for lock state of its current input */ 4093 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 4094 break; 4095 case 12: 4096 /* Check TCO for valid time code on LTC input. */ 4097 val = hdspm_tco_input_check(hdspm, 4098 HDSPM_TCO1_LTC_Input_valid); 4099 break; 4100 default: 4101 break; 4102 } 4103 } 4104 4105 if (-1 == val) 4106 val = 3; 4107 4108 ucontrol->value.enumerated.item[0] = val; 4109 return 0; 4110 } 4111 4112 4113 4114 /* 4115 * TCO controls 4116 */ 4117 static void hdspm_tco_write(struct hdspm *hdspm) 4118 { 4119 unsigned int tc[4] = { 0, 0, 0, 0}; 4120 4121 switch (hdspm->tco->input) { 4122 case 0: 4123 tc[2] |= HDSPM_TCO2_set_input_MSB; 4124 break; 4125 case 1: 4126 tc[2] |= HDSPM_TCO2_set_input_LSB; 4127 break; 4128 default: 4129 break; 4130 } 4131 4132 switch (hdspm->tco->framerate) { 4133 case 1: 4134 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 4135 break; 4136 case 2: 4137 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 4138 break; 4139 case 3: 4140 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 4141 HDSPM_TCO1_set_drop_frame_flag; 4142 break; 4143 case 4: 4144 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4145 HDSPM_TCO1_LTC_Format_MSB; 4146 break; 4147 case 5: 4148 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4149 HDSPM_TCO1_LTC_Format_MSB + 4150 HDSPM_TCO1_set_drop_frame_flag; 4151 break; 4152 default: 4153 break; 4154 } 4155 4156 switch (hdspm->tco->wordclock) { 4157 case 1: 4158 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4159 break; 4160 case 2: 4161 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4162 break; 4163 default: 4164 break; 4165 } 4166 4167 switch (hdspm->tco->samplerate) { 4168 case 1: 4169 tc[2] |= HDSPM_TCO2_set_freq; 4170 break; 4171 case 2: 4172 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4173 break; 4174 default: 4175 break; 4176 } 4177 4178 switch (hdspm->tco->pull) { 4179 case 1: 4180 tc[2] |= HDSPM_TCO2_set_pull_up; 4181 break; 4182 case 2: 4183 tc[2] |= HDSPM_TCO2_set_pull_down; 4184 break; 4185 case 3: 4186 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4187 break; 4188 case 4: 4189 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4190 break; 4191 default: 4192 break; 4193 } 4194 4195 if (1 == hdspm->tco->term) { 4196 tc[2] |= HDSPM_TCO2_set_term_75R; 4197 } 4198 4199 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4200 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4201 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4202 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4203 } 4204 4205 4206 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4207 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4208 .name = xname, \ 4209 .index = xindex, \ 4210 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4211 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4212 .info = snd_hdspm_info_tco_sample_rate, \ 4213 .get = snd_hdspm_get_tco_sample_rate, \ 4214 .put = snd_hdspm_put_tco_sample_rate \ 4215 } 4216 4217 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4218 struct snd_ctl_elem_info *uinfo) 4219 { 4220 /* TODO freq from app could be supported here, see tco->samplerate */ 4221 static const char *const texts[] = { "44.1 kHz", "48 kHz" }; 4222 ENUMERATED_CTL_INFO(uinfo, texts); 4223 return 0; 4224 } 4225 4226 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4227 struct snd_ctl_elem_value *ucontrol) 4228 { 4229 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4230 4231 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4232 4233 return 0; 4234 } 4235 4236 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4237 struct snd_ctl_elem_value *ucontrol) 4238 { 4239 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4240 4241 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4242 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4243 4244 hdspm_tco_write(hdspm); 4245 4246 return 1; 4247 } 4248 4249 return 0; 4250 } 4251 4252 4253 #define HDSPM_TCO_PULL(xname, xindex) \ 4254 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4255 .name = xname, \ 4256 .index = xindex, \ 4257 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4258 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4259 .info = snd_hdspm_info_tco_pull, \ 4260 .get = snd_hdspm_get_tco_pull, \ 4261 .put = snd_hdspm_put_tco_pull \ 4262 } 4263 4264 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4265 struct snd_ctl_elem_info *uinfo) 4266 { 4267 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %", 4268 "+ 4 %", "- 4 %" }; 4269 ENUMERATED_CTL_INFO(uinfo, texts); 4270 return 0; 4271 } 4272 4273 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4274 struct snd_ctl_elem_value *ucontrol) 4275 { 4276 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4277 4278 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4279 4280 return 0; 4281 } 4282 4283 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4284 struct snd_ctl_elem_value *ucontrol) 4285 { 4286 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4287 4288 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4289 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4290 4291 hdspm_tco_write(hdspm); 4292 4293 return 1; 4294 } 4295 4296 return 0; 4297 } 4298 4299 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4300 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4301 .name = xname, \ 4302 .index = xindex, \ 4303 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4304 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4305 .info = snd_hdspm_info_tco_wck_conversion, \ 4306 .get = snd_hdspm_get_tco_wck_conversion, \ 4307 .put = snd_hdspm_put_tco_wck_conversion \ 4308 } 4309 4310 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4311 struct snd_ctl_elem_info *uinfo) 4312 { 4313 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4314 ENUMERATED_CTL_INFO(uinfo, texts); 4315 return 0; 4316 } 4317 4318 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4319 struct snd_ctl_elem_value *ucontrol) 4320 { 4321 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4322 4323 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4324 4325 return 0; 4326 } 4327 4328 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4329 struct snd_ctl_elem_value *ucontrol) 4330 { 4331 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4332 4333 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4334 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4335 4336 hdspm_tco_write(hdspm); 4337 4338 return 1; 4339 } 4340 4341 return 0; 4342 } 4343 4344 4345 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4346 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4347 .name = xname, \ 4348 .index = xindex, \ 4349 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4350 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4351 .info = snd_hdspm_info_tco_frame_rate, \ 4352 .get = snd_hdspm_get_tco_frame_rate, \ 4353 .put = snd_hdspm_put_tco_frame_rate \ 4354 } 4355 4356 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4357 struct snd_ctl_elem_info *uinfo) 4358 { 4359 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps", 4360 "29.97 dfps", "30 fps", "30 dfps" }; 4361 ENUMERATED_CTL_INFO(uinfo, texts); 4362 return 0; 4363 } 4364 4365 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4366 struct snd_ctl_elem_value *ucontrol) 4367 { 4368 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4369 4370 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4371 4372 return 0; 4373 } 4374 4375 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4376 struct snd_ctl_elem_value *ucontrol) 4377 { 4378 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4379 4380 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4381 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4382 4383 hdspm_tco_write(hdspm); 4384 4385 return 1; 4386 } 4387 4388 return 0; 4389 } 4390 4391 4392 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4393 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4394 .name = xname, \ 4395 .index = xindex, \ 4396 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4397 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4398 .info = snd_hdspm_info_tco_sync_source, \ 4399 .get = snd_hdspm_get_tco_sync_source, \ 4400 .put = snd_hdspm_put_tco_sync_source \ 4401 } 4402 4403 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4404 struct snd_ctl_elem_info *uinfo) 4405 { 4406 static const char *const texts[] = { "LTC", "Video", "WCK" }; 4407 ENUMERATED_CTL_INFO(uinfo, texts); 4408 return 0; 4409 } 4410 4411 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4412 struct snd_ctl_elem_value *ucontrol) 4413 { 4414 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4415 4416 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4417 4418 return 0; 4419 } 4420 4421 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4422 struct snd_ctl_elem_value *ucontrol) 4423 { 4424 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4425 4426 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4427 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4428 4429 hdspm_tco_write(hdspm); 4430 4431 return 1; 4432 } 4433 4434 return 0; 4435 } 4436 4437 4438 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4439 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4440 .name = xname, \ 4441 .index = xindex, \ 4442 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4443 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4444 .info = snd_hdspm_info_tco_word_term, \ 4445 .get = snd_hdspm_get_tco_word_term, \ 4446 .put = snd_hdspm_put_tco_word_term \ 4447 } 4448 4449 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4450 struct snd_ctl_elem_info *uinfo) 4451 { 4452 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4453 uinfo->count = 1; 4454 uinfo->value.integer.min = 0; 4455 uinfo->value.integer.max = 1; 4456 4457 return 0; 4458 } 4459 4460 4461 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4462 struct snd_ctl_elem_value *ucontrol) 4463 { 4464 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4465 4466 ucontrol->value.integer.value[0] = hdspm->tco->term; 4467 4468 return 0; 4469 } 4470 4471 4472 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4473 struct snd_ctl_elem_value *ucontrol) 4474 { 4475 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4476 4477 if (hdspm->tco->term != ucontrol->value.integer.value[0]) { 4478 hdspm->tco->term = ucontrol->value.integer.value[0]; 4479 4480 hdspm_tco_write(hdspm); 4481 4482 return 1; 4483 } 4484 4485 return 0; 4486 } 4487 4488 4489 4490 4491 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4492 HDSPM_MIXER("Mixer", 0), 4493 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4494 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4495 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4496 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4497 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4498 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4499 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4500 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4501 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4502 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4503 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4504 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4505 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4506 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4507 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4508 HDSPM_INPUT_SELECT("Input Select", 0), 4509 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4510 }; 4511 4512 4513 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4514 HDSPM_MIXER("Mixer", 0), 4515 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4516 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4517 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4518 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4519 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4520 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4521 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4522 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4523 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4524 }; 4525 4526 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4527 HDSPM_MIXER("Mixer", 0), 4528 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4529 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4530 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4531 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4532 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4533 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4534 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4535 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4536 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4537 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4538 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4539 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4540 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4541 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4542 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4543 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4544 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5), 4545 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0), 4546 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt), 4547 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4548 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1), 4549 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db), 4550 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48), 4551 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0), 4552 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0), 4553 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0) 4554 4555 /* 4556 HDSPM_INPUT_SELECT("Input Select", 0), 4557 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4558 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4559 HDSPM_SPDIF_IN("SPDIF In", 0); 4560 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4561 HDSPM_INPUT_LEVEL("Input Level", 0); 4562 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4563 HDSPM_PHONES("Phones", 0); 4564 */ 4565 }; 4566 4567 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4568 HDSPM_MIXER("Mixer", 0), 4569 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4570 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4571 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4572 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4573 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4574 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4575 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4576 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4577 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4578 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4579 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4580 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4581 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4582 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4583 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4584 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4585 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4586 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4587 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4588 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4589 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4590 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8), 4591 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4592 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48) 4593 }; 4594 4595 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4596 HDSPM_MIXER("Mixer", 0), 4597 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4598 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4599 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4600 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4601 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4602 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11), 4603 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4604 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4605 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4606 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4607 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4608 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4609 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4610 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4611 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4612 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4613 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4614 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4615 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4616 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4617 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4618 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4619 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4620 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4621 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4622 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4623 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4624 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4625 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4626 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4627 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4628 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4629 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4630 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4631 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4632 }; 4633 4634 4635 4636 /* Control elements for the optional TCO module */ 4637 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4638 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4639 HDSPM_TCO_PULL("TCO Pull", 0), 4640 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4641 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4642 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4643 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4644 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4645 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4646 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0), 4647 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0) 4648 }; 4649 4650 4651 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4652 4653 4654 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4655 { 4656 int i; 4657 4658 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4659 if (hdspm->system_sample_rate > 48000) { 4660 hdspm->playback_mixer_ctls[i]->vd[0].access = 4661 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4662 SNDRV_CTL_ELEM_ACCESS_READ | 4663 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4664 } else { 4665 hdspm->playback_mixer_ctls[i]->vd[0].access = 4666 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4667 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4668 } 4669 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4670 SNDRV_CTL_EVENT_MASK_INFO, 4671 &hdspm->playback_mixer_ctls[i]->id); 4672 } 4673 4674 return 0; 4675 } 4676 4677 4678 static int snd_hdspm_create_controls(struct snd_card *card, 4679 struct hdspm *hdspm) 4680 { 4681 unsigned int idx, limit; 4682 int err; 4683 struct snd_kcontrol *kctl; 4684 struct snd_kcontrol_new *list = NULL; 4685 4686 switch (hdspm->io_type) { 4687 case MADI: 4688 list = snd_hdspm_controls_madi; 4689 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4690 break; 4691 case MADIface: 4692 list = snd_hdspm_controls_madiface; 4693 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4694 break; 4695 case AIO: 4696 list = snd_hdspm_controls_aio; 4697 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4698 break; 4699 case RayDAT: 4700 list = snd_hdspm_controls_raydat; 4701 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4702 break; 4703 case AES32: 4704 list = snd_hdspm_controls_aes32; 4705 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4706 break; 4707 } 4708 4709 if (list) { 4710 for (idx = 0; idx < limit; idx++) { 4711 err = snd_ctl_add(card, 4712 snd_ctl_new1(&list[idx], hdspm)); 4713 if (err < 0) 4714 return err; 4715 } 4716 } 4717 4718 4719 /* create simple 1:1 playback mixer controls */ 4720 snd_hdspm_playback_mixer.name = "Chn"; 4721 if (hdspm->system_sample_rate >= 128000) { 4722 limit = hdspm->qs_out_channels; 4723 } else if (hdspm->system_sample_rate >= 64000) { 4724 limit = hdspm->ds_out_channels; 4725 } else { 4726 limit = hdspm->ss_out_channels; 4727 } 4728 for (idx = 0; idx < limit; ++idx) { 4729 snd_hdspm_playback_mixer.index = idx + 1; 4730 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4731 err = snd_ctl_add(card, kctl); 4732 if (err < 0) 4733 return err; 4734 hdspm->playback_mixer_ctls[idx] = kctl; 4735 } 4736 4737 4738 if (hdspm->tco) { 4739 /* add tco control elements */ 4740 list = snd_hdspm_controls_tco; 4741 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4742 for (idx = 0; idx < limit; idx++) { 4743 err = snd_ctl_add(card, 4744 snd_ctl_new1(&list[idx], hdspm)); 4745 if (err < 0) 4746 return err; 4747 } 4748 } 4749 4750 return 0; 4751 } 4752 4753 /*------------------------------------------------------------ 4754 /proc interface 4755 ------------------------------------------------------------*/ 4756 4757 static void 4758 snd_hdspm_proc_read_tco(struct snd_info_entry *entry, 4759 struct snd_info_buffer *buffer) 4760 { 4761 struct hdspm *hdspm = entry->private_data; 4762 unsigned int status, control; 4763 int a, ltc, frames, seconds, minutes, hours; 4764 unsigned int period; 4765 u64 freq_const = 0; 4766 u32 rate; 4767 4768 snd_iprintf(buffer, "--- TCO ---\n"); 4769 4770 status = hdspm_read(hdspm, HDSPM_statusRegister); 4771 control = hdspm->control_register; 4772 4773 4774 if (status & HDSPM_tco_detect) { 4775 snd_iprintf(buffer, "TCO module detected.\n"); 4776 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4777 if (a & HDSPM_TCO1_LTC_Input_valid) { 4778 snd_iprintf(buffer, " LTC valid, "); 4779 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4780 HDSPM_TCO1_LTC_Format_MSB)) { 4781 case 0: 4782 snd_iprintf(buffer, "24 fps, "); 4783 break; 4784 case HDSPM_TCO1_LTC_Format_LSB: 4785 snd_iprintf(buffer, "25 fps, "); 4786 break; 4787 case HDSPM_TCO1_LTC_Format_MSB: 4788 snd_iprintf(buffer, "29.97 fps, "); 4789 break; 4790 default: 4791 snd_iprintf(buffer, "30 fps, "); 4792 break; 4793 } 4794 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4795 snd_iprintf(buffer, "drop frame\n"); 4796 } else { 4797 snd_iprintf(buffer, "full frame\n"); 4798 } 4799 } else { 4800 snd_iprintf(buffer, " no LTC\n"); 4801 } 4802 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4803 snd_iprintf(buffer, " Video: NTSC\n"); 4804 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4805 snd_iprintf(buffer, " Video: PAL\n"); 4806 } else { 4807 snd_iprintf(buffer, " No video\n"); 4808 } 4809 if (a & HDSPM_TCO1_TCO_lock) { 4810 snd_iprintf(buffer, " Sync: lock\n"); 4811 } else { 4812 snd_iprintf(buffer, " Sync: no lock\n"); 4813 } 4814 4815 switch (hdspm->io_type) { 4816 case MADI: 4817 case AES32: 4818 freq_const = 110069313433624ULL; 4819 break; 4820 case RayDAT: 4821 case AIO: 4822 freq_const = 104857600000000ULL; 4823 break; 4824 case MADIface: 4825 break; /* no TCO possible */ 4826 } 4827 4828 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4829 snd_iprintf(buffer, " period: %u\n", period); 4830 4831 4832 /* rate = freq_const/period; */ 4833 rate = div_u64(freq_const, period); 4834 4835 if (control & HDSPM_QuadSpeed) { 4836 rate *= 4; 4837 } else if (control & HDSPM_DoubleSpeed) { 4838 rate *= 2; 4839 } 4840 4841 snd_iprintf(buffer, " Frequency: %u Hz\n", 4842 (unsigned int) rate); 4843 4844 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4845 frames = ltc & 0xF; 4846 ltc >>= 4; 4847 frames += (ltc & 0x3) * 10; 4848 ltc >>= 4; 4849 seconds = ltc & 0xF; 4850 ltc >>= 4; 4851 seconds += (ltc & 0x7) * 10; 4852 ltc >>= 4; 4853 minutes = ltc & 0xF; 4854 ltc >>= 4; 4855 minutes += (ltc & 0x7) * 10; 4856 ltc >>= 4; 4857 hours = ltc & 0xF; 4858 ltc >>= 4; 4859 hours += (ltc & 0x3) * 10; 4860 snd_iprintf(buffer, 4861 " LTC In: %02d:%02d:%02d:%02d\n", 4862 hours, minutes, seconds, frames); 4863 4864 } else { 4865 snd_iprintf(buffer, "No TCO module detected.\n"); 4866 } 4867 } 4868 4869 static void 4870 snd_hdspm_proc_read_madi(struct snd_info_entry *entry, 4871 struct snd_info_buffer *buffer) 4872 { 4873 struct hdspm *hdspm = entry->private_data; 4874 unsigned int status, status2; 4875 4876 char *pref_sync_ref; 4877 char *autosync_ref; 4878 char *system_clock_mode; 4879 int x, x2; 4880 4881 status = hdspm_read(hdspm, HDSPM_statusRegister); 4882 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4883 4884 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4885 hdspm->card_name, hdspm->card->number + 1, 4886 hdspm->firmware_rev, 4887 (status2 & HDSPM_version0) | 4888 (status2 & HDSPM_version1) | (status2 & 4889 HDSPM_version2)); 4890 4891 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4892 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4893 hdspm->serial); 4894 4895 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4896 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4897 4898 snd_iprintf(buffer, "--- System ---\n"); 4899 4900 snd_iprintf(buffer, 4901 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4902 status & HDSPM_audioIRQPending, 4903 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4904 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4905 hdspm->irq_count); 4906 snd_iprintf(buffer, 4907 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4908 "estimated= %ld (bytes)\n", 4909 ((status & HDSPM_BufferID) ? 1 : 0), 4910 (status & HDSPM_BufferPositionMask), 4911 (status & HDSPM_BufferPositionMask) % 4912 (2 * (int)hdspm->period_bytes), 4913 ((status & HDSPM_BufferPositionMask) - 64) % 4914 (2 * (int)hdspm->period_bytes), 4915 (long) hdspm_hw_pointer(hdspm) * 4); 4916 4917 snd_iprintf(buffer, 4918 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4919 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4920 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4921 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4922 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4923 snd_iprintf(buffer, 4924 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4925 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4926 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4927 snd_iprintf(buffer, 4928 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4929 "status2=0x%x\n", 4930 hdspm->control_register, hdspm->control2_register, 4931 status, status2); 4932 4933 4934 snd_iprintf(buffer, "--- Settings ---\n"); 4935 4936 x = hdspm_get_latency(hdspm); 4937 4938 snd_iprintf(buffer, 4939 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4940 x, (unsigned long) hdspm->period_bytes); 4941 4942 snd_iprintf(buffer, "Line out: %s\n", 4943 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4944 4945 snd_iprintf(buffer, 4946 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4947 "Auto Input %s\n", 4948 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4949 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4950 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4951 4952 4953 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4954 system_clock_mode = "AutoSync"; 4955 else 4956 system_clock_mode = "Master"; 4957 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4958 4959 switch (hdspm_pref_sync_ref(hdspm)) { 4960 case HDSPM_SYNC_FROM_WORD: 4961 pref_sync_ref = "Word Clock"; 4962 break; 4963 case HDSPM_SYNC_FROM_MADI: 4964 pref_sync_ref = "MADI Sync"; 4965 break; 4966 case HDSPM_SYNC_FROM_TCO: 4967 pref_sync_ref = "TCO"; 4968 break; 4969 case HDSPM_SYNC_FROM_SYNC_IN: 4970 pref_sync_ref = "Sync In"; 4971 break; 4972 default: 4973 pref_sync_ref = "XXXX Clock"; 4974 break; 4975 } 4976 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4977 pref_sync_ref); 4978 4979 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4980 hdspm->system_sample_rate); 4981 4982 4983 snd_iprintf(buffer, "--- Status:\n"); 4984 4985 x = status & HDSPM_madiSync; 4986 x2 = status2 & HDSPM_wcSync; 4987 4988 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4989 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4990 "NoLock", 4991 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4992 "NoLock"); 4993 4994 switch (hdspm_autosync_ref(hdspm)) { 4995 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4996 autosync_ref = "Sync In"; 4997 break; 4998 case HDSPM_AUTOSYNC_FROM_TCO: 4999 autosync_ref = "TCO"; 5000 break; 5001 case HDSPM_AUTOSYNC_FROM_WORD: 5002 autosync_ref = "Word Clock"; 5003 break; 5004 case HDSPM_AUTOSYNC_FROM_MADI: 5005 autosync_ref = "MADI Sync"; 5006 break; 5007 case HDSPM_AUTOSYNC_FROM_NONE: 5008 autosync_ref = "Input not valid"; 5009 break; 5010 default: 5011 autosync_ref = "---"; 5012 break; 5013 } 5014 snd_iprintf(buffer, 5015 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 5016 autosync_ref, hdspm_external_sample_rate(hdspm), 5017 (status & HDSPM_madiFreqMask) >> 22, 5018 (status2 & HDSPM_wcFreqMask) >> 5); 5019 5020 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 5021 (status & HDSPM_AB_int) ? "Coax" : "Optical", 5022 (status & HDSPM_RX_64ch) ? "64 channels" : 5023 "56 channels"); 5024 5025 /* call readout function for TCO specific status */ 5026 snd_hdspm_proc_read_tco(entry, buffer); 5027 5028 snd_iprintf(buffer, "\n"); 5029 } 5030 5031 static void 5032 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 5033 struct snd_info_buffer *buffer) 5034 { 5035 struct hdspm *hdspm = entry->private_data; 5036 unsigned int status; 5037 unsigned int status2; 5038 unsigned int timecode; 5039 unsigned int wcLock, wcSync; 5040 int pref_syncref; 5041 char *autosync_ref; 5042 int x; 5043 5044 status = hdspm_read(hdspm, HDSPM_statusRegister); 5045 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 5046 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 5047 5048 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 5049 hdspm->card_name, hdspm->card->number + 1, 5050 hdspm->firmware_rev); 5051 5052 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 5053 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 5054 5055 snd_iprintf(buffer, "--- System ---\n"); 5056 5057 snd_iprintf(buffer, 5058 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 5059 status & HDSPM_audioIRQPending, 5060 (status & HDSPM_midi0IRQPending) ? 1 : 0, 5061 (status & HDSPM_midi1IRQPending) ? 1 : 0, 5062 hdspm->irq_count); 5063 snd_iprintf(buffer, 5064 "HW pointer: id = %d, rawptr = %d (%d->%d) " 5065 "estimated= %ld (bytes)\n", 5066 ((status & HDSPM_BufferID) ? 1 : 0), 5067 (status & HDSPM_BufferPositionMask), 5068 (status & HDSPM_BufferPositionMask) % 5069 (2 * (int)hdspm->period_bytes), 5070 ((status & HDSPM_BufferPositionMask) - 64) % 5071 (2 * (int)hdspm->period_bytes), 5072 (long) hdspm_hw_pointer(hdspm) * 4); 5073 5074 snd_iprintf(buffer, 5075 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 5076 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 5077 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 5078 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 5079 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 5080 snd_iprintf(buffer, 5081 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 5082 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 5083 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 5084 snd_iprintf(buffer, 5085 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 5086 "status2=0x%x\n", 5087 hdspm->control_register, hdspm->control2_register, 5088 status, status2); 5089 5090 snd_iprintf(buffer, "--- Settings ---\n"); 5091 5092 x = hdspm_get_latency(hdspm); 5093 5094 snd_iprintf(buffer, 5095 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 5096 x, (unsigned long) hdspm->period_bytes); 5097 5098 snd_iprintf(buffer, "Line out: %s\n", 5099 (hdspm-> 5100 control_register & HDSPM_LineOut) ? "on " : "off"); 5101 5102 snd_iprintf(buffer, 5103 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 5104 (hdspm-> 5105 control_register & HDSPM_clr_tms) ? "on" : "off", 5106 (hdspm-> 5107 control_register & HDSPM_Emphasis) ? "on" : "off", 5108 (hdspm-> 5109 control_register & HDSPM_Dolby) ? "on" : "off"); 5110 5111 5112 pref_syncref = hdspm_pref_sync_ref(hdspm); 5113 if (pref_syncref == 0) 5114 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 5115 else 5116 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 5117 pref_syncref); 5118 5119 snd_iprintf(buffer, "System Clock Frequency: %d\n", 5120 hdspm->system_sample_rate); 5121 5122 snd_iprintf(buffer, "Double speed: %s\n", 5123 hdspm->control_register & HDSPM_DS_DoubleWire? 5124 "Double wire" : "Single wire"); 5125 snd_iprintf(buffer, "Quad speed: %s\n", 5126 hdspm->control_register & HDSPM_QS_DoubleWire? 5127 "Double wire" : 5128 hdspm->control_register & HDSPM_QS_QuadWire? 5129 "Quad wire" : "Single wire"); 5130 5131 snd_iprintf(buffer, "--- Status:\n"); 5132 5133 wcLock = status & HDSPM_AES32_wcLock; 5134 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 5135 5136 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5137 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 5138 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5139 5140 for (x = 0; x < 8; x++) { 5141 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5142 x+1, 5143 (status2 & (HDSPM_LockAES >> x)) ? 5144 "Sync " : "No Lock", 5145 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5146 } 5147 5148 switch (hdspm_autosync_ref(hdspm)) { 5149 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5150 autosync_ref = "None"; break; 5151 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5152 autosync_ref = "Word Clock"; break; 5153 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5154 autosync_ref = "AES1"; break; 5155 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5156 autosync_ref = "AES2"; break; 5157 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5158 autosync_ref = "AES3"; break; 5159 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5160 autosync_ref = "AES4"; break; 5161 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5162 autosync_ref = "AES5"; break; 5163 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5164 autosync_ref = "AES6"; break; 5165 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5166 autosync_ref = "AES7"; break; 5167 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5168 autosync_ref = "AES8"; break; 5169 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 5170 autosync_ref = "TCO"; break; 5171 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN: 5172 autosync_ref = "Sync In"; break; 5173 default: 5174 autosync_ref = "---"; break; 5175 } 5176 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5177 5178 /* call readout function for TCO specific status */ 5179 snd_hdspm_proc_read_tco(entry, buffer); 5180 5181 snd_iprintf(buffer, "\n"); 5182 } 5183 5184 static void 5185 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5186 struct snd_info_buffer *buffer) 5187 { 5188 struct hdspm *hdspm = entry->private_data; 5189 unsigned int status1, status2, status3, i; 5190 unsigned int lock, sync; 5191 5192 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5193 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5194 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5195 5196 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5197 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5198 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5199 5200 5201 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5202 5203 snd_iprintf(buffer, "Clock mode : %s\n", 5204 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5205 snd_iprintf(buffer, "System frequency: %d Hz\n", 5206 hdspm_get_system_sample_rate(hdspm)); 5207 5208 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5209 5210 lock = 0x1; 5211 sync = 0x100; 5212 5213 for (i = 0; i < 8; i++) { 5214 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5215 i, 5216 (status1 & lock) ? 1 : 0, 5217 (status1 & sync) ? 1 : 0, 5218 texts_freq[(status2 >> (i * 4)) & 0xF]); 5219 5220 lock = lock<<1; 5221 sync = sync<<1; 5222 } 5223 5224 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5225 (status1 & 0x1000000) ? 1 : 0, 5226 (status1 & 0x2000000) ? 1 : 0, 5227 texts_freq[(status1 >> 16) & 0xF]); 5228 5229 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5230 (status1 & 0x4000000) ? 1 : 0, 5231 (status1 & 0x8000000) ? 1 : 0, 5232 texts_freq[(status1 >> 20) & 0xF]); 5233 5234 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5235 (status3 & 0x400) ? 1 : 0, 5236 (status3 & 0x800) ? 1 : 0, 5237 texts_freq[(status2 >> 12) & 0xF]); 5238 5239 } 5240 5241 #ifdef CONFIG_SND_DEBUG 5242 static void 5243 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5244 struct snd_info_buffer *buffer) 5245 { 5246 struct hdspm *hdspm = entry->private_data; 5247 5248 int j,i; 5249 5250 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5251 snd_iprintf(buffer, "0x%08X: ", i); 5252 for (j = 0; j < 16; j += 4) 5253 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5254 snd_iprintf(buffer, "\n"); 5255 } 5256 } 5257 #endif 5258 5259 5260 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5261 struct snd_info_buffer *buffer) 5262 { 5263 struct hdspm *hdspm = entry->private_data; 5264 int i; 5265 5266 snd_iprintf(buffer, "# generated by hdspm\n"); 5267 5268 for (i = 0; i < hdspm->max_channels_in; i++) { 5269 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5270 } 5271 } 5272 5273 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5274 struct snd_info_buffer *buffer) 5275 { 5276 struct hdspm *hdspm = entry->private_data; 5277 int i; 5278 5279 snd_iprintf(buffer, "# generated by hdspm\n"); 5280 5281 for (i = 0; i < hdspm->max_channels_out; i++) { 5282 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5283 } 5284 } 5285 5286 5287 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5288 { 5289 struct snd_info_entry *entry; 5290 5291 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5292 switch (hdspm->io_type) { 5293 case AES32: 5294 snd_info_set_text_ops(entry, hdspm, 5295 snd_hdspm_proc_read_aes32); 5296 break; 5297 case MADI: 5298 snd_info_set_text_ops(entry, hdspm, 5299 snd_hdspm_proc_read_madi); 5300 break; 5301 case MADIface: 5302 /* snd_info_set_text_ops(entry, hdspm, 5303 snd_hdspm_proc_read_madiface); */ 5304 break; 5305 case RayDAT: 5306 snd_info_set_text_ops(entry, hdspm, 5307 snd_hdspm_proc_read_raydat); 5308 break; 5309 case AIO: 5310 break; 5311 } 5312 } 5313 5314 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5315 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5316 } 5317 5318 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5319 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5320 } 5321 5322 #ifdef CONFIG_SND_DEBUG 5323 /* debug file to read all hdspm registers */ 5324 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5325 snd_info_set_text_ops(entry, hdspm, 5326 snd_hdspm_proc_read_debug); 5327 #endif 5328 } 5329 5330 /*------------------------------------------------------------ 5331 hdspm intitialize 5332 ------------------------------------------------------------*/ 5333 5334 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5335 { 5336 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5337 hold it (e.g. during module initialization). 5338 */ 5339 5340 /* set defaults: */ 5341 5342 hdspm->settings_register = 0; 5343 5344 switch (hdspm->io_type) { 5345 case MADI: 5346 case MADIface: 5347 hdspm->control_register = 5348 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5349 break; 5350 5351 case RayDAT: 5352 case AIO: 5353 hdspm->settings_register = 0x1 + 0x1000; 5354 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5355 * line_out */ 5356 hdspm->control_register = 5357 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5358 break; 5359 5360 case AES32: 5361 hdspm->control_register = 5362 HDSPM_ClockModeMaster | /* Master Clock Mode on */ 5363 hdspm_encode_latency(7) | /* latency max=8192samples */ 5364 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5365 HDSPM_LineOut | /* Analog output in */ 5366 HDSPM_Professional; /* Professional mode */ 5367 break; 5368 } 5369 5370 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5371 5372 if (AES32 == hdspm->io_type) { 5373 /* No control2 register for AES32 */ 5374 #ifdef SNDRV_BIG_ENDIAN 5375 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5376 #else 5377 hdspm->control2_register = 0; 5378 #endif 5379 5380 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5381 } 5382 hdspm_compute_period_size(hdspm); 5383 5384 /* silence everything */ 5385 5386 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5387 5388 if (hdspm_is_raydat_or_aio(hdspm)) 5389 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5390 5391 /* set a default rate so that the channel map is set up. */ 5392 hdspm_set_rate(hdspm, 48000, 1); 5393 5394 return 0; 5395 } 5396 5397 5398 /*------------------------------------------------------------ 5399 interrupt 5400 ------------------------------------------------------------*/ 5401 5402 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5403 { 5404 struct hdspm *hdspm = (struct hdspm *) dev_id; 5405 unsigned int status; 5406 int i, audio, midi, schedule = 0; 5407 /* cycles_t now; */ 5408 5409 status = hdspm_read(hdspm, HDSPM_statusRegister); 5410 5411 audio = status & HDSPM_audioIRQPending; 5412 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5413 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5414 5415 /* now = get_cycles(); */ 5416 /* 5417 * LAT_2..LAT_0 period counter (win) counter (mac) 5418 * 6 4096 ~256053425 ~514672358 5419 * 5 2048 ~128024983 ~257373821 5420 * 4 1024 ~64023706 ~128718089 5421 * 3 512 ~32005945 ~64385999 5422 * 2 256 ~16003039 ~32260176 5423 * 1 128 ~7998738 ~16194507 5424 * 0 64 ~3998231 ~8191558 5425 */ 5426 /* 5427 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n", 5428 now-hdspm->last_interrupt, status & 0xFFC0); 5429 hdspm->last_interrupt = now; 5430 */ 5431 5432 if (!audio && !midi) 5433 return IRQ_NONE; 5434 5435 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5436 hdspm->irq_count++; 5437 5438 5439 if (audio) { 5440 if (hdspm->capture_substream) 5441 snd_pcm_period_elapsed(hdspm->capture_substream); 5442 5443 if (hdspm->playback_substream) 5444 snd_pcm_period_elapsed(hdspm->playback_substream); 5445 } 5446 5447 if (midi) { 5448 i = 0; 5449 while (i < hdspm->midiPorts) { 5450 if ((hdspm_read(hdspm, 5451 hdspm->midi[i].statusIn) & 0xff) && 5452 (status & hdspm->midi[i].irq)) { 5453 /* we disable interrupts for this input until 5454 * processing is done 5455 */ 5456 hdspm->control_register &= ~hdspm->midi[i].ie; 5457 hdspm_write(hdspm, HDSPM_controlRegister, 5458 hdspm->control_register); 5459 hdspm->midi[i].pending = 1; 5460 schedule = 1; 5461 } 5462 5463 i++; 5464 } 5465 5466 if (schedule) 5467 tasklet_hi_schedule(&hdspm->midi_tasklet); 5468 } 5469 5470 return IRQ_HANDLED; 5471 } 5472 5473 /*------------------------------------------------------------ 5474 pcm interface 5475 ------------------------------------------------------------*/ 5476 5477 5478 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5479 *substream) 5480 { 5481 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5482 return hdspm_hw_pointer(hdspm); 5483 } 5484 5485 5486 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5487 { 5488 struct snd_pcm_runtime *runtime = substream->runtime; 5489 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5490 struct snd_pcm_substream *other; 5491 5492 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5493 other = hdspm->capture_substream; 5494 else 5495 other = hdspm->playback_substream; 5496 5497 if (hdspm->running) 5498 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5499 else 5500 runtime->status->hw_ptr = 0; 5501 if (other) { 5502 struct snd_pcm_substream *s; 5503 struct snd_pcm_runtime *oruntime = other->runtime; 5504 snd_pcm_group_for_each_entry(s, substream) { 5505 if (s == other) { 5506 oruntime->status->hw_ptr = 5507 runtime->status->hw_ptr; 5508 break; 5509 } 5510 } 5511 } 5512 return 0; 5513 } 5514 5515 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5516 struct snd_pcm_hw_params *params) 5517 { 5518 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5519 int err; 5520 int i; 5521 pid_t this_pid; 5522 pid_t other_pid; 5523 5524 spin_lock_irq(&hdspm->lock); 5525 5526 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5527 this_pid = hdspm->playback_pid; 5528 other_pid = hdspm->capture_pid; 5529 } else { 5530 this_pid = hdspm->capture_pid; 5531 other_pid = hdspm->playback_pid; 5532 } 5533 5534 if (other_pid > 0 && this_pid != other_pid) { 5535 5536 /* The other stream is open, and not by the same 5537 task as this one. Make sure that the parameters 5538 that matter are the same. 5539 */ 5540 5541 if (params_rate(params) != hdspm->system_sample_rate) { 5542 spin_unlock_irq(&hdspm->lock); 5543 _snd_pcm_hw_param_setempty(params, 5544 SNDRV_PCM_HW_PARAM_RATE); 5545 return -EBUSY; 5546 } 5547 5548 if (params_period_size(params) != hdspm->period_bytes / 4) { 5549 spin_unlock_irq(&hdspm->lock); 5550 _snd_pcm_hw_param_setempty(params, 5551 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5552 return -EBUSY; 5553 } 5554 5555 } 5556 /* We're fine. */ 5557 spin_unlock_irq(&hdspm->lock); 5558 5559 /* how to make sure that the rate matches an externally-set one ? */ 5560 5561 spin_lock_irq(&hdspm->lock); 5562 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5563 if (err < 0) { 5564 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err); 5565 spin_unlock_irq(&hdspm->lock); 5566 _snd_pcm_hw_param_setempty(params, 5567 SNDRV_PCM_HW_PARAM_RATE); 5568 return err; 5569 } 5570 spin_unlock_irq(&hdspm->lock); 5571 5572 err = hdspm_set_interrupt_interval(hdspm, 5573 params_period_size(params)); 5574 if (err < 0) { 5575 dev_info(hdspm->card->dev, 5576 "err on hdspm_set_interrupt_interval: %d\n", err); 5577 _snd_pcm_hw_param_setempty(params, 5578 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5579 return err; 5580 } 5581 5582 /* Memory allocation, takashi's method, dont know if we should 5583 * spinlock 5584 */ 5585 /* malloc all buffer even if not enabled to get sure */ 5586 /* Update for MADI rev 204: we need to allocate for all channels, 5587 * otherwise it doesn't work at 96kHz */ 5588 5589 err = 5590 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5591 if (err < 0) { 5592 dev_info(hdspm->card->dev, 5593 "err on snd_pcm_lib_malloc_pages: %d\n", err); 5594 return err; 5595 } 5596 5597 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5598 5599 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5600 params_channels(params)); 5601 5602 for (i = 0; i < params_channels(params); ++i) 5603 snd_hdspm_enable_out(hdspm, i, 1); 5604 5605 hdspm->playback_buffer = 5606 (unsigned char *) substream->runtime->dma_area; 5607 dev_dbg(hdspm->card->dev, 5608 "Allocated sample buffer for playback at %p\n", 5609 hdspm->playback_buffer); 5610 } else { 5611 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5612 params_channels(params)); 5613 5614 for (i = 0; i < params_channels(params); ++i) 5615 snd_hdspm_enable_in(hdspm, i, 1); 5616 5617 hdspm->capture_buffer = 5618 (unsigned char *) substream->runtime->dma_area; 5619 dev_dbg(hdspm->card->dev, 5620 "Allocated sample buffer for capture at %p\n", 5621 hdspm->capture_buffer); 5622 } 5623 5624 /* 5625 dev_dbg(hdspm->card->dev, 5626 "Allocated sample buffer for %s at 0x%08X\n", 5627 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5628 "playback" : "capture", 5629 snd_pcm_sgbuf_get_addr(substream, 0)); 5630 */ 5631 /* 5632 dev_dbg(hdspm->card->dev, 5633 "set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5634 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5635 "playback" : "capture", 5636 params_rate(params), params_channels(params), 5637 params_buffer_size(params)); 5638 */ 5639 5640 5641 /* For AES cards, the float format bit is the same as the 5642 * preferred sync reference. Since we don't want to break 5643 * sync settings, we have to skip the remaining part of this 5644 * function. 5645 */ 5646 if (hdspm->io_type == AES32) { 5647 return 0; 5648 } 5649 5650 5651 /* Switch to native float format if requested */ 5652 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5653 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5654 dev_info(hdspm->card->dev, 5655 "Switching to native 32bit LE float format.\n"); 5656 5657 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5658 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5659 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5660 dev_info(hdspm->card->dev, 5661 "Switching to native 32bit LE integer format.\n"); 5662 5663 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5664 } 5665 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5666 5667 return 0; 5668 } 5669 5670 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5671 { 5672 int i; 5673 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5674 5675 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5676 5677 /* params_channels(params) should be enough, 5678 but to get sure in case of error */ 5679 for (i = 0; i < hdspm->max_channels_out; ++i) 5680 snd_hdspm_enable_out(hdspm, i, 0); 5681 5682 hdspm->playback_buffer = NULL; 5683 } else { 5684 for (i = 0; i < hdspm->max_channels_in; ++i) 5685 snd_hdspm_enable_in(hdspm, i, 0); 5686 5687 hdspm->capture_buffer = NULL; 5688 5689 } 5690 5691 snd_pcm_lib_free_pages(substream); 5692 5693 return 0; 5694 } 5695 5696 5697 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5698 struct snd_pcm_channel_info *info) 5699 { 5700 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5701 5702 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5703 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5704 dev_info(hdspm->card->dev, 5705 "snd_hdspm_channel_info: output channel out of range (%d)\n", 5706 info->channel); 5707 return -EINVAL; 5708 } 5709 5710 if (hdspm->channel_map_out[info->channel] < 0) { 5711 dev_info(hdspm->card->dev, 5712 "snd_hdspm_channel_info: output channel %d mapped out\n", 5713 info->channel); 5714 return -EINVAL; 5715 } 5716 5717 info->offset = hdspm->channel_map_out[info->channel] * 5718 HDSPM_CHANNEL_BUFFER_BYTES; 5719 } else { 5720 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5721 dev_info(hdspm->card->dev, 5722 "snd_hdspm_channel_info: input channel out of range (%d)\n", 5723 info->channel); 5724 return -EINVAL; 5725 } 5726 5727 if (hdspm->channel_map_in[info->channel] < 0) { 5728 dev_info(hdspm->card->dev, 5729 "snd_hdspm_channel_info: input channel %d mapped out\n", 5730 info->channel); 5731 return -EINVAL; 5732 } 5733 5734 info->offset = hdspm->channel_map_in[info->channel] * 5735 HDSPM_CHANNEL_BUFFER_BYTES; 5736 } 5737 5738 info->first = 0; 5739 info->step = 32; 5740 return 0; 5741 } 5742 5743 5744 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5745 unsigned int cmd, void *arg) 5746 { 5747 switch (cmd) { 5748 case SNDRV_PCM_IOCTL1_RESET: 5749 return snd_hdspm_reset(substream); 5750 5751 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5752 { 5753 struct snd_pcm_channel_info *info = arg; 5754 return snd_hdspm_channel_info(substream, info); 5755 } 5756 default: 5757 break; 5758 } 5759 5760 return snd_pcm_lib_ioctl(substream, cmd, arg); 5761 } 5762 5763 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5764 { 5765 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5766 struct snd_pcm_substream *other; 5767 int running; 5768 5769 spin_lock(&hdspm->lock); 5770 running = hdspm->running; 5771 switch (cmd) { 5772 case SNDRV_PCM_TRIGGER_START: 5773 running |= 1 << substream->stream; 5774 break; 5775 case SNDRV_PCM_TRIGGER_STOP: 5776 running &= ~(1 << substream->stream); 5777 break; 5778 default: 5779 snd_BUG(); 5780 spin_unlock(&hdspm->lock); 5781 return -EINVAL; 5782 } 5783 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5784 other = hdspm->capture_substream; 5785 else 5786 other = hdspm->playback_substream; 5787 5788 if (other) { 5789 struct snd_pcm_substream *s; 5790 snd_pcm_group_for_each_entry(s, substream) { 5791 if (s == other) { 5792 snd_pcm_trigger_done(s, substream); 5793 if (cmd == SNDRV_PCM_TRIGGER_START) 5794 running |= 1 << s->stream; 5795 else 5796 running &= ~(1 << s->stream); 5797 goto _ok; 5798 } 5799 } 5800 if (cmd == SNDRV_PCM_TRIGGER_START) { 5801 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5802 && substream->stream == 5803 SNDRV_PCM_STREAM_CAPTURE) 5804 hdspm_silence_playback(hdspm); 5805 } else { 5806 if (running && 5807 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5808 hdspm_silence_playback(hdspm); 5809 } 5810 } else { 5811 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5812 hdspm_silence_playback(hdspm); 5813 } 5814 _ok: 5815 snd_pcm_trigger_done(substream, substream); 5816 if (!hdspm->running && running) 5817 hdspm_start_audio(hdspm); 5818 else if (hdspm->running && !running) 5819 hdspm_stop_audio(hdspm); 5820 hdspm->running = running; 5821 spin_unlock(&hdspm->lock); 5822 5823 return 0; 5824 } 5825 5826 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5827 { 5828 return 0; 5829 } 5830 5831 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5832 .info = (SNDRV_PCM_INFO_MMAP | 5833 SNDRV_PCM_INFO_MMAP_VALID | 5834 SNDRV_PCM_INFO_NONINTERLEAVED | 5835 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5836 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5837 .rates = (SNDRV_PCM_RATE_32000 | 5838 SNDRV_PCM_RATE_44100 | 5839 SNDRV_PCM_RATE_48000 | 5840 SNDRV_PCM_RATE_64000 | 5841 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5842 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5843 .rate_min = 32000, 5844 .rate_max = 192000, 5845 .channels_min = 1, 5846 .channels_max = HDSPM_MAX_CHANNELS, 5847 .buffer_bytes_max = 5848 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5849 .period_bytes_min = (32 * 4), 5850 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5851 .periods_min = 2, 5852 .periods_max = 512, 5853 .fifo_size = 0 5854 }; 5855 5856 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5857 .info = (SNDRV_PCM_INFO_MMAP | 5858 SNDRV_PCM_INFO_MMAP_VALID | 5859 SNDRV_PCM_INFO_NONINTERLEAVED | 5860 SNDRV_PCM_INFO_SYNC_START), 5861 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5862 .rates = (SNDRV_PCM_RATE_32000 | 5863 SNDRV_PCM_RATE_44100 | 5864 SNDRV_PCM_RATE_48000 | 5865 SNDRV_PCM_RATE_64000 | 5866 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5867 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5868 .rate_min = 32000, 5869 .rate_max = 192000, 5870 .channels_min = 1, 5871 .channels_max = HDSPM_MAX_CHANNELS, 5872 .buffer_bytes_max = 5873 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5874 .period_bytes_min = (32 * 4), 5875 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5876 .periods_min = 2, 5877 .periods_max = 512, 5878 .fifo_size = 0 5879 }; 5880 5881 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5882 struct snd_pcm_hw_rule *rule) 5883 { 5884 struct hdspm *hdspm = rule->private; 5885 struct snd_interval *c = 5886 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5887 struct snd_interval *r = 5888 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5889 5890 if (r->min > 96000 && r->max <= 192000) { 5891 struct snd_interval t = { 5892 .min = hdspm->qs_in_channels, 5893 .max = hdspm->qs_in_channels, 5894 .integer = 1, 5895 }; 5896 return snd_interval_refine(c, &t); 5897 } else if (r->min > 48000 && r->max <= 96000) { 5898 struct snd_interval t = { 5899 .min = hdspm->ds_in_channels, 5900 .max = hdspm->ds_in_channels, 5901 .integer = 1, 5902 }; 5903 return snd_interval_refine(c, &t); 5904 } else if (r->max < 64000) { 5905 struct snd_interval t = { 5906 .min = hdspm->ss_in_channels, 5907 .max = hdspm->ss_in_channels, 5908 .integer = 1, 5909 }; 5910 return snd_interval_refine(c, &t); 5911 } 5912 5913 return 0; 5914 } 5915 5916 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5917 struct snd_pcm_hw_rule * rule) 5918 { 5919 struct hdspm *hdspm = rule->private; 5920 struct snd_interval *c = 5921 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5922 struct snd_interval *r = 5923 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5924 5925 if (r->min > 96000 && r->max <= 192000) { 5926 struct snd_interval t = { 5927 .min = hdspm->qs_out_channels, 5928 .max = hdspm->qs_out_channels, 5929 .integer = 1, 5930 }; 5931 return snd_interval_refine(c, &t); 5932 } else if (r->min > 48000 && r->max <= 96000) { 5933 struct snd_interval t = { 5934 .min = hdspm->ds_out_channels, 5935 .max = hdspm->ds_out_channels, 5936 .integer = 1, 5937 }; 5938 return snd_interval_refine(c, &t); 5939 } else if (r->max < 64000) { 5940 struct snd_interval t = { 5941 .min = hdspm->ss_out_channels, 5942 .max = hdspm->ss_out_channels, 5943 .integer = 1, 5944 }; 5945 return snd_interval_refine(c, &t); 5946 } else { 5947 } 5948 return 0; 5949 } 5950 5951 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5952 struct snd_pcm_hw_rule * rule) 5953 { 5954 struct hdspm *hdspm = rule->private; 5955 struct snd_interval *c = 5956 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5957 struct snd_interval *r = 5958 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5959 5960 if (c->min >= hdspm->ss_in_channels) { 5961 struct snd_interval t = { 5962 .min = 32000, 5963 .max = 48000, 5964 .integer = 1, 5965 }; 5966 return snd_interval_refine(r, &t); 5967 } else if (c->max <= hdspm->qs_in_channels) { 5968 struct snd_interval t = { 5969 .min = 128000, 5970 .max = 192000, 5971 .integer = 1, 5972 }; 5973 return snd_interval_refine(r, &t); 5974 } else if (c->max <= hdspm->ds_in_channels) { 5975 struct snd_interval t = { 5976 .min = 64000, 5977 .max = 96000, 5978 .integer = 1, 5979 }; 5980 return snd_interval_refine(r, &t); 5981 } 5982 5983 return 0; 5984 } 5985 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5986 struct snd_pcm_hw_rule *rule) 5987 { 5988 struct hdspm *hdspm = rule->private; 5989 struct snd_interval *c = 5990 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5991 struct snd_interval *r = 5992 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5993 5994 if (c->min >= hdspm->ss_out_channels) { 5995 struct snd_interval t = { 5996 .min = 32000, 5997 .max = 48000, 5998 .integer = 1, 5999 }; 6000 return snd_interval_refine(r, &t); 6001 } else if (c->max <= hdspm->qs_out_channels) { 6002 struct snd_interval t = { 6003 .min = 128000, 6004 .max = 192000, 6005 .integer = 1, 6006 }; 6007 return snd_interval_refine(r, &t); 6008 } else if (c->max <= hdspm->ds_out_channels) { 6009 struct snd_interval t = { 6010 .min = 64000, 6011 .max = 96000, 6012 .integer = 1, 6013 }; 6014 return snd_interval_refine(r, &t); 6015 } 6016 6017 return 0; 6018 } 6019 6020 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 6021 struct snd_pcm_hw_rule *rule) 6022 { 6023 unsigned int list[3]; 6024 struct hdspm *hdspm = rule->private; 6025 struct snd_interval *c = hw_param_interval(params, 6026 SNDRV_PCM_HW_PARAM_CHANNELS); 6027 6028 list[0] = hdspm->qs_in_channels; 6029 list[1] = hdspm->ds_in_channels; 6030 list[2] = hdspm->ss_in_channels; 6031 return snd_interval_list(c, 3, list, 0); 6032 } 6033 6034 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 6035 struct snd_pcm_hw_rule *rule) 6036 { 6037 unsigned int list[3]; 6038 struct hdspm *hdspm = rule->private; 6039 struct snd_interval *c = hw_param_interval(params, 6040 SNDRV_PCM_HW_PARAM_CHANNELS); 6041 6042 list[0] = hdspm->qs_out_channels; 6043 list[1] = hdspm->ds_out_channels; 6044 list[2] = hdspm->ss_out_channels; 6045 return snd_interval_list(c, 3, list, 0); 6046 } 6047 6048 6049 static const unsigned int hdspm_aes32_sample_rates[] = { 6050 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 6051 }; 6052 6053 static const struct snd_pcm_hw_constraint_list 6054 hdspm_hw_constraints_aes32_sample_rates = { 6055 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 6056 .list = hdspm_aes32_sample_rates, 6057 .mask = 0 6058 }; 6059 6060 static int snd_hdspm_open(struct snd_pcm_substream *substream) 6061 { 6062 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6063 struct snd_pcm_runtime *runtime = substream->runtime; 6064 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6065 6066 spin_lock_irq(&hdspm->lock); 6067 snd_pcm_set_sync(substream); 6068 runtime->hw = (playback) ? snd_hdspm_playback_subinfo : 6069 snd_hdspm_capture_subinfo; 6070 6071 if (playback) { 6072 if (!hdspm->capture_substream) 6073 hdspm_stop_audio(hdspm); 6074 6075 hdspm->playback_pid = current->pid; 6076 hdspm->playback_substream = substream; 6077 } else { 6078 if (!hdspm->playback_substream) 6079 hdspm_stop_audio(hdspm); 6080 6081 hdspm->capture_pid = current->pid; 6082 hdspm->capture_substream = substream; 6083 } 6084 6085 spin_unlock_irq(&hdspm->lock); 6086 6087 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6088 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6089 6090 switch (hdspm->io_type) { 6091 case AIO: 6092 case RayDAT: 6093 snd_pcm_hw_constraint_minmax(runtime, 6094 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6095 32, 4096); 6096 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 6097 snd_pcm_hw_constraint_single(runtime, 6098 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6099 16384); 6100 break; 6101 6102 default: 6103 snd_pcm_hw_constraint_minmax(runtime, 6104 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6105 64, 8192); 6106 snd_pcm_hw_constraint_single(runtime, 6107 SNDRV_PCM_HW_PARAM_PERIODS, 2); 6108 break; 6109 } 6110 6111 if (AES32 == hdspm->io_type) { 6112 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 6113 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6114 &hdspm_hw_constraints_aes32_sample_rates); 6115 } else { 6116 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6117 (playback ? 6118 snd_hdspm_hw_rule_rate_out_channels : 6119 snd_hdspm_hw_rule_rate_in_channels), hdspm, 6120 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6121 } 6122 6123 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6124 (playback ? snd_hdspm_hw_rule_out_channels : 6125 snd_hdspm_hw_rule_in_channels), hdspm, 6126 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6127 6128 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6129 (playback ? snd_hdspm_hw_rule_out_channels_rate : 6130 snd_hdspm_hw_rule_in_channels_rate), hdspm, 6131 SNDRV_PCM_HW_PARAM_RATE, -1); 6132 6133 return 0; 6134 } 6135 6136 static int snd_hdspm_release(struct snd_pcm_substream *substream) 6137 { 6138 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6139 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6140 6141 spin_lock_irq(&hdspm->lock); 6142 6143 if (playback) { 6144 hdspm->playback_pid = -1; 6145 hdspm->playback_substream = NULL; 6146 } else { 6147 hdspm->capture_pid = -1; 6148 hdspm->capture_substream = NULL; 6149 } 6150 6151 spin_unlock_irq(&hdspm->lock); 6152 6153 return 0; 6154 } 6155 6156 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6157 { 6158 /* we have nothing to initialize but the call is required */ 6159 return 0; 6160 } 6161 6162 static inline int copy_u32_le(void __user *dest, void __iomem *src) 6163 { 6164 u32 val = readl(src); 6165 return copy_to_user(dest, &val, 4); 6166 } 6167 6168 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6169 unsigned int cmd, unsigned long arg) 6170 { 6171 void __user *argp = (void __user *)arg; 6172 struct hdspm *hdspm = hw->private_data; 6173 struct hdspm_mixer_ioctl mixer; 6174 struct hdspm_config info; 6175 struct hdspm_status status; 6176 struct hdspm_version hdspm_version; 6177 struct hdspm_peak_rms *levels; 6178 struct hdspm_ltc ltc; 6179 unsigned int statusregister; 6180 long unsigned int s; 6181 int i = 0; 6182 6183 switch (cmd) { 6184 6185 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6186 levels = &hdspm->peak_rms; 6187 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6188 levels->input_peaks[i] = 6189 readl(hdspm->iobase + 6190 HDSPM_MADI_INPUT_PEAK + i*4); 6191 levels->playback_peaks[i] = 6192 readl(hdspm->iobase + 6193 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6194 levels->output_peaks[i] = 6195 readl(hdspm->iobase + 6196 HDSPM_MADI_OUTPUT_PEAK + i*4); 6197 6198 levels->input_rms[i] = 6199 ((uint64_t) readl(hdspm->iobase + 6200 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6201 (uint64_t) readl(hdspm->iobase + 6202 HDSPM_MADI_INPUT_RMS_L + i*4); 6203 levels->playback_rms[i] = 6204 ((uint64_t)readl(hdspm->iobase + 6205 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6206 (uint64_t)readl(hdspm->iobase + 6207 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6208 levels->output_rms[i] = 6209 ((uint64_t)readl(hdspm->iobase + 6210 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6211 (uint64_t)readl(hdspm->iobase + 6212 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6213 } 6214 6215 if (hdspm->system_sample_rate > 96000) { 6216 levels->speed = qs; 6217 } else if (hdspm->system_sample_rate > 48000) { 6218 levels->speed = ds; 6219 } else { 6220 levels->speed = ss; 6221 } 6222 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6223 6224 s = copy_to_user(argp, levels, sizeof(*levels)); 6225 if (0 != s) { 6226 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu 6227 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6228 */ 6229 return -EFAULT; 6230 } 6231 break; 6232 6233 case SNDRV_HDSPM_IOCTL_GET_LTC: 6234 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6235 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6236 if (i & HDSPM_TCO1_LTC_Input_valid) { 6237 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6238 HDSPM_TCO1_LTC_Format_MSB)) { 6239 case 0: 6240 ltc.format = fps_24; 6241 break; 6242 case HDSPM_TCO1_LTC_Format_LSB: 6243 ltc.format = fps_25; 6244 break; 6245 case HDSPM_TCO1_LTC_Format_MSB: 6246 ltc.format = fps_2997; 6247 break; 6248 default: 6249 ltc.format = fps_30; 6250 break; 6251 } 6252 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6253 ltc.frame = drop_frame; 6254 } else { 6255 ltc.frame = full_frame; 6256 } 6257 } else { 6258 ltc.format = format_invalid; 6259 ltc.frame = frame_invalid; 6260 } 6261 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6262 ltc.input_format = ntsc; 6263 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6264 ltc.input_format = pal; 6265 } else { 6266 ltc.input_format = no_video; 6267 } 6268 6269 s = copy_to_user(argp, <c, sizeof(ltc)); 6270 if (0 != s) { 6271 /* 6272 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6273 return -EFAULT; 6274 } 6275 6276 break; 6277 6278 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6279 6280 memset(&info, 0, sizeof(info)); 6281 spin_lock_irq(&hdspm->lock); 6282 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6283 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6284 6285 info.system_sample_rate = hdspm->system_sample_rate; 6286 info.autosync_sample_rate = 6287 hdspm_external_sample_rate(hdspm); 6288 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6289 info.clock_source = hdspm_clock_source(hdspm); 6290 info.autosync_ref = hdspm_autosync_ref(hdspm); 6291 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6292 info.passthru = 0; 6293 spin_unlock_irq(&hdspm->lock); 6294 if (copy_to_user(argp, &info, sizeof(info))) 6295 return -EFAULT; 6296 break; 6297 6298 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6299 memset(&status, 0, sizeof(status)); 6300 6301 status.card_type = hdspm->io_type; 6302 6303 status.autosync_source = hdspm_autosync_ref(hdspm); 6304 6305 status.card_clock = 110069313433624ULL; 6306 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6307 6308 switch (hdspm->io_type) { 6309 case MADI: 6310 case MADIface: 6311 status.card_specific.madi.sync_wc = 6312 hdspm_wc_sync_check(hdspm); 6313 status.card_specific.madi.sync_madi = 6314 hdspm_madi_sync_check(hdspm); 6315 status.card_specific.madi.sync_tco = 6316 hdspm_tco_sync_check(hdspm); 6317 status.card_specific.madi.sync_in = 6318 hdspm_sync_in_sync_check(hdspm); 6319 6320 statusregister = 6321 hdspm_read(hdspm, HDSPM_statusRegister); 6322 status.card_specific.madi.madi_input = 6323 (statusregister & HDSPM_AB_int) ? 1 : 0; 6324 status.card_specific.madi.channel_format = 6325 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6326 /* TODO: Mac driver sets it when f_s>48kHz */ 6327 status.card_specific.madi.frame_format = 0; 6328 6329 default: 6330 break; 6331 } 6332 6333 if (copy_to_user(argp, &status, sizeof(status))) 6334 return -EFAULT; 6335 6336 6337 break; 6338 6339 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6340 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6341 6342 hdspm_version.card_type = hdspm->io_type; 6343 strlcpy(hdspm_version.cardname, hdspm->card_name, 6344 sizeof(hdspm_version.cardname)); 6345 hdspm_version.serial = hdspm->serial; 6346 hdspm_version.firmware_rev = hdspm->firmware_rev; 6347 hdspm_version.addons = 0; 6348 if (hdspm->tco) 6349 hdspm_version.addons |= HDSPM_ADDON_TCO; 6350 6351 if (copy_to_user(argp, &hdspm_version, 6352 sizeof(hdspm_version))) 6353 return -EFAULT; 6354 break; 6355 6356 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6357 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6358 return -EFAULT; 6359 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6360 sizeof(*mixer.mixer))) 6361 return -EFAULT; 6362 break; 6363 6364 default: 6365 return -EINVAL; 6366 } 6367 return 0; 6368 } 6369 6370 static const struct snd_pcm_ops snd_hdspm_ops = { 6371 .open = snd_hdspm_open, 6372 .close = snd_hdspm_release, 6373 .ioctl = snd_hdspm_ioctl, 6374 .hw_params = snd_hdspm_hw_params, 6375 .hw_free = snd_hdspm_hw_free, 6376 .prepare = snd_hdspm_prepare, 6377 .trigger = snd_hdspm_trigger, 6378 .pointer = snd_hdspm_hw_pointer, 6379 .page = snd_pcm_sgbuf_ops_page, 6380 }; 6381 6382 static int snd_hdspm_create_hwdep(struct snd_card *card, 6383 struct hdspm *hdspm) 6384 { 6385 struct snd_hwdep *hw; 6386 int err; 6387 6388 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6389 if (err < 0) 6390 return err; 6391 6392 hdspm->hwdep = hw; 6393 hw->private_data = hdspm; 6394 strcpy(hw->name, "HDSPM hwdep interface"); 6395 6396 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6397 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6398 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6399 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6400 6401 return 0; 6402 } 6403 6404 6405 /*------------------------------------------------------------ 6406 memory interface 6407 ------------------------------------------------------------*/ 6408 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6409 { 6410 int err; 6411 struct snd_pcm *pcm; 6412 size_t wanted; 6413 6414 pcm = hdspm->pcm; 6415 6416 wanted = HDSPM_DMA_AREA_BYTES; 6417 6418 err = 6419 snd_pcm_lib_preallocate_pages_for_all(pcm, 6420 SNDRV_DMA_TYPE_DEV_SG, 6421 snd_dma_pci_data(hdspm->pci), 6422 wanted, 6423 wanted); 6424 if (err < 0) { 6425 dev_dbg(hdspm->card->dev, 6426 "Could not preallocate %zd Bytes\n", wanted); 6427 6428 return err; 6429 } else 6430 dev_dbg(hdspm->card->dev, 6431 " Preallocated %zd Bytes\n", wanted); 6432 6433 return 0; 6434 } 6435 6436 6437 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6438 struct snd_pcm_substream *substream, 6439 unsigned int reg, int channels) 6440 { 6441 int i; 6442 6443 /* continuous memory segment */ 6444 for (i = 0; i < (channels * 16); i++) 6445 hdspm_write(hdspm, reg + 4 * i, 6446 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6447 } 6448 6449 6450 /* ------------- ALSA Devices ---------------------------- */ 6451 static int snd_hdspm_create_pcm(struct snd_card *card, 6452 struct hdspm *hdspm) 6453 { 6454 struct snd_pcm *pcm; 6455 int err; 6456 6457 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6458 if (err < 0) 6459 return err; 6460 6461 hdspm->pcm = pcm; 6462 pcm->private_data = hdspm; 6463 strcpy(pcm->name, hdspm->card_name); 6464 6465 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6466 &snd_hdspm_ops); 6467 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6468 &snd_hdspm_ops); 6469 6470 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6471 6472 err = snd_hdspm_preallocate_memory(hdspm); 6473 if (err < 0) 6474 return err; 6475 6476 return 0; 6477 } 6478 6479 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6480 { 6481 int i; 6482 6483 for (i = 0; i < hdspm->midiPorts; i++) 6484 snd_hdspm_flush_midi_input(hdspm, i); 6485 } 6486 6487 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6488 struct hdspm *hdspm) 6489 { 6490 int err, i; 6491 6492 dev_dbg(card->dev, "Create card...\n"); 6493 err = snd_hdspm_create_pcm(card, hdspm); 6494 if (err < 0) 6495 return err; 6496 6497 i = 0; 6498 while (i < hdspm->midiPorts) { 6499 err = snd_hdspm_create_midi(card, hdspm, i); 6500 if (err < 0) { 6501 return err; 6502 } 6503 i++; 6504 } 6505 6506 err = snd_hdspm_create_controls(card, hdspm); 6507 if (err < 0) 6508 return err; 6509 6510 err = snd_hdspm_create_hwdep(card, hdspm); 6511 if (err < 0) 6512 return err; 6513 6514 dev_dbg(card->dev, "proc init...\n"); 6515 snd_hdspm_proc_init(hdspm); 6516 6517 hdspm->system_sample_rate = -1; 6518 hdspm->last_external_sample_rate = -1; 6519 hdspm->last_internal_sample_rate = -1; 6520 hdspm->playback_pid = -1; 6521 hdspm->capture_pid = -1; 6522 hdspm->capture_substream = NULL; 6523 hdspm->playback_substream = NULL; 6524 6525 dev_dbg(card->dev, "Set defaults...\n"); 6526 err = snd_hdspm_set_defaults(hdspm); 6527 if (err < 0) 6528 return err; 6529 6530 dev_dbg(card->dev, "Update mixer controls...\n"); 6531 hdspm_update_simple_mixer_controls(hdspm); 6532 6533 dev_dbg(card->dev, "Initializeing complete ???\n"); 6534 6535 err = snd_card_register(card); 6536 if (err < 0) { 6537 dev_err(card->dev, "error registering card\n"); 6538 return err; 6539 } 6540 6541 dev_dbg(card->dev, "... yes now\n"); 6542 6543 return 0; 6544 } 6545 6546 static int snd_hdspm_create(struct snd_card *card, 6547 struct hdspm *hdspm) 6548 { 6549 6550 struct pci_dev *pci = hdspm->pci; 6551 int err; 6552 unsigned long io_extent; 6553 6554 hdspm->irq = -1; 6555 hdspm->card = card; 6556 6557 spin_lock_init(&hdspm->lock); 6558 6559 pci_read_config_word(hdspm->pci, 6560 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6561 6562 strcpy(card->mixername, "Xilinx FPGA"); 6563 strcpy(card->driver, "HDSPM"); 6564 6565 switch (hdspm->firmware_rev) { 6566 case HDSPM_RAYDAT_REV: 6567 hdspm->io_type = RayDAT; 6568 hdspm->card_name = "RME RayDAT"; 6569 hdspm->midiPorts = 2; 6570 break; 6571 case HDSPM_AIO_REV: 6572 hdspm->io_type = AIO; 6573 hdspm->card_name = "RME AIO"; 6574 hdspm->midiPorts = 1; 6575 break; 6576 case HDSPM_MADIFACE_REV: 6577 hdspm->io_type = MADIface; 6578 hdspm->card_name = "RME MADIface"; 6579 hdspm->midiPorts = 1; 6580 break; 6581 default: 6582 if ((hdspm->firmware_rev == 0xf0) || 6583 ((hdspm->firmware_rev >= 0xe6) && 6584 (hdspm->firmware_rev <= 0xea))) { 6585 hdspm->io_type = AES32; 6586 hdspm->card_name = "RME AES32"; 6587 hdspm->midiPorts = 2; 6588 } else if ((hdspm->firmware_rev == 0xd2) || 6589 ((hdspm->firmware_rev >= 0xc8) && 6590 (hdspm->firmware_rev <= 0xcf))) { 6591 hdspm->io_type = MADI; 6592 hdspm->card_name = "RME MADI"; 6593 hdspm->midiPorts = 3; 6594 } else { 6595 dev_err(card->dev, 6596 "unknown firmware revision %x\n", 6597 hdspm->firmware_rev); 6598 return -ENODEV; 6599 } 6600 } 6601 6602 err = pci_enable_device(pci); 6603 if (err < 0) 6604 return err; 6605 6606 pci_set_master(hdspm->pci); 6607 6608 err = pci_request_regions(pci, "hdspm"); 6609 if (err < 0) 6610 return err; 6611 6612 hdspm->port = pci_resource_start(pci, 0); 6613 io_extent = pci_resource_len(pci, 0); 6614 6615 dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n", 6616 hdspm->port, hdspm->port + io_extent - 1); 6617 6618 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6619 if (!hdspm->iobase) { 6620 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n", 6621 hdspm->port, hdspm->port + io_extent - 1); 6622 return -EBUSY; 6623 } 6624 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n", 6625 (unsigned long)hdspm->iobase, hdspm->port, 6626 hdspm->port + io_extent - 1); 6627 6628 if (request_irq(pci->irq, snd_hdspm_interrupt, 6629 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6630 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq); 6631 return -EBUSY; 6632 } 6633 6634 dev_dbg(card->dev, "use IRQ %d\n", pci->irq); 6635 6636 hdspm->irq = pci->irq; 6637 6638 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n", 6639 sizeof(*hdspm->mixer)); 6640 hdspm->mixer = kzalloc(sizeof(*hdspm->mixer), GFP_KERNEL); 6641 if (!hdspm->mixer) 6642 return -ENOMEM; 6643 6644 hdspm->port_names_in = NULL; 6645 hdspm->port_names_out = NULL; 6646 6647 switch (hdspm->io_type) { 6648 case AES32: 6649 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6650 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6651 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6652 6653 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6654 channel_map_aes32; 6655 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6656 channel_map_aes32; 6657 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6658 channel_map_aes32; 6659 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6660 texts_ports_aes32; 6661 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6662 texts_ports_aes32; 6663 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6664 texts_ports_aes32; 6665 6666 hdspm->max_channels_out = hdspm->max_channels_in = 6667 AES32_CHANNELS; 6668 hdspm->port_names_in = hdspm->port_names_out = 6669 texts_ports_aes32; 6670 hdspm->channel_map_in = hdspm->channel_map_out = 6671 channel_map_aes32; 6672 6673 break; 6674 6675 case MADI: 6676 case MADIface: 6677 hdspm->ss_in_channels = hdspm->ss_out_channels = 6678 MADI_SS_CHANNELS; 6679 hdspm->ds_in_channels = hdspm->ds_out_channels = 6680 MADI_DS_CHANNELS; 6681 hdspm->qs_in_channels = hdspm->qs_out_channels = 6682 MADI_QS_CHANNELS; 6683 6684 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6685 channel_map_unity_ss; 6686 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6687 channel_map_unity_ss; 6688 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6689 channel_map_unity_ss; 6690 6691 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6692 texts_ports_madi; 6693 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6694 texts_ports_madi; 6695 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6696 texts_ports_madi; 6697 break; 6698 6699 case AIO: 6700 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6701 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6702 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6703 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6704 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6705 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6706 6707 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6708 dev_info(card->dev, "AEB input board found\n"); 6709 hdspm->ss_in_channels += 4; 6710 hdspm->ds_in_channels += 4; 6711 hdspm->qs_in_channels += 4; 6712 } 6713 6714 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) { 6715 dev_info(card->dev, "AEB output board found\n"); 6716 hdspm->ss_out_channels += 4; 6717 hdspm->ds_out_channels += 4; 6718 hdspm->qs_out_channels += 4; 6719 } 6720 6721 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6722 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6723 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6724 6725 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6726 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6727 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6728 6729 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6730 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6731 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6732 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6733 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6734 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6735 6736 break; 6737 6738 case RayDAT: 6739 hdspm->ss_in_channels = hdspm->ss_out_channels = 6740 RAYDAT_SS_CHANNELS; 6741 hdspm->ds_in_channels = hdspm->ds_out_channels = 6742 RAYDAT_DS_CHANNELS; 6743 hdspm->qs_in_channels = hdspm->qs_out_channels = 6744 RAYDAT_QS_CHANNELS; 6745 6746 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6747 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6748 6749 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6750 channel_map_raydat_ss; 6751 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6752 channel_map_raydat_ds; 6753 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6754 channel_map_raydat_qs; 6755 hdspm->channel_map_in = hdspm->channel_map_out = 6756 channel_map_raydat_ss; 6757 6758 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6759 texts_ports_raydat_ss; 6760 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6761 texts_ports_raydat_ds; 6762 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6763 texts_ports_raydat_qs; 6764 6765 6766 break; 6767 6768 } 6769 6770 /* TCO detection */ 6771 switch (hdspm->io_type) { 6772 case AIO: 6773 case RayDAT: 6774 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6775 HDSPM_s2_tco_detect) { 6776 hdspm->midiPorts++; 6777 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6778 if (hdspm->tco) 6779 hdspm_tco_write(hdspm); 6780 6781 dev_info(card->dev, "AIO/RayDAT TCO module found\n"); 6782 } else { 6783 hdspm->tco = NULL; 6784 } 6785 break; 6786 6787 case MADI: 6788 case AES32: 6789 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6790 hdspm->midiPorts++; 6791 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6792 if (hdspm->tco) 6793 hdspm_tco_write(hdspm); 6794 6795 dev_info(card->dev, "MADI/AES TCO module found\n"); 6796 } else { 6797 hdspm->tco = NULL; 6798 } 6799 break; 6800 6801 default: 6802 hdspm->tco = NULL; 6803 } 6804 6805 /* texts */ 6806 switch (hdspm->io_type) { 6807 case AES32: 6808 if (hdspm->tco) { 6809 hdspm->texts_autosync = texts_autosync_aes_tco; 6810 hdspm->texts_autosync_items = 6811 ARRAY_SIZE(texts_autosync_aes_tco); 6812 } else { 6813 hdspm->texts_autosync = texts_autosync_aes; 6814 hdspm->texts_autosync_items = 6815 ARRAY_SIZE(texts_autosync_aes); 6816 } 6817 break; 6818 6819 case MADI: 6820 if (hdspm->tco) { 6821 hdspm->texts_autosync = texts_autosync_madi_tco; 6822 hdspm->texts_autosync_items = 4; 6823 } else { 6824 hdspm->texts_autosync = texts_autosync_madi; 6825 hdspm->texts_autosync_items = 3; 6826 } 6827 break; 6828 6829 case MADIface: 6830 6831 break; 6832 6833 case RayDAT: 6834 if (hdspm->tco) { 6835 hdspm->texts_autosync = texts_autosync_raydat_tco; 6836 hdspm->texts_autosync_items = 9; 6837 } else { 6838 hdspm->texts_autosync = texts_autosync_raydat; 6839 hdspm->texts_autosync_items = 8; 6840 } 6841 break; 6842 6843 case AIO: 6844 if (hdspm->tco) { 6845 hdspm->texts_autosync = texts_autosync_aio_tco; 6846 hdspm->texts_autosync_items = 6; 6847 } else { 6848 hdspm->texts_autosync = texts_autosync_aio; 6849 hdspm->texts_autosync_items = 5; 6850 } 6851 break; 6852 6853 } 6854 6855 tasklet_init(&hdspm->midi_tasklet, 6856 hdspm_midi_tasklet, (unsigned long) hdspm); 6857 6858 6859 if (hdspm->io_type != MADIface) { 6860 hdspm->serial = (hdspm_read(hdspm, 6861 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6862 /* id contains either a user-provided value or the default 6863 * NULL. If it's the default, we're safe to 6864 * fill card->id with the serial number. 6865 * 6866 * If the serial number is 0xFFFFFF, then we're dealing with 6867 * an old PCI revision that comes without a sane number. In 6868 * this case, we don't set card->id to avoid collisions 6869 * when running with multiple cards. 6870 */ 6871 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6872 snprintf(card->id, sizeof(card->id), 6873 "HDSPMx%06x", hdspm->serial); 6874 snd_card_set_id(card, card->id); 6875 } 6876 } 6877 6878 dev_dbg(card->dev, "create alsa devices.\n"); 6879 err = snd_hdspm_create_alsa_devices(card, hdspm); 6880 if (err < 0) 6881 return err; 6882 6883 snd_hdspm_initialize_midi_flush(hdspm); 6884 6885 return 0; 6886 } 6887 6888 6889 static int snd_hdspm_free(struct hdspm * hdspm) 6890 { 6891 6892 if (hdspm->port) { 6893 6894 /* stop th audio, and cancel all interrupts */ 6895 hdspm->control_register &= 6896 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6897 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6898 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6899 hdspm_write(hdspm, HDSPM_controlRegister, 6900 hdspm->control_register); 6901 } 6902 6903 if (hdspm->irq >= 0) 6904 free_irq(hdspm->irq, (void *) hdspm); 6905 6906 kfree(hdspm->mixer); 6907 iounmap(hdspm->iobase); 6908 6909 if (hdspm->port) 6910 pci_release_regions(hdspm->pci); 6911 6912 pci_disable_device(hdspm->pci); 6913 return 0; 6914 } 6915 6916 6917 static void snd_hdspm_card_free(struct snd_card *card) 6918 { 6919 struct hdspm *hdspm = card->private_data; 6920 6921 if (hdspm) 6922 snd_hdspm_free(hdspm); 6923 } 6924 6925 6926 static int snd_hdspm_probe(struct pci_dev *pci, 6927 const struct pci_device_id *pci_id) 6928 { 6929 static int dev; 6930 struct hdspm *hdspm; 6931 struct snd_card *card; 6932 int err; 6933 6934 if (dev >= SNDRV_CARDS) 6935 return -ENODEV; 6936 if (!enable[dev]) { 6937 dev++; 6938 return -ENOENT; 6939 } 6940 6941 err = snd_card_new(&pci->dev, index[dev], id[dev], 6942 THIS_MODULE, sizeof(*hdspm), &card); 6943 if (err < 0) 6944 return err; 6945 6946 hdspm = card->private_data; 6947 card->private_free = snd_hdspm_card_free; 6948 hdspm->dev = dev; 6949 hdspm->pci = pci; 6950 6951 err = snd_hdspm_create(card, hdspm); 6952 if (err < 0) 6953 goto free_card; 6954 6955 if (hdspm->io_type != MADIface) { 6956 snprintf(card->shortname, sizeof(card->shortname), "%s_%x", 6957 hdspm->card_name, hdspm->serial); 6958 snprintf(card->longname, sizeof(card->longname), 6959 "%s S/N 0x%x at 0x%lx, irq %d", 6960 hdspm->card_name, hdspm->serial, 6961 hdspm->port, hdspm->irq); 6962 } else { 6963 snprintf(card->shortname, sizeof(card->shortname), "%s", 6964 hdspm->card_name); 6965 snprintf(card->longname, sizeof(card->longname), 6966 "%s at 0x%lx, irq %d", 6967 hdspm->card_name, hdspm->port, hdspm->irq); 6968 } 6969 6970 err = snd_card_register(card); 6971 if (err < 0) 6972 goto free_card; 6973 6974 pci_set_drvdata(pci, card); 6975 6976 dev++; 6977 return 0; 6978 6979 free_card: 6980 snd_card_free(card); 6981 return err; 6982 } 6983 6984 static void snd_hdspm_remove(struct pci_dev *pci) 6985 { 6986 snd_card_free(pci_get_drvdata(pci)); 6987 } 6988 6989 static struct pci_driver hdspm_driver = { 6990 .name = KBUILD_MODNAME, 6991 .id_table = snd_hdspm_ids, 6992 .probe = snd_hdspm_probe, 6993 .remove = snd_hdspm_remove, 6994 }; 6995 6996 module_pci_driver(hdspm_driver); 6997