1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 #include <linux/init.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/module.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/math64.h> 48 #include <asm/io.h> 49 50 #include <sound/core.h> 51 #include <sound/control.h> 52 #include <sound/pcm.h> 53 #include <sound/pcm_params.h> 54 #include <sound/info.h> 55 #include <sound/asoundef.h> 56 #include <sound/rawmidi.h> 57 #include <sound/hwdep.h> 58 #include <sound/initval.h> 59 60 #include <sound/hdspm.h> 61 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 68 69 module_param_array(id, charp, NULL, 0444); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 71 72 module_param_array(enable, bool, NULL, 0444); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 74 75 76 MODULE_AUTHOR 77 ( 78 "Winfried Ritsch <ritsch_AT_iem.at>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, " 82 "Florian Faber <faberman@linuxproaudio.org>, " 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 84 ); 85 MODULE_DESCRIPTION("RME HDSPM"); 86 MODULE_LICENSE("GPL"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 88 89 /* --- Write registers. --- 90 These are defined as byte-offsets from the iobase value. */ 91 92 #define HDSPM_WR_SETTINGS 0 93 #define HDSPM_outputBufferAddress 32 94 #define HDSPM_inputBufferAddress 36 95 #define HDSPM_controlRegister 64 96 #define HDSPM_interruptConfirmation 96 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 98 #define HDSPM_freqReg 256 /* for AES32 */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 100 #define HDSPM_midiDataOut1 356 101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 102 103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 106 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 109 #define HDSPM_pageAddressBufferOut 8192 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 111 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 113 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 115 116 /* --- Read registers. --- 117 These are defined as byte-offsets from the iobase value */ 118 #define HDSPM_statusRegister 0 119 /*#define HDSPM_statusRegister2 96 */ 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 121 * offset 192, for AES32 *and* MADI 122 * => need to check that offset 192 is working on MADI */ 123 #define HDSPM_statusRegister2 192 124 #define HDSPM_timecodeRegister 128 125 126 /* AIO, RayDAT */ 127 #define HDSPM_RD_STATUS_0 0 128 #define HDSPM_RD_STATUS_1 64 129 #define HDSPM_RD_STATUS_2 128 130 #define HDSPM_RD_STATUS_3 192 131 132 #define HDSPM_RD_TCO 256 133 #define HDSPM_RD_PLL_FREQ 512 134 #define HDSPM_WR_TCO 128 135 136 #define HDSPM_TCO1_TCO_lock 0x00000001 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 143 144 #define HDSPM_TCO1_set_TC 0x00000100 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 148 149 #define HDSPM_TCO2_TC_run 0x00010000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000 155 #define HDSPM_TCO2_set_flywheel 0x00400000 156 157 #define HDSPM_TCO2_set_01_4 0x01000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000 160 #define HDSPM_TCO2_set_freq 0x08000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 165 166 167 #define HDSPM_midiDataOut0 352 168 #define HDSPM_midiDataOut1 356 169 #define HDSPM_midiDataOut2 368 170 171 #define HDSPM_midiDataIn0 360 172 #define HDSPM_midiDataIn1 364 173 #define HDSPM_midiDataIn2 372 174 #define HDSPM_midiDataIn3 376 175 176 /* status is data bytes in MIDI-FIFO (0-128) */ 177 #define HDSPM_midiStatusOut0 384 178 #define HDSPM_midiStatusOut1 388 179 #define HDSPM_midiStatusOut2 400 180 181 #define HDSPM_midiStatusIn0 392 182 #define HDSPM_midiStatusIn1 396 183 #define HDSPM_midiStatusIn2 404 184 #define HDSPM_midiStatusIn3 408 185 186 187 /* the meters are regular i/o-mapped registers, but offset 188 considerably from the rest. the peak registers are reset 189 when read; the least-significant 4 bits are full-scale counters; 190 the actual peak value is in the most-significant 24 bits. 191 */ 192 193 #define HDSPM_MADI_INPUT_PEAK 4096 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 195 #define HDSPM_MADI_OUTPUT_PEAK 4608 196 197 #define HDSPM_MADI_INPUT_RMS_L 6144 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 200 201 #define HDSPM_MADI_INPUT_RMS_H 7168 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 204 205 /* --- Control Register bits --------- */ 206 #define HDSPM_Start (1<<0) /* start engine */ 207 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 211 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 214 register [RayDAT, AIO] */ 215 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 217 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 222 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 225 56channelMODE=0 */ /* MADI ONLY*/ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 227 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 229 0=off, 1=on */ /* MADI ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 231 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 233 * -- MADI ONLY 234 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 236 237 #define HDSPM_SyncRef2 (1<<13) 238 #define HDSPM_SyncRef3 (1<<25) 239 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 242 AES additional bits in 243 lower 5 Audiodatabits ??? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 246 247 #define HDSPM_Midi0InterruptEnable 0x0400000 248 #define HDSPM_Midi1InterruptEnable 0x0800000 249 #define HDSPM_Midi2InterruptEnable 0x0200000 250 #define HDSPM_Midi3InterruptEnable 0x4000000 251 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 253 #define HDSPe_FLOAT_FORMAT 0x2000000 254 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 258 259 #define HDSPM_wclk_sel (1<<30) 260 261 /* additional control register bits for AIO*/ 262 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 263 #define HDSPM_c0_Input0 0x1000 264 #define HDSPM_c0_Input1 0x2000 265 #define HDSPM_c0_Spdif_Opt 0x4000 266 #define HDSPM_c0_Pro 0x8000 267 #define HDSPM_c0_clr_tms 0x10000 268 #define HDSPM_c0_AEB1 0x20000 269 #define HDSPM_c0_AEB2 0x40000 270 #define HDSPM_c0_LineOut 0x80000 271 #define HDSPM_c0_AD_GAIN0 0x100000 272 #define HDSPM_c0_AD_GAIN1 0x200000 273 #define HDSPM_c0_DA_GAIN0 0x400000 274 #define HDSPM_c0_DA_GAIN1 0x800000 275 #define HDSPM_c0_PH_GAIN0 0x1000000 276 #define HDSPM_c0_PH_GAIN1 0x2000000 277 #define HDSPM_c0_Sym6db 0x4000000 278 279 280 /* --- bit helper defines */ 281 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 282 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 283 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 284 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 285 #define HDSPM_InputOptical 0 286 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 287 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 288 HDSPM_SyncRef2|HDSPM_SyncRef3) 289 290 #define HDSPM_c0_SyncRef0 0x2 291 #define HDSPM_c0_SyncRef1 0x4 292 #define HDSPM_c0_SyncRef2 0x8 293 #define HDSPM_c0_SyncRef3 0x10 294 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 295 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 296 297 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 298 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 299 #define HDSPM_SYNC_FROM_TCO 2 300 #define HDSPM_SYNC_FROM_SYNC_IN 3 301 302 #define HDSPM_Frequency32KHz HDSPM_Frequency0 303 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 304 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 305 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 306 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 307 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 308 HDSPM_Frequency0) 309 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 310 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 311 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 312 HDSPM_Frequency0) 313 314 315 /* Synccheck Status */ 316 #define HDSPM_SYNC_CHECK_NO_LOCK 0 317 #define HDSPM_SYNC_CHECK_LOCK 1 318 #define HDSPM_SYNC_CHECK_SYNC 2 319 320 /* AutoSync References - used by "autosync_ref" control switch */ 321 #define HDSPM_AUTOSYNC_FROM_WORD 0 322 #define HDSPM_AUTOSYNC_FROM_MADI 1 323 #define HDSPM_AUTOSYNC_FROM_TCO 2 324 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 325 #define HDSPM_AUTOSYNC_FROM_NONE 4 326 327 /* Possible sources of MADI input */ 328 #define HDSPM_OPTICAL 0 /* optical */ 329 #define HDSPM_COAXIAL 1 /* BNC */ 330 331 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 332 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 333 334 #define hdspm_encode_in(x) (((x)&0x3)<<14) 335 #define hdspm_decode_in(x) (((x)>>14)&0x3) 336 337 /* --- control2 register bits --- */ 338 #define HDSPM_TMS (1<<0) 339 #define HDSPM_TCK (1<<1) 340 #define HDSPM_TDI (1<<2) 341 #define HDSPM_JTAG (1<<3) 342 #define HDSPM_PWDN (1<<4) 343 #define HDSPM_PROGRAM (1<<5) 344 #define HDSPM_CONFIG_MODE_0 (1<<6) 345 #define HDSPM_CONFIG_MODE_1 (1<<7) 346 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 347 #define HDSPM_BIGENDIAN_MODE (1<<9) 348 #define HDSPM_RD_MULTIPLE (1<<10) 349 350 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 351 that do not conflict with specific bits for AES32 seem to be valid also 352 for the AES32 353 */ 354 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 355 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 356 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 357 * (like inp0) 358 */ 359 360 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 361 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 362 363 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 364 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 365 366 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 367 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 368 369 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 370 /* since 64byte accurate, last 6 bits are not used */ 371 372 373 374 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 375 376 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 377 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 378 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 379 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 380 381 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 382 * Interrupt 383 */ 384 #define HDSPM_tco_detect 0x08000000 385 #define HDSPM_tco_lock 0x20000000 386 387 #define HDSPM_s2_tco_detect 0x00000040 388 #define HDSPM_s2_AEBO_D 0x00000080 389 #define HDSPM_s2_AEBI_D 0x00000100 390 391 392 #define HDSPM_midi0IRQPending 0x40000000 393 #define HDSPM_midi1IRQPending 0x80000000 394 #define HDSPM_midi2IRQPending 0x20000000 395 #define HDSPM_midi2IRQPendingAES 0x00000020 396 #define HDSPM_midi3IRQPending 0x00200000 397 398 /* --- status bit helpers */ 399 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 400 HDSPM_madiFreq2|HDSPM_madiFreq3) 401 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 402 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 403 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 404 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 405 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 406 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 407 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 408 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 409 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 410 411 /* Status2 Register bits */ /* MADI ONLY */ 412 413 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 414 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 415 #define HDSPM_version2 (1<<2) 416 417 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 418 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 419 420 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 421 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 422 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 423 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 424 425 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 426 #define HDSPM_SyncRef1 0x20000 427 428 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 429 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 430 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 431 432 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 433 434 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 435 HDSPM_wc_freq3) 436 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 437 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 438 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 439 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 440 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 441 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 442 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 443 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 444 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 445 446 #define HDSPM_status1_F_0 0x0400000 447 #define HDSPM_status1_F_1 0x0800000 448 #define HDSPM_status1_F_2 0x1000000 449 #define HDSPM_status1_F_3 0x2000000 450 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 451 452 453 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 454 HDSPM_SelSyncRef2) 455 #define HDSPM_SelSyncRef_WORD 0 456 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 457 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 458 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 459 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 460 HDSPM_SelSyncRef2) 461 462 /* 463 For AES32, bits for status, status2 and timecode are different 464 */ 465 /* status */ 466 #define HDSPM_AES32_wcLock 0x0200000 467 #define HDSPM_AES32_wcSync 0x0100000 468 #define HDSPM_AES32_wcFreq_bit 22 469 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 470 HDSPM_bit2freq */ 471 #define HDSPM_AES32_syncref_bit 16 472 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 473 474 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 475 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 476 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 477 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 478 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 479 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 480 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 481 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 482 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 483 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 484 485 /* status2 */ 486 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 487 #define HDSPM_LockAES 0x80 488 #define HDSPM_LockAES1 0x80 489 #define HDSPM_LockAES2 0x40 490 #define HDSPM_LockAES3 0x20 491 #define HDSPM_LockAES4 0x10 492 #define HDSPM_LockAES5 0x8 493 #define HDSPM_LockAES6 0x4 494 #define HDSPM_LockAES7 0x2 495 #define HDSPM_LockAES8 0x1 496 /* 497 Timecode 498 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 499 AES i+1 500 bits 3210 501 0001 32kHz 502 0010 44.1kHz 503 0011 48kHz 504 0100 64kHz 505 0101 88.2kHz 506 0110 96kHz 507 0111 128kHz 508 1000 176.4kHz 509 1001 192kHz 510 NB: Timecode register doesn't seem to work on AES32 card revision 230 511 */ 512 513 /* Mixer Values */ 514 #define UNITY_GAIN 32768 /* = 65536/2 */ 515 #define MINUS_INFINITY_GAIN 0 516 517 /* Number of channels for different Speed Modes */ 518 #define MADI_SS_CHANNELS 64 519 #define MADI_DS_CHANNELS 32 520 #define MADI_QS_CHANNELS 16 521 522 #define RAYDAT_SS_CHANNELS 36 523 #define RAYDAT_DS_CHANNELS 20 524 #define RAYDAT_QS_CHANNELS 12 525 526 #define AIO_IN_SS_CHANNELS 14 527 #define AIO_IN_DS_CHANNELS 10 528 #define AIO_IN_QS_CHANNELS 8 529 #define AIO_OUT_SS_CHANNELS 16 530 #define AIO_OUT_DS_CHANNELS 12 531 #define AIO_OUT_QS_CHANNELS 10 532 533 #define AES32_CHANNELS 16 534 535 /* the size of a substream (1 mono data stream) */ 536 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 537 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 538 539 /* the size of the area we need to allocate for DMA transfers. the 540 size is the same regardless of the number of channels, and 541 also the latency to use. 542 for one direction !!! 543 */ 544 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 545 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 546 547 #define HDSPM_RAYDAT_REV 211 548 #define HDSPM_AIO_REV 212 549 #define HDSPM_MADIFACE_REV 213 550 551 /* speed factor modes */ 552 #define HDSPM_SPEED_SINGLE 0 553 #define HDSPM_SPEED_DOUBLE 1 554 #define HDSPM_SPEED_QUAD 2 555 556 /* names for speed modes */ 557 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 558 559 static char *texts_autosync_aes_tco[] = { "Word Clock", 560 "AES1", "AES2", "AES3", "AES4", 561 "AES5", "AES6", "AES7", "AES8", 562 "TCO" }; 563 static char *texts_autosync_aes[] = { "Word Clock", 564 "AES1", "AES2", "AES3", "AES4", 565 "AES5", "AES6", "AES7", "AES8" }; 566 static char *texts_autosync_madi_tco[] = { "Word Clock", 567 "MADI", "TCO", "Sync In" }; 568 static char *texts_autosync_madi[] = { "Word Clock", 569 "MADI", "Sync In" }; 570 571 static char *texts_autosync_raydat_tco[] = { 572 "Word Clock", 573 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 574 "AES", "SPDIF", "TCO", "Sync In" 575 }; 576 static char *texts_autosync_raydat[] = { 577 "Word Clock", 578 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 579 "AES", "SPDIF", "Sync In" 580 }; 581 static char *texts_autosync_aio_tco[] = { 582 "Word Clock", 583 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 584 }; 585 static char *texts_autosync_aio[] = { "Word Clock", 586 "ADAT", "AES", "SPDIF", "Sync In" }; 587 588 static char *texts_freq[] = { 589 "No Lock", 590 "32 kHz", 591 "44.1 kHz", 592 "48 kHz", 593 "64 kHz", 594 "88.2 kHz", 595 "96 kHz", 596 "128 kHz", 597 "176.4 kHz", 598 "192 kHz" 599 }; 600 601 static char *texts_ports_madi[] = { 602 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 603 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 604 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 605 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 606 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 607 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 608 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 609 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 610 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 611 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 612 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 613 }; 614 615 616 static char *texts_ports_raydat_ss[] = { 617 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 618 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 619 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 620 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 621 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 622 "ADAT4.7", "ADAT4.8", 623 "AES.L", "AES.R", 624 "SPDIF.L", "SPDIF.R" 625 }; 626 627 static char *texts_ports_raydat_ds[] = { 628 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 629 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 630 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 631 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 632 "AES.L", "AES.R", 633 "SPDIF.L", "SPDIF.R" 634 }; 635 636 static char *texts_ports_raydat_qs[] = { 637 "ADAT1.1", "ADAT1.2", 638 "ADAT2.1", "ADAT2.2", 639 "ADAT3.1", "ADAT3.2", 640 "ADAT4.1", "ADAT4.2", 641 "AES.L", "AES.R", 642 "SPDIF.L", "SPDIF.R" 643 }; 644 645 646 static char *texts_ports_aio_in_ss[] = { 647 "Analogue.L", "Analogue.R", 648 "AES.L", "AES.R", 649 "SPDIF.L", "SPDIF.R", 650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 651 "ADAT.7", "ADAT.8" 652 }; 653 654 static char *texts_ports_aio_out_ss[] = { 655 "Analogue.L", "Analogue.R", 656 "AES.L", "AES.R", 657 "SPDIF.L", "SPDIF.R", 658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 659 "ADAT.7", "ADAT.8", 660 "Phone.L", "Phone.R" 661 }; 662 663 static char *texts_ports_aio_in_ds[] = { 664 "Analogue.L", "Analogue.R", 665 "AES.L", "AES.R", 666 "SPDIF.L", "SPDIF.R", 667 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 668 }; 669 670 static char *texts_ports_aio_out_ds[] = { 671 "Analogue.L", "Analogue.R", 672 "AES.L", "AES.R", 673 "SPDIF.L", "SPDIF.R", 674 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 675 "Phone.L", "Phone.R" 676 }; 677 678 static char *texts_ports_aio_in_qs[] = { 679 "Analogue.L", "Analogue.R", 680 "AES.L", "AES.R", 681 "SPDIF.L", "SPDIF.R", 682 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 683 }; 684 685 static char *texts_ports_aio_out_qs[] = { 686 "Analogue.L", "Analogue.R", 687 "AES.L", "AES.R", 688 "SPDIF.L", "SPDIF.R", 689 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 690 "Phone.L", "Phone.R" 691 }; 692 693 static char *texts_ports_aes32[] = { 694 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 695 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 696 "AES.15", "AES.16" 697 }; 698 699 /* These tables map the ALSA channels 1..N to the channels that we 700 need to use in order to find the relevant channel buffer. RME 701 refers to this kind of mapping as between "the ADAT channel and 702 the DMA channel." We index it using the logical audio channel, 703 and the value is the DMA channel (i.e. channel buffer number) 704 where the data for that channel can be read/written from/to. 705 */ 706 707 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 708 0, 1, 2, 3, 4, 5, 6, 7, 709 8, 9, 10, 11, 12, 13, 14, 15, 710 16, 17, 18, 19, 20, 21, 22, 23, 711 24, 25, 26, 27, 28, 29, 30, 31, 712 32, 33, 34, 35, 36, 37, 38, 39, 713 40, 41, 42, 43, 44, 45, 46, 47, 714 48, 49, 50, 51, 52, 53, 54, 55, 715 56, 57, 58, 59, 60, 61, 62, 63 716 }; 717 718 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 719 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 720 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 721 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 722 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 723 0, 1, /* AES */ 724 2, 3, /* SPDIF */ 725 -1, -1, -1, -1, 726 -1, -1, -1, -1, -1, -1, -1, -1, 727 -1, -1, -1, -1, -1, -1, -1, -1, 728 -1, -1, -1, -1, -1, -1, -1, -1, 729 }; 730 731 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 732 4, 5, 6, 7, /* ADAT 1 */ 733 8, 9, 10, 11, /* ADAT 2 */ 734 12, 13, 14, 15, /* ADAT 3 */ 735 16, 17, 18, 19, /* ADAT 4 */ 736 0, 1, /* AES */ 737 2, 3, /* SPDIF */ 738 -1, -1, -1, -1, 739 -1, -1, -1, -1, -1, -1, -1, -1, 740 -1, -1, -1, -1, -1, -1, -1, -1, 741 -1, -1, -1, -1, -1, -1, -1, -1, 742 -1, -1, -1, -1, -1, -1, -1, -1, 743 -1, -1, -1, -1, -1, -1, -1, -1, 744 }; 745 746 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 747 4, 5, /* ADAT 1 */ 748 6, 7, /* ADAT 2 */ 749 8, 9, /* ADAT 3 */ 750 10, 11, /* ADAT 4 */ 751 0, 1, /* AES */ 752 2, 3, /* SPDIF */ 753 -1, -1, -1, -1, 754 -1, -1, -1, -1, -1, -1, -1, -1, 755 -1, -1, -1, -1, -1, -1, -1, -1, 756 -1, -1, -1, -1, -1, -1, -1, -1, 757 -1, -1, -1, -1, -1, -1, -1, -1, 758 -1, -1, -1, -1, -1, -1, -1, -1, 759 -1, -1, -1, -1, -1, -1, -1, -1, 760 }; 761 762 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 763 0, 1, /* line in */ 764 8, 9, /* aes in, */ 765 10, 11, /* spdif in */ 766 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 767 -1, -1, 768 -1, -1, -1, -1, -1, -1, -1, -1, 769 -1, -1, -1, -1, -1, -1, -1, -1, 770 -1, -1, -1, -1, -1, -1, -1, -1, 771 -1, -1, -1, -1, -1, -1, -1, -1, 772 -1, -1, -1, -1, -1, -1, -1, -1, 773 -1, -1, -1, -1, -1, -1, -1, -1, 774 }; 775 776 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 777 0, 1, /* line out */ 778 8, 9, /* aes out */ 779 10, 11, /* spdif out */ 780 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 781 6, 7, /* phone out */ 782 -1, -1, -1, -1, -1, -1, -1, -1, 783 -1, -1, -1, -1, -1, -1, -1, -1, 784 -1, -1, -1, -1, -1, -1, -1, -1, 785 -1, -1, -1, -1, -1, -1, -1, -1, 786 -1, -1, -1, -1, -1, -1, -1, -1, 787 -1, -1, -1, -1, -1, -1, -1, -1, 788 }; 789 790 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 791 0, 1, /* line in */ 792 8, 9, /* aes in */ 793 10, 11, /* spdif in */ 794 12, 14, 16, 18, /* adat in */ 795 -1, -1, -1, -1, -1, -1, 796 -1, -1, -1, -1, -1, -1, -1, -1, 797 -1, -1, -1, -1, -1, -1, -1, -1, 798 -1, -1, -1, -1, -1, -1, -1, -1, 799 -1, -1, -1, -1, -1, -1, -1, -1, 800 -1, -1, -1, -1, -1, -1, -1, -1, 801 -1, -1, -1, -1, -1, -1, -1, -1 802 }; 803 804 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 805 0, 1, /* line out */ 806 8, 9, /* aes out */ 807 10, 11, /* spdif out */ 808 12, 14, 16, 18, /* adat out */ 809 6, 7, /* phone out */ 810 -1, -1, -1, -1, 811 -1, -1, -1, -1, -1, -1, -1, -1, 812 -1, -1, -1, -1, -1, -1, -1, -1, 813 -1, -1, -1, -1, -1, -1, -1, -1, 814 -1, -1, -1, -1, -1, -1, -1, -1, 815 -1, -1, -1, -1, -1, -1, -1, -1, 816 -1, -1, -1, -1, -1, -1, -1, -1 817 }; 818 819 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 820 0, 1, /* line in */ 821 8, 9, /* aes in */ 822 10, 11, /* spdif in */ 823 12, 16, /* adat in */ 824 -1, -1, -1, -1, -1, -1, -1, -1, 825 -1, -1, -1, -1, -1, -1, -1, -1, 826 -1, -1, -1, -1, -1, -1, -1, -1, 827 -1, -1, -1, -1, -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1 831 }; 832 833 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 834 0, 1, /* line out */ 835 8, 9, /* aes out */ 836 10, 11, /* spdif out */ 837 12, 16, /* adat out */ 838 6, 7, /* phone out */ 839 -1, -1, -1, -1, -1, -1, 840 -1, -1, -1, -1, -1, -1, -1, -1, 841 -1, -1, -1, -1, -1, -1, -1, -1, 842 -1, -1, -1, -1, -1, -1, -1, -1, 843 -1, -1, -1, -1, -1, -1, -1, -1, 844 -1, -1, -1, -1, -1, -1, -1, -1, 845 -1, -1, -1, -1, -1, -1, -1, -1 846 }; 847 848 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 849 0, 1, 2, 3, 4, 5, 6, 7, 850 8, 9, 10, 11, 12, 13, 14, 15, 851 -1, -1, -1, -1, -1, -1, -1, -1, 852 -1, -1, -1, -1, -1, -1, -1, -1, 853 -1, -1, -1, -1, -1, -1, -1, -1, 854 -1, -1, -1, -1, -1, -1, -1, -1, 855 -1, -1, -1, -1, -1, -1, -1, -1, 856 -1, -1, -1, -1, -1, -1, -1, -1 857 }; 858 859 struct hdspm_midi { 860 struct hdspm *hdspm; 861 int id; 862 struct snd_rawmidi *rmidi; 863 struct snd_rawmidi_substream *input; 864 struct snd_rawmidi_substream *output; 865 char istimer; /* timer in use */ 866 struct timer_list timer; 867 spinlock_t lock; 868 int pending; 869 int dataIn; 870 int statusIn; 871 int dataOut; 872 int statusOut; 873 int ie; 874 int irq; 875 }; 876 877 struct hdspm_tco { 878 int input; 879 int framerate; 880 int wordclock; 881 int samplerate; 882 int pull; 883 int term; /* 0 = off, 1 = on */ 884 }; 885 886 struct hdspm { 887 spinlock_t lock; 888 /* only one playback and/or capture stream */ 889 struct snd_pcm_substream *capture_substream; 890 struct snd_pcm_substream *playback_substream; 891 892 char *card_name; /* for procinfo */ 893 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 894 895 uint8_t io_type; 896 897 int monitor_outs; /* set up monitoring outs init flag */ 898 899 u32 control_register; /* cached value */ 900 u32 control2_register; /* cached value */ 901 u32 settings_register; 902 903 struct hdspm_midi midi[4]; 904 struct tasklet_struct midi_tasklet; 905 906 size_t period_bytes; 907 unsigned char ss_in_channels; 908 unsigned char ds_in_channels; 909 unsigned char qs_in_channels; 910 unsigned char ss_out_channels; 911 unsigned char ds_out_channels; 912 unsigned char qs_out_channels; 913 914 unsigned char max_channels_in; 915 unsigned char max_channels_out; 916 917 signed char *channel_map_in; 918 signed char *channel_map_out; 919 920 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 921 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 922 923 char **port_names_in; 924 char **port_names_out; 925 926 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 927 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 928 929 unsigned char *playback_buffer; /* suitably aligned address */ 930 unsigned char *capture_buffer; /* suitably aligned address */ 931 932 pid_t capture_pid; /* process id which uses capture */ 933 pid_t playback_pid; /* process id which uses capture */ 934 int running; /* running status */ 935 936 int last_external_sample_rate; /* samplerate mystic ... */ 937 int last_internal_sample_rate; 938 int system_sample_rate; 939 940 int dev; /* Hardware vars... */ 941 int irq; 942 unsigned long port; 943 void __iomem *iobase; 944 945 int irq_count; /* for debug */ 946 int midiPorts; 947 948 struct snd_card *card; /* one card */ 949 struct snd_pcm *pcm; /* has one pcm */ 950 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 951 struct pci_dev *pci; /* and an pci info */ 952 953 /* Mixer vars */ 954 /* fast alsa mixer */ 955 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 956 /* but input to much, so not used */ 957 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 958 /* full mixer accessible over mixer ioctl or hwdep-device */ 959 struct hdspm_mixer *mixer; 960 961 struct hdspm_tco *tco; /* NULL if no TCO detected */ 962 963 char **texts_autosync; 964 int texts_autosync_items; 965 966 cycles_t last_interrupt; 967 968 unsigned int serial; 969 970 struct hdspm_peak_rms peak_rms; 971 }; 972 973 974 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 975 { 976 .vendor = PCI_VENDOR_ID_XILINX, 977 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 978 .subvendor = PCI_ANY_ID, 979 .subdevice = PCI_ANY_ID, 980 .class = 0, 981 .class_mask = 0, 982 .driver_data = 0}, 983 {0,} 984 }; 985 986 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 987 988 /* prototypes */ 989 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 990 struct hdspm *hdspm); 991 static int snd_hdspm_create_pcm(struct snd_card *card, 992 struct hdspm *hdspm); 993 994 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 995 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 996 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 997 static int hdspm_autosync_ref(struct hdspm *hdspm); 998 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 999 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1000 static void hdspm_set_sgbuf(struct hdspm *hdspm, 1001 struct snd_pcm_substream *substream, 1002 unsigned int reg, int channels); 1003 1004 static inline int HDSPM_bit2freq(int n) 1005 { 1006 static const int bit2freq_tab[] = { 1007 0, 32000, 44100, 48000, 64000, 88200, 1008 96000, 128000, 176400, 192000 }; 1009 if (n < 1 || n > 9) 1010 return 0; 1011 return bit2freq_tab[n]; 1012 } 1013 1014 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1015 { 1016 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1017 } 1018 1019 1020 /* Write/read to/from HDSPM with Adresses in Bytes 1021 not words but only 32Bit writes are allowed */ 1022 1023 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1024 unsigned int val) 1025 { 1026 writel(val, hdspm->iobase + reg); 1027 } 1028 1029 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1030 { 1031 return readl(hdspm->iobase + reg); 1032 } 1033 1034 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1035 mixer is write only on hardware so we have to cache him for read 1036 each fader is a u32, but uses only the first 16 bit */ 1037 1038 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1039 unsigned int in) 1040 { 1041 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1042 return 0; 1043 1044 return hdspm->mixer->ch[chan].in[in]; 1045 } 1046 1047 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1048 unsigned int pb) 1049 { 1050 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1051 return 0; 1052 return hdspm->mixer->ch[chan].pb[pb]; 1053 } 1054 1055 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1056 unsigned int in, unsigned short data) 1057 { 1058 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1059 return -1; 1060 1061 hdspm_write(hdspm, 1062 HDSPM_MADI_mixerBase + 1063 ((in + 128 * chan) * sizeof(u32)), 1064 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1065 return 0; 1066 } 1067 1068 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1069 unsigned int pb, unsigned short data) 1070 { 1071 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1072 return -1; 1073 1074 hdspm_write(hdspm, 1075 HDSPM_MADI_mixerBase + 1076 ((64 + pb + 128 * chan) * sizeof(u32)), 1077 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1078 return 0; 1079 } 1080 1081 1082 /* enable DMA for specific channels, now available for DSP-MADI */ 1083 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1084 { 1085 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1086 } 1087 1088 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1089 { 1090 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1091 } 1092 1093 /* check if same process is writing and reading */ 1094 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1095 { 1096 unsigned long flags; 1097 int ret = 1; 1098 1099 spin_lock_irqsave(&hdspm->lock, flags); 1100 if ((hdspm->playback_pid != hdspm->capture_pid) && 1101 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1102 ret = 0; 1103 } 1104 spin_unlock_irqrestore(&hdspm->lock, flags); 1105 return ret; 1106 } 1107 1108 /* round arbitary sample rates to commonly known rates */ 1109 static int hdspm_round_frequency(int rate) 1110 { 1111 if (rate < 38050) 1112 return 32000; 1113 if (rate < 46008) 1114 return 44100; 1115 else 1116 return 48000; 1117 } 1118 1119 /* QS and DS rates normally can not be detected 1120 * automatically by the card. Only exception is MADI 1121 * in 96k frame mode. 1122 * 1123 * So if we read SS values (32 .. 48k), check for 1124 * user-provided DS/QS bits in the control register 1125 * and multiply the base frequency accordingly. 1126 */ 1127 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1128 { 1129 if (rate <= 48000) { 1130 if (hdspm->control_register & HDSPM_QuadSpeed) 1131 return rate * 4; 1132 else if (hdspm->control_register & 1133 HDSPM_DoubleSpeed) 1134 return rate * 2; 1135 }; 1136 return rate; 1137 } 1138 1139 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1140 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1141 1142 /* check for external sample rate */ 1143 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1144 { 1145 unsigned int status, status2, timecode; 1146 int syncref, rate = 0, rate_bits; 1147 1148 switch (hdspm->io_type) { 1149 case AES32: 1150 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1151 status = hdspm_read(hdspm, HDSPM_statusRegister); 1152 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1153 1154 syncref = hdspm_autosync_ref(hdspm); 1155 1156 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1157 status & HDSPM_AES32_wcLock) 1158 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1159 1160 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1161 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1162 status2 & (HDSPM_LockAES >> 1163 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1164 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1165 return 0; 1166 break; 1167 1168 case MADIface: 1169 status = hdspm_read(hdspm, HDSPM_statusRegister); 1170 1171 if (!(status & HDSPM_madiLock)) { 1172 rate = 0; /* no lock */ 1173 } else { 1174 switch (status & (HDSPM_status1_freqMask)) { 1175 case HDSPM_status1_F_0*1: 1176 rate = 32000; break; 1177 case HDSPM_status1_F_0*2: 1178 rate = 44100; break; 1179 case HDSPM_status1_F_0*3: 1180 rate = 48000; break; 1181 case HDSPM_status1_F_0*4: 1182 rate = 64000; break; 1183 case HDSPM_status1_F_0*5: 1184 rate = 88200; break; 1185 case HDSPM_status1_F_0*6: 1186 rate = 96000; break; 1187 case HDSPM_status1_F_0*7: 1188 rate = 128000; break; 1189 case HDSPM_status1_F_0*8: 1190 rate = 176400; break; 1191 case HDSPM_status1_F_0*9: 1192 rate = 192000; break; 1193 default: 1194 rate = 0; break; 1195 } 1196 } 1197 1198 break; 1199 1200 case MADI: 1201 case AIO: 1202 case RayDAT: 1203 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1204 status = hdspm_read(hdspm, HDSPM_statusRegister); 1205 rate = 0; 1206 1207 /* if wordclock has synced freq and wordclock is valid */ 1208 if ((status2 & HDSPM_wcLock) != 0 && 1209 (status2 & HDSPM_SelSyncRef0) == 0) { 1210 1211 rate_bits = status2 & HDSPM_wcFreqMask; 1212 1213 1214 switch (rate_bits) { 1215 case HDSPM_wcFreq32: 1216 rate = 32000; 1217 break; 1218 case HDSPM_wcFreq44_1: 1219 rate = 44100; 1220 break; 1221 case HDSPM_wcFreq48: 1222 rate = 48000; 1223 break; 1224 case HDSPM_wcFreq64: 1225 rate = 64000; 1226 break; 1227 case HDSPM_wcFreq88_2: 1228 rate = 88200; 1229 break; 1230 case HDSPM_wcFreq96: 1231 rate = 96000; 1232 break; 1233 case HDSPM_wcFreq128: 1234 rate = 128000; 1235 break; 1236 case HDSPM_wcFreq176_4: 1237 rate = 176400; 1238 break; 1239 case HDSPM_wcFreq192: 1240 rate = 192000; 1241 break; 1242 default: 1243 rate = 0; 1244 break; 1245 } 1246 } 1247 1248 /* if rate detected and Syncref is Word than have it, 1249 * word has priority to MADI 1250 */ 1251 if (rate != 0 && 1252 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1253 return hdspm_rate_multiplier(hdspm, rate); 1254 1255 /* maybe a madi input (which is taken if sel sync is madi) */ 1256 if (status & HDSPM_madiLock) { 1257 rate_bits = status & HDSPM_madiFreqMask; 1258 1259 switch (rate_bits) { 1260 case HDSPM_madiFreq32: 1261 rate = 32000; 1262 break; 1263 case HDSPM_madiFreq44_1: 1264 rate = 44100; 1265 break; 1266 case HDSPM_madiFreq48: 1267 rate = 48000; 1268 break; 1269 case HDSPM_madiFreq64: 1270 rate = 64000; 1271 break; 1272 case HDSPM_madiFreq88_2: 1273 rate = 88200; 1274 break; 1275 case HDSPM_madiFreq96: 1276 rate = 96000; 1277 break; 1278 case HDSPM_madiFreq128: 1279 rate = 128000; 1280 break; 1281 case HDSPM_madiFreq176_4: 1282 rate = 176400; 1283 break; 1284 case HDSPM_madiFreq192: 1285 rate = 192000; 1286 break; 1287 default: 1288 rate = 0; 1289 break; 1290 } 1291 1292 } /* endif HDSPM_madiLock */ 1293 1294 /* check sample rate from TCO or SYNC_IN */ 1295 { 1296 bool is_valid_input = 0; 1297 bool has_sync = 0; 1298 1299 syncref = hdspm_autosync_ref(hdspm); 1300 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1301 is_valid_input = 1; 1302 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1303 hdspm_tco_sync_check(hdspm)); 1304 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1305 is_valid_input = 1; 1306 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1307 hdspm_sync_in_sync_check(hdspm)); 1308 } 1309 1310 if (is_valid_input && has_sync) { 1311 rate = hdspm_round_frequency( 1312 hdspm_get_pll_freq(hdspm)); 1313 } 1314 } 1315 1316 rate = hdspm_rate_multiplier(hdspm, rate); 1317 1318 break; 1319 } 1320 1321 return rate; 1322 } 1323 1324 /* return latency in samples per period */ 1325 static int hdspm_get_latency(struct hdspm *hdspm) 1326 { 1327 int n; 1328 1329 n = hdspm_decode_latency(hdspm->control_register); 1330 1331 /* Special case for new RME cards with 32 samples period size. 1332 * The three latency bits in the control register 1333 * (HDSP_LatencyMask) encode latency values of 64 samples as 1334 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1335 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1336 * it corresponds to 32 samples. 1337 */ 1338 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1339 n = -1; 1340 1341 return 1 << (n + 6); 1342 } 1343 1344 /* Latency function */ 1345 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1346 { 1347 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1348 } 1349 1350 1351 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1352 { 1353 int position; 1354 1355 position = hdspm_read(hdspm, HDSPM_statusRegister); 1356 1357 switch (hdspm->io_type) { 1358 case RayDAT: 1359 case AIO: 1360 position &= HDSPM_BufferPositionMask; 1361 position /= 4; /* Bytes per sample */ 1362 break; 1363 default: 1364 position = (position & HDSPM_BufferID) ? 1365 (hdspm->period_bytes / 4) : 0; 1366 } 1367 1368 return position; 1369 } 1370 1371 1372 static inline void hdspm_start_audio(struct hdspm * s) 1373 { 1374 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1375 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1376 } 1377 1378 static inline void hdspm_stop_audio(struct hdspm * s) 1379 { 1380 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1381 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1382 } 1383 1384 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1385 static void hdspm_silence_playback(struct hdspm *hdspm) 1386 { 1387 int i; 1388 int n = hdspm->period_bytes; 1389 void *buf = hdspm->playback_buffer; 1390 1391 if (buf == NULL) 1392 return; 1393 1394 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1395 memset(buf, 0, n); 1396 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1397 } 1398 } 1399 1400 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1401 { 1402 int n; 1403 1404 spin_lock_irq(&s->lock); 1405 1406 if (32 == frames) { 1407 /* Special case for new RME cards like RayDAT/AIO which 1408 * support period sizes of 32 samples. Since latency is 1409 * encoded in the three bits of HDSP_LatencyMask, we can only 1410 * have values from 0 .. 7. While 0 still means 64 samples and 1411 * 6 represents 4096 samples on all cards, 7 represents 8192 1412 * on older cards and 32 samples on new cards. 1413 * 1414 * In other words, period size in samples is calculated by 1415 * 2^(n+6) with n ranging from 0 .. 7. 1416 */ 1417 n = 7; 1418 } else { 1419 frames >>= 7; 1420 n = 0; 1421 while (frames) { 1422 n++; 1423 frames >>= 1; 1424 } 1425 } 1426 1427 s->control_register &= ~HDSPM_LatencyMask; 1428 s->control_register |= hdspm_encode_latency(n); 1429 1430 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1431 1432 hdspm_compute_period_size(s); 1433 1434 spin_unlock_irq(&s->lock); 1435 1436 return 0; 1437 } 1438 1439 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1440 { 1441 u64 freq_const; 1442 1443 if (period == 0) 1444 return 0; 1445 1446 switch (hdspm->io_type) { 1447 case MADI: 1448 case AES32: 1449 freq_const = 110069313433624ULL; 1450 break; 1451 case RayDAT: 1452 case AIO: 1453 freq_const = 104857600000000ULL; 1454 break; 1455 case MADIface: 1456 freq_const = 131072000000000ULL; 1457 break; 1458 default: 1459 snd_BUG(); 1460 return 0; 1461 } 1462 1463 return div_u64(freq_const, period); 1464 } 1465 1466 1467 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1468 { 1469 u64 n; 1470 1471 if (rate >= 112000) 1472 rate /= 4; 1473 else if (rate >= 56000) 1474 rate /= 2; 1475 1476 switch (hdspm->io_type) { 1477 case MADIface: 1478 n = 131072000000000ULL; /* 125 MHz */ 1479 break; 1480 case MADI: 1481 case AES32: 1482 n = 110069313433624ULL; /* 105 MHz */ 1483 break; 1484 case RayDAT: 1485 case AIO: 1486 n = 104857600000000ULL; /* 100 MHz */ 1487 break; 1488 default: 1489 snd_BUG(); 1490 return; 1491 } 1492 1493 n = div_u64(n, rate); 1494 /* n should be less than 2^32 for being written to FREQ register */ 1495 snd_BUG_ON(n >> 32); 1496 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1497 } 1498 1499 /* dummy set rate lets see what happens */ 1500 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1501 { 1502 int current_rate; 1503 int rate_bits; 1504 int not_set = 0; 1505 int current_speed, target_speed; 1506 1507 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1508 it (e.g. during module initialization). 1509 */ 1510 1511 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1512 1513 /* SLAVE --- */ 1514 if (called_internally) { 1515 1516 /* request from ctl or card initialization 1517 just make a warning an remember setting 1518 for future master mode switching */ 1519 1520 snd_printk(KERN_WARNING "HDSPM: " 1521 "Warning: device is not running " 1522 "as a clock master.\n"); 1523 not_set = 1; 1524 } else { 1525 1526 /* hw_param request while in AutoSync mode */ 1527 int external_freq = 1528 hdspm_external_sample_rate(hdspm); 1529 1530 if (hdspm_autosync_ref(hdspm) == 1531 HDSPM_AUTOSYNC_FROM_NONE) { 1532 1533 snd_printk(KERN_WARNING "HDSPM: " 1534 "Detected no Externel Sync \n"); 1535 not_set = 1; 1536 1537 } else if (rate != external_freq) { 1538 1539 snd_printk(KERN_WARNING "HDSPM: " 1540 "Warning: No AutoSync source for " 1541 "requested rate\n"); 1542 not_set = 1; 1543 } 1544 } 1545 } 1546 1547 current_rate = hdspm->system_sample_rate; 1548 1549 /* Changing between Singe, Double and Quad speed is not 1550 allowed if any substreams are open. This is because such a change 1551 causes a shift in the location of the DMA buffers and a reduction 1552 in the number of available buffers. 1553 1554 Note that a similar but essentially insoluble problem exists for 1555 externally-driven rate changes. All we can do is to flag rate 1556 changes in the read/write routines. 1557 */ 1558 1559 if (current_rate <= 48000) 1560 current_speed = HDSPM_SPEED_SINGLE; 1561 else if (current_rate <= 96000) 1562 current_speed = HDSPM_SPEED_DOUBLE; 1563 else 1564 current_speed = HDSPM_SPEED_QUAD; 1565 1566 if (rate <= 48000) 1567 target_speed = HDSPM_SPEED_SINGLE; 1568 else if (rate <= 96000) 1569 target_speed = HDSPM_SPEED_DOUBLE; 1570 else 1571 target_speed = HDSPM_SPEED_QUAD; 1572 1573 switch (rate) { 1574 case 32000: 1575 rate_bits = HDSPM_Frequency32KHz; 1576 break; 1577 case 44100: 1578 rate_bits = HDSPM_Frequency44_1KHz; 1579 break; 1580 case 48000: 1581 rate_bits = HDSPM_Frequency48KHz; 1582 break; 1583 case 64000: 1584 rate_bits = HDSPM_Frequency64KHz; 1585 break; 1586 case 88200: 1587 rate_bits = HDSPM_Frequency88_2KHz; 1588 break; 1589 case 96000: 1590 rate_bits = HDSPM_Frequency96KHz; 1591 break; 1592 case 128000: 1593 rate_bits = HDSPM_Frequency128KHz; 1594 break; 1595 case 176400: 1596 rate_bits = HDSPM_Frequency176_4KHz; 1597 break; 1598 case 192000: 1599 rate_bits = HDSPM_Frequency192KHz; 1600 break; 1601 default: 1602 return -EINVAL; 1603 } 1604 1605 if (current_speed != target_speed 1606 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1607 snd_printk 1608 (KERN_ERR "HDSPM: " 1609 "cannot change from %s speed to %s speed mode " 1610 "(capture PID = %d, playback PID = %d)\n", 1611 hdspm_speed_names[current_speed], 1612 hdspm_speed_names[target_speed], 1613 hdspm->capture_pid, hdspm->playback_pid); 1614 return -EBUSY; 1615 } 1616 1617 hdspm->control_register &= ~HDSPM_FrequencyMask; 1618 hdspm->control_register |= rate_bits; 1619 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1620 1621 /* For AES32, need to set DDS value in FREQ register 1622 For MADI, also apparently */ 1623 hdspm_set_dds_value(hdspm, rate); 1624 1625 if (AES32 == hdspm->io_type && rate != current_rate) 1626 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1627 1628 hdspm->system_sample_rate = rate; 1629 1630 if (rate <= 48000) { 1631 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1632 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1633 hdspm->max_channels_in = hdspm->ss_in_channels; 1634 hdspm->max_channels_out = hdspm->ss_out_channels; 1635 hdspm->port_names_in = hdspm->port_names_in_ss; 1636 hdspm->port_names_out = hdspm->port_names_out_ss; 1637 } else if (rate <= 96000) { 1638 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1639 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1640 hdspm->max_channels_in = hdspm->ds_in_channels; 1641 hdspm->max_channels_out = hdspm->ds_out_channels; 1642 hdspm->port_names_in = hdspm->port_names_in_ds; 1643 hdspm->port_names_out = hdspm->port_names_out_ds; 1644 } else { 1645 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1646 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1647 hdspm->max_channels_in = hdspm->qs_in_channels; 1648 hdspm->max_channels_out = hdspm->qs_out_channels; 1649 hdspm->port_names_in = hdspm->port_names_in_qs; 1650 hdspm->port_names_out = hdspm->port_names_out_qs; 1651 } 1652 1653 if (not_set != 0) 1654 return -1; 1655 1656 return 0; 1657 } 1658 1659 /* mainly for init to 0 on load */ 1660 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1661 { 1662 int i, j; 1663 unsigned int gain; 1664 1665 if (sgain > UNITY_GAIN) 1666 gain = UNITY_GAIN; 1667 else if (sgain < 0) 1668 gain = 0; 1669 else 1670 gain = sgain; 1671 1672 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1673 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1674 hdspm_write_in_gain(hdspm, i, j, gain); 1675 hdspm_write_pb_gain(hdspm, i, j, gain); 1676 } 1677 } 1678 1679 /*---------------------------------------------------------------------------- 1680 MIDI 1681 ----------------------------------------------------------------------------*/ 1682 1683 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1684 int id) 1685 { 1686 /* the hardware already does the relevant bit-mask with 0xff */ 1687 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1688 } 1689 1690 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1691 int val) 1692 { 1693 /* the hardware already does the relevant bit-mask with 0xff */ 1694 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1695 } 1696 1697 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1698 { 1699 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1700 } 1701 1702 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1703 { 1704 int fifo_bytes_used; 1705 1706 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1707 1708 if (fifo_bytes_used < 128) 1709 return 128 - fifo_bytes_used; 1710 else 1711 return 0; 1712 } 1713 1714 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1715 { 1716 while (snd_hdspm_midi_input_available (hdspm, id)) 1717 snd_hdspm_midi_read_byte (hdspm, id); 1718 } 1719 1720 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1721 { 1722 unsigned long flags; 1723 int n_pending; 1724 int to_write; 1725 int i; 1726 unsigned char buf[128]; 1727 1728 /* Output is not interrupt driven */ 1729 1730 spin_lock_irqsave (&hmidi->lock, flags); 1731 if (hmidi->output && 1732 !snd_rawmidi_transmit_empty (hmidi->output)) { 1733 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1734 hmidi->id); 1735 if (n_pending > 0) { 1736 if (n_pending > (int)sizeof (buf)) 1737 n_pending = sizeof (buf); 1738 1739 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1740 n_pending); 1741 if (to_write > 0) { 1742 for (i = 0; i < to_write; ++i) 1743 snd_hdspm_midi_write_byte (hmidi->hdspm, 1744 hmidi->id, 1745 buf[i]); 1746 } 1747 } 1748 } 1749 spin_unlock_irqrestore (&hmidi->lock, flags); 1750 return 0; 1751 } 1752 1753 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1754 { 1755 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1756 * input FIFO size 1757 */ 1758 unsigned long flags; 1759 int n_pending; 1760 int i; 1761 1762 spin_lock_irqsave (&hmidi->lock, flags); 1763 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1764 if (n_pending > 0) { 1765 if (hmidi->input) { 1766 if (n_pending > (int)sizeof (buf)) 1767 n_pending = sizeof (buf); 1768 for (i = 0; i < n_pending; ++i) 1769 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1770 hmidi->id); 1771 if (n_pending) 1772 snd_rawmidi_receive (hmidi->input, buf, 1773 n_pending); 1774 } else { 1775 /* flush the MIDI input FIFO */ 1776 while (n_pending--) 1777 snd_hdspm_midi_read_byte (hmidi->hdspm, 1778 hmidi->id); 1779 } 1780 } 1781 hmidi->pending = 0; 1782 spin_unlock_irqrestore(&hmidi->lock, flags); 1783 1784 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1785 hmidi->hdspm->control_register |= hmidi->ie; 1786 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1787 hmidi->hdspm->control_register); 1788 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1789 1790 return snd_hdspm_midi_output_write (hmidi); 1791 } 1792 1793 static void 1794 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1795 { 1796 struct hdspm *hdspm; 1797 struct hdspm_midi *hmidi; 1798 unsigned long flags; 1799 1800 hmidi = substream->rmidi->private_data; 1801 hdspm = hmidi->hdspm; 1802 1803 spin_lock_irqsave (&hdspm->lock, flags); 1804 if (up) { 1805 if (!(hdspm->control_register & hmidi->ie)) { 1806 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1807 hdspm->control_register |= hmidi->ie; 1808 } 1809 } else { 1810 hdspm->control_register &= ~hmidi->ie; 1811 } 1812 1813 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1814 spin_unlock_irqrestore (&hdspm->lock, flags); 1815 } 1816 1817 static void snd_hdspm_midi_output_timer(unsigned long data) 1818 { 1819 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1820 unsigned long flags; 1821 1822 snd_hdspm_midi_output_write(hmidi); 1823 spin_lock_irqsave (&hmidi->lock, flags); 1824 1825 /* this does not bump hmidi->istimer, because the 1826 kernel automatically removed the timer when it 1827 expired, and we are now adding it back, thus 1828 leaving istimer wherever it was set before. 1829 */ 1830 1831 if (hmidi->istimer) { 1832 hmidi->timer.expires = 1 + jiffies; 1833 add_timer(&hmidi->timer); 1834 } 1835 1836 spin_unlock_irqrestore (&hmidi->lock, flags); 1837 } 1838 1839 static void 1840 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1841 { 1842 struct hdspm_midi *hmidi; 1843 unsigned long flags; 1844 1845 hmidi = substream->rmidi->private_data; 1846 spin_lock_irqsave (&hmidi->lock, flags); 1847 if (up) { 1848 if (!hmidi->istimer) { 1849 init_timer(&hmidi->timer); 1850 hmidi->timer.function = snd_hdspm_midi_output_timer; 1851 hmidi->timer.data = (unsigned long) hmidi; 1852 hmidi->timer.expires = 1 + jiffies; 1853 add_timer(&hmidi->timer); 1854 hmidi->istimer++; 1855 } 1856 } else { 1857 if (hmidi->istimer && --hmidi->istimer <= 0) 1858 del_timer (&hmidi->timer); 1859 } 1860 spin_unlock_irqrestore (&hmidi->lock, flags); 1861 if (up) 1862 snd_hdspm_midi_output_write(hmidi); 1863 } 1864 1865 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1866 { 1867 struct hdspm_midi *hmidi; 1868 1869 hmidi = substream->rmidi->private_data; 1870 spin_lock_irq (&hmidi->lock); 1871 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1872 hmidi->input = substream; 1873 spin_unlock_irq (&hmidi->lock); 1874 1875 return 0; 1876 } 1877 1878 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1879 { 1880 struct hdspm_midi *hmidi; 1881 1882 hmidi = substream->rmidi->private_data; 1883 spin_lock_irq (&hmidi->lock); 1884 hmidi->output = substream; 1885 spin_unlock_irq (&hmidi->lock); 1886 1887 return 0; 1888 } 1889 1890 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1891 { 1892 struct hdspm_midi *hmidi; 1893 1894 snd_hdspm_midi_input_trigger (substream, 0); 1895 1896 hmidi = substream->rmidi->private_data; 1897 spin_lock_irq (&hmidi->lock); 1898 hmidi->input = NULL; 1899 spin_unlock_irq (&hmidi->lock); 1900 1901 return 0; 1902 } 1903 1904 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1905 { 1906 struct hdspm_midi *hmidi; 1907 1908 snd_hdspm_midi_output_trigger (substream, 0); 1909 1910 hmidi = substream->rmidi->private_data; 1911 spin_lock_irq (&hmidi->lock); 1912 hmidi->output = NULL; 1913 spin_unlock_irq (&hmidi->lock); 1914 1915 return 0; 1916 } 1917 1918 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1919 { 1920 .open = snd_hdspm_midi_output_open, 1921 .close = snd_hdspm_midi_output_close, 1922 .trigger = snd_hdspm_midi_output_trigger, 1923 }; 1924 1925 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1926 { 1927 .open = snd_hdspm_midi_input_open, 1928 .close = snd_hdspm_midi_input_close, 1929 .trigger = snd_hdspm_midi_input_trigger, 1930 }; 1931 1932 static int snd_hdspm_create_midi(struct snd_card *card, 1933 struct hdspm *hdspm, int id) 1934 { 1935 int err; 1936 char buf[32]; 1937 1938 hdspm->midi[id].id = id; 1939 hdspm->midi[id].hdspm = hdspm; 1940 spin_lock_init (&hdspm->midi[id].lock); 1941 1942 if (0 == id) { 1943 if (MADIface == hdspm->io_type) { 1944 /* MIDI-over-MADI on HDSPe MADIface */ 1945 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1946 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1947 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1948 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1949 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1950 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1951 } else { 1952 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1953 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1954 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1955 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1956 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1957 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1958 } 1959 } else if (1 == id) { 1960 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1961 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1962 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1963 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1964 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1965 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1966 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1967 /* MIDI-over-MADI on HDSPe MADI */ 1968 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1969 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1970 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1971 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1972 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1973 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1974 } else if (2 == id) { 1975 /* TCO MTC, read only */ 1976 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1977 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1978 hdspm->midi[2].dataOut = -1; 1979 hdspm->midi[2].statusOut = -1; 1980 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1981 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1982 } else if (3 == id) { 1983 /* TCO MTC on HDSPe MADI */ 1984 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1985 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1986 hdspm->midi[3].dataOut = -1; 1987 hdspm->midi[3].statusOut = -1; 1988 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1989 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1990 } 1991 1992 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1993 (MADIface == hdspm->io_type)))) { 1994 if ((id == 0) && (MADIface == hdspm->io_type)) { 1995 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1996 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1997 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1998 } else { 1999 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 2000 } 2001 err = snd_rawmidi_new(card, buf, id, 1, 1, 2002 &hdspm->midi[id].rmidi); 2003 if (err < 0) 2004 return err; 2005 2006 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 2007 card->id, id+1); 2008 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2009 2010 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2011 SNDRV_RAWMIDI_STREAM_OUTPUT, 2012 &snd_hdspm_midi_output); 2013 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2014 SNDRV_RAWMIDI_STREAM_INPUT, 2015 &snd_hdspm_midi_input); 2016 2017 hdspm->midi[id].rmidi->info_flags |= 2018 SNDRV_RAWMIDI_INFO_OUTPUT | 2019 SNDRV_RAWMIDI_INFO_INPUT | 2020 SNDRV_RAWMIDI_INFO_DUPLEX; 2021 } else { 2022 /* TCO MTC, read only */ 2023 sprintf(buf, "%s MTC %d", card->shortname, id+1); 2024 err = snd_rawmidi_new(card, buf, id, 1, 1, 2025 &hdspm->midi[id].rmidi); 2026 if (err < 0) 2027 return err; 2028 2029 sprintf(hdspm->midi[id].rmidi->name, 2030 "%s MTC %d", card->id, id+1); 2031 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2032 2033 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2034 SNDRV_RAWMIDI_STREAM_INPUT, 2035 &snd_hdspm_midi_input); 2036 2037 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2038 } 2039 2040 return 0; 2041 } 2042 2043 2044 static void hdspm_midi_tasklet(unsigned long arg) 2045 { 2046 struct hdspm *hdspm = (struct hdspm *)arg; 2047 int i = 0; 2048 2049 while (i < hdspm->midiPorts) { 2050 if (hdspm->midi[i].pending) 2051 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2052 2053 i++; 2054 } 2055 } 2056 2057 2058 /*----------------------------------------------------------------------------- 2059 Status Interface 2060 ----------------------------------------------------------------------------*/ 2061 2062 /* get the system sample rate which is set */ 2063 2064 2065 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2066 { 2067 unsigned int period, rate; 2068 2069 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2070 rate = hdspm_calc_dds_value(hdspm, period); 2071 2072 return rate; 2073 } 2074 2075 /** 2076 * Calculate the real sample rate from the 2077 * current DDS value. 2078 **/ 2079 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2080 { 2081 unsigned int rate; 2082 2083 rate = hdspm_get_pll_freq(hdspm); 2084 2085 if (rate > 207000) { 2086 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2087 if (0 == hdspm_system_clock_mode(hdspm)) { 2088 /* master mode, return internal sample rate */ 2089 rate = hdspm->system_sample_rate; 2090 } else { 2091 /* slave mode, return external sample rate */ 2092 rate = hdspm_external_sample_rate(hdspm); 2093 } 2094 } 2095 2096 return rate; 2097 } 2098 2099 2100 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2101 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2102 .name = xname, \ 2103 .index = xindex, \ 2104 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2105 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2106 .info = snd_hdspm_info_system_sample_rate, \ 2107 .put = snd_hdspm_put_system_sample_rate, \ 2108 .get = snd_hdspm_get_system_sample_rate \ 2109 } 2110 2111 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2112 struct snd_ctl_elem_info *uinfo) 2113 { 2114 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2115 uinfo->count = 1; 2116 uinfo->value.integer.min = 27000; 2117 uinfo->value.integer.max = 207000; 2118 uinfo->value.integer.step = 1; 2119 return 0; 2120 } 2121 2122 2123 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2124 struct snd_ctl_elem_value * 2125 ucontrol) 2126 { 2127 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2128 2129 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2130 return 0; 2131 } 2132 2133 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2134 struct snd_ctl_elem_value * 2135 ucontrol) 2136 { 2137 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2138 2139 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]); 2140 return 0; 2141 } 2142 2143 2144 /** 2145 * Returns the WordClock sample rate class for the given card. 2146 **/ 2147 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2148 { 2149 int status; 2150 2151 switch (hdspm->io_type) { 2152 case RayDAT: 2153 case AIO: 2154 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2155 return (status >> 16) & 0xF; 2156 break; 2157 default: 2158 break; 2159 } 2160 2161 2162 return 0; 2163 } 2164 2165 2166 /** 2167 * Returns the TCO sample rate class for the given card. 2168 **/ 2169 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2170 { 2171 int status; 2172 2173 if (hdspm->tco) { 2174 switch (hdspm->io_type) { 2175 case RayDAT: 2176 case AIO: 2177 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2178 return (status >> 20) & 0xF; 2179 break; 2180 default: 2181 break; 2182 } 2183 } 2184 2185 return 0; 2186 } 2187 2188 2189 /** 2190 * Returns the SYNC_IN sample rate class for the given card. 2191 **/ 2192 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2193 { 2194 int status; 2195 2196 if (hdspm->tco) { 2197 switch (hdspm->io_type) { 2198 case RayDAT: 2199 case AIO: 2200 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2201 return (status >> 12) & 0xF; 2202 break; 2203 default: 2204 break; 2205 } 2206 } 2207 2208 return 0; 2209 } 2210 2211 2212 /** 2213 * Returns the sample rate class for input source <idx> for 2214 * 'new style' cards like the AIO and RayDAT. 2215 **/ 2216 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2217 { 2218 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2219 2220 return (status >> (idx*4)) & 0xF; 2221 } 2222 2223 #define ENUMERATED_CTL_INFO(info, texts) \ 2224 { \ 2225 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \ 2226 uinfo->count = 1; \ 2227 uinfo->value.enumerated.items = ARRAY_SIZE(texts); \ 2228 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \ 2229 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; \ 2230 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \ 2231 } 2232 2233 2234 2235 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2236 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2237 .name = xname, \ 2238 .private_value = xindex, \ 2239 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2240 .info = snd_hdspm_info_autosync_sample_rate, \ 2241 .get = snd_hdspm_get_autosync_sample_rate \ 2242 } 2243 2244 2245 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2246 struct snd_ctl_elem_info *uinfo) 2247 { 2248 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2249 return 0; 2250 } 2251 2252 2253 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2254 struct snd_ctl_elem_value * 2255 ucontrol) 2256 { 2257 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2258 2259 switch (hdspm->io_type) { 2260 case RayDAT: 2261 switch (kcontrol->private_value) { 2262 case 0: 2263 ucontrol->value.enumerated.item[0] = 2264 hdspm_get_wc_sample_rate(hdspm); 2265 break; 2266 case 7: 2267 ucontrol->value.enumerated.item[0] = 2268 hdspm_get_tco_sample_rate(hdspm); 2269 break; 2270 case 8: 2271 ucontrol->value.enumerated.item[0] = 2272 hdspm_get_sync_in_sample_rate(hdspm); 2273 break; 2274 default: 2275 ucontrol->value.enumerated.item[0] = 2276 hdspm_get_s1_sample_rate(hdspm, 2277 kcontrol->private_value-1); 2278 } 2279 break; 2280 2281 case AIO: 2282 switch (kcontrol->private_value) { 2283 case 0: /* WC */ 2284 ucontrol->value.enumerated.item[0] = 2285 hdspm_get_wc_sample_rate(hdspm); 2286 break; 2287 case 4: /* TCO */ 2288 ucontrol->value.enumerated.item[0] = 2289 hdspm_get_tco_sample_rate(hdspm); 2290 break; 2291 case 5: /* SYNC_IN */ 2292 ucontrol->value.enumerated.item[0] = 2293 hdspm_get_sync_in_sample_rate(hdspm); 2294 break; 2295 default: 2296 ucontrol->value.enumerated.item[0] = 2297 hdspm_get_s1_sample_rate(hdspm, 2298 ucontrol->id.index-1); 2299 } 2300 break; 2301 2302 case AES32: 2303 2304 switch (kcontrol->private_value) { 2305 case 0: /* WC */ 2306 ucontrol->value.enumerated.item[0] = 2307 hdspm_get_wc_sample_rate(hdspm); 2308 break; 2309 case 9: /* TCO */ 2310 ucontrol->value.enumerated.item[0] = 2311 hdspm_get_tco_sample_rate(hdspm); 2312 break; 2313 case 10: /* SYNC_IN */ 2314 ucontrol->value.enumerated.item[0] = 2315 hdspm_get_sync_in_sample_rate(hdspm); 2316 break; 2317 default: /* AES1 to AES8 */ 2318 ucontrol->value.enumerated.item[0] = 2319 hdspm_get_s1_sample_rate(hdspm, 2320 kcontrol->private_value-1); 2321 break; 2322 } 2323 break; 2324 2325 case MADI: 2326 case MADIface: 2327 { 2328 int rate = hdspm_external_sample_rate(hdspm); 2329 int i, selected_rate = 0; 2330 for (i = 1; i < 10; i++) 2331 if (HDSPM_bit2freq(i) == rate) { 2332 selected_rate = i; 2333 break; 2334 } 2335 ucontrol->value.enumerated.item[0] = selected_rate; 2336 } 2337 break; 2338 2339 default: 2340 break; 2341 } 2342 2343 return 0; 2344 } 2345 2346 2347 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2348 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2349 .name = xname, \ 2350 .index = xindex, \ 2351 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2352 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2353 .info = snd_hdspm_info_system_clock_mode, \ 2354 .get = snd_hdspm_get_system_clock_mode, \ 2355 .put = snd_hdspm_put_system_clock_mode, \ 2356 } 2357 2358 2359 /** 2360 * Returns the system clock mode for the given card. 2361 * @returns 0 - master, 1 - slave 2362 **/ 2363 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2364 { 2365 switch (hdspm->io_type) { 2366 case AIO: 2367 case RayDAT: 2368 if (hdspm->settings_register & HDSPM_c0Master) 2369 return 0; 2370 break; 2371 2372 default: 2373 if (hdspm->control_register & HDSPM_ClockModeMaster) 2374 return 0; 2375 } 2376 2377 return 1; 2378 } 2379 2380 2381 /** 2382 * Sets the system clock mode. 2383 * @param mode 0 - master, 1 - slave 2384 **/ 2385 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2386 { 2387 switch (hdspm->io_type) { 2388 case AIO: 2389 case RayDAT: 2390 if (0 == mode) 2391 hdspm->settings_register |= HDSPM_c0Master; 2392 else 2393 hdspm->settings_register &= ~HDSPM_c0Master; 2394 2395 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2396 break; 2397 2398 default: 2399 if (0 == mode) 2400 hdspm->control_register |= HDSPM_ClockModeMaster; 2401 else 2402 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2403 2404 hdspm_write(hdspm, HDSPM_controlRegister, 2405 hdspm->control_register); 2406 } 2407 } 2408 2409 2410 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2411 struct snd_ctl_elem_info *uinfo) 2412 { 2413 static char *texts[] = { "Master", "AutoSync" }; 2414 ENUMERATED_CTL_INFO(uinfo, texts); 2415 return 0; 2416 } 2417 2418 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2419 struct snd_ctl_elem_value *ucontrol) 2420 { 2421 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2422 2423 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2424 return 0; 2425 } 2426 2427 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2428 struct snd_ctl_elem_value *ucontrol) 2429 { 2430 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2431 int val; 2432 2433 if (!snd_hdspm_use_is_exclusive(hdspm)) 2434 return -EBUSY; 2435 2436 val = ucontrol->value.enumerated.item[0]; 2437 if (val < 0) 2438 val = 0; 2439 else if (val > 1) 2440 val = 1; 2441 2442 hdspm_set_system_clock_mode(hdspm, val); 2443 2444 return 0; 2445 } 2446 2447 2448 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2449 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2450 .name = xname, \ 2451 .index = xindex, \ 2452 .info = snd_hdspm_info_clock_source, \ 2453 .get = snd_hdspm_get_clock_source, \ 2454 .put = snd_hdspm_put_clock_source \ 2455 } 2456 2457 2458 static int hdspm_clock_source(struct hdspm * hdspm) 2459 { 2460 switch (hdspm->system_sample_rate) { 2461 case 32000: return 0; 2462 case 44100: return 1; 2463 case 48000: return 2; 2464 case 64000: return 3; 2465 case 88200: return 4; 2466 case 96000: return 5; 2467 case 128000: return 6; 2468 case 176400: return 7; 2469 case 192000: return 8; 2470 } 2471 2472 return -1; 2473 } 2474 2475 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2476 { 2477 int rate; 2478 switch (mode) { 2479 case 0: 2480 rate = 32000; break; 2481 case 1: 2482 rate = 44100; break; 2483 case 2: 2484 rate = 48000; break; 2485 case 3: 2486 rate = 64000; break; 2487 case 4: 2488 rate = 88200; break; 2489 case 5: 2490 rate = 96000; break; 2491 case 6: 2492 rate = 128000; break; 2493 case 7: 2494 rate = 176400; break; 2495 case 8: 2496 rate = 192000; break; 2497 default: 2498 rate = 48000; 2499 } 2500 hdspm_set_rate(hdspm, rate, 1); 2501 return 0; 2502 } 2503 2504 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2505 struct snd_ctl_elem_info *uinfo) 2506 { 2507 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2508 uinfo->count = 1; 2509 uinfo->value.enumerated.items = 9; 2510 2511 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2512 uinfo->value.enumerated.item = 2513 uinfo->value.enumerated.items - 1; 2514 2515 strcpy(uinfo->value.enumerated.name, 2516 texts_freq[uinfo->value.enumerated.item+1]); 2517 2518 return 0; 2519 } 2520 2521 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2522 struct snd_ctl_elem_value *ucontrol) 2523 { 2524 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2525 2526 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2527 return 0; 2528 } 2529 2530 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2531 struct snd_ctl_elem_value *ucontrol) 2532 { 2533 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2534 int change; 2535 int val; 2536 2537 if (!snd_hdspm_use_is_exclusive(hdspm)) 2538 return -EBUSY; 2539 val = ucontrol->value.enumerated.item[0]; 2540 if (val < 0) 2541 val = 0; 2542 if (val > 9) 2543 val = 9; 2544 spin_lock_irq(&hdspm->lock); 2545 if (val != hdspm_clock_source(hdspm)) 2546 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2547 else 2548 change = 0; 2549 spin_unlock_irq(&hdspm->lock); 2550 return change; 2551 } 2552 2553 2554 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2555 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2556 .name = xname, \ 2557 .index = xindex, \ 2558 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2559 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2560 .info = snd_hdspm_info_pref_sync_ref, \ 2561 .get = snd_hdspm_get_pref_sync_ref, \ 2562 .put = snd_hdspm_put_pref_sync_ref \ 2563 } 2564 2565 2566 /** 2567 * Returns the current preferred sync reference setting. 2568 * The semantics of the return value are depending on the 2569 * card, please see the comments for clarification. 2570 **/ 2571 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2572 { 2573 switch (hdspm->io_type) { 2574 case AES32: 2575 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2576 case 0: return 0; /* WC */ 2577 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2578 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2579 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2580 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2581 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2582 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2583 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2584 return 7; /* AES 7 */ 2585 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2586 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2587 } 2588 break; 2589 2590 case MADI: 2591 case MADIface: 2592 if (hdspm->tco) { 2593 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2594 case 0: return 0; /* WC */ 2595 case HDSPM_SyncRef0: return 1; /* MADI */ 2596 case HDSPM_SyncRef1: return 2; /* TCO */ 2597 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2598 return 3; /* SYNC_IN */ 2599 } 2600 } else { 2601 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2602 case 0: return 0; /* WC */ 2603 case HDSPM_SyncRef0: return 1; /* MADI */ 2604 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2605 return 2; /* SYNC_IN */ 2606 } 2607 } 2608 break; 2609 2610 case RayDAT: 2611 if (hdspm->tco) { 2612 switch ((hdspm->settings_register & 2613 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2614 case 0: return 0; /* WC */ 2615 case 3: return 1; /* ADAT 1 */ 2616 case 4: return 2; /* ADAT 2 */ 2617 case 5: return 3; /* ADAT 3 */ 2618 case 6: return 4; /* ADAT 4 */ 2619 case 1: return 5; /* AES */ 2620 case 2: return 6; /* SPDIF */ 2621 case 9: return 7; /* TCO */ 2622 case 10: return 8; /* SYNC_IN */ 2623 } 2624 } else { 2625 switch ((hdspm->settings_register & 2626 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2627 case 0: return 0; /* WC */ 2628 case 3: return 1; /* ADAT 1 */ 2629 case 4: return 2; /* ADAT 2 */ 2630 case 5: return 3; /* ADAT 3 */ 2631 case 6: return 4; /* ADAT 4 */ 2632 case 1: return 5; /* AES */ 2633 case 2: return 6; /* SPDIF */ 2634 case 10: return 7; /* SYNC_IN */ 2635 } 2636 } 2637 2638 break; 2639 2640 case AIO: 2641 if (hdspm->tco) { 2642 switch ((hdspm->settings_register & 2643 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2644 case 0: return 0; /* WC */ 2645 case 3: return 1; /* ADAT */ 2646 case 1: return 2; /* AES */ 2647 case 2: return 3; /* SPDIF */ 2648 case 9: return 4; /* TCO */ 2649 case 10: return 5; /* SYNC_IN */ 2650 } 2651 } else { 2652 switch ((hdspm->settings_register & 2653 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2654 case 0: return 0; /* WC */ 2655 case 3: return 1; /* ADAT */ 2656 case 1: return 2; /* AES */ 2657 case 2: return 3; /* SPDIF */ 2658 case 10: return 4; /* SYNC_IN */ 2659 } 2660 } 2661 2662 break; 2663 } 2664 2665 return -1; 2666 } 2667 2668 2669 /** 2670 * Set the preferred sync reference to <pref>. The semantics 2671 * of <pref> are depending on the card type, see the comments 2672 * for clarification. 2673 **/ 2674 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2675 { 2676 int p = 0; 2677 2678 switch (hdspm->io_type) { 2679 case AES32: 2680 hdspm->control_register &= ~HDSPM_SyncRefMask; 2681 switch (pref) { 2682 case 0: /* WC */ 2683 break; 2684 case 1: /* AES 1 */ 2685 hdspm->control_register |= HDSPM_SyncRef0; 2686 break; 2687 case 2: /* AES 2 */ 2688 hdspm->control_register |= HDSPM_SyncRef1; 2689 break; 2690 case 3: /* AES 3 */ 2691 hdspm->control_register |= 2692 HDSPM_SyncRef1+HDSPM_SyncRef0; 2693 break; 2694 case 4: /* AES 4 */ 2695 hdspm->control_register |= HDSPM_SyncRef2; 2696 break; 2697 case 5: /* AES 5 */ 2698 hdspm->control_register |= 2699 HDSPM_SyncRef2+HDSPM_SyncRef0; 2700 break; 2701 case 6: /* AES 6 */ 2702 hdspm->control_register |= 2703 HDSPM_SyncRef2+HDSPM_SyncRef1; 2704 break; 2705 case 7: /* AES 7 */ 2706 hdspm->control_register |= 2707 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2708 break; 2709 case 8: /* AES 8 */ 2710 hdspm->control_register |= HDSPM_SyncRef3; 2711 break; 2712 case 9: /* TCO */ 2713 hdspm->control_register |= 2714 HDSPM_SyncRef3+HDSPM_SyncRef0; 2715 break; 2716 default: 2717 return -1; 2718 } 2719 2720 break; 2721 2722 case MADI: 2723 case MADIface: 2724 hdspm->control_register &= ~HDSPM_SyncRefMask; 2725 if (hdspm->tco) { 2726 switch (pref) { 2727 case 0: /* WC */ 2728 break; 2729 case 1: /* MADI */ 2730 hdspm->control_register |= HDSPM_SyncRef0; 2731 break; 2732 case 2: /* TCO */ 2733 hdspm->control_register |= HDSPM_SyncRef1; 2734 break; 2735 case 3: /* SYNC_IN */ 2736 hdspm->control_register |= 2737 HDSPM_SyncRef0+HDSPM_SyncRef1; 2738 break; 2739 default: 2740 return -1; 2741 } 2742 } else { 2743 switch (pref) { 2744 case 0: /* WC */ 2745 break; 2746 case 1: /* MADI */ 2747 hdspm->control_register |= HDSPM_SyncRef0; 2748 break; 2749 case 2: /* SYNC_IN */ 2750 hdspm->control_register |= 2751 HDSPM_SyncRef0+HDSPM_SyncRef1; 2752 break; 2753 default: 2754 return -1; 2755 } 2756 } 2757 2758 break; 2759 2760 case RayDAT: 2761 if (hdspm->tco) { 2762 switch (pref) { 2763 case 0: p = 0; break; /* WC */ 2764 case 1: p = 3; break; /* ADAT 1 */ 2765 case 2: p = 4; break; /* ADAT 2 */ 2766 case 3: p = 5; break; /* ADAT 3 */ 2767 case 4: p = 6; break; /* ADAT 4 */ 2768 case 5: p = 1; break; /* AES */ 2769 case 6: p = 2; break; /* SPDIF */ 2770 case 7: p = 9; break; /* TCO */ 2771 case 8: p = 10; break; /* SYNC_IN */ 2772 default: return -1; 2773 } 2774 } else { 2775 switch (pref) { 2776 case 0: p = 0; break; /* WC */ 2777 case 1: p = 3; break; /* ADAT 1 */ 2778 case 2: p = 4; break; /* ADAT 2 */ 2779 case 3: p = 5; break; /* ADAT 3 */ 2780 case 4: p = 6; break; /* ADAT 4 */ 2781 case 5: p = 1; break; /* AES */ 2782 case 6: p = 2; break; /* SPDIF */ 2783 case 7: p = 10; break; /* SYNC_IN */ 2784 default: return -1; 2785 } 2786 } 2787 break; 2788 2789 case AIO: 2790 if (hdspm->tco) { 2791 switch (pref) { 2792 case 0: p = 0; break; /* WC */ 2793 case 1: p = 3; break; /* ADAT */ 2794 case 2: p = 1; break; /* AES */ 2795 case 3: p = 2; break; /* SPDIF */ 2796 case 4: p = 9; break; /* TCO */ 2797 case 5: p = 10; break; /* SYNC_IN */ 2798 default: return -1; 2799 } 2800 } else { 2801 switch (pref) { 2802 case 0: p = 0; break; /* WC */ 2803 case 1: p = 3; break; /* ADAT */ 2804 case 2: p = 1; break; /* AES */ 2805 case 3: p = 2; break; /* SPDIF */ 2806 case 4: p = 10; break; /* SYNC_IN */ 2807 default: return -1; 2808 } 2809 } 2810 break; 2811 } 2812 2813 switch (hdspm->io_type) { 2814 case RayDAT: 2815 case AIO: 2816 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2817 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2818 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2819 break; 2820 2821 case MADI: 2822 case MADIface: 2823 case AES32: 2824 hdspm_write(hdspm, HDSPM_controlRegister, 2825 hdspm->control_register); 2826 } 2827 2828 return 0; 2829 } 2830 2831 2832 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2833 struct snd_ctl_elem_info *uinfo) 2834 { 2835 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2836 2837 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2838 uinfo->count = 1; 2839 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2840 2841 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2842 uinfo->value.enumerated.item = 2843 uinfo->value.enumerated.items - 1; 2844 2845 strcpy(uinfo->value.enumerated.name, 2846 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2847 2848 return 0; 2849 } 2850 2851 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2852 struct snd_ctl_elem_value *ucontrol) 2853 { 2854 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2855 int psf = hdspm_pref_sync_ref(hdspm); 2856 2857 if (psf >= 0) { 2858 ucontrol->value.enumerated.item[0] = psf; 2859 return 0; 2860 } 2861 2862 return -1; 2863 } 2864 2865 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2866 struct snd_ctl_elem_value *ucontrol) 2867 { 2868 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2869 int val, change = 0; 2870 2871 if (!snd_hdspm_use_is_exclusive(hdspm)) 2872 return -EBUSY; 2873 2874 val = ucontrol->value.enumerated.item[0]; 2875 2876 if (val < 0) 2877 val = 0; 2878 else if (val >= hdspm->texts_autosync_items) 2879 val = hdspm->texts_autosync_items-1; 2880 2881 spin_lock_irq(&hdspm->lock); 2882 if (val != hdspm_pref_sync_ref(hdspm)) 2883 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2884 2885 spin_unlock_irq(&hdspm->lock); 2886 return change; 2887 } 2888 2889 2890 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2891 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2892 .name = xname, \ 2893 .index = xindex, \ 2894 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2895 .info = snd_hdspm_info_autosync_ref, \ 2896 .get = snd_hdspm_get_autosync_ref, \ 2897 } 2898 2899 static int hdspm_autosync_ref(struct hdspm *hdspm) 2900 { 2901 if (AES32 == hdspm->io_type) { 2902 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2903 unsigned int syncref = 2904 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2905 if (syncref == 0) 2906 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2907 if (syncref <= 8) 2908 return syncref; 2909 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2910 } else if (MADI == hdspm->io_type) { 2911 /* This looks at the autosync selected sync reference */ 2912 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2913 2914 switch (status2 & HDSPM_SelSyncRefMask) { 2915 case HDSPM_SelSyncRef_WORD: 2916 return HDSPM_AUTOSYNC_FROM_WORD; 2917 case HDSPM_SelSyncRef_MADI: 2918 return HDSPM_AUTOSYNC_FROM_MADI; 2919 case HDSPM_SelSyncRef_TCO: 2920 return HDSPM_AUTOSYNC_FROM_TCO; 2921 case HDSPM_SelSyncRef_SyncIn: 2922 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2923 case HDSPM_SelSyncRef_NVALID: 2924 return HDSPM_AUTOSYNC_FROM_NONE; 2925 default: 2926 return 0; 2927 } 2928 2929 } 2930 return 0; 2931 } 2932 2933 2934 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2935 struct snd_ctl_elem_info *uinfo) 2936 { 2937 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2938 2939 if (AES32 == hdspm->io_type) { 2940 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2941 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2942 2943 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2944 uinfo->count = 1; 2945 uinfo->value.enumerated.items = 10; 2946 if (uinfo->value.enumerated.item >= 2947 uinfo->value.enumerated.items) 2948 uinfo->value.enumerated.item = 2949 uinfo->value.enumerated.items - 1; 2950 strcpy(uinfo->value.enumerated.name, 2951 texts[uinfo->value.enumerated.item]); 2952 } else if (MADI == hdspm->io_type) { 2953 static char *texts[] = {"Word Clock", "MADI", "TCO", 2954 "Sync In", "None" }; 2955 2956 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2957 uinfo->count = 1; 2958 uinfo->value.enumerated.items = 5; 2959 if (uinfo->value.enumerated.item >= 2960 uinfo->value.enumerated.items) 2961 uinfo->value.enumerated.item = 2962 uinfo->value.enumerated.items - 1; 2963 strcpy(uinfo->value.enumerated.name, 2964 texts[uinfo->value.enumerated.item]); 2965 } 2966 return 0; 2967 } 2968 2969 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2970 struct snd_ctl_elem_value *ucontrol) 2971 { 2972 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2973 2974 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2975 return 0; 2976 } 2977 2978 2979 2980 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \ 2981 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2982 .name = xname, \ 2983 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 2984 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2985 .info = snd_hdspm_info_tco_video_input_format, \ 2986 .get = snd_hdspm_get_tco_video_input_format, \ 2987 } 2988 2989 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 2990 struct snd_ctl_elem_info *uinfo) 2991 { 2992 static char *texts[] = {"No video", "NTSC", "PAL"}; 2993 ENUMERATED_CTL_INFO(uinfo, texts); 2994 return 0; 2995 } 2996 2997 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 2998 struct snd_ctl_elem_value *ucontrol) 2999 { 3000 u32 status; 3001 int ret = 0; 3002 3003 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3004 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3005 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3006 HDSPM_TCO1_Video_Input_Format_PAL)) { 3007 case HDSPM_TCO1_Video_Input_Format_NTSC: 3008 /* ntsc */ 3009 ret = 1; 3010 break; 3011 case HDSPM_TCO1_Video_Input_Format_PAL: 3012 /* pal */ 3013 ret = 2; 3014 break; 3015 default: 3016 /* no video */ 3017 ret = 0; 3018 break; 3019 } 3020 ucontrol->value.enumerated.item[0] = ret; 3021 return 0; 3022 } 3023 3024 3025 3026 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \ 3027 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3028 .name = xname, \ 3029 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3030 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3031 .info = snd_hdspm_info_tco_ltc_frames, \ 3032 .get = snd_hdspm_get_tco_ltc_frames, \ 3033 } 3034 3035 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3036 struct snd_ctl_elem_info *uinfo) 3037 { 3038 static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3039 "30 fps"}; 3040 ENUMERATED_CTL_INFO(uinfo, texts); 3041 return 0; 3042 } 3043 3044 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3045 { 3046 u32 status; 3047 int ret = 0; 3048 3049 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3050 if (status & HDSPM_TCO1_LTC_Input_valid) { 3051 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3052 HDSPM_TCO1_LTC_Format_MSB)) { 3053 case 0: 3054 /* 24 fps */ 3055 ret = 1; 3056 break; 3057 case HDSPM_TCO1_LTC_Format_LSB: 3058 /* 25 fps */ 3059 ret = 2; 3060 break; 3061 case HDSPM_TCO1_LTC_Format_MSB: 3062 /* 25 fps */ 3063 ret = 3; 3064 break; 3065 default: 3066 /* 30 fps */ 3067 ret = 4; 3068 break; 3069 } 3070 } 3071 3072 return ret; 3073 } 3074 3075 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3076 struct snd_ctl_elem_value *ucontrol) 3077 { 3078 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3079 3080 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3081 return 0; 3082 } 3083 3084 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3085 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3086 .name = xname, \ 3087 .private_value = xindex, \ 3088 .info = snd_hdspm_info_toggle_setting, \ 3089 .get = snd_hdspm_get_toggle_setting, \ 3090 .put = snd_hdspm_put_toggle_setting \ 3091 } 3092 3093 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3094 { 3095 u32 reg; 3096 3097 if (hdspm_is_raydat_or_aio(hdspm)) 3098 reg = hdspm->settings_register; 3099 else 3100 reg = hdspm->control_register; 3101 3102 return (reg & regmask) ? 1 : 0; 3103 } 3104 3105 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3106 { 3107 u32 *reg; 3108 u32 target_reg; 3109 3110 if (hdspm_is_raydat_or_aio(hdspm)) { 3111 reg = &(hdspm->settings_register); 3112 target_reg = HDSPM_WR_SETTINGS; 3113 } else { 3114 reg = &(hdspm->control_register); 3115 target_reg = HDSPM_controlRegister; 3116 } 3117 3118 if (out) 3119 *reg |= regmask; 3120 else 3121 *reg &= ~regmask; 3122 3123 hdspm_write(hdspm, target_reg, *reg); 3124 3125 return 0; 3126 } 3127 3128 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3129 3130 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3131 struct snd_ctl_elem_value *ucontrol) 3132 { 3133 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3134 u32 regmask = kcontrol->private_value; 3135 3136 spin_lock_irq(&hdspm->lock); 3137 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3138 spin_unlock_irq(&hdspm->lock); 3139 return 0; 3140 } 3141 3142 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3143 struct snd_ctl_elem_value *ucontrol) 3144 { 3145 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3146 u32 regmask = kcontrol->private_value; 3147 int change; 3148 unsigned int val; 3149 3150 if (!snd_hdspm_use_is_exclusive(hdspm)) 3151 return -EBUSY; 3152 val = ucontrol->value.integer.value[0] & 1; 3153 spin_lock_irq(&hdspm->lock); 3154 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3155 hdspm_set_toggle_setting(hdspm, regmask, val); 3156 spin_unlock_irq(&hdspm->lock); 3157 return change; 3158 } 3159 3160 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3161 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3162 .name = xname, \ 3163 .index = xindex, \ 3164 .info = snd_hdspm_info_input_select, \ 3165 .get = snd_hdspm_get_input_select, \ 3166 .put = snd_hdspm_put_input_select \ 3167 } 3168 3169 static int hdspm_input_select(struct hdspm * hdspm) 3170 { 3171 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3172 } 3173 3174 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3175 { 3176 if (out) 3177 hdspm->control_register |= HDSPM_InputSelect0; 3178 else 3179 hdspm->control_register &= ~HDSPM_InputSelect0; 3180 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3181 3182 return 0; 3183 } 3184 3185 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3186 struct snd_ctl_elem_info *uinfo) 3187 { 3188 static char *texts[] = { "optical", "coaxial" }; 3189 ENUMERATED_CTL_INFO(uinfo, texts); 3190 return 0; 3191 } 3192 3193 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3194 struct snd_ctl_elem_value *ucontrol) 3195 { 3196 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3197 3198 spin_lock_irq(&hdspm->lock); 3199 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3200 spin_unlock_irq(&hdspm->lock); 3201 return 0; 3202 } 3203 3204 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3205 struct snd_ctl_elem_value *ucontrol) 3206 { 3207 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3208 int change; 3209 unsigned int val; 3210 3211 if (!snd_hdspm_use_is_exclusive(hdspm)) 3212 return -EBUSY; 3213 val = ucontrol->value.integer.value[0] & 1; 3214 spin_lock_irq(&hdspm->lock); 3215 change = (int) val != hdspm_input_select(hdspm); 3216 hdspm_set_input_select(hdspm, val); 3217 spin_unlock_irq(&hdspm->lock); 3218 return change; 3219 } 3220 3221 3222 #define HDSPM_DS_WIRE(xname, xindex) \ 3223 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3224 .name = xname, \ 3225 .index = xindex, \ 3226 .info = snd_hdspm_info_ds_wire, \ 3227 .get = snd_hdspm_get_ds_wire, \ 3228 .put = snd_hdspm_put_ds_wire \ 3229 } 3230 3231 static int hdspm_ds_wire(struct hdspm * hdspm) 3232 { 3233 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3234 } 3235 3236 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3237 { 3238 if (ds) 3239 hdspm->control_register |= HDSPM_DS_DoubleWire; 3240 else 3241 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3242 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3243 3244 return 0; 3245 } 3246 3247 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3248 struct snd_ctl_elem_info *uinfo) 3249 { 3250 static char *texts[] = { "Single", "Double" }; 3251 ENUMERATED_CTL_INFO(uinfo, texts); 3252 return 0; 3253 } 3254 3255 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3256 struct snd_ctl_elem_value *ucontrol) 3257 { 3258 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3259 3260 spin_lock_irq(&hdspm->lock); 3261 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3262 spin_unlock_irq(&hdspm->lock); 3263 return 0; 3264 } 3265 3266 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3267 struct snd_ctl_elem_value *ucontrol) 3268 { 3269 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3270 int change; 3271 unsigned int val; 3272 3273 if (!snd_hdspm_use_is_exclusive(hdspm)) 3274 return -EBUSY; 3275 val = ucontrol->value.integer.value[0] & 1; 3276 spin_lock_irq(&hdspm->lock); 3277 change = (int) val != hdspm_ds_wire(hdspm); 3278 hdspm_set_ds_wire(hdspm, val); 3279 spin_unlock_irq(&hdspm->lock); 3280 return change; 3281 } 3282 3283 3284 #define HDSPM_QS_WIRE(xname, xindex) \ 3285 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3286 .name = xname, \ 3287 .index = xindex, \ 3288 .info = snd_hdspm_info_qs_wire, \ 3289 .get = snd_hdspm_get_qs_wire, \ 3290 .put = snd_hdspm_put_qs_wire \ 3291 } 3292 3293 static int hdspm_qs_wire(struct hdspm * hdspm) 3294 { 3295 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3296 return 1; 3297 if (hdspm->control_register & HDSPM_QS_QuadWire) 3298 return 2; 3299 return 0; 3300 } 3301 3302 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3303 { 3304 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3305 switch (mode) { 3306 case 0: 3307 break; 3308 case 1: 3309 hdspm->control_register |= HDSPM_QS_DoubleWire; 3310 break; 3311 case 2: 3312 hdspm->control_register |= HDSPM_QS_QuadWire; 3313 break; 3314 } 3315 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3316 3317 return 0; 3318 } 3319 3320 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3321 struct snd_ctl_elem_info *uinfo) 3322 { 3323 static char *texts[] = { "Single", "Double", "Quad" }; 3324 ENUMERATED_CTL_INFO(uinfo, texts); 3325 return 0; 3326 } 3327 3328 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3329 struct snd_ctl_elem_value *ucontrol) 3330 { 3331 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3332 3333 spin_lock_irq(&hdspm->lock); 3334 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3335 spin_unlock_irq(&hdspm->lock); 3336 return 0; 3337 } 3338 3339 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3340 struct snd_ctl_elem_value *ucontrol) 3341 { 3342 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3343 int change; 3344 int val; 3345 3346 if (!snd_hdspm_use_is_exclusive(hdspm)) 3347 return -EBUSY; 3348 val = ucontrol->value.integer.value[0]; 3349 if (val < 0) 3350 val = 0; 3351 if (val > 2) 3352 val = 2; 3353 spin_lock_irq(&hdspm->lock); 3354 change = val != hdspm_qs_wire(hdspm); 3355 hdspm_set_qs_wire(hdspm, val); 3356 spin_unlock_irq(&hdspm->lock); 3357 return change; 3358 } 3359 3360 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3361 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3362 .name = xname, \ 3363 .index = xindex, \ 3364 .info = snd_hdspm_info_madi_speedmode, \ 3365 .get = snd_hdspm_get_madi_speedmode, \ 3366 .put = snd_hdspm_put_madi_speedmode \ 3367 } 3368 3369 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3370 { 3371 if (hdspm->control_register & HDSPM_QuadSpeed) 3372 return 2; 3373 if (hdspm->control_register & HDSPM_DoubleSpeed) 3374 return 1; 3375 return 0; 3376 } 3377 3378 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3379 { 3380 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3381 switch (mode) { 3382 case 0: 3383 break; 3384 case 1: 3385 hdspm->control_register |= HDSPM_DoubleSpeed; 3386 break; 3387 case 2: 3388 hdspm->control_register |= HDSPM_QuadSpeed; 3389 break; 3390 } 3391 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3392 3393 return 0; 3394 } 3395 3396 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3397 struct snd_ctl_elem_info *uinfo) 3398 { 3399 static char *texts[] = { "Single", "Double", "Quad" }; 3400 ENUMERATED_CTL_INFO(uinfo, texts); 3401 return 0; 3402 } 3403 3404 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3405 struct snd_ctl_elem_value *ucontrol) 3406 { 3407 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3408 3409 spin_lock_irq(&hdspm->lock); 3410 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3411 spin_unlock_irq(&hdspm->lock); 3412 return 0; 3413 } 3414 3415 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3416 struct snd_ctl_elem_value *ucontrol) 3417 { 3418 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3419 int change; 3420 int val; 3421 3422 if (!snd_hdspm_use_is_exclusive(hdspm)) 3423 return -EBUSY; 3424 val = ucontrol->value.integer.value[0]; 3425 if (val < 0) 3426 val = 0; 3427 if (val > 2) 3428 val = 2; 3429 spin_lock_irq(&hdspm->lock); 3430 change = val != hdspm_madi_speedmode(hdspm); 3431 hdspm_set_madi_speedmode(hdspm, val); 3432 spin_unlock_irq(&hdspm->lock); 3433 return change; 3434 } 3435 3436 #define HDSPM_MIXER(xname, xindex) \ 3437 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3438 .name = xname, \ 3439 .index = xindex, \ 3440 .device = 0, \ 3441 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3442 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3443 .info = snd_hdspm_info_mixer, \ 3444 .get = snd_hdspm_get_mixer, \ 3445 .put = snd_hdspm_put_mixer \ 3446 } 3447 3448 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3449 struct snd_ctl_elem_info *uinfo) 3450 { 3451 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3452 uinfo->count = 3; 3453 uinfo->value.integer.min = 0; 3454 uinfo->value.integer.max = 65535; 3455 uinfo->value.integer.step = 1; 3456 return 0; 3457 } 3458 3459 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3460 struct snd_ctl_elem_value *ucontrol) 3461 { 3462 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3463 int source; 3464 int destination; 3465 3466 source = ucontrol->value.integer.value[0]; 3467 if (source < 0) 3468 source = 0; 3469 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3470 source = 2 * HDSPM_MAX_CHANNELS - 1; 3471 3472 destination = ucontrol->value.integer.value[1]; 3473 if (destination < 0) 3474 destination = 0; 3475 else if (destination >= HDSPM_MAX_CHANNELS) 3476 destination = HDSPM_MAX_CHANNELS - 1; 3477 3478 spin_lock_irq(&hdspm->lock); 3479 if (source >= HDSPM_MAX_CHANNELS) 3480 ucontrol->value.integer.value[2] = 3481 hdspm_read_pb_gain(hdspm, destination, 3482 source - HDSPM_MAX_CHANNELS); 3483 else 3484 ucontrol->value.integer.value[2] = 3485 hdspm_read_in_gain(hdspm, destination, source); 3486 3487 spin_unlock_irq(&hdspm->lock); 3488 3489 return 0; 3490 } 3491 3492 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3493 struct snd_ctl_elem_value *ucontrol) 3494 { 3495 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3496 int change; 3497 int source; 3498 int destination; 3499 int gain; 3500 3501 if (!snd_hdspm_use_is_exclusive(hdspm)) 3502 return -EBUSY; 3503 3504 source = ucontrol->value.integer.value[0]; 3505 destination = ucontrol->value.integer.value[1]; 3506 3507 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3508 return -1; 3509 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3510 return -1; 3511 3512 gain = ucontrol->value.integer.value[2]; 3513 3514 spin_lock_irq(&hdspm->lock); 3515 3516 if (source >= HDSPM_MAX_CHANNELS) 3517 change = gain != hdspm_read_pb_gain(hdspm, destination, 3518 source - 3519 HDSPM_MAX_CHANNELS); 3520 else 3521 change = gain != hdspm_read_in_gain(hdspm, destination, 3522 source); 3523 3524 if (change) { 3525 if (source >= HDSPM_MAX_CHANNELS) 3526 hdspm_write_pb_gain(hdspm, destination, 3527 source - HDSPM_MAX_CHANNELS, 3528 gain); 3529 else 3530 hdspm_write_in_gain(hdspm, destination, source, 3531 gain); 3532 } 3533 spin_unlock_irq(&hdspm->lock); 3534 3535 return change; 3536 } 3537 3538 /* The simple mixer control(s) provide gain control for the 3539 basic 1:1 mappings of playback streams to output 3540 streams. 3541 */ 3542 3543 #define HDSPM_PLAYBACK_MIXER \ 3544 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3545 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3546 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3547 .info = snd_hdspm_info_playback_mixer, \ 3548 .get = snd_hdspm_get_playback_mixer, \ 3549 .put = snd_hdspm_put_playback_mixer \ 3550 } 3551 3552 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3553 struct snd_ctl_elem_info *uinfo) 3554 { 3555 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3556 uinfo->count = 1; 3557 uinfo->value.integer.min = 0; 3558 uinfo->value.integer.max = 64; 3559 uinfo->value.integer.step = 1; 3560 return 0; 3561 } 3562 3563 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3564 struct snd_ctl_elem_value *ucontrol) 3565 { 3566 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3567 int channel; 3568 3569 channel = ucontrol->id.index - 1; 3570 3571 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3572 return -EINVAL; 3573 3574 spin_lock_irq(&hdspm->lock); 3575 ucontrol->value.integer.value[0] = 3576 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3577 spin_unlock_irq(&hdspm->lock); 3578 3579 return 0; 3580 } 3581 3582 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3583 struct snd_ctl_elem_value *ucontrol) 3584 { 3585 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3586 int change; 3587 int channel; 3588 int gain; 3589 3590 if (!snd_hdspm_use_is_exclusive(hdspm)) 3591 return -EBUSY; 3592 3593 channel = ucontrol->id.index - 1; 3594 3595 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3596 return -EINVAL; 3597 3598 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3599 3600 spin_lock_irq(&hdspm->lock); 3601 change = 3602 gain != hdspm_read_pb_gain(hdspm, channel, 3603 channel); 3604 if (change) 3605 hdspm_write_pb_gain(hdspm, channel, channel, 3606 gain); 3607 spin_unlock_irq(&hdspm->lock); 3608 return change; 3609 } 3610 3611 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3612 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3613 .name = xname, \ 3614 .private_value = xindex, \ 3615 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3616 .info = snd_hdspm_info_sync_check, \ 3617 .get = snd_hdspm_get_sync_check \ 3618 } 3619 3620 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3621 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3622 .name = xname, \ 3623 .private_value = xindex, \ 3624 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3625 .info = snd_hdspm_tco_info_lock_check, \ 3626 .get = snd_hdspm_get_sync_check \ 3627 } 3628 3629 3630 3631 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3632 struct snd_ctl_elem_info *uinfo) 3633 { 3634 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3635 ENUMERATED_CTL_INFO(uinfo, texts); 3636 return 0; 3637 } 3638 3639 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3640 struct snd_ctl_elem_info *uinfo) 3641 { 3642 static char *texts[] = { "No Lock", "Lock" }; 3643 ENUMERATED_CTL_INFO(uinfo, texts); 3644 return 0; 3645 } 3646 3647 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3648 { 3649 int status, status2; 3650 3651 switch (hdspm->io_type) { 3652 case AES32: 3653 status = hdspm_read(hdspm, HDSPM_statusRegister); 3654 if (status & HDSPM_AES32_wcLock) { 3655 if (status & HDSPM_AES32_wcSync) 3656 return 2; 3657 else 3658 return 1; 3659 } 3660 return 0; 3661 break; 3662 3663 case MADI: 3664 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3665 if (status2 & HDSPM_wcLock) { 3666 if (status2 & HDSPM_wcSync) 3667 return 2; 3668 else 3669 return 1; 3670 } 3671 return 0; 3672 break; 3673 3674 case RayDAT: 3675 case AIO: 3676 status = hdspm_read(hdspm, HDSPM_statusRegister); 3677 3678 if (status & 0x2000000) 3679 return 2; 3680 else if (status & 0x1000000) 3681 return 1; 3682 return 0; 3683 3684 break; 3685 3686 case MADIface: 3687 break; 3688 } 3689 3690 3691 return 3; 3692 } 3693 3694 3695 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3696 { 3697 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3698 if (status & HDSPM_madiLock) { 3699 if (status & HDSPM_madiSync) 3700 return 2; 3701 else 3702 return 1; 3703 } 3704 return 0; 3705 } 3706 3707 3708 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3709 { 3710 int status, lock, sync; 3711 3712 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3713 3714 lock = (status & (0x1<<idx)) ? 1 : 0; 3715 sync = (status & (0x100<<idx)) ? 1 : 0; 3716 3717 if (lock && sync) 3718 return 2; 3719 else if (lock) 3720 return 1; 3721 return 0; 3722 } 3723 3724 3725 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3726 { 3727 int status, lock = 0, sync = 0; 3728 3729 switch (hdspm->io_type) { 3730 case RayDAT: 3731 case AIO: 3732 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3733 lock = (status & 0x400) ? 1 : 0; 3734 sync = (status & 0x800) ? 1 : 0; 3735 break; 3736 3737 case MADI: 3738 status = hdspm_read(hdspm, HDSPM_statusRegister); 3739 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3740 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3741 break; 3742 3743 case AES32: 3744 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3745 lock = (status & 0x100000) ? 1 : 0; 3746 sync = (status & 0x200000) ? 1 : 0; 3747 break; 3748 3749 case MADIface: 3750 break; 3751 } 3752 3753 if (lock && sync) 3754 return 2; 3755 else if (lock) 3756 return 1; 3757 3758 return 0; 3759 } 3760 3761 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3762 { 3763 int status2, lock, sync; 3764 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3765 3766 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3767 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3768 3769 if (sync) 3770 return 2; 3771 else if (lock) 3772 return 1; 3773 return 0; 3774 } 3775 3776 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3777 { 3778 u32 status; 3779 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3780 3781 return (status & mask) ? 1 : 0; 3782 } 3783 3784 3785 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3786 { 3787 int status; 3788 3789 if (hdspm->tco) { 3790 switch (hdspm->io_type) { 3791 case MADI: 3792 case AES32: 3793 status = hdspm_read(hdspm, HDSPM_statusRegister); 3794 if (status & HDSPM_tcoLock) { 3795 if (status & HDSPM_tcoSync) 3796 return 2; 3797 else 3798 return 1; 3799 } 3800 return 0; 3801 3802 break; 3803 3804 case RayDAT: 3805 case AIO: 3806 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3807 3808 if (status & 0x8000000) 3809 return 2; /* Sync */ 3810 if (status & 0x4000000) 3811 return 1; /* Lock */ 3812 return 0; /* No signal */ 3813 break; 3814 3815 default: 3816 break; 3817 } 3818 } 3819 3820 return 3; /* N/A */ 3821 } 3822 3823 3824 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3825 struct snd_ctl_elem_value *ucontrol) 3826 { 3827 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3828 int val = -1; 3829 3830 switch (hdspm->io_type) { 3831 case RayDAT: 3832 switch (kcontrol->private_value) { 3833 case 0: /* WC */ 3834 val = hdspm_wc_sync_check(hdspm); break; 3835 case 7: /* TCO */ 3836 val = hdspm_tco_sync_check(hdspm); break; 3837 case 8: /* SYNC IN */ 3838 val = hdspm_sync_in_sync_check(hdspm); break; 3839 default: 3840 val = hdspm_s1_sync_check(hdspm, 3841 kcontrol->private_value-1); 3842 } 3843 break; 3844 3845 case AIO: 3846 switch (kcontrol->private_value) { 3847 case 0: /* WC */ 3848 val = hdspm_wc_sync_check(hdspm); break; 3849 case 4: /* TCO */ 3850 val = hdspm_tco_sync_check(hdspm); break; 3851 case 5: /* SYNC IN */ 3852 val = hdspm_sync_in_sync_check(hdspm); break; 3853 default: 3854 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3855 } 3856 break; 3857 3858 case MADI: 3859 switch (kcontrol->private_value) { 3860 case 0: /* WC */ 3861 val = hdspm_wc_sync_check(hdspm); break; 3862 case 1: /* MADI */ 3863 val = hdspm_madi_sync_check(hdspm); break; 3864 case 2: /* TCO */ 3865 val = hdspm_tco_sync_check(hdspm); break; 3866 case 3: /* SYNC_IN */ 3867 val = hdspm_sync_in_sync_check(hdspm); break; 3868 } 3869 break; 3870 3871 case MADIface: 3872 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3873 break; 3874 3875 case AES32: 3876 switch (kcontrol->private_value) { 3877 case 0: /* WC */ 3878 val = hdspm_wc_sync_check(hdspm); break; 3879 case 9: /* TCO */ 3880 val = hdspm_tco_sync_check(hdspm); break; 3881 case 10 /* SYNC IN */: 3882 val = hdspm_sync_in_sync_check(hdspm); break; 3883 default: /* AES1 to AES8 */ 3884 val = hdspm_aes_sync_check(hdspm, 3885 kcontrol->private_value-1); 3886 } 3887 break; 3888 3889 } 3890 3891 if (hdspm->tco) { 3892 switch (kcontrol->private_value) { 3893 case 11: 3894 /* Check TCO for lock state of its current input */ 3895 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 3896 break; 3897 case 12: 3898 /* Check TCO for valid time code on LTC input. */ 3899 val = hdspm_tco_input_check(hdspm, 3900 HDSPM_TCO1_LTC_Input_valid); 3901 break; 3902 default: 3903 break; 3904 } 3905 } 3906 3907 if (-1 == val) 3908 val = 3; 3909 3910 ucontrol->value.enumerated.item[0] = val; 3911 return 0; 3912 } 3913 3914 3915 3916 /** 3917 * TCO controls 3918 **/ 3919 static void hdspm_tco_write(struct hdspm *hdspm) 3920 { 3921 unsigned int tc[4] = { 0, 0, 0, 0}; 3922 3923 switch (hdspm->tco->input) { 3924 case 0: 3925 tc[2] |= HDSPM_TCO2_set_input_MSB; 3926 break; 3927 case 1: 3928 tc[2] |= HDSPM_TCO2_set_input_LSB; 3929 break; 3930 default: 3931 break; 3932 } 3933 3934 switch (hdspm->tco->framerate) { 3935 case 1: 3936 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 3937 break; 3938 case 2: 3939 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 3940 break; 3941 case 3: 3942 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 3943 HDSPM_TCO1_set_drop_frame_flag; 3944 break; 3945 case 4: 3946 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3947 HDSPM_TCO1_LTC_Format_MSB; 3948 break; 3949 case 5: 3950 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3951 HDSPM_TCO1_LTC_Format_MSB + 3952 HDSPM_TCO1_set_drop_frame_flag; 3953 break; 3954 default: 3955 break; 3956 } 3957 3958 switch (hdspm->tco->wordclock) { 3959 case 1: 3960 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 3961 break; 3962 case 2: 3963 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 3964 break; 3965 default: 3966 break; 3967 } 3968 3969 switch (hdspm->tco->samplerate) { 3970 case 1: 3971 tc[2] |= HDSPM_TCO2_set_freq; 3972 break; 3973 case 2: 3974 tc[2] |= HDSPM_TCO2_set_freq_from_app; 3975 break; 3976 default: 3977 break; 3978 } 3979 3980 switch (hdspm->tco->pull) { 3981 case 1: 3982 tc[2] |= HDSPM_TCO2_set_pull_up; 3983 break; 3984 case 2: 3985 tc[2] |= HDSPM_TCO2_set_pull_down; 3986 break; 3987 case 3: 3988 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 3989 break; 3990 case 4: 3991 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 3992 break; 3993 default: 3994 break; 3995 } 3996 3997 if (1 == hdspm->tco->term) { 3998 tc[2] |= HDSPM_TCO2_set_term_75R; 3999 } 4000 4001 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4002 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4003 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4004 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4005 } 4006 4007 4008 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4009 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4010 .name = xname, \ 4011 .index = xindex, \ 4012 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4013 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4014 .info = snd_hdspm_info_tco_sample_rate, \ 4015 .get = snd_hdspm_get_tco_sample_rate, \ 4016 .put = snd_hdspm_put_tco_sample_rate \ 4017 } 4018 4019 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4020 struct snd_ctl_elem_info *uinfo) 4021 { 4022 static char *texts[] = { "44.1 kHz", "48 kHz" }; 4023 ENUMERATED_CTL_INFO(uinfo, texts); 4024 return 0; 4025 } 4026 4027 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4028 struct snd_ctl_elem_value *ucontrol) 4029 { 4030 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4031 4032 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4033 4034 return 0; 4035 } 4036 4037 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4038 struct snd_ctl_elem_value *ucontrol) 4039 { 4040 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4041 4042 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4043 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4044 4045 hdspm_tco_write(hdspm); 4046 4047 return 1; 4048 } 4049 4050 return 0; 4051 } 4052 4053 4054 #define HDSPM_TCO_PULL(xname, xindex) \ 4055 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4056 .name = xname, \ 4057 .index = xindex, \ 4058 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4059 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4060 .info = snd_hdspm_info_tco_pull, \ 4061 .get = snd_hdspm_get_tco_pull, \ 4062 .put = snd_hdspm_put_tco_pull \ 4063 } 4064 4065 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4066 struct snd_ctl_elem_info *uinfo) 4067 { 4068 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 4069 ENUMERATED_CTL_INFO(uinfo, texts); 4070 return 0; 4071 } 4072 4073 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4074 struct snd_ctl_elem_value *ucontrol) 4075 { 4076 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4077 4078 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4079 4080 return 0; 4081 } 4082 4083 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4084 struct snd_ctl_elem_value *ucontrol) 4085 { 4086 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4087 4088 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4089 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4090 4091 hdspm_tco_write(hdspm); 4092 4093 return 1; 4094 } 4095 4096 return 0; 4097 } 4098 4099 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4101 .name = xname, \ 4102 .index = xindex, \ 4103 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4104 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4105 .info = snd_hdspm_info_tco_wck_conversion, \ 4106 .get = snd_hdspm_get_tco_wck_conversion, \ 4107 .put = snd_hdspm_put_tco_wck_conversion \ 4108 } 4109 4110 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4111 struct snd_ctl_elem_info *uinfo) 4112 { 4113 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4114 ENUMERATED_CTL_INFO(uinfo, texts); 4115 return 0; 4116 } 4117 4118 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4119 struct snd_ctl_elem_value *ucontrol) 4120 { 4121 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4122 4123 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4124 4125 return 0; 4126 } 4127 4128 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4129 struct snd_ctl_elem_value *ucontrol) 4130 { 4131 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4132 4133 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4134 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4135 4136 hdspm_tco_write(hdspm); 4137 4138 return 1; 4139 } 4140 4141 return 0; 4142 } 4143 4144 4145 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4146 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4147 .name = xname, \ 4148 .index = xindex, \ 4149 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4150 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4151 .info = snd_hdspm_info_tco_frame_rate, \ 4152 .get = snd_hdspm_get_tco_frame_rate, \ 4153 .put = snd_hdspm_put_tco_frame_rate \ 4154 } 4155 4156 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4157 struct snd_ctl_elem_info *uinfo) 4158 { 4159 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 4160 "29.97 dfps", "30 fps", "30 dfps" }; 4161 ENUMERATED_CTL_INFO(uinfo, texts); 4162 return 0; 4163 } 4164 4165 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4166 struct snd_ctl_elem_value *ucontrol) 4167 { 4168 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4169 4170 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4171 4172 return 0; 4173 } 4174 4175 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4176 struct snd_ctl_elem_value *ucontrol) 4177 { 4178 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4179 4180 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4181 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4182 4183 hdspm_tco_write(hdspm); 4184 4185 return 1; 4186 } 4187 4188 return 0; 4189 } 4190 4191 4192 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4193 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4194 .name = xname, \ 4195 .index = xindex, \ 4196 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4197 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4198 .info = snd_hdspm_info_tco_sync_source, \ 4199 .get = snd_hdspm_get_tco_sync_source, \ 4200 .put = snd_hdspm_put_tco_sync_source \ 4201 } 4202 4203 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4204 struct snd_ctl_elem_info *uinfo) 4205 { 4206 static char *texts[] = { "LTC", "Video", "WCK" }; 4207 ENUMERATED_CTL_INFO(uinfo, texts); 4208 return 0; 4209 } 4210 4211 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4212 struct snd_ctl_elem_value *ucontrol) 4213 { 4214 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4215 4216 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4217 4218 return 0; 4219 } 4220 4221 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4222 struct snd_ctl_elem_value *ucontrol) 4223 { 4224 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4225 4226 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4227 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4228 4229 hdspm_tco_write(hdspm); 4230 4231 return 1; 4232 } 4233 4234 return 0; 4235 } 4236 4237 4238 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4239 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4240 .name = xname, \ 4241 .index = xindex, \ 4242 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4243 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4244 .info = snd_hdspm_info_tco_word_term, \ 4245 .get = snd_hdspm_get_tco_word_term, \ 4246 .put = snd_hdspm_put_tco_word_term \ 4247 } 4248 4249 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4250 struct snd_ctl_elem_info *uinfo) 4251 { 4252 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4253 uinfo->count = 1; 4254 uinfo->value.integer.min = 0; 4255 uinfo->value.integer.max = 1; 4256 4257 return 0; 4258 } 4259 4260 4261 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4262 struct snd_ctl_elem_value *ucontrol) 4263 { 4264 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4265 4266 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4267 4268 return 0; 4269 } 4270 4271 4272 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4273 struct snd_ctl_elem_value *ucontrol) 4274 { 4275 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4276 4277 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4278 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4279 4280 hdspm_tco_write(hdspm); 4281 4282 return 1; 4283 } 4284 4285 return 0; 4286 } 4287 4288 4289 4290 4291 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4292 HDSPM_MIXER("Mixer", 0), 4293 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4294 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4295 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4296 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4297 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4298 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4299 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4300 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4301 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4302 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4303 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4304 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4305 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4306 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4307 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4308 HDSPM_INPUT_SELECT("Input Select", 0), 4309 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4310 }; 4311 4312 4313 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4314 HDSPM_MIXER("Mixer", 0), 4315 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4316 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4317 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4318 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4319 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4320 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4321 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4322 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4323 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4324 }; 4325 4326 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4327 HDSPM_MIXER("Mixer", 0), 4328 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4329 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4330 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4331 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4332 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4333 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4334 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4335 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4336 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4337 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4338 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4339 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4340 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4341 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4342 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4343 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4344 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4345 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4346 4347 /* 4348 HDSPM_INPUT_SELECT("Input Select", 0), 4349 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4350 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4351 HDSPM_SPDIF_IN("SPDIF In", 0); 4352 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4353 HDSPM_INPUT_LEVEL("Input Level", 0); 4354 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4355 HDSPM_PHONES("Phones", 0); 4356 */ 4357 }; 4358 4359 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4360 HDSPM_MIXER("Mixer", 0), 4361 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4362 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4363 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4364 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4365 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4366 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4367 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4368 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4369 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4370 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4371 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4372 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4373 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4374 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4375 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4376 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4377 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4378 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4379 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4380 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4381 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4382 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4383 }; 4384 4385 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4386 HDSPM_MIXER("Mixer", 0), 4387 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4388 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4389 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4390 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4391 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4392 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4393 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4394 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4395 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4396 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4397 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4398 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4399 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4400 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4401 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4402 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4403 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4404 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4405 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4406 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4407 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4408 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4409 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4410 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4411 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4412 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4413 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4414 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4415 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4416 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4417 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4418 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4419 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4420 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4421 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4422 }; 4423 4424 4425 4426 /* Control elements for the optional TCO module */ 4427 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4428 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4429 HDSPM_TCO_PULL("TCO Pull", 0), 4430 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4431 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4432 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4433 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4434 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4435 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4436 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0), 4437 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0) 4438 }; 4439 4440 4441 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4442 4443 4444 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4445 { 4446 int i; 4447 4448 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4449 if (hdspm->system_sample_rate > 48000) { 4450 hdspm->playback_mixer_ctls[i]->vd[0].access = 4451 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4452 SNDRV_CTL_ELEM_ACCESS_READ | 4453 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4454 } else { 4455 hdspm->playback_mixer_ctls[i]->vd[0].access = 4456 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4457 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4458 } 4459 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4460 SNDRV_CTL_EVENT_MASK_INFO, 4461 &hdspm->playback_mixer_ctls[i]->id); 4462 } 4463 4464 return 0; 4465 } 4466 4467 4468 static int snd_hdspm_create_controls(struct snd_card *card, 4469 struct hdspm *hdspm) 4470 { 4471 unsigned int idx, limit; 4472 int err; 4473 struct snd_kcontrol *kctl; 4474 struct snd_kcontrol_new *list = NULL; 4475 4476 switch (hdspm->io_type) { 4477 case MADI: 4478 list = snd_hdspm_controls_madi; 4479 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4480 break; 4481 case MADIface: 4482 list = snd_hdspm_controls_madiface; 4483 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4484 break; 4485 case AIO: 4486 list = snd_hdspm_controls_aio; 4487 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4488 break; 4489 case RayDAT: 4490 list = snd_hdspm_controls_raydat; 4491 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4492 break; 4493 case AES32: 4494 list = snd_hdspm_controls_aes32; 4495 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4496 break; 4497 } 4498 4499 if (NULL != list) { 4500 for (idx = 0; idx < limit; idx++) { 4501 err = snd_ctl_add(card, 4502 snd_ctl_new1(&list[idx], hdspm)); 4503 if (err < 0) 4504 return err; 4505 } 4506 } 4507 4508 4509 /* create simple 1:1 playback mixer controls */ 4510 snd_hdspm_playback_mixer.name = "Chn"; 4511 if (hdspm->system_sample_rate >= 128000) { 4512 limit = hdspm->qs_out_channels; 4513 } else if (hdspm->system_sample_rate >= 64000) { 4514 limit = hdspm->ds_out_channels; 4515 } else { 4516 limit = hdspm->ss_out_channels; 4517 } 4518 for (idx = 0; idx < limit; ++idx) { 4519 snd_hdspm_playback_mixer.index = idx + 1; 4520 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4521 err = snd_ctl_add(card, kctl); 4522 if (err < 0) 4523 return err; 4524 hdspm->playback_mixer_ctls[idx] = kctl; 4525 } 4526 4527 4528 if (hdspm->tco) { 4529 /* add tco control elements */ 4530 list = snd_hdspm_controls_tco; 4531 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4532 for (idx = 0; idx < limit; idx++) { 4533 err = snd_ctl_add(card, 4534 snd_ctl_new1(&list[idx], hdspm)); 4535 if (err < 0) 4536 return err; 4537 } 4538 } 4539 4540 return 0; 4541 } 4542 4543 /*------------------------------------------------------------ 4544 /proc interface 4545 ------------------------------------------------------------*/ 4546 4547 static void 4548 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4549 struct snd_info_buffer *buffer) 4550 { 4551 struct hdspm *hdspm = entry->private_data; 4552 unsigned int status, status2, control, freq; 4553 4554 char *pref_sync_ref; 4555 char *autosync_ref; 4556 char *system_clock_mode; 4557 char *insel; 4558 int x, x2; 4559 4560 /* TCO stuff */ 4561 int a, ltc, frames, seconds, minutes, hours; 4562 unsigned int period; 4563 u64 freq_const = 0; 4564 u32 rate; 4565 4566 status = hdspm_read(hdspm, HDSPM_statusRegister); 4567 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4568 control = hdspm->control_register; 4569 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4570 4571 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4572 hdspm->card_name, hdspm->card->number + 1, 4573 hdspm->firmware_rev, 4574 (status2 & HDSPM_version0) | 4575 (status2 & HDSPM_version1) | (status2 & 4576 HDSPM_version2)); 4577 4578 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4579 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4580 hdspm->serial); 4581 4582 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4583 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4584 4585 snd_iprintf(buffer, "--- System ---\n"); 4586 4587 snd_iprintf(buffer, 4588 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4589 status & HDSPM_audioIRQPending, 4590 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4591 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4592 hdspm->irq_count); 4593 snd_iprintf(buffer, 4594 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4595 "estimated= %ld (bytes)\n", 4596 ((status & HDSPM_BufferID) ? 1 : 0), 4597 (status & HDSPM_BufferPositionMask), 4598 (status & HDSPM_BufferPositionMask) % 4599 (2 * (int)hdspm->period_bytes), 4600 ((status & HDSPM_BufferPositionMask) - 64) % 4601 (2 * (int)hdspm->period_bytes), 4602 (long) hdspm_hw_pointer(hdspm) * 4); 4603 4604 snd_iprintf(buffer, 4605 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4606 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4607 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4608 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4609 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4610 snd_iprintf(buffer, 4611 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4612 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4613 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4614 snd_iprintf(buffer, 4615 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4616 "status2=0x%x\n", 4617 hdspm->control_register, hdspm->control2_register, 4618 status, status2); 4619 if (status & HDSPM_tco_detect) { 4620 snd_iprintf(buffer, "TCO module detected.\n"); 4621 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4622 if (a & HDSPM_TCO1_LTC_Input_valid) { 4623 snd_iprintf(buffer, " LTC valid, "); 4624 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4625 HDSPM_TCO1_LTC_Format_MSB)) { 4626 case 0: 4627 snd_iprintf(buffer, "24 fps, "); 4628 break; 4629 case HDSPM_TCO1_LTC_Format_LSB: 4630 snd_iprintf(buffer, "25 fps, "); 4631 break; 4632 case HDSPM_TCO1_LTC_Format_MSB: 4633 snd_iprintf(buffer, "29.97 fps, "); 4634 break; 4635 default: 4636 snd_iprintf(buffer, "30 fps, "); 4637 break; 4638 } 4639 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4640 snd_iprintf(buffer, "drop frame\n"); 4641 } else { 4642 snd_iprintf(buffer, "full frame\n"); 4643 } 4644 } else { 4645 snd_iprintf(buffer, " no LTC\n"); 4646 } 4647 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4648 snd_iprintf(buffer, " Video: NTSC\n"); 4649 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4650 snd_iprintf(buffer, " Video: PAL\n"); 4651 } else { 4652 snd_iprintf(buffer, " No video\n"); 4653 } 4654 if (a & HDSPM_TCO1_TCO_lock) { 4655 snd_iprintf(buffer, " Sync: lock\n"); 4656 } else { 4657 snd_iprintf(buffer, " Sync: no lock\n"); 4658 } 4659 4660 switch (hdspm->io_type) { 4661 case MADI: 4662 case AES32: 4663 freq_const = 110069313433624ULL; 4664 break; 4665 case RayDAT: 4666 case AIO: 4667 freq_const = 104857600000000ULL; 4668 break; 4669 case MADIface: 4670 break; /* no TCO possible */ 4671 } 4672 4673 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4674 snd_iprintf(buffer, " period: %u\n", period); 4675 4676 4677 /* rate = freq_const/period; */ 4678 rate = div_u64(freq_const, period); 4679 4680 if (control & HDSPM_QuadSpeed) { 4681 rate *= 4; 4682 } else if (control & HDSPM_DoubleSpeed) { 4683 rate *= 2; 4684 } 4685 4686 snd_iprintf(buffer, " Frequency: %u Hz\n", 4687 (unsigned int) rate); 4688 4689 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4690 frames = ltc & 0xF; 4691 ltc >>= 4; 4692 frames += (ltc & 0x3) * 10; 4693 ltc >>= 4; 4694 seconds = ltc & 0xF; 4695 ltc >>= 4; 4696 seconds += (ltc & 0x7) * 10; 4697 ltc >>= 4; 4698 minutes = ltc & 0xF; 4699 ltc >>= 4; 4700 minutes += (ltc & 0x7) * 10; 4701 ltc >>= 4; 4702 hours = ltc & 0xF; 4703 ltc >>= 4; 4704 hours += (ltc & 0x3) * 10; 4705 snd_iprintf(buffer, 4706 " LTC In: %02d:%02d:%02d:%02d\n", 4707 hours, minutes, seconds, frames); 4708 4709 } else { 4710 snd_iprintf(buffer, "No TCO module detected.\n"); 4711 } 4712 4713 snd_iprintf(buffer, "--- Settings ---\n"); 4714 4715 x = hdspm_get_latency(hdspm); 4716 4717 snd_iprintf(buffer, 4718 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4719 x, (unsigned long) hdspm->period_bytes); 4720 4721 snd_iprintf(buffer, "Line out: %s\n", 4722 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4723 4724 switch (hdspm->control_register & HDSPM_InputMask) { 4725 case HDSPM_InputOptical: 4726 insel = "Optical"; 4727 break; 4728 case HDSPM_InputCoaxial: 4729 insel = "Coaxial"; 4730 break; 4731 default: 4732 insel = "Unknown"; 4733 } 4734 4735 snd_iprintf(buffer, 4736 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4737 "Auto Input %s\n", 4738 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4739 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4740 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4741 4742 4743 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4744 system_clock_mode = "AutoSync"; 4745 else 4746 system_clock_mode = "Master"; 4747 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4748 4749 switch (hdspm_pref_sync_ref(hdspm)) { 4750 case HDSPM_SYNC_FROM_WORD: 4751 pref_sync_ref = "Word Clock"; 4752 break; 4753 case HDSPM_SYNC_FROM_MADI: 4754 pref_sync_ref = "MADI Sync"; 4755 break; 4756 case HDSPM_SYNC_FROM_TCO: 4757 pref_sync_ref = "TCO"; 4758 break; 4759 case HDSPM_SYNC_FROM_SYNC_IN: 4760 pref_sync_ref = "Sync In"; 4761 break; 4762 default: 4763 pref_sync_ref = "XXXX Clock"; 4764 break; 4765 } 4766 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4767 pref_sync_ref); 4768 4769 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4770 hdspm->system_sample_rate); 4771 4772 4773 snd_iprintf(buffer, "--- Status:\n"); 4774 4775 x = status & HDSPM_madiSync; 4776 x2 = status2 & HDSPM_wcSync; 4777 4778 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4779 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4780 "NoLock", 4781 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4782 "NoLock"); 4783 4784 switch (hdspm_autosync_ref(hdspm)) { 4785 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4786 autosync_ref = "Sync In"; 4787 break; 4788 case HDSPM_AUTOSYNC_FROM_TCO: 4789 autosync_ref = "TCO"; 4790 break; 4791 case HDSPM_AUTOSYNC_FROM_WORD: 4792 autosync_ref = "Word Clock"; 4793 break; 4794 case HDSPM_AUTOSYNC_FROM_MADI: 4795 autosync_ref = "MADI Sync"; 4796 break; 4797 case HDSPM_AUTOSYNC_FROM_NONE: 4798 autosync_ref = "Input not valid"; 4799 break; 4800 default: 4801 autosync_ref = "---"; 4802 break; 4803 } 4804 snd_iprintf(buffer, 4805 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4806 autosync_ref, hdspm_external_sample_rate(hdspm), 4807 (status & HDSPM_madiFreqMask) >> 22, 4808 (status2 & HDSPM_wcFreqMask) >> 5); 4809 4810 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4811 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4812 (status & HDSPM_RX_64ch) ? "64 channels" : 4813 "56 channels"); 4814 4815 snd_iprintf(buffer, "\n"); 4816 } 4817 4818 static void 4819 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4820 struct snd_info_buffer *buffer) 4821 { 4822 struct hdspm *hdspm = entry->private_data; 4823 unsigned int status; 4824 unsigned int status2; 4825 unsigned int timecode; 4826 unsigned int wcLock, wcSync; 4827 int pref_syncref; 4828 char *autosync_ref; 4829 int x; 4830 4831 status = hdspm_read(hdspm, HDSPM_statusRegister); 4832 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4833 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4834 4835 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4836 hdspm->card_name, hdspm->card->number + 1, 4837 hdspm->firmware_rev); 4838 4839 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4840 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4841 4842 snd_iprintf(buffer, "--- System ---\n"); 4843 4844 snd_iprintf(buffer, 4845 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4846 status & HDSPM_audioIRQPending, 4847 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4848 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4849 hdspm->irq_count); 4850 snd_iprintf(buffer, 4851 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4852 "estimated= %ld (bytes)\n", 4853 ((status & HDSPM_BufferID) ? 1 : 0), 4854 (status & HDSPM_BufferPositionMask), 4855 (status & HDSPM_BufferPositionMask) % 4856 (2 * (int)hdspm->period_bytes), 4857 ((status & HDSPM_BufferPositionMask) - 64) % 4858 (2 * (int)hdspm->period_bytes), 4859 (long) hdspm_hw_pointer(hdspm) * 4); 4860 4861 snd_iprintf(buffer, 4862 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4863 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4864 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4865 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4866 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4867 snd_iprintf(buffer, 4868 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4869 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4870 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4871 snd_iprintf(buffer, 4872 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4873 "status2=0x%x\n", 4874 hdspm->control_register, hdspm->control2_register, 4875 status, status2); 4876 4877 snd_iprintf(buffer, "--- Settings ---\n"); 4878 4879 x = hdspm_get_latency(hdspm); 4880 4881 snd_iprintf(buffer, 4882 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4883 x, (unsigned long) hdspm->period_bytes); 4884 4885 snd_iprintf(buffer, "Line out: %s\n", 4886 (hdspm-> 4887 control_register & HDSPM_LineOut) ? "on " : "off"); 4888 4889 snd_iprintf(buffer, 4890 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 4891 (hdspm-> 4892 control_register & HDSPM_clr_tms) ? "on" : "off", 4893 (hdspm-> 4894 control_register & HDSPM_Emphasis) ? "on" : "off", 4895 (hdspm-> 4896 control_register & HDSPM_Dolby) ? "on" : "off"); 4897 4898 4899 pref_syncref = hdspm_pref_sync_ref(hdspm); 4900 if (pref_syncref == 0) 4901 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 4902 else 4903 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 4904 pref_syncref); 4905 4906 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4907 hdspm->system_sample_rate); 4908 4909 snd_iprintf(buffer, "Double speed: %s\n", 4910 hdspm->control_register & HDSPM_DS_DoubleWire? 4911 "Double wire" : "Single wire"); 4912 snd_iprintf(buffer, "Quad speed: %s\n", 4913 hdspm->control_register & HDSPM_QS_DoubleWire? 4914 "Double wire" : 4915 hdspm->control_register & HDSPM_QS_QuadWire? 4916 "Quad wire" : "Single wire"); 4917 4918 snd_iprintf(buffer, "--- Status:\n"); 4919 4920 wcLock = status & HDSPM_AES32_wcLock; 4921 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 4922 4923 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 4924 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 4925 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 4926 4927 for (x = 0; x < 8; x++) { 4928 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 4929 x+1, 4930 (status2 & (HDSPM_LockAES >> x)) ? 4931 "Sync " : "No Lock", 4932 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 4933 } 4934 4935 switch (hdspm_autosync_ref(hdspm)) { 4936 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 4937 autosync_ref = "None"; break; 4938 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 4939 autosync_ref = "Word Clock"; break; 4940 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 4941 autosync_ref = "AES1"; break; 4942 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 4943 autosync_ref = "AES2"; break; 4944 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 4945 autosync_ref = "AES3"; break; 4946 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 4947 autosync_ref = "AES4"; break; 4948 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 4949 autosync_ref = "AES5"; break; 4950 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 4951 autosync_ref = "AES6"; break; 4952 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 4953 autosync_ref = "AES7"; break; 4954 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 4955 autosync_ref = "AES8"; break; 4956 default: 4957 autosync_ref = "---"; break; 4958 } 4959 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 4960 4961 snd_iprintf(buffer, "\n"); 4962 } 4963 4964 static void 4965 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 4966 struct snd_info_buffer *buffer) 4967 { 4968 struct hdspm *hdspm = entry->private_data; 4969 unsigned int status1, status2, status3, control, i; 4970 unsigned int lock, sync; 4971 4972 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 4973 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 4974 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 4975 4976 control = hdspm->control_register; 4977 4978 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 4979 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 4980 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 4981 4982 4983 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 4984 4985 snd_iprintf(buffer, "Clock mode : %s\n", 4986 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 4987 snd_iprintf(buffer, "System frequency: %d Hz\n", 4988 hdspm_get_system_sample_rate(hdspm)); 4989 4990 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 4991 4992 lock = 0x1; 4993 sync = 0x100; 4994 4995 for (i = 0; i < 8; i++) { 4996 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 4997 i, 4998 (status1 & lock) ? 1 : 0, 4999 (status1 & sync) ? 1 : 0, 5000 texts_freq[(status2 >> (i * 4)) & 0xF]); 5001 5002 lock = lock<<1; 5003 sync = sync<<1; 5004 } 5005 5006 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5007 (status1 & 0x1000000) ? 1 : 0, 5008 (status1 & 0x2000000) ? 1 : 0, 5009 texts_freq[(status1 >> 16) & 0xF]); 5010 5011 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5012 (status1 & 0x4000000) ? 1 : 0, 5013 (status1 & 0x8000000) ? 1 : 0, 5014 texts_freq[(status1 >> 20) & 0xF]); 5015 5016 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5017 (status3 & 0x400) ? 1 : 0, 5018 (status3 & 0x800) ? 1 : 0, 5019 texts_freq[(status2 >> 12) & 0xF]); 5020 5021 } 5022 5023 #ifdef CONFIG_SND_DEBUG 5024 static void 5025 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5026 struct snd_info_buffer *buffer) 5027 { 5028 struct hdspm *hdspm = entry->private_data; 5029 5030 int j,i; 5031 5032 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5033 snd_iprintf(buffer, "0x%08X: ", i); 5034 for (j = 0; j < 16; j += 4) 5035 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5036 snd_iprintf(buffer, "\n"); 5037 } 5038 } 5039 #endif 5040 5041 5042 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5043 struct snd_info_buffer *buffer) 5044 { 5045 struct hdspm *hdspm = entry->private_data; 5046 int i; 5047 5048 snd_iprintf(buffer, "# generated by hdspm\n"); 5049 5050 for (i = 0; i < hdspm->max_channels_in; i++) { 5051 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5052 } 5053 } 5054 5055 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5056 struct snd_info_buffer *buffer) 5057 { 5058 struct hdspm *hdspm = entry->private_data; 5059 int i; 5060 5061 snd_iprintf(buffer, "# generated by hdspm\n"); 5062 5063 for (i = 0; i < hdspm->max_channels_out; i++) { 5064 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5065 } 5066 } 5067 5068 5069 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5070 { 5071 struct snd_info_entry *entry; 5072 5073 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5074 switch (hdspm->io_type) { 5075 case AES32: 5076 snd_info_set_text_ops(entry, hdspm, 5077 snd_hdspm_proc_read_aes32); 5078 break; 5079 case MADI: 5080 snd_info_set_text_ops(entry, hdspm, 5081 snd_hdspm_proc_read_madi); 5082 break; 5083 case MADIface: 5084 /* snd_info_set_text_ops(entry, hdspm, 5085 snd_hdspm_proc_read_madiface); */ 5086 break; 5087 case RayDAT: 5088 snd_info_set_text_ops(entry, hdspm, 5089 snd_hdspm_proc_read_raydat); 5090 break; 5091 case AIO: 5092 break; 5093 } 5094 } 5095 5096 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5097 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5098 } 5099 5100 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5101 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5102 } 5103 5104 #ifdef CONFIG_SND_DEBUG 5105 /* debug file to read all hdspm registers */ 5106 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5107 snd_info_set_text_ops(entry, hdspm, 5108 snd_hdspm_proc_read_debug); 5109 #endif 5110 } 5111 5112 /*------------------------------------------------------------ 5113 hdspm intitialize 5114 ------------------------------------------------------------*/ 5115 5116 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5117 { 5118 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5119 hold it (e.g. during module initialization). 5120 */ 5121 5122 /* set defaults: */ 5123 5124 hdspm->settings_register = 0; 5125 5126 switch (hdspm->io_type) { 5127 case MADI: 5128 case MADIface: 5129 hdspm->control_register = 5130 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5131 break; 5132 5133 case RayDAT: 5134 case AIO: 5135 hdspm->settings_register = 0x1 + 0x1000; 5136 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5137 * line_out */ 5138 hdspm->control_register = 5139 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5140 break; 5141 5142 case AES32: 5143 hdspm->control_register = 5144 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 5145 hdspm_encode_latency(7) | /* latency max=8192samples */ 5146 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5147 HDSPM_LineOut | /* Analog output in */ 5148 HDSPM_Professional; /* Professional mode */ 5149 break; 5150 } 5151 5152 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5153 5154 if (AES32 == hdspm->io_type) { 5155 /* No control2 register for AES32 */ 5156 #ifdef SNDRV_BIG_ENDIAN 5157 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5158 #else 5159 hdspm->control2_register = 0; 5160 #endif 5161 5162 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5163 } 5164 hdspm_compute_period_size(hdspm); 5165 5166 /* silence everything */ 5167 5168 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5169 5170 if (hdspm_is_raydat_or_aio(hdspm)) 5171 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5172 5173 /* set a default rate so that the channel map is set up. */ 5174 hdspm_set_rate(hdspm, 48000, 1); 5175 5176 return 0; 5177 } 5178 5179 5180 /*------------------------------------------------------------ 5181 interrupt 5182 ------------------------------------------------------------*/ 5183 5184 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5185 { 5186 struct hdspm *hdspm = (struct hdspm *) dev_id; 5187 unsigned int status; 5188 int i, audio, midi, schedule = 0; 5189 /* cycles_t now; */ 5190 5191 status = hdspm_read(hdspm, HDSPM_statusRegister); 5192 5193 audio = status & HDSPM_audioIRQPending; 5194 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5195 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5196 5197 /* now = get_cycles(); */ 5198 /** 5199 * LAT_2..LAT_0 period counter (win) counter (mac) 5200 * 6 4096 ~256053425 ~514672358 5201 * 5 2048 ~128024983 ~257373821 5202 * 4 1024 ~64023706 ~128718089 5203 * 3 512 ~32005945 ~64385999 5204 * 2 256 ~16003039 ~32260176 5205 * 1 128 ~7998738 ~16194507 5206 * 0 64 ~3998231 ~8191558 5207 **/ 5208 /* 5209 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5210 now-hdspm->last_interrupt, status & 0xFFC0); 5211 hdspm->last_interrupt = now; 5212 */ 5213 5214 if (!audio && !midi) 5215 return IRQ_NONE; 5216 5217 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5218 hdspm->irq_count++; 5219 5220 5221 if (audio) { 5222 if (hdspm->capture_substream) 5223 snd_pcm_period_elapsed(hdspm->capture_substream); 5224 5225 if (hdspm->playback_substream) 5226 snd_pcm_period_elapsed(hdspm->playback_substream); 5227 } 5228 5229 if (midi) { 5230 i = 0; 5231 while (i < hdspm->midiPorts) { 5232 if ((hdspm_read(hdspm, 5233 hdspm->midi[i].statusIn) & 0xff) && 5234 (status & hdspm->midi[i].irq)) { 5235 /* we disable interrupts for this input until 5236 * processing is done 5237 */ 5238 hdspm->control_register &= ~hdspm->midi[i].ie; 5239 hdspm_write(hdspm, HDSPM_controlRegister, 5240 hdspm->control_register); 5241 hdspm->midi[i].pending = 1; 5242 schedule = 1; 5243 } 5244 5245 i++; 5246 } 5247 5248 if (schedule) 5249 tasklet_hi_schedule(&hdspm->midi_tasklet); 5250 } 5251 5252 return IRQ_HANDLED; 5253 } 5254 5255 /*------------------------------------------------------------ 5256 pcm interface 5257 ------------------------------------------------------------*/ 5258 5259 5260 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5261 *substream) 5262 { 5263 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5264 return hdspm_hw_pointer(hdspm); 5265 } 5266 5267 5268 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5269 { 5270 struct snd_pcm_runtime *runtime = substream->runtime; 5271 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5272 struct snd_pcm_substream *other; 5273 5274 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5275 other = hdspm->capture_substream; 5276 else 5277 other = hdspm->playback_substream; 5278 5279 if (hdspm->running) 5280 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5281 else 5282 runtime->status->hw_ptr = 0; 5283 if (other) { 5284 struct snd_pcm_substream *s; 5285 struct snd_pcm_runtime *oruntime = other->runtime; 5286 snd_pcm_group_for_each_entry(s, substream) { 5287 if (s == other) { 5288 oruntime->status->hw_ptr = 5289 runtime->status->hw_ptr; 5290 break; 5291 } 5292 } 5293 } 5294 return 0; 5295 } 5296 5297 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5298 struct snd_pcm_hw_params *params) 5299 { 5300 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5301 int err; 5302 int i; 5303 pid_t this_pid; 5304 pid_t other_pid; 5305 5306 spin_lock_irq(&hdspm->lock); 5307 5308 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5309 this_pid = hdspm->playback_pid; 5310 other_pid = hdspm->capture_pid; 5311 } else { 5312 this_pid = hdspm->capture_pid; 5313 other_pid = hdspm->playback_pid; 5314 } 5315 5316 if (other_pid > 0 && this_pid != other_pid) { 5317 5318 /* The other stream is open, and not by the same 5319 task as this one. Make sure that the parameters 5320 that matter are the same. 5321 */ 5322 5323 if (params_rate(params) != hdspm->system_sample_rate) { 5324 spin_unlock_irq(&hdspm->lock); 5325 _snd_pcm_hw_param_setempty(params, 5326 SNDRV_PCM_HW_PARAM_RATE); 5327 return -EBUSY; 5328 } 5329 5330 if (params_period_size(params) != hdspm->period_bytes / 4) { 5331 spin_unlock_irq(&hdspm->lock); 5332 _snd_pcm_hw_param_setempty(params, 5333 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5334 return -EBUSY; 5335 } 5336 5337 } 5338 /* We're fine. */ 5339 spin_unlock_irq(&hdspm->lock); 5340 5341 /* how to make sure that the rate matches an externally-set one ? */ 5342 5343 spin_lock_irq(&hdspm->lock); 5344 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5345 if (err < 0) { 5346 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5347 spin_unlock_irq(&hdspm->lock); 5348 _snd_pcm_hw_param_setempty(params, 5349 SNDRV_PCM_HW_PARAM_RATE); 5350 return err; 5351 } 5352 spin_unlock_irq(&hdspm->lock); 5353 5354 err = hdspm_set_interrupt_interval(hdspm, 5355 params_period_size(params)); 5356 if (err < 0) { 5357 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5358 _snd_pcm_hw_param_setempty(params, 5359 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5360 return err; 5361 } 5362 5363 /* Memory allocation, takashi's method, dont know if we should 5364 * spinlock 5365 */ 5366 /* malloc all buffer even if not enabled to get sure */ 5367 /* Update for MADI rev 204: we need to allocate for all channels, 5368 * otherwise it doesn't work at 96kHz */ 5369 5370 err = 5371 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5372 if (err < 0) { 5373 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5374 return err; 5375 } 5376 5377 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5378 5379 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5380 params_channels(params)); 5381 5382 for (i = 0; i < params_channels(params); ++i) 5383 snd_hdspm_enable_out(hdspm, i, 1); 5384 5385 hdspm->playback_buffer = 5386 (unsigned char *) substream->runtime->dma_area; 5387 snd_printdd("Allocated sample buffer for playback at %p\n", 5388 hdspm->playback_buffer); 5389 } else { 5390 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5391 params_channels(params)); 5392 5393 for (i = 0; i < params_channels(params); ++i) 5394 snd_hdspm_enable_in(hdspm, i, 1); 5395 5396 hdspm->capture_buffer = 5397 (unsigned char *) substream->runtime->dma_area; 5398 snd_printdd("Allocated sample buffer for capture at %p\n", 5399 hdspm->capture_buffer); 5400 } 5401 5402 /* 5403 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5404 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5405 "playback" : "capture", 5406 snd_pcm_sgbuf_get_addr(substream, 0)); 5407 */ 5408 /* 5409 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5410 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5411 "playback" : "capture", 5412 params_rate(params), params_channels(params), 5413 params_buffer_size(params)); 5414 */ 5415 5416 5417 /* Switch to native float format if requested */ 5418 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5419 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5420 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5421 5422 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5423 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5424 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5425 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5426 5427 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5428 } 5429 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5430 5431 return 0; 5432 } 5433 5434 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5435 { 5436 int i; 5437 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5438 5439 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5440 5441 /* params_channels(params) should be enough, 5442 but to get sure in case of error */ 5443 for (i = 0; i < hdspm->max_channels_out; ++i) 5444 snd_hdspm_enable_out(hdspm, i, 0); 5445 5446 hdspm->playback_buffer = NULL; 5447 } else { 5448 for (i = 0; i < hdspm->max_channels_in; ++i) 5449 snd_hdspm_enable_in(hdspm, i, 0); 5450 5451 hdspm->capture_buffer = NULL; 5452 5453 } 5454 5455 snd_pcm_lib_free_pages(substream); 5456 5457 return 0; 5458 } 5459 5460 5461 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5462 struct snd_pcm_channel_info *info) 5463 { 5464 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5465 5466 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5467 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5468 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5469 return -EINVAL; 5470 } 5471 5472 if (hdspm->channel_map_out[info->channel] < 0) { 5473 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5474 return -EINVAL; 5475 } 5476 5477 info->offset = hdspm->channel_map_out[info->channel] * 5478 HDSPM_CHANNEL_BUFFER_BYTES; 5479 } else { 5480 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5481 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5482 return -EINVAL; 5483 } 5484 5485 if (hdspm->channel_map_in[info->channel] < 0) { 5486 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5487 return -EINVAL; 5488 } 5489 5490 info->offset = hdspm->channel_map_in[info->channel] * 5491 HDSPM_CHANNEL_BUFFER_BYTES; 5492 } 5493 5494 info->first = 0; 5495 info->step = 32; 5496 return 0; 5497 } 5498 5499 5500 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5501 unsigned int cmd, void *arg) 5502 { 5503 switch (cmd) { 5504 case SNDRV_PCM_IOCTL1_RESET: 5505 return snd_hdspm_reset(substream); 5506 5507 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5508 { 5509 struct snd_pcm_channel_info *info = arg; 5510 return snd_hdspm_channel_info(substream, info); 5511 } 5512 default: 5513 break; 5514 } 5515 5516 return snd_pcm_lib_ioctl(substream, cmd, arg); 5517 } 5518 5519 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5520 { 5521 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5522 struct snd_pcm_substream *other; 5523 int running; 5524 5525 spin_lock(&hdspm->lock); 5526 running = hdspm->running; 5527 switch (cmd) { 5528 case SNDRV_PCM_TRIGGER_START: 5529 running |= 1 << substream->stream; 5530 break; 5531 case SNDRV_PCM_TRIGGER_STOP: 5532 running &= ~(1 << substream->stream); 5533 break; 5534 default: 5535 snd_BUG(); 5536 spin_unlock(&hdspm->lock); 5537 return -EINVAL; 5538 } 5539 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5540 other = hdspm->capture_substream; 5541 else 5542 other = hdspm->playback_substream; 5543 5544 if (other) { 5545 struct snd_pcm_substream *s; 5546 snd_pcm_group_for_each_entry(s, substream) { 5547 if (s == other) { 5548 snd_pcm_trigger_done(s, substream); 5549 if (cmd == SNDRV_PCM_TRIGGER_START) 5550 running |= 1 << s->stream; 5551 else 5552 running &= ~(1 << s->stream); 5553 goto _ok; 5554 } 5555 } 5556 if (cmd == SNDRV_PCM_TRIGGER_START) { 5557 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5558 && substream->stream == 5559 SNDRV_PCM_STREAM_CAPTURE) 5560 hdspm_silence_playback(hdspm); 5561 } else { 5562 if (running && 5563 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5564 hdspm_silence_playback(hdspm); 5565 } 5566 } else { 5567 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5568 hdspm_silence_playback(hdspm); 5569 } 5570 _ok: 5571 snd_pcm_trigger_done(substream, substream); 5572 if (!hdspm->running && running) 5573 hdspm_start_audio(hdspm); 5574 else if (hdspm->running && !running) 5575 hdspm_stop_audio(hdspm); 5576 hdspm->running = running; 5577 spin_unlock(&hdspm->lock); 5578 5579 return 0; 5580 } 5581 5582 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5583 { 5584 return 0; 5585 } 5586 5587 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5588 .info = (SNDRV_PCM_INFO_MMAP | 5589 SNDRV_PCM_INFO_MMAP_VALID | 5590 SNDRV_PCM_INFO_NONINTERLEAVED | 5591 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5592 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5593 .rates = (SNDRV_PCM_RATE_32000 | 5594 SNDRV_PCM_RATE_44100 | 5595 SNDRV_PCM_RATE_48000 | 5596 SNDRV_PCM_RATE_64000 | 5597 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5598 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5599 .rate_min = 32000, 5600 .rate_max = 192000, 5601 .channels_min = 1, 5602 .channels_max = HDSPM_MAX_CHANNELS, 5603 .buffer_bytes_max = 5604 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5605 .period_bytes_min = (32 * 4), 5606 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5607 .periods_min = 2, 5608 .periods_max = 512, 5609 .fifo_size = 0 5610 }; 5611 5612 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5613 .info = (SNDRV_PCM_INFO_MMAP | 5614 SNDRV_PCM_INFO_MMAP_VALID | 5615 SNDRV_PCM_INFO_NONINTERLEAVED | 5616 SNDRV_PCM_INFO_SYNC_START), 5617 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5618 .rates = (SNDRV_PCM_RATE_32000 | 5619 SNDRV_PCM_RATE_44100 | 5620 SNDRV_PCM_RATE_48000 | 5621 SNDRV_PCM_RATE_64000 | 5622 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5623 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5624 .rate_min = 32000, 5625 .rate_max = 192000, 5626 .channels_min = 1, 5627 .channels_max = HDSPM_MAX_CHANNELS, 5628 .buffer_bytes_max = 5629 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5630 .period_bytes_min = (32 * 4), 5631 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5632 .periods_min = 2, 5633 .periods_max = 512, 5634 .fifo_size = 0 5635 }; 5636 5637 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5638 struct snd_pcm_hw_rule *rule) 5639 { 5640 struct hdspm *hdspm = rule->private; 5641 struct snd_interval *c = 5642 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5643 struct snd_interval *r = 5644 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5645 5646 if (r->min > 96000 && r->max <= 192000) { 5647 struct snd_interval t = { 5648 .min = hdspm->qs_in_channels, 5649 .max = hdspm->qs_in_channels, 5650 .integer = 1, 5651 }; 5652 return snd_interval_refine(c, &t); 5653 } else if (r->min > 48000 && r->max <= 96000) { 5654 struct snd_interval t = { 5655 .min = hdspm->ds_in_channels, 5656 .max = hdspm->ds_in_channels, 5657 .integer = 1, 5658 }; 5659 return snd_interval_refine(c, &t); 5660 } else if (r->max < 64000) { 5661 struct snd_interval t = { 5662 .min = hdspm->ss_in_channels, 5663 .max = hdspm->ss_in_channels, 5664 .integer = 1, 5665 }; 5666 return snd_interval_refine(c, &t); 5667 } 5668 5669 return 0; 5670 } 5671 5672 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5673 struct snd_pcm_hw_rule * rule) 5674 { 5675 struct hdspm *hdspm = rule->private; 5676 struct snd_interval *c = 5677 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5678 struct snd_interval *r = 5679 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5680 5681 if (r->min > 96000 && r->max <= 192000) { 5682 struct snd_interval t = { 5683 .min = hdspm->qs_out_channels, 5684 .max = hdspm->qs_out_channels, 5685 .integer = 1, 5686 }; 5687 return snd_interval_refine(c, &t); 5688 } else if (r->min > 48000 && r->max <= 96000) { 5689 struct snd_interval t = { 5690 .min = hdspm->ds_out_channels, 5691 .max = hdspm->ds_out_channels, 5692 .integer = 1, 5693 }; 5694 return snd_interval_refine(c, &t); 5695 } else if (r->max < 64000) { 5696 struct snd_interval t = { 5697 .min = hdspm->ss_out_channels, 5698 .max = hdspm->ss_out_channels, 5699 .integer = 1, 5700 }; 5701 return snd_interval_refine(c, &t); 5702 } else { 5703 } 5704 return 0; 5705 } 5706 5707 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5708 struct snd_pcm_hw_rule * rule) 5709 { 5710 struct hdspm *hdspm = rule->private; 5711 struct snd_interval *c = 5712 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5713 struct snd_interval *r = 5714 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5715 5716 if (c->min >= hdspm->ss_in_channels) { 5717 struct snd_interval t = { 5718 .min = 32000, 5719 .max = 48000, 5720 .integer = 1, 5721 }; 5722 return snd_interval_refine(r, &t); 5723 } else if (c->max <= hdspm->qs_in_channels) { 5724 struct snd_interval t = { 5725 .min = 128000, 5726 .max = 192000, 5727 .integer = 1, 5728 }; 5729 return snd_interval_refine(r, &t); 5730 } else if (c->max <= hdspm->ds_in_channels) { 5731 struct snd_interval t = { 5732 .min = 64000, 5733 .max = 96000, 5734 .integer = 1, 5735 }; 5736 return snd_interval_refine(r, &t); 5737 } 5738 5739 return 0; 5740 } 5741 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5742 struct snd_pcm_hw_rule *rule) 5743 { 5744 struct hdspm *hdspm = rule->private; 5745 struct snd_interval *c = 5746 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5747 struct snd_interval *r = 5748 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5749 5750 if (c->min >= hdspm->ss_out_channels) { 5751 struct snd_interval t = { 5752 .min = 32000, 5753 .max = 48000, 5754 .integer = 1, 5755 }; 5756 return snd_interval_refine(r, &t); 5757 } else if (c->max <= hdspm->qs_out_channels) { 5758 struct snd_interval t = { 5759 .min = 128000, 5760 .max = 192000, 5761 .integer = 1, 5762 }; 5763 return snd_interval_refine(r, &t); 5764 } else if (c->max <= hdspm->ds_out_channels) { 5765 struct snd_interval t = { 5766 .min = 64000, 5767 .max = 96000, 5768 .integer = 1, 5769 }; 5770 return snd_interval_refine(r, &t); 5771 } 5772 5773 return 0; 5774 } 5775 5776 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5777 struct snd_pcm_hw_rule *rule) 5778 { 5779 unsigned int list[3]; 5780 struct hdspm *hdspm = rule->private; 5781 struct snd_interval *c = hw_param_interval(params, 5782 SNDRV_PCM_HW_PARAM_CHANNELS); 5783 5784 list[0] = hdspm->qs_in_channels; 5785 list[1] = hdspm->ds_in_channels; 5786 list[2] = hdspm->ss_in_channels; 5787 return snd_interval_list(c, 3, list, 0); 5788 } 5789 5790 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5791 struct snd_pcm_hw_rule *rule) 5792 { 5793 unsigned int list[3]; 5794 struct hdspm *hdspm = rule->private; 5795 struct snd_interval *c = hw_param_interval(params, 5796 SNDRV_PCM_HW_PARAM_CHANNELS); 5797 5798 list[0] = hdspm->qs_out_channels; 5799 list[1] = hdspm->ds_out_channels; 5800 list[2] = hdspm->ss_out_channels; 5801 return snd_interval_list(c, 3, list, 0); 5802 } 5803 5804 5805 static unsigned int hdspm_aes32_sample_rates[] = { 5806 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5807 }; 5808 5809 static struct snd_pcm_hw_constraint_list 5810 hdspm_hw_constraints_aes32_sample_rates = { 5811 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5812 .list = hdspm_aes32_sample_rates, 5813 .mask = 0 5814 }; 5815 5816 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5817 { 5818 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5819 struct snd_pcm_runtime *runtime = substream->runtime; 5820 5821 spin_lock_irq(&hdspm->lock); 5822 5823 snd_pcm_set_sync(substream); 5824 5825 5826 runtime->hw = snd_hdspm_playback_subinfo; 5827 5828 if (hdspm->capture_substream == NULL) 5829 hdspm_stop_audio(hdspm); 5830 5831 hdspm->playback_pid = current->pid; 5832 hdspm->playback_substream = substream; 5833 5834 spin_unlock_irq(&hdspm->lock); 5835 5836 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5837 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5838 5839 switch (hdspm->io_type) { 5840 case AIO: 5841 case RayDAT: 5842 snd_pcm_hw_constraint_minmax(runtime, 5843 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5844 32, 4096); 5845 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 5846 snd_pcm_hw_constraint_minmax(runtime, 5847 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5848 16384, 16384); 5849 break; 5850 5851 default: 5852 snd_pcm_hw_constraint_minmax(runtime, 5853 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5854 64, 8192); 5855 break; 5856 } 5857 5858 if (AES32 == hdspm->io_type) { 5859 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5860 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5861 &hdspm_hw_constraints_aes32_sample_rates); 5862 } else { 5863 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5864 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5865 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5866 } 5867 5868 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5869 snd_hdspm_hw_rule_out_channels, hdspm, 5870 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5871 5872 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5873 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5874 SNDRV_PCM_HW_PARAM_RATE, -1); 5875 5876 return 0; 5877 } 5878 5879 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5880 { 5881 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5882 5883 spin_lock_irq(&hdspm->lock); 5884 5885 hdspm->playback_pid = -1; 5886 hdspm->playback_substream = NULL; 5887 5888 spin_unlock_irq(&hdspm->lock); 5889 5890 return 0; 5891 } 5892 5893 5894 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 5895 { 5896 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5897 struct snd_pcm_runtime *runtime = substream->runtime; 5898 5899 spin_lock_irq(&hdspm->lock); 5900 snd_pcm_set_sync(substream); 5901 runtime->hw = snd_hdspm_capture_subinfo; 5902 5903 if (hdspm->playback_substream == NULL) 5904 hdspm_stop_audio(hdspm); 5905 5906 hdspm->capture_pid = current->pid; 5907 hdspm->capture_substream = substream; 5908 5909 spin_unlock_irq(&hdspm->lock); 5910 5911 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5912 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5913 5914 switch (hdspm->io_type) { 5915 case AIO: 5916 case RayDAT: 5917 snd_pcm_hw_constraint_minmax(runtime, 5918 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5919 32, 4096); 5920 snd_pcm_hw_constraint_minmax(runtime, 5921 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5922 16384, 16384); 5923 break; 5924 5925 default: 5926 snd_pcm_hw_constraint_minmax(runtime, 5927 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5928 64, 8192); 5929 break; 5930 } 5931 5932 if (AES32 == hdspm->io_type) { 5933 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5934 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5935 &hdspm_hw_constraints_aes32_sample_rates); 5936 } else { 5937 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5938 snd_hdspm_hw_rule_rate_in_channels, hdspm, 5939 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5940 } 5941 5942 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5943 snd_hdspm_hw_rule_in_channels, hdspm, 5944 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5945 5946 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5947 snd_hdspm_hw_rule_in_channels_rate, hdspm, 5948 SNDRV_PCM_HW_PARAM_RATE, -1); 5949 5950 return 0; 5951 } 5952 5953 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 5954 { 5955 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5956 5957 spin_lock_irq(&hdspm->lock); 5958 5959 hdspm->capture_pid = -1; 5960 hdspm->capture_substream = NULL; 5961 5962 spin_unlock_irq(&hdspm->lock); 5963 return 0; 5964 } 5965 5966 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 5967 { 5968 /* we have nothing to initialize but the call is required */ 5969 return 0; 5970 } 5971 5972 static inline int copy_u32_le(void __user *dest, void __iomem *src) 5973 { 5974 u32 val = readl(src); 5975 return copy_to_user(dest, &val, 4); 5976 } 5977 5978 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 5979 unsigned int cmd, unsigned long arg) 5980 { 5981 void __user *argp = (void __user *)arg; 5982 struct hdspm *hdspm = hw->private_data; 5983 struct hdspm_mixer_ioctl mixer; 5984 struct hdspm_config info; 5985 struct hdspm_status status; 5986 struct hdspm_version hdspm_version; 5987 struct hdspm_peak_rms *levels; 5988 struct hdspm_ltc ltc; 5989 unsigned int statusregister; 5990 long unsigned int s; 5991 int i = 0; 5992 5993 switch (cmd) { 5994 5995 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 5996 levels = &hdspm->peak_rms; 5997 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 5998 levels->input_peaks[i] = 5999 readl(hdspm->iobase + 6000 HDSPM_MADI_INPUT_PEAK + i*4); 6001 levels->playback_peaks[i] = 6002 readl(hdspm->iobase + 6003 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6004 levels->output_peaks[i] = 6005 readl(hdspm->iobase + 6006 HDSPM_MADI_OUTPUT_PEAK + i*4); 6007 6008 levels->input_rms[i] = 6009 ((uint64_t) readl(hdspm->iobase + 6010 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6011 (uint64_t) readl(hdspm->iobase + 6012 HDSPM_MADI_INPUT_RMS_L + i*4); 6013 levels->playback_rms[i] = 6014 ((uint64_t)readl(hdspm->iobase + 6015 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6016 (uint64_t)readl(hdspm->iobase + 6017 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6018 levels->output_rms[i] = 6019 ((uint64_t)readl(hdspm->iobase + 6020 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6021 (uint64_t)readl(hdspm->iobase + 6022 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6023 } 6024 6025 if (hdspm->system_sample_rate > 96000) { 6026 levels->speed = qs; 6027 } else if (hdspm->system_sample_rate > 48000) { 6028 levels->speed = ds; 6029 } else { 6030 levels->speed = ss; 6031 } 6032 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6033 6034 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 6035 if (0 != s) { 6036 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 6037 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6038 */ 6039 return -EFAULT; 6040 } 6041 break; 6042 6043 case SNDRV_HDSPM_IOCTL_GET_LTC: 6044 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6045 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6046 if (i & HDSPM_TCO1_LTC_Input_valid) { 6047 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6048 HDSPM_TCO1_LTC_Format_MSB)) { 6049 case 0: 6050 ltc.format = fps_24; 6051 break; 6052 case HDSPM_TCO1_LTC_Format_LSB: 6053 ltc.format = fps_25; 6054 break; 6055 case HDSPM_TCO1_LTC_Format_MSB: 6056 ltc.format = fps_2997; 6057 break; 6058 default: 6059 ltc.format = 30; 6060 break; 6061 } 6062 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6063 ltc.frame = drop_frame; 6064 } else { 6065 ltc.frame = full_frame; 6066 } 6067 } else { 6068 ltc.format = format_invalid; 6069 ltc.frame = frame_invalid; 6070 } 6071 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6072 ltc.input_format = ntsc; 6073 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6074 ltc.input_format = pal; 6075 } else { 6076 ltc.input_format = no_video; 6077 } 6078 6079 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 6080 if (0 != s) { 6081 /* 6082 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6083 return -EFAULT; 6084 } 6085 6086 break; 6087 6088 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6089 6090 memset(&info, 0, sizeof(info)); 6091 spin_lock_irq(&hdspm->lock); 6092 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6093 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6094 6095 info.system_sample_rate = hdspm->system_sample_rate; 6096 info.autosync_sample_rate = 6097 hdspm_external_sample_rate(hdspm); 6098 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6099 info.clock_source = hdspm_clock_source(hdspm); 6100 info.autosync_ref = hdspm_autosync_ref(hdspm); 6101 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6102 info.passthru = 0; 6103 spin_unlock_irq(&hdspm->lock); 6104 if (copy_to_user(argp, &info, sizeof(info))) 6105 return -EFAULT; 6106 break; 6107 6108 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6109 memset(&status, 0, sizeof(status)); 6110 6111 status.card_type = hdspm->io_type; 6112 6113 status.autosync_source = hdspm_autosync_ref(hdspm); 6114 6115 status.card_clock = 110069313433624ULL; 6116 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6117 6118 switch (hdspm->io_type) { 6119 case MADI: 6120 case MADIface: 6121 status.card_specific.madi.sync_wc = 6122 hdspm_wc_sync_check(hdspm); 6123 status.card_specific.madi.sync_madi = 6124 hdspm_madi_sync_check(hdspm); 6125 status.card_specific.madi.sync_tco = 6126 hdspm_tco_sync_check(hdspm); 6127 status.card_specific.madi.sync_in = 6128 hdspm_sync_in_sync_check(hdspm); 6129 6130 statusregister = 6131 hdspm_read(hdspm, HDSPM_statusRegister); 6132 status.card_specific.madi.madi_input = 6133 (statusregister & HDSPM_AB_int) ? 1 : 0; 6134 status.card_specific.madi.channel_format = 6135 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6136 /* TODO: Mac driver sets it when f_s>48kHz */ 6137 status.card_specific.madi.frame_format = 0; 6138 6139 default: 6140 break; 6141 } 6142 6143 if (copy_to_user(argp, &status, sizeof(status))) 6144 return -EFAULT; 6145 6146 6147 break; 6148 6149 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6150 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6151 6152 hdspm_version.card_type = hdspm->io_type; 6153 strncpy(hdspm_version.cardname, hdspm->card_name, 6154 sizeof(hdspm_version.cardname)); 6155 hdspm_version.serial = hdspm->serial; 6156 hdspm_version.firmware_rev = hdspm->firmware_rev; 6157 hdspm_version.addons = 0; 6158 if (hdspm->tco) 6159 hdspm_version.addons |= HDSPM_ADDON_TCO; 6160 6161 if (copy_to_user(argp, &hdspm_version, 6162 sizeof(hdspm_version))) 6163 return -EFAULT; 6164 break; 6165 6166 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6167 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6168 return -EFAULT; 6169 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6170 sizeof(struct hdspm_mixer))) 6171 return -EFAULT; 6172 break; 6173 6174 default: 6175 return -EINVAL; 6176 } 6177 return 0; 6178 } 6179 6180 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6181 .open = snd_hdspm_playback_open, 6182 .close = snd_hdspm_playback_release, 6183 .ioctl = snd_hdspm_ioctl, 6184 .hw_params = snd_hdspm_hw_params, 6185 .hw_free = snd_hdspm_hw_free, 6186 .prepare = snd_hdspm_prepare, 6187 .trigger = snd_hdspm_trigger, 6188 .pointer = snd_hdspm_hw_pointer, 6189 .page = snd_pcm_sgbuf_ops_page, 6190 }; 6191 6192 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6193 .open = snd_hdspm_capture_open, 6194 .close = snd_hdspm_capture_release, 6195 .ioctl = snd_hdspm_ioctl, 6196 .hw_params = snd_hdspm_hw_params, 6197 .hw_free = snd_hdspm_hw_free, 6198 .prepare = snd_hdspm_prepare, 6199 .trigger = snd_hdspm_trigger, 6200 .pointer = snd_hdspm_hw_pointer, 6201 .page = snd_pcm_sgbuf_ops_page, 6202 }; 6203 6204 static int snd_hdspm_create_hwdep(struct snd_card *card, 6205 struct hdspm *hdspm) 6206 { 6207 struct snd_hwdep *hw; 6208 int err; 6209 6210 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6211 if (err < 0) 6212 return err; 6213 6214 hdspm->hwdep = hw; 6215 hw->private_data = hdspm; 6216 strcpy(hw->name, "HDSPM hwdep interface"); 6217 6218 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6219 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6220 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6221 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6222 6223 return 0; 6224 } 6225 6226 6227 /*------------------------------------------------------------ 6228 memory interface 6229 ------------------------------------------------------------*/ 6230 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6231 { 6232 int err; 6233 struct snd_pcm *pcm; 6234 size_t wanted; 6235 6236 pcm = hdspm->pcm; 6237 6238 wanted = HDSPM_DMA_AREA_BYTES; 6239 6240 err = 6241 snd_pcm_lib_preallocate_pages_for_all(pcm, 6242 SNDRV_DMA_TYPE_DEV_SG, 6243 snd_dma_pci_data(hdspm->pci), 6244 wanted, 6245 wanted); 6246 if (err < 0) { 6247 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6248 6249 return err; 6250 } else 6251 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6252 6253 return 0; 6254 } 6255 6256 6257 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6258 struct snd_pcm_substream *substream, 6259 unsigned int reg, int channels) 6260 { 6261 int i; 6262 6263 /* continuous memory segment */ 6264 for (i = 0; i < (channels * 16); i++) 6265 hdspm_write(hdspm, reg + 4 * i, 6266 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6267 } 6268 6269 6270 /* ------------- ALSA Devices ---------------------------- */ 6271 static int snd_hdspm_create_pcm(struct snd_card *card, 6272 struct hdspm *hdspm) 6273 { 6274 struct snd_pcm *pcm; 6275 int err; 6276 6277 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6278 if (err < 0) 6279 return err; 6280 6281 hdspm->pcm = pcm; 6282 pcm->private_data = hdspm; 6283 strcpy(pcm->name, hdspm->card_name); 6284 6285 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6286 &snd_hdspm_playback_ops); 6287 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6288 &snd_hdspm_capture_ops); 6289 6290 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6291 6292 err = snd_hdspm_preallocate_memory(hdspm); 6293 if (err < 0) 6294 return err; 6295 6296 return 0; 6297 } 6298 6299 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6300 { 6301 int i; 6302 6303 for (i = 0; i < hdspm->midiPorts; i++) 6304 snd_hdspm_flush_midi_input(hdspm, i); 6305 } 6306 6307 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6308 struct hdspm *hdspm) 6309 { 6310 int err, i; 6311 6312 snd_printdd("Create card...\n"); 6313 err = snd_hdspm_create_pcm(card, hdspm); 6314 if (err < 0) 6315 return err; 6316 6317 i = 0; 6318 while (i < hdspm->midiPorts) { 6319 err = snd_hdspm_create_midi(card, hdspm, i); 6320 if (err < 0) { 6321 return err; 6322 } 6323 i++; 6324 } 6325 6326 err = snd_hdspm_create_controls(card, hdspm); 6327 if (err < 0) 6328 return err; 6329 6330 err = snd_hdspm_create_hwdep(card, hdspm); 6331 if (err < 0) 6332 return err; 6333 6334 snd_printdd("proc init...\n"); 6335 snd_hdspm_proc_init(hdspm); 6336 6337 hdspm->system_sample_rate = -1; 6338 hdspm->last_external_sample_rate = -1; 6339 hdspm->last_internal_sample_rate = -1; 6340 hdspm->playback_pid = -1; 6341 hdspm->capture_pid = -1; 6342 hdspm->capture_substream = NULL; 6343 hdspm->playback_substream = NULL; 6344 6345 snd_printdd("Set defaults...\n"); 6346 err = snd_hdspm_set_defaults(hdspm); 6347 if (err < 0) 6348 return err; 6349 6350 snd_printdd("Update mixer controls...\n"); 6351 hdspm_update_simple_mixer_controls(hdspm); 6352 6353 snd_printdd("Initializeing complete ???\n"); 6354 6355 err = snd_card_register(card); 6356 if (err < 0) { 6357 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6358 return err; 6359 } 6360 6361 snd_printdd("... yes now\n"); 6362 6363 return 0; 6364 } 6365 6366 static int snd_hdspm_create(struct snd_card *card, 6367 struct hdspm *hdspm) 6368 { 6369 6370 struct pci_dev *pci = hdspm->pci; 6371 int err; 6372 unsigned long io_extent; 6373 6374 hdspm->irq = -1; 6375 hdspm->card = card; 6376 6377 spin_lock_init(&hdspm->lock); 6378 6379 pci_read_config_word(hdspm->pci, 6380 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6381 6382 strcpy(card->mixername, "Xilinx FPGA"); 6383 strcpy(card->driver, "HDSPM"); 6384 6385 switch (hdspm->firmware_rev) { 6386 case HDSPM_RAYDAT_REV: 6387 hdspm->io_type = RayDAT; 6388 hdspm->card_name = "RME RayDAT"; 6389 hdspm->midiPorts = 2; 6390 break; 6391 case HDSPM_AIO_REV: 6392 hdspm->io_type = AIO; 6393 hdspm->card_name = "RME AIO"; 6394 hdspm->midiPorts = 1; 6395 break; 6396 case HDSPM_MADIFACE_REV: 6397 hdspm->io_type = MADIface; 6398 hdspm->card_name = "RME MADIface"; 6399 hdspm->midiPorts = 1; 6400 break; 6401 default: 6402 if ((hdspm->firmware_rev == 0xf0) || 6403 ((hdspm->firmware_rev >= 0xe6) && 6404 (hdspm->firmware_rev <= 0xea))) { 6405 hdspm->io_type = AES32; 6406 hdspm->card_name = "RME AES32"; 6407 hdspm->midiPorts = 2; 6408 } else if ((hdspm->firmware_rev == 0xd2) || 6409 ((hdspm->firmware_rev >= 0xc8) && 6410 (hdspm->firmware_rev <= 0xcf))) { 6411 hdspm->io_type = MADI; 6412 hdspm->card_name = "RME MADI"; 6413 hdspm->midiPorts = 3; 6414 } else { 6415 snd_printk(KERN_ERR 6416 "HDSPM: unknown firmware revision %x\n", 6417 hdspm->firmware_rev); 6418 return -ENODEV; 6419 } 6420 } 6421 6422 err = pci_enable_device(pci); 6423 if (err < 0) 6424 return err; 6425 6426 pci_set_master(hdspm->pci); 6427 6428 err = pci_request_regions(pci, "hdspm"); 6429 if (err < 0) 6430 return err; 6431 6432 hdspm->port = pci_resource_start(pci, 0); 6433 io_extent = pci_resource_len(pci, 0); 6434 6435 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6436 hdspm->port, hdspm->port + io_extent - 1); 6437 6438 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6439 if (!hdspm->iobase) { 6440 snd_printk(KERN_ERR "HDSPM: " 6441 "unable to remap region 0x%lx-0x%lx\n", 6442 hdspm->port, hdspm->port + io_extent - 1); 6443 return -EBUSY; 6444 } 6445 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6446 (unsigned long)hdspm->iobase, hdspm->port, 6447 hdspm->port + io_extent - 1); 6448 6449 if (request_irq(pci->irq, snd_hdspm_interrupt, 6450 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6451 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6452 return -EBUSY; 6453 } 6454 6455 snd_printdd("use IRQ %d\n", pci->irq); 6456 6457 hdspm->irq = pci->irq; 6458 6459 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6460 sizeof(struct hdspm_mixer)); 6461 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6462 if (!hdspm->mixer) { 6463 snd_printk(KERN_ERR "HDSPM: " 6464 "unable to kmalloc Mixer memory of %d Bytes\n", 6465 (int)sizeof(struct hdspm_mixer)); 6466 return -ENOMEM; 6467 } 6468 6469 hdspm->port_names_in = NULL; 6470 hdspm->port_names_out = NULL; 6471 6472 switch (hdspm->io_type) { 6473 case AES32: 6474 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6475 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6476 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6477 6478 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6479 channel_map_aes32; 6480 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6481 channel_map_aes32; 6482 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6483 channel_map_aes32; 6484 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6485 texts_ports_aes32; 6486 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6487 texts_ports_aes32; 6488 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6489 texts_ports_aes32; 6490 6491 hdspm->max_channels_out = hdspm->max_channels_in = 6492 AES32_CHANNELS; 6493 hdspm->port_names_in = hdspm->port_names_out = 6494 texts_ports_aes32; 6495 hdspm->channel_map_in = hdspm->channel_map_out = 6496 channel_map_aes32; 6497 6498 break; 6499 6500 case MADI: 6501 case MADIface: 6502 hdspm->ss_in_channels = hdspm->ss_out_channels = 6503 MADI_SS_CHANNELS; 6504 hdspm->ds_in_channels = hdspm->ds_out_channels = 6505 MADI_DS_CHANNELS; 6506 hdspm->qs_in_channels = hdspm->qs_out_channels = 6507 MADI_QS_CHANNELS; 6508 6509 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6510 channel_map_unity_ss; 6511 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6512 channel_map_unity_ss; 6513 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6514 channel_map_unity_ss; 6515 6516 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6517 texts_ports_madi; 6518 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6519 texts_ports_madi; 6520 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6521 texts_ports_madi; 6522 break; 6523 6524 case AIO: 6525 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6526 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6527 } 6528 6529 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6530 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6531 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6532 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6533 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6534 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6535 6536 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6537 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6538 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6539 6540 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6541 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6542 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6543 6544 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6545 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6546 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6547 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6548 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6549 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6550 6551 break; 6552 6553 case RayDAT: 6554 hdspm->ss_in_channels = hdspm->ss_out_channels = 6555 RAYDAT_SS_CHANNELS; 6556 hdspm->ds_in_channels = hdspm->ds_out_channels = 6557 RAYDAT_DS_CHANNELS; 6558 hdspm->qs_in_channels = hdspm->qs_out_channels = 6559 RAYDAT_QS_CHANNELS; 6560 6561 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6562 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6563 6564 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6565 channel_map_raydat_ss; 6566 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6567 channel_map_raydat_ds; 6568 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6569 channel_map_raydat_qs; 6570 hdspm->channel_map_in = hdspm->channel_map_out = 6571 channel_map_raydat_ss; 6572 6573 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6574 texts_ports_raydat_ss; 6575 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6576 texts_ports_raydat_ds; 6577 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6578 texts_ports_raydat_qs; 6579 6580 6581 break; 6582 6583 } 6584 6585 /* TCO detection */ 6586 switch (hdspm->io_type) { 6587 case AIO: 6588 case RayDAT: 6589 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6590 HDSPM_s2_tco_detect) { 6591 hdspm->midiPorts++; 6592 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6593 GFP_KERNEL); 6594 if (NULL != hdspm->tco) { 6595 hdspm_tco_write(hdspm); 6596 } 6597 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6598 } else { 6599 hdspm->tco = NULL; 6600 } 6601 break; 6602 6603 case MADI: 6604 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6605 hdspm->midiPorts++; 6606 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6607 GFP_KERNEL); 6608 if (NULL != hdspm->tco) { 6609 hdspm_tco_write(hdspm); 6610 } 6611 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6612 } else { 6613 hdspm->tco = NULL; 6614 } 6615 break; 6616 6617 default: 6618 hdspm->tco = NULL; 6619 } 6620 6621 /* texts */ 6622 switch (hdspm->io_type) { 6623 case AES32: 6624 if (hdspm->tco) { 6625 hdspm->texts_autosync = texts_autosync_aes_tco; 6626 hdspm->texts_autosync_items = 10; 6627 } else { 6628 hdspm->texts_autosync = texts_autosync_aes; 6629 hdspm->texts_autosync_items = 9; 6630 } 6631 break; 6632 6633 case MADI: 6634 if (hdspm->tco) { 6635 hdspm->texts_autosync = texts_autosync_madi_tco; 6636 hdspm->texts_autosync_items = 4; 6637 } else { 6638 hdspm->texts_autosync = texts_autosync_madi; 6639 hdspm->texts_autosync_items = 3; 6640 } 6641 break; 6642 6643 case MADIface: 6644 6645 break; 6646 6647 case RayDAT: 6648 if (hdspm->tco) { 6649 hdspm->texts_autosync = texts_autosync_raydat_tco; 6650 hdspm->texts_autosync_items = 9; 6651 } else { 6652 hdspm->texts_autosync = texts_autosync_raydat; 6653 hdspm->texts_autosync_items = 8; 6654 } 6655 break; 6656 6657 case AIO: 6658 if (hdspm->tco) { 6659 hdspm->texts_autosync = texts_autosync_aio_tco; 6660 hdspm->texts_autosync_items = 6; 6661 } else { 6662 hdspm->texts_autosync = texts_autosync_aio; 6663 hdspm->texts_autosync_items = 5; 6664 } 6665 break; 6666 6667 } 6668 6669 tasklet_init(&hdspm->midi_tasklet, 6670 hdspm_midi_tasklet, (unsigned long) hdspm); 6671 6672 6673 if (hdspm->io_type != MADIface) { 6674 hdspm->serial = (hdspm_read(hdspm, 6675 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6676 /* id contains either a user-provided value or the default 6677 * NULL. If it's the default, we're safe to 6678 * fill card->id with the serial number. 6679 * 6680 * If the serial number is 0xFFFFFF, then we're dealing with 6681 * an old PCI revision that comes without a sane number. In 6682 * this case, we don't set card->id to avoid collisions 6683 * when running with multiple cards. 6684 */ 6685 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6686 sprintf(card->id, "HDSPMx%06x", hdspm->serial); 6687 snd_card_set_id(card, card->id); 6688 } 6689 } 6690 6691 snd_printdd("create alsa devices.\n"); 6692 err = snd_hdspm_create_alsa_devices(card, hdspm); 6693 if (err < 0) 6694 return err; 6695 6696 snd_hdspm_initialize_midi_flush(hdspm); 6697 6698 return 0; 6699 } 6700 6701 6702 static int snd_hdspm_free(struct hdspm * hdspm) 6703 { 6704 6705 if (hdspm->port) { 6706 6707 /* stop th audio, and cancel all interrupts */ 6708 hdspm->control_register &= 6709 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6710 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6711 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6712 hdspm_write(hdspm, HDSPM_controlRegister, 6713 hdspm->control_register); 6714 } 6715 6716 if (hdspm->irq >= 0) 6717 free_irq(hdspm->irq, (void *) hdspm); 6718 6719 kfree(hdspm->mixer); 6720 6721 if (hdspm->iobase) 6722 iounmap(hdspm->iobase); 6723 6724 if (hdspm->port) 6725 pci_release_regions(hdspm->pci); 6726 6727 pci_disable_device(hdspm->pci); 6728 return 0; 6729 } 6730 6731 6732 static void snd_hdspm_card_free(struct snd_card *card) 6733 { 6734 struct hdspm *hdspm = card->private_data; 6735 6736 if (hdspm) 6737 snd_hdspm_free(hdspm); 6738 } 6739 6740 6741 static int snd_hdspm_probe(struct pci_dev *pci, 6742 const struct pci_device_id *pci_id) 6743 { 6744 static int dev; 6745 struct hdspm *hdspm; 6746 struct snd_card *card; 6747 int err; 6748 6749 if (dev >= SNDRV_CARDS) 6750 return -ENODEV; 6751 if (!enable[dev]) { 6752 dev++; 6753 return -ENOENT; 6754 } 6755 6756 err = snd_card_create(index[dev], id[dev], 6757 THIS_MODULE, sizeof(struct hdspm), &card); 6758 if (err < 0) 6759 return err; 6760 6761 hdspm = card->private_data; 6762 card->private_free = snd_hdspm_card_free; 6763 hdspm->dev = dev; 6764 hdspm->pci = pci; 6765 6766 snd_card_set_dev(card, &pci->dev); 6767 6768 err = snd_hdspm_create(card, hdspm); 6769 if (err < 0) { 6770 snd_card_free(card); 6771 return err; 6772 } 6773 6774 if (hdspm->io_type != MADIface) { 6775 sprintf(card->shortname, "%s_%x", 6776 hdspm->card_name, 6777 hdspm->serial); 6778 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6779 hdspm->card_name, 6780 hdspm->serial, 6781 hdspm->port, hdspm->irq); 6782 } else { 6783 sprintf(card->shortname, "%s", hdspm->card_name); 6784 sprintf(card->longname, "%s at 0x%lx, irq %d", 6785 hdspm->card_name, hdspm->port, hdspm->irq); 6786 } 6787 6788 err = snd_card_register(card); 6789 if (err < 0) { 6790 snd_card_free(card); 6791 return err; 6792 } 6793 6794 pci_set_drvdata(pci, card); 6795 6796 dev++; 6797 return 0; 6798 } 6799 6800 static void snd_hdspm_remove(struct pci_dev *pci) 6801 { 6802 snd_card_free(pci_get_drvdata(pci)); 6803 } 6804 6805 static struct pci_driver hdspm_driver = { 6806 .name = KBUILD_MODNAME, 6807 .id_table = snd_hdspm_ids, 6808 .probe = snd_hdspm_probe, 6809 .remove = snd_hdspm_remove, 6810 }; 6811 6812 module_pci_driver(hdspm_driver); 6813