1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 #include <linux/init.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/module.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/math64.h> 48 #include <asm/io.h> 49 50 #include <sound/core.h> 51 #include <sound/control.h> 52 #include <sound/pcm.h> 53 #include <sound/pcm_params.h> 54 #include <sound/info.h> 55 #include <sound/asoundef.h> 56 #include <sound/rawmidi.h> 57 #include <sound/hwdep.h> 58 #include <sound/initval.h> 59 60 #include <sound/hdspm.h> 61 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 68 69 module_param_array(id, charp, NULL, 0444); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 71 72 module_param_array(enable, bool, NULL, 0444); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 74 75 76 MODULE_AUTHOR 77 ( 78 "Winfried Ritsch <ritsch_AT_iem.at>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, " 82 "Florian Faber <faberman@linuxproaudio.org>, " 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 84 ); 85 MODULE_DESCRIPTION("RME HDSPM"); 86 MODULE_LICENSE("GPL"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 88 89 /* --- Write registers. --- 90 These are defined as byte-offsets from the iobase value. */ 91 92 #define HDSPM_WR_SETTINGS 0 93 #define HDSPM_outputBufferAddress 32 94 #define HDSPM_inputBufferAddress 36 95 #define HDSPM_controlRegister 64 96 #define HDSPM_interruptConfirmation 96 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 98 #define HDSPM_freqReg 256 /* for AES32 */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 100 #define HDSPM_midiDataOut1 356 101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 102 103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 106 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 109 #define HDSPM_pageAddressBufferOut 8192 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 111 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 113 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 115 116 /* --- Read registers. --- 117 These are defined as byte-offsets from the iobase value */ 118 #define HDSPM_statusRegister 0 119 /*#define HDSPM_statusRegister2 96 */ 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 121 * offset 192, for AES32 *and* MADI 122 * => need to check that offset 192 is working on MADI */ 123 #define HDSPM_statusRegister2 192 124 #define HDSPM_timecodeRegister 128 125 126 /* AIO, RayDAT */ 127 #define HDSPM_RD_STATUS_0 0 128 #define HDSPM_RD_STATUS_1 64 129 #define HDSPM_RD_STATUS_2 128 130 #define HDSPM_RD_STATUS_3 192 131 132 #define HDSPM_RD_TCO 256 133 #define HDSPM_RD_PLL_FREQ 512 134 #define HDSPM_WR_TCO 128 135 136 #define HDSPM_TCO1_TCO_lock 0x00000001 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 143 144 #define HDSPM_TCO1_set_TC 0x00000100 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 148 149 #define HDSPM_TCO2_TC_run 0x00010000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000 155 #define HDSPM_TCO2_set_flywheel 0x00400000 156 157 #define HDSPM_TCO2_set_01_4 0x01000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000 160 #define HDSPM_TCO2_set_freq 0x08000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 165 166 167 #define HDSPM_midiDataOut0 352 168 #define HDSPM_midiDataOut1 356 169 #define HDSPM_midiDataOut2 368 170 171 #define HDSPM_midiDataIn0 360 172 #define HDSPM_midiDataIn1 364 173 #define HDSPM_midiDataIn2 372 174 #define HDSPM_midiDataIn3 376 175 176 /* status is data bytes in MIDI-FIFO (0-128) */ 177 #define HDSPM_midiStatusOut0 384 178 #define HDSPM_midiStatusOut1 388 179 #define HDSPM_midiStatusOut2 400 180 181 #define HDSPM_midiStatusIn0 392 182 #define HDSPM_midiStatusIn1 396 183 #define HDSPM_midiStatusIn2 404 184 #define HDSPM_midiStatusIn3 408 185 186 187 /* the meters are regular i/o-mapped registers, but offset 188 considerably from the rest. the peak registers are reset 189 when read; the least-significant 4 bits are full-scale counters; 190 the actual peak value is in the most-significant 24 bits. 191 */ 192 193 #define HDSPM_MADI_INPUT_PEAK 4096 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 195 #define HDSPM_MADI_OUTPUT_PEAK 4608 196 197 #define HDSPM_MADI_INPUT_RMS_L 6144 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 200 201 #define HDSPM_MADI_INPUT_RMS_H 7168 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 204 205 /* --- Control Register bits --------- */ 206 #define HDSPM_Start (1<<0) /* start engine */ 207 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 211 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 214 register [RayDAT, AIO] */ 215 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 217 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 222 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 225 56channelMODE=0 */ /* MADI ONLY*/ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 227 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 229 0=off, 1=on */ /* MADI ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 231 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 233 * -- MADI ONLY 234 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 236 237 #define HDSPM_SyncRef2 (1<<13) 238 #define HDSPM_SyncRef3 (1<<25) 239 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 242 AES additional bits in 243 lower 5 Audiodatabits ??? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 246 247 #define HDSPM_Midi0InterruptEnable 0x0400000 248 #define HDSPM_Midi1InterruptEnable 0x0800000 249 #define HDSPM_Midi2InterruptEnable 0x0200000 250 #define HDSPM_Midi3InterruptEnable 0x4000000 251 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 253 #define HDSPe_FLOAT_FORMAT 0x2000000 254 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 258 259 #define HDSPM_wclk_sel (1<<30) 260 261 /* additional control register bits for AIO*/ 262 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 263 #define HDSPM_c0_Input0 0x1000 264 #define HDSPM_c0_Input1 0x2000 265 #define HDSPM_c0_Spdif_Opt 0x4000 266 #define HDSPM_c0_Pro 0x8000 267 #define HDSPM_c0_clr_tms 0x10000 268 #define HDSPM_c0_AEB1 0x20000 269 #define HDSPM_c0_AEB2 0x40000 270 #define HDSPM_c0_LineOut 0x80000 271 #define HDSPM_c0_AD_GAIN0 0x100000 272 #define HDSPM_c0_AD_GAIN1 0x200000 273 #define HDSPM_c0_DA_GAIN0 0x400000 274 #define HDSPM_c0_DA_GAIN1 0x800000 275 #define HDSPM_c0_PH_GAIN0 0x1000000 276 #define HDSPM_c0_PH_GAIN1 0x2000000 277 #define HDSPM_c0_Sym6db 0x4000000 278 279 280 /* --- bit helper defines */ 281 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 282 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 283 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 284 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 285 #define HDSPM_InputOptical 0 286 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 287 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 288 HDSPM_SyncRef2|HDSPM_SyncRef3) 289 290 #define HDSPM_c0_SyncRef0 0x2 291 #define HDSPM_c0_SyncRef1 0x4 292 #define HDSPM_c0_SyncRef2 0x8 293 #define HDSPM_c0_SyncRef3 0x10 294 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 295 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 296 297 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 298 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 299 #define HDSPM_SYNC_FROM_TCO 2 300 #define HDSPM_SYNC_FROM_SYNC_IN 3 301 302 #define HDSPM_Frequency32KHz HDSPM_Frequency0 303 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 304 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 305 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 306 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 307 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 308 HDSPM_Frequency0) 309 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 310 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 311 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 312 HDSPM_Frequency0) 313 314 315 /* Synccheck Status */ 316 #define HDSPM_SYNC_CHECK_NO_LOCK 0 317 #define HDSPM_SYNC_CHECK_LOCK 1 318 #define HDSPM_SYNC_CHECK_SYNC 2 319 320 /* AutoSync References - used by "autosync_ref" control switch */ 321 #define HDSPM_AUTOSYNC_FROM_WORD 0 322 #define HDSPM_AUTOSYNC_FROM_MADI 1 323 #define HDSPM_AUTOSYNC_FROM_TCO 2 324 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 325 #define HDSPM_AUTOSYNC_FROM_NONE 4 326 327 /* Possible sources of MADI input */ 328 #define HDSPM_OPTICAL 0 /* optical */ 329 #define HDSPM_COAXIAL 1 /* BNC */ 330 331 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 332 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 333 334 #define hdspm_encode_in(x) (((x)&0x3)<<14) 335 #define hdspm_decode_in(x) (((x)>>14)&0x3) 336 337 /* --- control2 register bits --- */ 338 #define HDSPM_TMS (1<<0) 339 #define HDSPM_TCK (1<<1) 340 #define HDSPM_TDI (1<<2) 341 #define HDSPM_JTAG (1<<3) 342 #define HDSPM_PWDN (1<<4) 343 #define HDSPM_PROGRAM (1<<5) 344 #define HDSPM_CONFIG_MODE_0 (1<<6) 345 #define HDSPM_CONFIG_MODE_1 (1<<7) 346 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 347 #define HDSPM_BIGENDIAN_MODE (1<<9) 348 #define HDSPM_RD_MULTIPLE (1<<10) 349 350 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 351 that do not conflict with specific bits for AES32 seem to be valid also 352 for the AES32 353 */ 354 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 355 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 356 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 357 * (like inp0) 358 */ 359 360 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 361 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 362 363 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 364 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 365 366 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 367 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 368 369 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 370 /* since 64byte accurate, last 6 bits are not used */ 371 372 373 374 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 375 376 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 377 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 378 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 379 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 380 381 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 382 * Interrupt 383 */ 384 #define HDSPM_tco_detect 0x08000000 385 #define HDSPM_tco_lock 0x20000000 386 387 #define HDSPM_s2_tco_detect 0x00000040 388 #define HDSPM_s2_AEBO_D 0x00000080 389 #define HDSPM_s2_AEBI_D 0x00000100 390 391 392 #define HDSPM_midi0IRQPending 0x40000000 393 #define HDSPM_midi1IRQPending 0x80000000 394 #define HDSPM_midi2IRQPending 0x20000000 395 #define HDSPM_midi2IRQPendingAES 0x00000020 396 #define HDSPM_midi3IRQPending 0x00200000 397 398 /* --- status bit helpers */ 399 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 400 HDSPM_madiFreq2|HDSPM_madiFreq3) 401 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 402 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 403 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 404 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 405 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 406 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 407 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 408 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 409 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 410 411 /* Status2 Register bits */ /* MADI ONLY */ 412 413 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 414 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 415 #define HDSPM_version2 (1<<2) 416 417 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 418 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 419 420 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 421 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 422 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 423 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 424 425 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 426 #define HDSPM_SyncRef1 0x20000 427 428 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 429 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 430 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 431 432 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 433 434 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 435 HDSPM_wc_freq3) 436 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 437 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 438 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 439 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 440 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 441 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 442 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 443 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 444 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 445 446 #define HDSPM_status1_F_0 0x0400000 447 #define HDSPM_status1_F_1 0x0800000 448 #define HDSPM_status1_F_2 0x1000000 449 #define HDSPM_status1_F_3 0x2000000 450 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 451 452 453 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 454 HDSPM_SelSyncRef2) 455 #define HDSPM_SelSyncRef_WORD 0 456 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 457 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 458 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 459 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 460 HDSPM_SelSyncRef2) 461 462 /* 463 For AES32, bits for status, status2 and timecode are different 464 */ 465 /* status */ 466 #define HDSPM_AES32_wcLock 0x0200000 467 #define HDSPM_AES32_wcSync 0x0100000 468 #define HDSPM_AES32_wcFreq_bit 22 469 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 470 HDSPM_bit2freq */ 471 #define HDSPM_AES32_syncref_bit 16 472 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 473 474 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 475 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 476 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 477 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 478 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 479 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 480 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 481 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 482 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 483 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 484 485 /* status2 */ 486 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 487 #define HDSPM_LockAES 0x80 488 #define HDSPM_LockAES1 0x80 489 #define HDSPM_LockAES2 0x40 490 #define HDSPM_LockAES3 0x20 491 #define HDSPM_LockAES4 0x10 492 #define HDSPM_LockAES5 0x8 493 #define HDSPM_LockAES6 0x4 494 #define HDSPM_LockAES7 0x2 495 #define HDSPM_LockAES8 0x1 496 /* 497 Timecode 498 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 499 AES i+1 500 bits 3210 501 0001 32kHz 502 0010 44.1kHz 503 0011 48kHz 504 0100 64kHz 505 0101 88.2kHz 506 0110 96kHz 507 0111 128kHz 508 1000 176.4kHz 509 1001 192kHz 510 NB: Timecode register doesn't seem to work on AES32 card revision 230 511 */ 512 513 /* Mixer Values */ 514 #define UNITY_GAIN 32768 /* = 65536/2 */ 515 #define MINUS_INFINITY_GAIN 0 516 517 /* Number of channels for different Speed Modes */ 518 #define MADI_SS_CHANNELS 64 519 #define MADI_DS_CHANNELS 32 520 #define MADI_QS_CHANNELS 16 521 522 #define RAYDAT_SS_CHANNELS 36 523 #define RAYDAT_DS_CHANNELS 20 524 #define RAYDAT_QS_CHANNELS 12 525 526 #define AIO_IN_SS_CHANNELS 14 527 #define AIO_IN_DS_CHANNELS 10 528 #define AIO_IN_QS_CHANNELS 8 529 #define AIO_OUT_SS_CHANNELS 16 530 #define AIO_OUT_DS_CHANNELS 12 531 #define AIO_OUT_QS_CHANNELS 10 532 533 #define AES32_CHANNELS 16 534 535 /* the size of a substream (1 mono data stream) */ 536 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 537 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 538 539 /* the size of the area we need to allocate for DMA transfers. the 540 size is the same regardless of the number of channels, and 541 also the latency to use. 542 for one direction !!! 543 */ 544 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 545 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 546 547 #define HDSPM_RAYDAT_REV 211 548 #define HDSPM_AIO_REV 212 549 #define HDSPM_MADIFACE_REV 213 550 551 /* speed factor modes */ 552 #define HDSPM_SPEED_SINGLE 0 553 #define HDSPM_SPEED_DOUBLE 1 554 #define HDSPM_SPEED_QUAD 2 555 556 /* names for speed modes */ 557 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 558 559 static char *texts_autosync_aes_tco[] = { "Word Clock", 560 "AES1", "AES2", "AES3", "AES4", 561 "AES5", "AES6", "AES7", "AES8", 562 "TCO" }; 563 static char *texts_autosync_aes[] = { "Word Clock", 564 "AES1", "AES2", "AES3", "AES4", 565 "AES5", "AES6", "AES7", "AES8" }; 566 static char *texts_autosync_madi_tco[] = { "Word Clock", 567 "MADI", "TCO", "Sync In" }; 568 static char *texts_autosync_madi[] = { "Word Clock", 569 "MADI", "Sync In" }; 570 571 static char *texts_autosync_raydat_tco[] = { 572 "Word Clock", 573 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 574 "AES", "SPDIF", "TCO", "Sync In" 575 }; 576 static char *texts_autosync_raydat[] = { 577 "Word Clock", 578 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 579 "AES", "SPDIF", "Sync In" 580 }; 581 static char *texts_autosync_aio_tco[] = { 582 "Word Clock", 583 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 584 }; 585 static char *texts_autosync_aio[] = { "Word Clock", 586 "ADAT", "AES", "SPDIF", "Sync In" }; 587 588 static char *texts_freq[] = { 589 "No Lock", 590 "32 kHz", 591 "44.1 kHz", 592 "48 kHz", 593 "64 kHz", 594 "88.2 kHz", 595 "96 kHz", 596 "128 kHz", 597 "176.4 kHz", 598 "192 kHz" 599 }; 600 601 static char *texts_ports_madi[] = { 602 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 603 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 604 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 605 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 606 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 607 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 608 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 609 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 610 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 611 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 612 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 613 }; 614 615 616 static char *texts_ports_raydat_ss[] = { 617 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 618 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 619 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 620 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 621 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 622 "ADAT4.7", "ADAT4.8", 623 "AES.L", "AES.R", 624 "SPDIF.L", "SPDIF.R" 625 }; 626 627 static char *texts_ports_raydat_ds[] = { 628 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 629 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 630 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 631 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 632 "AES.L", "AES.R", 633 "SPDIF.L", "SPDIF.R" 634 }; 635 636 static char *texts_ports_raydat_qs[] = { 637 "ADAT1.1", "ADAT1.2", 638 "ADAT2.1", "ADAT2.2", 639 "ADAT3.1", "ADAT3.2", 640 "ADAT4.1", "ADAT4.2", 641 "AES.L", "AES.R", 642 "SPDIF.L", "SPDIF.R" 643 }; 644 645 646 static char *texts_ports_aio_in_ss[] = { 647 "Analogue.L", "Analogue.R", 648 "AES.L", "AES.R", 649 "SPDIF.L", "SPDIF.R", 650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 651 "ADAT.7", "ADAT.8" 652 }; 653 654 static char *texts_ports_aio_out_ss[] = { 655 "Analogue.L", "Analogue.R", 656 "AES.L", "AES.R", 657 "SPDIF.L", "SPDIF.R", 658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 659 "ADAT.7", "ADAT.8", 660 "Phone.L", "Phone.R" 661 }; 662 663 static char *texts_ports_aio_in_ds[] = { 664 "Analogue.L", "Analogue.R", 665 "AES.L", "AES.R", 666 "SPDIF.L", "SPDIF.R", 667 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 668 }; 669 670 static char *texts_ports_aio_out_ds[] = { 671 "Analogue.L", "Analogue.R", 672 "AES.L", "AES.R", 673 "SPDIF.L", "SPDIF.R", 674 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 675 "Phone.L", "Phone.R" 676 }; 677 678 static char *texts_ports_aio_in_qs[] = { 679 "Analogue.L", "Analogue.R", 680 "AES.L", "AES.R", 681 "SPDIF.L", "SPDIF.R", 682 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 683 }; 684 685 static char *texts_ports_aio_out_qs[] = { 686 "Analogue.L", "Analogue.R", 687 "AES.L", "AES.R", 688 "SPDIF.L", "SPDIF.R", 689 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 690 "Phone.L", "Phone.R" 691 }; 692 693 static char *texts_ports_aes32[] = { 694 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 695 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 696 "AES.15", "AES.16" 697 }; 698 699 /* These tables map the ALSA channels 1..N to the channels that we 700 need to use in order to find the relevant channel buffer. RME 701 refers to this kind of mapping as between "the ADAT channel and 702 the DMA channel." We index it using the logical audio channel, 703 and the value is the DMA channel (i.e. channel buffer number) 704 where the data for that channel can be read/written from/to. 705 */ 706 707 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 708 0, 1, 2, 3, 4, 5, 6, 7, 709 8, 9, 10, 11, 12, 13, 14, 15, 710 16, 17, 18, 19, 20, 21, 22, 23, 711 24, 25, 26, 27, 28, 29, 30, 31, 712 32, 33, 34, 35, 36, 37, 38, 39, 713 40, 41, 42, 43, 44, 45, 46, 47, 714 48, 49, 50, 51, 52, 53, 54, 55, 715 56, 57, 58, 59, 60, 61, 62, 63 716 }; 717 718 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 719 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 720 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 721 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 722 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 723 0, 1, /* AES */ 724 2, 3, /* SPDIF */ 725 -1, -1, -1, -1, 726 -1, -1, -1, -1, -1, -1, -1, -1, 727 -1, -1, -1, -1, -1, -1, -1, -1, 728 -1, -1, -1, -1, -1, -1, -1, -1, 729 }; 730 731 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 732 4, 5, 6, 7, /* ADAT 1 */ 733 8, 9, 10, 11, /* ADAT 2 */ 734 12, 13, 14, 15, /* ADAT 3 */ 735 16, 17, 18, 19, /* ADAT 4 */ 736 0, 1, /* AES */ 737 2, 3, /* SPDIF */ 738 -1, -1, -1, -1, 739 -1, -1, -1, -1, -1, -1, -1, -1, 740 -1, -1, -1, -1, -1, -1, -1, -1, 741 -1, -1, -1, -1, -1, -1, -1, -1, 742 -1, -1, -1, -1, -1, -1, -1, -1, 743 -1, -1, -1, -1, -1, -1, -1, -1, 744 }; 745 746 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 747 4, 5, /* ADAT 1 */ 748 6, 7, /* ADAT 2 */ 749 8, 9, /* ADAT 3 */ 750 10, 11, /* ADAT 4 */ 751 0, 1, /* AES */ 752 2, 3, /* SPDIF */ 753 -1, -1, -1, -1, 754 -1, -1, -1, -1, -1, -1, -1, -1, 755 -1, -1, -1, -1, -1, -1, -1, -1, 756 -1, -1, -1, -1, -1, -1, -1, -1, 757 -1, -1, -1, -1, -1, -1, -1, -1, 758 -1, -1, -1, -1, -1, -1, -1, -1, 759 -1, -1, -1, -1, -1, -1, -1, -1, 760 }; 761 762 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 763 0, 1, /* line in */ 764 8, 9, /* aes in, */ 765 10, 11, /* spdif in */ 766 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 767 -1, -1, 768 -1, -1, -1, -1, -1, -1, -1, -1, 769 -1, -1, -1, -1, -1, -1, -1, -1, 770 -1, -1, -1, -1, -1, -1, -1, -1, 771 -1, -1, -1, -1, -1, -1, -1, -1, 772 -1, -1, -1, -1, -1, -1, -1, -1, 773 -1, -1, -1, -1, -1, -1, -1, -1, 774 }; 775 776 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 777 0, 1, /* line out */ 778 8, 9, /* aes out */ 779 10, 11, /* spdif out */ 780 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 781 6, 7, /* phone out */ 782 -1, -1, -1, -1, -1, -1, -1, -1, 783 -1, -1, -1, -1, -1, -1, -1, -1, 784 -1, -1, -1, -1, -1, -1, -1, -1, 785 -1, -1, -1, -1, -1, -1, -1, -1, 786 -1, -1, -1, -1, -1, -1, -1, -1, 787 -1, -1, -1, -1, -1, -1, -1, -1, 788 }; 789 790 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 791 0, 1, /* line in */ 792 8, 9, /* aes in */ 793 10, 11, /* spdif in */ 794 12, 14, 16, 18, /* adat in */ 795 -1, -1, -1, -1, -1, -1, 796 -1, -1, -1, -1, -1, -1, -1, -1, 797 -1, -1, -1, -1, -1, -1, -1, -1, 798 -1, -1, -1, -1, -1, -1, -1, -1, 799 -1, -1, -1, -1, -1, -1, -1, -1, 800 -1, -1, -1, -1, -1, -1, -1, -1, 801 -1, -1, -1, -1, -1, -1, -1, -1 802 }; 803 804 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 805 0, 1, /* line out */ 806 8, 9, /* aes out */ 807 10, 11, /* spdif out */ 808 12, 14, 16, 18, /* adat out */ 809 6, 7, /* phone out */ 810 -1, -1, -1, -1, 811 -1, -1, -1, -1, -1, -1, -1, -1, 812 -1, -1, -1, -1, -1, -1, -1, -1, 813 -1, -1, -1, -1, -1, -1, -1, -1, 814 -1, -1, -1, -1, -1, -1, -1, -1, 815 -1, -1, -1, -1, -1, -1, -1, -1, 816 -1, -1, -1, -1, -1, -1, -1, -1 817 }; 818 819 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 820 0, 1, /* line in */ 821 8, 9, /* aes in */ 822 10, 11, /* spdif in */ 823 12, 16, /* adat in */ 824 -1, -1, -1, -1, -1, -1, -1, -1, 825 -1, -1, -1, -1, -1, -1, -1, -1, 826 -1, -1, -1, -1, -1, -1, -1, -1, 827 -1, -1, -1, -1, -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1 831 }; 832 833 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 834 0, 1, /* line out */ 835 8, 9, /* aes out */ 836 10, 11, /* spdif out */ 837 12, 16, /* adat out */ 838 6, 7, /* phone out */ 839 -1, -1, -1, -1, -1, -1, 840 -1, -1, -1, -1, -1, -1, -1, -1, 841 -1, -1, -1, -1, -1, -1, -1, -1, 842 -1, -1, -1, -1, -1, -1, -1, -1, 843 -1, -1, -1, -1, -1, -1, -1, -1, 844 -1, -1, -1, -1, -1, -1, -1, -1, 845 -1, -1, -1, -1, -1, -1, -1, -1 846 }; 847 848 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 849 0, 1, 2, 3, 4, 5, 6, 7, 850 8, 9, 10, 11, 12, 13, 14, 15, 851 -1, -1, -1, -1, -1, -1, -1, -1, 852 -1, -1, -1, -1, -1, -1, -1, -1, 853 -1, -1, -1, -1, -1, -1, -1, -1, 854 -1, -1, -1, -1, -1, -1, -1, -1, 855 -1, -1, -1, -1, -1, -1, -1, -1, 856 -1, -1, -1, -1, -1, -1, -1, -1 857 }; 858 859 struct hdspm_midi { 860 struct hdspm *hdspm; 861 int id; 862 struct snd_rawmidi *rmidi; 863 struct snd_rawmidi_substream *input; 864 struct snd_rawmidi_substream *output; 865 char istimer; /* timer in use */ 866 struct timer_list timer; 867 spinlock_t lock; 868 int pending; 869 int dataIn; 870 int statusIn; 871 int dataOut; 872 int statusOut; 873 int ie; 874 int irq; 875 }; 876 877 struct hdspm_tco { 878 int input; 879 int framerate; 880 int wordclock; 881 int samplerate; 882 int pull; 883 int term; /* 0 = off, 1 = on */ 884 }; 885 886 struct hdspm { 887 spinlock_t lock; 888 /* only one playback and/or capture stream */ 889 struct snd_pcm_substream *capture_substream; 890 struct snd_pcm_substream *playback_substream; 891 892 char *card_name; /* for procinfo */ 893 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 894 895 uint8_t io_type; 896 897 int monitor_outs; /* set up monitoring outs init flag */ 898 899 u32 control_register; /* cached value */ 900 u32 control2_register; /* cached value */ 901 u32 settings_register; 902 903 struct hdspm_midi midi[4]; 904 struct tasklet_struct midi_tasklet; 905 906 size_t period_bytes; 907 unsigned char ss_in_channels; 908 unsigned char ds_in_channels; 909 unsigned char qs_in_channels; 910 unsigned char ss_out_channels; 911 unsigned char ds_out_channels; 912 unsigned char qs_out_channels; 913 914 unsigned char max_channels_in; 915 unsigned char max_channels_out; 916 917 signed char *channel_map_in; 918 signed char *channel_map_out; 919 920 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 921 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 922 923 char **port_names_in; 924 char **port_names_out; 925 926 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 927 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 928 929 unsigned char *playback_buffer; /* suitably aligned address */ 930 unsigned char *capture_buffer; /* suitably aligned address */ 931 932 pid_t capture_pid; /* process id which uses capture */ 933 pid_t playback_pid; /* process id which uses capture */ 934 int running; /* running status */ 935 936 int last_external_sample_rate; /* samplerate mystic ... */ 937 int last_internal_sample_rate; 938 int system_sample_rate; 939 940 int dev; /* Hardware vars... */ 941 int irq; 942 unsigned long port; 943 void __iomem *iobase; 944 945 int irq_count; /* for debug */ 946 int midiPorts; 947 948 struct snd_card *card; /* one card */ 949 struct snd_pcm *pcm; /* has one pcm */ 950 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 951 struct pci_dev *pci; /* and an pci info */ 952 953 /* Mixer vars */ 954 /* fast alsa mixer */ 955 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 956 /* but input to much, so not used */ 957 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 958 /* full mixer accessible over mixer ioctl or hwdep-device */ 959 struct hdspm_mixer *mixer; 960 961 struct hdspm_tco *tco; /* NULL if no TCO detected */ 962 963 char **texts_autosync; 964 int texts_autosync_items; 965 966 cycles_t last_interrupt; 967 968 unsigned int serial; 969 970 struct hdspm_peak_rms peak_rms; 971 }; 972 973 974 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 975 { 976 .vendor = PCI_VENDOR_ID_XILINX, 977 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 978 .subvendor = PCI_ANY_ID, 979 .subdevice = PCI_ANY_ID, 980 .class = 0, 981 .class_mask = 0, 982 .driver_data = 0}, 983 {0,} 984 }; 985 986 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 987 988 /* prototypes */ 989 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 990 struct hdspm *hdspm); 991 static int snd_hdspm_create_pcm(struct snd_card *card, 992 struct hdspm *hdspm); 993 994 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 995 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 996 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 997 static int hdspm_autosync_ref(struct hdspm *hdspm); 998 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 999 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1000 static void hdspm_set_sgbuf(struct hdspm *hdspm, 1001 struct snd_pcm_substream *substream, 1002 unsigned int reg, int channels); 1003 1004 static inline int HDSPM_bit2freq(int n) 1005 { 1006 static const int bit2freq_tab[] = { 1007 0, 32000, 44100, 48000, 64000, 88200, 1008 96000, 128000, 176400, 192000 }; 1009 if (n < 1 || n > 9) 1010 return 0; 1011 return bit2freq_tab[n]; 1012 } 1013 1014 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1015 { 1016 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1017 } 1018 1019 1020 /* Write/read to/from HDSPM with Adresses in Bytes 1021 not words but only 32Bit writes are allowed */ 1022 1023 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1024 unsigned int val) 1025 { 1026 writel(val, hdspm->iobase + reg); 1027 } 1028 1029 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1030 { 1031 return readl(hdspm->iobase + reg); 1032 } 1033 1034 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1035 mixer is write only on hardware so we have to cache him for read 1036 each fader is a u32, but uses only the first 16 bit */ 1037 1038 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1039 unsigned int in) 1040 { 1041 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1042 return 0; 1043 1044 return hdspm->mixer->ch[chan].in[in]; 1045 } 1046 1047 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1048 unsigned int pb) 1049 { 1050 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1051 return 0; 1052 return hdspm->mixer->ch[chan].pb[pb]; 1053 } 1054 1055 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1056 unsigned int in, unsigned short data) 1057 { 1058 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1059 return -1; 1060 1061 hdspm_write(hdspm, 1062 HDSPM_MADI_mixerBase + 1063 ((in + 128 * chan) * sizeof(u32)), 1064 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1065 return 0; 1066 } 1067 1068 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1069 unsigned int pb, unsigned short data) 1070 { 1071 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1072 return -1; 1073 1074 hdspm_write(hdspm, 1075 HDSPM_MADI_mixerBase + 1076 ((64 + pb + 128 * chan) * sizeof(u32)), 1077 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1078 return 0; 1079 } 1080 1081 1082 /* enable DMA for specific channels, now available for DSP-MADI */ 1083 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1084 { 1085 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1086 } 1087 1088 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1089 { 1090 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1091 } 1092 1093 /* check if same process is writing and reading */ 1094 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1095 { 1096 unsigned long flags; 1097 int ret = 1; 1098 1099 spin_lock_irqsave(&hdspm->lock, flags); 1100 if ((hdspm->playback_pid != hdspm->capture_pid) && 1101 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1102 ret = 0; 1103 } 1104 spin_unlock_irqrestore(&hdspm->lock, flags); 1105 return ret; 1106 } 1107 1108 /* round arbitary sample rates to commonly known rates */ 1109 static int hdspm_round_frequency(int rate) 1110 { 1111 if (rate < 38050) 1112 return 32000; 1113 if (rate < 46008) 1114 return 44100; 1115 else 1116 return 48000; 1117 } 1118 1119 /* QS and DS rates normally can not be detected 1120 * automatically by the card. Only exception is MADI 1121 * in 96k frame mode. 1122 * 1123 * So if we read SS values (32 .. 48k), check for 1124 * user-provided DS/QS bits in the control register 1125 * and multiply the base frequency accordingly. 1126 */ 1127 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1128 { 1129 if (rate <= 48000) { 1130 if (hdspm->control_register & HDSPM_QuadSpeed) 1131 return rate * 4; 1132 else if (hdspm->control_register & 1133 HDSPM_DoubleSpeed) 1134 return rate * 2; 1135 }; 1136 return rate; 1137 } 1138 1139 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1140 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1141 1142 /* check for external sample rate */ 1143 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1144 { 1145 unsigned int status, status2, timecode; 1146 int syncref, rate = 0, rate_bits; 1147 1148 switch (hdspm->io_type) { 1149 case AES32: 1150 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1151 status = hdspm_read(hdspm, HDSPM_statusRegister); 1152 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1153 1154 syncref = hdspm_autosync_ref(hdspm); 1155 1156 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1157 status & HDSPM_AES32_wcLock) 1158 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1159 1160 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1161 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1162 status2 & (HDSPM_LockAES >> 1163 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1164 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1165 return 0; 1166 break; 1167 1168 case MADIface: 1169 status = hdspm_read(hdspm, HDSPM_statusRegister); 1170 1171 if (!(status & HDSPM_madiLock)) { 1172 rate = 0; /* no lock */ 1173 } else { 1174 switch (status & (HDSPM_status1_freqMask)) { 1175 case HDSPM_status1_F_0*1: 1176 rate = 32000; break; 1177 case HDSPM_status1_F_0*2: 1178 rate = 44100; break; 1179 case HDSPM_status1_F_0*3: 1180 rate = 48000; break; 1181 case HDSPM_status1_F_0*4: 1182 rate = 64000; break; 1183 case HDSPM_status1_F_0*5: 1184 rate = 88200; break; 1185 case HDSPM_status1_F_0*6: 1186 rate = 96000; break; 1187 case HDSPM_status1_F_0*7: 1188 rate = 128000; break; 1189 case HDSPM_status1_F_0*8: 1190 rate = 176400; break; 1191 case HDSPM_status1_F_0*9: 1192 rate = 192000; break; 1193 default: 1194 rate = 0; break; 1195 } 1196 } 1197 1198 break; 1199 1200 case MADI: 1201 case AIO: 1202 case RayDAT: 1203 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1204 status = hdspm_read(hdspm, HDSPM_statusRegister); 1205 rate = 0; 1206 1207 /* if wordclock has synced freq and wordclock is valid */ 1208 if ((status2 & HDSPM_wcLock) != 0 && 1209 (status2 & HDSPM_SelSyncRef0) == 0) { 1210 1211 rate_bits = status2 & HDSPM_wcFreqMask; 1212 1213 1214 switch (rate_bits) { 1215 case HDSPM_wcFreq32: 1216 rate = 32000; 1217 break; 1218 case HDSPM_wcFreq44_1: 1219 rate = 44100; 1220 break; 1221 case HDSPM_wcFreq48: 1222 rate = 48000; 1223 break; 1224 case HDSPM_wcFreq64: 1225 rate = 64000; 1226 break; 1227 case HDSPM_wcFreq88_2: 1228 rate = 88200; 1229 break; 1230 case HDSPM_wcFreq96: 1231 rate = 96000; 1232 break; 1233 case HDSPM_wcFreq128: 1234 rate = 128000; 1235 break; 1236 case HDSPM_wcFreq176_4: 1237 rate = 176400; 1238 break; 1239 case HDSPM_wcFreq192: 1240 rate = 192000; 1241 break; 1242 default: 1243 rate = 0; 1244 break; 1245 } 1246 } 1247 1248 /* if rate detected and Syncref is Word than have it, 1249 * word has priority to MADI 1250 */ 1251 if (rate != 0 && 1252 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1253 return hdspm_rate_multiplier(hdspm, rate); 1254 1255 /* maybe a madi input (which is taken if sel sync is madi) */ 1256 if (status & HDSPM_madiLock) { 1257 rate_bits = status & HDSPM_madiFreqMask; 1258 1259 switch (rate_bits) { 1260 case HDSPM_madiFreq32: 1261 rate = 32000; 1262 break; 1263 case HDSPM_madiFreq44_1: 1264 rate = 44100; 1265 break; 1266 case HDSPM_madiFreq48: 1267 rate = 48000; 1268 break; 1269 case HDSPM_madiFreq64: 1270 rate = 64000; 1271 break; 1272 case HDSPM_madiFreq88_2: 1273 rate = 88200; 1274 break; 1275 case HDSPM_madiFreq96: 1276 rate = 96000; 1277 break; 1278 case HDSPM_madiFreq128: 1279 rate = 128000; 1280 break; 1281 case HDSPM_madiFreq176_4: 1282 rate = 176400; 1283 break; 1284 case HDSPM_madiFreq192: 1285 rate = 192000; 1286 break; 1287 default: 1288 rate = 0; 1289 break; 1290 } 1291 1292 } /* endif HDSPM_madiLock */ 1293 1294 /* check sample rate from TCO or SYNC_IN */ 1295 { 1296 bool is_valid_input = 0; 1297 bool has_sync = 0; 1298 1299 syncref = hdspm_autosync_ref(hdspm); 1300 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1301 is_valid_input = 1; 1302 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1303 hdspm_tco_sync_check(hdspm)); 1304 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1305 is_valid_input = 1; 1306 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1307 hdspm_sync_in_sync_check(hdspm)); 1308 } 1309 1310 if (is_valid_input && has_sync) { 1311 rate = hdspm_round_frequency( 1312 hdspm_get_pll_freq(hdspm)); 1313 } 1314 } 1315 1316 rate = hdspm_rate_multiplier(hdspm, rate); 1317 1318 break; 1319 } 1320 1321 return rate; 1322 } 1323 1324 /* return latency in samples per period */ 1325 static int hdspm_get_latency(struct hdspm *hdspm) 1326 { 1327 int n; 1328 1329 n = hdspm_decode_latency(hdspm->control_register); 1330 1331 /* Special case for new RME cards with 32 samples period size. 1332 * The three latency bits in the control register 1333 * (HDSP_LatencyMask) encode latency values of 64 samples as 1334 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1335 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1336 * it corresponds to 32 samples. 1337 */ 1338 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1339 n = -1; 1340 1341 return 1 << (n + 6); 1342 } 1343 1344 /* Latency function */ 1345 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1346 { 1347 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1348 } 1349 1350 1351 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1352 { 1353 int position; 1354 1355 position = hdspm_read(hdspm, HDSPM_statusRegister); 1356 1357 switch (hdspm->io_type) { 1358 case RayDAT: 1359 case AIO: 1360 position &= HDSPM_BufferPositionMask; 1361 position /= 4; /* Bytes per sample */ 1362 break; 1363 default: 1364 position = (position & HDSPM_BufferID) ? 1365 (hdspm->period_bytes / 4) : 0; 1366 } 1367 1368 return position; 1369 } 1370 1371 1372 static inline void hdspm_start_audio(struct hdspm * s) 1373 { 1374 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1375 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1376 } 1377 1378 static inline void hdspm_stop_audio(struct hdspm * s) 1379 { 1380 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1381 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1382 } 1383 1384 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1385 static void hdspm_silence_playback(struct hdspm *hdspm) 1386 { 1387 int i; 1388 int n = hdspm->period_bytes; 1389 void *buf = hdspm->playback_buffer; 1390 1391 if (buf == NULL) 1392 return; 1393 1394 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1395 memset(buf, 0, n); 1396 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1397 } 1398 } 1399 1400 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1401 { 1402 int n; 1403 1404 spin_lock_irq(&s->lock); 1405 1406 if (32 == frames) { 1407 /* Special case for new RME cards like RayDAT/AIO which 1408 * support period sizes of 32 samples. Since latency is 1409 * encoded in the three bits of HDSP_LatencyMask, we can only 1410 * have values from 0 .. 7. While 0 still means 64 samples and 1411 * 6 represents 4096 samples on all cards, 7 represents 8192 1412 * on older cards and 32 samples on new cards. 1413 * 1414 * In other words, period size in samples is calculated by 1415 * 2^(n+6) with n ranging from 0 .. 7. 1416 */ 1417 n = 7; 1418 } else { 1419 frames >>= 7; 1420 n = 0; 1421 while (frames) { 1422 n++; 1423 frames >>= 1; 1424 } 1425 } 1426 1427 s->control_register &= ~HDSPM_LatencyMask; 1428 s->control_register |= hdspm_encode_latency(n); 1429 1430 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1431 1432 hdspm_compute_period_size(s); 1433 1434 spin_unlock_irq(&s->lock); 1435 1436 return 0; 1437 } 1438 1439 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1440 { 1441 u64 freq_const; 1442 1443 if (period == 0) 1444 return 0; 1445 1446 switch (hdspm->io_type) { 1447 case MADI: 1448 case AES32: 1449 freq_const = 110069313433624ULL; 1450 break; 1451 case RayDAT: 1452 case AIO: 1453 freq_const = 104857600000000ULL; 1454 break; 1455 case MADIface: 1456 freq_const = 131072000000000ULL; 1457 break; 1458 default: 1459 snd_BUG(); 1460 return 0; 1461 } 1462 1463 return div_u64(freq_const, period); 1464 } 1465 1466 1467 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1468 { 1469 u64 n; 1470 1471 if (rate >= 112000) 1472 rate /= 4; 1473 else if (rate >= 56000) 1474 rate /= 2; 1475 1476 switch (hdspm->io_type) { 1477 case MADIface: 1478 n = 131072000000000ULL; /* 125 MHz */ 1479 break; 1480 case MADI: 1481 case AES32: 1482 n = 110069313433624ULL; /* 105 MHz */ 1483 break; 1484 case RayDAT: 1485 case AIO: 1486 n = 104857600000000ULL; /* 100 MHz */ 1487 break; 1488 default: 1489 snd_BUG(); 1490 return; 1491 } 1492 1493 n = div_u64(n, rate); 1494 /* n should be less than 2^32 for being written to FREQ register */ 1495 snd_BUG_ON(n >> 32); 1496 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1497 } 1498 1499 /* dummy set rate lets see what happens */ 1500 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1501 { 1502 int current_rate; 1503 int rate_bits; 1504 int not_set = 0; 1505 int current_speed, target_speed; 1506 1507 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1508 it (e.g. during module initialization). 1509 */ 1510 1511 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1512 1513 /* SLAVE --- */ 1514 if (called_internally) { 1515 1516 /* request from ctl or card initialization 1517 just make a warning an remember setting 1518 for future master mode switching */ 1519 1520 snd_printk(KERN_WARNING "HDSPM: " 1521 "Warning: device is not running " 1522 "as a clock master.\n"); 1523 not_set = 1; 1524 } else { 1525 1526 /* hw_param request while in AutoSync mode */ 1527 int external_freq = 1528 hdspm_external_sample_rate(hdspm); 1529 1530 if (hdspm_autosync_ref(hdspm) == 1531 HDSPM_AUTOSYNC_FROM_NONE) { 1532 1533 snd_printk(KERN_WARNING "HDSPM: " 1534 "Detected no Externel Sync \n"); 1535 not_set = 1; 1536 1537 } else if (rate != external_freq) { 1538 1539 snd_printk(KERN_WARNING "HDSPM: " 1540 "Warning: No AutoSync source for " 1541 "requested rate\n"); 1542 not_set = 1; 1543 } 1544 } 1545 } 1546 1547 current_rate = hdspm->system_sample_rate; 1548 1549 /* Changing between Singe, Double and Quad speed is not 1550 allowed if any substreams are open. This is because such a change 1551 causes a shift in the location of the DMA buffers and a reduction 1552 in the number of available buffers. 1553 1554 Note that a similar but essentially insoluble problem exists for 1555 externally-driven rate changes. All we can do is to flag rate 1556 changes in the read/write routines. 1557 */ 1558 1559 if (current_rate <= 48000) 1560 current_speed = HDSPM_SPEED_SINGLE; 1561 else if (current_rate <= 96000) 1562 current_speed = HDSPM_SPEED_DOUBLE; 1563 else 1564 current_speed = HDSPM_SPEED_QUAD; 1565 1566 if (rate <= 48000) 1567 target_speed = HDSPM_SPEED_SINGLE; 1568 else if (rate <= 96000) 1569 target_speed = HDSPM_SPEED_DOUBLE; 1570 else 1571 target_speed = HDSPM_SPEED_QUAD; 1572 1573 switch (rate) { 1574 case 32000: 1575 rate_bits = HDSPM_Frequency32KHz; 1576 break; 1577 case 44100: 1578 rate_bits = HDSPM_Frequency44_1KHz; 1579 break; 1580 case 48000: 1581 rate_bits = HDSPM_Frequency48KHz; 1582 break; 1583 case 64000: 1584 rate_bits = HDSPM_Frequency64KHz; 1585 break; 1586 case 88200: 1587 rate_bits = HDSPM_Frequency88_2KHz; 1588 break; 1589 case 96000: 1590 rate_bits = HDSPM_Frequency96KHz; 1591 break; 1592 case 128000: 1593 rate_bits = HDSPM_Frequency128KHz; 1594 break; 1595 case 176400: 1596 rate_bits = HDSPM_Frequency176_4KHz; 1597 break; 1598 case 192000: 1599 rate_bits = HDSPM_Frequency192KHz; 1600 break; 1601 default: 1602 return -EINVAL; 1603 } 1604 1605 if (current_speed != target_speed 1606 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1607 snd_printk 1608 (KERN_ERR "HDSPM: " 1609 "cannot change from %s speed to %s speed mode " 1610 "(capture PID = %d, playback PID = %d)\n", 1611 hdspm_speed_names[current_speed], 1612 hdspm_speed_names[target_speed], 1613 hdspm->capture_pid, hdspm->playback_pid); 1614 return -EBUSY; 1615 } 1616 1617 hdspm->control_register &= ~HDSPM_FrequencyMask; 1618 hdspm->control_register |= rate_bits; 1619 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1620 1621 /* For AES32, need to set DDS value in FREQ register 1622 For MADI, also apparently */ 1623 hdspm_set_dds_value(hdspm, rate); 1624 1625 if (AES32 == hdspm->io_type && rate != current_rate) 1626 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1627 1628 hdspm->system_sample_rate = rate; 1629 1630 if (rate <= 48000) { 1631 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1632 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1633 hdspm->max_channels_in = hdspm->ss_in_channels; 1634 hdspm->max_channels_out = hdspm->ss_out_channels; 1635 hdspm->port_names_in = hdspm->port_names_in_ss; 1636 hdspm->port_names_out = hdspm->port_names_out_ss; 1637 } else if (rate <= 96000) { 1638 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1639 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1640 hdspm->max_channels_in = hdspm->ds_in_channels; 1641 hdspm->max_channels_out = hdspm->ds_out_channels; 1642 hdspm->port_names_in = hdspm->port_names_in_ds; 1643 hdspm->port_names_out = hdspm->port_names_out_ds; 1644 } else { 1645 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1646 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1647 hdspm->max_channels_in = hdspm->qs_in_channels; 1648 hdspm->max_channels_out = hdspm->qs_out_channels; 1649 hdspm->port_names_in = hdspm->port_names_in_qs; 1650 hdspm->port_names_out = hdspm->port_names_out_qs; 1651 } 1652 1653 if (not_set != 0) 1654 return -1; 1655 1656 return 0; 1657 } 1658 1659 /* mainly for init to 0 on load */ 1660 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1661 { 1662 int i, j; 1663 unsigned int gain; 1664 1665 if (sgain > UNITY_GAIN) 1666 gain = UNITY_GAIN; 1667 else if (sgain < 0) 1668 gain = 0; 1669 else 1670 gain = sgain; 1671 1672 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1673 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1674 hdspm_write_in_gain(hdspm, i, j, gain); 1675 hdspm_write_pb_gain(hdspm, i, j, gain); 1676 } 1677 } 1678 1679 /*---------------------------------------------------------------------------- 1680 MIDI 1681 ----------------------------------------------------------------------------*/ 1682 1683 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1684 int id) 1685 { 1686 /* the hardware already does the relevant bit-mask with 0xff */ 1687 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1688 } 1689 1690 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1691 int val) 1692 { 1693 /* the hardware already does the relevant bit-mask with 0xff */ 1694 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1695 } 1696 1697 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1698 { 1699 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1700 } 1701 1702 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1703 { 1704 int fifo_bytes_used; 1705 1706 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1707 1708 if (fifo_bytes_used < 128) 1709 return 128 - fifo_bytes_used; 1710 else 1711 return 0; 1712 } 1713 1714 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1715 { 1716 while (snd_hdspm_midi_input_available (hdspm, id)) 1717 snd_hdspm_midi_read_byte (hdspm, id); 1718 } 1719 1720 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1721 { 1722 unsigned long flags; 1723 int n_pending; 1724 int to_write; 1725 int i; 1726 unsigned char buf[128]; 1727 1728 /* Output is not interrupt driven */ 1729 1730 spin_lock_irqsave (&hmidi->lock, flags); 1731 if (hmidi->output && 1732 !snd_rawmidi_transmit_empty (hmidi->output)) { 1733 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1734 hmidi->id); 1735 if (n_pending > 0) { 1736 if (n_pending > (int)sizeof (buf)) 1737 n_pending = sizeof (buf); 1738 1739 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1740 n_pending); 1741 if (to_write > 0) { 1742 for (i = 0; i < to_write; ++i) 1743 snd_hdspm_midi_write_byte (hmidi->hdspm, 1744 hmidi->id, 1745 buf[i]); 1746 } 1747 } 1748 } 1749 spin_unlock_irqrestore (&hmidi->lock, flags); 1750 return 0; 1751 } 1752 1753 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1754 { 1755 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1756 * input FIFO size 1757 */ 1758 unsigned long flags; 1759 int n_pending; 1760 int i; 1761 1762 spin_lock_irqsave (&hmidi->lock, flags); 1763 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1764 if (n_pending > 0) { 1765 if (hmidi->input) { 1766 if (n_pending > (int)sizeof (buf)) 1767 n_pending = sizeof (buf); 1768 for (i = 0; i < n_pending; ++i) 1769 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1770 hmidi->id); 1771 if (n_pending) 1772 snd_rawmidi_receive (hmidi->input, buf, 1773 n_pending); 1774 } else { 1775 /* flush the MIDI input FIFO */ 1776 while (n_pending--) 1777 snd_hdspm_midi_read_byte (hmidi->hdspm, 1778 hmidi->id); 1779 } 1780 } 1781 hmidi->pending = 0; 1782 spin_unlock_irqrestore(&hmidi->lock, flags); 1783 1784 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1785 hmidi->hdspm->control_register |= hmidi->ie; 1786 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1787 hmidi->hdspm->control_register); 1788 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1789 1790 return snd_hdspm_midi_output_write (hmidi); 1791 } 1792 1793 static void 1794 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1795 { 1796 struct hdspm *hdspm; 1797 struct hdspm_midi *hmidi; 1798 unsigned long flags; 1799 1800 hmidi = substream->rmidi->private_data; 1801 hdspm = hmidi->hdspm; 1802 1803 spin_lock_irqsave (&hdspm->lock, flags); 1804 if (up) { 1805 if (!(hdspm->control_register & hmidi->ie)) { 1806 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1807 hdspm->control_register |= hmidi->ie; 1808 } 1809 } else { 1810 hdspm->control_register &= ~hmidi->ie; 1811 } 1812 1813 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1814 spin_unlock_irqrestore (&hdspm->lock, flags); 1815 } 1816 1817 static void snd_hdspm_midi_output_timer(unsigned long data) 1818 { 1819 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1820 unsigned long flags; 1821 1822 snd_hdspm_midi_output_write(hmidi); 1823 spin_lock_irqsave (&hmidi->lock, flags); 1824 1825 /* this does not bump hmidi->istimer, because the 1826 kernel automatically removed the timer when it 1827 expired, and we are now adding it back, thus 1828 leaving istimer wherever it was set before. 1829 */ 1830 1831 if (hmidi->istimer) { 1832 hmidi->timer.expires = 1 + jiffies; 1833 add_timer(&hmidi->timer); 1834 } 1835 1836 spin_unlock_irqrestore (&hmidi->lock, flags); 1837 } 1838 1839 static void 1840 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1841 { 1842 struct hdspm_midi *hmidi; 1843 unsigned long flags; 1844 1845 hmidi = substream->rmidi->private_data; 1846 spin_lock_irqsave (&hmidi->lock, flags); 1847 if (up) { 1848 if (!hmidi->istimer) { 1849 init_timer(&hmidi->timer); 1850 hmidi->timer.function = snd_hdspm_midi_output_timer; 1851 hmidi->timer.data = (unsigned long) hmidi; 1852 hmidi->timer.expires = 1 + jiffies; 1853 add_timer(&hmidi->timer); 1854 hmidi->istimer++; 1855 } 1856 } else { 1857 if (hmidi->istimer && --hmidi->istimer <= 0) 1858 del_timer (&hmidi->timer); 1859 } 1860 spin_unlock_irqrestore (&hmidi->lock, flags); 1861 if (up) 1862 snd_hdspm_midi_output_write(hmidi); 1863 } 1864 1865 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1866 { 1867 struct hdspm_midi *hmidi; 1868 1869 hmidi = substream->rmidi->private_data; 1870 spin_lock_irq (&hmidi->lock); 1871 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1872 hmidi->input = substream; 1873 spin_unlock_irq (&hmidi->lock); 1874 1875 return 0; 1876 } 1877 1878 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1879 { 1880 struct hdspm_midi *hmidi; 1881 1882 hmidi = substream->rmidi->private_data; 1883 spin_lock_irq (&hmidi->lock); 1884 hmidi->output = substream; 1885 spin_unlock_irq (&hmidi->lock); 1886 1887 return 0; 1888 } 1889 1890 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1891 { 1892 struct hdspm_midi *hmidi; 1893 1894 snd_hdspm_midi_input_trigger (substream, 0); 1895 1896 hmidi = substream->rmidi->private_data; 1897 spin_lock_irq (&hmidi->lock); 1898 hmidi->input = NULL; 1899 spin_unlock_irq (&hmidi->lock); 1900 1901 return 0; 1902 } 1903 1904 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1905 { 1906 struct hdspm_midi *hmidi; 1907 1908 snd_hdspm_midi_output_trigger (substream, 0); 1909 1910 hmidi = substream->rmidi->private_data; 1911 spin_lock_irq (&hmidi->lock); 1912 hmidi->output = NULL; 1913 spin_unlock_irq (&hmidi->lock); 1914 1915 return 0; 1916 } 1917 1918 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1919 { 1920 .open = snd_hdspm_midi_output_open, 1921 .close = snd_hdspm_midi_output_close, 1922 .trigger = snd_hdspm_midi_output_trigger, 1923 }; 1924 1925 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1926 { 1927 .open = snd_hdspm_midi_input_open, 1928 .close = snd_hdspm_midi_input_close, 1929 .trigger = snd_hdspm_midi_input_trigger, 1930 }; 1931 1932 static int snd_hdspm_create_midi(struct snd_card *card, 1933 struct hdspm *hdspm, int id) 1934 { 1935 int err; 1936 char buf[32]; 1937 1938 hdspm->midi[id].id = id; 1939 hdspm->midi[id].hdspm = hdspm; 1940 spin_lock_init (&hdspm->midi[id].lock); 1941 1942 if (0 == id) { 1943 if (MADIface == hdspm->io_type) { 1944 /* MIDI-over-MADI on HDSPe MADIface */ 1945 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1946 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1947 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1948 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1949 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1950 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1951 } else { 1952 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1953 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1954 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1955 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1956 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1957 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1958 } 1959 } else if (1 == id) { 1960 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1961 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1962 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1963 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1964 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1965 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1966 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1967 /* MIDI-over-MADI on HDSPe MADI */ 1968 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1969 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1970 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1971 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1972 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1973 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1974 } else if (2 == id) { 1975 /* TCO MTC, read only */ 1976 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1977 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1978 hdspm->midi[2].dataOut = -1; 1979 hdspm->midi[2].statusOut = -1; 1980 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1981 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1982 } else if (3 == id) { 1983 /* TCO MTC on HDSPe MADI */ 1984 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1985 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1986 hdspm->midi[3].dataOut = -1; 1987 hdspm->midi[3].statusOut = -1; 1988 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1989 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1990 } 1991 1992 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1993 (MADIface == hdspm->io_type)))) { 1994 if ((id == 0) && (MADIface == hdspm->io_type)) { 1995 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1996 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1997 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1998 } else { 1999 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 2000 } 2001 err = snd_rawmidi_new(card, buf, id, 1, 1, 2002 &hdspm->midi[id].rmidi); 2003 if (err < 0) 2004 return err; 2005 2006 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 2007 card->id, id+1); 2008 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2009 2010 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2011 SNDRV_RAWMIDI_STREAM_OUTPUT, 2012 &snd_hdspm_midi_output); 2013 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2014 SNDRV_RAWMIDI_STREAM_INPUT, 2015 &snd_hdspm_midi_input); 2016 2017 hdspm->midi[id].rmidi->info_flags |= 2018 SNDRV_RAWMIDI_INFO_OUTPUT | 2019 SNDRV_RAWMIDI_INFO_INPUT | 2020 SNDRV_RAWMIDI_INFO_DUPLEX; 2021 } else { 2022 /* TCO MTC, read only */ 2023 sprintf(buf, "%s MTC %d", card->shortname, id+1); 2024 err = snd_rawmidi_new(card, buf, id, 1, 1, 2025 &hdspm->midi[id].rmidi); 2026 if (err < 0) 2027 return err; 2028 2029 sprintf(hdspm->midi[id].rmidi->name, 2030 "%s MTC %d", card->id, id+1); 2031 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2032 2033 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2034 SNDRV_RAWMIDI_STREAM_INPUT, 2035 &snd_hdspm_midi_input); 2036 2037 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2038 } 2039 2040 return 0; 2041 } 2042 2043 2044 static void hdspm_midi_tasklet(unsigned long arg) 2045 { 2046 struct hdspm *hdspm = (struct hdspm *)arg; 2047 int i = 0; 2048 2049 while (i < hdspm->midiPorts) { 2050 if (hdspm->midi[i].pending) 2051 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2052 2053 i++; 2054 } 2055 } 2056 2057 2058 /*----------------------------------------------------------------------------- 2059 Status Interface 2060 ----------------------------------------------------------------------------*/ 2061 2062 /* get the system sample rate which is set */ 2063 2064 2065 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2066 { 2067 unsigned int period, rate; 2068 2069 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2070 rate = hdspm_calc_dds_value(hdspm, period); 2071 2072 return rate; 2073 } 2074 2075 /** 2076 * Calculate the real sample rate from the 2077 * current DDS value. 2078 **/ 2079 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2080 { 2081 unsigned int rate; 2082 2083 rate = hdspm_get_pll_freq(hdspm); 2084 2085 if (rate > 207000) { 2086 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2087 if (0 == hdspm_system_clock_mode(hdspm)) { 2088 /* master mode, return internal sample rate */ 2089 rate = hdspm->system_sample_rate; 2090 } else { 2091 /* slave mode, return external sample rate */ 2092 rate = hdspm_external_sample_rate(hdspm); 2093 } 2094 } 2095 2096 return rate; 2097 } 2098 2099 2100 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2101 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2102 .name = xname, \ 2103 .index = xindex, \ 2104 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2105 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2106 .info = snd_hdspm_info_system_sample_rate, \ 2107 .put = snd_hdspm_put_system_sample_rate, \ 2108 .get = snd_hdspm_get_system_sample_rate \ 2109 } 2110 2111 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2112 struct snd_ctl_elem_info *uinfo) 2113 { 2114 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2115 uinfo->count = 1; 2116 uinfo->value.integer.min = 27000; 2117 uinfo->value.integer.max = 207000; 2118 uinfo->value.integer.step = 1; 2119 return 0; 2120 } 2121 2122 2123 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2124 struct snd_ctl_elem_value * 2125 ucontrol) 2126 { 2127 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2128 2129 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2130 return 0; 2131 } 2132 2133 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2134 struct snd_ctl_elem_value * 2135 ucontrol) 2136 { 2137 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2138 2139 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]); 2140 return 0; 2141 } 2142 2143 2144 /** 2145 * Returns the WordClock sample rate class for the given card. 2146 **/ 2147 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2148 { 2149 int status; 2150 2151 switch (hdspm->io_type) { 2152 case RayDAT: 2153 case AIO: 2154 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2155 return (status >> 16) & 0xF; 2156 break; 2157 default: 2158 break; 2159 } 2160 2161 2162 return 0; 2163 } 2164 2165 2166 /** 2167 * Returns the TCO sample rate class for the given card. 2168 **/ 2169 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2170 { 2171 int status; 2172 2173 if (hdspm->tco) { 2174 switch (hdspm->io_type) { 2175 case RayDAT: 2176 case AIO: 2177 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2178 return (status >> 20) & 0xF; 2179 break; 2180 default: 2181 break; 2182 } 2183 } 2184 2185 return 0; 2186 } 2187 2188 2189 /** 2190 * Returns the SYNC_IN sample rate class for the given card. 2191 **/ 2192 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2193 { 2194 int status; 2195 2196 if (hdspm->tco) { 2197 switch (hdspm->io_type) { 2198 case RayDAT: 2199 case AIO: 2200 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2201 return (status >> 12) & 0xF; 2202 break; 2203 default: 2204 break; 2205 } 2206 } 2207 2208 return 0; 2209 } 2210 2211 2212 /** 2213 * Returns the sample rate class for input source <idx> for 2214 * 'new style' cards like the AIO and RayDAT. 2215 **/ 2216 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2217 { 2218 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2219 2220 return (status >> (idx*4)) & 0xF; 2221 } 2222 2223 #define ENUMERATED_CTL_INFO(info, texts) \ 2224 { \ 2225 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \ 2226 uinfo->count = 1; \ 2227 uinfo->value.enumerated.items = ARRAY_SIZE(texts); \ 2228 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \ 2229 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; \ 2230 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \ 2231 } 2232 2233 2234 2235 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2236 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2237 .name = xname, \ 2238 .private_value = xindex, \ 2239 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2240 .info = snd_hdspm_info_autosync_sample_rate, \ 2241 .get = snd_hdspm_get_autosync_sample_rate \ 2242 } 2243 2244 2245 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2246 struct snd_ctl_elem_info *uinfo) 2247 { 2248 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2249 return 0; 2250 } 2251 2252 2253 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2254 struct snd_ctl_elem_value * 2255 ucontrol) 2256 { 2257 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2258 2259 switch (hdspm->io_type) { 2260 case RayDAT: 2261 switch (kcontrol->private_value) { 2262 case 0: 2263 ucontrol->value.enumerated.item[0] = 2264 hdspm_get_wc_sample_rate(hdspm); 2265 break; 2266 case 7: 2267 ucontrol->value.enumerated.item[0] = 2268 hdspm_get_tco_sample_rate(hdspm); 2269 break; 2270 case 8: 2271 ucontrol->value.enumerated.item[0] = 2272 hdspm_get_sync_in_sample_rate(hdspm); 2273 break; 2274 default: 2275 ucontrol->value.enumerated.item[0] = 2276 hdspm_get_s1_sample_rate(hdspm, 2277 kcontrol->private_value-1); 2278 } 2279 break; 2280 2281 case AIO: 2282 switch (kcontrol->private_value) { 2283 case 0: /* WC */ 2284 ucontrol->value.enumerated.item[0] = 2285 hdspm_get_wc_sample_rate(hdspm); 2286 break; 2287 case 4: /* TCO */ 2288 ucontrol->value.enumerated.item[0] = 2289 hdspm_get_tco_sample_rate(hdspm); 2290 break; 2291 case 5: /* SYNC_IN */ 2292 ucontrol->value.enumerated.item[0] = 2293 hdspm_get_sync_in_sample_rate(hdspm); 2294 break; 2295 default: 2296 ucontrol->value.enumerated.item[0] = 2297 hdspm_get_s1_sample_rate(hdspm, 2298 ucontrol->id.index-1); 2299 } 2300 break; 2301 2302 case AES32: 2303 2304 switch (kcontrol->private_value) { 2305 case 0: /* WC */ 2306 ucontrol->value.enumerated.item[0] = 2307 hdspm_get_wc_sample_rate(hdspm); 2308 break; 2309 case 9: /* TCO */ 2310 ucontrol->value.enumerated.item[0] = 2311 hdspm_get_tco_sample_rate(hdspm); 2312 break; 2313 case 10: /* SYNC_IN */ 2314 ucontrol->value.enumerated.item[0] = 2315 hdspm_get_sync_in_sample_rate(hdspm); 2316 break; 2317 default: /* AES1 to AES8 */ 2318 ucontrol->value.enumerated.item[0] = 2319 hdspm_get_s1_sample_rate(hdspm, 2320 kcontrol->private_value-1); 2321 break; 2322 } 2323 break; 2324 2325 case MADI: 2326 case MADIface: 2327 { 2328 int rate = hdspm_external_sample_rate(hdspm); 2329 int i, selected_rate = 0; 2330 for (i = 1; i < 10; i++) 2331 if (HDSPM_bit2freq(i) == rate) { 2332 selected_rate = i; 2333 break; 2334 } 2335 ucontrol->value.enumerated.item[0] = selected_rate; 2336 } 2337 break; 2338 2339 default: 2340 break; 2341 } 2342 2343 return 0; 2344 } 2345 2346 2347 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2348 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2349 .name = xname, \ 2350 .index = xindex, \ 2351 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2352 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2353 .info = snd_hdspm_info_system_clock_mode, \ 2354 .get = snd_hdspm_get_system_clock_mode, \ 2355 .put = snd_hdspm_put_system_clock_mode, \ 2356 } 2357 2358 2359 /** 2360 * Returns the system clock mode for the given card. 2361 * @returns 0 - master, 1 - slave 2362 **/ 2363 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2364 { 2365 switch (hdspm->io_type) { 2366 case AIO: 2367 case RayDAT: 2368 if (hdspm->settings_register & HDSPM_c0Master) 2369 return 0; 2370 break; 2371 2372 default: 2373 if (hdspm->control_register & HDSPM_ClockModeMaster) 2374 return 0; 2375 } 2376 2377 return 1; 2378 } 2379 2380 2381 /** 2382 * Sets the system clock mode. 2383 * @param mode 0 - master, 1 - slave 2384 **/ 2385 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2386 { 2387 switch (hdspm->io_type) { 2388 case AIO: 2389 case RayDAT: 2390 if (0 == mode) 2391 hdspm->settings_register |= HDSPM_c0Master; 2392 else 2393 hdspm->settings_register &= ~HDSPM_c0Master; 2394 2395 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2396 break; 2397 2398 default: 2399 if (0 == mode) 2400 hdspm->control_register |= HDSPM_ClockModeMaster; 2401 else 2402 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2403 2404 hdspm_write(hdspm, HDSPM_controlRegister, 2405 hdspm->control_register); 2406 } 2407 } 2408 2409 2410 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2411 struct snd_ctl_elem_info *uinfo) 2412 { 2413 static char *texts[] = { "Master", "AutoSync" }; 2414 ENUMERATED_CTL_INFO(uinfo, texts); 2415 return 0; 2416 } 2417 2418 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2419 struct snd_ctl_elem_value *ucontrol) 2420 { 2421 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2422 2423 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2424 return 0; 2425 } 2426 2427 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2428 struct snd_ctl_elem_value *ucontrol) 2429 { 2430 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2431 int val; 2432 2433 if (!snd_hdspm_use_is_exclusive(hdspm)) 2434 return -EBUSY; 2435 2436 val = ucontrol->value.enumerated.item[0]; 2437 if (val < 0) 2438 val = 0; 2439 else if (val > 1) 2440 val = 1; 2441 2442 hdspm_set_system_clock_mode(hdspm, val); 2443 2444 return 0; 2445 } 2446 2447 2448 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2449 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2450 .name = xname, \ 2451 .index = xindex, \ 2452 .info = snd_hdspm_info_clock_source, \ 2453 .get = snd_hdspm_get_clock_source, \ 2454 .put = snd_hdspm_put_clock_source \ 2455 } 2456 2457 2458 static int hdspm_clock_source(struct hdspm * hdspm) 2459 { 2460 switch (hdspm->system_sample_rate) { 2461 case 32000: return 0; 2462 case 44100: return 1; 2463 case 48000: return 2; 2464 case 64000: return 3; 2465 case 88200: return 4; 2466 case 96000: return 5; 2467 case 128000: return 6; 2468 case 176400: return 7; 2469 case 192000: return 8; 2470 } 2471 2472 return -1; 2473 } 2474 2475 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2476 { 2477 int rate; 2478 switch (mode) { 2479 case 0: 2480 rate = 32000; break; 2481 case 1: 2482 rate = 44100; break; 2483 case 2: 2484 rate = 48000; break; 2485 case 3: 2486 rate = 64000; break; 2487 case 4: 2488 rate = 88200; break; 2489 case 5: 2490 rate = 96000; break; 2491 case 6: 2492 rate = 128000; break; 2493 case 7: 2494 rate = 176400; break; 2495 case 8: 2496 rate = 192000; break; 2497 default: 2498 rate = 48000; 2499 } 2500 hdspm_set_rate(hdspm, rate, 1); 2501 return 0; 2502 } 2503 2504 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2505 struct snd_ctl_elem_info *uinfo) 2506 { 2507 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2508 uinfo->count = 1; 2509 uinfo->value.enumerated.items = 9; 2510 2511 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2512 uinfo->value.enumerated.item = 2513 uinfo->value.enumerated.items - 1; 2514 2515 strcpy(uinfo->value.enumerated.name, 2516 texts_freq[uinfo->value.enumerated.item+1]); 2517 2518 return 0; 2519 } 2520 2521 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2522 struct snd_ctl_elem_value *ucontrol) 2523 { 2524 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2525 2526 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2527 return 0; 2528 } 2529 2530 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2531 struct snd_ctl_elem_value *ucontrol) 2532 { 2533 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2534 int change; 2535 int val; 2536 2537 if (!snd_hdspm_use_is_exclusive(hdspm)) 2538 return -EBUSY; 2539 val = ucontrol->value.enumerated.item[0]; 2540 if (val < 0) 2541 val = 0; 2542 if (val > 9) 2543 val = 9; 2544 spin_lock_irq(&hdspm->lock); 2545 if (val != hdspm_clock_source(hdspm)) 2546 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2547 else 2548 change = 0; 2549 spin_unlock_irq(&hdspm->lock); 2550 return change; 2551 } 2552 2553 2554 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2555 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2556 .name = xname, \ 2557 .index = xindex, \ 2558 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2559 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2560 .info = snd_hdspm_info_pref_sync_ref, \ 2561 .get = snd_hdspm_get_pref_sync_ref, \ 2562 .put = snd_hdspm_put_pref_sync_ref \ 2563 } 2564 2565 2566 /** 2567 * Returns the current preferred sync reference setting. 2568 * The semantics of the return value are depending on the 2569 * card, please see the comments for clarification. 2570 **/ 2571 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2572 { 2573 switch (hdspm->io_type) { 2574 case AES32: 2575 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2576 case 0: return 0; /* WC */ 2577 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2578 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2579 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2580 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2581 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2582 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2583 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2584 return 7; /* AES 7 */ 2585 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2586 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2587 } 2588 break; 2589 2590 case MADI: 2591 case MADIface: 2592 if (hdspm->tco) { 2593 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2594 case 0: return 0; /* WC */ 2595 case HDSPM_SyncRef0: return 1; /* MADI */ 2596 case HDSPM_SyncRef1: return 2; /* TCO */ 2597 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2598 return 3; /* SYNC_IN */ 2599 } 2600 } else { 2601 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2602 case 0: return 0; /* WC */ 2603 case HDSPM_SyncRef0: return 1; /* MADI */ 2604 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2605 return 2; /* SYNC_IN */ 2606 } 2607 } 2608 break; 2609 2610 case RayDAT: 2611 if (hdspm->tco) { 2612 switch ((hdspm->settings_register & 2613 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2614 case 0: return 0; /* WC */ 2615 case 3: return 1; /* ADAT 1 */ 2616 case 4: return 2; /* ADAT 2 */ 2617 case 5: return 3; /* ADAT 3 */ 2618 case 6: return 4; /* ADAT 4 */ 2619 case 1: return 5; /* AES */ 2620 case 2: return 6; /* SPDIF */ 2621 case 9: return 7; /* TCO */ 2622 case 10: return 8; /* SYNC_IN */ 2623 } 2624 } else { 2625 switch ((hdspm->settings_register & 2626 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2627 case 0: return 0; /* WC */ 2628 case 3: return 1; /* ADAT 1 */ 2629 case 4: return 2; /* ADAT 2 */ 2630 case 5: return 3; /* ADAT 3 */ 2631 case 6: return 4; /* ADAT 4 */ 2632 case 1: return 5; /* AES */ 2633 case 2: return 6; /* SPDIF */ 2634 case 10: return 7; /* SYNC_IN */ 2635 } 2636 } 2637 2638 break; 2639 2640 case AIO: 2641 if (hdspm->tco) { 2642 switch ((hdspm->settings_register & 2643 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2644 case 0: return 0; /* WC */ 2645 case 3: return 1; /* ADAT */ 2646 case 1: return 2; /* AES */ 2647 case 2: return 3; /* SPDIF */ 2648 case 9: return 4; /* TCO */ 2649 case 10: return 5; /* SYNC_IN */ 2650 } 2651 } else { 2652 switch ((hdspm->settings_register & 2653 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2654 case 0: return 0; /* WC */ 2655 case 3: return 1; /* ADAT */ 2656 case 1: return 2; /* AES */ 2657 case 2: return 3; /* SPDIF */ 2658 case 10: return 4; /* SYNC_IN */ 2659 } 2660 } 2661 2662 break; 2663 } 2664 2665 return -1; 2666 } 2667 2668 2669 /** 2670 * Set the preferred sync reference to <pref>. The semantics 2671 * of <pref> are depending on the card type, see the comments 2672 * for clarification. 2673 **/ 2674 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2675 { 2676 int p = 0; 2677 2678 switch (hdspm->io_type) { 2679 case AES32: 2680 hdspm->control_register &= ~HDSPM_SyncRefMask; 2681 switch (pref) { 2682 case 0: /* WC */ 2683 break; 2684 case 1: /* AES 1 */ 2685 hdspm->control_register |= HDSPM_SyncRef0; 2686 break; 2687 case 2: /* AES 2 */ 2688 hdspm->control_register |= HDSPM_SyncRef1; 2689 break; 2690 case 3: /* AES 3 */ 2691 hdspm->control_register |= 2692 HDSPM_SyncRef1+HDSPM_SyncRef0; 2693 break; 2694 case 4: /* AES 4 */ 2695 hdspm->control_register |= HDSPM_SyncRef2; 2696 break; 2697 case 5: /* AES 5 */ 2698 hdspm->control_register |= 2699 HDSPM_SyncRef2+HDSPM_SyncRef0; 2700 break; 2701 case 6: /* AES 6 */ 2702 hdspm->control_register |= 2703 HDSPM_SyncRef2+HDSPM_SyncRef1; 2704 break; 2705 case 7: /* AES 7 */ 2706 hdspm->control_register |= 2707 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2708 break; 2709 case 8: /* AES 8 */ 2710 hdspm->control_register |= HDSPM_SyncRef3; 2711 break; 2712 case 9: /* TCO */ 2713 hdspm->control_register |= 2714 HDSPM_SyncRef3+HDSPM_SyncRef0; 2715 break; 2716 default: 2717 return -1; 2718 } 2719 2720 break; 2721 2722 case MADI: 2723 case MADIface: 2724 hdspm->control_register &= ~HDSPM_SyncRefMask; 2725 if (hdspm->tco) { 2726 switch (pref) { 2727 case 0: /* WC */ 2728 break; 2729 case 1: /* MADI */ 2730 hdspm->control_register |= HDSPM_SyncRef0; 2731 break; 2732 case 2: /* TCO */ 2733 hdspm->control_register |= HDSPM_SyncRef1; 2734 break; 2735 case 3: /* SYNC_IN */ 2736 hdspm->control_register |= 2737 HDSPM_SyncRef0+HDSPM_SyncRef1; 2738 break; 2739 default: 2740 return -1; 2741 } 2742 } else { 2743 switch (pref) { 2744 case 0: /* WC */ 2745 break; 2746 case 1: /* MADI */ 2747 hdspm->control_register |= HDSPM_SyncRef0; 2748 break; 2749 case 2: /* SYNC_IN */ 2750 hdspm->control_register |= 2751 HDSPM_SyncRef0+HDSPM_SyncRef1; 2752 break; 2753 default: 2754 return -1; 2755 } 2756 } 2757 2758 break; 2759 2760 case RayDAT: 2761 if (hdspm->tco) { 2762 switch (pref) { 2763 case 0: p = 0; break; /* WC */ 2764 case 1: p = 3; break; /* ADAT 1 */ 2765 case 2: p = 4; break; /* ADAT 2 */ 2766 case 3: p = 5; break; /* ADAT 3 */ 2767 case 4: p = 6; break; /* ADAT 4 */ 2768 case 5: p = 1; break; /* AES */ 2769 case 6: p = 2; break; /* SPDIF */ 2770 case 7: p = 9; break; /* TCO */ 2771 case 8: p = 10; break; /* SYNC_IN */ 2772 default: return -1; 2773 } 2774 } else { 2775 switch (pref) { 2776 case 0: p = 0; break; /* WC */ 2777 case 1: p = 3; break; /* ADAT 1 */ 2778 case 2: p = 4; break; /* ADAT 2 */ 2779 case 3: p = 5; break; /* ADAT 3 */ 2780 case 4: p = 6; break; /* ADAT 4 */ 2781 case 5: p = 1; break; /* AES */ 2782 case 6: p = 2; break; /* SPDIF */ 2783 case 7: p = 10; break; /* SYNC_IN */ 2784 default: return -1; 2785 } 2786 } 2787 break; 2788 2789 case AIO: 2790 if (hdspm->tco) { 2791 switch (pref) { 2792 case 0: p = 0; break; /* WC */ 2793 case 1: p = 3; break; /* ADAT */ 2794 case 2: p = 1; break; /* AES */ 2795 case 3: p = 2; break; /* SPDIF */ 2796 case 4: p = 9; break; /* TCO */ 2797 case 5: p = 10; break; /* SYNC_IN */ 2798 default: return -1; 2799 } 2800 } else { 2801 switch (pref) { 2802 case 0: p = 0; break; /* WC */ 2803 case 1: p = 3; break; /* ADAT */ 2804 case 2: p = 1; break; /* AES */ 2805 case 3: p = 2; break; /* SPDIF */ 2806 case 4: p = 10; break; /* SYNC_IN */ 2807 default: return -1; 2808 } 2809 } 2810 break; 2811 } 2812 2813 switch (hdspm->io_type) { 2814 case RayDAT: 2815 case AIO: 2816 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2817 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2818 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2819 break; 2820 2821 case MADI: 2822 case MADIface: 2823 case AES32: 2824 hdspm_write(hdspm, HDSPM_controlRegister, 2825 hdspm->control_register); 2826 } 2827 2828 return 0; 2829 } 2830 2831 2832 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2833 struct snd_ctl_elem_info *uinfo) 2834 { 2835 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2836 2837 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2838 uinfo->count = 1; 2839 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2840 2841 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2842 uinfo->value.enumerated.item = 2843 uinfo->value.enumerated.items - 1; 2844 2845 strcpy(uinfo->value.enumerated.name, 2846 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2847 2848 return 0; 2849 } 2850 2851 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2852 struct snd_ctl_elem_value *ucontrol) 2853 { 2854 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2855 int psf = hdspm_pref_sync_ref(hdspm); 2856 2857 if (psf >= 0) { 2858 ucontrol->value.enumerated.item[0] = psf; 2859 return 0; 2860 } 2861 2862 return -1; 2863 } 2864 2865 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2866 struct snd_ctl_elem_value *ucontrol) 2867 { 2868 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2869 int val, change = 0; 2870 2871 if (!snd_hdspm_use_is_exclusive(hdspm)) 2872 return -EBUSY; 2873 2874 val = ucontrol->value.enumerated.item[0]; 2875 2876 if (val < 0) 2877 val = 0; 2878 else if (val >= hdspm->texts_autosync_items) 2879 val = hdspm->texts_autosync_items-1; 2880 2881 spin_lock_irq(&hdspm->lock); 2882 if (val != hdspm_pref_sync_ref(hdspm)) 2883 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2884 2885 spin_unlock_irq(&hdspm->lock); 2886 return change; 2887 } 2888 2889 2890 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2891 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2892 .name = xname, \ 2893 .index = xindex, \ 2894 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2895 .info = snd_hdspm_info_autosync_ref, \ 2896 .get = snd_hdspm_get_autosync_ref, \ 2897 } 2898 2899 static int hdspm_autosync_ref(struct hdspm *hdspm) 2900 { 2901 if (AES32 == hdspm->io_type) { 2902 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2903 unsigned int syncref = 2904 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2905 if (syncref == 0) 2906 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2907 if (syncref <= 8) 2908 return syncref; 2909 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2910 } else if (MADI == hdspm->io_type) { 2911 /* This looks at the autosync selected sync reference */ 2912 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2913 2914 switch (status2 & HDSPM_SelSyncRefMask) { 2915 case HDSPM_SelSyncRef_WORD: 2916 return HDSPM_AUTOSYNC_FROM_WORD; 2917 case HDSPM_SelSyncRef_MADI: 2918 return HDSPM_AUTOSYNC_FROM_MADI; 2919 case HDSPM_SelSyncRef_TCO: 2920 return HDSPM_AUTOSYNC_FROM_TCO; 2921 case HDSPM_SelSyncRef_SyncIn: 2922 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2923 case HDSPM_SelSyncRef_NVALID: 2924 return HDSPM_AUTOSYNC_FROM_NONE; 2925 default: 2926 return 0; 2927 } 2928 2929 } 2930 return 0; 2931 } 2932 2933 2934 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2935 struct snd_ctl_elem_info *uinfo) 2936 { 2937 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2938 2939 if (AES32 == hdspm->io_type) { 2940 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2941 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2942 2943 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2944 uinfo->count = 1; 2945 uinfo->value.enumerated.items = 10; 2946 if (uinfo->value.enumerated.item >= 2947 uinfo->value.enumerated.items) 2948 uinfo->value.enumerated.item = 2949 uinfo->value.enumerated.items - 1; 2950 strcpy(uinfo->value.enumerated.name, 2951 texts[uinfo->value.enumerated.item]); 2952 } else if (MADI == hdspm->io_type) { 2953 static char *texts[] = {"Word Clock", "MADI", "TCO", 2954 "Sync In", "None" }; 2955 2956 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2957 uinfo->count = 1; 2958 uinfo->value.enumerated.items = 5; 2959 if (uinfo->value.enumerated.item >= 2960 uinfo->value.enumerated.items) 2961 uinfo->value.enumerated.item = 2962 uinfo->value.enumerated.items - 1; 2963 strcpy(uinfo->value.enumerated.name, 2964 texts[uinfo->value.enumerated.item]); 2965 } 2966 return 0; 2967 } 2968 2969 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2970 struct snd_ctl_elem_value *ucontrol) 2971 { 2972 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2973 2974 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2975 return 0; 2976 } 2977 2978 2979 2980 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \ 2981 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2982 .name = xname, \ 2983 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 2984 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2985 .info = snd_hdspm_info_tco_video_input_format, \ 2986 .get = snd_hdspm_get_tco_video_input_format, \ 2987 } 2988 2989 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 2990 struct snd_ctl_elem_info *uinfo) 2991 { 2992 static char *texts[] = {"No video", "NTSC", "PAL"}; 2993 ENUMERATED_CTL_INFO(uinfo, texts); 2994 return 0; 2995 } 2996 2997 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 2998 struct snd_ctl_elem_value *ucontrol) 2999 { 3000 u32 status; 3001 int ret = 0; 3002 3003 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3004 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3005 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3006 HDSPM_TCO1_Video_Input_Format_PAL)) { 3007 case HDSPM_TCO1_Video_Input_Format_NTSC: 3008 /* ntsc */ 3009 ret = 1; 3010 break; 3011 case HDSPM_TCO1_Video_Input_Format_PAL: 3012 /* pal */ 3013 ret = 2; 3014 break; 3015 default: 3016 /* no video */ 3017 ret = 0; 3018 break; 3019 } 3020 ucontrol->value.enumerated.item[0] = ret; 3021 return 0; 3022 } 3023 3024 3025 3026 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \ 3027 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3028 .name = xname, \ 3029 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3030 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3031 .info = snd_hdspm_info_tco_ltc_frames, \ 3032 .get = snd_hdspm_get_tco_ltc_frames, \ 3033 } 3034 3035 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3036 struct snd_ctl_elem_info *uinfo) 3037 { 3038 static char *texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3039 "30 fps"}; 3040 ENUMERATED_CTL_INFO(uinfo, texts); 3041 return 0; 3042 } 3043 3044 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3045 { 3046 u32 status; 3047 int ret = 0; 3048 3049 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3050 if (status & HDSPM_TCO1_LTC_Input_valid) { 3051 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3052 HDSPM_TCO1_LTC_Format_MSB)) { 3053 case 0: 3054 /* 24 fps */ 3055 ret = 1; 3056 break; 3057 case HDSPM_TCO1_LTC_Format_LSB: 3058 /* 25 fps */ 3059 ret = 2; 3060 break; 3061 case HDSPM_TCO1_LTC_Format_MSB: 3062 /* 25 fps */ 3063 ret = 3; 3064 break; 3065 default: 3066 /* 30 fps */ 3067 ret = 4; 3068 break; 3069 } 3070 } 3071 3072 return ret; 3073 } 3074 3075 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3076 struct snd_ctl_elem_value *ucontrol) 3077 { 3078 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3079 3080 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3081 return 0; 3082 } 3083 3084 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3085 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3086 .name = xname, \ 3087 .private_value = xindex, \ 3088 .info = snd_hdspm_info_toggle_setting, \ 3089 .get = snd_hdspm_get_toggle_setting, \ 3090 .put = snd_hdspm_put_toggle_setting \ 3091 } 3092 3093 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3094 { 3095 return (hdspm->control_register & regmask) ? 1 : 0; 3096 } 3097 3098 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3099 { 3100 if (out) 3101 hdspm->control_register |= regmask; 3102 else 3103 hdspm->control_register &= ~regmask; 3104 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3105 3106 return 0; 3107 } 3108 3109 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3110 3111 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3112 struct snd_ctl_elem_value *ucontrol) 3113 { 3114 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3115 u32 regmask = kcontrol->private_value; 3116 3117 spin_lock_irq(&hdspm->lock); 3118 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3119 spin_unlock_irq(&hdspm->lock); 3120 return 0; 3121 } 3122 3123 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3124 struct snd_ctl_elem_value *ucontrol) 3125 { 3126 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3127 u32 regmask = kcontrol->private_value; 3128 int change; 3129 unsigned int val; 3130 3131 if (!snd_hdspm_use_is_exclusive(hdspm)) 3132 return -EBUSY; 3133 val = ucontrol->value.integer.value[0] & 1; 3134 spin_lock_irq(&hdspm->lock); 3135 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3136 hdspm_set_toggle_setting(hdspm, regmask, val); 3137 spin_unlock_irq(&hdspm->lock); 3138 return change; 3139 } 3140 3141 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3142 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3143 .name = xname, \ 3144 .index = xindex, \ 3145 .info = snd_hdspm_info_input_select, \ 3146 .get = snd_hdspm_get_input_select, \ 3147 .put = snd_hdspm_put_input_select \ 3148 } 3149 3150 static int hdspm_input_select(struct hdspm * hdspm) 3151 { 3152 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3153 } 3154 3155 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3156 { 3157 if (out) 3158 hdspm->control_register |= HDSPM_InputSelect0; 3159 else 3160 hdspm->control_register &= ~HDSPM_InputSelect0; 3161 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3162 3163 return 0; 3164 } 3165 3166 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3167 struct snd_ctl_elem_info *uinfo) 3168 { 3169 static char *texts[] = { "optical", "coaxial" }; 3170 ENUMERATED_CTL_INFO(uinfo, texts); 3171 return 0; 3172 } 3173 3174 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3175 struct snd_ctl_elem_value *ucontrol) 3176 { 3177 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3178 3179 spin_lock_irq(&hdspm->lock); 3180 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3181 spin_unlock_irq(&hdspm->lock); 3182 return 0; 3183 } 3184 3185 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3186 struct snd_ctl_elem_value *ucontrol) 3187 { 3188 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3189 int change; 3190 unsigned int val; 3191 3192 if (!snd_hdspm_use_is_exclusive(hdspm)) 3193 return -EBUSY; 3194 val = ucontrol->value.integer.value[0] & 1; 3195 spin_lock_irq(&hdspm->lock); 3196 change = (int) val != hdspm_input_select(hdspm); 3197 hdspm_set_input_select(hdspm, val); 3198 spin_unlock_irq(&hdspm->lock); 3199 return change; 3200 } 3201 3202 3203 #define HDSPM_DS_WIRE(xname, xindex) \ 3204 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3205 .name = xname, \ 3206 .index = xindex, \ 3207 .info = snd_hdspm_info_ds_wire, \ 3208 .get = snd_hdspm_get_ds_wire, \ 3209 .put = snd_hdspm_put_ds_wire \ 3210 } 3211 3212 static int hdspm_ds_wire(struct hdspm * hdspm) 3213 { 3214 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3215 } 3216 3217 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3218 { 3219 if (ds) 3220 hdspm->control_register |= HDSPM_DS_DoubleWire; 3221 else 3222 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3223 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3224 3225 return 0; 3226 } 3227 3228 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3229 struct snd_ctl_elem_info *uinfo) 3230 { 3231 static char *texts[] = { "Single", "Double" }; 3232 ENUMERATED_CTL_INFO(uinfo, texts); 3233 return 0; 3234 } 3235 3236 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3237 struct snd_ctl_elem_value *ucontrol) 3238 { 3239 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3240 3241 spin_lock_irq(&hdspm->lock); 3242 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3243 spin_unlock_irq(&hdspm->lock); 3244 return 0; 3245 } 3246 3247 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3248 struct snd_ctl_elem_value *ucontrol) 3249 { 3250 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3251 int change; 3252 unsigned int val; 3253 3254 if (!snd_hdspm_use_is_exclusive(hdspm)) 3255 return -EBUSY; 3256 val = ucontrol->value.integer.value[0] & 1; 3257 spin_lock_irq(&hdspm->lock); 3258 change = (int) val != hdspm_ds_wire(hdspm); 3259 hdspm_set_ds_wire(hdspm, val); 3260 spin_unlock_irq(&hdspm->lock); 3261 return change; 3262 } 3263 3264 3265 #define HDSPM_QS_WIRE(xname, xindex) \ 3266 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3267 .name = xname, \ 3268 .index = xindex, \ 3269 .info = snd_hdspm_info_qs_wire, \ 3270 .get = snd_hdspm_get_qs_wire, \ 3271 .put = snd_hdspm_put_qs_wire \ 3272 } 3273 3274 static int hdspm_qs_wire(struct hdspm * hdspm) 3275 { 3276 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3277 return 1; 3278 if (hdspm->control_register & HDSPM_QS_QuadWire) 3279 return 2; 3280 return 0; 3281 } 3282 3283 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3284 { 3285 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3286 switch (mode) { 3287 case 0: 3288 break; 3289 case 1: 3290 hdspm->control_register |= HDSPM_QS_DoubleWire; 3291 break; 3292 case 2: 3293 hdspm->control_register |= HDSPM_QS_QuadWire; 3294 break; 3295 } 3296 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3297 3298 return 0; 3299 } 3300 3301 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3302 struct snd_ctl_elem_info *uinfo) 3303 { 3304 static char *texts[] = { "Single", "Double", "Quad" }; 3305 ENUMERATED_CTL_INFO(uinfo, texts); 3306 return 0; 3307 } 3308 3309 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3310 struct snd_ctl_elem_value *ucontrol) 3311 { 3312 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3313 3314 spin_lock_irq(&hdspm->lock); 3315 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3316 spin_unlock_irq(&hdspm->lock); 3317 return 0; 3318 } 3319 3320 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3321 struct snd_ctl_elem_value *ucontrol) 3322 { 3323 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3324 int change; 3325 int val; 3326 3327 if (!snd_hdspm_use_is_exclusive(hdspm)) 3328 return -EBUSY; 3329 val = ucontrol->value.integer.value[0]; 3330 if (val < 0) 3331 val = 0; 3332 if (val > 2) 3333 val = 2; 3334 spin_lock_irq(&hdspm->lock); 3335 change = val != hdspm_qs_wire(hdspm); 3336 hdspm_set_qs_wire(hdspm, val); 3337 spin_unlock_irq(&hdspm->lock); 3338 return change; 3339 } 3340 3341 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3342 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3343 .name = xname, \ 3344 .index = xindex, \ 3345 .info = snd_hdspm_info_madi_speedmode, \ 3346 .get = snd_hdspm_get_madi_speedmode, \ 3347 .put = snd_hdspm_put_madi_speedmode \ 3348 } 3349 3350 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3351 { 3352 if (hdspm->control_register & HDSPM_QuadSpeed) 3353 return 2; 3354 if (hdspm->control_register & HDSPM_DoubleSpeed) 3355 return 1; 3356 return 0; 3357 } 3358 3359 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3360 { 3361 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3362 switch (mode) { 3363 case 0: 3364 break; 3365 case 1: 3366 hdspm->control_register |= HDSPM_DoubleSpeed; 3367 break; 3368 case 2: 3369 hdspm->control_register |= HDSPM_QuadSpeed; 3370 break; 3371 } 3372 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3373 3374 return 0; 3375 } 3376 3377 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3378 struct snd_ctl_elem_info *uinfo) 3379 { 3380 static char *texts[] = { "Single", "Double", "Quad" }; 3381 ENUMERATED_CTL_INFO(uinfo, texts); 3382 return 0; 3383 } 3384 3385 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3386 struct snd_ctl_elem_value *ucontrol) 3387 { 3388 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3389 3390 spin_lock_irq(&hdspm->lock); 3391 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3392 spin_unlock_irq(&hdspm->lock); 3393 return 0; 3394 } 3395 3396 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3397 struct snd_ctl_elem_value *ucontrol) 3398 { 3399 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3400 int change; 3401 int val; 3402 3403 if (!snd_hdspm_use_is_exclusive(hdspm)) 3404 return -EBUSY; 3405 val = ucontrol->value.integer.value[0]; 3406 if (val < 0) 3407 val = 0; 3408 if (val > 2) 3409 val = 2; 3410 spin_lock_irq(&hdspm->lock); 3411 change = val != hdspm_madi_speedmode(hdspm); 3412 hdspm_set_madi_speedmode(hdspm, val); 3413 spin_unlock_irq(&hdspm->lock); 3414 return change; 3415 } 3416 3417 #define HDSPM_MIXER(xname, xindex) \ 3418 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3419 .name = xname, \ 3420 .index = xindex, \ 3421 .device = 0, \ 3422 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3423 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3424 .info = snd_hdspm_info_mixer, \ 3425 .get = snd_hdspm_get_mixer, \ 3426 .put = snd_hdspm_put_mixer \ 3427 } 3428 3429 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3430 struct snd_ctl_elem_info *uinfo) 3431 { 3432 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3433 uinfo->count = 3; 3434 uinfo->value.integer.min = 0; 3435 uinfo->value.integer.max = 65535; 3436 uinfo->value.integer.step = 1; 3437 return 0; 3438 } 3439 3440 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3441 struct snd_ctl_elem_value *ucontrol) 3442 { 3443 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3444 int source; 3445 int destination; 3446 3447 source = ucontrol->value.integer.value[0]; 3448 if (source < 0) 3449 source = 0; 3450 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3451 source = 2 * HDSPM_MAX_CHANNELS - 1; 3452 3453 destination = ucontrol->value.integer.value[1]; 3454 if (destination < 0) 3455 destination = 0; 3456 else if (destination >= HDSPM_MAX_CHANNELS) 3457 destination = HDSPM_MAX_CHANNELS - 1; 3458 3459 spin_lock_irq(&hdspm->lock); 3460 if (source >= HDSPM_MAX_CHANNELS) 3461 ucontrol->value.integer.value[2] = 3462 hdspm_read_pb_gain(hdspm, destination, 3463 source - HDSPM_MAX_CHANNELS); 3464 else 3465 ucontrol->value.integer.value[2] = 3466 hdspm_read_in_gain(hdspm, destination, source); 3467 3468 spin_unlock_irq(&hdspm->lock); 3469 3470 return 0; 3471 } 3472 3473 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3474 struct snd_ctl_elem_value *ucontrol) 3475 { 3476 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3477 int change; 3478 int source; 3479 int destination; 3480 int gain; 3481 3482 if (!snd_hdspm_use_is_exclusive(hdspm)) 3483 return -EBUSY; 3484 3485 source = ucontrol->value.integer.value[0]; 3486 destination = ucontrol->value.integer.value[1]; 3487 3488 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3489 return -1; 3490 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3491 return -1; 3492 3493 gain = ucontrol->value.integer.value[2]; 3494 3495 spin_lock_irq(&hdspm->lock); 3496 3497 if (source >= HDSPM_MAX_CHANNELS) 3498 change = gain != hdspm_read_pb_gain(hdspm, destination, 3499 source - 3500 HDSPM_MAX_CHANNELS); 3501 else 3502 change = gain != hdspm_read_in_gain(hdspm, destination, 3503 source); 3504 3505 if (change) { 3506 if (source >= HDSPM_MAX_CHANNELS) 3507 hdspm_write_pb_gain(hdspm, destination, 3508 source - HDSPM_MAX_CHANNELS, 3509 gain); 3510 else 3511 hdspm_write_in_gain(hdspm, destination, source, 3512 gain); 3513 } 3514 spin_unlock_irq(&hdspm->lock); 3515 3516 return change; 3517 } 3518 3519 /* The simple mixer control(s) provide gain control for the 3520 basic 1:1 mappings of playback streams to output 3521 streams. 3522 */ 3523 3524 #define HDSPM_PLAYBACK_MIXER \ 3525 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3526 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3527 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3528 .info = snd_hdspm_info_playback_mixer, \ 3529 .get = snd_hdspm_get_playback_mixer, \ 3530 .put = snd_hdspm_put_playback_mixer \ 3531 } 3532 3533 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3534 struct snd_ctl_elem_info *uinfo) 3535 { 3536 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3537 uinfo->count = 1; 3538 uinfo->value.integer.min = 0; 3539 uinfo->value.integer.max = 64; 3540 uinfo->value.integer.step = 1; 3541 return 0; 3542 } 3543 3544 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3545 struct snd_ctl_elem_value *ucontrol) 3546 { 3547 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3548 int channel; 3549 3550 channel = ucontrol->id.index - 1; 3551 3552 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3553 return -EINVAL; 3554 3555 spin_lock_irq(&hdspm->lock); 3556 ucontrol->value.integer.value[0] = 3557 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3558 spin_unlock_irq(&hdspm->lock); 3559 3560 return 0; 3561 } 3562 3563 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3564 struct snd_ctl_elem_value *ucontrol) 3565 { 3566 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3567 int change; 3568 int channel; 3569 int gain; 3570 3571 if (!snd_hdspm_use_is_exclusive(hdspm)) 3572 return -EBUSY; 3573 3574 channel = ucontrol->id.index - 1; 3575 3576 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3577 return -EINVAL; 3578 3579 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3580 3581 spin_lock_irq(&hdspm->lock); 3582 change = 3583 gain != hdspm_read_pb_gain(hdspm, channel, 3584 channel); 3585 if (change) 3586 hdspm_write_pb_gain(hdspm, channel, channel, 3587 gain); 3588 spin_unlock_irq(&hdspm->lock); 3589 return change; 3590 } 3591 3592 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3593 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3594 .name = xname, \ 3595 .private_value = xindex, \ 3596 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3597 .info = snd_hdspm_info_sync_check, \ 3598 .get = snd_hdspm_get_sync_check \ 3599 } 3600 3601 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3602 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3603 .name = xname, \ 3604 .private_value = xindex, \ 3605 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3606 .info = snd_hdspm_tco_info_lock_check, \ 3607 .get = snd_hdspm_get_sync_check \ 3608 } 3609 3610 3611 3612 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3613 struct snd_ctl_elem_info *uinfo) 3614 { 3615 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3616 ENUMERATED_CTL_INFO(uinfo, texts); 3617 return 0; 3618 } 3619 3620 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3621 struct snd_ctl_elem_info *uinfo) 3622 { 3623 static char *texts[] = { "No Lock", "Lock" }; 3624 ENUMERATED_CTL_INFO(uinfo, texts); 3625 return 0; 3626 } 3627 3628 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3629 { 3630 int status, status2; 3631 3632 switch (hdspm->io_type) { 3633 case AES32: 3634 status = hdspm_read(hdspm, HDSPM_statusRegister); 3635 if (status & HDSPM_AES32_wcLock) { 3636 if (status & HDSPM_AES32_wcSync) 3637 return 2; 3638 else 3639 return 1; 3640 } 3641 return 0; 3642 break; 3643 3644 case MADI: 3645 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3646 if (status2 & HDSPM_wcLock) { 3647 if (status2 & HDSPM_wcSync) 3648 return 2; 3649 else 3650 return 1; 3651 } 3652 return 0; 3653 break; 3654 3655 case RayDAT: 3656 case AIO: 3657 status = hdspm_read(hdspm, HDSPM_statusRegister); 3658 3659 if (status & 0x2000000) 3660 return 2; 3661 else if (status & 0x1000000) 3662 return 1; 3663 return 0; 3664 3665 break; 3666 3667 case MADIface: 3668 break; 3669 } 3670 3671 3672 return 3; 3673 } 3674 3675 3676 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3677 { 3678 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3679 if (status & HDSPM_madiLock) { 3680 if (status & HDSPM_madiSync) 3681 return 2; 3682 else 3683 return 1; 3684 } 3685 return 0; 3686 } 3687 3688 3689 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3690 { 3691 int status, lock, sync; 3692 3693 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3694 3695 lock = (status & (0x1<<idx)) ? 1 : 0; 3696 sync = (status & (0x100<<idx)) ? 1 : 0; 3697 3698 if (lock && sync) 3699 return 2; 3700 else if (lock) 3701 return 1; 3702 return 0; 3703 } 3704 3705 3706 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3707 { 3708 int status, lock = 0, sync = 0; 3709 3710 switch (hdspm->io_type) { 3711 case RayDAT: 3712 case AIO: 3713 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3714 lock = (status & 0x400) ? 1 : 0; 3715 sync = (status & 0x800) ? 1 : 0; 3716 break; 3717 3718 case MADI: 3719 status = hdspm_read(hdspm, HDSPM_statusRegister); 3720 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3721 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3722 break; 3723 3724 case AES32: 3725 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3726 lock = (status & 0x100000) ? 1 : 0; 3727 sync = (status & 0x200000) ? 1 : 0; 3728 break; 3729 3730 case MADIface: 3731 break; 3732 } 3733 3734 if (lock && sync) 3735 return 2; 3736 else if (lock) 3737 return 1; 3738 3739 return 0; 3740 } 3741 3742 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3743 { 3744 int status2, lock, sync; 3745 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3746 3747 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3748 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3749 3750 if (sync) 3751 return 2; 3752 else if (lock) 3753 return 1; 3754 return 0; 3755 } 3756 3757 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3758 { 3759 u32 status; 3760 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3761 3762 return (status & mask) ? 1 : 0; 3763 } 3764 3765 3766 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3767 { 3768 int status; 3769 3770 if (hdspm->tco) { 3771 switch (hdspm->io_type) { 3772 case MADI: 3773 case AES32: 3774 status = hdspm_read(hdspm, HDSPM_statusRegister); 3775 if (status & HDSPM_tcoLock) { 3776 if (status & HDSPM_tcoSync) 3777 return 2; 3778 else 3779 return 1; 3780 } 3781 return 0; 3782 3783 break; 3784 3785 case RayDAT: 3786 case AIO: 3787 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3788 3789 if (status & 0x8000000) 3790 return 2; /* Sync */ 3791 if (status & 0x4000000) 3792 return 1; /* Lock */ 3793 return 0; /* No signal */ 3794 break; 3795 3796 default: 3797 break; 3798 } 3799 } 3800 3801 return 3; /* N/A */ 3802 } 3803 3804 3805 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3806 struct snd_ctl_elem_value *ucontrol) 3807 { 3808 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3809 int val = -1; 3810 3811 switch (hdspm->io_type) { 3812 case RayDAT: 3813 switch (kcontrol->private_value) { 3814 case 0: /* WC */ 3815 val = hdspm_wc_sync_check(hdspm); break; 3816 case 7: /* TCO */ 3817 val = hdspm_tco_sync_check(hdspm); break; 3818 case 8: /* SYNC IN */ 3819 val = hdspm_sync_in_sync_check(hdspm); break; 3820 default: 3821 val = hdspm_s1_sync_check(hdspm, 3822 kcontrol->private_value-1); 3823 } 3824 break; 3825 3826 case AIO: 3827 switch (kcontrol->private_value) { 3828 case 0: /* WC */ 3829 val = hdspm_wc_sync_check(hdspm); break; 3830 case 4: /* TCO */ 3831 val = hdspm_tco_sync_check(hdspm); break; 3832 case 5: /* SYNC IN */ 3833 val = hdspm_sync_in_sync_check(hdspm); break; 3834 default: 3835 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3836 } 3837 break; 3838 3839 case MADI: 3840 switch (kcontrol->private_value) { 3841 case 0: /* WC */ 3842 val = hdspm_wc_sync_check(hdspm); break; 3843 case 1: /* MADI */ 3844 val = hdspm_madi_sync_check(hdspm); break; 3845 case 2: /* TCO */ 3846 val = hdspm_tco_sync_check(hdspm); break; 3847 case 3: /* SYNC_IN */ 3848 val = hdspm_sync_in_sync_check(hdspm); break; 3849 } 3850 break; 3851 3852 case MADIface: 3853 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3854 break; 3855 3856 case AES32: 3857 switch (kcontrol->private_value) { 3858 case 0: /* WC */ 3859 val = hdspm_wc_sync_check(hdspm); break; 3860 case 9: /* TCO */ 3861 val = hdspm_tco_sync_check(hdspm); break; 3862 case 10 /* SYNC IN */: 3863 val = hdspm_sync_in_sync_check(hdspm); break; 3864 default: /* AES1 to AES8 */ 3865 val = hdspm_aes_sync_check(hdspm, 3866 kcontrol->private_value-1); 3867 } 3868 break; 3869 3870 } 3871 3872 if (hdspm->tco) { 3873 switch (kcontrol->private_value) { 3874 case 11: 3875 /* Check TCO for lock state of its current input */ 3876 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 3877 break; 3878 case 12: 3879 /* Check TCO for valid time code on LTC input. */ 3880 val = hdspm_tco_input_check(hdspm, 3881 HDSPM_TCO1_LTC_Input_valid); 3882 break; 3883 default: 3884 break; 3885 } 3886 } 3887 3888 if (-1 == val) 3889 val = 3; 3890 3891 ucontrol->value.enumerated.item[0] = val; 3892 return 0; 3893 } 3894 3895 3896 3897 /** 3898 * TCO controls 3899 **/ 3900 static void hdspm_tco_write(struct hdspm *hdspm) 3901 { 3902 unsigned int tc[4] = { 0, 0, 0, 0}; 3903 3904 switch (hdspm->tco->input) { 3905 case 0: 3906 tc[2] |= HDSPM_TCO2_set_input_MSB; 3907 break; 3908 case 1: 3909 tc[2] |= HDSPM_TCO2_set_input_LSB; 3910 break; 3911 default: 3912 break; 3913 } 3914 3915 switch (hdspm->tco->framerate) { 3916 case 1: 3917 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 3918 break; 3919 case 2: 3920 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 3921 break; 3922 case 3: 3923 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 3924 HDSPM_TCO1_set_drop_frame_flag; 3925 break; 3926 case 4: 3927 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3928 HDSPM_TCO1_LTC_Format_MSB; 3929 break; 3930 case 5: 3931 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3932 HDSPM_TCO1_LTC_Format_MSB + 3933 HDSPM_TCO1_set_drop_frame_flag; 3934 break; 3935 default: 3936 break; 3937 } 3938 3939 switch (hdspm->tco->wordclock) { 3940 case 1: 3941 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 3942 break; 3943 case 2: 3944 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 3945 break; 3946 default: 3947 break; 3948 } 3949 3950 switch (hdspm->tco->samplerate) { 3951 case 1: 3952 tc[2] |= HDSPM_TCO2_set_freq; 3953 break; 3954 case 2: 3955 tc[2] |= HDSPM_TCO2_set_freq_from_app; 3956 break; 3957 default: 3958 break; 3959 } 3960 3961 switch (hdspm->tco->pull) { 3962 case 1: 3963 tc[2] |= HDSPM_TCO2_set_pull_up; 3964 break; 3965 case 2: 3966 tc[2] |= HDSPM_TCO2_set_pull_down; 3967 break; 3968 case 3: 3969 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 3970 break; 3971 case 4: 3972 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 3973 break; 3974 default: 3975 break; 3976 } 3977 3978 if (1 == hdspm->tco->term) { 3979 tc[2] |= HDSPM_TCO2_set_term_75R; 3980 } 3981 3982 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 3983 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 3984 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 3985 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 3986 } 3987 3988 3989 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 3990 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3991 .name = xname, \ 3992 .index = xindex, \ 3993 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3994 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3995 .info = snd_hdspm_info_tco_sample_rate, \ 3996 .get = snd_hdspm_get_tco_sample_rate, \ 3997 .put = snd_hdspm_put_tco_sample_rate \ 3998 } 3999 4000 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4001 struct snd_ctl_elem_info *uinfo) 4002 { 4003 static char *texts[] = { "44.1 kHz", "48 kHz" }; 4004 ENUMERATED_CTL_INFO(uinfo, texts); 4005 return 0; 4006 } 4007 4008 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4009 struct snd_ctl_elem_value *ucontrol) 4010 { 4011 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4012 4013 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4014 4015 return 0; 4016 } 4017 4018 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4019 struct snd_ctl_elem_value *ucontrol) 4020 { 4021 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4022 4023 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4024 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4025 4026 hdspm_tco_write(hdspm); 4027 4028 return 1; 4029 } 4030 4031 return 0; 4032 } 4033 4034 4035 #define HDSPM_TCO_PULL(xname, xindex) \ 4036 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4037 .name = xname, \ 4038 .index = xindex, \ 4039 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4040 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4041 .info = snd_hdspm_info_tco_pull, \ 4042 .get = snd_hdspm_get_tco_pull, \ 4043 .put = snd_hdspm_put_tco_pull \ 4044 } 4045 4046 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4047 struct snd_ctl_elem_info *uinfo) 4048 { 4049 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 4050 ENUMERATED_CTL_INFO(uinfo, texts); 4051 return 0; 4052 } 4053 4054 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4055 struct snd_ctl_elem_value *ucontrol) 4056 { 4057 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4058 4059 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4060 4061 return 0; 4062 } 4063 4064 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4065 struct snd_ctl_elem_value *ucontrol) 4066 { 4067 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4068 4069 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4070 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4071 4072 hdspm_tco_write(hdspm); 4073 4074 return 1; 4075 } 4076 4077 return 0; 4078 } 4079 4080 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4081 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4082 .name = xname, \ 4083 .index = xindex, \ 4084 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4085 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4086 .info = snd_hdspm_info_tco_wck_conversion, \ 4087 .get = snd_hdspm_get_tco_wck_conversion, \ 4088 .put = snd_hdspm_put_tco_wck_conversion \ 4089 } 4090 4091 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4092 struct snd_ctl_elem_info *uinfo) 4093 { 4094 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4095 ENUMERATED_CTL_INFO(uinfo, texts); 4096 return 0; 4097 } 4098 4099 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4100 struct snd_ctl_elem_value *ucontrol) 4101 { 4102 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4103 4104 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4105 4106 return 0; 4107 } 4108 4109 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4110 struct snd_ctl_elem_value *ucontrol) 4111 { 4112 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4113 4114 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4115 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4116 4117 hdspm_tco_write(hdspm); 4118 4119 return 1; 4120 } 4121 4122 return 0; 4123 } 4124 4125 4126 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4127 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4128 .name = xname, \ 4129 .index = xindex, \ 4130 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4131 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4132 .info = snd_hdspm_info_tco_frame_rate, \ 4133 .get = snd_hdspm_get_tco_frame_rate, \ 4134 .put = snd_hdspm_put_tco_frame_rate \ 4135 } 4136 4137 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4138 struct snd_ctl_elem_info *uinfo) 4139 { 4140 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 4141 "29.97 dfps", "30 fps", "30 dfps" }; 4142 ENUMERATED_CTL_INFO(uinfo, texts); 4143 return 0; 4144 } 4145 4146 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4147 struct snd_ctl_elem_value *ucontrol) 4148 { 4149 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4150 4151 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4152 4153 return 0; 4154 } 4155 4156 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4157 struct snd_ctl_elem_value *ucontrol) 4158 { 4159 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4160 4161 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4162 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4163 4164 hdspm_tco_write(hdspm); 4165 4166 return 1; 4167 } 4168 4169 return 0; 4170 } 4171 4172 4173 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4174 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4175 .name = xname, \ 4176 .index = xindex, \ 4177 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4178 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4179 .info = snd_hdspm_info_tco_sync_source, \ 4180 .get = snd_hdspm_get_tco_sync_source, \ 4181 .put = snd_hdspm_put_tco_sync_source \ 4182 } 4183 4184 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4185 struct snd_ctl_elem_info *uinfo) 4186 { 4187 static char *texts[] = { "LTC", "Video", "WCK" }; 4188 ENUMERATED_CTL_INFO(uinfo, texts); 4189 return 0; 4190 } 4191 4192 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4193 struct snd_ctl_elem_value *ucontrol) 4194 { 4195 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4196 4197 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4198 4199 return 0; 4200 } 4201 4202 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4203 struct snd_ctl_elem_value *ucontrol) 4204 { 4205 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4206 4207 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4208 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4209 4210 hdspm_tco_write(hdspm); 4211 4212 return 1; 4213 } 4214 4215 return 0; 4216 } 4217 4218 4219 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4220 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4221 .name = xname, \ 4222 .index = xindex, \ 4223 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4224 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4225 .info = snd_hdspm_info_tco_word_term, \ 4226 .get = snd_hdspm_get_tco_word_term, \ 4227 .put = snd_hdspm_put_tco_word_term \ 4228 } 4229 4230 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4231 struct snd_ctl_elem_info *uinfo) 4232 { 4233 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4234 uinfo->count = 1; 4235 uinfo->value.integer.min = 0; 4236 uinfo->value.integer.max = 1; 4237 4238 return 0; 4239 } 4240 4241 4242 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4243 struct snd_ctl_elem_value *ucontrol) 4244 { 4245 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4246 4247 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4248 4249 return 0; 4250 } 4251 4252 4253 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4254 struct snd_ctl_elem_value *ucontrol) 4255 { 4256 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4257 4258 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4259 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4260 4261 hdspm_tco_write(hdspm); 4262 4263 return 1; 4264 } 4265 4266 return 0; 4267 } 4268 4269 4270 4271 4272 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4273 HDSPM_MIXER("Mixer", 0), 4274 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4275 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4276 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4277 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4278 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4279 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4280 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4281 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4282 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4283 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4284 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4285 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4286 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4287 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4288 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4289 HDSPM_INPUT_SELECT("Input Select", 0), 4290 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4291 }; 4292 4293 4294 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4295 HDSPM_MIXER("Mixer", 0), 4296 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4297 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4298 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4299 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4300 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4301 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4302 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4303 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4304 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4305 }; 4306 4307 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4308 HDSPM_MIXER("Mixer", 0), 4309 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4310 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4311 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4312 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4313 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4314 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4315 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4316 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4317 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4318 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4319 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4320 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4321 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4322 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4323 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4324 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4325 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4326 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4327 4328 /* 4329 HDSPM_INPUT_SELECT("Input Select", 0), 4330 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4331 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4332 HDSPM_SPDIF_IN("SPDIF In", 0); 4333 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4334 HDSPM_INPUT_LEVEL("Input Level", 0); 4335 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4336 HDSPM_PHONES("Phones", 0); 4337 */ 4338 }; 4339 4340 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4341 HDSPM_MIXER("Mixer", 0), 4342 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4343 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4344 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4345 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4346 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4347 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4348 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4349 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4350 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4351 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4352 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4353 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4354 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4355 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4356 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4357 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4358 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4359 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4360 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4361 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4362 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4363 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4364 }; 4365 4366 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4367 HDSPM_MIXER("Mixer", 0), 4368 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4369 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4370 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4371 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4372 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4373 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4374 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4375 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4376 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4377 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4378 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4379 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4380 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4381 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4382 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4383 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4384 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4385 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4386 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4387 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4388 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4389 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4390 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4391 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4392 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4393 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4394 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4395 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4396 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4397 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4398 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4399 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4400 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4401 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4402 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4403 }; 4404 4405 4406 4407 /* Control elements for the optional TCO module */ 4408 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4409 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4410 HDSPM_TCO_PULL("TCO Pull", 0), 4411 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4412 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4413 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4414 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4415 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4416 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4417 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0), 4418 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0) 4419 }; 4420 4421 4422 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4423 4424 4425 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4426 { 4427 int i; 4428 4429 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4430 if (hdspm->system_sample_rate > 48000) { 4431 hdspm->playback_mixer_ctls[i]->vd[0].access = 4432 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4433 SNDRV_CTL_ELEM_ACCESS_READ | 4434 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4435 } else { 4436 hdspm->playback_mixer_ctls[i]->vd[0].access = 4437 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4438 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4439 } 4440 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4441 SNDRV_CTL_EVENT_MASK_INFO, 4442 &hdspm->playback_mixer_ctls[i]->id); 4443 } 4444 4445 return 0; 4446 } 4447 4448 4449 static int snd_hdspm_create_controls(struct snd_card *card, 4450 struct hdspm *hdspm) 4451 { 4452 unsigned int idx, limit; 4453 int err; 4454 struct snd_kcontrol *kctl; 4455 struct snd_kcontrol_new *list = NULL; 4456 4457 switch (hdspm->io_type) { 4458 case MADI: 4459 list = snd_hdspm_controls_madi; 4460 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4461 break; 4462 case MADIface: 4463 list = snd_hdspm_controls_madiface; 4464 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4465 break; 4466 case AIO: 4467 list = snd_hdspm_controls_aio; 4468 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4469 break; 4470 case RayDAT: 4471 list = snd_hdspm_controls_raydat; 4472 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4473 break; 4474 case AES32: 4475 list = snd_hdspm_controls_aes32; 4476 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4477 break; 4478 } 4479 4480 if (NULL != list) { 4481 for (idx = 0; idx < limit; idx++) { 4482 err = snd_ctl_add(card, 4483 snd_ctl_new1(&list[idx], hdspm)); 4484 if (err < 0) 4485 return err; 4486 } 4487 } 4488 4489 4490 /* create simple 1:1 playback mixer controls */ 4491 snd_hdspm_playback_mixer.name = "Chn"; 4492 if (hdspm->system_sample_rate >= 128000) { 4493 limit = hdspm->qs_out_channels; 4494 } else if (hdspm->system_sample_rate >= 64000) { 4495 limit = hdspm->ds_out_channels; 4496 } else { 4497 limit = hdspm->ss_out_channels; 4498 } 4499 for (idx = 0; idx < limit; ++idx) { 4500 snd_hdspm_playback_mixer.index = idx + 1; 4501 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4502 err = snd_ctl_add(card, kctl); 4503 if (err < 0) 4504 return err; 4505 hdspm->playback_mixer_ctls[idx] = kctl; 4506 } 4507 4508 4509 if (hdspm->tco) { 4510 /* add tco control elements */ 4511 list = snd_hdspm_controls_tco; 4512 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4513 for (idx = 0; idx < limit; idx++) { 4514 err = snd_ctl_add(card, 4515 snd_ctl_new1(&list[idx], hdspm)); 4516 if (err < 0) 4517 return err; 4518 } 4519 } 4520 4521 return 0; 4522 } 4523 4524 /*------------------------------------------------------------ 4525 /proc interface 4526 ------------------------------------------------------------*/ 4527 4528 static void 4529 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4530 struct snd_info_buffer *buffer) 4531 { 4532 struct hdspm *hdspm = entry->private_data; 4533 unsigned int status, status2, control, freq; 4534 4535 char *pref_sync_ref; 4536 char *autosync_ref; 4537 char *system_clock_mode; 4538 char *insel; 4539 int x, x2; 4540 4541 /* TCO stuff */ 4542 int a, ltc, frames, seconds, minutes, hours; 4543 unsigned int period; 4544 u64 freq_const = 0; 4545 u32 rate; 4546 4547 status = hdspm_read(hdspm, HDSPM_statusRegister); 4548 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4549 control = hdspm->control_register; 4550 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4551 4552 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4553 hdspm->card_name, hdspm->card->number + 1, 4554 hdspm->firmware_rev, 4555 (status2 & HDSPM_version0) | 4556 (status2 & HDSPM_version1) | (status2 & 4557 HDSPM_version2)); 4558 4559 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4560 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4561 hdspm->serial); 4562 4563 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4564 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4565 4566 snd_iprintf(buffer, "--- System ---\n"); 4567 4568 snd_iprintf(buffer, 4569 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4570 status & HDSPM_audioIRQPending, 4571 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4572 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4573 hdspm->irq_count); 4574 snd_iprintf(buffer, 4575 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4576 "estimated= %ld (bytes)\n", 4577 ((status & HDSPM_BufferID) ? 1 : 0), 4578 (status & HDSPM_BufferPositionMask), 4579 (status & HDSPM_BufferPositionMask) % 4580 (2 * (int)hdspm->period_bytes), 4581 ((status & HDSPM_BufferPositionMask) - 64) % 4582 (2 * (int)hdspm->period_bytes), 4583 (long) hdspm_hw_pointer(hdspm) * 4); 4584 4585 snd_iprintf(buffer, 4586 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4587 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4588 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4589 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4590 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4591 snd_iprintf(buffer, 4592 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4593 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4594 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4595 snd_iprintf(buffer, 4596 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4597 "status2=0x%x\n", 4598 hdspm->control_register, hdspm->control2_register, 4599 status, status2); 4600 if (status & HDSPM_tco_detect) { 4601 snd_iprintf(buffer, "TCO module detected.\n"); 4602 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4603 if (a & HDSPM_TCO1_LTC_Input_valid) { 4604 snd_iprintf(buffer, " LTC valid, "); 4605 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4606 HDSPM_TCO1_LTC_Format_MSB)) { 4607 case 0: 4608 snd_iprintf(buffer, "24 fps, "); 4609 break; 4610 case HDSPM_TCO1_LTC_Format_LSB: 4611 snd_iprintf(buffer, "25 fps, "); 4612 break; 4613 case HDSPM_TCO1_LTC_Format_MSB: 4614 snd_iprintf(buffer, "29.97 fps, "); 4615 break; 4616 default: 4617 snd_iprintf(buffer, "30 fps, "); 4618 break; 4619 } 4620 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4621 snd_iprintf(buffer, "drop frame\n"); 4622 } else { 4623 snd_iprintf(buffer, "full frame\n"); 4624 } 4625 } else { 4626 snd_iprintf(buffer, " no LTC\n"); 4627 } 4628 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4629 snd_iprintf(buffer, " Video: NTSC\n"); 4630 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4631 snd_iprintf(buffer, " Video: PAL\n"); 4632 } else { 4633 snd_iprintf(buffer, " No video\n"); 4634 } 4635 if (a & HDSPM_TCO1_TCO_lock) { 4636 snd_iprintf(buffer, " Sync: lock\n"); 4637 } else { 4638 snd_iprintf(buffer, " Sync: no lock\n"); 4639 } 4640 4641 switch (hdspm->io_type) { 4642 case MADI: 4643 case AES32: 4644 freq_const = 110069313433624ULL; 4645 break; 4646 case RayDAT: 4647 case AIO: 4648 freq_const = 104857600000000ULL; 4649 break; 4650 case MADIface: 4651 break; /* no TCO possible */ 4652 } 4653 4654 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4655 snd_iprintf(buffer, " period: %u\n", period); 4656 4657 4658 /* rate = freq_const/period; */ 4659 rate = div_u64(freq_const, period); 4660 4661 if (control & HDSPM_QuadSpeed) { 4662 rate *= 4; 4663 } else if (control & HDSPM_DoubleSpeed) { 4664 rate *= 2; 4665 } 4666 4667 snd_iprintf(buffer, " Frequency: %u Hz\n", 4668 (unsigned int) rate); 4669 4670 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4671 frames = ltc & 0xF; 4672 ltc >>= 4; 4673 frames += (ltc & 0x3) * 10; 4674 ltc >>= 4; 4675 seconds = ltc & 0xF; 4676 ltc >>= 4; 4677 seconds += (ltc & 0x7) * 10; 4678 ltc >>= 4; 4679 minutes = ltc & 0xF; 4680 ltc >>= 4; 4681 minutes += (ltc & 0x7) * 10; 4682 ltc >>= 4; 4683 hours = ltc & 0xF; 4684 ltc >>= 4; 4685 hours += (ltc & 0x3) * 10; 4686 snd_iprintf(buffer, 4687 " LTC In: %02d:%02d:%02d:%02d\n", 4688 hours, minutes, seconds, frames); 4689 4690 } else { 4691 snd_iprintf(buffer, "No TCO module detected.\n"); 4692 } 4693 4694 snd_iprintf(buffer, "--- Settings ---\n"); 4695 4696 x = hdspm_get_latency(hdspm); 4697 4698 snd_iprintf(buffer, 4699 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4700 x, (unsigned long) hdspm->period_bytes); 4701 4702 snd_iprintf(buffer, "Line out: %s\n", 4703 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4704 4705 switch (hdspm->control_register & HDSPM_InputMask) { 4706 case HDSPM_InputOptical: 4707 insel = "Optical"; 4708 break; 4709 case HDSPM_InputCoaxial: 4710 insel = "Coaxial"; 4711 break; 4712 default: 4713 insel = "Unknown"; 4714 } 4715 4716 snd_iprintf(buffer, 4717 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4718 "Auto Input %s\n", 4719 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4720 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4721 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4722 4723 4724 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4725 system_clock_mode = "AutoSync"; 4726 else 4727 system_clock_mode = "Master"; 4728 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4729 4730 switch (hdspm_pref_sync_ref(hdspm)) { 4731 case HDSPM_SYNC_FROM_WORD: 4732 pref_sync_ref = "Word Clock"; 4733 break; 4734 case HDSPM_SYNC_FROM_MADI: 4735 pref_sync_ref = "MADI Sync"; 4736 break; 4737 case HDSPM_SYNC_FROM_TCO: 4738 pref_sync_ref = "TCO"; 4739 break; 4740 case HDSPM_SYNC_FROM_SYNC_IN: 4741 pref_sync_ref = "Sync In"; 4742 break; 4743 default: 4744 pref_sync_ref = "XXXX Clock"; 4745 break; 4746 } 4747 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4748 pref_sync_ref); 4749 4750 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4751 hdspm->system_sample_rate); 4752 4753 4754 snd_iprintf(buffer, "--- Status:\n"); 4755 4756 x = status & HDSPM_madiSync; 4757 x2 = status2 & HDSPM_wcSync; 4758 4759 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4760 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4761 "NoLock", 4762 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4763 "NoLock"); 4764 4765 switch (hdspm_autosync_ref(hdspm)) { 4766 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4767 autosync_ref = "Sync In"; 4768 break; 4769 case HDSPM_AUTOSYNC_FROM_TCO: 4770 autosync_ref = "TCO"; 4771 break; 4772 case HDSPM_AUTOSYNC_FROM_WORD: 4773 autosync_ref = "Word Clock"; 4774 break; 4775 case HDSPM_AUTOSYNC_FROM_MADI: 4776 autosync_ref = "MADI Sync"; 4777 break; 4778 case HDSPM_AUTOSYNC_FROM_NONE: 4779 autosync_ref = "Input not valid"; 4780 break; 4781 default: 4782 autosync_ref = "---"; 4783 break; 4784 } 4785 snd_iprintf(buffer, 4786 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4787 autosync_ref, hdspm_external_sample_rate(hdspm), 4788 (status & HDSPM_madiFreqMask) >> 22, 4789 (status2 & HDSPM_wcFreqMask) >> 5); 4790 4791 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4792 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4793 (status & HDSPM_RX_64ch) ? "64 channels" : 4794 "56 channels"); 4795 4796 snd_iprintf(buffer, "\n"); 4797 } 4798 4799 static void 4800 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4801 struct snd_info_buffer *buffer) 4802 { 4803 struct hdspm *hdspm = entry->private_data; 4804 unsigned int status; 4805 unsigned int status2; 4806 unsigned int timecode; 4807 unsigned int wcLock, wcSync; 4808 int pref_syncref; 4809 char *autosync_ref; 4810 int x; 4811 4812 status = hdspm_read(hdspm, HDSPM_statusRegister); 4813 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4814 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4815 4816 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4817 hdspm->card_name, hdspm->card->number + 1, 4818 hdspm->firmware_rev); 4819 4820 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4821 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4822 4823 snd_iprintf(buffer, "--- System ---\n"); 4824 4825 snd_iprintf(buffer, 4826 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4827 status & HDSPM_audioIRQPending, 4828 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4829 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4830 hdspm->irq_count); 4831 snd_iprintf(buffer, 4832 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4833 "estimated= %ld (bytes)\n", 4834 ((status & HDSPM_BufferID) ? 1 : 0), 4835 (status & HDSPM_BufferPositionMask), 4836 (status & HDSPM_BufferPositionMask) % 4837 (2 * (int)hdspm->period_bytes), 4838 ((status & HDSPM_BufferPositionMask) - 64) % 4839 (2 * (int)hdspm->period_bytes), 4840 (long) hdspm_hw_pointer(hdspm) * 4); 4841 4842 snd_iprintf(buffer, 4843 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4844 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4845 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4846 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4847 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4848 snd_iprintf(buffer, 4849 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4850 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4851 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4852 snd_iprintf(buffer, 4853 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4854 "status2=0x%x\n", 4855 hdspm->control_register, hdspm->control2_register, 4856 status, status2); 4857 4858 snd_iprintf(buffer, "--- Settings ---\n"); 4859 4860 x = hdspm_get_latency(hdspm); 4861 4862 snd_iprintf(buffer, 4863 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4864 x, (unsigned long) hdspm->period_bytes); 4865 4866 snd_iprintf(buffer, "Line out: %s\n", 4867 (hdspm-> 4868 control_register & HDSPM_LineOut) ? "on " : "off"); 4869 4870 snd_iprintf(buffer, 4871 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 4872 (hdspm-> 4873 control_register & HDSPM_clr_tms) ? "on" : "off", 4874 (hdspm-> 4875 control_register & HDSPM_Emphasis) ? "on" : "off", 4876 (hdspm-> 4877 control_register & HDSPM_Dolby) ? "on" : "off"); 4878 4879 4880 pref_syncref = hdspm_pref_sync_ref(hdspm); 4881 if (pref_syncref == 0) 4882 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 4883 else 4884 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 4885 pref_syncref); 4886 4887 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4888 hdspm->system_sample_rate); 4889 4890 snd_iprintf(buffer, "Double speed: %s\n", 4891 hdspm->control_register & HDSPM_DS_DoubleWire? 4892 "Double wire" : "Single wire"); 4893 snd_iprintf(buffer, "Quad speed: %s\n", 4894 hdspm->control_register & HDSPM_QS_DoubleWire? 4895 "Double wire" : 4896 hdspm->control_register & HDSPM_QS_QuadWire? 4897 "Quad wire" : "Single wire"); 4898 4899 snd_iprintf(buffer, "--- Status:\n"); 4900 4901 wcLock = status & HDSPM_AES32_wcLock; 4902 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 4903 4904 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 4905 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 4906 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 4907 4908 for (x = 0; x < 8; x++) { 4909 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 4910 x+1, 4911 (status2 & (HDSPM_LockAES >> x)) ? 4912 "Sync " : "No Lock", 4913 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 4914 } 4915 4916 switch (hdspm_autosync_ref(hdspm)) { 4917 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 4918 autosync_ref = "None"; break; 4919 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 4920 autosync_ref = "Word Clock"; break; 4921 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 4922 autosync_ref = "AES1"; break; 4923 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 4924 autosync_ref = "AES2"; break; 4925 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 4926 autosync_ref = "AES3"; break; 4927 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 4928 autosync_ref = "AES4"; break; 4929 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 4930 autosync_ref = "AES5"; break; 4931 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 4932 autosync_ref = "AES6"; break; 4933 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 4934 autosync_ref = "AES7"; break; 4935 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 4936 autosync_ref = "AES8"; break; 4937 default: 4938 autosync_ref = "---"; break; 4939 } 4940 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 4941 4942 snd_iprintf(buffer, "\n"); 4943 } 4944 4945 static void 4946 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 4947 struct snd_info_buffer *buffer) 4948 { 4949 struct hdspm *hdspm = entry->private_data; 4950 unsigned int status1, status2, status3, control, i; 4951 unsigned int lock, sync; 4952 4953 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 4954 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 4955 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 4956 4957 control = hdspm->control_register; 4958 4959 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 4960 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 4961 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 4962 4963 4964 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 4965 4966 snd_iprintf(buffer, "Clock mode : %s\n", 4967 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 4968 snd_iprintf(buffer, "System frequency: %d Hz\n", 4969 hdspm_get_system_sample_rate(hdspm)); 4970 4971 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 4972 4973 lock = 0x1; 4974 sync = 0x100; 4975 4976 for (i = 0; i < 8; i++) { 4977 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 4978 i, 4979 (status1 & lock) ? 1 : 0, 4980 (status1 & sync) ? 1 : 0, 4981 texts_freq[(status2 >> (i * 4)) & 0xF]); 4982 4983 lock = lock<<1; 4984 sync = sync<<1; 4985 } 4986 4987 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 4988 (status1 & 0x1000000) ? 1 : 0, 4989 (status1 & 0x2000000) ? 1 : 0, 4990 texts_freq[(status1 >> 16) & 0xF]); 4991 4992 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 4993 (status1 & 0x4000000) ? 1 : 0, 4994 (status1 & 0x8000000) ? 1 : 0, 4995 texts_freq[(status1 >> 20) & 0xF]); 4996 4997 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 4998 (status3 & 0x400) ? 1 : 0, 4999 (status3 & 0x800) ? 1 : 0, 5000 texts_freq[(status2 >> 12) & 0xF]); 5001 5002 } 5003 5004 #ifdef CONFIG_SND_DEBUG 5005 static void 5006 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5007 struct snd_info_buffer *buffer) 5008 { 5009 struct hdspm *hdspm = entry->private_data; 5010 5011 int j,i; 5012 5013 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5014 snd_iprintf(buffer, "0x%08X: ", i); 5015 for (j = 0; j < 16; j += 4) 5016 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5017 snd_iprintf(buffer, "\n"); 5018 } 5019 } 5020 #endif 5021 5022 5023 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5024 struct snd_info_buffer *buffer) 5025 { 5026 struct hdspm *hdspm = entry->private_data; 5027 int i; 5028 5029 snd_iprintf(buffer, "# generated by hdspm\n"); 5030 5031 for (i = 0; i < hdspm->max_channels_in; i++) { 5032 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5033 } 5034 } 5035 5036 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5037 struct snd_info_buffer *buffer) 5038 { 5039 struct hdspm *hdspm = entry->private_data; 5040 int i; 5041 5042 snd_iprintf(buffer, "# generated by hdspm\n"); 5043 5044 for (i = 0; i < hdspm->max_channels_out; i++) { 5045 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5046 } 5047 } 5048 5049 5050 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5051 { 5052 struct snd_info_entry *entry; 5053 5054 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5055 switch (hdspm->io_type) { 5056 case AES32: 5057 snd_info_set_text_ops(entry, hdspm, 5058 snd_hdspm_proc_read_aes32); 5059 break; 5060 case MADI: 5061 snd_info_set_text_ops(entry, hdspm, 5062 snd_hdspm_proc_read_madi); 5063 break; 5064 case MADIface: 5065 /* snd_info_set_text_ops(entry, hdspm, 5066 snd_hdspm_proc_read_madiface); */ 5067 break; 5068 case RayDAT: 5069 snd_info_set_text_ops(entry, hdspm, 5070 snd_hdspm_proc_read_raydat); 5071 break; 5072 case AIO: 5073 break; 5074 } 5075 } 5076 5077 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5078 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5079 } 5080 5081 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5082 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5083 } 5084 5085 #ifdef CONFIG_SND_DEBUG 5086 /* debug file to read all hdspm registers */ 5087 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5088 snd_info_set_text_ops(entry, hdspm, 5089 snd_hdspm_proc_read_debug); 5090 #endif 5091 } 5092 5093 /*------------------------------------------------------------ 5094 hdspm intitialize 5095 ------------------------------------------------------------*/ 5096 5097 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5098 { 5099 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5100 hold it (e.g. during module initialization). 5101 */ 5102 5103 /* set defaults: */ 5104 5105 hdspm->settings_register = 0; 5106 5107 switch (hdspm->io_type) { 5108 case MADI: 5109 case MADIface: 5110 hdspm->control_register = 5111 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5112 break; 5113 5114 case RayDAT: 5115 case AIO: 5116 hdspm->settings_register = 0x1 + 0x1000; 5117 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5118 * line_out */ 5119 hdspm->control_register = 5120 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5121 break; 5122 5123 case AES32: 5124 hdspm->control_register = 5125 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 5126 hdspm_encode_latency(7) | /* latency max=8192samples */ 5127 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5128 HDSPM_LineOut | /* Analog output in */ 5129 HDSPM_Professional; /* Professional mode */ 5130 break; 5131 } 5132 5133 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5134 5135 if (AES32 == hdspm->io_type) { 5136 /* No control2 register for AES32 */ 5137 #ifdef SNDRV_BIG_ENDIAN 5138 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5139 #else 5140 hdspm->control2_register = 0; 5141 #endif 5142 5143 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5144 } 5145 hdspm_compute_period_size(hdspm); 5146 5147 /* silence everything */ 5148 5149 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5150 5151 if (hdspm_is_raydat_or_aio(hdspm)) 5152 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5153 5154 /* set a default rate so that the channel map is set up. */ 5155 hdspm_set_rate(hdspm, 48000, 1); 5156 5157 return 0; 5158 } 5159 5160 5161 /*------------------------------------------------------------ 5162 interrupt 5163 ------------------------------------------------------------*/ 5164 5165 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5166 { 5167 struct hdspm *hdspm = (struct hdspm *) dev_id; 5168 unsigned int status; 5169 int i, audio, midi, schedule = 0; 5170 /* cycles_t now; */ 5171 5172 status = hdspm_read(hdspm, HDSPM_statusRegister); 5173 5174 audio = status & HDSPM_audioIRQPending; 5175 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5176 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5177 5178 /* now = get_cycles(); */ 5179 /** 5180 * LAT_2..LAT_0 period counter (win) counter (mac) 5181 * 6 4096 ~256053425 ~514672358 5182 * 5 2048 ~128024983 ~257373821 5183 * 4 1024 ~64023706 ~128718089 5184 * 3 512 ~32005945 ~64385999 5185 * 2 256 ~16003039 ~32260176 5186 * 1 128 ~7998738 ~16194507 5187 * 0 64 ~3998231 ~8191558 5188 **/ 5189 /* 5190 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5191 now-hdspm->last_interrupt, status & 0xFFC0); 5192 hdspm->last_interrupt = now; 5193 */ 5194 5195 if (!audio && !midi) 5196 return IRQ_NONE; 5197 5198 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5199 hdspm->irq_count++; 5200 5201 5202 if (audio) { 5203 if (hdspm->capture_substream) 5204 snd_pcm_period_elapsed(hdspm->capture_substream); 5205 5206 if (hdspm->playback_substream) 5207 snd_pcm_period_elapsed(hdspm->playback_substream); 5208 } 5209 5210 if (midi) { 5211 i = 0; 5212 while (i < hdspm->midiPorts) { 5213 if ((hdspm_read(hdspm, 5214 hdspm->midi[i].statusIn) & 0xff) && 5215 (status & hdspm->midi[i].irq)) { 5216 /* we disable interrupts for this input until 5217 * processing is done 5218 */ 5219 hdspm->control_register &= ~hdspm->midi[i].ie; 5220 hdspm_write(hdspm, HDSPM_controlRegister, 5221 hdspm->control_register); 5222 hdspm->midi[i].pending = 1; 5223 schedule = 1; 5224 } 5225 5226 i++; 5227 } 5228 5229 if (schedule) 5230 tasklet_hi_schedule(&hdspm->midi_tasklet); 5231 } 5232 5233 return IRQ_HANDLED; 5234 } 5235 5236 /*------------------------------------------------------------ 5237 pcm interface 5238 ------------------------------------------------------------*/ 5239 5240 5241 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5242 *substream) 5243 { 5244 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5245 return hdspm_hw_pointer(hdspm); 5246 } 5247 5248 5249 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5250 { 5251 struct snd_pcm_runtime *runtime = substream->runtime; 5252 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5253 struct snd_pcm_substream *other; 5254 5255 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5256 other = hdspm->capture_substream; 5257 else 5258 other = hdspm->playback_substream; 5259 5260 if (hdspm->running) 5261 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5262 else 5263 runtime->status->hw_ptr = 0; 5264 if (other) { 5265 struct snd_pcm_substream *s; 5266 struct snd_pcm_runtime *oruntime = other->runtime; 5267 snd_pcm_group_for_each_entry(s, substream) { 5268 if (s == other) { 5269 oruntime->status->hw_ptr = 5270 runtime->status->hw_ptr; 5271 break; 5272 } 5273 } 5274 } 5275 return 0; 5276 } 5277 5278 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5279 struct snd_pcm_hw_params *params) 5280 { 5281 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5282 int err; 5283 int i; 5284 pid_t this_pid; 5285 pid_t other_pid; 5286 5287 spin_lock_irq(&hdspm->lock); 5288 5289 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5290 this_pid = hdspm->playback_pid; 5291 other_pid = hdspm->capture_pid; 5292 } else { 5293 this_pid = hdspm->capture_pid; 5294 other_pid = hdspm->playback_pid; 5295 } 5296 5297 if (other_pid > 0 && this_pid != other_pid) { 5298 5299 /* The other stream is open, and not by the same 5300 task as this one. Make sure that the parameters 5301 that matter are the same. 5302 */ 5303 5304 if (params_rate(params) != hdspm->system_sample_rate) { 5305 spin_unlock_irq(&hdspm->lock); 5306 _snd_pcm_hw_param_setempty(params, 5307 SNDRV_PCM_HW_PARAM_RATE); 5308 return -EBUSY; 5309 } 5310 5311 if (params_period_size(params) != hdspm->period_bytes / 4) { 5312 spin_unlock_irq(&hdspm->lock); 5313 _snd_pcm_hw_param_setempty(params, 5314 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5315 return -EBUSY; 5316 } 5317 5318 } 5319 /* We're fine. */ 5320 spin_unlock_irq(&hdspm->lock); 5321 5322 /* how to make sure that the rate matches an externally-set one ? */ 5323 5324 spin_lock_irq(&hdspm->lock); 5325 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5326 if (err < 0) { 5327 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5328 spin_unlock_irq(&hdspm->lock); 5329 _snd_pcm_hw_param_setempty(params, 5330 SNDRV_PCM_HW_PARAM_RATE); 5331 return err; 5332 } 5333 spin_unlock_irq(&hdspm->lock); 5334 5335 err = hdspm_set_interrupt_interval(hdspm, 5336 params_period_size(params)); 5337 if (err < 0) { 5338 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5339 _snd_pcm_hw_param_setempty(params, 5340 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5341 return err; 5342 } 5343 5344 /* Memory allocation, takashi's method, dont know if we should 5345 * spinlock 5346 */ 5347 /* malloc all buffer even if not enabled to get sure */ 5348 /* Update for MADI rev 204: we need to allocate for all channels, 5349 * otherwise it doesn't work at 96kHz */ 5350 5351 err = 5352 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5353 if (err < 0) { 5354 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5355 return err; 5356 } 5357 5358 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5359 5360 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5361 params_channels(params)); 5362 5363 for (i = 0; i < params_channels(params); ++i) 5364 snd_hdspm_enable_out(hdspm, i, 1); 5365 5366 hdspm->playback_buffer = 5367 (unsigned char *) substream->runtime->dma_area; 5368 snd_printdd("Allocated sample buffer for playback at %p\n", 5369 hdspm->playback_buffer); 5370 } else { 5371 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5372 params_channels(params)); 5373 5374 for (i = 0; i < params_channels(params); ++i) 5375 snd_hdspm_enable_in(hdspm, i, 1); 5376 5377 hdspm->capture_buffer = 5378 (unsigned char *) substream->runtime->dma_area; 5379 snd_printdd("Allocated sample buffer for capture at %p\n", 5380 hdspm->capture_buffer); 5381 } 5382 5383 /* 5384 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5385 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5386 "playback" : "capture", 5387 snd_pcm_sgbuf_get_addr(substream, 0)); 5388 */ 5389 /* 5390 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5391 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5392 "playback" : "capture", 5393 params_rate(params), params_channels(params), 5394 params_buffer_size(params)); 5395 */ 5396 5397 5398 /* Switch to native float format if requested */ 5399 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5400 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5401 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5402 5403 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5404 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5405 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5406 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5407 5408 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5409 } 5410 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5411 5412 return 0; 5413 } 5414 5415 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5416 { 5417 int i; 5418 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5419 5420 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5421 5422 /* params_channels(params) should be enough, 5423 but to get sure in case of error */ 5424 for (i = 0; i < hdspm->max_channels_out; ++i) 5425 snd_hdspm_enable_out(hdspm, i, 0); 5426 5427 hdspm->playback_buffer = NULL; 5428 } else { 5429 for (i = 0; i < hdspm->max_channels_in; ++i) 5430 snd_hdspm_enable_in(hdspm, i, 0); 5431 5432 hdspm->capture_buffer = NULL; 5433 5434 } 5435 5436 snd_pcm_lib_free_pages(substream); 5437 5438 return 0; 5439 } 5440 5441 5442 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5443 struct snd_pcm_channel_info *info) 5444 { 5445 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5446 5447 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5448 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5449 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5450 return -EINVAL; 5451 } 5452 5453 if (hdspm->channel_map_out[info->channel] < 0) { 5454 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5455 return -EINVAL; 5456 } 5457 5458 info->offset = hdspm->channel_map_out[info->channel] * 5459 HDSPM_CHANNEL_BUFFER_BYTES; 5460 } else { 5461 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5462 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5463 return -EINVAL; 5464 } 5465 5466 if (hdspm->channel_map_in[info->channel] < 0) { 5467 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5468 return -EINVAL; 5469 } 5470 5471 info->offset = hdspm->channel_map_in[info->channel] * 5472 HDSPM_CHANNEL_BUFFER_BYTES; 5473 } 5474 5475 info->first = 0; 5476 info->step = 32; 5477 return 0; 5478 } 5479 5480 5481 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5482 unsigned int cmd, void *arg) 5483 { 5484 switch (cmd) { 5485 case SNDRV_PCM_IOCTL1_RESET: 5486 return snd_hdspm_reset(substream); 5487 5488 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5489 { 5490 struct snd_pcm_channel_info *info = arg; 5491 return snd_hdspm_channel_info(substream, info); 5492 } 5493 default: 5494 break; 5495 } 5496 5497 return snd_pcm_lib_ioctl(substream, cmd, arg); 5498 } 5499 5500 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5501 { 5502 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5503 struct snd_pcm_substream *other; 5504 int running; 5505 5506 spin_lock(&hdspm->lock); 5507 running = hdspm->running; 5508 switch (cmd) { 5509 case SNDRV_PCM_TRIGGER_START: 5510 running |= 1 << substream->stream; 5511 break; 5512 case SNDRV_PCM_TRIGGER_STOP: 5513 running &= ~(1 << substream->stream); 5514 break; 5515 default: 5516 snd_BUG(); 5517 spin_unlock(&hdspm->lock); 5518 return -EINVAL; 5519 } 5520 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5521 other = hdspm->capture_substream; 5522 else 5523 other = hdspm->playback_substream; 5524 5525 if (other) { 5526 struct snd_pcm_substream *s; 5527 snd_pcm_group_for_each_entry(s, substream) { 5528 if (s == other) { 5529 snd_pcm_trigger_done(s, substream); 5530 if (cmd == SNDRV_PCM_TRIGGER_START) 5531 running |= 1 << s->stream; 5532 else 5533 running &= ~(1 << s->stream); 5534 goto _ok; 5535 } 5536 } 5537 if (cmd == SNDRV_PCM_TRIGGER_START) { 5538 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5539 && substream->stream == 5540 SNDRV_PCM_STREAM_CAPTURE) 5541 hdspm_silence_playback(hdspm); 5542 } else { 5543 if (running && 5544 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5545 hdspm_silence_playback(hdspm); 5546 } 5547 } else { 5548 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5549 hdspm_silence_playback(hdspm); 5550 } 5551 _ok: 5552 snd_pcm_trigger_done(substream, substream); 5553 if (!hdspm->running && running) 5554 hdspm_start_audio(hdspm); 5555 else if (hdspm->running && !running) 5556 hdspm_stop_audio(hdspm); 5557 hdspm->running = running; 5558 spin_unlock(&hdspm->lock); 5559 5560 return 0; 5561 } 5562 5563 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5564 { 5565 return 0; 5566 } 5567 5568 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5569 .info = (SNDRV_PCM_INFO_MMAP | 5570 SNDRV_PCM_INFO_MMAP_VALID | 5571 SNDRV_PCM_INFO_NONINTERLEAVED | 5572 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5573 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5574 .rates = (SNDRV_PCM_RATE_32000 | 5575 SNDRV_PCM_RATE_44100 | 5576 SNDRV_PCM_RATE_48000 | 5577 SNDRV_PCM_RATE_64000 | 5578 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5579 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5580 .rate_min = 32000, 5581 .rate_max = 192000, 5582 .channels_min = 1, 5583 .channels_max = HDSPM_MAX_CHANNELS, 5584 .buffer_bytes_max = 5585 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5586 .period_bytes_min = (32 * 4), 5587 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5588 .periods_min = 2, 5589 .periods_max = 512, 5590 .fifo_size = 0 5591 }; 5592 5593 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5594 .info = (SNDRV_PCM_INFO_MMAP | 5595 SNDRV_PCM_INFO_MMAP_VALID | 5596 SNDRV_PCM_INFO_NONINTERLEAVED | 5597 SNDRV_PCM_INFO_SYNC_START), 5598 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5599 .rates = (SNDRV_PCM_RATE_32000 | 5600 SNDRV_PCM_RATE_44100 | 5601 SNDRV_PCM_RATE_48000 | 5602 SNDRV_PCM_RATE_64000 | 5603 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5604 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5605 .rate_min = 32000, 5606 .rate_max = 192000, 5607 .channels_min = 1, 5608 .channels_max = HDSPM_MAX_CHANNELS, 5609 .buffer_bytes_max = 5610 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5611 .period_bytes_min = (32 * 4), 5612 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5613 .periods_min = 2, 5614 .periods_max = 512, 5615 .fifo_size = 0 5616 }; 5617 5618 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5619 struct snd_pcm_hw_rule *rule) 5620 { 5621 struct hdspm *hdspm = rule->private; 5622 struct snd_interval *c = 5623 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5624 struct snd_interval *r = 5625 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5626 5627 if (r->min > 96000 && r->max <= 192000) { 5628 struct snd_interval t = { 5629 .min = hdspm->qs_in_channels, 5630 .max = hdspm->qs_in_channels, 5631 .integer = 1, 5632 }; 5633 return snd_interval_refine(c, &t); 5634 } else if (r->min > 48000 && r->max <= 96000) { 5635 struct snd_interval t = { 5636 .min = hdspm->ds_in_channels, 5637 .max = hdspm->ds_in_channels, 5638 .integer = 1, 5639 }; 5640 return snd_interval_refine(c, &t); 5641 } else if (r->max < 64000) { 5642 struct snd_interval t = { 5643 .min = hdspm->ss_in_channels, 5644 .max = hdspm->ss_in_channels, 5645 .integer = 1, 5646 }; 5647 return snd_interval_refine(c, &t); 5648 } 5649 5650 return 0; 5651 } 5652 5653 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5654 struct snd_pcm_hw_rule * rule) 5655 { 5656 struct hdspm *hdspm = rule->private; 5657 struct snd_interval *c = 5658 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5659 struct snd_interval *r = 5660 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5661 5662 if (r->min > 96000 && r->max <= 192000) { 5663 struct snd_interval t = { 5664 .min = hdspm->qs_out_channels, 5665 .max = hdspm->qs_out_channels, 5666 .integer = 1, 5667 }; 5668 return snd_interval_refine(c, &t); 5669 } else if (r->min > 48000 && r->max <= 96000) { 5670 struct snd_interval t = { 5671 .min = hdspm->ds_out_channels, 5672 .max = hdspm->ds_out_channels, 5673 .integer = 1, 5674 }; 5675 return snd_interval_refine(c, &t); 5676 } else if (r->max < 64000) { 5677 struct snd_interval t = { 5678 .min = hdspm->ss_out_channels, 5679 .max = hdspm->ss_out_channels, 5680 .integer = 1, 5681 }; 5682 return snd_interval_refine(c, &t); 5683 } else { 5684 } 5685 return 0; 5686 } 5687 5688 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5689 struct snd_pcm_hw_rule * rule) 5690 { 5691 struct hdspm *hdspm = rule->private; 5692 struct snd_interval *c = 5693 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5694 struct snd_interval *r = 5695 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5696 5697 if (c->min >= hdspm->ss_in_channels) { 5698 struct snd_interval t = { 5699 .min = 32000, 5700 .max = 48000, 5701 .integer = 1, 5702 }; 5703 return snd_interval_refine(r, &t); 5704 } else if (c->max <= hdspm->qs_in_channels) { 5705 struct snd_interval t = { 5706 .min = 128000, 5707 .max = 192000, 5708 .integer = 1, 5709 }; 5710 return snd_interval_refine(r, &t); 5711 } else if (c->max <= hdspm->ds_in_channels) { 5712 struct snd_interval t = { 5713 .min = 64000, 5714 .max = 96000, 5715 .integer = 1, 5716 }; 5717 return snd_interval_refine(r, &t); 5718 } 5719 5720 return 0; 5721 } 5722 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5723 struct snd_pcm_hw_rule *rule) 5724 { 5725 struct hdspm *hdspm = rule->private; 5726 struct snd_interval *c = 5727 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5728 struct snd_interval *r = 5729 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5730 5731 if (c->min >= hdspm->ss_out_channels) { 5732 struct snd_interval t = { 5733 .min = 32000, 5734 .max = 48000, 5735 .integer = 1, 5736 }; 5737 return snd_interval_refine(r, &t); 5738 } else if (c->max <= hdspm->qs_out_channels) { 5739 struct snd_interval t = { 5740 .min = 128000, 5741 .max = 192000, 5742 .integer = 1, 5743 }; 5744 return snd_interval_refine(r, &t); 5745 } else if (c->max <= hdspm->ds_out_channels) { 5746 struct snd_interval t = { 5747 .min = 64000, 5748 .max = 96000, 5749 .integer = 1, 5750 }; 5751 return snd_interval_refine(r, &t); 5752 } 5753 5754 return 0; 5755 } 5756 5757 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5758 struct snd_pcm_hw_rule *rule) 5759 { 5760 unsigned int list[3]; 5761 struct hdspm *hdspm = rule->private; 5762 struct snd_interval *c = hw_param_interval(params, 5763 SNDRV_PCM_HW_PARAM_CHANNELS); 5764 5765 list[0] = hdspm->qs_in_channels; 5766 list[1] = hdspm->ds_in_channels; 5767 list[2] = hdspm->ss_in_channels; 5768 return snd_interval_list(c, 3, list, 0); 5769 } 5770 5771 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5772 struct snd_pcm_hw_rule *rule) 5773 { 5774 unsigned int list[3]; 5775 struct hdspm *hdspm = rule->private; 5776 struct snd_interval *c = hw_param_interval(params, 5777 SNDRV_PCM_HW_PARAM_CHANNELS); 5778 5779 list[0] = hdspm->qs_out_channels; 5780 list[1] = hdspm->ds_out_channels; 5781 list[2] = hdspm->ss_out_channels; 5782 return snd_interval_list(c, 3, list, 0); 5783 } 5784 5785 5786 static unsigned int hdspm_aes32_sample_rates[] = { 5787 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5788 }; 5789 5790 static struct snd_pcm_hw_constraint_list 5791 hdspm_hw_constraints_aes32_sample_rates = { 5792 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5793 .list = hdspm_aes32_sample_rates, 5794 .mask = 0 5795 }; 5796 5797 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5798 { 5799 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5800 struct snd_pcm_runtime *runtime = substream->runtime; 5801 5802 spin_lock_irq(&hdspm->lock); 5803 5804 snd_pcm_set_sync(substream); 5805 5806 5807 runtime->hw = snd_hdspm_playback_subinfo; 5808 5809 if (hdspm->capture_substream == NULL) 5810 hdspm_stop_audio(hdspm); 5811 5812 hdspm->playback_pid = current->pid; 5813 hdspm->playback_substream = substream; 5814 5815 spin_unlock_irq(&hdspm->lock); 5816 5817 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5818 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5819 5820 switch (hdspm->io_type) { 5821 case AIO: 5822 case RayDAT: 5823 snd_pcm_hw_constraint_minmax(runtime, 5824 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5825 32, 4096); 5826 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 5827 snd_pcm_hw_constraint_minmax(runtime, 5828 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5829 16384, 16384); 5830 break; 5831 5832 default: 5833 snd_pcm_hw_constraint_minmax(runtime, 5834 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5835 64, 8192); 5836 break; 5837 } 5838 5839 if (AES32 == hdspm->io_type) { 5840 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5841 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5842 &hdspm_hw_constraints_aes32_sample_rates); 5843 } else { 5844 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5845 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5846 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5847 } 5848 5849 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5850 snd_hdspm_hw_rule_out_channels, hdspm, 5851 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5852 5853 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5854 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5855 SNDRV_PCM_HW_PARAM_RATE, -1); 5856 5857 return 0; 5858 } 5859 5860 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5861 { 5862 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5863 5864 spin_lock_irq(&hdspm->lock); 5865 5866 hdspm->playback_pid = -1; 5867 hdspm->playback_substream = NULL; 5868 5869 spin_unlock_irq(&hdspm->lock); 5870 5871 return 0; 5872 } 5873 5874 5875 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 5876 { 5877 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5878 struct snd_pcm_runtime *runtime = substream->runtime; 5879 5880 spin_lock_irq(&hdspm->lock); 5881 snd_pcm_set_sync(substream); 5882 runtime->hw = snd_hdspm_capture_subinfo; 5883 5884 if (hdspm->playback_substream == NULL) 5885 hdspm_stop_audio(hdspm); 5886 5887 hdspm->capture_pid = current->pid; 5888 hdspm->capture_substream = substream; 5889 5890 spin_unlock_irq(&hdspm->lock); 5891 5892 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5893 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5894 5895 switch (hdspm->io_type) { 5896 case AIO: 5897 case RayDAT: 5898 snd_pcm_hw_constraint_minmax(runtime, 5899 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5900 32, 4096); 5901 snd_pcm_hw_constraint_minmax(runtime, 5902 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5903 16384, 16384); 5904 break; 5905 5906 default: 5907 snd_pcm_hw_constraint_minmax(runtime, 5908 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5909 64, 8192); 5910 break; 5911 } 5912 5913 if (AES32 == hdspm->io_type) { 5914 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5915 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5916 &hdspm_hw_constraints_aes32_sample_rates); 5917 } else { 5918 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5919 snd_hdspm_hw_rule_rate_in_channels, hdspm, 5920 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5921 } 5922 5923 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5924 snd_hdspm_hw_rule_in_channels, hdspm, 5925 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5926 5927 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5928 snd_hdspm_hw_rule_in_channels_rate, hdspm, 5929 SNDRV_PCM_HW_PARAM_RATE, -1); 5930 5931 return 0; 5932 } 5933 5934 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 5935 { 5936 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5937 5938 spin_lock_irq(&hdspm->lock); 5939 5940 hdspm->capture_pid = -1; 5941 hdspm->capture_substream = NULL; 5942 5943 spin_unlock_irq(&hdspm->lock); 5944 return 0; 5945 } 5946 5947 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 5948 { 5949 /* we have nothing to initialize but the call is required */ 5950 return 0; 5951 } 5952 5953 static inline int copy_u32_le(void __user *dest, void __iomem *src) 5954 { 5955 u32 val = readl(src); 5956 return copy_to_user(dest, &val, 4); 5957 } 5958 5959 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 5960 unsigned int cmd, unsigned long arg) 5961 { 5962 void __user *argp = (void __user *)arg; 5963 struct hdspm *hdspm = hw->private_data; 5964 struct hdspm_mixer_ioctl mixer; 5965 struct hdspm_config info; 5966 struct hdspm_status status; 5967 struct hdspm_version hdspm_version; 5968 struct hdspm_peak_rms *levels; 5969 struct hdspm_ltc ltc; 5970 unsigned int statusregister; 5971 long unsigned int s; 5972 int i = 0; 5973 5974 switch (cmd) { 5975 5976 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 5977 levels = &hdspm->peak_rms; 5978 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 5979 levels->input_peaks[i] = 5980 readl(hdspm->iobase + 5981 HDSPM_MADI_INPUT_PEAK + i*4); 5982 levels->playback_peaks[i] = 5983 readl(hdspm->iobase + 5984 HDSPM_MADI_PLAYBACK_PEAK + i*4); 5985 levels->output_peaks[i] = 5986 readl(hdspm->iobase + 5987 HDSPM_MADI_OUTPUT_PEAK + i*4); 5988 5989 levels->input_rms[i] = 5990 ((uint64_t) readl(hdspm->iobase + 5991 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 5992 (uint64_t) readl(hdspm->iobase + 5993 HDSPM_MADI_INPUT_RMS_L + i*4); 5994 levels->playback_rms[i] = 5995 ((uint64_t)readl(hdspm->iobase + 5996 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 5997 (uint64_t)readl(hdspm->iobase + 5998 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 5999 levels->output_rms[i] = 6000 ((uint64_t)readl(hdspm->iobase + 6001 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6002 (uint64_t)readl(hdspm->iobase + 6003 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6004 } 6005 6006 if (hdspm->system_sample_rate > 96000) { 6007 levels->speed = qs; 6008 } else if (hdspm->system_sample_rate > 48000) { 6009 levels->speed = ds; 6010 } else { 6011 levels->speed = ss; 6012 } 6013 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6014 6015 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 6016 if (0 != s) { 6017 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 6018 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6019 */ 6020 return -EFAULT; 6021 } 6022 break; 6023 6024 case SNDRV_HDSPM_IOCTL_GET_LTC: 6025 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6026 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6027 if (i & HDSPM_TCO1_LTC_Input_valid) { 6028 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6029 HDSPM_TCO1_LTC_Format_MSB)) { 6030 case 0: 6031 ltc.format = fps_24; 6032 break; 6033 case HDSPM_TCO1_LTC_Format_LSB: 6034 ltc.format = fps_25; 6035 break; 6036 case HDSPM_TCO1_LTC_Format_MSB: 6037 ltc.format = fps_2997; 6038 break; 6039 default: 6040 ltc.format = 30; 6041 break; 6042 } 6043 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6044 ltc.frame = drop_frame; 6045 } else { 6046 ltc.frame = full_frame; 6047 } 6048 } else { 6049 ltc.format = format_invalid; 6050 ltc.frame = frame_invalid; 6051 } 6052 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6053 ltc.input_format = ntsc; 6054 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6055 ltc.input_format = pal; 6056 } else { 6057 ltc.input_format = no_video; 6058 } 6059 6060 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 6061 if (0 != s) { 6062 /* 6063 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6064 return -EFAULT; 6065 } 6066 6067 break; 6068 6069 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6070 6071 memset(&info, 0, sizeof(info)); 6072 spin_lock_irq(&hdspm->lock); 6073 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6074 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6075 6076 info.system_sample_rate = hdspm->system_sample_rate; 6077 info.autosync_sample_rate = 6078 hdspm_external_sample_rate(hdspm); 6079 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6080 info.clock_source = hdspm_clock_source(hdspm); 6081 info.autosync_ref = hdspm_autosync_ref(hdspm); 6082 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6083 info.passthru = 0; 6084 spin_unlock_irq(&hdspm->lock); 6085 if (copy_to_user(argp, &info, sizeof(info))) 6086 return -EFAULT; 6087 break; 6088 6089 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6090 memset(&status, 0, sizeof(status)); 6091 6092 status.card_type = hdspm->io_type; 6093 6094 status.autosync_source = hdspm_autosync_ref(hdspm); 6095 6096 status.card_clock = 110069313433624ULL; 6097 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6098 6099 switch (hdspm->io_type) { 6100 case MADI: 6101 case MADIface: 6102 status.card_specific.madi.sync_wc = 6103 hdspm_wc_sync_check(hdspm); 6104 status.card_specific.madi.sync_madi = 6105 hdspm_madi_sync_check(hdspm); 6106 status.card_specific.madi.sync_tco = 6107 hdspm_tco_sync_check(hdspm); 6108 status.card_specific.madi.sync_in = 6109 hdspm_sync_in_sync_check(hdspm); 6110 6111 statusregister = 6112 hdspm_read(hdspm, HDSPM_statusRegister); 6113 status.card_specific.madi.madi_input = 6114 (statusregister & HDSPM_AB_int) ? 1 : 0; 6115 status.card_specific.madi.channel_format = 6116 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6117 /* TODO: Mac driver sets it when f_s>48kHz */ 6118 status.card_specific.madi.frame_format = 0; 6119 6120 default: 6121 break; 6122 } 6123 6124 if (copy_to_user(argp, &status, sizeof(status))) 6125 return -EFAULT; 6126 6127 6128 break; 6129 6130 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6131 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6132 6133 hdspm_version.card_type = hdspm->io_type; 6134 strncpy(hdspm_version.cardname, hdspm->card_name, 6135 sizeof(hdspm_version.cardname)); 6136 hdspm_version.serial = hdspm->serial; 6137 hdspm_version.firmware_rev = hdspm->firmware_rev; 6138 hdspm_version.addons = 0; 6139 if (hdspm->tco) 6140 hdspm_version.addons |= HDSPM_ADDON_TCO; 6141 6142 if (copy_to_user(argp, &hdspm_version, 6143 sizeof(hdspm_version))) 6144 return -EFAULT; 6145 break; 6146 6147 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6148 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6149 return -EFAULT; 6150 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6151 sizeof(struct hdspm_mixer))) 6152 return -EFAULT; 6153 break; 6154 6155 default: 6156 return -EINVAL; 6157 } 6158 return 0; 6159 } 6160 6161 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6162 .open = snd_hdspm_playback_open, 6163 .close = snd_hdspm_playback_release, 6164 .ioctl = snd_hdspm_ioctl, 6165 .hw_params = snd_hdspm_hw_params, 6166 .hw_free = snd_hdspm_hw_free, 6167 .prepare = snd_hdspm_prepare, 6168 .trigger = snd_hdspm_trigger, 6169 .pointer = snd_hdspm_hw_pointer, 6170 .page = snd_pcm_sgbuf_ops_page, 6171 }; 6172 6173 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6174 .open = snd_hdspm_capture_open, 6175 .close = snd_hdspm_capture_release, 6176 .ioctl = snd_hdspm_ioctl, 6177 .hw_params = snd_hdspm_hw_params, 6178 .hw_free = snd_hdspm_hw_free, 6179 .prepare = snd_hdspm_prepare, 6180 .trigger = snd_hdspm_trigger, 6181 .pointer = snd_hdspm_hw_pointer, 6182 .page = snd_pcm_sgbuf_ops_page, 6183 }; 6184 6185 static int snd_hdspm_create_hwdep(struct snd_card *card, 6186 struct hdspm *hdspm) 6187 { 6188 struct snd_hwdep *hw; 6189 int err; 6190 6191 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6192 if (err < 0) 6193 return err; 6194 6195 hdspm->hwdep = hw; 6196 hw->private_data = hdspm; 6197 strcpy(hw->name, "HDSPM hwdep interface"); 6198 6199 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6200 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6201 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6202 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6203 6204 return 0; 6205 } 6206 6207 6208 /*------------------------------------------------------------ 6209 memory interface 6210 ------------------------------------------------------------*/ 6211 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6212 { 6213 int err; 6214 struct snd_pcm *pcm; 6215 size_t wanted; 6216 6217 pcm = hdspm->pcm; 6218 6219 wanted = HDSPM_DMA_AREA_BYTES; 6220 6221 err = 6222 snd_pcm_lib_preallocate_pages_for_all(pcm, 6223 SNDRV_DMA_TYPE_DEV_SG, 6224 snd_dma_pci_data(hdspm->pci), 6225 wanted, 6226 wanted); 6227 if (err < 0) { 6228 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6229 6230 return err; 6231 } else 6232 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6233 6234 return 0; 6235 } 6236 6237 6238 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6239 struct snd_pcm_substream *substream, 6240 unsigned int reg, int channels) 6241 { 6242 int i; 6243 6244 /* continuous memory segment */ 6245 for (i = 0; i < (channels * 16); i++) 6246 hdspm_write(hdspm, reg + 4 * i, 6247 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6248 } 6249 6250 6251 /* ------------- ALSA Devices ---------------------------- */ 6252 static int snd_hdspm_create_pcm(struct snd_card *card, 6253 struct hdspm *hdspm) 6254 { 6255 struct snd_pcm *pcm; 6256 int err; 6257 6258 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6259 if (err < 0) 6260 return err; 6261 6262 hdspm->pcm = pcm; 6263 pcm->private_data = hdspm; 6264 strcpy(pcm->name, hdspm->card_name); 6265 6266 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6267 &snd_hdspm_playback_ops); 6268 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6269 &snd_hdspm_capture_ops); 6270 6271 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6272 6273 err = snd_hdspm_preallocate_memory(hdspm); 6274 if (err < 0) 6275 return err; 6276 6277 return 0; 6278 } 6279 6280 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6281 { 6282 int i; 6283 6284 for (i = 0; i < hdspm->midiPorts; i++) 6285 snd_hdspm_flush_midi_input(hdspm, i); 6286 } 6287 6288 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6289 struct hdspm *hdspm) 6290 { 6291 int err, i; 6292 6293 snd_printdd("Create card...\n"); 6294 err = snd_hdspm_create_pcm(card, hdspm); 6295 if (err < 0) 6296 return err; 6297 6298 i = 0; 6299 while (i < hdspm->midiPorts) { 6300 err = snd_hdspm_create_midi(card, hdspm, i); 6301 if (err < 0) { 6302 return err; 6303 } 6304 i++; 6305 } 6306 6307 err = snd_hdspm_create_controls(card, hdspm); 6308 if (err < 0) 6309 return err; 6310 6311 err = snd_hdspm_create_hwdep(card, hdspm); 6312 if (err < 0) 6313 return err; 6314 6315 snd_printdd("proc init...\n"); 6316 snd_hdspm_proc_init(hdspm); 6317 6318 hdspm->system_sample_rate = -1; 6319 hdspm->last_external_sample_rate = -1; 6320 hdspm->last_internal_sample_rate = -1; 6321 hdspm->playback_pid = -1; 6322 hdspm->capture_pid = -1; 6323 hdspm->capture_substream = NULL; 6324 hdspm->playback_substream = NULL; 6325 6326 snd_printdd("Set defaults...\n"); 6327 err = snd_hdspm_set_defaults(hdspm); 6328 if (err < 0) 6329 return err; 6330 6331 snd_printdd("Update mixer controls...\n"); 6332 hdspm_update_simple_mixer_controls(hdspm); 6333 6334 snd_printdd("Initializeing complete ???\n"); 6335 6336 err = snd_card_register(card); 6337 if (err < 0) { 6338 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6339 return err; 6340 } 6341 6342 snd_printdd("... yes now\n"); 6343 6344 return 0; 6345 } 6346 6347 static int snd_hdspm_create(struct snd_card *card, 6348 struct hdspm *hdspm) 6349 { 6350 6351 struct pci_dev *pci = hdspm->pci; 6352 int err; 6353 unsigned long io_extent; 6354 6355 hdspm->irq = -1; 6356 hdspm->card = card; 6357 6358 spin_lock_init(&hdspm->lock); 6359 6360 pci_read_config_word(hdspm->pci, 6361 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6362 6363 strcpy(card->mixername, "Xilinx FPGA"); 6364 strcpy(card->driver, "HDSPM"); 6365 6366 switch (hdspm->firmware_rev) { 6367 case HDSPM_RAYDAT_REV: 6368 hdspm->io_type = RayDAT; 6369 hdspm->card_name = "RME RayDAT"; 6370 hdspm->midiPorts = 2; 6371 break; 6372 case HDSPM_AIO_REV: 6373 hdspm->io_type = AIO; 6374 hdspm->card_name = "RME AIO"; 6375 hdspm->midiPorts = 1; 6376 break; 6377 case HDSPM_MADIFACE_REV: 6378 hdspm->io_type = MADIface; 6379 hdspm->card_name = "RME MADIface"; 6380 hdspm->midiPorts = 1; 6381 break; 6382 default: 6383 if ((hdspm->firmware_rev == 0xf0) || 6384 ((hdspm->firmware_rev >= 0xe6) && 6385 (hdspm->firmware_rev <= 0xea))) { 6386 hdspm->io_type = AES32; 6387 hdspm->card_name = "RME AES32"; 6388 hdspm->midiPorts = 2; 6389 } else if ((hdspm->firmware_rev == 0xd2) || 6390 ((hdspm->firmware_rev >= 0xc8) && 6391 (hdspm->firmware_rev <= 0xcf))) { 6392 hdspm->io_type = MADI; 6393 hdspm->card_name = "RME MADI"; 6394 hdspm->midiPorts = 3; 6395 } else { 6396 snd_printk(KERN_ERR 6397 "HDSPM: unknown firmware revision %x\n", 6398 hdspm->firmware_rev); 6399 return -ENODEV; 6400 } 6401 } 6402 6403 err = pci_enable_device(pci); 6404 if (err < 0) 6405 return err; 6406 6407 pci_set_master(hdspm->pci); 6408 6409 err = pci_request_regions(pci, "hdspm"); 6410 if (err < 0) 6411 return err; 6412 6413 hdspm->port = pci_resource_start(pci, 0); 6414 io_extent = pci_resource_len(pci, 0); 6415 6416 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6417 hdspm->port, hdspm->port + io_extent - 1); 6418 6419 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6420 if (!hdspm->iobase) { 6421 snd_printk(KERN_ERR "HDSPM: " 6422 "unable to remap region 0x%lx-0x%lx\n", 6423 hdspm->port, hdspm->port + io_extent - 1); 6424 return -EBUSY; 6425 } 6426 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6427 (unsigned long)hdspm->iobase, hdspm->port, 6428 hdspm->port + io_extent - 1); 6429 6430 if (request_irq(pci->irq, snd_hdspm_interrupt, 6431 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6432 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6433 return -EBUSY; 6434 } 6435 6436 snd_printdd("use IRQ %d\n", pci->irq); 6437 6438 hdspm->irq = pci->irq; 6439 6440 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6441 sizeof(struct hdspm_mixer)); 6442 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6443 if (!hdspm->mixer) { 6444 snd_printk(KERN_ERR "HDSPM: " 6445 "unable to kmalloc Mixer memory of %d Bytes\n", 6446 (int)sizeof(struct hdspm_mixer)); 6447 return -ENOMEM; 6448 } 6449 6450 hdspm->port_names_in = NULL; 6451 hdspm->port_names_out = NULL; 6452 6453 switch (hdspm->io_type) { 6454 case AES32: 6455 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6456 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6457 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6458 6459 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6460 channel_map_aes32; 6461 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6462 channel_map_aes32; 6463 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6464 channel_map_aes32; 6465 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6466 texts_ports_aes32; 6467 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6468 texts_ports_aes32; 6469 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6470 texts_ports_aes32; 6471 6472 hdspm->max_channels_out = hdspm->max_channels_in = 6473 AES32_CHANNELS; 6474 hdspm->port_names_in = hdspm->port_names_out = 6475 texts_ports_aes32; 6476 hdspm->channel_map_in = hdspm->channel_map_out = 6477 channel_map_aes32; 6478 6479 break; 6480 6481 case MADI: 6482 case MADIface: 6483 hdspm->ss_in_channels = hdspm->ss_out_channels = 6484 MADI_SS_CHANNELS; 6485 hdspm->ds_in_channels = hdspm->ds_out_channels = 6486 MADI_DS_CHANNELS; 6487 hdspm->qs_in_channels = hdspm->qs_out_channels = 6488 MADI_QS_CHANNELS; 6489 6490 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6491 channel_map_unity_ss; 6492 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6493 channel_map_unity_ss; 6494 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6495 channel_map_unity_ss; 6496 6497 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6498 texts_ports_madi; 6499 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6500 texts_ports_madi; 6501 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6502 texts_ports_madi; 6503 break; 6504 6505 case AIO: 6506 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6507 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6508 } 6509 6510 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6511 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6512 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6513 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6514 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6515 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6516 6517 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6518 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6519 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6520 6521 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6522 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6523 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6524 6525 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6526 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6527 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6528 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6529 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6530 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6531 6532 break; 6533 6534 case RayDAT: 6535 hdspm->ss_in_channels = hdspm->ss_out_channels = 6536 RAYDAT_SS_CHANNELS; 6537 hdspm->ds_in_channels = hdspm->ds_out_channels = 6538 RAYDAT_DS_CHANNELS; 6539 hdspm->qs_in_channels = hdspm->qs_out_channels = 6540 RAYDAT_QS_CHANNELS; 6541 6542 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6543 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6544 6545 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6546 channel_map_raydat_ss; 6547 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6548 channel_map_raydat_ds; 6549 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6550 channel_map_raydat_qs; 6551 hdspm->channel_map_in = hdspm->channel_map_out = 6552 channel_map_raydat_ss; 6553 6554 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6555 texts_ports_raydat_ss; 6556 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6557 texts_ports_raydat_ds; 6558 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6559 texts_ports_raydat_qs; 6560 6561 6562 break; 6563 6564 } 6565 6566 /* TCO detection */ 6567 switch (hdspm->io_type) { 6568 case AIO: 6569 case RayDAT: 6570 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6571 HDSPM_s2_tco_detect) { 6572 hdspm->midiPorts++; 6573 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6574 GFP_KERNEL); 6575 if (NULL != hdspm->tco) { 6576 hdspm_tco_write(hdspm); 6577 } 6578 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6579 } else { 6580 hdspm->tco = NULL; 6581 } 6582 break; 6583 6584 case MADI: 6585 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6586 hdspm->midiPorts++; 6587 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6588 GFP_KERNEL); 6589 if (NULL != hdspm->tco) { 6590 hdspm_tco_write(hdspm); 6591 } 6592 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6593 } else { 6594 hdspm->tco = NULL; 6595 } 6596 break; 6597 6598 default: 6599 hdspm->tco = NULL; 6600 } 6601 6602 /* texts */ 6603 switch (hdspm->io_type) { 6604 case AES32: 6605 if (hdspm->tco) { 6606 hdspm->texts_autosync = texts_autosync_aes_tco; 6607 hdspm->texts_autosync_items = 10; 6608 } else { 6609 hdspm->texts_autosync = texts_autosync_aes; 6610 hdspm->texts_autosync_items = 9; 6611 } 6612 break; 6613 6614 case MADI: 6615 if (hdspm->tco) { 6616 hdspm->texts_autosync = texts_autosync_madi_tco; 6617 hdspm->texts_autosync_items = 4; 6618 } else { 6619 hdspm->texts_autosync = texts_autosync_madi; 6620 hdspm->texts_autosync_items = 3; 6621 } 6622 break; 6623 6624 case MADIface: 6625 6626 break; 6627 6628 case RayDAT: 6629 if (hdspm->tco) { 6630 hdspm->texts_autosync = texts_autosync_raydat_tco; 6631 hdspm->texts_autosync_items = 9; 6632 } else { 6633 hdspm->texts_autosync = texts_autosync_raydat; 6634 hdspm->texts_autosync_items = 8; 6635 } 6636 break; 6637 6638 case AIO: 6639 if (hdspm->tco) { 6640 hdspm->texts_autosync = texts_autosync_aio_tco; 6641 hdspm->texts_autosync_items = 6; 6642 } else { 6643 hdspm->texts_autosync = texts_autosync_aio; 6644 hdspm->texts_autosync_items = 5; 6645 } 6646 break; 6647 6648 } 6649 6650 tasklet_init(&hdspm->midi_tasklet, 6651 hdspm_midi_tasklet, (unsigned long) hdspm); 6652 6653 6654 if (hdspm->io_type != MADIface) { 6655 hdspm->serial = (hdspm_read(hdspm, 6656 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6657 /* id contains either a user-provided value or the default 6658 * NULL. If it's the default, we're safe to 6659 * fill card->id with the serial number. 6660 * 6661 * If the serial number is 0xFFFFFF, then we're dealing with 6662 * an old PCI revision that comes without a sane number. In 6663 * this case, we don't set card->id to avoid collisions 6664 * when running with multiple cards. 6665 */ 6666 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6667 sprintf(card->id, "HDSPMx%06x", hdspm->serial); 6668 snd_card_set_id(card, card->id); 6669 } 6670 } 6671 6672 snd_printdd("create alsa devices.\n"); 6673 err = snd_hdspm_create_alsa_devices(card, hdspm); 6674 if (err < 0) 6675 return err; 6676 6677 snd_hdspm_initialize_midi_flush(hdspm); 6678 6679 return 0; 6680 } 6681 6682 6683 static int snd_hdspm_free(struct hdspm * hdspm) 6684 { 6685 6686 if (hdspm->port) { 6687 6688 /* stop th audio, and cancel all interrupts */ 6689 hdspm->control_register &= 6690 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6691 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6692 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6693 hdspm_write(hdspm, HDSPM_controlRegister, 6694 hdspm->control_register); 6695 } 6696 6697 if (hdspm->irq >= 0) 6698 free_irq(hdspm->irq, (void *) hdspm); 6699 6700 kfree(hdspm->mixer); 6701 6702 if (hdspm->iobase) 6703 iounmap(hdspm->iobase); 6704 6705 if (hdspm->port) 6706 pci_release_regions(hdspm->pci); 6707 6708 pci_disable_device(hdspm->pci); 6709 return 0; 6710 } 6711 6712 6713 static void snd_hdspm_card_free(struct snd_card *card) 6714 { 6715 struct hdspm *hdspm = card->private_data; 6716 6717 if (hdspm) 6718 snd_hdspm_free(hdspm); 6719 } 6720 6721 6722 static int snd_hdspm_probe(struct pci_dev *pci, 6723 const struct pci_device_id *pci_id) 6724 { 6725 static int dev; 6726 struct hdspm *hdspm; 6727 struct snd_card *card; 6728 int err; 6729 6730 if (dev >= SNDRV_CARDS) 6731 return -ENODEV; 6732 if (!enable[dev]) { 6733 dev++; 6734 return -ENOENT; 6735 } 6736 6737 err = snd_card_create(index[dev], id[dev], 6738 THIS_MODULE, sizeof(struct hdspm), &card); 6739 if (err < 0) 6740 return err; 6741 6742 hdspm = card->private_data; 6743 card->private_free = snd_hdspm_card_free; 6744 hdspm->dev = dev; 6745 hdspm->pci = pci; 6746 6747 snd_card_set_dev(card, &pci->dev); 6748 6749 err = snd_hdspm_create(card, hdspm); 6750 if (err < 0) { 6751 snd_card_free(card); 6752 return err; 6753 } 6754 6755 if (hdspm->io_type != MADIface) { 6756 sprintf(card->shortname, "%s_%x", 6757 hdspm->card_name, 6758 hdspm->serial); 6759 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6760 hdspm->card_name, 6761 hdspm->serial, 6762 hdspm->port, hdspm->irq); 6763 } else { 6764 sprintf(card->shortname, "%s", hdspm->card_name); 6765 sprintf(card->longname, "%s at 0x%lx, irq %d", 6766 hdspm->card_name, hdspm->port, hdspm->irq); 6767 } 6768 6769 err = snd_card_register(card); 6770 if (err < 0) { 6771 snd_card_free(card); 6772 return err; 6773 } 6774 6775 pci_set_drvdata(pci, card); 6776 6777 dev++; 6778 return 0; 6779 } 6780 6781 static void snd_hdspm_remove(struct pci_dev *pci) 6782 { 6783 snd_card_free(pci_get_drvdata(pci)); 6784 } 6785 6786 static struct pci_driver hdspm_driver = { 6787 .name = KBUILD_MODNAME, 6788 .id_table = snd_hdspm_ids, 6789 .probe = snd_hdspm_probe, 6790 .remove = snd_hdspm_remove, 6791 }; 6792 6793 module_pci_driver(hdspm_driver); 6794