1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 42 /* ************* Register Documentation ******************************************************* 43 * 44 * Work in progress! Documentation is based on the code in this file. 45 * 46 * --------- HDSPM_controlRegister --------- 47 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 48 * :||||.||||:||||.||||:||||.||||:||||.||||: 49 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 50 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 51 * :||||.||||:||||.||||:||||.||||:||||.||||: 52 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 53 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits 54 * : . : . : . : . x: HDSPM_Start / enables audio IO 55 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave 56 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency 57 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512, 58 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192 59 * :x . : . : . x:xx . : HDSPM_FrequencyMask 60 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=?? 61 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed 62 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed 63 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask : 64 * : . : . x: . : . : HDSPM_SyncRef0 65 * : . : . x : . : . : HDSPM_SyncRef1 66 * : . : . : x . : . : <AES32> HDSPM_SyncRef2 67 * : . x : . : . : . : <AES32> HDSPM_SyncRef3 68 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn 69 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn? 70 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT 71 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax 72 * : . : . :x . : . : <MADI> HDSPM_InputSelect1 73 * : . : .x : . : . : <MADI> HDSPM_clr_tms 74 * : . : . : . x : . : <MADI> HDSPM_TX_64ch 75 * : . : . : . x : . : <AES32> HDSPM_Emphasis 76 * : . : . : .x : . : <MADI> HDSPM_AutoInp 77 * : . : . x : . : . : <MADI> HDSPM_SMUX 78 * : . : .x : . : . : <MADI> HDSPM_clr_tms 79 * : . : x. : . : . : <MADI> HDSPM_taxi_reset 80 * : . x: . : . : . : <MADI> HDSPM_LineOut 81 * : . x: . : . : . : <AES32> ?????????????????? 82 * : . : x. : . : . : <AES32> HDSPM_WCK48 83 * : . : . : .x : . : <AES32> HDSPM_Dolby 84 * : . : x . : . : . : HDSPM_Midi0InterruptEnable 85 * : . :x . : . : . : HDSPM_Midi1InterruptEnable 86 * : . : x . : . : . : HDSPM_Midi2InterruptEnable 87 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable 88 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire 89 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire 90 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire 91 * : . : . : . x : . : <AES32> HDSPM_Professional 92 * : x . : . : . : . : HDSPM_wclk_sel 93 * : . : . : . : . : 94 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 95 * :||||.||||:||||.||||:||||.||||:||||.||||: 96 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 97 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 98 * :||||.||||:||||.||||:||||.||||:||||.||||: 99 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit 100 * 101 * 102 * 103 * AIO / RayDAT only 104 * 105 * ------------ HDSPM_WR_SETTINGS ---------- 106 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 107 * :1098.7654:3210.9876:5432.1098:7654.3210: 108 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 109 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 110 * :||||.||||:||||.||||:||||.||||:||||.||||: 111 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 112 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave 113 * : . : . : . : . x : HDSPM_c0_SyncRef0 114 * : . : . : . : . x : HDSPM_c0_SyncRef1 115 * : . : . : . : .x : HDSPM_c0_SyncRef2 116 * : . : . : . : x. : HDSPM_c0_SyncRef3 117 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask: 118 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4, 119 * : . : . : . : . : 9:TCO, 10:SyncIn 120 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT, 121 * : . : . : . : . : 9:TCO, 10:SyncIn 122 * : . : . : . : . : 123 * : . : . : . : . : 124 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 125 * :1098.7654:3210.9876:5432.1098:7654.3210: 126 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 127 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 128 * :||||.||||:||||.||||:||||.||||:||||.||||: 129 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 130 * 131 */ 132 #include <linux/init.h> 133 #include <linux/delay.h> 134 #include <linux/interrupt.h> 135 #include <linux/module.h> 136 #include <linux/slab.h> 137 #include <linux/pci.h> 138 #include <linux/math64.h> 139 #include <asm/io.h> 140 141 #include <sound/core.h> 142 #include <sound/control.h> 143 #include <sound/pcm.h> 144 #include <sound/pcm_params.h> 145 #include <sound/info.h> 146 #include <sound/asoundef.h> 147 #include <sound/rawmidi.h> 148 #include <sound/hwdep.h> 149 #include <sound/initval.h> 150 151 #include <sound/hdspm.h> 152 153 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 154 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 155 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 156 157 module_param_array(index, int, NULL, 0444); 158 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 159 160 module_param_array(id, charp, NULL, 0444); 161 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 162 163 module_param_array(enable, bool, NULL, 0444); 164 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 165 166 167 MODULE_AUTHOR 168 ( 169 "Winfried Ritsch <ritsch_AT_iem.at>, " 170 "Paul Davis <paul@linuxaudiosystems.com>, " 171 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 172 "Remy Bruno <remy.bruno@trinnov.com>, " 173 "Florian Faber <faberman@linuxproaudio.org>, " 174 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 175 ); 176 MODULE_DESCRIPTION("RME HDSPM"); 177 MODULE_LICENSE("GPL"); 178 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 179 180 /* --- Write registers. --- 181 These are defined as byte-offsets from the iobase value. */ 182 183 #define HDSPM_WR_SETTINGS 0 184 #define HDSPM_outputBufferAddress 32 185 #define HDSPM_inputBufferAddress 36 186 #define HDSPM_controlRegister 64 187 #define HDSPM_interruptConfirmation 96 188 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 189 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */ 190 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 191 #define HDSPM_midiDataOut1 356 192 #define HDSPM_eeprom_wr 384 /* for AES32 */ 193 194 /* DMA enable for 64 channels, only Bit 0 is relevant */ 195 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 196 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 197 198 /* 16 page addresses for each of the 64 channels DMA buffer in and out 199 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 200 #define HDSPM_pageAddressBufferOut 8192 201 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 202 203 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 204 205 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 206 207 /* --- Read registers. --- 208 These are defined as byte-offsets from the iobase value */ 209 #define HDSPM_statusRegister 0 210 /*#define HDSPM_statusRegister2 96 */ 211 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 212 * offset 192, for AES32 *and* MADI 213 * => need to check that offset 192 is working on MADI */ 214 #define HDSPM_statusRegister2 192 215 #define HDSPM_timecodeRegister 128 216 217 /* AIO, RayDAT */ 218 #define HDSPM_RD_STATUS_0 0 219 #define HDSPM_RD_STATUS_1 64 220 #define HDSPM_RD_STATUS_2 128 221 #define HDSPM_RD_STATUS_3 192 222 223 #define HDSPM_RD_TCO 256 224 #define HDSPM_RD_PLL_FREQ 512 225 #define HDSPM_WR_TCO 128 226 227 #define HDSPM_TCO1_TCO_lock 0x00000001 228 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 229 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 230 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 231 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 232 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 233 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 234 235 #define HDSPM_TCO1_set_TC 0x00000100 236 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 237 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 238 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 239 240 #define HDSPM_TCO2_TC_run 0x00010000 241 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 242 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 243 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 244 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 245 #define HDSPM_TCO2_set_jam_sync 0x00200000 246 #define HDSPM_TCO2_set_flywheel 0x00400000 247 248 #define HDSPM_TCO2_set_01_4 0x01000000 249 #define HDSPM_TCO2_set_pull_down 0x02000000 250 #define HDSPM_TCO2_set_pull_up 0x04000000 251 #define HDSPM_TCO2_set_freq 0x08000000 252 #define HDSPM_TCO2_set_term_75R 0x10000000 253 #define HDSPM_TCO2_set_input_LSB 0x20000000 254 #define HDSPM_TCO2_set_input_MSB 0x40000000 255 #define HDSPM_TCO2_set_freq_from_app 0x80000000 256 257 258 #define HDSPM_midiDataOut0 352 259 #define HDSPM_midiDataOut1 356 260 #define HDSPM_midiDataOut2 368 261 262 #define HDSPM_midiDataIn0 360 263 #define HDSPM_midiDataIn1 364 264 #define HDSPM_midiDataIn2 372 265 #define HDSPM_midiDataIn3 376 266 267 /* status is data bytes in MIDI-FIFO (0-128) */ 268 #define HDSPM_midiStatusOut0 384 269 #define HDSPM_midiStatusOut1 388 270 #define HDSPM_midiStatusOut2 400 271 272 #define HDSPM_midiStatusIn0 392 273 #define HDSPM_midiStatusIn1 396 274 #define HDSPM_midiStatusIn2 404 275 #define HDSPM_midiStatusIn3 408 276 277 278 /* the meters are regular i/o-mapped registers, but offset 279 considerably from the rest. the peak registers are reset 280 when read; the least-significant 4 bits are full-scale counters; 281 the actual peak value is in the most-significant 24 bits. 282 */ 283 284 #define HDSPM_MADI_INPUT_PEAK 4096 285 #define HDSPM_MADI_PLAYBACK_PEAK 4352 286 #define HDSPM_MADI_OUTPUT_PEAK 4608 287 288 #define HDSPM_MADI_INPUT_RMS_L 6144 289 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 290 #define HDSPM_MADI_OUTPUT_RMS_L 6656 291 292 #define HDSPM_MADI_INPUT_RMS_H 7168 293 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 294 #define HDSPM_MADI_OUTPUT_RMS_H 7680 295 296 /* --- Control Register bits --------- */ 297 #define HDSPM_Start (1<<0) /* start engine */ 298 299 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 300 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 301 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 302 303 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 304 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 305 register [RayDAT, AIO] */ 306 307 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 308 309 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 310 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 311 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 312 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 313 314 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 315 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 316 56channelMODE=0 */ /* MADI ONLY*/ 317 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 318 319 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 320 0=off, 1=on */ /* MADI ONLY */ 321 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 322 323 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 324 * -- MADI ONLY 325 */ 326 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 327 328 #define HDSPM_SyncRef2 (1<<13) 329 #define HDSPM_SyncRef3 (1<<25) 330 331 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 332 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 333 AES additional bits in 334 lower 5 Audiodatabits ??? */ 335 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 336 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 337 338 #define HDSPM_Midi0InterruptEnable 0x0400000 339 #define HDSPM_Midi1InterruptEnable 0x0800000 340 #define HDSPM_Midi2InterruptEnable 0x0200000 341 #define HDSPM_Midi3InterruptEnable 0x4000000 342 343 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 344 #define HDSPe_FLOAT_FORMAT 0x2000000 345 346 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 347 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 348 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 349 350 #define HDSPM_wclk_sel (1<<30) 351 352 /* additional control register bits for AIO*/ 353 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 354 #define HDSPM_c0_Input0 0x1000 355 #define HDSPM_c0_Input1 0x2000 356 #define HDSPM_c0_Spdif_Opt 0x4000 357 #define HDSPM_c0_Pro 0x8000 358 #define HDSPM_c0_clr_tms 0x10000 359 #define HDSPM_c0_AEB1 0x20000 360 #define HDSPM_c0_AEB2 0x40000 361 #define HDSPM_c0_LineOut 0x80000 362 #define HDSPM_c0_AD_GAIN0 0x100000 363 #define HDSPM_c0_AD_GAIN1 0x200000 364 #define HDSPM_c0_DA_GAIN0 0x400000 365 #define HDSPM_c0_DA_GAIN1 0x800000 366 #define HDSPM_c0_PH_GAIN0 0x1000000 367 #define HDSPM_c0_PH_GAIN1 0x2000000 368 #define HDSPM_c0_Sym6db 0x4000000 369 370 371 /* --- bit helper defines */ 372 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 373 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 374 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 375 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 376 #define HDSPM_InputOptical 0 377 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 378 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 379 HDSPM_SyncRef2|HDSPM_SyncRef3) 380 381 #define HDSPM_c0_SyncRef0 0x2 382 #define HDSPM_c0_SyncRef1 0x4 383 #define HDSPM_c0_SyncRef2 0x8 384 #define HDSPM_c0_SyncRef3 0x10 385 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 386 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 387 388 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 389 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 390 #define HDSPM_SYNC_FROM_TCO 2 391 #define HDSPM_SYNC_FROM_SYNC_IN 3 392 393 #define HDSPM_Frequency32KHz HDSPM_Frequency0 394 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 395 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 396 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 397 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 398 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 399 HDSPM_Frequency0) 400 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 401 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 402 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 403 HDSPM_Frequency0) 404 405 406 /* Synccheck Status */ 407 #define HDSPM_SYNC_CHECK_NO_LOCK 0 408 #define HDSPM_SYNC_CHECK_LOCK 1 409 #define HDSPM_SYNC_CHECK_SYNC 2 410 411 /* AutoSync References - used by "autosync_ref" control switch */ 412 #define HDSPM_AUTOSYNC_FROM_WORD 0 413 #define HDSPM_AUTOSYNC_FROM_MADI 1 414 #define HDSPM_AUTOSYNC_FROM_TCO 2 415 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 416 #define HDSPM_AUTOSYNC_FROM_NONE 4 417 418 /* Possible sources of MADI input */ 419 #define HDSPM_OPTICAL 0 /* optical */ 420 #define HDSPM_COAXIAL 1 /* BNC */ 421 422 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 423 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 424 425 #define hdspm_encode_in(x) (((x)&0x3)<<14) 426 #define hdspm_decode_in(x) (((x)>>14)&0x3) 427 428 /* --- control2 register bits --- */ 429 #define HDSPM_TMS (1<<0) 430 #define HDSPM_TCK (1<<1) 431 #define HDSPM_TDI (1<<2) 432 #define HDSPM_JTAG (1<<3) 433 #define HDSPM_PWDN (1<<4) 434 #define HDSPM_PROGRAM (1<<5) 435 #define HDSPM_CONFIG_MODE_0 (1<<6) 436 #define HDSPM_CONFIG_MODE_1 (1<<7) 437 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 438 #define HDSPM_BIGENDIAN_MODE (1<<9) 439 #define HDSPM_RD_MULTIPLE (1<<10) 440 441 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 442 that do not conflict with specific bits for AES32 seem to be valid also 443 for the AES32 444 */ 445 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 446 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 447 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 448 * (like inp0) 449 */ 450 451 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 452 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 453 454 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/ 455 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/ 456 457 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */ 458 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */ 459 460 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 461 /* since 64byte accurate, last 6 bits are not used */ 462 463 464 465 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 466 467 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 468 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 469 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 470 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 471 472 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 473 * Interrupt 474 */ 475 #define HDSPM_tco_detect 0x08000000 476 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */ 477 478 #define HDSPM_s2_tco_detect 0x00000040 479 #define HDSPM_s2_AEBO_D 0x00000080 480 #define HDSPM_s2_AEBI_D 0x00000100 481 482 483 #define HDSPM_midi0IRQPending 0x40000000 484 #define HDSPM_midi1IRQPending 0x80000000 485 #define HDSPM_midi2IRQPending 0x20000000 486 #define HDSPM_midi2IRQPendingAES 0x00000020 487 #define HDSPM_midi3IRQPending 0x00200000 488 489 /* --- status bit helpers */ 490 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 491 HDSPM_madiFreq2|HDSPM_madiFreq3) 492 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 493 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 494 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 495 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 496 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 497 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 498 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 499 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 500 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 501 502 /* Status2 Register bits */ /* MADI ONLY */ 503 504 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 505 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 506 #define HDSPM_version2 (1<<2) 507 508 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 509 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 510 511 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 512 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 513 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 514 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 515 516 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 517 #define HDSPM_SyncRef1 0x20000 518 519 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 520 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 521 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 522 523 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 524 525 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 526 HDSPM_wc_freq3) 527 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 528 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 529 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 530 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 531 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 532 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 533 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 534 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 535 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 536 537 #define HDSPM_status1_F_0 0x0400000 538 #define HDSPM_status1_F_1 0x0800000 539 #define HDSPM_status1_F_2 0x1000000 540 #define HDSPM_status1_F_3 0x2000000 541 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 542 543 544 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 545 HDSPM_SelSyncRef2) 546 #define HDSPM_SelSyncRef_WORD 0 547 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 548 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 549 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 550 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 551 HDSPM_SelSyncRef2) 552 553 /* 554 For AES32, bits for status, status2 and timecode are different 555 */ 556 /* status */ 557 #define HDSPM_AES32_wcLock 0x0200000 558 #define HDSPM_AES32_wcSync 0x0100000 559 #define HDSPM_AES32_wcFreq_bit 22 560 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 561 HDSPM_bit2freq */ 562 #define HDSPM_AES32_syncref_bit 16 563 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 564 565 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 566 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 567 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 568 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 569 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 570 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 571 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 572 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 573 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 574 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9 575 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10 576 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11 577 578 /* status2 */ 579 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 580 #define HDSPM_LockAES 0x80 581 #define HDSPM_LockAES1 0x80 582 #define HDSPM_LockAES2 0x40 583 #define HDSPM_LockAES3 0x20 584 #define HDSPM_LockAES4 0x10 585 #define HDSPM_LockAES5 0x8 586 #define HDSPM_LockAES6 0x4 587 #define HDSPM_LockAES7 0x2 588 #define HDSPM_LockAES8 0x1 589 /* 590 Timecode 591 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 592 AES i+1 593 bits 3210 594 0001 32kHz 595 0010 44.1kHz 596 0011 48kHz 597 0100 64kHz 598 0101 88.2kHz 599 0110 96kHz 600 0111 128kHz 601 1000 176.4kHz 602 1001 192kHz 603 NB: Timecode register doesn't seem to work on AES32 card revision 230 604 */ 605 606 /* Mixer Values */ 607 #define UNITY_GAIN 32768 /* = 65536/2 */ 608 #define MINUS_INFINITY_GAIN 0 609 610 /* Number of channels for different Speed Modes */ 611 #define MADI_SS_CHANNELS 64 612 #define MADI_DS_CHANNELS 32 613 #define MADI_QS_CHANNELS 16 614 615 #define RAYDAT_SS_CHANNELS 36 616 #define RAYDAT_DS_CHANNELS 20 617 #define RAYDAT_QS_CHANNELS 12 618 619 #define AIO_IN_SS_CHANNELS 14 620 #define AIO_IN_DS_CHANNELS 10 621 #define AIO_IN_QS_CHANNELS 8 622 #define AIO_OUT_SS_CHANNELS 16 623 #define AIO_OUT_DS_CHANNELS 12 624 #define AIO_OUT_QS_CHANNELS 10 625 626 #define AES32_CHANNELS 16 627 628 /* the size of a substream (1 mono data stream) */ 629 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 630 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 631 632 /* the size of the area we need to allocate for DMA transfers. the 633 size is the same regardless of the number of channels, and 634 also the latency to use. 635 for one direction !!! 636 */ 637 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 638 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 639 640 #define HDSPM_RAYDAT_REV 211 641 #define HDSPM_AIO_REV 212 642 #define HDSPM_MADIFACE_REV 213 643 644 /* speed factor modes */ 645 #define HDSPM_SPEED_SINGLE 0 646 #define HDSPM_SPEED_DOUBLE 1 647 #define HDSPM_SPEED_QUAD 2 648 649 /* names for speed modes */ 650 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 651 652 static const char *const texts_autosync_aes_tco[] = { "Word Clock", 653 "AES1", "AES2", "AES3", "AES4", 654 "AES5", "AES6", "AES7", "AES8", 655 "TCO", "Sync In" 656 }; 657 static const char *const texts_autosync_aes[] = { "Word Clock", 658 "AES1", "AES2", "AES3", "AES4", 659 "AES5", "AES6", "AES7", "AES8", 660 "Sync In" 661 }; 662 static const char *const texts_autosync_madi_tco[] = { "Word Clock", 663 "MADI", "TCO", "Sync In" }; 664 static const char *const texts_autosync_madi[] = { "Word Clock", 665 "MADI", "Sync In" }; 666 667 static const char *const texts_autosync_raydat_tco[] = { 668 "Word Clock", 669 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 670 "AES", "SPDIF", "TCO", "Sync In" 671 }; 672 static const char *const texts_autosync_raydat[] = { 673 "Word Clock", 674 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 675 "AES", "SPDIF", "Sync In" 676 }; 677 static const char *const texts_autosync_aio_tco[] = { 678 "Word Clock", 679 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 680 }; 681 static const char *const texts_autosync_aio[] = { "Word Clock", 682 "ADAT", "AES", "SPDIF", "Sync In" }; 683 684 static const char *const texts_freq[] = { 685 "No Lock", 686 "32 kHz", 687 "44.1 kHz", 688 "48 kHz", 689 "64 kHz", 690 "88.2 kHz", 691 "96 kHz", 692 "128 kHz", 693 "176.4 kHz", 694 "192 kHz" 695 }; 696 697 static char *texts_ports_madi[] = { 698 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 699 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 700 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 701 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 702 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 703 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 704 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 705 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 706 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 707 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 708 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 709 }; 710 711 712 static char *texts_ports_raydat_ss[] = { 713 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 714 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 715 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 716 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 717 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 718 "ADAT4.7", "ADAT4.8", 719 "AES.L", "AES.R", 720 "SPDIF.L", "SPDIF.R" 721 }; 722 723 static char *texts_ports_raydat_ds[] = { 724 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 725 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 726 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 727 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 728 "AES.L", "AES.R", 729 "SPDIF.L", "SPDIF.R" 730 }; 731 732 static char *texts_ports_raydat_qs[] = { 733 "ADAT1.1", "ADAT1.2", 734 "ADAT2.1", "ADAT2.2", 735 "ADAT3.1", "ADAT3.2", 736 "ADAT4.1", "ADAT4.2", 737 "AES.L", "AES.R", 738 "SPDIF.L", "SPDIF.R" 739 }; 740 741 742 static char *texts_ports_aio_in_ss[] = { 743 "Analogue.L", "Analogue.R", 744 "AES.L", "AES.R", 745 "SPDIF.L", "SPDIF.R", 746 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 747 "ADAT.7", "ADAT.8", 748 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 749 }; 750 751 static char *texts_ports_aio_out_ss[] = { 752 "Analogue.L", "Analogue.R", 753 "AES.L", "AES.R", 754 "SPDIF.L", "SPDIF.R", 755 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 756 "ADAT.7", "ADAT.8", 757 "Phone.L", "Phone.R", 758 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 759 }; 760 761 static char *texts_ports_aio_in_ds[] = { 762 "Analogue.L", "Analogue.R", 763 "AES.L", "AES.R", 764 "SPDIF.L", "SPDIF.R", 765 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 766 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 767 }; 768 769 static char *texts_ports_aio_out_ds[] = { 770 "Analogue.L", "Analogue.R", 771 "AES.L", "AES.R", 772 "SPDIF.L", "SPDIF.R", 773 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 774 "Phone.L", "Phone.R", 775 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 776 }; 777 778 static char *texts_ports_aio_in_qs[] = { 779 "Analogue.L", "Analogue.R", 780 "AES.L", "AES.R", 781 "SPDIF.L", "SPDIF.R", 782 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 783 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 784 }; 785 786 static char *texts_ports_aio_out_qs[] = { 787 "Analogue.L", "Analogue.R", 788 "AES.L", "AES.R", 789 "SPDIF.L", "SPDIF.R", 790 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 791 "Phone.L", "Phone.R", 792 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 793 }; 794 795 static char *texts_ports_aes32[] = { 796 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 797 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 798 "AES.15", "AES.16" 799 }; 800 801 /* These tables map the ALSA channels 1..N to the channels that we 802 need to use in order to find the relevant channel buffer. RME 803 refers to this kind of mapping as between "the ADAT channel and 804 the DMA channel." We index it using the logical audio channel, 805 and the value is the DMA channel (i.e. channel buffer number) 806 where the data for that channel can be read/written from/to. 807 */ 808 809 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 810 0, 1, 2, 3, 4, 5, 6, 7, 811 8, 9, 10, 11, 12, 13, 14, 15, 812 16, 17, 18, 19, 20, 21, 22, 23, 813 24, 25, 26, 27, 28, 29, 30, 31, 814 32, 33, 34, 35, 36, 37, 38, 39, 815 40, 41, 42, 43, 44, 45, 46, 47, 816 48, 49, 50, 51, 52, 53, 54, 55, 817 56, 57, 58, 59, 60, 61, 62, 63 818 }; 819 820 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 821 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 822 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 823 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 824 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 825 0, 1, /* AES */ 826 2, 3, /* SPDIF */ 827 -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1, 831 }; 832 833 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 834 4, 5, 6, 7, /* ADAT 1 */ 835 8, 9, 10, 11, /* ADAT 2 */ 836 12, 13, 14, 15, /* ADAT 3 */ 837 16, 17, 18, 19, /* ADAT 4 */ 838 0, 1, /* AES */ 839 2, 3, /* SPDIF */ 840 -1, -1, -1, -1, 841 -1, -1, -1, -1, -1, -1, -1, -1, 842 -1, -1, -1, -1, -1, -1, -1, -1, 843 -1, -1, -1, -1, -1, -1, -1, -1, 844 -1, -1, -1, -1, -1, -1, -1, -1, 845 -1, -1, -1, -1, -1, -1, -1, -1, 846 }; 847 848 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 849 4, 5, /* ADAT 1 */ 850 6, 7, /* ADAT 2 */ 851 8, 9, /* ADAT 3 */ 852 10, 11, /* ADAT 4 */ 853 0, 1, /* AES */ 854 2, 3, /* SPDIF */ 855 -1, -1, -1, -1, 856 -1, -1, -1, -1, -1, -1, -1, -1, 857 -1, -1, -1, -1, -1, -1, -1, -1, 858 -1, -1, -1, -1, -1, -1, -1, -1, 859 -1, -1, -1, -1, -1, -1, -1, -1, 860 -1, -1, -1, -1, -1, -1, -1, -1, 861 -1, -1, -1, -1, -1, -1, -1, -1, 862 }; 863 864 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 865 0, 1, /* line in */ 866 8, 9, /* aes in, */ 867 10, 11, /* spdif in */ 868 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 869 2, 3, 4, 5, /* AEB */ 870 -1, -1, -1, -1, -1, -1, 871 -1, -1, -1, -1, -1, -1, -1, -1, 872 -1, -1, -1, -1, -1, -1, -1, -1, 873 -1, -1, -1, -1, -1, -1, -1, -1, 874 -1, -1, -1, -1, -1, -1, -1, -1, 875 -1, -1, -1, -1, -1, -1, -1, -1, 876 }; 877 878 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 879 0, 1, /* line out */ 880 8, 9, /* aes out */ 881 10, 11, /* spdif out */ 882 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 883 6, 7, /* phone out */ 884 2, 3, 4, 5, /* AEB */ 885 -1, -1, -1, -1, 886 -1, -1, -1, -1, -1, -1, -1, -1, 887 -1, -1, -1, -1, -1, -1, -1, -1, 888 -1, -1, -1, -1, -1, -1, -1, -1, 889 -1, -1, -1, -1, -1, -1, -1, -1, 890 -1, -1, -1, -1, -1, -1, -1, -1, 891 }; 892 893 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 894 0, 1, /* line in */ 895 8, 9, /* aes in */ 896 10, 11, /* spdif in */ 897 12, 14, 16, 18, /* adat in */ 898 2, 3, 4, 5, /* AEB */ 899 -1, -1, 900 -1, -1, -1, -1, -1, -1, -1, -1, 901 -1, -1, -1, -1, -1, -1, -1, -1, 902 -1, -1, -1, -1, -1, -1, -1, -1, 903 -1, -1, -1, -1, -1, -1, -1, -1, 904 -1, -1, -1, -1, -1, -1, -1, -1, 905 -1, -1, -1, -1, -1, -1, -1, -1 906 }; 907 908 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 909 0, 1, /* line out */ 910 8, 9, /* aes out */ 911 10, 11, /* spdif out */ 912 12, 14, 16, 18, /* adat out */ 913 6, 7, /* phone out */ 914 2, 3, 4, 5, /* AEB */ 915 -1, -1, -1, -1, -1, -1, -1, -1, 916 -1, -1, -1, -1, -1, -1, -1, -1, 917 -1, -1, -1, -1, -1, -1, -1, -1, 918 -1, -1, -1, -1, -1, -1, -1, -1, 919 -1, -1, -1, -1, -1, -1, -1, -1, 920 -1, -1, -1, -1, -1, -1, -1, -1 921 }; 922 923 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 924 0, 1, /* line in */ 925 8, 9, /* aes in */ 926 10, 11, /* spdif in */ 927 12, 16, /* adat in */ 928 2, 3, 4, 5, /* AEB */ 929 -1, -1, -1, -1, 930 -1, -1, -1, -1, -1, -1, -1, -1, 931 -1, -1, -1, -1, -1, -1, -1, -1, 932 -1, -1, -1, -1, -1, -1, -1, -1, 933 -1, -1, -1, -1, -1, -1, -1, -1, 934 -1, -1, -1, -1, -1, -1, -1, -1, 935 -1, -1, -1, -1, -1, -1, -1, -1 936 }; 937 938 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 939 0, 1, /* line out */ 940 8, 9, /* aes out */ 941 10, 11, /* spdif out */ 942 12, 16, /* adat out */ 943 6, 7, /* phone out */ 944 2, 3, 4, 5, /* AEB */ 945 -1, -1, 946 -1, -1, -1, -1, -1, -1, -1, -1, 947 -1, -1, -1, -1, -1, -1, -1, -1, 948 -1, -1, -1, -1, -1, -1, -1, -1, 949 -1, -1, -1, -1, -1, -1, -1, -1, 950 -1, -1, -1, -1, -1, -1, -1, -1, 951 -1, -1, -1, -1, -1, -1, -1, -1 952 }; 953 954 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 955 0, 1, 2, 3, 4, 5, 6, 7, 956 8, 9, 10, 11, 12, 13, 14, 15, 957 -1, -1, -1, -1, -1, -1, -1, -1, 958 -1, -1, -1, -1, -1, -1, -1, -1, 959 -1, -1, -1, -1, -1, -1, -1, -1, 960 -1, -1, -1, -1, -1, -1, -1, -1, 961 -1, -1, -1, -1, -1, -1, -1, -1, 962 -1, -1, -1, -1, -1, -1, -1, -1 963 }; 964 965 struct hdspm_midi { 966 struct hdspm *hdspm; 967 int id; 968 struct snd_rawmidi *rmidi; 969 struct snd_rawmidi_substream *input; 970 struct snd_rawmidi_substream *output; 971 char istimer; /* timer in use */ 972 struct timer_list timer; 973 spinlock_t lock; 974 int pending; 975 int dataIn; 976 int statusIn; 977 int dataOut; 978 int statusOut; 979 int ie; 980 int irq; 981 }; 982 983 struct hdspm_tco { 984 int input; /* 0: LTC, 1:Video, 2: WC*/ 985 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */ 986 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */ 987 int samplerate; /* 0=44.1, 1=48, 2= freq from app */ 988 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/ 989 int term; /* 0 = off, 1 = on */ 990 }; 991 992 struct hdspm { 993 spinlock_t lock; 994 /* only one playback and/or capture stream */ 995 struct snd_pcm_substream *capture_substream; 996 struct snd_pcm_substream *playback_substream; 997 998 char *card_name; /* for procinfo */ 999 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 1000 1001 uint8_t io_type; 1002 1003 int monitor_outs; /* set up monitoring outs init flag */ 1004 1005 u32 control_register; /* cached value */ 1006 u32 control2_register; /* cached value */ 1007 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */ 1008 1009 struct hdspm_midi midi[4]; 1010 struct tasklet_struct midi_tasklet; 1011 1012 size_t period_bytes; 1013 unsigned char ss_in_channels; 1014 unsigned char ds_in_channels; 1015 unsigned char qs_in_channels; 1016 unsigned char ss_out_channels; 1017 unsigned char ds_out_channels; 1018 unsigned char qs_out_channels; 1019 1020 unsigned char max_channels_in; 1021 unsigned char max_channels_out; 1022 1023 signed char *channel_map_in; 1024 signed char *channel_map_out; 1025 1026 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 1027 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 1028 1029 char **port_names_in; 1030 char **port_names_out; 1031 1032 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 1033 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 1034 1035 unsigned char *playback_buffer; /* suitably aligned address */ 1036 unsigned char *capture_buffer; /* suitably aligned address */ 1037 1038 pid_t capture_pid; /* process id which uses capture */ 1039 pid_t playback_pid; /* process id which uses capture */ 1040 int running; /* running status */ 1041 1042 int last_external_sample_rate; /* samplerate mystic ... */ 1043 int last_internal_sample_rate; 1044 int system_sample_rate; 1045 1046 int dev; /* Hardware vars... */ 1047 int irq; 1048 unsigned long port; 1049 void __iomem *iobase; 1050 1051 int irq_count; /* for debug */ 1052 int midiPorts; 1053 1054 struct snd_card *card; /* one card */ 1055 struct snd_pcm *pcm; /* has one pcm */ 1056 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 1057 struct pci_dev *pci; /* and an pci info */ 1058 1059 /* Mixer vars */ 1060 /* fast alsa mixer */ 1061 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 1062 /* but input to much, so not used */ 1063 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 1064 /* full mixer accessible over mixer ioctl or hwdep-device */ 1065 struct hdspm_mixer *mixer; 1066 1067 struct hdspm_tco *tco; /* NULL if no TCO detected */ 1068 1069 const char *const *texts_autosync; 1070 int texts_autosync_items; 1071 1072 cycles_t last_interrupt; 1073 1074 unsigned int serial; 1075 1076 struct hdspm_peak_rms peak_rms; 1077 }; 1078 1079 1080 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 1081 { 1082 .vendor = PCI_VENDOR_ID_XILINX, 1083 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 1084 .subvendor = PCI_ANY_ID, 1085 .subdevice = PCI_ANY_ID, 1086 .class = 0, 1087 .class_mask = 0, 1088 .driver_data = 0}, 1089 {0,} 1090 }; 1091 1092 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 1093 1094 /* prototypes */ 1095 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 1096 struct hdspm *hdspm); 1097 static int snd_hdspm_create_pcm(struct snd_card *card, 1098 struct hdspm *hdspm); 1099 1100 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 1101 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 1102 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 1103 static int hdspm_autosync_ref(struct hdspm *hdspm); 1104 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out); 1105 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 1106 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1107 static void hdspm_set_sgbuf(struct hdspm *hdspm, 1108 struct snd_pcm_substream *substream, 1109 unsigned int reg, int channels); 1110 1111 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx); 1112 static int hdspm_wc_sync_check(struct hdspm *hdspm); 1113 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1114 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1115 1116 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index); 1117 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm); 1118 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm); 1119 1120 1121 1122 static inline int HDSPM_bit2freq(int n) 1123 { 1124 static const int bit2freq_tab[] = { 1125 0, 32000, 44100, 48000, 64000, 88200, 1126 96000, 128000, 176400, 192000 }; 1127 if (n < 1 || n > 9) 1128 return 0; 1129 return bit2freq_tab[n]; 1130 } 1131 1132 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1133 { 1134 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1135 } 1136 1137 1138 /* Write/read to/from HDSPM with Adresses in Bytes 1139 not words but only 32Bit writes are allowed */ 1140 1141 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1142 unsigned int val) 1143 { 1144 writel(val, hdspm->iobase + reg); 1145 } 1146 1147 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1148 { 1149 return readl(hdspm->iobase + reg); 1150 } 1151 1152 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1153 mixer is write only on hardware so we have to cache him for read 1154 each fader is a u32, but uses only the first 16 bit */ 1155 1156 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1157 unsigned int in) 1158 { 1159 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1160 return 0; 1161 1162 return hdspm->mixer->ch[chan].in[in]; 1163 } 1164 1165 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1166 unsigned int pb) 1167 { 1168 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1169 return 0; 1170 return hdspm->mixer->ch[chan].pb[pb]; 1171 } 1172 1173 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1174 unsigned int in, unsigned short data) 1175 { 1176 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1177 return -1; 1178 1179 hdspm_write(hdspm, 1180 HDSPM_MADI_mixerBase + 1181 ((in + 128 * chan) * sizeof(u32)), 1182 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1183 return 0; 1184 } 1185 1186 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1187 unsigned int pb, unsigned short data) 1188 { 1189 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1190 return -1; 1191 1192 hdspm_write(hdspm, 1193 HDSPM_MADI_mixerBase + 1194 ((64 + pb + 128 * chan) * sizeof(u32)), 1195 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1196 return 0; 1197 } 1198 1199 1200 /* enable DMA for specific channels, now available for DSP-MADI */ 1201 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1202 { 1203 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1204 } 1205 1206 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1207 { 1208 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1209 } 1210 1211 /* check if same process is writing and reading */ 1212 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1213 { 1214 unsigned long flags; 1215 int ret = 1; 1216 1217 spin_lock_irqsave(&hdspm->lock, flags); 1218 if ((hdspm->playback_pid != hdspm->capture_pid) && 1219 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1220 ret = 0; 1221 } 1222 spin_unlock_irqrestore(&hdspm->lock, flags); 1223 return ret; 1224 } 1225 1226 /* round arbitary sample rates to commonly known rates */ 1227 static int hdspm_round_frequency(int rate) 1228 { 1229 if (rate < 38050) 1230 return 32000; 1231 if (rate < 46008) 1232 return 44100; 1233 else 1234 return 48000; 1235 } 1236 1237 /* QS and DS rates normally can not be detected 1238 * automatically by the card. Only exception is MADI 1239 * in 96k frame mode. 1240 * 1241 * So if we read SS values (32 .. 48k), check for 1242 * user-provided DS/QS bits in the control register 1243 * and multiply the base frequency accordingly. 1244 */ 1245 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1246 { 1247 if (rate <= 48000) { 1248 if (hdspm->control_register & HDSPM_QuadSpeed) 1249 return rate * 4; 1250 else if (hdspm->control_register & 1251 HDSPM_DoubleSpeed) 1252 return rate * 2; 1253 } 1254 return rate; 1255 } 1256 1257 /* check for external sample rate, returns the sample rate in Hz*/ 1258 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1259 { 1260 unsigned int status, status2, timecode; 1261 int syncref, rate = 0, rate_bits; 1262 1263 switch (hdspm->io_type) { 1264 case AES32: 1265 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1266 status = hdspm_read(hdspm, HDSPM_statusRegister); 1267 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1268 1269 syncref = hdspm_autosync_ref(hdspm); 1270 switch (syncref) { 1271 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 1272 /* Check WC sync and get sample rate */ 1273 if (hdspm_wc_sync_check(hdspm)) 1274 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm)); 1275 break; 1276 1277 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 1278 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 1279 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 1280 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 1281 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 1282 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 1283 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 1284 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 1285 /* Check AES sync and get sample rate */ 1286 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)) 1287 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm, 1288 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)); 1289 break; 1290 1291 1292 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 1293 /* Check TCO sync and get sample rate */ 1294 if (hdspm_tco_sync_check(hdspm)) 1295 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm)); 1296 break; 1297 default: 1298 return 0; 1299 } /* end switch(syncref) */ 1300 break; 1301 1302 case MADIface: 1303 status = hdspm_read(hdspm, HDSPM_statusRegister); 1304 1305 if (!(status & HDSPM_madiLock)) { 1306 rate = 0; /* no lock */ 1307 } else { 1308 switch (status & (HDSPM_status1_freqMask)) { 1309 case HDSPM_status1_F_0*1: 1310 rate = 32000; break; 1311 case HDSPM_status1_F_0*2: 1312 rate = 44100; break; 1313 case HDSPM_status1_F_0*3: 1314 rate = 48000; break; 1315 case HDSPM_status1_F_0*4: 1316 rate = 64000; break; 1317 case HDSPM_status1_F_0*5: 1318 rate = 88200; break; 1319 case HDSPM_status1_F_0*6: 1320 rate = 96000; break; 1321 case HDSPM_status1_F_0*7: 1322 rate = 128000; break; 1323 case HDSPM_status1_F_0*8: 1324 rate = 176400; break; 1325 case HDSPM_status1_F_0*9: 1326 rate = 192000; break; 1327 default: 1328 rate = 0; break; 1329 } 1330 } 1331 1332 break; 1333 1334 case MADI: 1335 case AIO: 1336 case RayDAT: 1337 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1338 status = hdspm_read(hdspm, HDSPM_statusRegister); 1339 rate = 0; 1340 1341 /* if wordclock has synced freq and wordclock is valid */ 1342 if ((status2 & HDSPM_wcLock) != 0 && 1343 (status2 & HDSPM_SelSyncRef0) == 0) { 1344 1345 rate_bits = status2 & HDSPM_wcFreqMask; 1346 1347 1348 switch (rate_bits) { 1349 case HDSPM_wcFreq32: 1350 rate = 32000; 1351 break; 1352 case HDSPM_wcFreq44_1: 1353 rate = 44100; 1354 break; 1355 case HDSPM_wcFreq48: 1356 rate = 48000; 1357 break; 1358 case HDSPM_wcFreq64: 1359 rate = 64000; 1360 break; 1361 case HDSPM_wcFreq88_2: 1362 rate = 88200; 1363 break; 1364 case HDSPM_wcFreq96: 1365 rate = 96000; 1366 break; 1367 case HDSPM_wcFreq128: 1368 rate = 128000; 1369 break; 1370 case HDSPM_wcFreq176_4: 1371 rate = 176400; 1372 break; 1373 case HDSPM_wcFreq192: 1374 rate = 192000; 1375 break; 1376 default: 1377 rate = 0; 1378 break; 1379 } 1380 } 1381 1382 /* if rate detected and Syncref is Word than have it, 1383 * word has priority to MADI 1384 */ 1385 if (rate != 0 && 1386 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1387 return hdspm_rate_multiplier(hdspm, rate); 1388 1389 /* maybe a madi input (which is taken if sel sync is madi) */ 1390 if (status & HDSPM_madiLock) { 1391 rate_bits = status & HDSPM_madiFreqMask; 1392 1393 switch (rate_bits) { 1394 case HDSPM_madiFreq32: 1395 rate = 32000; 1396 break; 1397 case HDSPM_madiFreq44_1: 1398 rate = 44100; 1399 break; 1400 case HDSPM_madiFreq48: 1401 rate = 48000; 1402 break; 1403 case HDSPM_madiFreq64: 1404 rate = 64000; 1405 break; 1406 case HDSPM_madiFreq88_2: 1407 rate = 88200; 1408 break; 1409 case HDSPM_madiFreq96: 1410 rate = 96000; 1411 break; 1412 case HDSPM_madiFreq128: 1413 rate = 128000; 1414 break; 1415 case HDSPM_madiFreq176_4: 1416 rate = 176400; 1417 break; 1418 case HDSPM_madiFreq192: 1419 rate = 192000; 1420 break; 1421 default: 1422 rate = 0; 1423 break; 1424 } 1425 1426 } /* endif HDSPM_madiLock */ 1427 1428 /* check sample rate from TCO or SYNC_IN */ 1429 { 1430 bool is_valid_input = 0; 1431 bool has_sync = 0; 1432 1433 syncref = hdspm_autosync_ref(hdspm); 1434 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1435 is_valid_input = 1; 1436 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1437 hdspm_tco_sync_check(hdspm)); 1438 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1439 is_valid_input = 1; 1440 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1441 hdspm_sync_in_sync_check(hdspm)); 1442 } 1443 1444 if (is_valid_input && has_sync) { 1445 rate = hdspm_round_frequency( 1446 hdspm_get_pll_freq(hdspm)); 1447 } 1448 } 1449 1450 rate = hdspm_rate_multiplier(hdspm, rate); 1451 1452 break; 1453 } 1454 1455 return rate; 1456 } 1457 1458 /* return latency in samples per period */ 1459 static int hdspm_get_latency(struct hdspm *hdspm) 1460 { 1461 int n; 1462 1463 n = hdspm_decode_latency(hdspm->control_register); 1464 1465 /* Special case for new RME cards with 32 samples period size. 1466 * The three latency bits in the control register 1467 * (HDSP_LatencyMask) encode latency values of 64 samples as 1468 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1469 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1470 * it corresponds to 32 samples. 1471 */ 1472 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1473 n = -1; 1474 1475 return 1 << (n + 6); 1476 } 1477 1478 /* Latency function */ 1479 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1480 { 1481 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1482 } 1483 1484 1485 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1486 { 1487 int position; 1488 1489 position = hdspm_read(hdspm, HDSPM_statusRegister); 1490 1491 switch (hdspm->io_type) { 1492 case RayDAT: 1493 case AIO: 1494 position &= HDSPM_BufferPositionMask; 1495 position /= 4; /* Bytes per sample */ 1496 break; 1497 default: 1498 position = (position & HDSPM_BufferID) ? 1499 (hdspm->period_bytes / 4) : 0; 1500 } 1501 1502 return position; 1503 } 1504 1505 1506 static inline void hdspm_start_audio(struct hdspm * s) 1507 { 1508 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1509 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1510 } 1511 1512 static inline void hdspm_stop_audio(struct hdspm * s) 1513 { 1514 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1515 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1516 } 1517 1518 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1519 static void hdspm_silence_playback(struct hdspm *hdspm) 1520 { 1521 int i; 1522 int n = hdspm->period_bytes; 1523 void *buf = hdspm->playback_buffer; 1524 1525 if (buf == NULL) 1526 return; 1527 1528 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1529 memset(buf, 0, n); 1530 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1531 } 1532 } 1533 1534 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1535 { 1536 int n; 1537 1538 spin_lock_irq(&s->lock); 1539 1540 if (32 == frames) { 1541 /* Special case for new RME cards like RayDAT/AIO which 1542 * support period sizes of 32 samples. Since latency is 1543 * encoded in the three bits of HDSP_LatencyMask, we can only 1544 * have values from 0 .. 7. While 0 still means 64 samples and 1545 * 6 represents 4096 samples on all cards, 7 represents 8192 1546 * on older cards and 32 samples on new cards. 1547 * 1548 * In other words, period size in samples is calculated by 1549 * 2^(n+6) with n ranging from 0 .. 7. 1550 */ 1551 n = 7; 1552 } else { 1553 frames >>= 7; 1554 n = 0; 1555 while (frames) { 1556 n++; 1557 frames >>= 1; 1558 } 1559 } 1560 1561 s->control_register &= ~HDSPM_LatencyMask; 1562 s->control_register |= hdspm_encode_latency(n); 1563 1564 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1565 1566 hdspm_compute_period_size(s); 1567 1568 spin_unlock_irq(&s->lock); 1569 1570 return 0; 1571 } 1572 1573 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1574 { 1575 u64 freq_const; 1576 1577 if (period == 0) 1578 return 0; 1579 1580 switch (hdspm->io_type) { 1581 case MADI: 1582 case AES32: 1583 freq_const = 110069313433624ULL; 1584 break; 1585 case RayDAT: 1586 case AIO: 1587 freq_const = 104857600000000ULL; 1588 break; 1589 case MADIface: 1590 freq_const = 131072000000000ULL; 1591 break; 1592 default: 1593 snd_BUG(); 1594 return 0; 1595 } 1596 1597 return div_u64(freq_const, period); 1598 } 1599 1600 1601 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1602 { 1603 u64 n; 1604 1605 if (rate >= 112000) 1606 rate /= 4; 1607 else if (rate >= 56000) 1608 rate /= 2; 1609 1610 switch (hdspm->io_type) { 1611 case MADIface: 1612 n = 131072000000000ULL; /* 125 MHz */ 1613 break; 1614 case MADI: 1615 case AES32: 1616 n = 110069313433624ULL; /* 105 MHz */ 1617 break; 1618 case RayDAT: 1619 case AIO: 1620 n = 104857600000000ULL; /* 100 MHz */ 1621 break; 1622 default: 1623 snd_BUG(); 1624 return; 1625 } 1626 1627 n = div_u64(n, rate); 1628 /* n should be less than 2^32 for being written to FREQ register */ 1629 snd_BUG_ON(n >> 32); 1630 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1631 } 1632 1633 /* dummy set rate lets see what happens */ 1634 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1635 { 1636 int current_rate; 1637 int rate_bits; 1638 int not_set = 0; 1639 int current_speed, target_speed; 1640 1641 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1642 it (e.g. during module initialization). 1643 */ 1644 1645 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1646 1647 /* SLAVE --- */ 1648 if (called_internally) { 1649 1650 /* request from ctl or card initialization 1651 just make a warning an remember setting 1652 for future master mode switching */ 1653 1654 dev_warn(hdspm->card->dev, 1655 "Warning: device is not running as a clock master.\n"); 1656 not_set = 1; 1657 } else { 1658 1659 /* hw_param request while in AutoSync mode */ 1660 int external_freq = 1661 hdspm_external_sample_rate(hdspm); 1662 1663 if (hdspm_autosync_ref(hdspm) == 1664 HDSPM_AUTOSYNC_FROM_NONE) { 1665 1666 dev_warn(hdspm->card->dev, 1667 "Detected no Externel Sync\n"); 1668 not_set = 1; 1669 1670 } else if (rate != external_freq) { 1671 1672 dev_warn(hdspm->card->dev, 1673 "Warning: No AutoSync source for requested rate\n"); 1674 not_set = 1; 1675 } 1676 } 1677 } 1678 1679 current_rate = hdspm->system_sample_rate; 1680 1681 /* Changing between Singe, Double and Quad speed is not 1682 allowed if any substreams are open. This is because such a change 1683 causes a shift in the location of the DMA buffers and a reduction 1684 in the number of available buffers. 1685 1686 Note that a similar but essentially insoluble problem exists for 1687 externally-driven rate changes. All we can do is to flag rate 1688 changes in the read/write routines. 1689 */ 1690 1691 if (current_rate <= 48000) 1692 current_speed = HDSPM_SPEED_SINGLE; 1693 else if (current_rate <= 96000) 1694 current_speed = HDSPM_SPEED_DOUBLE; 1695 else 1696 current_speed = HDSPM_SPEED_QUAD; 1697 1698 if (rate <= 48000) 1699 target_speed = HDSPM_SPEED_SINGLE; 1700 else if (rate <= 96000) 1701 target_speed = HDSPM_SPEED_DOUBLE; 1702 else 1703 target_speed = HDSPM_SPEED_QUAD; 1704 1705 switch (rate) { 1706 case 32000: 1707 rate_bits = HDSPM_Frequency32KHz; 1708 break; 1709 case 44100: 1710 rate_bits = HDSPM_Frequency44_1KHz; 1711 break; 1712 case 48000: 1713 rate_bits = HDSPM_Frequency48KHz; 1714 break; 1715 case 64000: 1716 rate_bits = HDSPM_Frequency64KHz; 1717 break; 1718 case 88200: 1719 rate_bits = HDSPM_Frequency88_2KHz; 1720 break; 1721 case 96000: 1722 rate_bits = HDSPM_Frequency96KHz; 1723 break; 1724 case 128000: 1725 rate_bits = HDSPM_Frequency128KHz; 1726 break; 1727 case 176400: 1728 rate_bits = HDSPM_Frequency176_4KHz; 1729 break; 1730 case 192000: 1731 rate_bits = HDSPM_Frequency192KHz; 1732 break; 1733 default: 1734 return -EINVAL; 1735 } 1736 1737 if (current_speed != target_speed 1738 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1739 dev_err(hdspm->card->dev, 1740 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n", 1741 hdspm_speed_names[current_speed], 1742 hdspm_speed_names[target_speed], 1743 hdspm->capture_pid, hdspm->playback_pid); 1744 return -EBUSY; 1745 } 1746 1747 hdspm->control_register &= ~HDSPM_FrequencyMask; 1748 hdspm->control_register |= rate_bits; 1749 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1750 1751 /* For AES32, need to set DDS value in FREQ register 1752 For MADI, also apparently */ 1753 hdspm_set_dds_value(hdspm, rate); 1754 1755 if (AES32 == hdspm->io_type && rate != current_rate) 1756 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1757 1758 hdspm->system_sample_rate = rate; 1759 1760 if (rate <= 48000) { 1761 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1762 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1763 hdspm->max_channels_in = hdspm->ss_in_channels; 1764 hdspm->max_channels_out = hdspm->ss_out_channels; 1765 hdspm->port_names_in = hdspm->port_names_in_ss; 1766 hdspm->port_names_out = hdspm->port_names_out_ss; 1767 } else if (rate <= 96000) { 1768 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1769 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1770 hdspm->max_channels_in = hdspm->ds_in_channels; 1771 hdspm->max_channels_out = hdspm->ds_out_channels; 1772 hdspm->port_names_in = hdspm->port_names_in_ds; 1773 hdspm->port_names_out = hdspm->port_names_out_ds; 1774 } else { 1775 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1776 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1777 hdspm->max_channels_in = hdspm->qs_in_channels; 1778 hdspm->max_channels_out = hdspm->qs_out_channels; 1779 hdspm->port_names_in = hdspm->port_names_in_qs; 1780 hdspm->port_names_out = hdspm->port_names_out_qs; 1781 } 1782 1783 if (not_set != 0) 1784 return -1; 1785 1786 return 0; 1787 } 1788 1789 /* mainly for init to 0 on load */ 1790 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1791 { 1792 int i, j; 1793 unsigned int gain; 1794 1795 if (sgain > UNITY_GAIN) 1796 gain = UNITY_GAIN; 1797 else if (sgain < 0) 1798 gain = 0; 1799 else 1800 gain = sgain; 1801 1802 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1803 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1804 hdspm_write_in_gain(hdspm, i, j, gain); 1805 hdspm_write_pb_gain(hdspm, i, j, gain); 1806 } 1807 } 1808 1809 /*---------------------------------------------------------------------------- 1810 MIDI 1811 ----------------------------------------------------------------------------*/ 1812 1813 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1814 int id) 1815 { 1816 /* the hardware already does the relevant bit-mask with 0xff */ 1817 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1818 } 1819 1820 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1821 int val) 1822 { 1823 /* the hardware already does the relevant bit-mask with 0xff */ 1824 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1825 } 1826 1827 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1828 { 1829 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1830 } 1831 1832 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1833 { 1834 int fifo_bytes_used; 1835 1836 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1837 1838 if (fifo_bytes_used < 128) 1839 return 128 - fifo_bytes_used; 1840 else 1841 return 0; 1842 } 1843 1844 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1845 { 1846 while (snd_hdspm_midi_input_available (hdspm, id)) 1847 snd_hdspm_midi_read_byte (hdspm, id); 1848 } 1849 1850 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1851 { 1852 unsigned long flags; 1853 int n_pending; 1854 int to_write; 1855 int i; 1856 unsigned char buf[128]; 1857 1858 /* Output is not interrupt driven */ 1859 1860 spin_lock_irqsave (&hmidi->lock, flags); 1861 if (hmidi->output && 1862 !snd_rawmidi_transmit_empty (hmidi->output)) { 1863 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1864 hmidi->id); 1865 if (n_pending > 0) { 1866 if (n_pending > (int)sizeof (buf)) 1867 n_pending = sizeof (buf); 1868 1869 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1870 n_pending); 1871 if (to_write > 0) { 1872 for (i = 0; i < to_write; ++i) 1873 snd_hdspm_midi_write_byte (hmidi->hdspm, 1874 hmidi->id, 1875 buf[i]); 1876 } 1877 } 1878 } 1879 spin_unlock_irqrestore (&hmidi->lock, flags); 1880 return 0; 1881 } 1882 1883 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1884 { 1885 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1886 * input FIFO size 1887 */ 1888 unsigned long flags; 1889 int n_pending; 1890 int i; 1891 1892 spin_lock_irqsave (&hmidi->lock, flags); 1893 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1894 if (n_pending > 0) { 1895 if (hmidi->input) { 1896 if (n_pending > (int)sizeof (buf)) 1897 n_pending = sizeof (buf); 1898 for (i = 0; i < n_pending; ++i) 1899 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1900 hmidi->id); 1901 if (n_pending) 1902 snd_rawmidi_receive (hmidi->input, buf, 1903 n_pending); 1904 } else { 1905 /* flush the MIDI input FIFO */ 1906 while (n_pending--) 1907 snd_hdspm_midi_read_byte (hmidi->hdspm, 1908 hmidi->id); 1909 } 1910 } 1911 hmidi->pending = 0; 1912 spin_unlock_irqrestore(&hmidi->lock, flags); 1913 1914 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1915 hmidi->hdspm->control_register |= hmidi->ie; 1916 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1917 hmidi->hdspm->control_register); 1918 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1919 1920 return snd_hdspm_midi_output_write (hmidi); 1921 } 1922 1923 static void 1924 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1925 { 1926 struct hdspm *hdspm; 1927 struct hdspm_midi *hmidi; 1928 unsigned long flags; 1929 1930 hmidi = substream->rmidi->private_data; 1931 hdspm = hmidi->hdspm; 1932 1933 spin_lock_irqsave (&hdspm->lock, flags); 1934 if (up) { 1935 if (!(hdspm->control_register & hmidi->ie)) { 1936 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1937 hdspm->control_register |= hmidi->ie; 1938 } 1939 } else { 1940 hdspm->control_register &= ~hmidi->ie; 1941 } 1942 1943 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1944 spin_unlock_irqrestore (&hdspm->lock, flags); 1945 } 1946 1947 static void snd_hdspm_midi_output_timer(unsigned long data) 1948 { 1949 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1950 unsigned long flags; 1951 1952 snd_hdspm_midi_output_write(hmidi); 1953 spin_lock_irqsave (&hmidi->lock, flags); 1954 1955 /* this does not bump hmidi->istimer, because the 1956 kernel automatically removed the timer when it 1957 expired, and we are now adding it back, thus 1958 leaving istimer wherever it was set before. 1959 */ 1960 1961 if (hmidi->istimer) { 1962 hmidi->timer.expires = 1 + jiffies; 1963 add_timer(&hmidi->timer); 1964 } 1965 1966 spin_unlock_irqrestore (&hmidi->lock, flags); 1967 } 1968 1969 static void 1970 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1971 { 1972 struct hdspm_midi *hmidi; 1973 unsigned long flags; 1974 1975 hmidi = substream->rmidi->private_data; 1976 spin_lock_irqsave (&hmidi->lock, flags); 1977 if (up) { 1978 if (!hmidi->istimer) { 1979 init_timer(&hmidi->timer); 1980 hmidi->timer.function = snd_hdspm_midi_output_timer; 1981 hmidi->timer.data = (unsigned long) hmidi; 1982 hmidi->timer.expires = 1 + jiffies; 1983 add_timer(&hmidi->timer); 1984 hmidi->istimer++; 1985 } 1986 } else { 1987 if (hmidi->istimer && --hmidi->istimer <= 0) 1988 del_timer (&hmidi->timer); 1989 } 1990 spin_unlock_irqrestore (&hmidi->lock, flags); 1991 if (up) 1992 snd_hdspm_midi_output_write(hmidi); 1993 } 1994 1995 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1996 { 1997 struct hdspm_midi *hmidi; 1998 1999 hmidi = substream->rmidi->private_data; 2000 spin_lock_irq (&hmidi->lock); 2001 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 2002 hmidi->input = substream; 2003 spin_unlock_irq (&hmidi->lock); 2004 2005 return 0; 2006 } 2007 2008 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 2009 { 2010 struct hdspm_midi *hmidi; 2011 2012 hmidi = substream->rmidi->private_data; 2013 spin_lock_irq (&hmidi->lock); 2014 hmidi->output = substream; 2015 spin_unlock_irq (&hmidi->lock); 2016 2017 return 0; 2018 } 2019 2020 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 2021 { 2022 struct hdspm_midi *hmidi; 2023 2024 snd_hdspm_midi_input_trigger (substream, 0); 2025 2026 hmidi = substream->rmidi->private_data; 2027 spin_lock_irq (&hmidi->lock); 2028 hmidi->input = NULL; 2029 spin_unlock_irq (&hmidi->lock); 2030 2031 return 0; 2032 } 2033 2034 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 2035 { 2036 struct hdspm_midi *hmidi; 2037 2038 snd_hdspm_midi_output_trigger (substream, 0); 2039 2040 hmidi = substream->rmidi->private_data; 2041 spin_lock_irq (&hmidi->lock); 2042 hmidi->output = NULL; 2043 spin_unlock_irq (&hmidi->lock); 2044 2045 return 0; 2046 } 2047 2048 static struct snd_rawmidi_ops snd_hdspm_midi_output = 2049 { 2050 .open = snd_hdspm_midi_output_open, 2051 .close = snd_hdspm_midi_output_close, 2052 .trigger = snd_hdspm_midi_output_trigger, 2053 }; 2054 2055 static struct snd_rawmidi_ops snd_hdspm_midi_input = 2056 { 2057 .open = snd_hdspm_midi_input_open, 2058 .close = snd_hdspm_midi_input_close, 2059 .trigger = snd_hdspm_midi_input_trigger, 2060 }; 2061 2062 static int snd_hdspm_create_midi(struct snd_card *card, 2063 struct hdspm *hdspm, int id) 2064 { 2065 int err; 2066 char buf[32]; 2067 2068 hdspm->midi[id].id = id; 2069 hdspm->midi[id].hdspm = hdspm; 2070 spin_lock_init (&hdspm->midi[id].lock); 2071 2072 if (0 == id) { 2073 if (MADIface == hdspm->io_type) { 2074 /* MIDI-over-MADI on HDSPe MADIface */ 2075 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 2076 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 2077 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 2078 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 2079 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 2080 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 2081 } else { 2082 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 2083 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 2084 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 2085 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 2086 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 2087 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 2088 } 2089 } else if (1 == id) { 2090 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 2091 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 2092 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 2093 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 2094 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 2095 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 2096 } else if ((2 == id) && (MADI == hdspm->io_type)) { 2097 /* MIDI-over-MADI on HDSPe MADI */ 2098 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2099 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2100 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 2101 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 2102 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2103 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 2104 } else if (2 == id) { 2105 /* TCO MTC, read only */ 2106 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2107 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2108 hdspm->midi[2].dataOut = -1; 2109 hdspm->midi[2].statusOut = -1; 2110 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2111 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 2112 } else if (3 == id) { 2113 /* TCO MTC on HDSPe MADI */ 2114 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 2115 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 2116 hdspm->midi[3].dataOut = -1; 2117 hdspm->midi[3].statusOut = -1; 2118 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 2119 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 2120 } 2121 2122 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 2123 (MADIface == hdspm->io_type)))) { 2124 if ((id == 0) && (MADIface == hdspm->io_type)) { 2125 sprintf(buf, "%s MIDIoverMADI", card->shortname); 2126 } else if ((id == 2) && (MADI == hdspm->io_type)) { 2127 sprintf(buf, "%s MIDIoverMADI", card->shortname); 2128 } else { 2129 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 2130 } 2131 err = snd_rawmidi_new(card, buf, id, 1, 1, 2132 &hdspm->midi[id].rmidi); 2133 if (err < 0) 2134 return err; 2135 2136 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 2137 card->id, id+1); 2138 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2139 2140 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2141 SNDRV_RAWMIDI_STREAM_OUTPUT, 2142 &snd_hdspm_midi_output); 2143 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2144 SNDRV_RAWMIDI_STREAM_INPUT, 2145 &snd_hdspm_midi_input); 2146 2147 hdspm->midi[id].rmidi->info_flags |= 2148 SNDRV_RAWMIDI_INFO_OUTPUT | 2149 SNDRV_RAWMIDI_INFO_INPUT | 2150 SNDRV_RAWMIDI_INFO_DUPLEX; 2151 } else { 2152 /* TCO MTC, read only */ 2153 sprintf(buf, "%s MTC %d", card->shortname, id+1); 2154 err = snd_rawmidi_new(card, buf, id, 1, 1, 2155 &hdspm->midi[id].rmidi); 2156 if (err < 0) 2157 return err; 2158 2159 sprintf(hdspm->midi[id].rmidi->name, 2160 "%s MTC %d", card->id, id+1); 2161 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2162 2163 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2164 SNDRV_RAWMIDI_STREAM_INPUT, 2165 &snd_hdspm_midi_input); 2166 2167 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2168 } 2169 2170 return 0; 2171 } 2172 2173 2174 static void hdspm_midi_tasklet(unsigned long arg) 2175 { 2176 struct hdspm *hdspm = (struct hdspm *)arg; 2177 int i = 0; 2178 2179 while (i < hdspm->midiPorts) { 2180 if (hdspm->midi[i].pending) 2181 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2182 2183 i++; 2184 } 2185 } 2186 2187 2188 /*----------------------------------------------------------------------------- 2189 Status Interface 2190 ----------------------------------------------------------------------------*/ 2191 2192 /* get the system sample rate which is set */ 2193 2194 2195 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2196 { 2197 unsigned int period, rate; 2198 2199 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2200 rate = hdspm_calc_dds_value(hdspm, period); 2201 2202 return rate; 2203 } 2204 2205 /** 2206 * Calculate the real sample rate from the 2207 * current DDS value. 2208 **/ 2209 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2210 { 2211 unsigned int rate; 2212 2213 rate = hdspm_get_pll_freq(hdspm); 2214 2215 if (rate > 207000) { 2216 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2217 if (0 == hdspm_system_clock_mode(hdspm)) { 2218 /* master mode, return internal sample rate */ 2219 rate = hdspm->system_sample_rate; 2220 } else { 2221 /* slave mode, return external sample rate */ 2222 rate = hdspm_external_sample_rate(hdspm); 2223 } 2224 } 2225 2226 return rate; 2227 } 2228 2229 2230 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2231 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2232 .name = xname, \ 2233 .index = xindex, \ 2234 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2235 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2236 .info = snd_hdspm_info_system_sample_rate, \ 2237 .put = snd_hdspm_put_system_sample_rate, \ 2238 .get = snd_hdspm_get_system_sample_rate \ 2239 } 2240 2241 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2242 struct snd_ctl_elem_info *uinfo) 2243 { 2244 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2245 uinfo->count = 1; 2246 uinfo->value.integer.min = 27000; 2247 uinfo->value.integer.max = 207000; 2248 uinfo->value.integer.step = 1; 2249 return 0; 2250 } 2251 2252 2253 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2254 struct snd_ctl_elem_value * 2255 ucontrol) 2256 { 2257 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2258 2259 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2260 return 0; 2261 } 2262 2263 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2264 struct snd_ctl_elem_value * 2265 ucontrol) 2266 { 2267 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2268 2269 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]); 2270 return 0; 2271 } 2272 2273 2274 /** 2275 * Returns the WordClock sample rate class for the given card. 2276 **/ 2277 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2278 { 2279 int status; 2280 2281 switch (hdspm->io_type) { 2282 case RayDAT: 2283 case AIO: 2284 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2285 return (status >> 16) & 0xF; 2286 break; 2287 case AES32: 2288 status = hdspm_read(hdspm, HDSPM_statusRegister); 2289 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF; 2290 default: 2291 break; 2292 } 2293 2294 2295 return 0; 2296 } 2297 2298 2299 /** 2300 * Returns the TCO sample rate class for the given card. 2301 **/ 2302 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2303 { 2304 int status; 2305 2306 if (hdspm->tco) { 2307 switch (hdspm->io_type) { 2308 case RayDAT: 2309 case AIO: 2310 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2311 return (status >> 20) & 0xF; 2312 break; 2313 case AES32: 2314 status = hdspm_read(hdspm, HDSPM_statusRegister); 2315 return (status >> 1) & 0xF; 2316 default: 2317 break; 2318 } 2319 } 2320 2321 return 0; 2322 } 2323 2324 2325 /** 2326 * Returns the SYNC_IN sample rate class for the given card. 2327 **/ 2328 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2329 { 2330 int status; 2331 2332 if (hdspm->tco) { 2333 switch (hdspm->io_type) { 2334 case RayDAT: 2335 case AIO: 2336 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2337 return (status >> 12) & 0xF; 2338 break; 2339 default: 2340 break; 2341 } 2342 } 2343 2344 return 0; 2345 } 2346 2347 /** 2348 * Returns the AES sample rate class for the given card. 2349 **/ 2350 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index) 2351 { 2352 int timecode; 2353 2354 switch (hdspm->io_type) { 2355 case AES32: 2356 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 2357 return (timecode >> (4*index)) & 0xF; 2358 break; 2359 default: 2360 break; 2361 } 2362 return 0; 2363 } 2364 2365 /** 2366 * Returns the sample rate class for input source <idx> for 2367 * 'new style' cards like the AIO and RayDAT. 2368 **/ 2369 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2370 { 2371 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2372 2373 return (status >> (idx*4)) & 0xF; 2374 } 2375 2376 #define ENUMERATED_CTL_INFO(info, texts) \ 2377 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts) 2378 2379 2380 /* Helper function to query the external sample rate and return the 2381 * corresponding enum to be returned to userspace. 2382 */ 2383 static int hdspm_external_rate_to_enum(struct hdspm *hdspm) 2384 { 2385 int rate = hdspm_external_sample_rate(hdspm); 2386 int i, selected_rate = 0; 2387 for (i = 1; i < 10; i++) 2388 if (HDSPM_bit2freq(i) == rate) { 2389 selected_rate = i; 2390 break; 2391 } 2392 return selected_rate; 2393 } 2394 2395 2396 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2397 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2398 .name = xname, \ 2399 .private_value = xindex, \ 2400 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2401 .info = snd_hdspm_info_autosync_sample_rate, \ 2402 .get = snd_hdspm_get_autosync_sample_rate \ 2403 } 2404 2405 2406 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2407 struct snd_ctl_elem_info *uinfo) 2408 { 2409 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2410 return 0; 2411 } 2412 2413 2414 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2415 struct snd_ctl_elem_value * 2416 ucontrol) 2417 { 2418 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2419 2420 switch (hdspm->io_type) { 2421 case RayDAT: 2422 switch (kcontrol->private_value) { 2423 case 0: 2424 ucontrol->value.enumerated.item[0] = 2425 hdspm_get_wc_sample_rate(hdspm); 2426 break; 2427 case 7: 2428 ucontrol->value.enumerated.item[0] = 2429 hdspm_get_tco_sample_rate(hdspm); 2430 break; 2431 case 8: 2432 ucontrol->value.enumerated.item[0] = 2433 hdspm_get_sync_in_sample_rate(hdspm); 2434 break; 2435 default: 2436 ucontrol->value.enumerated.item[0] = 2437 hdspm_get_s1_sample_rate(hdspm, 2438 kcontrol->private_value-1); 2439 } 2440 break; 2441 2442 case AIO: 2443 switch (kcontrol->private_value) { 2444 case 0: /* WC */ 2445 ucontrol->value.enumerated.item[0] = 2446 hdspm_get_wc_sample_rate(hdspm); 2447 break; 2448 case 4: /* TCO */ 2449 ucontrol->value.enumerated.item[0] = 2450 hdspm_get_tco_sample_rate(hdspm); 2451 break; 2452 case 5: /* SYNC_IN */ 2453 ucontrol->value.enumerated.item[0] = 2454 hdspm_get_sync_in_sample_rate(hdspm); 2455 break; 2456 default: 2457 ucontrol->value.enumerated.item[0] = 2458 hdspm_get_s1_sample_rate(hdspm, 2459 kcontrol->private_value-1); 2460 } 2461 break; 2462 2463 case AES32: 2464 2465 switch (kcontrol->private_value) { 2466 case 0: /* WC */ 2467 ucontrol->value.enumerated.item[0] = 2468 hdspm_get_wc_sample_rate(hdspm); 2469 break; 2470 case 9: /* TCO */ 2471 ucontrol->value.enumerated.item[0] = 2472 hdspm_get_tco_sample_rate(hdspm); 2473 break; 2474 case 10: /* SYNC_IN */ 2475 ucontrol->value.enumerated.item[0] = 2476 hdspm_get_sync_in_sample_rate(hdspm); 2477 break; 2478 case 11: /* External Rate */ 2479 ucontrol->value.enumerated.item[0] = 2480 hdspm_external_rate_to_enum(hdspm); 2481 break; 2482 default: /* AES1 to AES8 */ 2483 ucontrol->value.enumerated.item[0] = 2484 hdspm_get_aes_sample_rate(hdspm, 2485 kcontrol->private_value - 2486 HDSPM_AES32_AUTOSYNC_FROM_AES1); 2487 break; 2488 } 2489 break; 2490 2491 case MADI: 2492 case MADIface: 2493 ucontrol->value.enumerated.item[0] = 2494 hdspm_external_rate_to_enum(hdspm); 2495 break; 2496 default: 2497 break; 2498 } 2499 2500 return 0; 2501 } 2502 2503 2504 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2505 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2506 .name = xname, \ 2507 .index = xindex, \ 2508 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2509 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2510 .info = snd_hdspm_info_system_clock_mode, \ 2511 .get = snd_hdspm_get_system_clock_mode, \ 2512 .put = snd_hdspm_put_system_clock_mode, \ 2513 } 2514 2515 2516 /** 2517 * Returns the system clock mode for the given card. 2518 * @returns 0 - master, 1 - slave 2519 **/ 2520 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2521 { 2522 switch (hdspm->io_type) { 2523 case AIO: 2524 case RayDAT: 2525 if (hdspm->settings_register & HDSPM_c0Master) 2526 return 0; 2527 break; 2528 2529 default: 2530 if (hdspm->control_register & HDSPM_ClockModeMaster) 2531 return 0; 2532 } 2533 2534 return 1; 2535 } 2536 2537 2538 /** 2539 * Sets the system clock mode. 2540 * @param mode 0 - master, 1 - slave 2541 **/ 2542 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2543 { 2544 hdspm_set_toggle_setting(hdspm, 2545 (hdspm_is_raydat_or_aio(hdspm)) ? 2546 HDSPM_c0Master : HDSPM_ClockModeMaster, 2547 (0 == mode)); 2548 } 2549 2550 2551 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2552 struct snd_ctl_elem_info *uinfo) 2553 { 2554 static const char *const texts[] = { "Master", "AutoSync" }; 2555 ENUMERATED_CTL_INFO(uinfo, texts); 2556 return 0; 2557 } 2558 2559 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2560 struct snd_ctl_elem_value *ucontrol) 2561 { 2562 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2563 2564 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2565 return 0; 2566 } 2567 2568 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2569 struct snd_ctl_elem_value *ucontrol) 2570 { 2571 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2572 int val; 2573 2574 if (!snd_hdspm_use_is_exclusive(hdspm)) 2575 return -EBUSY; 2576 2577 val = ucontrol->value.enumerated.item[0]; 2578 if (val < 0) 2579 val = 0; 2580 else if (val > 1) 2581 val = 1; 2582 2583 hdspm_set_system_clock_mode(hdspm, val); 2584 2585 return 0; 2586 } 2587 2588 2589 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2590 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2591 .name = xname, \ 2592 .index = xindex, \ 2593 .info = snd_hdspm_info_clock_source, \ 2594 .get = snd_hdspm_get_clock_source, \ 2595 .put = snd_hdspm_put_clock_source \ 2596 } 2597 2598 2599 static int hdspm_clock_source(struct hdspm * hdspm) 2600 { 2601 switch (hdspm->system_sample_rate) { 2602 case 32000: return 0; 2603 case 44100: return 1; 2604 case 48000: return 2; 2605 case 64000: return 3; 2606 case 88200: return 4; 2607 case 96000: return 5; 2608 case 128000: return 6; 2609 case 176400: return 7; 2610 case 192000: return 8; 2611 } 2612 2613 return -1; 2614 } 2615 2616 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2617 { 2618 int rate; 2619 switch (mode) { 2620 case 0: 2621 rate = 32000; break; 2622 case 1: 2623 rate = 44100; break; 2624 case 2: 2625 rate = 48000; break; 2626 case 3: 2627 rate = 64000; break; 2628 case 4: 2629 rate = 88200; break; 2630 case 5: 2631 rate = 96000; break; 2632 case 6: 2633 rate = 128000; break; 2634 case 7: 2635 rate = 176400; break; 2636 case 8: 2637 rate = 192000; break; 2638 default: 2639 rate = 48000; 2640 } 2641 hdspm_set_rate(hdspm, rate, 1); 2642 return 0; 2643 } 2644 2645 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2646 struct snd_ctl_elem_info *uinfo) 2647 { 2648 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2649 uinfo->count = 1; 2650 uinfo->value.enumerated.items = 9; 2651 2652 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2653 uinfo->value.enumerated.item = 2654 uinfo->value.enumerated.items - 1; 2655 2656 strcpy(uinfo->value.enumerated.name, 2657 texts_freq[uinfo->value.enumerated.item+1]); 2658 2659 return 0; 2660 } 2661 2662 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2663 struct snd_ctl_elem_value *ucontrol) 2664 { 2665 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2666 2667 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2668 return 0; 2669 } 2670 2671 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2672 struct snd_ctl_elem_value *ucontrol) 2673 { 2674 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2675 int change; 2676 int val; 2677 2678 if (!snd_hdspm_use_is_exclusive(hdspm)) 2679 return -EBUSY; 2680 val = ucontrol->value.enumerated.item[0]; 2681 if (val < 0) 2682 val = 0; 2683 if (val > 9) 2684 val = 9; 2685 spin_lock_irq(&hdspm->lock); 2686 if (val != hdspm_clock_source(hdspm)) 2687 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2688 else 2689 change = 0; 2690 spin_unlock_irq(&hdspm->lock); 2691 return change; 2692 } 2693 2694 2695 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2696 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2697 .name = xname, \ 2698 .index = xindex, \ 2699 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2700 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2701 .info = snd_hdspm_info_pref_sync_ref, \ 2702 .get = snd_hdspm_get_pref_sync_ref, \ 2703 .put = snd_hdspm_put_pref_sync_ref \ 2704 } 2705 2706 2707 /** 2708 * Returns the current preferred sync reference setting. 2709 * The semantics of the return value are depending on the 2710 * card, please see the comments for clarification. 2711 **/ 2712 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2713 { 2714 switch (hdspm->io_type) { 2715 case AES32: 2716 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2717 case 0: return 0; /* WC */ 2718 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2719 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2720 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2721 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2722 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2723 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2724 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2725 return 7; /* AES 7 */ 2726 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2727 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2728 } 2729 break; 2730 2731 case MADI: 2732 case MADIface: 2733 if (hdspm->tco) { 2734 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2735 case 0: return 0; /* WC */ 2736 case HDSPM_SyncRef0: return 1; /* MADI */ 2737 case HDSPM_SyncRef1: return 2; /* TCO */ 2738 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2739 return 3; /* SYNC_IN */ 2740 } 2741 } else { 2742 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2743 case 0: return 0; /* WC */ 2744 case HDSPM_SyncRef0: return 1; /* MADI */ 2745 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2746 return 2; /* SYNC_IN */ 2747 } 2748 } 2749 break; 2750 2751 case RayDAT: 2752 if (hdspm->tco) { 2753 switch ((hdspm->settings_register & 2754 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2755 case 0: return 0; /* WC */ 2756 case 3: return 1; /* ADAT 1 */ 2757 case 4: return 2; /* ADAT 2 */ 2758 case 5: return 3; /* ADAT 3 */ 2759 case 6: return 4; /* ADAT 4 */ 2760 case 1: return 5; /* AES */ 2761 case 2: return 6; /* SPDIF */ 2762 case 9: return 7; /* TCO */ 2763 case 10: return 8; /* SYNC_IN */ 2764 } 2765 } else { 2766 switch ((hdspm->settings_register & 2767 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2768 case 0: return 0; /* WC */ 2769 case 3: return 1; /* ADAT 1 */ 2770 case 4: return 2; /* ADAT 2 */ 2771 case 5: return 3; /* ADAT 3 */ 2772 case 6: return 4; /* ADAT 4 */ 2773 case 1: return 5; /* AES */ 2774 case 2: return 6; /* SPDIF */ 2775 case 10: return 7; /* SYNC_IN */ 2776 } 2777 } 2778 2779 break; 2780 2781 case AIO: 2782 if (hdspm->tco) { 2783 switch ((hdspm->settings_register & 2784 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2785 case 0: return 0; /* WC */ 2786 case 3: return 1; /* ADAT */ 2787 case 1: return 2; /* AES */ 2788 case 2: return 3; /* SPDIF */ 2789 case 9: return 4; /* TCO */ 2790 case 10: return 5; /* SYNC_IN */ 2791 } 2792 } else { 2793 switch ((hdspm->settings_register & 2794 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2795 case 0: return 0; /* WC */ 2796 case 3: return 1; /* ADAT */ 2797 case 1: return 2; /* AES */ 2798 case 2: return 3; /* SPDIF */ 2799 case 10: return 4; /* SYNC_IN */ 2800 } 2801 } 2802 2803 break; 2804 } 2805 2806 return -1; 2807 } 2808 2809 2810 /** 2811 * Set the preferred sync reference to <pref>. The semantics 2812 * of <pref> are depending on the card type, see the comments 2813 * for clarification. 2814 **/ 2815 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2816 { 2817 int p = 0; 2818 2819 switch (hdspm->io_type) { 2820 case AES32: 2821 hdspm->control_register &= ~HDSPM_SyncRefMask; 2822 switch (pref) { 2823 case 0: /* WC */ 2824 break; 2825 case 1: /* AES 1 */ 2826 hdspm->control_register |= HDSPM_SyncRef0; 2827 break; 2828 case 2: /* AES 2 */ 2829 hdspm->control_register |= HDSPM_SyncRef1; 2830 break; 2831 case 3: /* AES 3 */ 2832 hdspm->control_register |= 2833 HDSPM_SyncRef1+HDSPM_SyncRef0; 2834 break; 2835 case 4: /* AES 4 */ 2836 hdspm->control_register |= HDSPM_SyncRef2; 2837 break; 2838 case 5: /* AES 5 */ 2839 hdspm->control_register |= 2840 HDSPM_SyncRef2+HDSPM_SyncRef0; 2841 break; 2842 case 6: /* AES 6 */ 2843 hdspm->control_register |= 2844 HDSPM_SyncRef2+HDSPM_SyncRef1; 2845 break; 2846 case 7: /* AES 7 */ 2847 hdspm->control_register |= 2848 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2849 break; 2850 case 8: /* AES 8 */ 2851 hdspm->control_register |= HDSPM_SyncRef3; 2852 break; 2853 case 9: /* TCO */ 2854 hdspm->control_register |= 2855 HDSPM_SyncRef3+HDSPM_SyncRef0; 2856 break; 2857 default: 2858 return -1; 2859 } 2860 2861 break; 2862 2863 case MADI: 2864 case MADIface: 2865 hdspm->control_register &= ~HDSPM_SyncRefMask; 2866 if (hdspm->tco) { 2867 switch (pref) { 2868 case 0: /* WC */ 2869 break; 2870 case 1: /* MADI */ 2871 hdspm->control_register |= HDSPM_SyncRef0; 2872 break; 2873 case 2: /* TCO */ 2874 hdspm->control_register |= HDSPM_SyncRef1; 2875 break; 2876 case 3: /* SYNC_IN */ 2877 hdspm->control_register |= 2878 HDSPM_SyncRef0+HDSPM_SyncRef1; 2879 break; 2880 default: 2881 return -1; 2882 } 2883 } else { 2884 switch (pref) { 2885 case 0: /* WC */ 2886 break; 2887 case 1: /* MADI */ 2888 hdspm->control_register |= HDSPM_SyncRef0; 2889 break; 2890 case 2: /* SYNC_IN */ 2891 hdspm->control_register |= 2892 HDSPM_SyncRef0+HDSPM_SyncRef1; 2893 break; 2894 default: 2895 return -1; 2896 } 2897 } 2898 2899 break; 2900 2901 case RayDAT: 2902 if (hdspm->tco) { 2903 switch (pref) { 2904 case 0: p = 0; break; /* WC */ 2905 case 1: p = 3; break; /* ADAT 1 */ 2906 case 2: p = 4; break; /* ADAT 2 */ 2907 case 3: p = 5; break; /* ADAT 3 */ 2908 case 4: p = 6; break; /* ADAT 4 */ 2909 case 5: p = 1; break; /* AES */ 2910 case 6: p = 2; break; /* SPDIF */ 2911 case 7: p = 9; break; /* TCO */ 2912 case 8: p = 10; break; /* SYNC_IN */ 2913 default: return -1; 2914 } 2915 } else { 2916 switch (pref) { 2917 case 0: p = 0; break; /* WC */ 2918 case 1: p = 3; break; /* ADAT 1 */ 2919 case 2: p = 4; break; /* ADAT 2 */ 2920 case 3: p = 5; break; /* ADAT 3 */ 2921 case 4: p = 6; break; /* ADAT 4 */ 2922 case 5: p = 1; break; /* AES */ 2923 case 6: p = 2; break; /* SPDIF */ 2924 case 7: p = 10; break; /* SYNC_IN */ 2925 default: return -1; 2926 } 2927 } 2928 break; 2929 2930 case AIO: 2931 if (hdspm->tco) { 2932 switch (pref) { 2933 case 0: p = 0; break; /* WC */ 2934 case 1: p = 3; break; /* ADAT */ 2935 case 2: p = 1; break; /* AES */ 2936 case 3: p = 2; break; /* SPDIF */ 2937 case 4: p = 9; break; /* TCO */ 2938 case 5: p = 10; break; /* SYNC_IN */ 2939 default: return -1; 2940 } 2941 } else { 2942 switch (pref) { 2943 case 0: p = 0; break; /* WC */ 2944 case 1: p = 3; break; /* ADAT */ 2945 case 2: p = 1; break; /* AES */ 2946 case 3: p = 2; break; /* SPDIF */ 2947 case 4: p = 10; break; /* SYNC_IN */ 2948 default: return -1; 2949 } 2950 } 2951 break; 2952 } 2953 2954 switch (hdspm->io_type) { 2955 case RayDAT: 2956 case AIO: 2957 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2958 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2959 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2960 break; 2961 2962 case MADI: 2963 case MADIface: 2964 case AES32: 2965 hdspm_write(hdspm, HDSPM_controlRegister, 2966 hdspm->control_register); 2967 } 2968 2969 return 0; 2970 } 2971 2972 2973 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2974 struct snd_ctl_elem_info *uinfo) 2975 { 2976 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2977 2978 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync); 2979 2980 return 0; 2981 } 2982 2983 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2984 struct snd_ctl_elem_value *ucontrol) 2985 { 2986 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2987 int psf = hdspm_pref_sync_ref(hdspm); 2988 2989 if (psf >= 0) { 2990 ucontrol->value.enumerated.item[0] = psf; 2991 return 0; 2992 } 2993 2994 return -1; 2995 } 2996 2997 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2998 struct snd_ctl_elem_value *ucontrol) 2999 { 3000 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3001 int val, change = 0; 3002 3003 if (!snd_hdspm_use_is_exclusive(hdspm)) 3004 return -EBUSY; 3005 3006 val = ucontrol->value.enumerated.item[0]; 3007 3008 if (val < 0) 3009 val = 0; 3010 else if (val >= hdspm->texts_autosync_items) 3011 val = hdspm->texts_autosync_items-1; 3012 3013 spin_lock_irq(&hdspm->lock); 3014 if (val != hdspm_pref_sync_ref(hdspm)) 3015 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 3016 3017 spin_unlock_irq(&hdspm->lock); 3018 return change; 3019 } 3020 3021 3022 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 3023 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3024 .name = xname, \ 3025 .index = xindex, \ 3026 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 3027 .info = snd_hdspm_info_autosync_ref, \ 3028 .get = snd_hdspm_get_autosync_ref, \ 3029 } 3030 3031 static int hdspm_autosync_ref(struct hdspm *hdspm) 3032 { 3033 /* This looks at the autosync selected sync reference */ 3034 if (AES32 == hdspm->io_type) { 3035 3036 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 3037 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF; 3038 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) && 3039 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) { 3040 return syncref; 3041 } 3042 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 3043 3044 } else if (MADI == hdspm->io_type) { 3045 3046 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3047 switch (status2 & HDSPM_SelSyncRefMask) { 3048 case HDSPM_SelSyncRef_WORD: 3049 return HDSPM_AUTOSYNC_FROM_WORD; 3050 case HDSPM_SelSyncRef_MADI: 3051 return HDSPM_AUTOSYNC_FROM_MADI; 3052 case HDSPM_SelSyncRef_TCO: 3053 return HDSPM_AUTOSYNC_FROM_TCO; 3054 case HDSPM_SelSyncRef_SyncIn: 3055 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 3056 case HDSPM_SelSyncRef_NVALID: 3057 return HDSPM_AUTOSYNC_FROM_NONE; 3058 default: 3059 return HDSPM_AUTOSYNC_FROM_NONE; 3060 } 3061 3062 } 3063 return 0; 3064 } 3065 3066 3067 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 3068 struct snd_ctl_elem_info *uinfo) 3069 { 3070 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3071 3072 if (AES32 == hdspm->io_type) { 3073 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3", 3074 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"}; 3075 3076 ENUMERATED_CTL_INFO(uinfo, texts); 3077 } else if (MADI == hdspm->io_type) { 3078 static const char *const texts[] = {"Word Clock", "MADI", "TCO", 3079 "Sync In", "None" }; 3080 3081 ENUMERATED_CTL_INFO(uinfo, texts); 3082 } 3083 return 0; 3084 } 3085 3086 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 3087 struct snd_ctl_elem_value *ucontrol) 3088 { 3089 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3090 3091 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 3092 return 0; 3093 } 3094 3095 3096 3097 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \ 3098 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3099 .name = xname, \ 3100 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3101 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3102 .info = snd_hdspm_info_tco_video_input_format, \ 3103 .get = snd_hdspm_get_tco_video_input_format, \ 3104 } 3105 3106 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 3107 struct snd_ctl_elem_info *uinfo) 3108 { 3109 static const char *const texts[] = {"No video", "NTSC", "PAL"}; 3110 ENUMERATED_CTL_INFO(uinfo, texts); 3111 return 0; 3112 } 3113 3114 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 3115 struct snd_ctl_elem_value *ucontrol) 3116 { 3117 u32 status; 3118 int ret = 0; 3119 3120 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3121 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3122 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3123 HDSPM_TCO1_Video_Input_Format_PAL)) { 3124 case HDSPM_TCO1_Video_Input_Format_NTSC: 3125 /* ntsc */ 3126 ret = 1; 3127 break; 3128 case HDSPM_TCO1_Video_Input_Format_PAL: 3129 /* pal */ 3130 ret = 2; 3131 break; 3132 default: 3133 /* no video */ 3134 ret = 0; 3135 break; 3136 } 3137 ucontrol->value.enumerated.item[0] = ret; 3138 return 0; 3139 } 3140 3141 3142 3143 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \ 3144 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3145 .name = xname, \ 3146 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3147 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3148 .info = snd_hdspm_info_tco_ltc_frames, \ 3149 .get = snd_hdspm_get_tco_ltc_frames, \ 3150 } 3151 3152 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3153 struct snd_ctl_elem_info *uinfo) 3154 { 3155 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3156 "30 fps"}; 3157 ENUMERATED_CTL_INFO(uinfo, texts); 3158 return 0; 3159 } 3160 3161 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3162 { 3163 u32 status; 3164 int ret = 0; 3165 3166 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3167 if (status & HDSPM_TCO1_LTC_Input_valid) { 3168 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3169 HDSPM_TCO1_LTC_Format_MSB)) { 3170 case 0: 3171 /* 24 fps */ 3172 ret = fps_24; 3173 break; 3174 case HDSPM_TCO1_LTC_Format_LSB: 3175 /* 25 fps */ 3176 ret = fps_25; 3177 break; 3178 case HDSPM_TCO1_LTC_Format_MSB: 3179 /* 29.97 fps */ 3180 ret = fps_2997; 3181 break; 3182 default: 3183 /* 30 fps */ 3184 ret = fps_30; 3185 break; 3186 } 3187 } 3188 3189 return ret; 3190 } 3191 3192 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3193 struct snd_ctl_elem_value *ucontrol) 3194 { 3195 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3196 3197 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3198 return 0; 3199 } 3200 3201 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3202 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3203 .name = xname, \ 3204 .private_value = xindex, \ 3205 .info = snd_hdspm_info_toggle_setting, \ 3206 .get = snd_hdspm_get_toggle_setting, \ 3207 .put = snd_hdspm_put_toggle_setting \ 3208 } 3209 3210 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3211 { 3212 u32 reg; 3213 3214 if (hdspm_is_raydat_or_aio(hdspm)) 3215 reg = hdspm->settings_register; 3216 else 3217 reg = hdspm->control_register; 3218 3219 return (reg & regmask) ? 1 : 0; 3220 } 3221 3222 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3223 { 3224 u32 *reg; 3225 u32 target_reg; 3226 3227 if (hdspm_is_raydat_or_aio(hdspm)) { 3228 reg = &(hdspm->settings_register); 3229 target_reg = HDSPM_WR_SETTINGS; 3230 } else { 3231 reg = &(hdspm->control_register); 3232 target_reg = HDSPM_controlRegister; 3233 } 3234 3235 if (out) 3236 *reg |= regmask; 3237 else 3238 *reg &= ~regmask; 3239 3240 hdspm_write(hdspm, target_reg, *reg); 3241 3242 return 0; 3243 } 3244 3245 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3246 3247 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3248 struct snd_ctl_elem_value *ucontrol) 3249 { 3250 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3251 u32 regmask = kcontrol->private_value; 3252 3253 spin_lock_irq(&hdspm->lock); 3254 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3255 spin_unlock_irq(&hdspm->lock); 3256 return 0; 3257 } 3258 3259 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3260 struct snd_ctl_elem_value *ucontrol) 3261 { 3262 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3263 u32 regmask = kcontrol->private_value; 3264 int change; 3265 unsigned int val; 3266 3267 if (!snd_hdspm_use_is_exclusive(hdspm)) 3268 return -EBUSY; 3269 val = ucontrol->value.integer.value[0] & 1; 3270 spin_lock_irq(&hdspm->lock); 3271 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3272 hdspm_set_toggle_setting(hdspm, regmask, val); 3273 spin_unlock_irq(&hdspm->lock); 3274 return change; 3275 } 3276 3277 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3278 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3279 .name = xname, \ 3280 .index = xindex, \ 3281 .info = snd_hdspm_info_input_select, \ 3282 .get = snd_hdspm_get_input_select, \ 3283 .put = snd_hdspm_put_input_select \ 3284 } 3285 3286 static int hdspm_input_select(struct hdspm * hdspm) 3287 { 3288 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3289 } 3290 3291 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3292 { 3293 if (out) 3294 hdspm->control_register |= HDSPM_InputSelect0; 3295 else 3296 hdspm->control_register &= ~HDSPM_InputSelect0; 3297 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3298 3299 return 0; 3300 } 3301 3302 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3303 struct snd_ctl_elem_info *uinfo) 3304 { 3305 static const char *const texts[] = { "optical", "coaxial" }; 3306 ENUMERATED_CTL_INFO(uinfo, texts); 3307 return 0; 3308 } 3309 3310 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3311 struct snd_ctl_elem_value *ucontrol) 3312 { 3313 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3314 3315 spin_lock_irq(&hdspm->lock); 3316 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3317 spin_unlock_irq(&hdspm->lock); 3318 return 0; 3319 } 3320 3321 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3322 struct snd_ctl_elem_value *ucontrol) 3323 { 3324 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3325 int change; 3326 unsigned int val; 3327 3328 if (!snd_hdspm_use_is_exclusive(hdspm)) 3329 return -EBUSY; 3330 val = ucontrol->value.integer.value[0] & 1; 3331 spin_lock_irq(&hdspm->lock); 3332 change = (int) val != hdspm_input_select(hdspm); 3333 hdspm_set_input_select(hdspm, val); 3334 spin_unlock_irq(&hdspm->lock); 3335 return change; 3336 } 3337 3338 3339 #define HDSPM_DS_WIRE(xname, xindex) \ 3340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3341 .name = xname, \ 3342 .index = xindex, \ 3343 .info = snd_hdspm_info_ds_wire, \ 3344 .get = snd_hdspm_get_ds_wire, \ 3345 .put = snd_hdspm_put_ds_wire \ 3346 } 3347 3348 static int hdspm_ds_wire(struct hdspm * hdspm) 3349 { 3350 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3351 } 3352 3353 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3354 { 3355 if (ds) 3356 hdspm->control_register |= HDSPM_DS_DoubleWire; 3357 else 3358 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3359 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3360 3361 return 0; 3362 } 3363 3364 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3365 struct snd_ctl_elem_info *uinfo) 3366 { 3367 static const char *const texts[] = { "Single", "Double" }; 3368 ENUMERATED_CTL_INFO(uinfo, texts); 3369 return 0; 3370 } 3371 3372 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3373 struct snd_ctl_elem_value *ucontrol) 3374 { 3375 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3376 3377 spin_lock_irq(&hdspm->lock); 3378 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3379 spin_unlock_irq(&hdspm->lock); 3380 return 0; 3381 } 3382 3383 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3384 struct snd_ctl_elem_value *ucontrol) 3385 { 3386 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3387 int change; 3388 unsigned int val; 3389 3390 if (!snd_hdspm_use_is_exclusive(hdspm)) 3391 return -EBUSY; 3392 val = ucontrol->value.integer.value[0] & 1; 3393 spin_lock_irq(&hdspm->lock); 3394 change = (int) val != hdspm_ds_wire(hdspm); 3395 hdspm_set_ds_wire(hdspm, val); 3396 spin_unlock_irq(&hdspm->lock); 3397 return change; 3398 } 3399 3400 3401 #define HDSPM_QS_WIRE(xname, xindex) \ 3402 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3403 .name = xname, \ 3404 .index = xindex, \ 3405 .info = snd_hdspm_info_qs_wire, \ 3406 .get = snd_hdspm_get_qs_wire, \ 3407 .put = snd_hdspm_put_qs_wire \ 3408 } 3409 3410 static int hdspm_qs_wire(struct hdspm * hdspm) 3411 { 3412 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3413 return 1; 3414 if (hdspm->control_register & HDSPM_QS_QuadWire) 3415 return 2; 3416 return 0; 3417 } 3418 3419 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3420 { 3421 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3422 switch (mode) { 3423 case 0: 3424 break; 3425 case 1: 3426 hdspm->control_register |= HDSPM_QS_DoubleWire; 3427 break; 3428 case 2: 3429 hdspm->control_register |= HDSPM_QS_QuadWire; 3430 break; 3431 } 3432 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3433 3434 return 0; 3435 } 3436 3437 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3438 struct snd_ctl_elem_info *uinfo) 3439 { 3440 static const char *const texts[] = { "Single", "Double", "Quad" }; 3441 ENUMERATED_CTL_INFO(uinfo, texts); 3442 return 0; 3443 } 3444 3445 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3446 struct snd_ctl_elem_value *ucontrol) 3447 { 3448 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3449 3450 spin_lock_irq(&hdspm->lock); 3451 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3452 spin_unlock_irq(&hdspm->lock); 3453 return 0; 3454 } 3455 3456 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3457 struct snd_ctl_elem_value *ucontrol) 3458 { 3459 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3460 int change; 3461 int val; 3462 3463 if (!snd_hdspm_use_is_exclusive(hdspm)) 3464 return -EBUSY; 3465 val = ucontrol->value.integer.value[0]; 3466 if (val < 0) 3467 val = 0; 3468 if (val > 2) 3469 val = 2; 3470 spin_lock_irq(&hdspm->lock); 3471 change = val != hdspm_qs_wire(hdspm); 3472 hdspm_set_qs_wire(hdspm, val); 3473 spin_unlock_irq(&hdspm->lock); 3474 return change; 3475 } 3476 3477 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \ 3478 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3479 .name = xname, \ 3480 .private_value = xindex, \ 3481 .info = snd_hdspm_info_tristate, \ 3482 .get = snd_hdspm_get_tristate, \ 3483 .put = snd_hdspm_put_tristate \ 3484 } 3485 3486 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask) 3487 { 3488 u32 reg = hdspm->settings_register & (regmask * 3); 3489 return reg / regmask; 3490 } 3491 3492 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask) 3493 { 3494 hdspm->settings_register &= ~(regmask * 3); 3495 hdspm->settings_register |= (regmask * mode); 3496 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 3497 3498 return 0; 3499 } 3500 3501 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol, 3502 struct snd_ctl_elem_info *uinfo) 3503 { 3504 u32 regmask = kcontrol->private_value; 3505 3506 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" }; 3507 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" }; 3508 3509 switch (regmask) { 3510 case HDSPM_c0_Input0: 3511 ENUMERATED_CTL_INFO(uinfo, texts_spdif); 3512 break; 3513 default: 3514 ENUMERATED_CTL_INFO(uinfo, texts_levels); 3515 break; 3516 } 3517 return 0; 3518 } 3519 3520 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol, 3521 struct snd_ctl_elem_value *ucontrol) 3522 { 3523 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3524 u32 regmask = kcontrol->private_value; 3525 3526 spin_lock_irq(&hdspm->lock); 3527 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask); 3528 spin_unlock_irq(&hdspm->lock); 3529 return 0; 3530 } 3531 3532 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol, 3533 struct snd_ctl_elem_value *ucontrol) 3534 { 3535 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3536 u32 regmask = kcontrol->private_value; 3537 int change; 3538 int val; 3539 3540 if (!snd_hdspm_use_is_exclusive(hdspm)) 3541 return -EBUSY; 3542 val = ucontrol->value.integer.value[0]; 3543 if (val < 0) 3544 val = 0; 3545 if (val > 2) 3546 val = 2; 3547 3548 spin_lock_irq(&hdspm->lock); 3549 change = val != hdspm_tristate(hdspm, regmask); 3550 hdspm_set_tristate(hdspm, val, regmask); 3551 spin_unlock_irq(&hdspm->lock); 3552 return change; 3553 } 3554 3555 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3556 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3557 .name = xname, \ 3558 .index = xindex, \ 3559 .info = snd_hdspm_info_madi_speedmode, \ 3560 .get = snd_hdspm_get_madi_speedmode, \ 3561 .put = snd_hdspm_put_madi_speedmode \ 3562 } 3563 3564 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3565 { 3566 if (hdspm->control_register & HDSPM_QuadSpeed) 3567 return 2; 3568 if (hdspm->control_register & HDSPM_DoubleSpeed) 3569 return 1; 3570 return 0; 3571 } 3572 3573 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3574 { 3575 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3576 switch (mode) { 3577 case 0: 3578 break; 3579 case 1: 3580 hdspm->control_register |= HDSPM_DoubleSpeed; 3581 break; 3582 case 2: 3583 hdspm->control_register |= HDSPM_QuadSpeed; 3584 break; 3585 } 3586 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3587 3588 return 0; 3589 } 3590 3591 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3592 struct snd_ctl_elem_info *uinfo) 3593 { 3594 static const char *const texts[] = { "Single", "Double", "Quad" }; 3595 ENUMERATED_CTL_INFO(uinfo, texts); 3596 return 0; 3597 } 3598 3599 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3600 struct snd_ctl_elem_value *ucontrol) 3601 { 3602 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3603 3604 spin_lock_irq(&hdspm->lock); 3605 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3606 spin_unlock_irq(&hdspm->lock); 3607 return 0; 3608 } 3609 3610 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3611 struct snd_ctl_elem_value *ucontrol) 3612 { 3613 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3614 int change; 3615 int val; 3616 3617 if (!snd_hdspm_use_is_exclusive(hdspm)) 3618 return -EBUSY; 3619 val = ucontrol->value.integer.value[0]; 3620 if (val < 0) 3621 val = 0; 3622 if (val > 2) 3623 val = 2; 3624 spin_lock_irq(&hdspm->lock); 3625 change = val != hdspm_madi_speedmode(hdspm); 3626 hdspm_set_madi_speedmode(hdspm, val); 3627 spin_unlock_irq(&hdspm->lock); 3628 return change; 3629 } 3630 3631 #define HDSPM_MIXER(xname, xindex) \ 3632 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3633 .name = xname, \ 3634 .index = xindex, \ 3635 .device = 0, \ 3636 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3637 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3638 .info = snd_hdspm_info_mixer, \ 3639 .get = snd_hdspm_get_mixer, \ 3640 .put = snd_hdspm_put_mixer \ 3641 } 3642 3643 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3644 struct snd_ctl_elem_info *uinfo) 3645 { 3646 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3647 uinfo->count = 3; 3648 uinfo->value.integer.min = 0; 3649 uinfo->value.integer.max = 65535; 3650 uinfo->value.integer.step = 1; 3651 return 0; 3652 } 3653 3654 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3655 struct snd_ctl_elem_value *ucontrol) 3656 { 3657 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3658 int source; 3659 int destination; 3660 3661 source = ucontrol->value.integer.value[0]; 3662 if (source < 0) 3663 source = 0; 3664 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3665 source = 2 * HDSPM_MAX_CHANNELS - 1; 3666 3667 destination = ucontrol->value.integer.value[1]; 3668 if (destination < 0) 3669 destination = 0; 3670 else if (destination >= HDSPM_MAX_CHANNELS) 3671 destination = HDSPM_MAX_CHANNELS - 1; 3672 3673 spin_lock_irq(&hdspm->lock); 3674 if (source >= HDSPM_MAX_CHANNELS) 3675 ucontrol->value.integer.value[2] = 3676 hdspm_read_pb_gain(hdspm, destination, 3677 source - HDSPM_MAX_CHANNELS); 3678 else 3679 ucontrol->value.integer.value[2] = 3680 hdspm_read_in_gain(hdspm, destination, source); 3681 3682 spin_unlock_irq(&hdspm->lock); 3683 3684 return 0; 3685 } 3686 3687 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3688 struct snd_ctl_elem_value *ucontrol) 3689 { 3690 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3691 int change; 3692 int source; 3693 int destination; 3694 int gain; 3695 3696 if (!snd_hdspm_use_is_exclusive(hdspm)) 3697 return -EBUSY; 3698 3699 source = ucontrol->value.integer.value[0]; 3700 destination = ucontrol->value.integer.value[1]; 3701 3702 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3703 return -1; 3704 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3705 return -1; 3706 3707 gain = ucontrol->value.integer.value[2]; 3708 3709 spin_lock_irq(&hdspm->lock); 3710 3711 if (source >= HDSPM_MAX_CHANNELS) 3712 change = gain != hdspm_read_pb_gain(hdspm, destination, 3713 source - 3714 HDSPM_MAX_CHANNELS); 3715 else 3716 change = gain != hdspm_read_in_gain(hdspm, destination, 3717 source); 3718 3719 if (change) { 3720 if (source >= HDSPM_MAX_CHANNELS) 3721 hdspm_write_pb_gain(hdspm, destination, 3722 source - HDSPM_MAX_CHANNELS, 3723 gain); 3724 else 3725 hdspm_write_in_gain(hdspm, destination, source, 3726 gain); 3727 } 3728 spin_unlock_irq(&hdspm->lock); 3729 3730 return change; 3731 } 3732 3733 /* The simple mixer control(s) provide gain control for the 3734 basic 1:1 mappings of playback streams to output 3735 streams. 3736 */ 3737 3738 #define HDSPM_PLAYBACK_MIXER \ 3739 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3740 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3741 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3742 .info = snd_hdspm_info_playback_mixer, \ 3743 .get = snd_hdspm_get_playback_mixer, \ 3744 .put = snd_hdspm_put_playback_mixer \ 3745 } 3746 3747 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3748 struct snd_ctl_elem_info *uinfo) 3749 { 3750 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3751 uinfo->count = 1; 3752 uinfo->value.integer.min = 0; 3753 uinfo->value.integer.max = 64; 3754 uinfo->value.integer.step = 1; 3755 return 0; 3756 } 3757 3758 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3759 struct snd_ctl_elem_value *ucontrol) 3760 { 3761 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3762 int channel; 3763 3764 channel = ucontrol->id.index - 1; 3765 3766 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3767 return -EINVAL; 3768 3769 spin_lock_irq(&hdspm->lock); 3770 ucontrol->value.integer.value[0] = 3771 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3772 spin_unlock_irq(&hdspm->lock); 3773 3774 return 0; 3775 } 3776 3777 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3778 struct snd_ctl_elem_value *ucontrol) 3779 { 3780 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3781 int change; 3782 int channel; 3783 int gain; 3784 3785 if (!snd_hdspm_use_is_exclusive(hdspm)) 3786 return -EBUSY; 3787 3788 channel = ucontrol->id.index - 1; 3789 3790 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3791 return -EINVAL; 3792 3793 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3794 3795 spin_lock_irq(&hdspm->lock); 3796 change = 3797 gain != hdspm_read_pb_gain(hdspm, channel, 3798 channel); 3799 if (change) 3800 hdspm_write_pb_gain(hdspm, channel, channel, 3801 gain); 3802 spin_unlock_irq(&hdspm->lock); 3803 return change; 3804 } 3805 3806 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3807 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3808 .name = xname, \ 3809 .private_value = xindex, \ 3810 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3811 .info = snd_hdspm_info_sync_check, \ 3812 .get = snd_hdspm_get_sync_check \ 3813 } 3814 3815 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3816 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3817 .name = xname, \ 3818 .private_value = xindex, \ 3819 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3820 .info = snd_hdspm_tco_info_lock_check, \ 3821 .get = snd_hdspm_get_sync_check \ 3822 } 3823 3824 3825 3826 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3827 struct snd_ctl_elem_info *uinfo) 3828 { 3829 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3830 ENUMERATED_CTL_INFO(uinfo, texts); 3831 return 0; 3832 } 3833 3834 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3835 struct snd_ctl_elem_info *uinfo) 3836 { 3837 static const char *const texts[] = { "No Lock", "Lock" }; 3838 ENUMERATED_CTL_INFO(uinfo, texts); 3839 return 0; 3840 } 3841 3842 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3843 { 3844 int status, status2; 3845 3846 switch (hdspm->io_type) { 3847 case AES32: 3848 status = hdspm_read(hdspm, HDSPM_statusRegister); 3849 if (status & HDSPM_AES32_wcLock) { 3850 if (status & HDSPM_AES32_wcSync) 3851 return 2; 3852 else 3853 return 1; 3854 } 3855 return 0; 3856 break; 3857 3858 case MADI: 3859 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3860 if (status2 & HDSPM_wcLock) { 3861 if (status2 & HDSPM_wcSync) 3862 return 2; 3863 else 3864 return 1; 3865 } 3866 return 0; 3867 break; 3868 3869 case RayDAT: 3870 case AIO: 3871 status = hdspm_read(hdspm, HDSPM_statusRegister); 3872 3873 if (status & 0x2000000) 3874 return 2; 3875 else if (status & 0x1000000) 3876 return 1; 3877 return 0; 3878 3879 break; 3880 3881 case MADIface: 3882 break; 3883 } 3884 3885 3886 return 3; 3887 } 3888 3889 3890 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3891 { 3892 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3893 if (status & HDSPM_madiLock) { 3894 if (status & HDSPM_madiSync) 3895 return 2; 3896 else 3897 return 1; 3898 } 3899 return 0; 3900 } 3901 3902 3903 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3904 { 3905 int status, lock, sync; 3906 3907 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3908 3909 lock = (status & (0x1<<idx)) ? 1 : 0; 3910 sync = (status & (0x100<<idx)) ? 1 : 0; 3911 3912 if (lock && sync) 3913 return 2; 3914 else if (lock) 3915 return 1; 3916 return 0; 3917 } 3918 3919 3920 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3921 { 3922 int status, lock = 0, sync = 0; 3923 3924 switch (hdspm->io_type) { 3925 case RayDAT: 3926 case AIO: 3927 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3928 lock = (status & 0x400) ? 1 : 0; 3929 sync = (status & 0x800) ? 1 : 0; 3930 break; 3931 3932 case MADI: 3933 status = hdspm_read(hdspm, HDSPM_statusRegister); 3934 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3935 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3936 break; 3937 3938 case AES32: 3939 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3940 lock = (status & 0x100000) ? 1 : 0; 3941 sync = (status & 0x200000) ? 1 : 0; 3942 break; 3943 3944 case MADIface: 3945 break; 3946 } 3947 3948 if (lock && sync) 3949 return 2; 3950 else if (lock) 3951 return 1; 3952 3953 return 0; 3954 } 3955 3956 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3957 { 3958 int status2, lock, sync; 3959 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3960 3961 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3962 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3963 3964 if (sync) 3965 return 2; 3966 else if (lock) 3967 return 1; 3968 return 0; 3969 } 3970 3971 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3972 { 3973 u32 status; 3974 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3975 3976 return (status & mask) ? 1 : 0; 3977 } 3978 3979 3980 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3981 { 3982 int status; 3983 3984 if (hdspm->tco) { 3985 switch (hdspm->io_type) { 3986 case MADI: 3987 status = hdspm_read(hdspm, HDSPM_statusRegister); 3988 if (status & HDSPM_tcoLockMadi) { 3989 if (status & HDSPM_tcoSync) 3990 return 2; 3991 else 3992 return 1; 3993 } 3994 return 0; 3995 case AES32: 3996 status = hdspm_read(hdspm, HDSPM_statusRegister); 3997 if (status & HDSPM_tcoLockAes) { 3998 if (status & HDSPM_tcoSync) 3999 return 2; 4000 else 4001 return 1; 4002 } 4003 return 0; 4004 case RayDAT: 4005 case AIO: 4006 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 4007 4008 if (status & 0x8000000) 4009 return 2; /* Sync */ 4010 if (status & 0x4000000) 4011 return 1; /* Lock */ 4012 return 0; /* No signal */ 4013 4014 default: 4015 break; 4016 } 4017 } 4018 4019 return 3; /* N/A */ 4020 } 4021 4022 4023 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 4024 struct snd_ctl_elem_value *ucontrol) 4025 { 4026 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4027 int val = -1; 4028 4029 switch (hdspm->io_type) { 4030 case RayDAT: 4031 switch (kcontrol->private_value) { 4032 case 0: /* WC */ 4033 val = hdspm_wc_sync_check(hdspm); break; 4034 case 7: /* TCO */ 4035 val = hdspm_tco_sync_check(hdspm); break; 4036 case 8: /* SYNC IN */ 4037 val = hdspm_sync_in_sync_check(hdspm); break; 4038 default: 4039 val = hdspm_s1_sync_check(hdspm, 4040 kcontrol->private_value-1); 4041 } 4042 break; 4043 4044 case AIO: 4045 switch (kcontrol->private_value) { 4046 case 0: /* WC */ 4047 val = hdspm_wc_sync_check(hdspm); break; 4048 case 4: /* TCO */ 4049 val = hdspm_tco_sync_check(hdspm); break; 4050 case 5: /* SYNC IN */ 4051 val = hdspm_sync_in_sync_check(hdspm); break; 4052 default: 4053 val = hdspm_s1_sync_check(hdspm, 4054 kcontrol->private_value-1); 4055 } 4056 break; 4057 4058 case MADI: 4059 switch (kcontrol->private_value) { 4060 case 0: /* WC */ 4061 val = hdspm_wc_sync_check(hdspm); break; 4062 case 1: /* MADI */ 4063 val = hdspm_madi_sync_check(hdspm); break; 4064 case 2: /* TCO */ 4065 val = hdspm_tco_sync_check(hdspm); break; 4066 case 3: /* SYNC_IN */ 4067 val = hdspm_sync_in_sync_check(hdspm); break; 4068 } 4069 break; 4070 4071 case MADIface: 4072 val = hdspm_madi_sync_check(hdspm); /* MADI */ 4073 break; 4074 4075 case AES32: 4076 switch (kcontrol->private_value) { 4077 case 0: /* WC */ 4078 val = hdspm_wc_sync_check(hdspm); break; 4079 case 9: /* TCO */ 4080 val = hdspm_tco_sync_check(hdspm); break; 4081 case 10 /* SYNC IN */: 4082 val = hdspm_sync_in_sync_check(hdspm); break; 4083 default: /* AES1 to AES8 */ 4084 val = hdspm_aes_sync_check(hdspm, 4085 kcontrol->private_value-1); 4086 } 4087 break; 4088 4089 } 4090 4091 if (hdspm->tco) { 4092 switch (kcontrol->private_value) { 4093 case 11: 4094 /* Check TCO for lock state of its current input */ 4095 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 4096 break; 4097 case 12: 4098 /* Check TCO for valid time code on LTC input. */ 4099 val = hdspm_tco_input_check(hdspm, 4100 HDSPM_TCO1_LTC_Input_valid); 4101 break; 4102 default: 4103 break; 4104 } 4105 } 4106 4107 if (-1 == val) 4108 val = 3; 4109 4110 ucontrol->value.enumerated.item[0] = val; 4111 return 0; 4112 } 4113 4114 4115 4116 /** 4117 * TCO controls 4118 **/ 4119 static void hdspm_tco_write(struct hdspm *hdspm) 4120 { 4121 unsigned int tc[4] = { 0, 0, 0, 0}; 4122 4123 switch (hdspm->tco->input) { 4124 case 0: 4125 tc[2] |= HDSPM_TCO2_set_input_MSB; 4126 break; 4127 case 1: 4128 tc[2] |= HDSPM_TCO2_set_input_LSB; 4129 break; 4130 default: 4131 break; 4132 } 4133 4134 switch (hdspm->tco->framerate) { 4135 case 1: 4136 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 4137 break; 4138 case 2: 4139 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 4140 break; 4141 case 3: 4142 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 4143 HDSPM_TCO1_set_drop_frame_flag; 4144 break; 4145 case 4: 4146 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4147 HDSPM_TCO1_LTC_Format_MSB; 4148 break; 4149 case 5: 4150 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4151 HDSPM_TCO1_LTC_Format_MSB + 4152 HDSPM_TCO1_set_drop_frame_flag; 4153 break; 4154 default: 4155 break; 4156 } 4157 4158 switch (hdspm->tco->wordclock) { 4159 case 1: 4160 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4161 break; 4162 case 2: 4163 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4164 break; 4165 default: 4166 break; 4167 } 4168 4169 switch (hdspm->tco->samplerate) { 4170 case 1: 4171 tc[2] |= HDSPM_TCO2_set_freq; 4172 break; 4173 case 2: 4174 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4175 break; 4176 default: 4177 break; 4178 } 4179 4180 switch (hdspm->tco->pull) { 4181 case 1: 4182 tc[2] |= HDSPM_TCO2_set_pull_up; 4183 break; 4184 case 2: 4185 tc[2] |= HDSPM_TCO2_set_pull_down; 4186 break; 4187 case 3: 4188 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4189 break; 4190 case 4: 4191 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4192 break; 4193 default: 4194 break; 4195 } 4196 4197 if (1 == hdspm->tco->term) { 4198 tc[2] |= HDSPM_TCO2_set_term_75R; 4199 } 4200 4201 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4202 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4203 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4204 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4205 } 4206 4207 4208 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4209 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4210 .name = xname, \ 4211 .index = xindex, \ 4212 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4213 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4214 .info = snd_hdspm_info_tco_sample_rate, \ 4215 .get = snd_hdspm_get_tco_sample_rate, \ 4216 .put = snd_hdspm_put_tco_sample_rate \ 4217 } 4218 4219 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4220 struct snd_ctl_elem_info *uinfo) 4221 { 4222 /* TODO freq from app could be supported here, see tco->samplerate */ 4223 static const char *const texts[] = { "44.1 kHz", "48 kHz" }; 4224 ENUMERATED_CTL_INFO(uinfo, texts); 4225 return 0; 4226 } 4227 4228 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4229 struct snd_ctl_elem_value *ucontrol) 4230 { 4231 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4232 4233 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4234 4235 return 0; 4236 } 4237 4238 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4239 struct snd_ctl_elem_value *ucontrol) 4240 { 4241 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4242 4243 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4244 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4245 4246 hdspm_tco_write(hdspm); 4247 4248 return 1; 4249 } 4250 4251 return 0; 4252 } 4253 4254 4255 #define HDSPM_TCO_PULL(xname, xindex) \ 4256 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4257 .name = xname, \ 4258 .index = xindex, \ 4259 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4260 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4261 .info = snd_hdspm_info_tco_pull, \ 4262 .get = snd_hdspm_get_tco_pull, \ 4263 .put = snd_hdspm_put_tco_pull \ 4264 } 4265 4266 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4267 struct snd_ctl_elem_info *uinfo) 4268 { 4269 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %", 4270 "+ 4 %", "- 4 %" }; 4271 ENUMERATED_CTL_INFO(uinfo, texts); 4272 return 0; 4273 } 4274 4275 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4276 struct snd_ctl_elem_value *ucontrol) 4277 { 4278 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4279 4280 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4281 4282 return 0; 4283 } 4284 4285 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4286 struct snd_ctl_elem_value *ucontrol) 4287 { 4288 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4289 4290 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4291 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4292 4293 hdspm_tco_write(hdspm); 4294 4295 return 1; 4296 } 4297 4298 return 0; 4299 } 4300 4301 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4302 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4303 .name = xname, \ 4304 .index = xindex, \ 4305 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4306 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4307 .info = snd_hdspm_info_tco_wck_conversion, \ 4308 .get = snd_hdspm_get_tco_wck_conversion, \ 4309 .put = snd_hdspm_put_tco_wck_conversion \ 4310 } 4311 4312 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4313 struct snd_ctl_elem_info *uinfo) 4314 { 4315 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4316 ENUMERATED_CTL_INFO(uinfo, texts); 4317 return 0; 4318 } 4319 4320 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4321 struct snd_ctl_elem_value *ucontrol) 4322 { 4323 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4324 4325 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4326 4327 return 0; 4328 } 4329 4330 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4331 struct snd_ctl_elem_value *ucontrol) 4332 { 4333 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4334 4335 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4336 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4337 4338 hdspm_tco_write(hdspm); 4339 4340 return 1; 4341 } 4342 4343 return 0; 4344 } 4345 4346 4347 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4348 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4349 .name = xname, \ 4350 .index = xindex, \ 4351 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4352 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4353 .info = snd_hdspm_info_tco_frame_rate, \ 4354 .get = snd_hdspm_get_tco_frame_rate, \ 4355 .put = snd_hdspm_put_tco_frame_rate \ 4356 } 4357 4358 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4359 struct snd_ctl_elem_info *uinfo) 4360 { 4361 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps", 4362 "29.97 dfps", "30 fps", "30 dfps" }; 4363 ENUMERATED_CTL_INFO(uinfo, texts); 4364 return 0; 4365 } 4366 4367 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4368 struct snd_ctl_elem_value *ucontrol) 4369 { 4370 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4371 4372 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4373 4374 return 0; 4375 } 4376 4377 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4378 struct snd_ctl_elem_value *ucontrol) 4379 { 4380 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4381 4382 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4383 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4384 4385 hdspm_tco_write(hdspm); 4386 4387 return 1; 4388 } 4389 4390 return 0; 4391 } 4392 4393 4394 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4395 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4396 .name = xname, \ 4397 .index = xindex, \ 4398 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4399 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4400 .info = snd_hdspm_info_tco_sync_source, \ 4401 .get = snd_hdspm_get_tco_sync_source, \ 4402 .put = snd_hdspm_put_tco_sync_source \ 4403 } 4404 4405 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4406 struct snd_ctl_elem_info *uinfo) 4407 { 4408 static const char *const texts[] = { "LTC", "Video", "WCK" }; 4409 ENUMERATED_CTL_INFO(uinfo, texts); 4410 return 0; 4411 } 4412 4413 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4414 struct snd_ctl_elem_value *ucontrol) 4415 { 4416 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4417 4418 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4419 4420 return 0; 4421 } 4422 4423 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4424 struct snd_ctl_elem_value *ucontrol) 4425 { 4426 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4427 4428 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4429 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4430 4431 hdspm_tco_write(hdspm); 4432 4433 return 1; 4434 } 4435 4436 return 0; 4437 } 4438 4439 4440 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4441 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4442 .name = xname, \ 4443 .index = xindex, \ 4444 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4445 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4446 .info = snd_hdspm_info_tco_word_term, \ 4447 .get = snd_hdspm_get_tco_word_term, \ 4448 .put = snd_hdspm_put_tco_word_term \ 4449 } 4450 4451 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4452 struct snd_ctl_elem_info *uinfo) 4453 { 4454 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4455 uinfo->count = 1; 4456 uinfo->value.integer.min = 0; 4457 uinfo->value.integer.max = 1; 4458 4459 return 0; 4460 } 4461 4462 4463 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4464 struct snd_ctl_elem_value *ucontrol) 4465 { 4466 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4467 4468 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4469 4470 return 0; 4471 } 4472 4473 4474 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4475 struct snd_ctl_elem_value *ucontrol) 4476 { 4477 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4478 4479 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4480 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4481 4482 hdspm_tco_write(hdspm); 4483 4484 return 1; 4485 } 4486 4487 return 0; 4488 } 4489 4490 4491 4492 4493 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4494 HDSPM_MIXER("Mixer", 0), 4495 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4496 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4497 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4498 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4499 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4500 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4501 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4502 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4503 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4504 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4505 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4506 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4507 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4508 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4509 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4510 HDSPM_INPUT_SELECT("Input Select", 0), 4511 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4512 }; 4513 4514 4515 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4516 HDSPM_MIXER("Mixer", 0), 4517 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4518 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4519 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4520 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4521 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4522 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4523 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4524 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4525 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4526 }; 4527 4528 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4529 HDSPM_MIXER("Mixer", 0), 4530 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4531 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4532 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4533 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4534 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4535 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4536 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4537 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4538 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4539 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4540 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4541 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4542 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4543 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4544 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4545 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4546 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5), 4547 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0), 4548 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt), 4549 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4550 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1), 4551 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db), 4552 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48), 4553 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0), 4554 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0), 4555 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0) 4556 4557 /* 4558 HDSPM_INPUT_SELECT("Input Select", 0), 4559 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4560 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4561 HDSPM_SPDIF_IN("SPDIF In", 0); 4562 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4563 HDSPM_INPUT_LEVEL("Input Level", 0); 4564 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4565 HDSPM_PHONES("Phones", 0); 4566 */ 4567 }; 4568 4569 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4570 HDSPM_MIXER("Mixer", 0), 4571 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4572 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4573 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4574 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4575 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4576 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4577 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4578 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4579 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4580 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4581 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4582 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4583 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4584 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4585 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4586 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4587 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4588 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4589 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4590 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4591 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4592 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8), 4593 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4594 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48) 4595 }; 4596 4597 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4598 HDSPM_MIXER("Mixer", 0), 4599 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4600 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4601 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4602 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4603 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4604 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11), 4605 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4606 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4607 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4608 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4609 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4610 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4611 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4612 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4613 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4614 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4615 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4616 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4617 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4618 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4619 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4620 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4621 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4622 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4623 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4624 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4625 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4626 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4627 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4628 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4629 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4630 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4631 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4632 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4633 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4634 }; 4635 4636 4637 4638 /* Control elements for the optional TCO module */ 4639 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4640 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4641 HDSPM_TCO_PULL("TCO Pull", 0), 4642 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4643 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4644 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4645 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4646 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4647 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4648 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0), 4649 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0) 4650 }; 4651 4652 4653 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4654 4655 4656 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4657 { 4658 int i; 4659 4660 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4661 if (hdspm->system_sample_rate > 48000) { 4662 hdspm->playback_mixer_ctls[i]->vd[0].access = 4663 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4664 SNDRV_CTL_ELEM_ACCESS_READ | 4665 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4666 } else { 4667 hdspm->playback_mixer_ctls[i]->vd[0].access = 4668 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4669 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4670 } 4671 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4672 SNDRV_CTL_EVENT_MASK_INFO, 4673 &hdspm->playback_mixer_ctls[i]->id); 4674 } 4675 4676 return 0; 4677 } 4678 4679 4680 static int snd_hdspm_create_controls(struct snd_card *card, 4681 struct hdspm *hdspm) 4682 { 4683 unsigned int idx, limit; 4684 int err; 4685 struct snd_kcontrol *kctl; 4686 struct snd_kcontrol_new *list = NULL; 4687 4688 switch (hdspm->io_type) { 4689 case MADI: 4690 list = snd_hdspm_controls_madi; 4691 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4692 break; 4693 case MADIface: 4694 list = snd_hdspm_controls_madiface; 4695 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4696 break; 4697 case AIO: 4698 list = snd_hdspm_controls_aio; 4699 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4700 break; 4701 case RayDAT: 4702 list = snd_hdspm_controls_raydat; 4703 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4704 break; 4705 case AES32: 4706 list = snd_hdspm_controls_aes32; 4707 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4708 break; 4709 } 4710 4711 if (NULL != list) { 4712 for (idx = 0; idx < limit; idx++) { 4713 err = snd_ctl_add(card, 4714 snd_ctl_new1(&list[idx], hdspm)); 4715 if (err < 0) 4716 return err; 4717 } 4718 } 4719 4720 4721 /* create simple 1:1 playback mixer controls */ 4722 snd_hdspm_playback_mixer.name = "Chn"; 4723 if (hdspm->system_sample_rate >= 128000) { 4724 limit = hdspm->qs_out_channels; 4725 } else if (hdspm->system_sample_rate >= 64000) { 4726 limit = hdspm->ds_out_channels; 4727 } else { 4728 limit = hdspm->ss_out_channels; 4729 } 4730 for (idx = 0; idx < limit; ++idx) { 4731 snd_hdspm_playback_mixer.index = idx + 1; 4732 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4733 err = snd_ctl_add(card, kctl); 4734 if (err < 0) 4735 return err; 4736 hdspm->playback_mixer_ctls[idx] = kctl; 4737 } 4738 4739 4740 if (hdspm->tco) { 4741 /* add tco control elements */ 4742 list = snd_hdspm_controls_tco; 4743 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4744 for (idx = 0; idx < limit; idx++) { 4745 err = snd_ctl_add(card, 4746 snd_ctl_new1(&list[idx], hdspm)); 4747 if (err < 0) 4748 return err; 4749 } 4750 } 4751 4752 return 0; 4753 } 4754 4755 /*------------------------------------------------------------ 4756 /proc interface 4757 ------------------------------------------------------------*/ 4758 4759 static void 4760 snd_hdspm_proc_read_tco(struct snd_info_entry *entry, 4761 struct snd_info_buffer *buffer) 4762 { 4763 struct hdspm *hdspm = entry->private_data; 4764 unsigned int status, control; 4765 int a, ltc, frames, seconds, minutes, hours; 4766 unsigned int period; 4767 u64 freq_const = 0; 4768 u32 rate; 4769 4770 snd_iprintf(buffer, "--- TCO ---\n"); 4771 4772 status = hdspm_read(hdspm, HDSPM_statusRegister); 4773 control = hdspm->control_register; 4774 4775 4776 if (status & HDSPM_tco_detect) { 4777 snd_iprintf(buffer, "TCO module detected.\n"); 4778 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4779 if (a & HDSPM_TCO1_LTC_Input_valid) { 4780 snd_iprintf(buffer, " LTC valid, "); 4781 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4782 HDSPM_TCO1_LTC_Format_MSB)) { 4783 case 0: 4784 snd_iprintf(buffer, "24 fps, "); 4785 break; 4786 case HDSPM_TCO1_LTC_Format_LSB: 4787 snd_iprintf(buffer, "25 fps, "); 4788 break; 4789 case HDSPM_TCO1_LTC_Format_MSB: 4790 snd_iprintf(buffer, "29.97 fps, "); 4791 break; 4792 default: 4793 snd_iprintf(buffer, "30 fps, "); 4794 break; 4795 } 4796 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4797 snd_iprintf(buffer, "drop frame\n"); 4798 } else { 4799 snd_iprintf(buffer, "full frame\n"); 4800 } 4801 } else { 4802 snd_iprintf(buffer, " no LTC\n"); 4803 } 4804 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4805 snd_iprintf(buffer, " Video: NTSC\n"); 4806 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4807 snd_iprintf(buffer, " Video: PAL\n"); 4808 } else { 4809 snd_iprintf(buffer, " No video\n"); 4810 } 4811 if (a & HDSPM_TCO1_TCO_lock) { 4812 snd_iprintf(buffer, " Sync: lock\n"); 4813 } else { 4814 snd_iprintf(buffer, " Sync: no lock\n"); 4815 } 4816 4817 switch (hdspm->io_type) { 4818 case MADI: 4819 case AES32: 4820 freq_const = 110069313433624ULL; 4821 break; 4822 case RayDAT: 4823 case AIO: 4824 freq_const = 104857600000000ULL; 4825 break; 4826 case MADIface: 4827 break; /* no TCO possible */ 4828 } 4829 4830 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4831 snd_iprintf(buffer, " period: %u\n", period); 4832 4833 4834 /* rate = freq_const/period; */ 4835 rate = div_u64(freq_const, period); 4836 4837 if (control & HDSPM_QuadSpeed) { 4838 rate *= 4; 4839 } else if (control & HDSPM_DoubleSpeed) { 4840 rate *= 2; 4841 } 4842 4843 snd_iprintf(buffer, " Frequency: %u Hz\n", 4844 (unsigned int) rate); 4845 4846 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4847 frames = ltc & 0xF; 4848 ltc >>= 4; 4849 frames += (ltc & 0x3) * 10; 4850 ltc >>= 4; 4851 seconds = ltc & 0xF; 4852 ltc >>= 4; 4853 seconds += (ltc & 0x7) * 10; 4854 ltc >>= 4; 4855 minutes = ltc & 0xF; 4856 ltc >>= 4; 4857 minutes += (ltc & 0x7) * 10; 4858 ltc >>= 4; 4859 hours = ltc & 0xF; 4860 ltc >>= 4; 4861 hours += (ltc & 0x3) * 10; 4862 snd_iprintf(buffer, 4863 " LTC In: %02d:%02d:%02d:%02d\n", 4864 hours, minutes, seconds, frames); 4865 4866 } else { 4867 snd_iprintf(buffer, "No TCO module detected.\n"); 4868 } 4869 } 4870 4871 static void 4872 snd_hdspm_proc_read_madi(struct snd_info_entry *entry, 4873 struct snd_info_buffer *buffer) 4874 { 4875 struct hdspm *hdspm = entry->private_data; 4876 unsigned int status, status2, control, freq; 4877 4878 char *pref_sync_ref; 4879 char *autosync_ref; 4880 char *system_clock_mode; 4881 char *insel; 4882 int x, x2; 4883 4884 status = hdspm_read(hdspm, HDSPM_statusRegister); 4885 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4886 control = hdspm->control_register; 4887 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4888 4889 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4890 hdspm->card_name, hdspm->card->number + 1, 4891 hdspm->firmware_rev, 4892 (status2 & HDSPM_version0) | 4893 (status2 & HDSPM_version1) | (status2 & 4894 HDSPM_version2)); 4895 4896 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4897 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4898 hdspm->serial); 4899 4900 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4901 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4902 4903 snd_iprintf(buffer, "--- System ---\n"); 4904 4905 snd_iprintf(buffer, 4906 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4907 status & HDSPM_audioIRQPending, 4908 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4909 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4910 hdspm->irq_count); 4911 snd_iprintf(buffer, 4912 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4913 "estimated= %ld (bytes)\n", 4914 ((status & HDSPM_BufferID) ? 1 : 0), 4915 (status & HDSPM_BufferPositionMask), 4916 (status & HDSPM_BufferPositionMask) % 4917 (2 * (int)hdspm->period_bytes), 4918 ((status & HDSPM_BufferPositionMask) - 64) % 4919 (2 * (int)hdspm->period_bytes), 4920 (long) hdspm_hw_pointer(hdspm) * 4); 4921 4922 snd_iprintf(buffer, 4923 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4924 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4925 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4926 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4927 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4928 snd_iprintf(buffer, 4929 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4930 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4931 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4932 snd_iprintf(buffer, 4933 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4934 "status2=0x%x\n", 4935 hdspm->control_register, hdspm->control2_register, 4936 status, status2); 4937 4938 4939 snd_iprintf(buffer, "--- Settings ---\n"); 4940 4941 x = hdspm_get_latency(hdspm); 4942 4943 snd_iprintf(buffer, 4944 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4945 x, (unsigned long) hdspm->period_bytes); 4946 4947 snd_iprintf(buffer, "Line out: %s\n", 4948 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4949 4950 switch (hdspm->control_register & HDSPM_InputMask) { 4951 case HDSPM_InputOptical: 4952 insel = "Optical"; 4953 break; 4954 case HDSPM_InputCoaxial: 4955 insel = "Coaxial"; 4956 break; 4957 default: 4958 insel = "Unknown"; 4959 } 4960 4961 snd_iprintf(buffer, 4962 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4963 "Auto Input %s\n", 4964 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4965 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4966 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4967 4968 4969 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4970 system_clock_mode = "AutoSync"; 4971 else 4972 system_clock_mode = "Master"; 4973 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4974 4975 switch (hdspm_pref_sync_ref(hdspm)) { 4976 case HDSPM_SYNC_FROM_WORD: 4977 pref_sync_ref = "Word Clock"; 4978 break; 4979 case HDSPM_SYNC_FROM_MADI: 4980 pref_sync_ref = "MADI Sync"; 4981 break; 4982 case HDSPM_SYNC_FROM_TCO: 4983 pref_sync_ref = "TCO"; 4984 break; 4985 case HDSPM_SYNC_FROM_SYNC_IN: 4986 pref_sync_ref = "Sync In"; 4987 break; 4988 default: 4989 pref_sync_ref = "XXXX Clock"; 4990 break; 4991 } 4992 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4993 pref_sync_ref); 4994 4995 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4996 hdspm->system_sample_rate); 4997 4998 4999 snd_iprintf(buffer, "--- Status:\n"); 5000 5001 x = status & HDSPM_madiSync; 5002 x2 = status2 & HDSPM_wcSync; 5003 5004 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 5005 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 5006 "NoLock", 5007 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 5008 "NoLock"); 5009 5010 switch (hdspm_autosync_ref(hdspm)) { 5011 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 5012 autosync_ref = "Sync In"; 5013 break; 5014 case HDSPM_AUTOSYNC_FROM_TCO: 5015 autosync_ref = "TCO"; 5016 break; 5017 case HDSPM_AUTOSYNC_FROM_WORD: 5018 autosync_ref = "Word Clock"; 5019 break; 5020 case HDSPM_AUTOSYNC_FROM_MADI: 5021 autosync_ref = "MADI Sync"; 5022 break; 5023 case HDSPM_AUTOSYNC_FROM_NONE: 5024 autosync_ref = "Input not valid"; 5025 break; 5026 default: 5027 autosync_ref = "---"; 5028 break; 5029 } 5030 snd_iprintf(buffer, 5031 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 5032 autosync_ref, hdspm_external_sample_rate(hdspm), 5033 (status & HDSPM_madiFreqMask) >> 22, 5034 (status2 & HDSPM_wcFreqMask) >> 5); 5035 5036 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 5037 (status & HDSPM_AB_int) ? "Coax" : "Optical", 5038 (status & HDSPM_RX_64ch) ? "64 channels" : 5039 "56 channels"); 5040 5041 /* call readout function for TCO specific status */ 5042 snd_hdspm_proc_read_tco(entry, buffer); 5043 5044 snd_iprintf(buffer, "\n"); 5045 } 5046 5047 static void 5048 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 5049 struct snd_info_buffer *buffer) 5050 { 5051 struct hdspm *hdspm = entry->private_data; 5052 unsigned int status; 5053 unsigned int status2; 5054 unsigned int timecode; 5055 unsigned int wcLock, wcSync; 5056 int pref_syncref; 5057 char *autosync_ref; 5058 int x; 5059 5060 status = hdspm_read(hdspm, HDSPM_statusRegister); 5061 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 5062 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 5063 5064 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 5065 hdspm->card_name, hdspm->card->number + 1, 5066 hdspm->firmware_rev); 5067 5068 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 5069 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 5070 5071 snd_iprintf(buffer, "--- System ---\n"); 5072 5073 snd_iprintf(buffer, 5074 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 5075 status & HDSPM_audioIRQPending, 5076 (status & HDSPM_midi0IRQPending) ? 1 : 0, 5077 (status & HDSPM_midi1IRQPending) ? 1 : 0, 5078 hdspm->irq_count); 5079 snd_iprintf(buffer, 5080 "HW pointer: id = %d, rawptr = %d (%d->%d) " 5081 "estimated= %ld (bytes)\n", 5082 ((status & HDSPM_BufferID) ? 1 : 0), 5083 (status & HDSPM_BufferPositionMask), 5084 (status & HDSPM_BufferPositionMask) % 5085 (2 * (int)hdspm->period_bytes), 5086 ((status & HDSPM_BufferPositionMask) - 64) % 5087 (2 * (int)hdspm->period_bytes), 5088 (long) hdspm_hw_pointer(hdspm) * 4); 5089 5090 snd_iprintf(buffer, 5091 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 5092 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 5093 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 5094 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 5095 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 5096 snd_iprintf(buffer, 5097 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 5098 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 5099 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 5100 snd_iprintf(buffer, 5101 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 5102 "status2=0x%x\n", 5103 hdspm->control_register, hdspm->control2_register, 5104 status, status2); 5105 5106 snd_iprintf(buffer, "--- Settings ---\n"); 5107 5108 x = hdspm_get_latency(hdspm); 5109 5110 snd_iprintf(buffer, 5111 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 5112 x, (unsigned long) hdspm->period_bytes); 5113 5114 snd_iprintf(buffer, "Line out: %s\n", 5115 (hdspm-> 5116 control_register & HDSPM_LineOut) ? "on " : "off"); 5117 5118 snd_iprintf(buffer, 5119 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 5120 (hdspm-> 5121 control_register & HDSPM_clr_tms) ? "on" : "off", 5122 (hdspm-> 5123 control_register & HDSPM_Emphasis) ? "on" : "off", 5124 (hdspm-> 5125 control_register & HDSPM_Dolby) ? "on" : "off"); 5126 5127 5128 pref_syncref = hdspm_pref_sync_ref(hdspm); 5129 if (pref_syncref == 0) 5130 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 5131 else 5132 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 5133 pref_syncref); 5134 5135 snd_iprintf(buffer, "System Clock Frequency: %d\n", 5136 hdspm->system_sample_rate); 5137 5138 snd_iprintf(buffer, "Double speed: %s\n", 5139 hdspm->control_register & HDSPM_DS_DoubleWire? 5140 "Double wire" : "Single wire"); 5141 snd_iprintf(buffer, "Quad speed: %s\n", 5142 hdspm->control_register & HDSPM_QS_DoubleWire? 5143 "Double wire" : 5144 hdspm->control_register & HDSPM_QS_QuadWire? 5145 "Quad wire" : "Single wire"); 5146 5147 snd_iprintf(buffer, "--- Status:\n"); 5148 5149 wcLock = status & HDSPM_AES32_wcLock; 5150 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 5151 5152 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5153 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 5154 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5155 5156 for (x = 0; x < 8; x++) { 5157 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5158 x+1, 5159 (status2 & (HDSPM_LockAES >> x)) ? 5160 "Sync " : "No Lock", 5161 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5162 } 5163 5164 switch (hdspm_autosync_ref(hdspm)) { 5165 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5166 autosync_ref = "None"; break; 5167 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5168 autosync_ref = "Word Clock"; break; 5169 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5170 autosync_ref = "AES1"; break; 5171 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5172 autosync_ref = "AES2"; break; 5173 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5174 autosync_ref = "AES3"; break; 5175 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5176 autosync_ref = "AES4"; break; 5177 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5178 autosync_ref = "AES5"; break; 5179 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5180 autosync_ref = "AES6"; break; 5181 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5182 autosync_ref = "AES7"; break; 5183 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5184 autosync_ref = "AES8"; break; 5185 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 5186 autosync_ref = "TCO"; break; 5187 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN: 5188 autosync_ref = "Sync In"; break; 5189 default: 5190 autosync_ref = "---"; break; 5191 } 5192 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5193 5194 /* call readout function for TCO specific status */ 5195 snd_hdspm_proc_read_tco(entry, buffer); 5196 5197 snd_iprintf(buffer, "\n"); 5198 } 5199 5200 static void 5201 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5202 struct snd_info_buffer *buffer) 5203 { 5204 struct hdspm *hdspm = entry->private_data; 5205 unsigned int status1, status2, status3, control, i; 5206 unsigned int lock, sync; 5207 5208 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5209 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5210 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5211 5212 control = hdspm->control_register; 5213 5214 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5215 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5216 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5217 5218 5219 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5220 5221 snd_iprintf(buffer, "Clock mode : %s\n", 5222 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5223 snd_iprintf(buffer, "System frequency: %d Hz\n", 5224 hdspm_get_system_sample_rate(hdspm)); 5225 5226 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5227 5228 lock = 0x1; 5229 sync = 0x100; 5230 5231 for (i = 0; i < 8; i++) { 5232 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5233 i, 5234 (status1 & lock) ? 1 : 0, 5235 (status1 & sync) ? 1 : 0, 5236 texts_freq[(status2 >> (i * 4)) & 0xF]); 5237 5238 lock = lock<<1; 5239 sync = sync<<1; 5240 } 5241 5242 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5243 (status1 & 0x1000000) ? 1 : 0, 5244 (status1 & 0x2000000) ? 1 : 0, 5245 texts_freq[(status1 >> 16) & 0xF]); 5246 5247 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5248 (status1 & 0x4000000) ? 1 : 0, 5249 (status1 & 0x8000000) ? 1 : 0, 5250 texts_freq[(status1 >> 20) & 0xF]); 5251 5252 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5253 (status3 & 0x400) ? 1 : 0, 5254 (status3 & 0x800) ? 1 : 0, 5255 texts_freq[(status2 >> 12) & 0xF]); 5256 5257 } 5258 5259 #ifdef CONFIG_SND_DEBUG 5260 static void 5261 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5262 struct snd_info_buffer *buffer) 5263 { 5264 struct hdspm *hdspm = entry->private_data; 5265 5266 int j,i; 5267 5268 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5269 snd_iprintf(buffer, "0x%08X: ", i); 5270 for (j = 0; j < 16; j += 4) 5271 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5272 snd_iprintf(buffer, "\n"); 5273 } 5274 } 5275 #endif 5276 5277 5278 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5279 struct snd_info_buffer *buffer) 5280 { 5281 struct hdspm *hdspm = entry->private_data; 5282 int i; 5283 5284 snd_iprintf(buffer, "# generated by hdspm\n"); 5285 5286 for (i = 0; i < hdspm->max_channels_in; i++) { 5287 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5288 } 5289 } 5290 5291 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5292 struct snd_info_buffer *buffer) 5293 { 5294 struct hdspm *hdspm = entry->private_data; 5295 int i; 5296 5297 snd_iprintf(buffer, "# generated by hdspm\n"); 5298 5299 for (i = 0; i < hdspm->max_channels_out; i++) { 5300 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5301 } 5302 } 5303 5304 5305 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5306 { 5307 struct snd_info_entry *entry; 5308 5309 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5310 switch (hdspm->io_type) { 5311 case AES32: 5312 snd_info_set_text_ops(entry, hdspm, 5313 snd_hdspm_proc_read_aes32); 5314 break; 5315 case MADI: 5316 snd_info_set_text_ops(entry, hdspm, 5317 snd_hdspm_proc_read_madi); 5318 break; 5319 case MADIface: 5320 /* snd_info_set_text_ops(entry, hdspm, 5321 snd_hdspm_proc_read_madiface); */ 5322 break; 5323 case RayDAT: 5324 snd_info_set_text_ops(entry, hdspm, 5325 snd_hdspm_proc_read_raydat); 5326 break; 5327 case AIO: 5328 break; 5329 } 5330 } 5331 5332 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5333 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5334 } 5335 5336 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5337 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5338 } 5339 5340 #ifdef CONFIG_SND_DEBUG 5341 /* debug file to read all hdspm registers */ 5342 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5343 snd_info_set_text_ops(entry, hdspm, 5344 snd_hdspm_proc_read_debug); 5345 #endif 5346 } 5347 5348 /*------------------------------------------------------------ 5349 hdspm intitialize 5350 ------------------------------------------------------------*/ 5351 5352 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5353 { 5354 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5355 hold it (e.g. during module initialization). 5356 */ 5357 5358 /* set defaults: */ 5359 5360 hdspm->settings_register = 0; 5361 5362 switch (hdspm->io_type) { 5363 case MADI: 5364 case MADIface: 5365 hdspm->control_register = 5366 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5367 break; 5368 5369 case RayDAT: 5370 case AIO: 5371 hdspm->settings_register = 0x1 + 0x1000; 5372 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5373 * line_out */ 5374 hdspm->control_register = 5375 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5376 break; 5377 5378 case AES32: 5379 hdspm->control_register = 5380 HDSPM_ClockModeMaster | /* Master Clock Mode on */ 5381 hdspm_encode_latency(7) | /* latency max=8192samples */ 5382 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5383 HDSPM_LineOut | /* Analog output in */ 5384 HDSPM_Professional; /* Professional mode */ 5385 break; 5386 } 5387 5388 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5389 5390 if (AES32 == hdspm->io_type) { 5391 /* No control2 register for AES32 */ 5392 #ifdef SNDRV_BIG_ENDIAN 5393 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5394 #else 5395 hdspm->control2_register = 0; 5396 #endif 5397 5398 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5399 } 5400 hdspm_compute_period_size(hdspm); 5401 5402 /* silence everything */ 5403 5404 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5405 5406 if (hdspm_is_raydat_or_aio(hdspm)) 5407 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5408 5409 /* set a default rate so that the channel map is set up. */ 5410 hdspm_set_rate(hdspm, 48000, 1); 5411 5412 return 0; 5413 } 5414 5415 5416 /*------------------------------------------------------------ 5417 interrupt 5418 ------------------------------------------------------------*/ 5419 5420 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5421 { 5422 struct hdspm *hdspm = (struct hdspm *) dev_id; 5423 unsigned int status; 5424 int i, audio, midi, schedule = 0; 5425 /* cycles_t now; */ 5426 5427 status = hdspm_read(hdspm, HDSPM_statusRegister); 5428 5429 audio = status & HDSPM_audioIRQPending; 5430 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5431 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5432 5433 /* now = get_cycles(); */ 5434 /** 5435 * LAT_2..LAT_0 period counter (win) counter (mac) 5436 * 6 4096 ~256053425 ~514672358 5437 * 5 2048 ~128024983 ~257373821 5438 * 4 1024 ~64023706 ~128718089 5439 * 3 512 ~32005945 ~64385999 5440 * 2 256 ~16003039 ~32260176 5441 * 1 128 ~7998738 ~16194507 5442 * 0 64 ~3998231 ~8191558 5443 **/ 5444 /* 5445 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n", 5446 now-hdspm->last_interrupt, status & 0xFFC0); 5447 hdspm->last_interrupt = now; 5448 */ 5449 5450 if (!audio && !midi) 5451 return IRQ_NONE; 5452 5453 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5454 hdspm->irq_count++; 5455 5456 5457 if (audio) { 5458 if (hdspm->capture_substream) 5459 snd_pcm_period_elapsed(hdspm->capture_substream); 5460 5461 if (hdspm->playback_substream) 5462 snd_pcm_period_elapsed(hdspm->playback_substream); 5463 } 5464 5465 if (midi) { 5466 i = 0; 5467 while (i < hdspm->midiPorts) { 5468 if ((hdspm_read(hdspm, 5469 hdspm->midi[i].statusIn) & 0xff) && 5470 (status & hdspm->midi[i].irq)) { 5471 /* we disable interrupts for this input until 5472 * processing is done 5473 */ 5474 hdspm->control_register &= ~hdspm->midi[i].ie; 5475 hdspm_write(hdspm, HDSPM_controlRegister, 5476 hdspm->control_register); 5477 hdspm->midi[i].pending = 1; 5478 schedule = 1; 5479 } 5480 5481 i++; 5482 } 5483 5484 if (schedule) 5485 tasklet_hi_schedule(&hdspm->midi_tasklet); 5486 } 5487 5488 return IRQ_HANDLED; 5489 } 5490 5491 /*------------------------------------------------------------ 5492 pcm interface 5493 ------------------------------------------------------------*/ 5494 5495 5496 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5497 *substream) 5498 { 5499 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5500 return hdspm_hw_pointer(hdspm); 5501 } 5502 5503 5504 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5505 { 5506 struct snd_pcm_runtime *runtime = substream->runtime; 5507 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5508 struct snd_pcm_substream *other; 5509 5510 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5511 other = hdspm->capture_substream; 5512 else 5513 other = hdspm->playback_substream; 5514 5515 if (hdspm->running) 5516 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5517 else 5518 runtime->status->hw_ptr = 0; 5519 if (other) { 5520 struct snd_pcm_substream *s; 5521 struct snd_pcm_runtime *oruntime = other->runtime; 5522 snd_pcm_group_for_each_entry(s, substream) { 5523 if (s == other) { 5524 oruntime->status->hw_ptr = 5525 runtime->status->hw_ptr; 5526 break; 5527 } 5528 } 5529 } 5530 return 0; 5531 } 5532 5533 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5534 struct snd_pcm_hw_params *params) 5535 { 5536 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5537 int err; 5538 int i; 5539 pid_t this_pid; 5540 pid_t other_pid; 5541 5542 spin_lock_irq(&hdspm->lock); 5543 5544 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5545 this_pid = hdspm->playback_pid; 5546 other_pid = hdspm->capture_pid; 5547 } else { 5548 this_pid = hdspm->capture_pid; 5549 other_pid = hdspm->playback_pid; 5550 } 5551 5552 if (other_pid > 0 && this_pid != other_pid) { 5553 5554 /* The other stream is open, and not by the same 5555 task as this one. Make sure that the parameters 5556 that matter are the same. 5557 */ 5558 5559 if (params_rate(params) != hdspm->system_sample_rate) { 5560 spin_unlock_irq(&hdspm->lock); 5561 _snd_pcm_hw_param_setempty(params, 5562 SNDRV_PCM_HW_PARAM_RATE); 5563 return -EBUSY; 5564 } 5565 5566 if (params_period_size(params) != hdspm->period_bytes / 4) { 5567 spin_unlock_irq(&hdspm->lock); 5568 _snd_pcm_hw_param_setempty(params, 5569 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5570 return -EBUSY; 5571 } 5572 5573 } 5574 /* We're fine. */ 5575 spin_unlock_irq(&hdspm->lock); 5576 5577 /* how to make sure that the rate matches an externally-set one ? */ 5578 5579 spin_lock_irq(&hdspm->lock); 5580 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5581 if (err < 0) { 5582 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err); 5583 spin_unlock_irq(&hdspm->lock); 5584 _snd_pcm_hw_param_setempty(params, 5585 SNDRV_PCM_HW_PARAM_RATE); 5586 return err; 5587 } 5588 spin_unlock_irq(&hdspm->lock); 5589 5590 err = hdspm_set_interrupt_interval(hdspm, 5591 params_period_size(params)); 5592 if (err < 0) { 5593 dev_info(hdspm->card->dev, 5594 "err on hdspm_set_interrupt_interval: %d\n", err); 5595 _snd_pcm_hw_param_setempty(params, 5596 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5597 return err; 5598 } 5599 5600 /* Memory allocation, takashi's method, dont know if we should 5601 * spinlock 5602 */ 5603 /* malloc all buffer even if not enabled to get sure */ 5604 /* Update for MADI rev 204: we need to allocate for all channels, 5605 * otherwise it doesn't work at 96kHz */ 5606 5607 err = 5608 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5609 if (err < 0) { 5610 dev_info(hdspm->card->dev, 5611 "err on snd_pcm_lib_malloc_pages: %d\n", err); 5612 return err; 5613 } 5614 5615 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5616 5617 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5618 params_channels(params)); 5619 5620 for (i = 0; i < params_channels(params); ++i) 5621 snd_hdspm_enable_out(hdspm, i, 1); 5622 5623 hdspm->playback_buffer = 5624 (unsigned char *) substream->runtime->dma_area; 5625 dev_dbg(hdspm->card->dev, 5626 "Allocated sample buffer for playback at %p\n", 5627 hdspm->playback_buffer); 5628 } else { 5629 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5630 params_channels(params)); 5631 5632 for (i = 0; i < params_channels(params); ++i) 5633 snd_hdspm_enable_in(hdspm, i, 1); 5634 5635 hdspm->capture_buffer = 5636 (unsigned char *) substream->runtime->dma_area; 5637 dev_dbg(hdspm->card->dev, 5638 "Allocated sample buffer for capture at %p\n", 5639 hdspm->capture_buffer); 5640 } 5641 5642 /* 5643 dev_dbg(hdspm->card->dev, 5644 "Allocated sample buffer for %s at 0x%08X\n", 5645 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5646 "playback" : "capture", 5647 snd_pcm_sgbuf_get_addr(substream, 0)); 5648 */ 5649 /* 5650 dev_dbg(hdspm->card->dev, 5651 "set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5652 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5653 "playback" : "capture", 5654 params_rate(params), params_channels(params), 5655 params_buffer_size(params)); 5656 */ 5657 5658 5659 /* For AES cards, the float format bit is the same as the 5660 * preferred sync reference. Since we don't want to break 5661 * sync settings, we have to skip the remaining part of this 5662 * function. 5663 */ 5664 if (hdspm->io_type == AES32) { 5665 return 0; 5666 } 5667 5668 5669 /* Switch to native float format if requested */ 5670 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5671 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5672 dev_info(hdspm->card->dev, 5673 "Switching to native 32bit LE float format.\n"); 5674 5675 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5676 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5677 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5678 dev_info(hdspm->card->dev, 5679 "Switching to native 32bit LE integer format.\n"); 5680 5681 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5682 } 5683 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5684 5685 return 0; 5686 } 5687 5688 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5689 { 5690 int i; 5691 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5692 5693 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5694 5695 /* params_channels(params) should be enough, 5696 but to get sure in case of error */ 5697 for (i = 0; i < hdspm->max_channels_out; ++i) 5698 snd_hdspm_enable_out(hdspm, i, 0); 5699 5700 hdspm->playback_buffer = NULL; 5701 } else { 5702 for (i = 0; i < hdspm->max_channels_in; ++i) 5703 snd_hdspm_enable_in(hdspm, i, 0); 5704 5705 hdspm->capture_buffer = NULL; 5706 5707 } 5708 5709 snd_pcm_lib_free_pages(substream); 5710 5711 return 0; 5712 } 5713 5714 5715 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5716 struct snd_pcm_channel_info *info) 5717 { 5718 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5719 5720 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5721 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5722 dev_info(hdspm->card->dev, 5723 "snd_hdspm_channel_info: output channel out of range (%d)\n", 5724 info->channel); 5725 return -EINVAL; 5726 } 5727 5728 if (hdspm->channel_map_out[info->channel] < 0) { 5729 dev_info(hdspm->card->dev, 5730 "snd_hdspm_channel_info: output channel %d mapped out\n", 5731 info->channel); 5732 return -EINVAL; 5733 } 5734 5735 info->offset = hdspm->channel_map_out[info->channel] * 5736 HDSPM_CHANNEL_BUFFER_BYTES; 5737 } else { 5738 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5739 dev_info(hdspm->card->dev, 5740 "snd_hdspm_channel_info: input channel out of range (%d)\n", 5741 info->channel); 5742 return -EINVAL; 5743 } 5744 5745 if (hdspm->channel_map_in[info->channel] < 0) { 5746 dev_info(hdspm->card->dev, 5747 "snd_hdspm_channel_info: input channel %d mapped out\n", 5748 info->channel); 5749 return -EINVAL; 5750 } 5751 5752 info->offset = hdspm->channel_map_in[info->channel] * 5753 HDSPM_CHANNEL_BUFFER_BYTES; 5754 } 5755 5756 info->first = 0; 5757 info->step = 32; 5758 return 0; 5759 } 5760 5761 5762 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5763 unsigned int cmd, void *arg) 5764 { 5765 switch (cmd) { 5766 case SNDRV_PCM_IOCTL1_RESET: 5767 return snd_hdspm_reset(substream); 5768 5769 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5770 { 5771 struct snd_pcm_channel_info *info = arg; 5772 return snd_hdspm_channel_info(substream, info); 5773 } 5774 default: 5775 break; 5776 } 5777 5778 return snd_pcm_lib_ioctl(substream, cmd, arg); 5779 } 5780 5781 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5782 { 5783 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5784 struct snd_pcm_substream *other; 5785 int running; 5786 5787 spin_lock(&hdspm->lock); 5788 running = hdspm->running; 5789 switch (cmd) { 5790 case SNDRV_PCM_TRIGGER_START: 5791 running |= 1 << substream->stream; 5792 break; 5793 case SNDRV_PCM_TRIGGER_STOP: 5794 running &= ~(1 << substream->stream); 5795 break; 5796 default: 5797 snd_BUG(); 5798 spin_unlock(&hdspm->lock); 5799 return -EINVAL; 5800 } 5801 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5802 other = hdspm->capture_substream; 5803 else 5804 other = hdspm->playback_substream; 5805 5806 if (other) { 5807 struct snd_pcm_substream *s; 5808 snd_pcm_group_for_each_entry(s, substream) { 5809 if (s == other) { 5810 snd_pcm_trigger_done(s, substream); 5811 if (cmd == SNDRV_PCM_TRIGGER_START) 5812 running |= 1 << s->stream; 5813 else 5814 running &= ~(1 << s->stream); 5815 goto _ok; 5816 } 5817 } 5818 if (cmd == SNDRV_PCM_TRIGGER_START) { 5819 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5820 && substream->stream == 5821 SNDRV_PCM_STREAM_CAPTURE) 5822 hdspm_silence_playback(hdspm); 5823 } else { 5824 if (running && 5825 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5826 hdspm_silence_playback(hdspm); 5827 } 5828 } else { 5829 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5830 hdspm_silence_playback(hdspm); 5831 } 5832 _ok: 5833 snd_pcm_trigger_done(substream, substream); 5834 if (!hdspm->running && running) 5835 hdspm_start_audio(hdspm); 5836 else if (hdspm->running && !running) 5837 hdspm_stop_audio(hdspm); 5838 hdspm->running = running; 5839 spin_unlock(&hdspm->lock); 5840 5841 return 0; 5842 } 5843 5844 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5845 { 5846 return 0; 5847 } 5848 5849 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5850 .info = (SNDRV_PCM_INFO_MMAP | 5851 SNDRV_PCM_INFO_MMAP_VALID | 5852 SNDRV_PCM_INFO_NONINTERLEAVED | 5853 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5854 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5855 .rates = (SNDRV_PCM_RATE_32000 | 5856 SNDRV_PCM_RATE_44100 | 5857 SNDRV_PCM_RATE_48000 | 5858 SNDRV_PCM_RATE_64000 | 5859 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5860 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5861 .rate_min = 32000, 5862 .rate_max = 192000, 5863 .channels_min = 1, 5864 .channels_max = HDSPM_MAX_CHANNELS, 5865 .buffer_bytes_max = 5866 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5867 .period_bytes_min = (32 * 4), 5868 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5869 .periods_min = 2, 5870 .periods_max = 512, 5871 .fifo_size = 0 5872 }; 5873 5874 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5875 .info = (SNDRV_PCM_INFO_MMAP | 5876 SNDRV_PCM_INFO_MMAP_VALID | 5877 SNDRV_PCM_INFO_NONINTERLEAVED | 5878 SNDRV_PCM_INFO_SYNC_START), 5879 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5880 .rates = (SNDRV_PCM_RATE_32000 | 5881 SNDRV_PCM_RATE_44100 | 5882 SNDRV_PCM_RATE_48000 | 5883 SNDRV_PCM_RATE_64000 | 5884 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5885 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5886 .rate_min = 32000, 5887 .rate_max = 192000, 5888 .channels_min = 1, 5889 .channels_max = HDSPM_MAX_CHANNELS, 5890 .buffer_bytes_max = 5891 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5892 .period_bytes_min = (32 * 4), 5893 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5894 .periods_min = 2, 5895 .periods_max = 512, 5896 .fifo_size = 0 5897 }; 5898 5899 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5900 struct snd_pcm_hw_rule *rule) 5901 { 5902 struct hdspm *hdspm = rule->private; 5903 struct snd_interval *c = 5904 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5905 struct snd_interval *r = 5906 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5907 5908 if (r->min > 96000 && r->max <= 192000) { 5909 struct snd_interval t = { 5910 .min = hdspm->qs_in_channels, 5911 .max = hdspm->qs_in_channels, 5912 .integer = 1, 5913 }; 5914 return snd_interval_refine(c, &t); 5915 } else if (r->min > 48000 && r->max <= 96000) { 5916 struct snd_interval t = { 5917 .min = hdspm->ds_in_channels, 5918 .max = hdspm->ds_in_channels, 5919 .integer = 1, 5920 }; 5921 return snd_interval_refine(c, &t); 5922 } else if (r->max < 64000) { 5923 struct snd_interval t = { 5924 .min = hdspm->ss_in_channels, 5925 .max = hdspm->ss_in_channels, 5926 .integer = 1, 5927 }; 5928 return snd_interval_refine(c, &t); 5929 } 5930 5931 return 0; 5932 } 5933 5934 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5935 struct snd_pcm_hw_rule * rule) 5936 { 5937 struct hdspm *hdspm = rule->private; 5938 struct snd_interval *c = 5939 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5940 struct snd_interval *r = 5941 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5942 5943 if (r->min > 96000 && r->max <= 192000) { 5944 struct snd_interval t = { 5945 .min = hdspm->qs_out_channels, 5946 .max = hdspm->qs_out_channels, 5947 .integer = 1, 5948 }; 5949 return snd_interval_refine(c, &t); 5950 } else if (r->min > 48000 && r->max <= 96000) { 5951 struct snd_interval t = { 5952 .min = hdspm->ds_out_channels, 5953 .max = hdspm->ds_out_channels, 5954 .integer = 1, 5955 }; 5956 return snd_interval_refine(c, &t); 5957 } else if (r->max < 64000) { 5958 struct snd_interval t = { 5959 .min = hdspm->ss_out_channels, 5960 .max = hdspm->ss_out_channels, 5961 .integer = 1, 5962 }; 5963 return snd_interval_refine(c, &t); 5964 } else { 5965 } 5966 return 0; 5967 } 5968 5969 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5970 struct snd_pcm_hw_rule * rule) 5971 { 5972 struct hdspm *hdspm = rule->private; 5973 struct snd_interval *c = 5974 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5975 struct snd_interval *r = 5976 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5977 5978 if (c->min >= hdspm->ss_in_channels) { 5979 struct snd_interval t = { 5980 .min = 32000, 5981 .max = 48000, 5982 .integer = 1, 5983 }; 5984 return snd_interval_refine(r, &t); 5985 } else if (c->max <= hdspm->qs_in_channels) { 5986 struct snd_interval t = { 5987 .min = 128000, 5988 .max = 192000, 5989 .integer = 1, 5990 }; 5991 return snd_interval_refine(r, &t); 5992 } else if (c->max <= hdspm->ds_in_channels) { 5993 struct snd_interval t = { 5994 .min = 64000, 5995 .max = 96000, 5996 .integer = 1, 5997 }; 5998 return snd_interval_refine(r, &t); 5999 } 6000 6001 return 0; 6002 } 6003 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 6004 struct snd_pcm_hw_rule *rule) 6005 { 6006 struct hdspm *hdspm = rule->private; 6007 struct snd_interval *c = 6008 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 6009 struct snd_interval *r = 6010 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 6011 6012 if (c->min >= hdspm->ss_out_channels) { 6013 struct snd_interval t = { 6014 .min = 32000, 6015 .max = 48000, 6016 .integer = 1, 6017 }; 6018 return snd_interval_refine(r, &t); 6019 } else if (c->max <= hdspm->qs_out_channels) { 6020 struct snd_interval t = { 6021 .min = 128000, 6022 .max = 192000, 6023 .integer = 1, 6024 }; 6025 return snd_interval_refine(r, &t); 6026 } else if (c->max <= hdspm->ds_out_channels) { 6027 struct snd_interval t = { 6028 .min = 64000, 6029 .max = 96000, 6030 .integer = 1, 6031 }; 6032 return snd_interval_refine(r, &t); 6033 } 6034 6035 return 0; 6036 } 6037 6038 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 6039 struct snd_pcm_hw_rule *rule) 6040 { 6041 unsigned int list[3]; 6042 struct hdspm *hdspm = rule->private; 6043 struct snd_interval *c = hw_param_interval(params, 6044 SNDRV_PCM_HW_PARAM_CHANNELS); 6045 6046 list[0] = hdspm->qs_in_channels; 6047 list[1] = hdspm->ds_in_channels; 6048 list[2] = hdspm->ss_in_channels; 6049 return snd_interval_list(c, 3, list, 0); 6050 } 6051 6052 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 6053 struct snd_pcm_hw_rule *rule) 6054 { 6055 unsigned int list[3]; 6056 struct hdspm *hdspm = rule->private; 6057 struct snd_interval *c = hw_param_interval(params, 6058 SNDRV_PCM_HW_PARAM_CHANNELS); 6059 6060 list[0] = hdspm->qs_out_channels; 6061 list[1] = hdspm->ds_out_channels; 6062 list[2] = hdspm->ss_out_channels; 6063 return snd_interval_list(c, 3, list, 0); 6064 } 6065 6066 6067 static unsigned int hdspm_aes32_sample_rates[] = { 6068 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 6069 }; 6070 6071 static struct snd_pcm_hw_constraint_list 6072 hdspm_hw_constraints_aes32_sample_rates = { 6073 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 6074 .list = hdspm_aes32_sample_rates, 6075 .mask = 0 6076 }; 6077 6078 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 6079 { 6080 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6081 struct snd_pcm_runtime *runtime = substream->runtime; 6082 6083 spin_lock_irq(&hdspm->lock); 6084 6085 snd_pcm_set_sync(substream); 6086 6087 6088 runtime->hw = snd_hdspm_playback_subinfo; 6089 6090 if (hdspm->capture_substream == NULL) 6091 hdspm_stop_audio(hdspm); 6092 6093 hdspm->playback_pid = current->pid; 6094 hdspm->playback_substream = substream; 6095 6096 spin_unlock_irq(&hdspm->lock); 6097 6098 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6099 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6100 6101 switch (hdspm->io_type) { 6102 case AIO: 6103 case RayDAT: 6104 snd_pcm_hw_constraint_minmax(runtime, 6105 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6106 32, 4096); 6107 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 6108 snd_pcm_hw_constraint_minmax(runtime, 6109 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6110 16384, 16384); 6111 break; 6112 6113 default: 6114 snd_pcm_hw_constraint_minmax(runtime, 6115 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6116 64, 8192); 6117 break; 6118 } 6119 6120 if (AES32 == hdspm->io_type) { 6121 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 6122 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6123 &hdspm_hw_constraints_aes32_sample_rates); 6124 } else { 6125 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6126 snd_hdspm_hw_rule_rate_out_channels, hdspm, 6127 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6128 } 6129 6130 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6131 snd_hdspm_hw_rule_out_channels, hdspm, 6132 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6133 6134 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6135 snd_hdspm_hw_rule_out_channels_rate, hdspm, 6136 SNDRV_PCM_HW_PARAM_RATE, -1); 6137 6138 return 0; 6139 } 6140 6141 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 6142 { 6143 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6144 6145 spin_lock_irq(&hdspm->lock); 6146 6147 hdspm->playback_pid = -1; 6148 hdspm->playback_substream = NULL; 6149 6150 spin_unlock_irq(&hdspm->lock); 6151 6152 return 0; 6153 } 6154 6155 6156 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 6157 { 6158 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6159 struct snd_pcm_runtime *runtime = substream->runtime; 6160 6161 spin_lock_irq(&hdspm->lock); 6162 snd_pcm_set_sync(substream); 6163 runtime->hw = snd_hdspm_capture_subinfo; 6164 6165 if (hdspm->playback_substream == NULL) 6166 hdspm_stop_audio(hdspm); 6167 6168 hdspm->capture_pid = current->pid; 6169 hdspm->capture_substream = substream; 6170 6171 spin_unlock_irq(&hdspm->lock); 6172 6173 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6174 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6175 6176 switch (hdspm->io_type) { 6177 case AIO: 6178 case RayDAT: 6179 snd_pcm_hw_constraint_minmax(runtime, 6180 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6181 32, 4096); 6182 snd_pcm_hw_constraint_minmax(runtime, 6183 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6184 16384, 16384); 6185 break; 6186 6187 default: 6188 snd_pcm_hw_constraint_minmax(runtime, 6189 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6190 64, 8192); 6191 break; 6192 } 6193 6194 if (AES32 == hdspm->io_type) { 6195 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 6196 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6197 &hdspm_hw_constraints_aes32_sample_rates); 6198 } else { 6199 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6200 snd_hdspm_hw_rule_rate_in_channels, hdspm, 6201 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6202 } 6203 6204 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6205 snd_hdspm_hw_rule_in_channels, hdspm, 6206 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6207 6208 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6209 snd_hdspm_hw_rule_in_channels_rate, hdspm, 6210 SNDRV_PCM_HW_PARAM_RATE, -1); 6211 6212 return 0; 6213 } 6214 6215 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 6216 { 6217 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6218 6219 spin_lock_irq(&hdspm->lock); 6220 6221 hdspm->capture_pid = -1; 6222 hdspm->capture_substream = NULL; 6223 6224 spin_unlock_irq(&hdspm->lock); 6225 return 0; 6226 } 6227 6228 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6229 { 6230 /* we have nothing to initialize but the call is required */ 6231 return 0; 6232 } 6233 6234 static inline int copy_u32_le(void __user *dest, void __iomem *src) 6235 { 6236 u32 val = readl(src); 6237 return copy_to_user(dest, &val, 4); 6238 } 6239 6240 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6241 unsigned int cmd, unsigned long arg) 6242 { 6243 void __user *argp = (void __user *)arg; 6244 struct hdspm *hdspm = hw->private_data; 6245 struct hdspm_mixer_ioctl mixer; 6246 struct hdspm_config info; 6247 struct hdspm_status status; 6248 struct hdspm_version hdspm_version; 6249 struct hdspm_peak_rms *levels; 6250 struct hdspm_ltc ltc; 6251 unsigned int statusregister; 6252 long unsigned int s; 6253 int i = 0; 6254 6255 switch (cmd) { 6256 6257 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6258 levels = &hdspm->peak_rms; 6259 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6260 levels->input_peaks[i] = 6261 readl(hdspm->iobase + 6262 HDSPM_MADI_INPUT_PEAK + i*4); 6263 levels->playback_peaks[i] = 6264 readl(hdspm->iobase + 6265 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6266 levels->output_peaks[i] = 6267 readl(hdspm->iobase + 6268 HDSPM_MADI_OUTPUT_PEAK + i*4); 6269 6270 levels->input_rms[i] = 6271 ((uint64_t) readl(hdspm->iobase + 6272 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6273 (uint64_t) readl(hdspm->iobase + 6274 HDSPM_MADI_INPUT_RMS_L + i*4); 6275 levels->playback_rms[i] = 6276 ((uint64_t)readl(hdspm->iobase + 6277 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6278 (uint64_t)readl(hdspm->iobase + 6279 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6280 levels->output_rms[i] = 6281 ((uint64_t)readl(hdspm->iobase + 6282 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6283 (uint64_t)readl(hdspm->iobase + 6284 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6285 } 6286 6287 if (hdspm->system_sample_rate > 96000) { 6288 levels->speed = qs; 6289 } else if (hdspm->system_sample_rate > 48000) { 6290 levels->speed = ds; 6291 } else { 6292 levels->speed = ss; 6293 } 6294 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6295 6296 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 6297 if (0 != s) { 6298 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu 6299 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6300 */ 6301 return -EFAULT; 6302 } 6303 break; 6304 6305 case SNDRV_HDSPM_IOCTL_GET_LTC: 6306 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6307 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6308 if (i & HDSPM_TCO1_LTC_Input_valid) { 6309 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6310 HDSPM_TCO1_LTC_Format_MSB)) { 6311 case 0: 6312 ltc.format = fps_24; 6313 break; 6314 case HDSPM_TCO1_LTC_Format_LSB: 6315 ltc.format = fps_25; 6316 break; 6317 case HDSPM_TCO1_LTC_Format_MSB: 6318 ltc.format = fps_2997; 6319 break; 6320 default: 6321 ltc.format = fps_30; 6322 break; 6323 } 6324 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6325 ltc.frame = drop_frame; 6326 } else { 6327 ltc.frame = full_frame; 6328 } 6329 } else { 6330 ltc.format = format_invalid; 6331 ltc.frame = frame_invalid; 6332 } 6333 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6334 ltc.input_format = ntsc; 6335 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6336 ltc.input_format = pal; 6337 } else { 6338 ltc.input_format = no_video; 6339 } 6340 6341 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 6342 if (0 != s) { 6343 /* 6344 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6345 return -EFAULT; 6346 } 6347 6348 break; 6349 6350 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6351 6352 memset(&info, 0, sizeof(info)); 6353 spin_lock_irq(&hdspm->lock); 6354 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6355 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6356 6357 info.system_sample_rate = hdspm->system_sample_rate; 6358 info.autosync_sample_rate = 6359 hdspm_external_sample_rate(hdspm); 6360 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6361 info.clock_source = hdspm_clock_source(hdspm); 6362 info.autosync_ref = hdspm_autosync_ref(hdspm); 6363 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6364 info.passthru = 0; 6365 spin_unlock_irq(&hdspm->lock); 6366 if (copy_to_user(argp, &info, sizeof(info))) 6367 return -EFAULT; 6368 break; 6369 6370 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6371 memset(&status, 0, sizeof(status)); 6372 6373 status.card_type = hdspm->io_type; 6374 6375 status.autosync_source = hdspm_autosync_ref(hdspm); 6376 6377 status.card_clock = 110069313433624ULL; 6378 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6379 6380 switch (hdspm->io_type) { 6381 case MADI: 6382 case MADIface: 6383 status.card_specific.madi.sync_wc = 6384 hdspm_wc_sync_check(hdspm); 6385 status.card_specific.madi.sync_madi = 6386 hdspm_madi_sync_check(hdspm); 6387 status.card_specific.madi.sync_tco = 6388 hdspm_tco_sync_check(hdspm); 6389 status.card_specific.madi.sync_in = 6390 hdspm_sync_in_sync_check(hdspm); 6391 6392 statusregister = 6393 hdspm_read(hdspm, HDSPM_statusRegister); 6394 status.card_specific.madi.madi_input = 6395 (statusregister & HDSPM_AB_int) ? 1 : 0; 6396 status.card_specific.madi.channel_format = 6397 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6398 /* TODO: Mac driver sets it when f_s>48kHz */ 6399 status.card_specific.madi.frame_format = 0; 6400 6401 default: 6402 break; 6403 } 6404 6405 if (copy_to_user(argp, &status, sizeof(status))) 6406 return -EFAULT; 6407 6408 6409 break; 6410 6411 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6412 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6413 6414 hdspm_version.card_type = hdspm->io_type; 6415 strlcpy(hdspm_version.cardname, hdspm->card_name, 6416 sizeof(hdspm_version.cardname)); 6417 hdspm_version.serial = hdspm->serial; 6418 hdspm_version.firmware_rev = hdspm->firmware_rev; 6419 hdspm_version.addons = 0; 6420 if (hdspm->tco) 6421 hdspm_version.addons |= HDSPM_ADDON_TCO; 6422 6423 if (copy_to_user(argp, &hdspm_version, 6424 sizeof(hdspm_version))) 6425 return -EFAULT; 6426 break; 6427 6428 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6429 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6430 return -EFAULT; 6431 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6432 sizeof(struct hdspm_mixer))) 6433 return -EFAULT; 6434 break; 6435 6436 default: 6437 return -EINVAL; 6438 } 6439 return 0; 6440 } 6441 6442 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6443 .open = snd_hdspm_playback_open, 6444 .close = snd_hdspm_playback_release, 6445 .ioctl = snd_hdspm_ioctl, 6446 .hw_params = snd_hdspm_hw_params, 6447 .hw_free = snd_hdspm_hw_free, 6448 .prepare = snd_hdspm_prepare, 6449 .trigger = snd_hdspm_trigger, 6450 .pointer = snd_hdspm_hw_pointer, 6451 .page = snd_pcm_sgbuf_ops_page, 6452 }; 6453 6454 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6455 .open = snd_hdspm_capture_open, 6456 .close = snd_hdspm_capture_release, 6457 .ioctl = snd_hdspm_ioctl, 6458 .hw_params = snd_hdspm_hw_params, 6459 .hw_free = snd_hdspm_hw_free, 6460 .prepare = snd_hdspm_prepare, 6461 .trigger = snd_hdspm_trigger, 6462 .pointer = snd_hdspm_hw_pointer, 6463 .page = snd_pcm_sgbuf_ops_page, 6464 }; 6465 6466 static int snd_hdspm_create_hwdep(struct snd_card *card, 6467 struct hdspm *hdspm) 6468 { 6469 struct snd_hwdep *hw; 6470 int err; 6471 6472 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6473 if (err < 0) 6474 return err; 6475 6476 hdspm->hwdep = hw; 6477 hw->private_data = hdspm; 6478 strcpy(hw->name, "HDSPM hwdep interface"); 6479 6480 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6481 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6482 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6483 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6484 6485 return 0; 6486 } 6487 6488 6489 /*------------------------------------------------------------ 6490 memory interface 6491 ------------------------------------------------------------*/ 6492 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6493 { 6494 int err; 6495 struct snd_pcm *pcm; 6496 size_t wanted; 6497 6498 pcm = hdspm->pcm; 6499 6500 wanted = HDSPM_DMA_AREA_BYTES; 6501 6502 err = 6503 snd_pcm_lib_preallocate_pages_for_all(pcm, 6504 SNDRV_DMA_TYPE_DEV_SG, 6505 snd_dma_pci_data(hdspm->pci), 6506 wanted, 6507 wanted); 6508 if (err < 0) { 6509 dev_dbg(hdspm->card->dev, 6510 "Could not preallocate %zd Bytes\n", wanted); 6511 6512 return err; 6513 } else 6514 dev_dbg(hdspm->card->dev, 6515 " Preallocated %zd Bytes\n", wanted); 6516 6517 return 0; 6518 } 6519 6520 6521 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6522 struct snd_pcm_substream *substream, 6523 unsigned int reg, int channels) 6524 { 6525 int i; 6526 6527 /* continuous memory segment */ 6528 for (i = 0; i < (channels * 16); i++) 6529 hdspm_write(hdspm, reg + 4 * i, 6530 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6531 } 6532 6533 6534 /* ------------- ALSA Devices ---------------------------- */ 6535 static int snd_hdspm_create_pcm(struct snd_card *card, 6536 struct hdspm *hdspm) 6537 { 6538 struct snd_pcm *pcm; 6539 int err; 6540 6541 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6542 if (err < 0) 6543 return err; 6544 6545 hdspm->pcm = pcm; 6546 pcm->private_data = hdspm; 6547 strcpy(pcm->name, hdspm->card_name); 6548 6549 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6550 &snd_hdspm_playback_ops); 6551 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6552 &snd_hdspm_capture_ops); 6553 6554 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6555 6556 err = snd_hdspm_preallocate_memory(hdspm); 6557 if (err < 0) 6558 return err; 6559 6560 return 0; 6561 } 6562 6563 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6564 { 6565 int i; 6566 6567 for (i = 0; i < hdspm->midiPorts; i++) 6568 snd_hdspm_flush_midi_input(hdspm, i); 6569 } 6570 6571 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6572 struct hdspm *hdspm) 6573 { 6574 int err, i; 6575 6576 dev_dbg(card->dev, "Create card...\n"); 6577 err = snd_hdspm_create_pcm(card, hdspm); 6578 if (err < 0) 6579 return err; 6580 6581 i = 0; 6582 while (i < hdspm->midiPorts) { 6583 err = snd_hdspm_create_midi(card, hdspm, i); 6584 if (err < 0) { 6585 return err; 6586 } 6587 i++; 6588 } 6589 6590 err = snd_hdspm_create_controls(card, hdspm); 6591 if (err < 0) 6592 return err; 6593 6594 err = snd_hdspm_create_hwdep(card, hdspm); 6595 if (err < 0) 6596 return err; 6597 6598 dev_dbg(card->dev, "proc init...\n"); 6599 snd_hdspm_proc_init(hdspm); 6600 6601 hdspm->system_sample_rate = -1; 6602 hdspm->last_external_sample_rate = -1; 6603 hdspm->last_internal_sample_rate = -1; 6604 hdspm->playback_pid = -1; 6605 hdspm->capture_pid = -1; 6606 hdspm->capture_substream = NULL; 6607 hdspm->playback_substream = NULL; 6608 6609 dev_dbg(card->dev, "Set defaults...\n"); 6610 err = snd_hdspm_set_defaults(hdspm); 6611 if (err < 0) 6612 return err; 6613 6614 dev_dbg(card->dev, "Update mixer controls...\n"); 6615 hdspm_update_simple_mixer_controls(hdspm); 6616 6617 dev_dbg(card->dev, "Initializeing complete ???\n"); 6618 6619 err = snd_card_register(card); 6620 if (err < 0) { 6621 dev_err(card->dev, "error registering card\n"); 6622 return err; 6623 } 6624 6625 dev_dbg(card->dev, "... yes now\n"); 6626 6627 return 0; 6628 } 6629 6630 static int snd_hdspm_create(struct snd_card *card, 6631 struct hdspm *hdspm) 6632 { 6633 6634 struct pci_dev *pci = hdspm->pci; 6635 int err; 6636 unsigned long io_extent; 6637 6638 hdspm->irq = -1; 6639 hdspm->card = card; 6640 6641 spin_lock_init(&hdspm->lock); 6642 6643 pci_read_config_word(hdspm->pci, 6644 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6645 6646 strcpy(card->mixername, "Xilinx FPGA"); 6647 strcpy(card->driver, "HDSPM"); 6648 6649 switch (hdspm->firmware_rev) { 6650 case HDSPM_RAYDAT_REV: 6651 hdspm->io_type = RayDAT; 6652 hdspm->card_name = "RME RayDAT"; 6653 hdspm->midiPorts = 2; 6654 break; 6655 case HDSPM_AIO_REV: 6656 hdspm->io_type = AIO; 6657 hdspm->card_name = "RME AIO"; 6658 hdspm->midiPorts = 1; 6659 break; 6660 case HDSPM_MADIFACE_REV: 6661 hdspm->io_type = MADIface; 6662 hdspm->card_name = "RME MADIface"; 6663 hdspm->midiPorts = 1; 6664 break; 6665 default: 6666 if ((hdspm->firmware_rev == 0xf0) || 6667 ((hdspm->firmware_rev >= 0xe6) && 6668 (hdspm->firmware_rev <= 0xea))) { 6669 hdspm->io_type = AES32; 6670 hdspm->card_name = "RME AES32"; 6671 hdspm->midiPorts = 2; 6672 } else if ((hdspm->firmware_rev == 0xd2) || 6673 ((hdspm->firmware_rev >= 0xc8) && 6674 (hdspm->firmware_rev <= 0xcf))) { 6675 hdspm->io_type = MADI; 6676 hdspm->card_name = "RME MADI"; 6677 hdspm->midiPorts = 3; 6678 } else { 6679 dev_err(card->dev, 6680 "unknown firmware revision %x\n", 6681 hdspm->firmware_rev); 6682 return -ENODEV; 6683 } 6684 } 6685 6686 err = pci_enable_device(pci); 6687 if (err < 0) 6688 return err; 6689 6690 pci_set_master(hdspm->pci); 6691 6692 err = pci_request_regions(pci, "hdspm"); 6693 if (err < 0) 6694 return err; 6695 6696 hdspm->port = pci_resource_start(pci, 0); 6697 io_extent = pci_resource_len(pci, 0); 6698 6699 dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n", 6700 hdspm->port, hdspm->port + io_extent - 1); 6701 6702 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6703 if (!hdspm->iobase) { 6704 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n", 6705 hdspm->port, hdspm->port + io_extent - 1); 6706 return -EBUSY; 6707 } 6708 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n", 6709 (unsigned long)hdspm->iobase, hdspm->port, 6710 hdspm->port + io_extent - 1); 6711 6712 if (request_irq(pci->irq, snd_hdspm_interrupt, 6713 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6714 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq); 6715 return -EBUSY; 6716 } 6717 6718 dev_dbg(card->dev, "use IRQ %d\n", pci->irq); 6719 6720 hdspm->irq = pci->irq; 6721 6722 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n", 6723 sizeof(struct hdspm_mixer)); 6724 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6725 if (!hdspm->mixer) { 6726 dev_err(card->dev, 6727 "unable to kmalloc Mixer memory of %d Bytes\n", 6728 (int)sizeof(struct hdspm_mixer)); 6729 return -ENOMEM; 6730 } 6731 6732 hdspm->port_names_in = NULL; 6733 hdspm->port_names_out = NULL; 6734 6735 switch (hdspm->io_type) { 6736 case AES32: 6737 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6738 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6739 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6740 6741 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6742 channel_map_aes32; 6743 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6744 channel_map_aes32; 6745 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6746 channel_map_aes32; 6747 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6748 texts_ports_aes32; 6749 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6750 texts_ports_aes32; 6751 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6752 texts_ports_aes32; 6753 6754 hdspm->max_channels_out = hdspm->max_channels_in = 6755 AES32_CHANNELS; 6756 hdspm->port_names_in = hdspm->port_names_out = 6757 texts_ports_aes32; 6758 hdspm->channel_map_in = hdspm->channel_map_out = 6759 channel_map_aes32; 6760 6761 break; 6762 6763 case MADI: 6764 case MADIface: 6765 hdspm->ss_in_channels = hdspm->ss_out_channels = 6766 MADI_SS_CHANNELS; 6767 hdspm->ds_in_channels = hdspm->ds_out_channels = 6768 MADI_DS_CHANNELS; 6769 hdspm->qs_in_channels = hdspm->qs_out_channels = 6770 MADI_QS_CHANNELS; 6771 6772 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6773 channel_map_unity_ss; 6774 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6775 channel_map_unity_ss; 6776 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6777 channel_map_unity_ss; 6778 6779 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6780 texts_ports_madi; 6781 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6782 texts_ports_madi; 6783 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6784 texts_ports_madi; 6785 break; 6786 6787 case AIO: 6788 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6789 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6790 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6791 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6792 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6793 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6794 6795 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6796 dev_info(card->dev, "AEB input board found\n"); 6797 hdspm->ss_in_channels += 4; 6798 hdspm->ds_in_channels += 4; 6799 hdspm->qs_in_channels += 4; 6800 } 6801 6802 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) { 6803 dev_info(card->dev, "AEB output board found\n"); 6804 hdspm->ss_out_channels += 4; 6805 hdspm->ds_out_channels += 4; 6806 hdspm->qs_out_channels += 4; 6807 } 6808 6809 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6810 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6811 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6812 6813 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6814 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6815 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6816 6817 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6818 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6819 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6820 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6821 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6822 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6823 6824 break; 6825 6826 case RayDAT: 6827 hdspm->ss_in_channels = hdspm->ss_out_channels = 6828 RAYDAT_SS_CHANNELS; 6829 hdspm->ds_in_channels = hdspm->ds_out_channels = 6830 RAYDAT_DS_CHANNELS; 6831 hdspm->qs_in_channels = hdspm->qs_out_channels = 6832 RAYDAT_QS_CHANNELS; 6833 6834 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6835 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6836 6837 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6838 channel_map_raydat_ss; 6839 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6840 channel_map_raydat_ds; 6841 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6842 channel_map_raydat_qs; 6843 hdspm->channel_map_in = hdspm->channel_map_out = 6844 channel_map_raydat_ss; 6845 6846 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6847 texts_ports_raydat_ss; 6848 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6849 texts_ports_raydat_ds; 6850 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6851 texts_ports_raydat_qs; 6852 6853 6854 break; 6855 6856 } 6857 6858 /* TCO detection */ 6859 switch (hdspm->io_type) { 6860 case AIO: 6861 case RayDAT: 6862 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6863 HDSPM_s2_tco_detect) { 6864 hdspm->midiPorts++; 6865 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6866 GFP_KERNEL); 6867 if (NULL != hdspm->tco) { 6868 hdspm_tco_write(hdspm); 6869 } 6870 dev_info(card->dev, "AIO/RayDAT TCO module found\n"); 6871 } else { 6872 hdspm->tco = NULL; 6873 } 6874 break; 6875 6876 case MADI: 6877 case AES32: 6878 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6879 hdspm->midiPorts++; 6880 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6881 GFP_KERNEL); 6882 if (NULL != hdspm->tco) { 6883 hdspm_tco_write(hdspm); 6884 } 6885 dev_info(card->dev, "MADI/AES TCO module found\n"); 6886 } else { 6887 hdspm->tco = NULL; 6888 } 6889 break; 6890 6891 default: 6892 hdspm->tco = NULL; 6893 } 6894 6895 /* texts */ 6896 switch (hdspm->io_type) { 6897 case AES32: 6898 if (hdspm->tco) { 6899 hdspm->texts_autosync = texts_autosync_aes_tco; 6900 hdspm->texts_autosync_items = 6901 ARRAY_SIZE(texts_autosync_aes_tco); 6902 } else { 6903 hdspm->texts_autosync = texts_autosync_aes; 6904 hdspm->texts_autosync_items = 6905 ARRAY_SIZE(texts_autosync_aes); 6906 } 6907 break; 6908 6909 case MADI: 6910 if (hdspm->tco) { 6911 hdspm->texts_autosync = texts_autosync_madi_tco; 6912 hdspm->texts_autosync_items = 4; 6913 } else { 6914 hdspm->texts_autosync = texts_autosync_madi; 6915 hdspm->texts_autosync_items = 3; 6916 } 6917 break; 6918 6919 case MADIface: 6920 6921 break; 6922 6923 case RayDAT: 6924 if (hdspm->tco) { 6925 hdspm->texts_autosync = texts_autosync_raydat_tco; 6926 hdspm->texts_autosync_items = 9; 6927 } else { 6928 hdspm->texts_autosync = texts_autosync_raydat; 6929 hdspm->texts_autosync_items = 8; 6930 } 6931 break; 6932 6933 case AIO: 6934 if (hdspm->tco) { 6935 hdspm->texts_autosync = texts_autosync_aio_tco; 6936 hdspm->texts_autosync_items = 6; 6937 } else { 6938 hdspm->texts_autosync = texts_autosync_aio; 6939 hdspm->texts_autosync_items = 5; 6940 } 6941 break; 6942 6943 } 6944 6945 tasklet_init(&hdspm->midi_tasklet, 6946 hdspm_midi_tasklet, (unsigned long) hdspm); 6947 6948 6949 if (hdspm->io_type != MADIface) { 6950 hdspm->serial = (hdspm_read(hdspm, 6951 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6952 /* id contains either a user-provided value or the default 6953 * NULL. If it's the default, we're safe to 6954 * fill card->id with the serial number. 6955 * 6956 * If the serial number is 0xFFFFFF, then we're dealing with 6957 * an old PCI revision that comes without a sane number. In 6958 * this case, we don't set card->id to avoid collisions 6959 * when running with multiple cards. 6960 */ 6961 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6962 sprintf(card->id, "HDSPMx%06x", hdspm->serial); 6963 snd_card_set_id(card, card->id); 6964 } 6965 } 6966 6967 dev_dbg(card->dev, "create alsa devices.\n"); 6968 err = snd_hdspm_create_alsa_devices(card, hdspm); 6969 if (err < 0) 6970 return err; 6971 6972 snd_hdspm_initialize_midi_flush(hdspm); 6973 6974 return 0; 6975 } 6976 6977 6978 static int snd_hdspm_free(struct hdspm * hdspm) 6979 { 6980 6981 if (hdspm->port) { 6982 6983 /* stop th audio, and cancel all interrupts */ 6984 hdspm->control_register &= 6985 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6986 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6987 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6988 hdspm_write(hdspm, HDSPM_controlRegister, 6989 hdspm->control_register); 6990 } 6991 6992 if (hdspm->irq >= 0) 6993 free_irq(hdspm->irq, (void *) hdspm); 6994 6995 kfree(hdspm->mixer); 6996 6997 if (hdspm->iobase) 6998 iounmap(hdspm->iobase); 6999 7000 if (hdspm->port) 7001 pci_release_regions(hdspm->pci); 7002 7003 pci_disable_device(hdspm->pci); 7004 return 0; 7005 } 7006 7007 7008 static void snd_hdspm_card_free(struct snd_card *card) 7009 { 7010 struct hdspm *hdspm = card->private_data; 7011 7012 if (hdspm) 7013 snd_hdspm_free(hdspm); 7014 } 7015 7016 7017 static int snd_hdspm_probe(struct pci_dev *pci, 7018 const struct pci_device_id *pci_id) 7019 { 7020 static int dev; 7021 struct hdspm *hdspm; 7022 struct snd_card *card; 7023 int err; 7024 7025 if (dev >= SNDRV_CARDS) 7026 return -ENODEV; 7027 if (!enable[dev]) { 7028 dev++; 7029 return -ENOENT; 7030 } 7031 7032 err = snd_card_new(&pci->dev, index[dev], id[dev], 7033 THIS_MODULE, sizeof(struct hdspm), &card); 7034 if (err < 0) 7035 return err; 7036 7037 hdspm = card->private_data; 7038 card->private_free = snd_hdspm_card_free; 7039 hdspm->dev = dev; 7040 hdspm->pci = pci; 7041 7042 err = snd_hdspm_create(card, hdspm); 7043 if (err < 0) { 7044 snd_card_free(card); 7045 return err; 7046 } 7047 7048 if (hdspm->io_type != MADIface) { 7049 sprintf(card->shortname, "%s_%x", 7050 hdspm->card_name, 7051 hdspm->serial); 7052 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 7053 hdspm->card_name, 7054 hdspm->serial, 7055 hdspm->port, hdspm->irq); 7056 } else { 7057 sprintf(card->shortname, "%s", hdspm->card_name); 7058 sprintf(card->longname, "%s at 0x%lx, irq %d", 7059 hdspm->card_name, hdspm->port, hdspm->irq); 7060 } 7061 7062 err = snd_card_register(card); 7063 if (err < 0) { 7064 snd_card_free(card); 7065 return err; 7066 } 7067 7068 pci_set_drvdata(pci, card); 7069 7070 dev++; 7071 return 0; 7072 } 7073 7074 static void snd_hdspm_remove(struct pci_dev *pci) 7075 { 7076 snd_card_free(pci_get_drvdata(pci)); 7077 } 7078 7079 static struct pci_driver hdspm_driver = { 7080 .name = KBUILD_MODNAME, 7081 .id_table = snd_hdspm_ids, 7082 .probe = snd_hdspm_probe, 7083 .remove = snd_hdspm_remove, 7084 }; 7085 7086 module_pci_driver(hdspm_driver); 7087