1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 #include <linux/init.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/moduleparam.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/math64.h> 48 #include <asm/io.h> 49 50 #include <sound/core.h> 51 #include <sound/control.h> 52 #include <sound/pcm.h> 53 #include <sound/pcm_params.h> 54 #include <sound/info.h> 55 #include <sound/asoundef.h> 56 #include <sound/rawmidi.h> 57 #include <sound/hwdep.h> 58 #include <sound/initval.h> 59 60 #include <sound/hdspm.h> 61 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 64 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 68 69 module_param_array(id, charp, NULL, 0444); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 71 72 module_param_array(enable, bool, NULL, 0444); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 74 75 76 MODULE_AUTHOR 77 ( 78 "Winfried Ritsch <ritsch_AT_iem.at>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, " 82 "Florian Faber <faberman@linuxproaudio.org>, " 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 84 ); 85 MODULE_DESCRIPTION("RME HDSPM"); 86 MODULE_LICENSE("GPL"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 88 89 /* --- Write registers. --- 90 These are defined as byte-offsets from the iobase value. */ 91 92 #define HDSPM_WR_SETTINGS 0 93 #define HDSPM_outputBufferAddress 32 94 #define HDSPM_inputBufferAddress 36 95 #define HDSPM_controlRegister 64 96 #define HDSPM_interruptConfirmation 96 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 98 #define HDSPM_freqReg 256 /* for AES32 */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 100 #define HDSPM_midiDataOut1 356 101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 102 103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 106 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 109 #define HDSPM_pageAddressBufferOut 8192 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 111 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 113 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 115 116 /* --- Read registers. --- 117 These are defined as byte-offsets from the iobase value */ 118 #define HDSPM_statusRegister 0 119 /*#define HDSPM_statusRegister2 96 */ 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 121 * offset 192, for AES32 *and* MADI 122 * => need to check that offset 192 is working on MADI */ 123 #define HDSPM_statusRegister2 192 124 #define HDSPM_timecodeRegister 128 125 126 /* AIO, RayDAT */ 127 #define HDSPM_RD_STATUS_0 0 128 #define HDSPM_RD_STATUS_1 64 129 #define HDSPM_RD_STATUS_2 128 130 #define HDSPM_RD_STATUS_3 192 131 132 #define HDSPM_RD_TCO 256 133 #define HDSPM_RD_PLL_FREQ 512 134 #define HDSPM_WR_TCO 128 135 136 #define HDSPM_TCO1_TCO_lock 0x00000001 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 143 144 #define HDSPM_TCO1_set_TC 0x00000100 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 148 149 #define HDSPM_TCO2_TC_run 0x00010000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000 155 #define HDSPM_TCO2_set_flywheel 0x00400000 156 157 #define HDSPM_TCO2_set_01_4 0x01000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000 160 #define HDSPM_TCO2_set_freq 0x08000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 165 166 167 #define HDSPM_midiDataOut0 352 168 #define HDSPM_midiDataOut1 356 169 #define HDSPM_midiDataOut2 368 170 171 #define HDSPM_midiDataIn0 360 172 #define HDSPM_midiDataIn1 364 173 #define HDSPM_midiDataIn2 372 174 #define HDSPM_midiDataIn3 376 175 176 /* status is data bytes in MIDI-FIFO (0-128) */ 177 #define HDSPM_midiStatusOut0 384 178 #define HDSPM_midiStatusOut1 388 179 #define HDSPM_midiStatusOut2 400 180 181 #define HDSPM_midiStatusIn0 392 182 #define HDSPM_midiStatusIn1 396 183 #define HDSPM_midiStatusIn2 404 184 #define HDSPM_midiStatusIn3 408 185 186 187 /* the meters are regular i/o-mapped registers, but offset 188 considerably from the rest. the peak registers are reset 189 when read; the least-significant 4 bits are full-scale counters; 190 the actual peak value is in the most-significant 24 bits. 191 */ 192 193 #define HDSPM_MADI_INPUT_PEAK 4096 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 195 #define HDSPM_MADI_OUTPUT_PEAK 4608 196 197 #define HDSPM_MADI_INPUT_RMS_L 6144 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 200 201 #define HDSPM_MADI_INPUT_RMS_H 7168 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 204 205 /* --- Control Register bits --------- */ 206 #define HDSPM_Start (1<<0) /* start engine */ 207 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 211 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 214 register [RayDAT, AIO] */ 215 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 217 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 222 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 225 56channelMODE=0 */ /* MADI ONLY*/ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 227 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 229 0=off, 1=on */ /* MADI ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 231 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 233 * -- MADI ONLY 234 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 236 237 #define HDSPM_SyncRef2 (1<<13) 238 #define HDSPM_SyncRef3 (1<<25) 239 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 242 AES additional bits in 243 lower 5 Audiodatabits ??? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 246 247 #define HDSPM_Midi0InterruptEnable 0x0400000 248 #define HDSPM_Midi1InterruptEnable 0x0800000 249 #define HDSPM_Midi2InterruptEnable 0x0200000 250 #define HDSPM_Midi3InterruptEnable 0x4000000 251 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 253 #define HDSPe_FLOAT_FORMAT 0x2000000 254 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 258 259 #define HDSPM_wclk_sel (1<<30) 260 261 /* --- bit helper defines */ 262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 266 #define HDSPM_InputOptical 0 267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 269 HDSPM_SyncRef2|HDSPM_SyncRef3) 270 271 #define HDSPM_c0_SyncRef0 0x2 272 #define HDSPM_c0_SyncRef1 0x4 273 #define HDSPM_c0_SyncRef2 0x8 274 #define HDSPM_c0_SyncRef3 0x10 275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 277 278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 280 #define HDSPM_SYNC_FROM_TCO 2 281 #define HDSPM_SYNC_FROM_SYNC_IN 3 282 283 #define HDSPM_Frequency32KHz HDSPM_Frequency0 284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 289 HDSPM_Frequency0) 290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 293 HDSPM_Frequency0) 294 295 296 /* Synccheck Status */ 297 #define HDSPM_SYNC_CHECK_NO_LOCK 0 298 #define HDSPM_SYNC_CHECK_LOCK 1 299 #define HDSPM_SYNC_CHECK_SYNC 2 300 301 /* AutoSync References - used by "autosync_ref" control switch */ 302 #define HDSPM_AUTOSYNC_FROM_WORD 0 303 #define HDSPM_AUTOSYNC_FROM_MADI 1 304 #define HDSPM_AUTOSYNC_FROM_TCO 2 305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 306 #define HDSPM_AUTOSYNC_FROM_NONE 4 307 308 /* Possible sources of MADI input */ 309 #define HDSPM_OPTICAL 0 /* optical */ 310 #define HDSPM_COAXIAL 1 /* BNC */ 311 312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 314 315 #define hdspm_encode_in(x) (((x)&0x3)<<14) 316 #define hdspm_decode_in(x) (((x)>>14)&0x3) 317 318 /* --- control2 register bits --- */ 319 #define HDSPM_TMS (1<<0) 320 #define HDSPM_TCK (1<<1) 321 #define HDSPM_TDI (1<<2) 322 #define HDSPM_JTAG (1<<3) 323 #define HDSPM_PWDN (1<<4) 324 #define HDSPM_PROGRAM (1<<5) 325 #define HDSPM_CONFIG_MODE_0 (1<<6) 326 #define HDSPM_CONFIG_MODE_1 (1<<7) 327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 328 #define HDSPM_BIGENDIAN_MODE (1<<9) 329 #define HDSPM_RD_MULTIPLE (1<<10) 330 331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 332 that do not conflict with specific bits for AES32 seem to be valid also 333 for the AES32 334 */ 335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 338 * (like inp0) 339 */ 340 341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 343 344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 346 347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 349 350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 351 /* since 64byte accurate, last 6 bits are not used */ 352 353 354 355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 356 357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 361 362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 363 * Interrupt 364 */ 365 #define HDSPM_tco_detect 0x08000000 366 #define HDSPM_tco_lock 0x20000000 367 368 #define HDSPM_s2_tco_detect 0x00000040 369 #define HDSPM_s2_AEBO_D 0x00000080 370 #define HDSPM_s2_AEBI_D 0x00000100 371 372 373 #define HDSPM_midi0IRQPending 0x40000000 374 #define HDSPM_midi1IRQPending 0x80000000 375 #define HDSPM_midi2IRQPending 0x20000000 376 #define HDSPM_midi2IRQPendingAES 0x00000020 377 #define HDSPM_midi3IRQPending 0x00200000 378 379 /* --- status bit helpers */ 380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 381 HDSPM_madiFreq2|HDSPM_madiFreq3) 382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 391 392 /* Status2 Register bits */ /* MADI ONLY */ 393 394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 396 #define HDSPM_version2 (1<<2) 397 398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 400 401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ 404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */ 405 406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 407 #define HDSPM_SyncRef1 0x20000 408 409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 412 413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 414 415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 422 423 #define HDSPM_status1_F_0 0x0400000 424 #define HDSPM_status1_F_1 0x0800000 425 #define HDSPM_status1_F_2 0x1000000 426 #define HDSPM_status1_F_3 0x2000000 427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 428 429 430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 431 HDSPM_SelSyncRef2) 432 #define HDSPM_SelSyncRef_WORD 0 433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 437 HDSPM_SelSyncRef2) 438 439 /* 440 For AES32, bits for status, status2 and timecode are different 441 */ 442 /* status */ 443 #define HDSPM_AES32_wcLock 0x0200000 444 #define HDSPM_AES32_wcFreq_bit 22 445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 446 HDSPM_bit2freq */ 447 #define HDSPM_AES32_syncref_bit 16 448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 449 450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 460 461 /* status2 */ 462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 463 #define HDSPM_LockAES 0x80 464 #define HDSPM_LockAES1 0x80 465 #define HDSPM_LockAES2 0x40 466 #define HDSPM_LockAES3 0x20 467 #define HDSPM_LockAES4 0x10 468 #define HDSPM_LockAES5 0x8 469 #define HDSPM_LockAES6 0x4 470 #define HDSPM_LockAES7 0x2 471 #define HDSPM_LockAES8 0x1 472 /* 473 Timecode 474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 475 AES i+1 476 bits 3210 477 0001 32kHz 478 0010 44.1kHz 479 0011 48kHz 480 0100 64kHz 481 0101 88.2kHz 482 0110 96kHz 483 0111 128kHz 484 1000 176.4kHz 485 1001 192kHz 486 NB: Timecode register doesn't seem to work on AES32 card revision 230 487 */ 488 489 /* Mixer Values */ 490 #define UNITY_GAIN 32768 /* = 65536/2 */ 491 #define MINUS_INFINITY_GAIN 0 492 493 /* Number of channels for different Speed Modes */ 494 #define MADI_SS_CHANNELS 64 495 #define MADI_DS_CHANNELS 32 496 #define MADI_QS_CHANNELS 16 497 498 #define RAYDAT_SS_CHANNELS 36 499 #define RAYDAT_DS_CHANNELS 20 500 #define RAYDAT_QS_CHANNELS 12 501 502 #define AIO_IN_SS_CHANNELS 14 503 #define AIO_IN_DS_CHANNELS 10 504 #define AIO_IN_QS_CHANNELS 8 505 #define AIO_OUT_SS_CHANNELS 16 506 #define AIO_OUT_DS_CHANNELS 12 507 #define AIO_OUT_QS_CHANNELS 10 508 509 #define AES32_CHANNELS 16 510 511 /* the size of a substream (1 mono data stream) */ 512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 514 515 /* the size of the area we need to allocate for DMA transfers. the 516 size is the same regardless of the number of channels, and 517 also the latency to use. 518 for one direction !!! 519 */ 520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 522 523 /* revisions >= 230 indicate AES32 card */ 524 #define HDSPM_MADI_OLD_REV 207 525 #define HDSPM_MADI_REV 210 526 #define HDSPM_RAYDAT_REV 211 527 #define HDSPM_AIO_REV 212 528 #define HDSPM_MADIFACE_REV 213 529 #define HDSPM_AES_REV 240 530 #define HDSPM_AES32_REV 234 531 #define HDSPM_AES32_OLD_REV 233 532 533 /* speed factor modes */ 534 #define HDSPM_SPEED_SINGLE 0 535 #define HDSPM_SPEED_DOUBLE 1 536 #define HDSPM_SPEED_QUAD 2 537 538 /* names for speed modes */ 539 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 540 541 static char *texts_autosync_aes_tco[] = { "Word Clock", 542 "AES1", "AES2", "AES3", "AES4", 543 "AES5", "AES6", "AES7", "AES8", 544 "TCO" }; 545 static char *texts_autosync_aes[] = { "Word Clock", 546 "AES1", "AES2", "AES3", "AES4", 547 "AES5", "AES6", "AES7", "AES8" }; 548 static char *texts_autosync_madi_tco[] = { "Word Clock", 549 "MADI", "TCO", "Sync In" }; 550 static char *texts_autosync_madi[] = { "Word Clock", 551 "MADI", "Sync In" }; 552 553 static char *texts_autosync_raydat_tco[] = { 554 "Word Clock", 555 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 556 "AES", "SPDIF", "TCO", "Sync In" 557 }; 558 static char *texts_autosync_raydat[] = { 559 "Word Clock", 560 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 561 "AES", "SPDIF", "Sync In" 562 }; 563 static char *texts_autosync_aio_tco[] = { 564 "Word Clock", 565 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 566 }; 567 static char *texts_autosync_aio[] = { "Word Clock", 568 "ADAT", "AES", "SPDIF", "Sync In" }; 569 570 static char *texts_freq[] = { 571 "No Lock", 572 "32 kHz", 573 "44.1 kHz", 574 "48 kHz", 575 "64 kHz", 576 "88.2 kHz", 577 "96 kHz", 578 "128 kHz", 579 "176.4 kHz", 580 "192 kHz" 581 }; 582 583 static char *texts_ports_madi[] = { 584 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 585 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 586 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 587 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 588 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 589 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 590 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 591 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 592 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 593 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 594 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 595 }; 596 597 598 static char *texts_ports_raydat_ss[] = { 599 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 600 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 601 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 602 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 603 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 604 "ADAT4.7", "ADAT4.8", 605 "AES.L", "AES.R", 606 "SPDIF.L", "SPDIF.R" 607 }; 608 609 static char *texts_ports_raydat_ds[] = { 610 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 611 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 612 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 613 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 614 "AES.L", "AES.R", 615 "SPDIF.L", "SPDIF.R" 616 }; 617 618 static char *texts_ports_raydat_qs[] = { 619 "ADAT1.1", "ADAT1.2", 620 "ADAT2.1", "ADAT2.2", 621 "ADAT3.1", "ADAT3.2", 622 "ADAT4.1", "ADAT4.2", 623 "AES.L", "AES.R", 624 "SPDIF.L", "SPDIF.R" 625 }; 626 627 628 static char *texts_ports_aio_in_ss[] = { 629 "Analogue.L", "Analogue.R", 630 "AES.L", "AES.R", 631 "SPDIF.L", "SPDIF.R", 632 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 633 "ADAT.7", "ADAT.8" 634 }; 635 636 static char *texts_ports_aio_out_ss[] = { 637 "Analogue.L", "Analogue.R", 638 "AES.L", "AES.R", 639 "SPDIF.L", "SPDIF.R", 640 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 641 "ADAT.7", "ADAT.8", 642 "Phone.L", "Phone.R" 643 }; 644 645 static char *texts_ports_aio_in_ds[] = { 646 "Analogue.L", "Analogue.R", 647 "AES.L", "AES.R", 648 "SPDIF.L", "SPDIF.R", 649 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 650 }; 651 652 static char *texts_ports_aio_out_ds[] = { 653 "Analogue.L", "Analogue.R", 654 "AES.L", "AES.R", 655 "SPDIF.L", "SPDIF.R", 656 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 657 "Phone.L", "Phone.R" 658 }; 659 660 static char *texts_ports_aio_in_qs[] = { 661 "Analogue.L", "Analogue.R", 662 "AES.L", "AES.R", 663 "SPDIF.L", "SPDIF.R", 664 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 665 }; 666 667 static char *texts_ports_aio_out_qs[] = { 668 "Analogue.L", "Analogue.R", 669 "AES.L", "AES.R", 670 "SPDIF.L", "SPDIF.R", 671 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 672 "Phone.L", "Phone.R" 673 }; 674 675 static char *texts_ports_aes32[] = { 676 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 677 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 678 "AES.15", "AES.16" 679 }; 680 681 /* These tables map the ALSA channels 1..N to the channels that we 682 need to use in order to find the relevant channel buffer. RME 683 refers to this kind of mapping as between "the ADAT channel and 684 the DMA channel." We index it using the logical audio channel, 685 and the value is the DMA channel (i.e. channel buffer number) 686 where the data for that channel can be read/written from/to. 687 */ 688 689 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 690 0, 1, 2, 3, 4, 5, 6, 7, 691 8, 9, 10, 11, 12, 13, 14, 15, 692 16, 17, 18, 19, 20, 21, 22, 23, 693 24, 25, 26, 27, 28, 29, 30, 31, 694 32, 33, 34, 35, 36, 37, 38, 39, 695 40, 41, 42, 43, 44, 45, 46, 47, 696 48, 49, 50, 51, 52, 53, 54, 55, 697 56, 57, 58, 59, 60, 61, 62, 63 698 }; 699 700 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 701 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 702 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 703 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 704 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 705 0, 1, /* AES */ 706 2, 3, /* SPDIF */ 707 -1, -1, -1, -1, 708 -1, -1, -1, -1, -1, -1, -1, -1, 709 -1, -1, -1, -1, -1, -1, -1, -1, 710 -1, -1, -1, -1, -1, -1, -1, -1, 711 }; 712 713 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 714 4, 5, 6, 7, /* ADAT 1 */ 715 8, 9, 10, 11, /* ADAT 2 */ 716 12, 13, 14, 15, /* ADAT 3 */ 717 16, 17, 18, 19, /* ADAT 4 */ 718 0, 1, /* AES */ 719 2, 3, /* SPDIF */ 720 -1, -1, -1, -1, 721 -1, -1, -1, -1, -1, -1, -1, -1, 722 -1, -1, -1, -1, -1, -1, -1, -1, 723 -1, -1, -1, -1, -1, -1, -1, -1, 724 -1, -1, -1, -1, -1, -1, -1, -1, 725 -1, -1, -1, -1, -1, -1, -1, -1, 726 }; 727 728 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 729 4, 5, /* ADAT 1 */ 730 6, 7, /* ADAT 2 */ 731 8, 9, /* ADAT 3 */ 732 10, 11, /* ADAT 4 */ 733 0, 1, /* AES */ 734 2, 3, /* SPDIF */ 735 -1, -1, -1, -1, 736 -1, -1, -1, -1, -1, -1, -1, -1, 737 -1, -1, -1, -1, -1, -1, -1, -1, 738 -1, -1, -1, -1, -1, -1, -1, -1, 739 -1, -1, -1, -1, -1, -1, -1, -1, 740 -1, -1, -1, -1, -1, -1, -1, -1, 741 -1, -1, -1, -1, -1, -1, -1, -1, 742 }; 743 744 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 745 0, 1, /* line in */ 746 8, 9, /* aes in, */ 747 10, 11, /* spdif in */ 748 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 749 -1, -1, 750 -1, -1, -1, -1, -1, -1, -1, -1, 751 -1, -1, -1, -1, -1, -1, -1, -1, 752 -1, -1, -1, -1, -1, -1, -1, -1, 753 -1, -1, -1, -1, -1, -1, -1, -1, 754 -1, -1, -1, -1, -1, -1, -1, -1, 755 -1, -1, -1, -1, -1, -1, -1, -1, 756 }; 757 758 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 759 0, 1, /* line out */ 760 8, 9, /* aes out */ 761 10, 11, /* spdif out */ 762 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 763 6, 7, /* phone out */ 764 -1, -1, -1, -1, -1, -1, -1, -1, 765 -1, -1, -1, -1, -1, -1, -1, -1, 766 -1, -1, -1, -1, -1, -1, -1, -1, 767 -1, -1, -1, -1, -1, -1, -1, -1, 768 -1, -1, -1, -1, -1, -1, -1, -1, 769 -1, -1, -1, -1, -1, -1, -1, -1, 770 }; 771 772 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 773 0, 1, /* line in */ 774 8, 9, /* aes in */ 775 10, 11, /* spdif in */ 776 12, 14, 16, 18, /* adat in */ 777 -1, -1, -1, -1, -1, -1, 778 -1, -1, -1, -1, -1, -1, -1, -1, 779 -1, -1, -1, -1, -1, -1, -1, -1, 780 -1, -1, -1, -1, -1, -1, -1, -1, 781 -1, -1, -1, -1, -1, -1, -1, -1, 782 -1, -1, -1, -1, -1, -1, -1, -1, 783 -1, -1, -1, -1, -1, -1, -1, -1 784 }; 785 786 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 787 0, 1, /* line out */ 788 8, 9, /* aes out */ 789 10, 11, /* spdif out */ 790 12, 14, 16, 18, /* adat out */ 791 6, 7, /* phone out */ 792 -1, -1, -1, -1, 793 -1, -1, -1, -1, -1, -1, -1, -1, 794 -1, -1, -1, -1, -1, -1, -1, -1, 795 -1, -1, -1, -1, -1, -1, -1, -1, 796 -1, -1, -1, -1, -1, -1, -1, -1, 797 -1, -1, -1, -1, -1, -1, -1, -1, 798 -1, -1, -1, -1, -1, -1, -1, -1 799 }; 800 801 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 802 0, 1, /* line in */ 803 8, 9, /* aes in */ 804 10, 11, /* spdif in */ 805 12, 16, /* adat in */ 806 -1, -1, -1, -1, -1, -1, -1, -1, 807 -1, -1, -1, -1, -1, -1, -1, -1, 808 -1, -1, -1, -1, -1, -1, -1, -1, 809 -1, -1, -1, -1, -1, -1, -1, -1, 810 -1, -1, -1, -1, -1, -1, -1, -1, 811 -1, -1, -1, -1, -1, -1, -1, -1, 812 -1, -1, -1, -1, -1, -1, -1, -1 813 }; 814 815 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 816 0, 1, /* line out */ 817 8, 9, /* aes out */ 818 10, 11, /* spdif out */ 819 12, 16, /* adat out */ 820 6, 7, /* phone out */ 821 -1, -1, -1, -1, -1, -1, 822 -1, -1, -1, -1, -1, -1, -1, -1, 823 -1, -1, -1, -1, -1, -1, -1, -1, 824 -1, -1, -1, -1, -1, -1, -1, -1, 825 -1, -1, -1, -1, -1, -1, -1, -1, 826 -1, -1, -1, -1, -1, -1, -1, -1, 827 -1, -1, -1, -1, -1, -1, -1, -1 828 }; 829 830 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 831 0, 1, 2, 3, 4, 5, 6, 7, 832 8, 9, 10, 11, 12, 13, 14, 15, 833 -1, -1, -1, -1, -1, -1, -1, -1, 834 -1, -1, -1, -1, -1, -1, -1, -1, 835 -1, -1, -1, -1, -1, -1, -1, -1, 836 -1, -1, -1, -1, -1, -1, -1, -1, 837 -1, -1, -1, -1, -1, -1, -1, -1, 838 -1, -1, -1, -1, -1, -1, -1, -1 839 }; 840 841 struct hdspm_midi { 842 struct hdspm *hdspm; 843 int id; 844 struct snd_rawmidi *rmidi; 845 struct snd_rawmidi_substream *input; 846 struct snd_rawmidi_substream *output; 847 char istimer; /* timer in use */ 848 struct timer_list timer; 849 spinlock_t lock; 850 int pending; 851 int dataIn; 852 int statusIn; 853 int dataOut; 854 int statusOut; 855 int ie; 856 int irq; 857 }; 858 859 struct hdspm_tco { 860 int input; 861 int framerate; 862 int wordclock; 863 int samplerate; 864 int pull; 865 int term; /* 0 = off, 1 = on */ 866 }; 867 868 struct hdspm { 869 spinlock_t lock; 870 /* only one playback and/or capture stream */ 871 struct snd_pcm_substream *capture_substream; 872 struct snd_pcm_substream *playback_substream; 873 874 char *card_name; /* for procinfo */ 875 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 876 877 uint8_t io_type; 878 879 int monitor_outs; /* set up monitoring outs init flag */ 880 881 u32 control_register; /* cached value */ 882 u32 control2_register; /* cached value */ 883 u32 settings_register; 884 885 struct hdspm_midi midi[4]; 886 struct tasklet_struct midi_tasklet; 887 888 size_t period_bytes; 889 unsigned char ss_in_channels; 890 unsigned char ds_in_channels; 891 unsigned char qs_in_channels; 892 unsigned char ss_out_channels; 893 unsigned char ds_out_channels; 894 unsigned char qs_out_channels; 895 896 unsigned char max_channels_in; 897 unsigned char max_channels_out; 898 899 signed char *channel_map_in; 900 signed char *channel_map_out; 901 902 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 903 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 904 905 char **port_names_in; 906 char **port_names_out; 907 908 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 909 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 910 911 unsigned char *playback_buffer; /* suitably aligned address */ 912 unsigned char *capture_buffer; /* suitably aligned address */ 913 914 pid_t capture_pid; /* process id which uses capture */ 915 pid_t playback_pid; /* process id which uses capture */ 916 int running; /* running status */ 917 918 int last_external_sample_rate; /* samplerate mystic ... */ 919 int last_internal_sample_rate; 920 int system_sample_rate; 921 922 int dev; /* Hardware vars... */ 923 int irq; 924 unsigned long port; 925 void __iomem *iobase; 926 927 int irq_count; /* for debug */ 928 int midiPorts; 929 930 struct snd_card *card; /* one card */ 931 struct snd_pcm *pcm; /* has one pcm */ 932 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 933 struct pci_dev *pci; /* and an pci info */ 934 935 /* Mixer vars */ 936 /* fast alsa mixer */ 937 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 938 /* but input to much, so not used */ 939 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 940 /* full mixer accessible over mixer ioctl or hwdep-device */ 941 struct hdspm_mixer *mixer; 942 943 struct hdspm_tco *tco; /* NULL if no TCO detected */ 944 945 char **texts_autosync; 946 int texts_autosync_items; 947 948 cycles_t last_interrupt; 949 950 struct hdspm_peak_rms peak_rms; 951 }; 952 953 954 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 955 { 956 .vendor = PCI_VENDOR_ID_XILINX, 957 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 958 .subvendor = PCI_ANY_ID, 959 .subdevice = PCI_ANY_ID, 960 .class = 0, 961 .class_mask = 0, 962 .driver_data = 0}, 963 {0,} 964 }; 965 966 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 967 968 /* prototypes */ 969 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 970 struct hdspm * hdspm); 971 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 972 struct hdspm * hdspm); 973 974 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 975 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 976 static int hdspm_autosync_ref(struct hdspm *hdspm); 977 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 978 static void hdspm_set_sgbuf(struct hdspm *hdspm, 979 struct snd_pcm_substream *substream, 980 unsigned int reg, int channels); 981 982 static inline int HDSPM_bit2freq(int n) 983 { 984 static const int bit2freq_tab[] = { 985 0, 32000, 44100, 48000, 64000, 88200, 986 96000, 128000, 176400, 192000 }; 987 if (n < 1 || n > 9) 988 return 0; 989 return bit2freq_tab[n]; 990 } 991 992 /* Write/read to/from HDSPM with Adresses in Bytes 993 not words but only 32Bit writes are allowed */ 994 995 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 996 unsigned int val) 997 { 998 writel(val, hdspm->iobase + reg); 999 } 1000 1001 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1002 { 1003 return readl(hdspm->iobase + reg); 1004 } 1005 1006 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1007 mixer is write only on hardware so we have to cache him for read 1008 each fader is a u32, but uses only the first 16 bit */ 1009 1010 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1011 unsigned int in) 1012 { 1013 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1014 return 0; 1015 1016 return hdspm->mixer->ch[chan].in[in]; 1017 } 1018 1019 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1020 unsigned int pb) 1021 { 1022 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1023 return 0; 1024 return hdspm->mixer->ch[chan].pb[pb]; 1025 } 1026 1027 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1028 unsigned int in, unsigned short data) 1029 { 1030 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1031 return -1; 1032 1033 hdspm_write(hdspm, 1034 HDSPM_MADI_mixerBase + 1035 ((in + 128 * chan) * sizeof(u32)), 1036 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1037 return 0; 1038 } 1039 1040 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1041 unsigned int pb, unsigned short data) 1042 { 1043 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1044 return -1; 1045 1046 hdspm_write(hdspm, 1047 HDSPM_MADI_mixerBase + 1048 ((64 + pb + 128 * chan) * sizeof(u32)), 1049 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1050 return 0; 1051 } 1052 1053 1054 /* enable DMA for specific channels, now available for DSP-MADI */ 1055 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1056 { 1057 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1058 } 1059 1060 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1061 { 1062 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1063 } 1064 1065 /* check if same process is writing and reading */ 1066 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1067 { 1068 unsigned long flags; 1069 int ret = 1; 1070 1071 spin_lock_irqsave(&hdspm->lock, flags); 1072 if ((hdspm->playback_pid != hdspm->capture_pid) && 1073 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1074 ret = 0; 1075 } 1076 spin_unlock_irqrestore(&hdspm->lock, flags); 1077 return ret; 1078 } 1079 1080 /* check for external sample rate */ 1081 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1082 { 1083 unsigned int status, status2, timecode; 1084 int syncref, rate = 0, rate_bits; 1085 1086 switch (hdspm->io_type) { 1087 case AES32: 1088 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1089 status = hdspm_read(hdspm, HDSPM_statusRegister); 1090 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1091 1092 syncref = hdspm_autosync_ref(hdspm); 1093 1094 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1095 status & HDSPM_AES32_wcLock) 1096 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1097 1098 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1099 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1100 status2 & (HDSPM_LockAES >> 1101 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1102 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1103 return 0; 1104 break; 1105 1106 case MADIface: 1107 status = hdspm_read(hdspm, HDSPM_statusRegister); 1108 1109 if (!(status & HDSPM_madiLock)) { 1110 rate = 0; /* no lock */ 1111 } else { 1112 switch (status & (HDSPM_status1_freqMask)) { 1113 case HDSPM_status1_F_0*1: 1114 rate = 32000; break; 1115 case HDSPM_status1_F_0*2: 1116 rate = 44100; break; 1117 case HDSPM_status1_F_0*3: 1118 rate = 48000; break; 1119 case HDSPM_status1_F_0*4: 1120 rate = 64000; break; 1121 case HDSPM_status1_F_0*5: 1122 rate = 88200; break; 1123 case HDSPM_status1_F_0*6: 1124 rate = 96000; break; 1125 case HDSPM_status1_F_0*7: 1126 rate = 128000; break; 1127 case HDSPM_status1_F_0*8: 1128 rate = 176400; break; 1129 case HDSPM_status1_F_0*9: 1130 rate = 192000; break; 1131 default: 1132 rate = 0; break; 1133 } 1134 } 1135 1136 break; 1137 1138 case MADI: 1139 case AIO: 1140 case RayDAT: 1141 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1142 status = hdspm_read(hdspm, HDSPM_statusRegister); 1143 rate = 0; 1144 1145 /* if wordclock has synced freq and wordclock is valid */ 1146 if ((status2 & HDSPM_wcLock) != 0 && 1147 (status2 & HDSPM_SelSyncRef0) == 0) { 1148 1149 rate_bits = status2 & HDSPM_wcFreqMask; 1150 1151 1152 switch (rate_bits) { 1153 case HDSPM_wcFreq32: 1154 rate = 32000; 1155 break; 1156 case HDSPM_wcFreq44_1: 1157 rate = 44100; 1158 break; 1159 case HDSPM_wcFreq48: 1160 rate = 48000; 1161 break; 1162 case HDSPM_wcFreq64: 1163 rate = 64000; 1164 break; 1165 case HDSPM_wcFreq88_2: 1166 rate = 88200; 1167 break; 1168 case HDSPM_wcFreq96: 1169 rate = 96000; 1170 break; 1171 default: 1172 rate = 0; 1173 break; 1174 } 1175 } 1176 1177 /* if rate detected and Syncref is Word than have it, 1178 * word has priority to MADI 1179 */ 1180 if (rate != 0 && 1181 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1182 return rate; 1183 1184 /* maybe a madi input (which is taken if sel sync is madi) */ 1185 if (status & HDSPM_madiLock) { 1186 rate_bits = status & HDSPM_madiFreqMask; 1187 1188 switch (rate_bits) { 1189 case HDSPM_madiFreq32: 1190 rate = 32000; 1191 break; 1192 case HDSPM_madiFreq44_1: 1193 rate = 44100; 1194 break; 1195 case HDSPM_madiFreq48: 1196 rate = 48000; 1197 break; 1198 case HDSPM_madiFreq64: 1199 rate = 64000; 1200 break; 1201 case HDSPM_madiFreq88_2: 1202 rate = 88200; 1203 break; 1204 case HDSPM_madiFreq96: 1205 rate = 96000; 1206 break; 1207 case HDSPM_madiFreq128: 1208 rate = 128000; 1209 break; 1210 case HDSPM_madiFreq176_4: 1211 rate = 176400; 1212 break; 1213 case HDSPM_madiFreq192: 1214 rate = 192000; 1215 break; 1216 default: 1217 rate = 0; 1218 break; 1219 } 1220 } 1221 break; 1222 } 1223 1224 return rate; 1225 } 1226 1227 /* Latency function */ 1228 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1229 { 1230 hdspm->period_bytes = 1 << ((hdspm_decode_latency(hdspm->control_register) + 8)); 1231 } 1232 1233 1234 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1235 { 1236 int position; 1237 1238 position = hdspm_read(hdspm, HDSPM_statusRegister); 1239 1240 switch (hdspm->io_type) { 1241 case RayDAT: 1242 case AIO: 1243 position &= HDSPM_BufferPositionMask; 1244 position /= 4; /* Bytes per sample */ 1245 break; 1246 default: 1247 position = (position & HDSPM_BufferID) ? 1248 (hdspm->period_bytes / 4) : 0; 1249 } 1250 1251 return position; 1252 } 1253 1254 1255 static inline void hdspm_start_audio(struct hdspm * s) 1256 { 1257 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1258 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1259 } 1260 1261 static inline void hdspm_stop_audio(struct hdspm * s) 1262 { 1263 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1264 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1265 } 1266 1267 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1268 static void hdspm_silence_playback(struct hdspm *hdspm) 1269 { 1270 int i; 1271 int n = hdspm->period_bytes; 1272 void *buf = hdspm->playback_buffer; 1273 1274 if (buf == NULL) 1275 return; 1276 1277 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1278 memset(buf, 0, n); 1279 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1280 } 1281 } 1282 1283 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1284 { 1285 int n; 1286 1287 spin_lock_irq(&s->lock); 1288 1289 frames >>= 7; 1290 n = 0; 1291 while (frames) { 1292 n++; 1293 frames >>= 1; 1294 } 1295 s->control_register &= ~HDSPM_LatencyMask; 1296 s->control_register |= hdspm_encode_latency(n); 1297 1298 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1299 1300 hdspm_compute_period_size(s); 1301 1302 spin_unlock_irq(&s->lock); 1303 1304 return 0; 1305 } 1306 1307 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1308 { 1309 u64 freq_const; 1310 1311 if (period == 0) 1312 return 0; 1313 1314 switch (hdspm->io_type) { 1315 case MADI: 1316 case AES32: 1317 freq_const = 110069313433624ULL; 1318 break; 1319 case RayDAT: 1320 case AIO: 1321 freq_const = 104857600000000ULL; 1322 break; 1323 case MADIface: 1324 freq_const = 131072000000000ULL; 1325 } 1326 1327 return div_u64(freq_const, period); 1328 } 1329 1330 1331 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1332 { 1333 u64 n; 1334 1335 if (rate >= 112000) 1336 rate /= 4; 1337 else if (rate >= 56000) 1338 rate /= 2; 1339 1340 switch (hdspm->io_type) { 1341 case MADIface: 1342 n = 131072000000000ULL; /* 125 MHz */ 1343 break; 1344 case MADI: 1345 case AES32: 1346 n = 110069313433624ULL; /* 105 MHz */ 1347 break; 1348 case RayDAT: 1349 case AIO: 1350 n = 104857600000000ULL; /* 100 MHz */ 1351 break; 1352 } 1353 1354 n = div_u64(n, rate); 1355 /* n should be less than 2^32 for being written to FREQ register */ 1356 snd_BUG_ON(n >> 32); 1357 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1358 } 1359 1360 /* dummy set rate lets see what happens */ 1361 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1362 { 1363 int current_rate; 1364 int rate_bits; 1365 int not_set = 0; 1366 int current_speed, target_speed; 1367 1368 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1369 it (e.g. during module initialization). 1370 */ 1371 1372 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1373 1374 /* SLAVE --- */ 1375 if (called_internally) { 1376 1377 /* request from ctl or card initialization 1378 just make a warning an remember setting 1379 for future master mode switching */ 1380 1381 snd_printk(KERN_WARNING "HDSPM: " 1382 "Warning: device is not running " 1383 "as a clock master.\n"); 1384 not_set = 1; 1385 } else { 1386 1387 /* hw_param request while in AutoSync mode */ 1388 int external_freq = 1389 hdspm_external_sample_rate(hdspm); 1390 1391 if (hdspm_autosync_ref(hdspm) == 1392 HDSPM_AUTOSYNC_FROM_NONE) { 1393 1394 snd_printk(KERN_WARNING "HDSPM: " 1395 "Detected no Externel Sync \n"); 1396 not_set = 1; 1397 1398 } else if (rate != external_freq) { 1399 1400 snd_printk(KERN_WARNING "HDSPM: " 1401 "Warning: No AutoSync source for " 1402 "requested rate\n"); 1403 not_set = 1; 1404 } 1405 } 1406 } 1407 1408 current_rate = hdspm->system_sample_rate; 1409 1410 /* Changing between Singe, Double and Quad speed is not 1411 allowed if any substreams are open. This is because such a change 1412 causes a shift in the location of the DMA buffers and a reduction 1413 in the number of available buffers. 1414 1415 Note that a similar but essentially insoluble problem exists for 1416 externally-driven rate changes. All we can do is to flag rate 1417 changes in the read/write routines. 1418 */ 1419 1420 if (current_rate <= 48000) 1421 current_speed = HDSPM_SPEED_SINGLE; 1422 else if (current_rate <= 96000) 1423 current_speed = HDSPM_SPEED_DOUBLE; 1424 else 1425 current_speed = HDSPM_SPEED_QUAD; 1426 1427 if (rate <= 48000) 1428 target_speed = HDSPM_SPEED_SINGLE; 1429 else if (rate <= 96000) 1430 target_speed = HDSPM_SPEED_DOUBLE; 1431 else 1432 target_speed = HDSPM_SPEED_QUAD; 1433 1434 switch (rate) { 1435 case 32000: 1436 rate_bits = HDSPM_Frequency32KHz; 1437 break; 1438 case 44100: 1439 rate_bits = HDSPM_Frequency44_1KHz; 1440 break; 1441 case 48000: 1442 rate_bits = HDSPM_Frequency48KHz; 1443 break; 1444 case 64000: 1445 rate_bits = HDSPM_Frequency64KHz; 1446 break; 1447 case 88200: 1448 rate_bits = HDSPM_Frequency88_2KHz; 1449 break; 1450 case 96000: 1451 rate_bits = HDSPM_Frequency96KHz; 1452 break; 1453 case 128000: 1454 rate_bits = HDSPM_Frequency128KHz; 1455 break; 1456 case 176400: 1457 rate_bits = HDSPM_Frequency176_4KHz; 1458 break; 1459 case 192000: 1460 rate_bits = HDSPM_Frequency192KHz; 1461 break; 1462 default: 1463 return -EINVAL; 1464 } 1465 1466 if (current_speed != target_speed 1467 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1468 snd_printk 1469 (KERN_ERR "HDSPM: " 1470 "cannot change from %s speed to %s speed mode " 1471 "(capture PID = %d, playback PID = %d)\n", 1472 hdspm_speed_names[current_speed], 1473 hdspm_speed_names[target_speed], 1474 hdspm->capture_pid, hdspm->playback_pid); 1475 return -EBUSY; 1476 } 1477 1478 hdspm->control_register &= ~HDSPM_FrequencyMask; 1479 hdspm->control_register |= rate_bits; 1480 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1481 1482 /* For AES32, need to set DDS value in FREQ register 1483 For MADI, also apparently */ 1484 hdspm_set_dds_value(hdspm, rate); 1485 1486 if (AES32 == hdspm->io_type && rate != current_rate) 1487 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1488 1489 hdspm->system_sample_rate = rate; 1490 1491 if (rate <= 48000) { 1492 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1493 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1494 hdspm->max_channels_in = hdspm->ss_in_channels; 1495 hdspm->max_channels_out = hdspm->ss_out_channels; 1496 hdspm->port_names_in = hdspm->port_names_in_ss; 1497 hdspm->port_names_out = hdspm->port_names_out_ss; 1498 } else if (rate <= 96000) { 1499 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1500 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1501 hdspm->max_channels_in = hdspm->ds_in_channels; 1502 hdspm->max_channels_out = hdspm->ds_out_channels; 1503 hdspm->port_names_in = hdspm->port_names_in_ds; 1504 hdspm->port_names_out = hdspm->port_names_out_ds; 1505 } else { 1506 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1507 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1508 hdspm->max_channels_in = hdspm->qs_in_channels; 1509 hdspm->max_channels_out = hdspm->qs_out_channels; 1510 hdspm->port_names_in = hdspm->port_names_in_qs; 1511 hdspm->port_names_out = hdspm->port_names_out_qs; 1512 } 1513 1514 if (not_set != 0) 1515 return -1; 1516 1517 return 0; 1518 } 1519 1520 /* mainly for init to 0 on load */ 1521 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1522 { 1523 int i, j; 1524 unsigned int gain; 1525 1526 if (sgain > UNITY_GAIN) 1527 gain = UNITY_GAIN; 1528 else if (sgain < 0) 1529 gain = 0; 1530 else 1531 gain = sgain; 1532 1533 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1534 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1535 hdspm_write_in_gain(hdspm, i, j, gain); 1536 hdspm_write_pb_gain(hdspm, i, j, gain); 1537 } 1538 } 1539 1540 /*---------------------------------------------------------------------------- 1541 MIDI 1542 ----------------------------------------------------------------------------*/ 1543 1544 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1545 int id) 1546 { 1547 /* the hardware already does the relevant bit-mask with 0xff */ 1548 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1549 } 1550 1551 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1552 int val) 1553 { 1554 /* the hardware already does the relevant bit-mask with 0xff */ 1555 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1556 } 1557 1558 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1559 { 1560 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1561 } 1562 1563 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1564 { 1565 int fifo_bytes_used; 1566 1567 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1568 1569 if (fifo_bytes_used < 128) 1570 return 128 - fifo_bytes_used; 1571 else 1572 return 0; 1573 } 1574 1575 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1576 { 1577 while (snd_hdspm_midi_input_available (hdspm, id)) 1578 snd_hdspm_midi_read_byte (hdspm, id); 1579 } 1580 1581 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1582 { 1583 unsigned long flags; 1584 int n_pending; 1585 int to_write; 1586 int i; 1587 unsigned char buf[128]; 1588 1589 /* Output is not interrupt driven */ 1590 1591 spin_lock_irqsave (&hmidi->lock, flags); 1592 if (hmidi->output && 1593 !snd_rawmidi_transmit_empty (hmidi->output)) { 1594 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1595 hmidi->id); 1596 if (n_pending > 0) { 1597 if (n_pending > (int)sizeof (buf)) 1598 n_pending = sizeof (buf); 1599 1600 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1601 n_pending); 1602 if (to_write > 0) { 1603 for (i = 0; i < to_write; ++i) 1604 snd_hdspm_midi_write_byte (hmidi->hdspm, 1605 hmidi->id, 1606 buf[i]); 1607 } 1608 } 1609 } 1610 spin_unlock_irqrestore (&hmidi->lock, flags); 1611 return 0; 1612 } 1613 1614 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1615 { 1616 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1617 * input FIFO size 1618 */ 1619 unsigned long flags; 1620 int n_pending; 1621 int i; 1622 1623 spin_lock_irqsave (&hmidi->lock, flags); 1624 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1625 if (n_pending > 0) { 1626 if (hmidi->input) { 1627 if (n_pending > (int)sizeof (buf)) 1628 n_pending = sizeof (buf); 1629 for (i = 0; i < n_pending; ++i) 1630 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1631 hmidi->id); 1632 if (n_pending) 1633 snd_rawmidi_receive (hmidi->input, buf, 1634 n_pending); 1635 } else { 1636 /* flush the MIDI input FIFO */ 1637 while (n_pending--) 1638 snd_hdspm_midi_read_byte (hmidi->hdspm, 1639 hmidi->id); 1640 } 1641 } 1642 hmidi->pending = 0; 1643 spin_unlock_irqrestore(&hmidi->lock, flags); 1644 1645 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1646 hmidi->hdspm->control_register |= hmidi->ie; 1647 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1648 hmidi->hdspm->control_register); 1649 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1650 1651 return snd_hdspm_midi_output_write (hmidi); 1652 } 1653 1654 static void 1655 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1656 { 1657 struct hdspm *hdspm; 1658 struct hdspm_midi *hmidi; 1659 unsigned long flags; 1660 1661 hmidi = substream->rmidi->private_data; 1662 hdspm = hmidi->hdspm; 1663 1664 spin_lock_irqsave (&hdspm->lock, flags); 1665 if (up) { 1666 if (!(hdspm->control_register & hmidi->ie)) { 1667 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1668 hdspm->control_register |= hmidi->ie; 1669 } 1670 } else { 1671 hdspm->control_register &= ~hmidi->ie; 1672 } 1673 1674 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1675 spin_unlock_irqrestore (&hdspm->lock, flags); 1676 } 1677 1678 static void snd_hdspm_midi_output_timer(unsigned long data) 1679 { 1680 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1681 unsigned long flags; 1682 1683 snd_hdspm_midi_output_write(hmidi); 1684 spin_lock_irqsave (&hmidi->lock, flags); 1685 1686 /* this does not bump hmidi->istimer, because the 1687 kernel automatically removed the timer when it 1688 expired, and we are now adding it back, thus 1689 leaving istimer wherever it was set before. 1690 */ 1691 1692 if (hmidi->istimer) { 1693 hmidi->timer.expires = 1 + jiffies; 1694 add_timer(&hmidi->timer); 1695 } 1696 1697 spin_unlock_irqrestore (&hmidi->lock, flags); 1698 } 1699 1700 static void 1701 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1702 { 1703 struct hdspm_midi *hmidi; 1704 unsigned long flags; 1705 1706 hmidi = substream->rmidi->private_data; 1707 spin_lock_irqsave (&hmidi->lock, flags); 1708 if (up) { 1709 if (!hmidi->istimer) { 1710 init_timer(&hmidi->timer); 1711 hmidi->timer.function = snd_hdspm_midi_output_timer; 1712 hmidi->timer.data = (unsigned long) hmidi; 1713 hmidi->timer.expires = 1 + jiffies; 1714 add_timer(&hmidi->timer); 1715 hmidi->istimer++; 1716 } 1717 } else { 1718 if (hmidi->istimer && --hmidi->istimer <= 0) 1719 del_timer (&hmidi->timer); 1720 } 1721 spin_unlock_irqrestore (&hmidi->lock, flags); 1722 if (up) 1723 snd_hdspm_midi_output_write(hmidi); 1724 } 1725 1726 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1727 { 1728 struct hdspm_midi *hmidi; 1729 1730 hmidi = substream->rmidi->private_data; 1731 spin_lock_irq (&hmidi->lock); 1732 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1733 hmidi->input = substream; 1734 spin_unlock_irq (&hmidi->lock); 1735 1736 return 0; 1737 } 1738 1739 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1740 { 1741 struct hdspm_midi *hmidi; 1742 1743 hmidi = substream->rmidi->private_data; 1744 spin_lock_irq (&hmidi->lock); 1745 hmidi->output = substream; 1746 spin_unlock_irq (&hmidi->lock); 1747 1748 return 0; 1749 } 1750 1751 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1752 { 1753 struct hdspm_midi *hmidi; 1754 1755 snd_hdspm_midi_input_trigger (substream, 0); 1756 1757 hmidi = substream->rmidi->private_data; 1758 spin_lock_irq (&hmidi->lock); 1759 hmidi->input = NULL; 1760 spin_unlock_irq (&hmidi->lock); 1761 1762 return 0; 1763 } 1764 1765 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1766 { 1767 struct hdspm_midi *hmidi; 1768 1769 snd_hdspm_midi_output_trigger (substream, 0); 1770 1771 hmidi = substream->rmidi->private_data; 1772 spin_lock_irq (&hmidi->lock); 1773 hmidi->output = NULL; 1774 spin_unlock_irq (&hmidi->lock); 1775 1776 return 0; 1777 } 1778 1779 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1780 { 1781 .open = snd_hdspm_midi_output_open, 1782 .close = snd_hdspm_midi_output_close, 1783 .trigger = snd_hdspm_midi_output_trigger, 1784 }; 1785 1786 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1787 { 1788 .open = snd_hdspm_midi_input_open, 1789 .close = snd_hdspm_midi_input_close, 1790 .trigger = snd_hdspm_midi_input_trigger, 1791 }; 1792 1793 static int __devinit snd_hdspm_create_midi (struct snd_card *card, 1794 struct hdspm *hdspm, int id) 1795 { 1796 int err; 1797 char buf[32]; 1798 1799 hdspm->midi[id].id = id; 1800 hdspm->midi[id].hdspm = hdspm; 1801 spin_lock_init (&hdspm->midi[id].lock); 1802 1803 if (0 == id) { 1804 if (MADIface == hdspm->io_type) { 1805 /* MIDI-over-MADI on HDSPe MADIface */ 1806 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1807 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1808 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1809 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1810 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1811 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1812 } else { 1813 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1814 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1815 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1816 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1817 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1818 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1819 } 1820 } else if (1 == id) { 1821 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1822 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1823 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1824 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1825 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1826 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1827 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1828 /* MIDI-over-MADI on HDSPe MADI */ 1829 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1830 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1831 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1832 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1833 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1834 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1835 } else if (2 == id) { 1836 /* TCO MTC, read only */ 1837 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1838 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1839 hdspm->midi[2].dataOut = -1; 1840 hdspm->midi[2].statusOut = -1; 1841 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1842 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1843 } else if (3 == id) { 1844 /* TCO MTC on HDSPe MADI */ 1845 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1846 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1847 hdspm->midi[3].dataOut = -1; 1848 hdspm->midi[3].statusOut = -1; 1849 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1850 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1851 } 1852 1853 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1854 (MADIface == hdspm->io_type)))) { 1855 if ((id == 0) && (MADIface == hdspm->io_type)) { 1856 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1857 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1858 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1859 } else { 1860 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 1861 } 1862 err = snd_rawmidi_new(card, buf, id, 1, 1, 1863 &hdspm->midi[id].rmidi); 1864 if (err < 0) 1865 return err; 1866 1867 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 1868 card->id, id+1); 1869 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1870 1871 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1872 SNDRV_RAWMIDI_STREAM_OUTPUT, 1873 &snd_hdspm_midi_output); 1874 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1875 SNDRV_RAWMIDI_STREAM_INPUT, 1876 &snd_hdspm_midi_input); 1877 1878 hdspm->midi[id].rmidi->info_flags |= 1879 SNDRV_RAWMIDI_INFO_OUTPUT | 1880 SNDRV_RAWMIDI_INFO_INPUT | 1881 SNDRV_RAWMIDI_INFO_DUPLEX; 1882 } else { 1883 /* TCO MTC, read only */ 1884 sprintf(buf, "%s MTC %d", card->shortname, id+1); 1885 err = snd_rawmidi_new(card, buf, id, 1, 1, 1886 &hdspm->midi[id].rmidi); 1887 if (err < 0) 1888 return err; 1889 1890 sprintf(hdspm->midi[id].rmidi->name, 1891 "%s MTC %d", card->id, id+1); 1892 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1893 1894 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1895 SNDRV_RAWMIDI_STREAM_INPUT, 1896 &snd_hdspm_midi_input); 1897 1898 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 1899 } 1900 1901 return 0; 1902 } 1903 1904 1905 static void hdspm_midi_tasklet(unsigned long arg) 1906 { 1907 struct hdspm *hdspm = (struct hdspm *)arg; 1908 int i = 0; 1909 1910 while (i < hdspm->midiPorts) { 1911 if (hdspm->midi[i].pending) 1912 snd_hdspm_midi_input_read(&hdspm->midi[i]); 1913 1914 i++; 1915 } 1916 } 1917 1918 1919 /*----------------------------------------------------------------------------- 1920 Status Interface 1921 ----------------------------------------------------------------------------*/ 1922 1923 /* get the system sample rate which is set */ 1924 1925 1926 /** 1927 * Calculate the real sample rate from the 1928 * current DDS value. 1929 **/ 1930 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 1931 { 1932 unsigned int period, rate; 1933 1934 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 1935 rate = hdspm_calc_dds_value(hdspm, period); 1936 1937 return rate; 1938 } 1939 1940 1941 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1942 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1943 .name = xname, \ 1944 .index = xindex, \ 1945 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1946 .info = snd_hdspm_info_system_sample_rate, \ 1947 .get = snd_hdspm_get_system_sample_rate \ 1948 } 1949 1950 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 1951 struct snd_ctl_elem_info *uinfo) 1952 { 1953 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1954 uinfo->count = 1; 1955 uinfo->value.integer.min = 27000; 1956 uinfo->value.integer.max = 207000; 1957 uinfo->value.integer.step = 1; 1958 return 0; 1959 } 1960 1961 1962 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 1963 struct snd_ctl_elem_value * 1964 ucontrol) 1965 { 1966 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 1967 1968 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 1969 return 0; 1970 } 1971 1972 1973 /** 1974 * Returns the WordClock sample rate class for the given card. 1975 **/ 1976 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 1977 { 1978 int status; 1979 1980 switch (hdspm->io_type) { 1981 case RayDAT: 1982 case AIO: 1983 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 1984 return (status >> 16) & 0xF; 1985 break; 1986 default: 1987 break; 1988 } 1989 1990 1991 return 0; 1992 } 1993 1994 1995 /** 1996 * Returns the TCO sample rate class for the given card. 1997 **/ 1998 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 1999 { 2000 int status; 2001 2002 if (hdspm->tco) { 2003 switch (hdspm->io_type) { 2004 case RayDAT: 2005 case AIO: 2006 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2007 return (status >> 20) & 0xF; 2008 break; 2009 default: 2010 break; 2011 } 2012 } 2013 2014 return 0; 2015 } 2016 2017 2018 /** 2019 * Returns the SYNC_IN sample rate class for the given card. 2020 **/ 2021 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2022 { 2023 int status; 2024 2025 if (hdspm->tco) { 2026 switch (hdspm->io_type) { 2027 case RayDAT: 2028 case AIO: 2029 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2030 return (status >> 12) & 0xF; 2031 break; 2032 default: 2033 break; 2034 } 2035 } 2036 2037 return 0; 2038 } 2039 2040 2041 /** 2042 * Returns the sample rate class for input source <idx> for 2043 * 'new style' cards like the AIO and RayDAT. 2044 **/ 2045 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2046 { 2047 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2048 2049 return (status >> (idx*4)) & 0xF; 2050 } 2051 2052 2053 2054 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2055 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2056 .name = xname, \ 2057 .private_value = xindex, \ 2058 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2059 .info = snd_hdspm_info_autosync_sample_rate, \ 2060 .get = snd_hdspm_get_autosync_sample_rate \ 2061 } 2062 2063 2064 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2065 struct snd_ctl_elem_info *uinfo) 2066 { 2067 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2068 uinfo->count = 1; 2069 uinfo->value.enumerated.items = 10; 2070 2071 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2072 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2073 strcpy(uinfo->value.enumerated.name, 2074 texts_freq[uinfo->value.enumerated.item]); 2075 return 0; 2076 } 2077 2078 2079 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2080 struct snd_ctl_elem_value * 2081 ucontrol) 2082 { 2083 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2084 2085 switch (hdspm->io_type) { 2086 case RayDAT: 2087 switch (kcontrol->private_value) { 2088 case 0: 2089 ucontrol->value.enumerated.item[0] = 2090 hdspm_get_wc_sample_rate(hdspm); 2091 break; 2092 case 7: 2093 ucontrol->value.enumerated.item[0] = 2094 hdspm_get_tco_sample_rate(hdspm); 2095 break; 2096 case 8: 2097 ucontrol->value.enumerated.item[0] = 2098 hdspm_get_sync_in_sample_rate(hdspm); 2099 break; 2100 default: 2101 ucontrol->value.enumerated.item[0] = 2102 hdspm_get_s1_sample_rate(hdspm, 2103 kcontrol->private_value-1); 2104 } 2105 2106 case AIO: 2107 switch (kcontrol->private_value) { 2108 case 0: /* WC */ 2109 ucontrol->value.enumerated.item[0] = 2110 hdspm_get_wc_sample_rate(hdspm); 2111 break; 2112 case 4: /* TCO */ 2113 ucontrol->value.enumerated.item[0] = 2114 hdspm_get_tco_sample_rate(hdspm); 2115 break; 2116 case 5: /* SYNC_IN */ 2117 ucontrol->value.enumerated.item[0] = 2118 hdspm_get_sync_in_sample_rate(hdspm); 2119 break; 2120 default: 2121 ucontrol->value.enumerated.item[0] = 2122 hdspm_get_s1_sample_rate(hdspm, 2123 ucontrol->id.index-1); 2124 } 2125 2126 case AES32: 2127 2128 switch (kcontrol->private_value) { 2129 case 0: /* WC */ 2130 ucontrol->value.enumerated.item[0] = 2131 hdspm_get_wc_sample_rate(hdspm); 2132 break; 2133 case 9: /* TCO */ 2134 ucontrol->value.enumerated.item[0] = 2135 hdspm_get_tco_sample_rate(hdspm); 2136 break; 2137 case 10: /* SYNC_IN */ 2138 ucontrol->value.enumerated.item[0] = 2139 hdspm_get_sync_in_sample_rate(hdspm); 2140 break; 2141 default: /* AES1 to AES8 */ 2142 ucontrol->value.enumerated.item[0] = 2143 hdspm_get_s1_sample_rate(hdspm, 2144 kcontrol->private_value-1); 2145 break; 2146 2147 } 2148 default: 2149 break; 2150 } 2151 2152 return 0; 2153 } 2154 2155 2156 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2157 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2158 .name = xname, \ 2159 .index = xindex, \ 2160 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2161 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2162 .info = snd_hdspm_info_system_clock_mode, \ 2163 .get = snd_hdspm_get_system_clock_mode, \ 2164 .put = snd_hdspm_put_system_clock_mode, \ 2165 } 2166 2167 2168 /** 2169 * Returns the system clock mode for the given card. 2170 * @returns 0 - master, 1 - slave 2171 **/ 2172 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2173 { 2174 switch (hdspm->io_type) { 2175 case AIO: 2176 case RayDAT: 2177 if (hdspm->settings_register & HDSPM_c0Master) 2178 return 0; 2179 break; 2180 2181 default: 2182 if (hdspm->control_register & HDSPM_ClockModeMaster) 2183 return 0; 2184 } 2185 2186 return 1; 2187 } 2188 2189 2190 /** 2191 * Sets the system clock mode. 2192 * @param mode 0 - master, 1 - slave 2193 **/ 2194 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2195 { 2196 switch (hdspm->io_type) { 2197 case AIO: 2198 case RayDAT: 2199 if (0 == mode) 2200 hdspm->settings_register |= HDSPM_c0Master; 2201 else 2202 hdspm->settings_register &= ~HDSPM_c0Master; 2203 2204 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2205 break; 2206 2207 default: 2208 if (0 == mode) 2209 hdspm->control_register |= HDSPM_ClockModeMaster; 2210 else 2211 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2212 2213 hdspm_write(hdspm, HDSPM_controlRegister, 2214 hdspm->control_register); 2215 } 2216 } 2217 2218 2219 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2220 struct snd_ctl_elem_info *uinfo) 2221 { 2222 static char *texts[] = { "Master", "AutoSync" }; 2223 2224 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2225 uinfo->count = 1; 2226 uinfo->value.enumerated.items = 2; 2227 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2228 uinfo->value.enumerated.item = 2229 uinfo->value.enumerated.items - 1; 2230 strcpy(uinfo->value.enumerated.name, 2231 texts[uinfo->value.enumerated.item]); 2232 return 0; 2233 } 2234 2235 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2236 struct snd_ctl_elem_value *ucontrol) 2237 { 2238 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2239 2240 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2241 return 0; 2242 } 2243 2244 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2245 struct snd_ctl_elem_value *ucontrol) 2246 { 2247 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2248 int val; 2249 2250 if (!snd_hdspm_use_is_exclusive(hdspm)) 2251 return -EBUSY; 2252 2253 val = ucontrol->value.enumerated.item[0]; 2254 if (val < 0) 2255 val = 0; 2256 else if (val > 1) 2257 val = 1; 2258 2259 hdspm_set_system_clock_mode(hdspm, val); 2260 2261 return 0; 2262 } 2263 2264 2265 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2266 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2267 .name = xname, \ 2268 .index = xindex, \ 2269 .info = snd_hdspm_info_clock_source, \ 2270 .get = snd_hdspm_get_clock_source, \ 2271 .put = snd_hdspm_put_clock_source \ 2272 } 2273 2274 2275 static int hdspm_clock_source(struct hdspm * hdspm) 2276 { 2277 switch (hdspm->system_sample_rate) { 2278 case 32000: return 0; 2279 case 44100: return 1; 2280 case 48000: return 2; 2281 case 64000: return 3; 2282 case 88200: return 4; 2283 case 96000: return 5; 2284 case 128000: return 6; 2285 case 176400: return 7; 2286 case 192000: return 8; 2287 } 2288 2289 return -1; 2290 } 2291 2292 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2293 { 2294 int rate; 2295 switch (mode) { 2296 case 0: 2297 rate = 32000; break; 2298 case 1: 2299 rate = 44100; break; 2300 case 2: 2301 rate = 48000; break; 2302 case 3: 2303 rate = 64000; break; 2304 case 4: 2305 rate = 88200; break; 2306 case 5: 2307 rate = 96000; break; 2308 case 6: 2309 rate = 128000; break; 2310 case 7: 2311 rate = 176400; break; 2312 case 8: 2313 rate = 192000; break; 2314 default: 2315 rate = 48000; 2316 } 2317 hdspm_set_rate(hdspm, rate, 1); 2318 return 0; 2319 } 2320 2321 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2322 struct snd_ctl_elem_info *uinfo) 2323 { 2324 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2325 uinfo->count = 1; 2326 uinfo->value.enumerated.items = 9; 2327 2328 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2329 uinfo->value.enumerated.item = 2330 uinfo->value.enumerated.items - 1; 2331 2332 strcpy(uinfo->value.enumerated.name, 2333 texts_freq[uinfo->value.enumerated.item+1]); 2334 2335 return 0; 2336 } 2337 2338 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2339 struct snd_ctl_elem_value *ucontrol) 2340 { 2341 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2342 2343 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2344 return 0; 2345 } 2346 2347 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2348 struct snd_ctl_elem_value *ucontrol) 2349 { 2350 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2351 int change; 2352 int val; 2353 2354 if (!snd_hdspm_use_is_exclusive(hdspm)) 2355 return -EBUSY; 2356 val = ucontrol->value.enumerated.item[0]; 2357 if (val < 0) 2358 val = 0; 2359 if (val > 9) 2360 val = 9; 2361 spin_lock_irq(&hdspm->lock); 2362 if (val != hdspm_clock_source(hdspm)) 2363 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2364 else 2365 change = 0; 2366 spin_unlock_irq(&hdspm->lock); 2367 return change; 2368 } 2369 2370 2371 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2372 {.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2373 .name = xname, \ 2374 .index = xindex, \ 2375 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2376 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2377 .info = snd_hdspm_info_pref_sync_ref, \ 2378 .get = snd_hdspm_get_pref_sync_ref, \ 2379 .put = snd_hdspm_put_pref_sync_ref \ 2380 } 2381 2382 2383 /** 2384 * Returns the current preferred sync reference setting. 2385 * The semantics of the return value are depending on the 2386 * card, please see the comments for clarification. 2387 **/ 2388 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2389 { 2390 switch (hdspm->io_type) { 2391 case AES32: 2392 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2393 case 0: return 0; /* WC */ 2394 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2395 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2396 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2397 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2398 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2399 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2400 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2401 return 7; /* AES 7 */ 2402 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2403 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2404 } 2405 break; 2406 2407 case MADI: 2408 case MADIface: 2409 if (hdspm->tco) { 2410 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2411 case 0: return 0; /* WC */ 2412 case HDSPM_SyncRef0: return 1; /* MADI */ 2413 case HDSPM_SyncRef1: return 2; /* TCO */ 2414 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2415 return 3; /* SYNC_IN */ 2416 } 2417 } else { 2418 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2419 case 0: return 0; /* WC */ 2420 case HDSPM_SyncRef0: return 1; /* MADI */ 2421 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2422 return 2; /* SYNC_IN */ 2423 } 2424 } 2425 break; 2426 2427 case RayDAT: 2428 if (hdspm->tco) { 2429 switch ((hdspm->settings_register & 2430 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2431 case 0: return 0; /* WC */ 2432 case 3: return 1; /* ADAT 1 */ 2433 case 4: return 2; /* ADAT 2 */ 2434 case 5: return 3; /* ADAT 3 */ 2435 case 6: return 4; /* ADAT 4 */ 2436 case 1: return 5; /* AES */ 2437 case 2: return 6; /* SPDIF */ 2438 case 9: return 7; /* TCO */ 2439 case 10: return 8; /* SYNC_IN */ 2440 } 2441 } else { 2442 switch ((hdspm->settings_register & 2443 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2444 case 0: return 0; /* WC */ 2445 case 3: return 1; /* ADAT 1 */ 2446 case 4: return 2; /* ADAT 2 */ 2447 case 5: return 3; /* ADAT 3 */ 2448 case 6: return 4; /* ADAT 4 */ 2449 case 1: return 5; /* AES */ 2450 case 2: return 6; /* SPDIF */ 2451 case 10: return 7; /* SYNC_IN */ 2452 } 2453 } 2454 2455 break; 2456 2457 case AIO: 2458 if (hdspm->tco) { 2459 switch ((hdspm->settings_register & 2460 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2461 case 0: return 0; /* WC */ 2462 case 3: return 1; /* ADAT */ 2463 case 1: return 2; /* AES */ 2464 case 2: return 3; /* SPDIF */ 2465 case 9: return 4; /* TCO */ 2466 case 10: return 5; /* SYNC_IN */ 2467 } 2468 } else { 2469 switch ((hdspm->settings_register & 2470 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2471 case 0: return 0; /* WC */ 2472 case 3: return 1; /* ADAT */ 2473 case 1: return 2; /* AES */ 2474 case 2: return 3; /* SPDIF */ 2475 case 10: return 4; /* SYNC_IN */ 2476 } 2477 } 2478 2479 break; 2480 } 2481 2482 return -1; 2483 } 2484 2485 2486 /** 2487 * Set the preferred sync reference to <pref>. The semantics 2488 * of <pref> are depending on the card type, see the comments 2489 * for clarification. 2490 **/ 2491 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2492 { 2493 int p = 0; 2494 2495 switch (hdspm->io_type) { 2496 case AES32: 2497 hdspm->control_register &= ~HDSPM_SyncRefMask; 2498 switch (pref) { 2499 case 0: /* WC */ 2500 break; 2501 case 1: /* AES 1 */ 2502 hdspm->control_register |= HDSPM_SyncRef0; 2503 break; 2504 case 2: /* AES 2 */ 2505 hdspm->control_register |= HDSPM_SyncRef1; 2506 break; 2507 case 3: /* AES 3 */ 2508 hdspm->control_register |= 2509 HDSPM_SyncRef1+HDSPM_SyncRef0; 2510 break; 2511 case 4: /* AES 4 */ 2512 hdspm->control_register |= HDSPM_SyncRef2; 2513 break; 2514 case 5: /* AES 5 */ 2515 hdspm->control_register |= 2516 HDSPM_SyncRef2+HDSPM_SyncRef0; 2517 break; 2518 case 6: /* AES 6 */ 2519 hdspm->control_register |= 2520 HDSPM_SyncRef2+HDSPM_SyncRef1; 2521 break; 2522 case 7: /* AES 7 */ 2523 hdspm->control_register |= 2524 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2525 break; 2526 case 8: /* AES 8 */ 2527 hdspm->control_register |= HDSPM_SyncRef3; 2528 break; 2529 case 9: /* TCO */ 2530 hdspm->control_register |= 2531 HDSPM_SyncRef3+HDSPM_SyncRef0; 2532 break; 2533 default: 2534 return -1; 2535 } 2536 2537 break; 2538 2539 case MADI: 2540 case MADIface: 2541 hdspm->control_register &= ~HDSPM_SyncRefMask; 2542 if (hdspm->tco) { 2543 switch (pref) { 2544 case 0: /* WC */ 2545 break; 2546 case 1: /* MADI */ 2547 hdspm->control_register |= HDSPM_SyncRef0; 2548 break; 2549 case 2: /* TCO */ 2550 hdspm->control_register |= HDSPM_SyncRef1; 2551 break; 2552 case 3: /* SYNC_IN */ 2553 hdspm->control_register |= 2554 HDSPM_SyncRef0+HDSPM_SyncRef1; 2555 break; 2556 default: 2557 return -1; 2558 } 2559 } else { 2560 switch (pref) { 2561 case 0: /* WC */ 2562 break; 2563 case 1: /* MADI */ 2564 hdspm->control_register |= HDSPM_SyncRef0; 2565 break; 2566 case 2: /* SYNC_IN */ 2567 hdspm->control_register |= 2568 HDSPM_SyncRef0+HDSPM_SyncRef1; 2569 break; 2570 default: 2571 return -1; 2572 } 2573 } 2574 2575 break; 2576 2577 case RayDAT: 2578 if (hdspm->tco) { 2579 switch (pref) { 2580 case 0: p = 0; break; /* WC */ 2581 case 1: p = 3; break; /* ADAT 1 */ 2582 case 2: p = 4; break; /* ADAT 2 */ 2583 case 3: p = 5; break; /* ADAT 3 */ 2584 case 4: p = 6; break; /* ADAT 4 */ 2585 case 5: p = 1; break; /* AES */ 2586 case 6: p = 2; break; /* SPDIF */ 2587 case 7: p = 9; break; /* TCO */ 2588 case 8: p = 10; break; /* SYNC_IN */ 2589 default: return -1; 2590 } 2591 } else { 2592 switch (pref) { 2593 case 0: p = 0; break; /* WC */ 2594 case 1: p = 3; break; /* ADAT 1 */ 2595 case 2: p = 4; break; /* ADAT 2 */ 2596 case 3: p = 5; break; /* ADAT 3 */ 2597 case 4: p = 6; break; /* ADAT 4 */ 2598 case 5: p = 1; break; /* AES */ 2599 case 6: p = 2; break; /* SPDIF */ 2600 case 7: p = 10; break; /* SYNC_IN */ 2601 default: return -1; 2602 } 2603 } 2604 break; 2605 2606 case AIO: 2607 if (hdspm->tco) { 2608 switch (pref) { 2609 case 0: p = 0; break; /* WC */ 2610 case 1: p = 3; break; /* ADAT */ 2611 case 2: p = 1; break; /* AES */ 2612 case 3: p = 2; break; /* SPDIF */ 2613 case 4: p = 9; break; /* TCO */ 2614 case 5: p = 10; break; /* SYNC_IN */ 2615 default: return -1; 2616 } 2617 } else { 2618 switch (pref) { 2619 case 0: p = 0; break; /* WC */ 2620 case 1: p = 3; break; /* ADAT */ 2621 case 2: p = 1; break; /* AES */ 2622 case 3: p = 2; break; /* SPDIF */ 2623 case 4: p = 10; break; /* SYNC_IN */ 2624 default: return -1; 2625 } 2626 } 2627 break; 2628 } 2629 2630 switch (hdspm->io_type) { 2631 case RayDAT: 2632 case AIO: 2633 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2634 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2635 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2636 break; 2637 2638 case MADI: 2639 case MADIface: 2640 case AES32: 2641 hdspm_write(hdspm, HDSPM_controlRegister, 2642 hdspm->control_register); 2643 } 2644 2645 return 0; 2646 } 2647 2648 2649 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2650 struct snd_ctl_elem_info *uinfo) 2651 { 2652 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2653 2654 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2655 uinfo->count = 1; 2656 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2657 2658 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2659 uinfo->value.enumerated.item = 2660 uinfo->value.enumerated.items - 1; 2661 2662 strcpy(uinfo->value.enumerated.name, 2663 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2664 2665 return 0; 2666 } 2667 2668 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2669 struct snd_ctl_elem_value *ucontrol) 2670 { 2671 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2672 int psf = hdspm_pref_sync_ref(hdspm); 2673 2674 if (psf >= 0) { 2675 ucontrol->value.enumerated.item[0] = psf; 2676 return 0; 2677 } 2678 2679 return -1; 2680 } 2681 2682 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2683 struct snd_ctl_elem_value *ucontrol) 2684 { 2685 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2686 int val, change = 0; 2687 2688 if (!snd_hdspm_use_is_exclusive(hdspm)) 2689 return -EBUSY; 2690 2691 val = ucontrol->value.enumerated.item[0]; 2692 2693 if (val < 0) 2694 val = 0; 2695 else if (val >= hdspm->texts_autosync_items) 2696 val = hdspm->texts_autosync_items-1; 2697 2698 spin_lock_irq(&hdspm->lock); 2699 if (val != hdspm_pref_sync_ref(hdspm)) 2700 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2701 2702 spin_unlock_irq(&hdspm->lock); 2703 return change; 2704 } 2705 2706 2707 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2708 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2709 .name = xname, \ 2710 .index = xindex, \ 2711 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2712 .info = snd_hdspm_info_autosync_ref, \ 2713 .get = snd_hdspm_get_autosync_ref, \ 2714 } 2715 2716 static int hdspm_autosync_ref(struct hdspm *hdspm) 2717 { 2718 if (AES32 == hdspm->io_type) { 2719 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2720 unsigned int syncref = 2721 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2722 if (syncref == 0) 2723 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2724 if (syncref <= 8) 2725 return syncref; 2726 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2727 } else if (MADI == hdspm->io_type) { 2728 /* This looks at the autosync selected sync reference */ 2729 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2730 2731 switch (status2 & HDSPM_SelSyncRefMask) { 2732 case HDSPM_SelSyncRef_WORD: 2733 return HDSPM_AUTOSYNC_FROM_WORD; 2734 case HDSPM_SelSyncRef_MADI: 2735 return HDSPM_AUTOSYNC_FROM_MADI; 2736 case HDSPM_SelSyncRef_TCO: 2737 return HDSPM_AUTOSYNC_FROM_TCO; 2738 case HDSPM_SelSyncRef_SyncIn: 2739 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2740 case HDSPM_SelSyncRef_NVALID: 2741 return HDSPM_AUTOSYNC_FROM_NONE; 2742 default: 2743 return 0; 2744 } 2745 2746 } 2747 return 0; 2748 } 2749 2750 2751 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2752 struct snd_ctl_elem_info *uinfo) 2753 { 2754 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2755 2756 if (AES32 == hdspm->io_type) { 2757 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2758 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2759 2760 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2761 uinfo->count = 1; 2762 uinfo->value.enumerated.items = 10; 2763 if (uinfo->value.enumerated.item >= 2764 uinfo->value.enumerated.items) 2765 uinfo->value.enumerated.item = 2766 uinfo->value.enumerated.items - 1; 2767 strcpy(uinfo->value.enumerated.name, 2768 texts[uinfo->value.enumerated.item]); 2769 } else if (MADI == hdspm->io_type) { 2770 static char *texts[] = {"Word Clock", "MADI", "TCO", 2771 "Sync In", "None" }; 2772 2773 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2774 uinfo->count = 1; 2775 uinfo->value.enumerated.items = 5; 2776 if (uinfo->value.enumerated.item >= 2777 uinfo->value.enumerated.items) 2778 uinfo->value.enumerated.item = 2779 uinfo->value.enumerated.items - 1; 2780 strcpy(uinfo->value.enumerated.name, 2781 texts[uinfo->value.enumerated.item]); 2782 } 2783 return 0; 2784 } 2785 2786 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2787 struct snd_ctl_elem_value *ucontrol) 2788 { 2789 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2790 2791 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2792 return 0; 2793 } 2794 2795 2796 #define HDSPM_LINE_OUT(xname, xindex) \ 2797 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2798 .name = xname, \ 2799 .index = xindex, \ 2800 .info = snd_hdspm_info_line_out, \ 2801 .get = snd_hdspm_get_line_out, \ 2802 .put = snd_hdspm_put_line_out \ 2803 } 2804 2805 static int hdspm_line_out(struct hdspm * hdspm) 2806 { 2807 return (hdspm->control_register & HDSPM_LineOut) ? 1 : 0; 2808 } 2809 2810 2811 static int hdspm_set_line_output(struct hdspm * hdspm, int out) 2812 { 2813 if (out) 2814 hdspm->control_register |= HDSPM_LineOut; 2815 else 2816 hdspm->control_register &= ~HDSPM_LineOut; 2817 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2818 2819 return 0; 2820 } 2821 2822 #define snd_hdspm_info_line_out snd_ctl_boolean_mono_info 2823 2824 static int snd_hdspm_get_line_out(struct snd_kcontrol *kcontrol, 2825 struct snd_ctl_elem_value *ucontrol) 2826 { 2827 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2828 2829 spin_lock_irq(&hdspm->lock); 2830 ucontrol->value.integer.value[0] = hdspm_line_out(hdspm); 2831 spin_unlock_irq(&hdspm->lock); 2832 return 0; 2833 } 2834 2835 static int snd_hdspm_put_line_out(struct snd_kcontrol *kcontrol, 2836 struct snd_ctl_elem_value *ucontrol) 2837 { 2838 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2839 int change; 2840 unsigned int val; 2841 2842 if (!snd_hdspm_use_is_exclusive(hdspm)) 2843 return -EBUSY; 2844 val = ucontrol->value.integer.value[0] & 1; 2845 spin_lock_irq(&hdspm->lock); 2846 change = (int) val != hdspm_line_out(hdspm); 2847 hdspm_set_line_output(hdspm, val); 2848 spin_unlock_irq(&hdspm->lock); 2849 return change; 2850 } 2851 2852 2853 #define HDSPM_TX_64(xname, xindex) \ 2854 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2855 .name = xname, \ 2856 .index = xindex, \ 2857 .info = snd_hdspm_info_tx_64, \ 2858 .get = snd_hdspm_get_tx_64, \ 2859 .put = snd_hdspm_put_tx_64 \ 2860 } 2861 2862 static int hdspm_tx_64(struct hdspm * hdspm) 2863 { 2864 return (hdspm->control_register & HDSPM_TX_64ch) ? 1 : 0; 2865 } 2866 2867 static int hdspm_set_tx_64(struct hdspm * hdspm, int out) 2868 { 2869 if (out) 2870 hdspm->control_register |= HDSPM_TX_64ch; 2871 else 2872 hdspm->control_register &= ~HDSPM_TX_64ch; 2873 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2874 2875 return 0; 2876 } 2877 2878 #define snd_hdspm_info_tx_64 snd_ctl_boolean_mono_info 2879 2880 static int snd_hdspm_get_tx_64(struct snd_kcontrol *kcontrol, 2881 struct snd_ctl_elem_value *ucontrol) 2882 { 2883 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2884 2885 spin_lock_irq(&hdspm->lock); 2886 ucontrol->value.integer.value[0] = hdspm_tx_64(hdspm); 2887 spin_unlock_irq(&hdspm->lock); 2888 return 0; 2889 } 2890 2891 static int snd_hdspm_put_tx_64(struct snd_kcontrol *kcontrol, 2892 struct snd_ctl_elem_value *ucontrol) 2893 { 2894 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2895 int change; 2896 unsigned int val; 2897 2898 if (!snd_hdspm_use_is_exclusive(hdspm)) 2899 return -EBUSY; 2900 val = ucontrol->value.integer.value[0] & 1; 2901 spin_lock_irq(&hdspm->lock); 2902 change = (int) val != hdspm_tx_64(hdspm); 2903 hdspm_set_tx_64(hdspm, val); 2904 spin_unlock_irq(&hdspm->lock); 2905 return change; 2906 } 2907 2908 2909 #define HDSPM_C_TMS(xname, xindex) \ 2910 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2911 .name = xname, \ 2912 .index = xindex, \ 2913 .info = snd_hdspm_info_c_tms, \ 2914 .get = snd_hdspm_get_c_tms, \ 2915 .put = snd_hdspm_put_c_tms \ 2916 } 2917 2918 static int hdspm_c_tms(struct hdspm * hdspm) 2919 { 2920 return (hdspm->control_register & HDSPM_clr_tms) ? 1 : 0; 2921 } 2922 2923 static int hdspm_set_c_tms(struct hdspm * hdspm, int out) 2924 { 2925 if (out) 2926 hdspm->control_register |= HDSPM_clr_tms; 2927 else 2928 hdspm->control_register &= ~HDSPM_clr_tms; 2929 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2930 2931 return 0; 2932 } 2933 2934 #define snd_hdspm_info_c_tms snd_ctl_boolean_mono_info 2935 2936 static int snd_hdspm_get_c_tms(struct snd_kcontrol *kcontrol, 2937 struct snd_ctl_elem_value *ucontrol) 2938 { 2939 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2940 2941 spin_lock_irq(&hdspm->lock); 2942 ucontrol->value.integer.value[0] = hdspm_c_tms(hdspm); 2943 spin_unlock_irq(&hdspm->lock); 2944 return 0; 2945 } 2946 2947 static int snd_hdspm_put_c_tms(struct snd_kcontrol *kcontrol, 2948 struct snd_ctl_elem_value *ucontrol) 2949 { 2950 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2951 int change; 2952 unsigned int val; 2953 2954 if (!snd_hdspm_use_is_exclusive(hdspm)) 2955 return -EBUSY; 2956 val = ucontrol->value.integer.value[0] & 1; 2957 spin_lock_irq(&hdspm->lock); 2958 change = (int) val != hdspm_c_tms(hdspm); 2959 hdspm_set_c_tms(hdspm, val); 2960 spin_unlock_irq(&hdspm->lock); 2961 return change; 2962 } 2963 2964 2965 #define HDSPM_SAFE_MODE(xname, xindex) \ 2966 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2967 .name = xname, \ 2968 .index = xindex, \ 2969 .info = snd_hdspm_info_safe_mode, \ 2970 .get = snd_hdspm_get_safe_mode, \ 2971 .put = snd_hdspm_put_safe_mode \ 2972 } 2973 2974 static int hdspm_safe_mode(struct hdspm * hdspm) 2975 { 2976 return (hdspm->control_register & HDSPM_AutoInp) ? 1 : 0; 2977 } 2978 2979 static int hdspm_set_safe_mode(struct hdspm * hdspm, int out) 2980 { 2981 if (out) 2982 hdspm->control_register |= HDSPM_AutoInp; 2983 else 2984 hdspm->control_register &= ~HDSPM_AutoInp; 2985 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2986 2987 return 0; 2988 } 2989 2990 #define snd_hdspm_info_safe_mode snd_ctl_boolean_mono_info 2991 2992 static int snd_hdspm_get_safe_mode(struct snd_kcontrol *kcontrol, 2993 struct snd_ctl_elem_value *ucontrol) 2994 { 2995 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2996 2997 spin_lock_irq(&hdspm->lock); 2998 ucontrol->value.integer.value[0] = hdspm_safe_mode(hdspm); 2999 spin_unlock_irq(&hdspm->lock); 3000 return 0; 3001 } 3002 3003 static int snd_hdspm_put_safe_mode(struct snd_kcontrol *kcontrol, 3004 struct snd_ctl_elem_value *ucontrol) 3005 { 3006 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3007 int change; 3008 unsigned int val; 3009 3010 if (!snd_hdspm_use_is_exclusive(hdspm)) 3011 return -EBUSY; 3012 val = ucontrol->value.integer.value[0] & 1; 3013 spin_lock_irq(&hdspm->lock); 3014 change = (int) val != hdspm_safe_mode(hdspm); 3015 hdspm_set_safe_mode(hdspm, val); 3016 spin_unlock_irq(&hdspm->lock); 3017 return change; 3018 } 3019 3020 3021 #define HDSPM_EMPHASIS(xname, xindex) \ 3022 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3023 .name = xname, \ 3024 .index = xindex, \ 3025 .info = snd_hdspm_info_emphasis, \ 3026 .get = snd_hdspm_get_emphasis, \ 3027 .put = snd_hdspm_put_emphasis \ 3028 } 3029 3030 static int hdspm_emphasis(struct hdspm * hdspm) 3031 { 3032 return (hdspm->control_register & HDSPM_Emphasis) ? 1 : 0; 3033 } 3034 3035 static int hdspm_set_emphasis(struct hdspm * hdspm, int emp) 3036 { 3037 if (emp) 3038 hdspm->control_register |= HDSPM_Emphasis; 3039 else 3040 hdspm->control_register &= ~HDSPM_Emphasis; 3041 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3042 3043 return 0; 3044 } 3045 3046 #define snd_hdspm_info_emphasis snd_ctl_boolean_mono_info 3047 3048 static int snd_hdspm_get_emphasis(struct snd_kcontrol *kcontrol, 3049 struct snd_ctl_elem_value *ucontrol) 3050 { 3051 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3052 3053 spin_lock_irq(&hdspm->lock); 3054 ucontrol->value.enumerated.item[0] = hdspm_emphasis(hdspm); 3055 spin_unlock_irq(&hdspm->lock); 3056 return 0; 3057 } 3058 3059 static int snd_hdspm_put_emphasis(struct snd_kcontrol *kcontrol, 3060 struct snd_ctl_elem_value *ucontrol) 3061 { 3062 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3063 int change; 3064 unsigned int val; 3065 3066 if (!snd_hdspm_use_is_exclusive(hdspm)) 3067 return -EBUSY; 3068 val = ucontrol->value.integer.value[0] & 1; 3069 spin_lock_irq(&hdspm->lock); 3070 change = (int) val != hdspm_emphasis(hdspm); 3071 hdspm_set_emphasis(hdspm, val); 3072 spin_unlock_irq(&hdspm->lock); 3073 return change; 3074 } 3075 3076 3077 #define HDSPM_DOLBY(xname, xindex) \ 3078 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3079 .name = xname, \ 3080 .index = xindex, \ 3081 .info = snd_hdspm_info_dolby, \ 3082 .get = snd_hdspm_get_dolby, \ 3083 .put = snd_hdspm_put_dolby \ 3084 } 3085 3086 static int hdspm_dolby(struct hdspm * hdspm) 3087 { 3088 return (hdspm->control_register & HDSPM_Dolby) ? 1 : 0; 3089 } 3090 3091 static int hdspm_set_dolby(struct hdspm * hdspm, int dol) 3092 { 3093 if (dol) 3094 hdspm->control_register |= HDSPM_Dolby; 3095 else 3096 hdspm->control_register &= ~HDSPM_Dolby; 3097 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3098 3099 return 0; 3100 } 3101 3102 #define snd_hdspm_info_dolby snd_ctl_boolean_mono_info 3103 3104 static int snd_hdspm_get_dolby(struct snd_kcontrol *kcontrol, 3105 struct snd_ctl_elem_value *ucontrol) 3106 { 3107 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3108 3109 spin_lock_irq(&hdspm->lock); 3110 ucontrol->value.enumerated.item[0] = hdspm_dolby(hdspm); 3111 spin_unlock_irq(&hdspm->lock); 3112 return 0; 3113 } 3114 3115 static int snd_hdspm_put_dolby(struct snd_kcontrol *kcontrol, 3116 struct snd_ctl_elem_value *ucontrol) 3117 { 3118 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3119 int change; 3120 unsigned int val; 3121 3122 if (!snd_hdspm_use_is_exclusive(hdspm)) 3123 return -EBUSY; 3124 val = ucontrol->value.integer.value[0] & 1; 3125 spin_lock_irq(&hdspm->lock); 3126 change = (int) val != hdspm_dolby(hdspm); 3127 hdspm_set_dolby(hdspm, val); 3128 spin_unlock_irq(&hdspm->lock); 3129 return change; 3130 } 3131 3132 3133 #define HDSPM_PROFESSIONAL(xname, xindex) \ 3134 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3135 .name = xname, \ 3136 .index = xindex, \ 3137 .info = snd_hdspm_info_professional, \ 3138 .get = snd_hdspm_get_professional, \ 3139 .put = snd_hdspm_put_professional \ 3140 } 3141 3142 static int hdspm_professional(struct hdspm * hdspm) 3143 { 3144 return (hdspm->control_register & HDSPM_Professional) ? 1 : 0; 3145 } 3146 3147 static int hdspm_set_professional(struct hdspm * hdspm, int dol) 3148 { 3149 if (dol) 3150 hdspm->control_register |= HDSPM_Professional; 3151 else 3152 hdspm->control_register &= ~HDSPM_Professional; 3153 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3154 3155 return 0; 3156 } 3157 3158 #define snd_hdspm_info_professional snd_ctl_boolean_mono_info 3159 3160 static int snd_hdspm_get_professional(struct snd_kcontrol *kcontrol, 3161 struct snd_ctl_elem_value *ucontrol) 3162 { 3163 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3164 3165 spin_lock_irq(&hdspm->lock); 3166 ucontrol->value.enumerated.item[0] = hdspm_professional(hdspm); 3167 spin_unlock_irq(&hdspm->lock); 3168 return 0; 3169 } 3170 3171 static int snd_hdspm_put_professional(struct snd_kcontrol *kcontrol, 3172 struct snd_ctl_elem_value *ucontrol) 3173 { 3174 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3175 int change; 3176 unsigned int val; 3177 3178 if (!snd_hdspm_use_is_exclusive(hdspm)) 3179 return -EBUSY; 3180 val = ucontrol->value.integer.value[0] & 1; 3181 spin_lock_irq(&hdspm->lock); 3182 change = (int) val != hdspm_professional(hdspm); 3183 hdspm_set_professional(hdspm, val); 3184 spin_unlock_irq(&hdspm->lock); 3185 return change; 3186 } 3187 3188 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3189 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3190 .name = xname, \ 3191 .index = xindex, \ 3192 .info = snd_hdspm_info_input_select, \ 3193 .get = snd_hdspm_get_input_select, \ 3194 .put = snd_hdspm_put_input_select \ 3195 } 3196 3197 static int hdspm_input_select(struct hdspm * hdspm) 3198 { 3199 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3200 } 3201 3202 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3203 { 3204 if (out) 3205 hdspm->control_register |= HDSPM_InputSelect0; 3206 else 3207 hdspm->control_register &= ~HDSPM_InputSelect0; 3208 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3209 3210 return 0; 3211 } 3212 3213 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3214 struct snd_ctl_elem_info *uinfo) 3215 { 3216 static char *texts[] = { "optical", "coaxial" }; 3217 3218 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3219 uinfo->count = 1; 3220 uinfo->value.enumerated.items = 2; 3221 3222 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3223 uinfo->value.enumerated.item = 3224 uinfo->value.enumerated.items - 1; 3225 strcpy(uinfo->value.enumerated.name, 3226 texts[uinfo->value.enumerated.item]); 3227 3228 return 0; 3229 } 3230 3231 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3232 struct snd_ctl_elem_value *ucontrol) 3233 { 3234 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3235 3236 spin_lock_irq(&hdspm->lock); 3237 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3238 spin_unlock_irq(&hdspm->lock); 3239 return 0; 3240 } 3241 3242 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3243 struct snd_ctl_elem_value *ucontrol) 3244 { 3245 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3246 int change; 3247 unsigned int val; 3248 3249 if (!snd_hdspm_use_is_exclusive(hdspm)) 3250 return -EBUSY; 3251 val = ucontrol->value.integer.value[0] & 1; 3252 spin_lock_irq(&hdspm->lock); 3253 change = (int) val != hdspm_input_select(hdspm); 3254 hdspm_set_input_select(hdspm, val); 3255 spin_unlock_irq(&hdspm->lock); 3256 return change; 3257 } 3258 3259 3260 #define HDSPM_DS_WIRE(xname, xindex) \ 3261 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3262 .name = xname, \ 3263 .index = xindex, \ 3264 .info = snd_hdspm_info_ds_wire, \ 3265 .get = snd_hdspm_get_ds_wire, \ 3266 .put = snd_hdspm_put_ds_wire \ 3267 } 3268 3269 static int hdspm_ds_wire(struct hdspm * hdspm) 3270 { 3271 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3272 } 3273 3274 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3275 { 3276 if (ds) 3277 hdspm->control_register |= HDSPM_DS_DoubleWire; 3278 else 3279 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3280 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3281 3282 return 0; 3283 } 3284 3285 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3286 struct snd_ctl_elem_info *uinfo) 3287 { 3288 static char *texts[] = { "Single", "Double" }; 3289 3290 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3291 uinfo->count = 1; 3292 uinfo->value.enumerated.items = 2; 3293 3294 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3295 uinfo->value.enumerated.item = 3296 uinfo->value.enumerated.items - 1; 3297 strcpy(uinfo->value.enumerated.name, 3298 texts[uinfo->value.enumerated.item]); 3299 3300 return 0; 3301 } 3302 3303 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3304 struct snd_ctl_elem_value *ucontrol) 3305 { 3306 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3307 3308 spin_lock_irq(&hdspm->lock); 3309 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3310 spin_unlock_irq(&hdspm->lock); 3311 return 0; 3312 } 3313 3314 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3315 struct snd_ctl_elem_value *ucontrol) 3316 { 3317 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3318 int change; 3319 unsigned int val; 3320 3321 if (!snd_hdspm_use_is_exclusive(hdspm)) 3322 return -EBUSY; 3323 val = ucontrol->value.integer.value[0] & 1; 3324 spin_lock_irq(&hdspm->lock); 3325 change = (int) val != hdspm_ds_wire(hdspm); 3326 hdspm_set_ds_wire(hdspm, val); 3327 spin_unlock_irq(&hdspm->lock); 3328 return change; 3329 } 3330 3331 3332 #define HDSPM_QS_WIRE(xname, xindex) \ 3333 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3334 .name = xname, \ 3335 .index = xindex, \ 3336 .info = snd_hdspm_info_qs_wire, \ 3337 .get = snd_hdspm_get_qs_wire, \ 3338 .put = snd_hdspm_put_qs_wire \ 3339 } 3340 3341 static int hdspm_qs_wire(struct hdspm * hdspm) 3342 { 3343 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3344 return 1; 3345 if (hdspm->control_register & HDSPM_QS_QuadWire) 3346 return 2; 3347 return 0; 3348 } 3349 3350 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3351 { 3352 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3353 switch (mode) { 3354 case 0: 3355 break; 3356 case 1: 3357 hdspm->control_register |= HDSPM_QS_DoubleWire; 3358 break; 3359 case 2: 3360 hdspm->control_register |= HDSPM_QS_QuadWire; 3361 break; 3362 } 3363 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3364 3365 return 0; 3366 } 3367 3368 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3369 struct snd_ctl_elem_info *uinfo) 3370 { 3371 static char *texts[] = { "Single", "Double", "Quad" }; 3372 3373 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3374 uinfo->count = 1; 3375 uinfo->value.enumerated.items = 3; 3376 3377 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3378 uinfo->value.enumerated.item = 3379 uinfo->value.enumerated.items - 1; 3380 strcpy(uinfo->value.enumerated.name, 3381 texts[uinfo->value.enumerated.item]); 3382 3383 return 0; 3384 } 3385 3386 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3387 struct snd_ctl_elem_value *ucontrol) 3388 { 3389 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3390 3391 spin_lock_irq(&hdspm->lock); 3392 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3393 spin_unlock_irq(&hdspm->lock); 3394 return 0; 3395 } 3396 3397 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3398 struct snd_ctl_elem_value *ucontrol) 3399 { 3400 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3401 int change; 3402 int val; 3403 3404 if (!snd_hdspm_use_is_exclusive(hdspm)) 3405 return -EBUSY; 3406 val = ucontrol->value.integer.value[0]; 3407 if (val < 0) 3408 val = 0; 3409 if (val > 2) 3410 val = 2; 3411 spin_lock_irq(&hdspm->lock); 3412 change = val != hdspm_qs_wire(hdspm); 3413 hdspm_set_qs_wire(hdspm, val); 3414 spin_unlock_irq(&hdspm->lock); 3415 return change; 3416 } 3417 3418 3419 #define HDSPM_MIXER(xname, xindex) \ 3420 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3421 .name = xname, \ 3422 .index = xindex, \ 3423 .device = 0, \ 3424 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3425 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3426 .info = snd_hdspm_info_mixer, \ 3427 .get = snd_hdspm_get_mixer, \ 3428 .put = snd_hdspm_put_mixer \ 3429 } 3430 3431 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3432 struct snd_ctl_elem_info *uinfo) 3433 { 3434 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3435 uinfo->count = 3; 3436 uinfo->value.integer.min = 0; 3437 uinfo->value.integer.max = 65535; 3438 uinfo->value.integer.step = 1; 3439 return 0; 3440 } 3441 3442 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3443 struct snd_ctl_elem_value *ucontrol) 3444 { 3445 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3446 int source; 3447 int destination; 3448 3449 source = ucontrol->value.integer.value[0]; 3450 if (source < 0) 3451 source = 0; 3452 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3453 source = 2 * HDSPM_MAX_CHANNELS - 1; 3454 3455 destination = ucontrol->value.integer.value[1]; 3456 if (destination < 0) 3457 destination = 0; 3458 else if (destination >= HDSPM_MAX_CHANNELS) 3459 destination = HDSPM_MAX_CHANNELS - 1; 3460 3461 spin_lock_irq(&hdspm->lock); 3462 if (source >= HDSPM_MAX_CHANNELS) 3463 ucontrol->value.integer.value[2] = 3464 hdspm_read_pb_gain(hdspm, destination, 3465 source - HDSPM_MAX_CHANNELS); 3466 else 3467 ucontrol->value.integer.value[2] = 3468 hdspm_read_in_gain(hdspm, destination, source); 3469 3470 spin_unlock_irq(&hdspm->lock); 3471 3472 return 0; 3473 } 3474 3475 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3476 struct snd_ctl_elem_value *ucontrol) 3477 { 3478 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3479 int change; 3480 int source; 3481 int destination; 3482 int gain; 3483 3484 if (!snd_hdspm_use_is_exclusive(hdspm)) 3485 return -EBUSY; 3486 3487 source = ucontrol->value.integer.value[0]; 3488 destination = ucontrol->value.integer.value[1]; 3489 3490 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3491 return -1; 3492 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3493 return -1; 3494 3495 gain = ucontrol->value.integer.value[2]; 3496 3497 spin_lock_irq(&hdspm->lock); 3498 3499 if (source >= HDSPM_MAX_CHANNELS) 3500 change = gain != hdspm_read_pb_gain(hdspm, destination, 3501 source - 3502 HDSPM_MAX_CHANNELS); 3503 else 3504 change = gain != hdspm_read_in_gain(hdspm, destination, 3505 source); 3506 3507 if (change) { 3508 if (source >= HDSPM_MAX_CHANNELS) 3509 hdspm_write_pb_gain(hdspm, destination, 3510 source - HDSPM_MAX_CHANNELS, 3511 gain); 3512 else 3513 hdspm_write_in_gain(hdspm, destination, source, 3514 gain); 3515 } 3516 spin_unlock_irq(&hdspm->lock); 3517 3518 return change; 3519 } 3520 3521 /* The simple mixer control(s) provide gain control for the 3522 basic 1:1 mappings of playback streams to output 3523 streams. 3524 */ 3525 3526 #define HDSPM_PLAYBACK_MIXER \ 3527 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3528 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3529 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3530 .info = snd_hdspm_info_playback_mixer, \ 3531 .get = snd_hdspm_get_playback_mixer, \ 3532 .put = snd_hdspm_put_playback_mixer \ 3533 } 3534 3535 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3536 struct snd_ctl_elem_info *uinfo) 3537 { 3538 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3539 uinfo->count = 1; 3540 uinfo->value.integer.min = 0; 3541 uinfo->value.integer.max = 64; 3542 uinfo->value.integer.step = 1; 3543 return 0; 3544 } 3545 3546 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3547 struct snd_ctl_elem_value *ucontrol) 3548 { 3549 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3550 int channel; 3551 3552 channel = ucontrol->id.index - 1; 3553 3554 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3555 return -EINVAL; 3556 3557 spin_lock_irq(&hdspm->lock); 3558 ucontrol->value.integer.value[0] = 3559 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3560 spin_unlock_irq(&hdspm->lock); 3561 3562 return 0; 3563 } 3564 3565 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3566 struct snd_ctl_elem_value *ucontrol) 3567 { 3568 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3569 int change; 3570 int channel; 3571 int gain; 3572 3573 if (!snd_hdspm_use_is_exclusive(hdspm)) 3574 return -EBUSY; 3575 3576 channel = ucontrol->id.index - 1; 3577 3578 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3579 return -EINVAL; 3580 3581 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3582 3583 spin_lock_irq(&hdspm->lock); 3584 change = 3585 gain != hdspm_read_pb_gain(hdspm, channel, 3586 channel); 3587 if (change) 3588 hdspm_write_pb_gain(hdspm, channel, channel, 3589 gain); 3590 spin_unlock_irq(&hdspm->lock); 3591 return change; 3592 } 3593 3594 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3595 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3596 .name = xname, \ 3597 .private_value = xindex, \ 3598 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3599 .info = snd_hdspm_info_sync_check, \ 3600 .get = snd_hdspm_get_sync_check \ 3601 } 3602 3603 3604 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3605 struct snd_ctl_elem_info *uinfo) 3606 { 3607 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3608 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3609 uinfo->count = 1; 3610 uinfo->value.enumerated.items = 4; 3611 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3612 uinfo->value.enumerated.item = 3613 uinfo->value.enumerated.items - 1; 3614 strcpy(uinfo->value.enumerated.name, 3615 texts[uinfo->value.enumerated.item]); 3616 return 0; 3617 } 3618 3619 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3620 { 3621 int status, status2; 3622 3623 switch (hdspm->io_type) { 3624 case AES32: 3625 status = hdspm_read(hdspm, HDSPM_statusRegister); 3626 if (status & HDSPM_wcSync) 3627 return 2; 3628 else if (status & HDSPM_wcLock) 3629 return 1; 3630 return 0; 3631 break; 3632 3633 case MADI: 3634 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3635 if (status2 & HDSPM_wcLock) { 3636 if (status2 & HDSPM_wcSync) 3637 return 2; 3638 else 3639 return 1; 3640 } 3641 return 0; 3642 break; 3643 3644 case RayDAT: 3645 case AIO: 3646 status = hdspm_read(hdspm, HDSPM_statusRegister); 3647 3648 if (status & 0x2000000) 3649 return 2; 3650 else if (status & 0x1000000) 3651 return 1; 3652 return 0; 3653 3654 break; 3655 3656 case MADIface: 3657 break; 3658 } 3659 3660 3661 return 3; 3662 } 3663 3664 3665 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3666 { 3667 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3668 if (status & HDSPM_madiLock) { 3669 if (status & HDSPM_madiSync) 3670 return 2; 3671 else 3672 return 1; 3673 } 3674 return 0; 3675 } 3676 3677 3678 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3679 { 3680 int status, lock, sync; 3681 3682 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3683 3684 lock = (status & (0x1<<idx)) ? 1 : 0; 3685 sync = (status & (0x100<<idx)) ? 1 : 0; 3686 3687 if (lock && sync) 3688 return 2; 3689 else if (lock) 3690 return 1; 3691 return 0; 3692 } 3693 3694 3695 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3696 { 3697 int status, lock = 0, sync = 0; 3698 3699 switch (hdspm->io_type) { 3700 case RayDAT: 3701 case AIO: 3702 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3703 lock = (status & 0x400) ? 1 : 0; 3704 sync = (status & 0x800) ? 1 : 0; 3705 break; 3706 3707 case MADI: 3708 case AES32: 3709 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3710 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3711 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3712 break; 3713 3714 case MADIface: 3715 break; 3716 } 3717 3718 if (lock && sync) 3719 return 2; 3720 else if (lock) 3721 return 1; 3722 3723 return 0; 3724 } 3725 3726 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3727 { 3728 int status2, lock, sync; 3729 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3730 3731 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3732 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3733 3734 if (sync) 3735 return 2; 3736 else if (lock) 3737 return 1; 3738 return 0; 3739 } 3740 3741 3742 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3743 { 3744 int status; 3745 3746 if (hdspm->tco) { 3747 switch (hdspm->io_type) { 3748 case MADI: 3749 case AES32: 3750 status = hdspm_read(hdspm, HDSPM_statusRegister); 3751 if (status & HDSPM_tcoLock) { 3752 if (status & HDSPM_tcoSync) 3753 return 2; 3754 else 3755 return 1; 3756 } 3757 return 0; 3758 3759 break; 3760 3761 case RayDAT: 3762 case AIO: 3763 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3764 3765 if (status & 0x8000000) 3766 return 2; /* Sync */ 3767 if (status & 0x4000000) 3768 return 1; /* Lock */ 3769 return 0; /* No signal */ 3770 break; 3771 3772 default: 3773 break; 3774 } 3775 } 3776 3777 return 3; /* N/A */ 3778 } 3779 3780 3781 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3782 struct snd_ctl_elem_value *ucontrol) 3783 { 3784 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3785 int val = -1; 3786 3787 switch (hdspm->io_type) { 3788 case RayDAT: 3789 switch (kcontrol->private_value) { 3790 case 0: /* WC */ 3791 val = hdspm_wc_sync_check(hdspm); break; 3792 case 7: /* TCO */ 3793 val = hdspm_tco_sync_check(hdspm); break; 3794 case 8: /* SYNC IN */ 3795 val = hdspm_sync_in_sync_check(hdspm); break; 3796 default: 3797 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3798 } 3799 3800 case AIO: 3801 switch (kcontrol->private_value) { 3802 case 0: /* WC */ 3803 val = hdspm_wc_sync_check(hdspm); break; 3804 case 4: /* TCO */ 3805 val = hdspm_tco_sync_check(hdspm); break; 3806 case 5: /* SYNC IN */ 3807 val = hdspm_sync_in_sync_check(hdspm); break; 3808 default: 3809 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3810 } 3811 3812 case MADI: 3813 switch (kcontrol->private_value) { 3814 case 0: /* WC */ 3815 val = hdspm_wc_sync_check(hdspm); break; 3816 case 1: /* MADI */ 3817 val = hdspm_madi_sync_check(hdspm); break; 3818 case 2: /* TCO */ 3819 val = hdspm_tco_sync_check(hdspm); break; 3820 case 3: /* SYNC_IN */ 3821 val = hdspm_sync_in_sync_check(hdspm); break; 3822 } 3823 3824 case MADIface: 3825 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3826 break; 3827 3828 case AES32: 3829 switch (kcontrol->private_value) { 3830 case 0: /* WC */ 3831 val = hdspm_wc_sync_check(hdspm); break; 3832 case 9: /* TCO */ 3833 val = hdspm_tco_sync_check(hdspm); break; 3834 case 10 /* SYNC IN */: 3835 val = hdspm_sync_in_sync_check(hdspm); break; 3836 default: /* AES1 to AES8 */ 3837 val = hdspm_aes_sync_check(hdspm, 3838 kcontrol->private_value-1); 3839 } 3840 3841 } 3842 3843 if (-1 == val) 3844 val = 3; 3845 3846 ucontrol->value.enumerated.item[0] = val; 3847 return 0; 3848 } 3849 3850 3851 3852 /** 3853 * TCO controls 3854 **/ 3855 static void hdspm_tco_write(struct hdspm *hdspm) 3856 { 3857 unsigned int tc[4] = { 0, 0, 0, 0}; 3858 3859 switch (hdspm->tco->input) { 3860 case 0: 3861 tc[2] |= HDSPM_TCO2_set_input_MSB; 3862 break; 3863 case 1: 3864 tc[2] |= HDSPM_TCO2_set_input_LSB; 3865 break; 3866 default: 3867 break; 3868 } 3869 3870 switch (hdspm->tco->framerate) { 3871 case 1: 3872 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 3873 break; 3874 case 2: 3875 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 3876 break; 3877 case 3: 3878 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 3879 HDSPM_TCO1_set_drop_frame_flag; 3880 break; 3881 case 4: 3882 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3883 HDSPM_TCO1_LTC_Format_MSB; 3884 break; 3885 case 5: 3886 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3887 HDSPM_TCO1_LTC_Format_MSB + 3888 HDSPM_TCO1_set_drop_frame_flag; 3889 break; 3890 default: 3891 break; 3892 } 3893 3894 switch (hdspm->tco->wordclock) { 3895 case 1: 3896 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 3897 break; 3898 case 2: 3899 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 3900 break; 3901 default: 3902 break; 3903 } 3904 3905 switch (hdspm->tco->samplerate) { 3906 case 1: 3907 tc[2] |= HDSPM_TCO2_set_freq; 3908 break; 3909 case 2: 3910 tc[2] |= HDSPM_TCO2_set_freq_from_app; 3911 break; 3912 default: 3913 break; 3914 } 3915 3916 switch (hdspm->tco->pull) { 3917 case 1: 3918 tc[2] |= HDSPM_TCO2_set_pull_up; 3919 break; 3920 case 2: 3921 tc[2] |= HDSPM_TCO2_set_pull_down; 3922 break; 3923 case 3: 3924 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 3925 break; 3926 case 4: 3927 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 3928 break; 3929 default: 3930 break; 3931 } 3932 3933 if (1 == hdspm->tco->term) { 3934 tc[2] |= HDSPM_TCO2_set_term_75R; 3935 } 3936 3937 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 3938 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 3939 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 3940 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 3941 } 3942 3943 3944 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 3945 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3946 .name = xname, \ 3947 .index = xindex, \ 3948 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3949 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3950 .info = snd_hdspm_info_tco_sample_rate, \ 3951 .get = snd_hdspm_get_tco_sample_rate, \ 3952 .put = snd_hdspm_put_tco_sample_rate \ 3953 } 3954 3955 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 3956 struct snd_ctl_elem_info *uinfo) 3957 { 3958 static char *texts[] = { "44.1 kHz", "48 kHz" }; 3959 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3960 uinfo->count = 1; 3961 uinfo->value.enumerated.items = 2; 3962 3963 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3964 uinfo->value.enumerated.item = 3965 uinfo->value.enumerated.items - 1; 3966 3967 strcpy(uinfo->value.enumerated.name, 3968 texts[uinfo->value.enumerated.item]); 3969 3970 return 0; 3971 } 3972 3973 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 3974 struct snd_ctl_elem_value *ucontrol) 3975 { 3976 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3977 3978 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 3979 3980 return 0; 3981 } 3982 3983 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 3984 struct snd_ctl_elem_value *ucontrol) 3985 { 3986 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3987 3988 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 3989 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 3990 3991 hdspm_tco_write(hdspm); 3992 3993 return 1; 3994 } 3995 3996 return 0; 3997 } 3998 3999 4000 #define HDSPM_TCO_PULL(xname, xindex) \ 4001 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4002 .name = xname, \ 4003 .index = xindex, \ 4004 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4005 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4006 .info = snd_hdspm_info_tco_pull, \ 4007 .get = snd_hdspm_get_tco_pull, \ 4008 .put = snd_hdspm_put_tco_pull \ 4009 } 4010 4011 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4012 struct snd_ctl_elem_info *uinfo) 4013 { 4014 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 4015 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4016 uinfo->count = 1; 4017 uinfo->value.enumerated.items = 5; 4018 4019 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4020 uinfo->value.enumerated.item = 4021 uinfo->value.enumerated.items - 1; 4022 4023 strcpy(uinfo->value.enumerated.name, 4024 texts[uinfo->value.enumerated.item]); 4025 4026 return 0; 4027 } 4028 4029 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4030 struct snd_ctl_elem_value *ucontrol) 4031 { 4032 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4033 4034 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4035 4036 return 0; 4037 } 4038 4039 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4040 struct snd_ctl_elem_value *ucontrol) 4041 { 4042 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4043 4044 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4045 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4046 4047 hdspm_tco_write(hdspm); 4048 4049 return 1; 4050 } 4051 4052 return 0; 4053 } 4054 4055 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4056 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4057 .name = xname, \ 4058 .index = xindex, \ 4059 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4060 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4061 .info = snd_hdspm_info_tco_wck_conversion, \ 4062 .get = snd_hdspm_get_tco_wck_conversion, \ 4063 .put = snd_hdspm_put_tco_wck_conversion \ 4064 } 4065 4066 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4067 struct snd_ctl_elem_info *uinfo) 4068 { 4069 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4070 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4071 uinfo->count = 1; 4072 uinfo->value.enumerated.items = 3; 4073 4074 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4075 uinfo->value.enumerated.item = 4076 uinfo->value.enumerated.items - 1; 4077 4078 strcpy(uinfo->value.enumerated.name, 4079 texts[uinfo->value.enumerated.item]); 4080 4081 return 0; 4082 } 4083 4084 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4085 struct snd_ctl_elem_value *ucontrol) 4086 { 4087 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4088 4089 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4090 4091 return 0; 4092 } 4093 4094 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4095 struct snd_ctl_elem_value *ucontrol) 4096 { 4097 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4098 4099 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4100 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4101 4102 hdspm_tco_write(hdspm); 4103 4104 return 1; 4105 } 4106 4107 return 0; 4108 } 4109 4110 4111 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4112 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4113 .name = xname, \ 4114 .index = xindex, \ 4115 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4116 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4117 .info = snd_hdspm_info_tco_frame_rate, \ 4118 .get = snd_hdspm_get_tco_frame_rate, \ 4119 .put = snd_hdspm_put_tco_frame_rate \ 4120 } 4121 4122 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4123 struct snd_ctl_elem_info *uinfo) 4124 { 4125 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 4126 "29.97 dfps", "30 fps", "30 dfps" }; 4127 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4128 uinfo->count = 1; 4129 uinfo->value.enumerated.items = 6; 4130 4131 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4132 uinfo->value.enumerated.item = 4133 uinfo->value.enumerated.items - 1; 4134 4135 strcpy(uinfo->value.enumerated.name, 4136 texts[uinfo->value.enumerated.item]); 4137 4138 return 0; 4139 } 4140 4141 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4142 struct snd_ctl_elem_value *ucontrol) 4143 { 4144 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4145 4146 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4147 4148 return 0; 4149 } 4150 4151 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4152 struct snd_ctl_elem_value *ucontrol) 4153 { 4154 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4155 4156 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4157 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4158 4159 hdspm_tco_write(hdspm); 4160 4161 return 1; 4162 } 4163 4164 return 0; 4165 } 4166 4167 4168 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4169 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4170 .name = xname, \ 4171 .index = xindex, \ 4172 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4173 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4174 .info = snd_hdspm_info_tco_sync_source, \ 4175 .get = snd_hdspm_get_tco_sync_source, \ 4176 .put = snd_hdspm_put_tco_sync_source \ 4177 } 4178 4179 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4180 struct snd_ctl_elem_info *uinfo) 4181 { 4182 static char *texts[] = { "LTC", "Video", "WCK" }; 4183 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4184 uinfo->count = 1; 4185 uinfo->value.enumerated.items = 3; 4186 4187 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4188 uinfo->value.enumerated.item = 4189 uinfo->value.enumerated.items - 1; 4190 4191 strcpy(uinfo->value.enumerated.name, 4192 texts[uinfo->value.enumerated.item]); 4193 4194 return 0; 4195 } 4196 4197 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4198 struct snd_ctl_elem_value *ucontrol) 4199 { 4200 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4201 4202 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4203 4204 return 0; 4205 } 4206 4207 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4208 struct snd_ctl_elem_value *ucontrol) 4209 { 4210 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4211 4212 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4213 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4214 4215 hdspm_tco_write(hdspm); 4216 4217 return 1; 4218 } 4219 4220 return 0; 4221 } 4222 4223 4224 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4225 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4226 .name = xname, \ 4227 .index = xindex, \ 4228 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4229 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4230 .info = snd_hdspm_info_tco_word_term, \ 4231 .get = snd_hdspm_get_tco_word_term, \ 4232 .put = snd_hdspm_put_tco_word_term \ 4233 } 4234 4235 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4236 struct snd_ctl_elem_info *uinfo) 4237 { 4238 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4239 uinfo->count = 1; 4240 uinfo->value.integer.min = 0; 4241 uinfo->value.integer.max = 1; 4242 4243 return 0; 4244 } 4245 4246 4247 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4248 struct snd_ctl_elem_value *ucontrol) 4249 { 4250 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4251 4252 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4253 4254 return 0; 4255 } 4256 4257 4258 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4259 struct snd_ctl_elem_value *ucontrol) 4260 { 4261 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4262 4263 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4264 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4265 4266 hdspm_tco_write(hdspm); 4267 4268 return 1; 4269 } 4270 4271 return 0; 4272 } 4273 4274 4275 4276 4277 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4278 HDSPM_MIXER("Mixer", 0), 4279 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4280 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4281 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4282 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4283 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4284 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4285 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4286 HDSPM_SYNC_CHECK("TCO SyncCHeck", 2), 4287 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4288 HDSPM_LINE_OUT("Line Out", 0), 4289 HDSPM_TX_64("TX 64 channels mode", 0), 4290 HDSPM_C_TMS("Clear Track Marker", 0), 4291 HDSPM_SAFE_MODE("Safe Mode", 0), 4292 HDSPM_INPUT_SELECT("Input Select", 0) 4293 }; 4294 4295 4296 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4297 HDSPM_MIXER("Mixer", 0), 4298 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4299 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4300 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4301 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4302 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4303 HDSPM_TX_64("TX 64 channels mode", 0), 4304 HDSPM_C_TMS("Clear Track Marker", 0), 4305 HDSPM_SAFE_MODE("Safe Mode", 0) 4306 }; 4307 4308 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4309 HDSPM_MIXER("Mixer", 0), 4310 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4311 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4312 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4313 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4314 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4315 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4316 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4317 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4318 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4319 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4320 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4321 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4322 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4323 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4324 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4325 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4326 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4327 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4328 4329 /* 4330 HDSPM_INPUT_SELECT("Input Select", 0), 4331 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4332 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4333 HDSPM_SPDIF_IN("SPDIF In", 0); 4334 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4335 HDSPM_INPUT_LEVEL("Input Level", 0); 4336 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4337 HDSPM_PHONES("Phones", 0); 4338 */ 4339 }; 4340 4341 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4342 HDSPM_MIXER("Mixer", 0), 4343 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4344 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4345 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4346 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4347 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4348 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4349 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4350 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4351 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4352 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4353 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4354 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4355 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4356 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4357 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4358 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4359 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4360 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4361 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4362 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4363 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4364 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4365 }; 4366 4367 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4368 HDSPM_MIXER("Mixer", 0), 4369 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4370 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4371 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4372 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4373 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4374 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4375 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4376 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4377 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4378 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4379 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4380 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4381 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4382 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4383 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4384 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4385 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4386 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4387 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4388 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4389 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4390 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4391 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4392 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4393 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4394 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4395 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4396 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4397 HDSPM_LINE_OUT("Line Out", 0), 4398 HDSPM_EMPHASIS("Emphasis", 0), 4399 HDSPM_DOLBY("Non Audio", 0), 4400 HDSPM_PROFESSIONAL("Professional", 0), 4401 HDSPM_C_TMS("Clear Track Marker", 0), 4402 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4403 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4404 }; 4405 4406 4407 4408 /* Control elements for the optional TCO module */ 4409 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4410 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4411 HDSPM_TCO_PULL("TCO Pull", 0), 4412 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4413 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4414 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4415 HDSPM_TCO_WORD_TERM("TCO Word Term", 0) 4416 }; 4417 4418 4419 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4420 4421 4422 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4423 { 4424 int i; 4425 4426 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4427 if (hdspm->system_sample_rate > 48000) { 4428 hdspm->playback_mixer_ctls[i]->vd[0].access = 4429 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4430 SNDRV_CTL_ELEM_ACCESS_READ | 4431 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4432 } else { 4433 hdspm->playback_mixer_ctls[i]->vd[0].access = 4434 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4435 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4436 } 4437 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4438 SNDRV_CTL_EVENT_MASK_INFO, 4439 &hdspm->playback_mixer_ctls[i]->id); 4440 } 4441 4442 return 0; 4443 } 4444 4445 4446 static int snd_hdspm_create_controls(struct snd_card *card, 4447 struct hdspm *hdspm) 4448 { 4449 unsigned int idx, limit; 4450 int err; 4451 struct snd_kcontrol *kctl; 4452 struct snd_kcontrol_new *list = NULL; 4453 4454 switch (hdspm->io_type) { 4455 case MADI: 4456 list = snd_hdspm_controls_madi; 4457 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4458 break; 4459 case MADIface: 4460 list = snd_hdspm_controls_madiface; 4461 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4462 break; 4463 case AIO: 4464 list = snd_hdspm_controls_aio; 4465 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4466 break; 4467 case RayDAT: 4468 list = snd_hdspm_controls_raydat; 4469 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4470 break; 4471 case AES32: 4472 list = snd_hdspm_controls_aes32; 4473 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4474 break; 4475 } 4476 4477 if (NULL != list) { 4478 for (idx = 0; idx < limit; idx++) { 4479 err = snd_ctl_add(card, 4480 snd_ctl_new1(&list[idx], hdspm)); 4481 if (err < 0) 4482 return err; 4483 } 4484 } 4485 4486 4487 /* create simple 1:1 playback mixer controls */ 4488 snd_hdspm_playback_mixer.name = "Chn"; 4489 if (hdspm->system_sample_rate >= 128000) { 4490 limit = hdspm->qs_out_channels; 4491 } else if (hdspm->system_sample_rate >= 64000) { 4492 limit = hdspm->ds_out_channels; 4493 } else { 4494 limit = hdspm->ss_out_channels; 4495 } 4496 for (idx = 0; idx < limit; ++idx) { 4497 snd_hdspm_playback_mixer.index = idx + 1; 4498 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4499 err = snd_ctl_add(card, kctl); 4500 if (err < 0) 4501 return err; 4502 hdspm->playback_mixer_ctls[idx] = kctl; 4503 } 4504 4505 4506 if (hdspm->tco) { 4507 /* add tco control elements */ 4508 list = snd_hdspm_controls_tco; 4509 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4510 for (idx = 0; idx < limit; idx++) { 4511 err = snd_ctl_add(card, 4512 snd_ctl_new1(&list[idx], hdspm)); 4513 if (err < 0) 4514 return err; 4515 } 4516 } 4517 4518 return 0; 4519 } 4520 4521 /*------------------------------------------------------------ 4522 /proc interface 4523 ------------------------------------------------------------*/ 4524 4525 static void 4526 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4527 struct snd_info_buffer *buffer) 4528 { 4529 struct hdspm *hdspm = entry->private_data; 4530 unsigned int status, status2, control, freq; 4531 4532 char *pref_sync_ref; 4533 char *autosync_ref; 4534 char *system_clock_mode; 4535 char *insel; 4536 int x, x2; 4537 4538 /* TCO stuff */ 4539 int a, ltc, frames, seconds, minutes, hours; 4540 unsigned int period; 4541 u64 freq_const = 0; 4542 u32 rate; 4543 4544 status = hdspm_read(hdspm, HDSPM_statusRegister); 4545 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4546 control = hdspm->control_register; 4547 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4548 4549 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4550 hdspm->card_name, hdspm->card->number + 1, 4551 hdspm->firmware_rev, 4552 (status2 & HDSPM_version0) | 4553 (status2 & HDSPM_version1) | (status2 & 4554 HDSPM_version2)); 4555 4556 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4557 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4558 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 4559 4560 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4561 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4562 4563 snd_iprintf(buffer, "--- System ---\n"); 4564 4565 snd_iprintf(buffer, 4566 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4567 status & HDSPM_audioIRQPending, 4568 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4569 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4570 hdspm->irq_count); 4571 snd_iprintf(buffer, 4572 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4573 "estimated= %ld (bytes)\n", 4574 ((status & HDSPM_BufferID) ? 1 : 0), 4575 (status & HDSPM_BufferPositionMask), 4576 (status & HDSPM_BufferPositionMask) % 4577 (2 * (int)hdspm->period_bytes), 4578 ((status & HDSPM_BufferPositionMask) - 64) % 4579 (2 * (int)hdspm->period_bytes), 4580 (long) hdspm_hw_pointer(hdspm) * 4); 4581 4582 snd_iprintf(buffer, 4583 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4584 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4585 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4586 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4587 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4588 snd_iprintf(buffer, 4589 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4590 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4591 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4592 snd_iprintf(buffer, 4593 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4594 "status2=0x%x\n", 4595 hdspm->control_register, hdspm->control2_register, 4596 status, status2); 4597 if (status & HDSPM_tco_detect) { 4598 snd_iprintf(buffer, "TCO module detected.\n"); 4599 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4600 if (a & HDSPM_TCO1_LTC_Input_valid) { 4601 snd_iprintf(buffer, " LTC valid, "); 4602 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4603 HDSPM_TCO1_LTC_Format_MSB)) { 4604 case 0: 4605 snd_iprintf(buffer, "24 fps, "); 4606 break; 4607 case HDSPM_TCO1_LTC_Format_LSB: 4608 snd_iprintf(buffer, "25 fps, "); 4609 break; 4610 case HDSPM_TCO1_LTC_Format_MSB: 4611 snd_iprintf(buffer, "29.97 fps, "); 4612 break; 4613 default: 4614 snd_iprintf(buffer, "30 fps, "); 4615 break; 4616 } 4617 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4618 snd_iprintf(buffer, "drop frame\n"); 4619 } else { 4620 snd_iprintf(buffer, "full frame\n"); 4621 } 4622 } else { 4623 snd_iprintf(buffer, " no LTC\n"); 4624 } 4625 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4626 snd_iprintf(buffer, " Video: NTSC\n"); 4627 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4628 snd_iprintf(buffer, " Video: PAL\n"); 4629 } else { 4630 snd_iprintf(buffer, " No video\n"); 4631 } 4632 if (a & HDSPM_TCO1_TCO_lock) { 4633 snd_iprintf(buffer, " Sync: lock\n"); 4634 } else { 4635 snd_iprintf(buffer, " Sync: no lock\n"); 4636 } 4637 4638 switch (hdspm->io_type) { 4639 case MADI: 4640 case AES32: 4641 freq_const = 110069313433624ULL; 4642 break; 4643 case RayDAT: 4644 case AIO: 4645 freq_const = 104857600000000ULL; 4646 break; 4647 case MADIface: 4648 break; /* no TCO possible */ 4649 } 4650 4651 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4652 snd_iprintf(buffer, " period: %u\n", period); 4653 4654 4655 /* rate = freq_const/period; */ 4656 rate = div_u64(freq_const, period); 4657 4658 if (control & HDSPM_QuadSpeed) { 4659 rate *= 4; 4660 } else if (control & HDSPM_DoubleSpeed) { 4661 rate *= 2; 4662 } 4663 4664 snd_iprintf(buffer, " Frequency: %u Hz\n", 4665 (unsigned int) rate); 4666 4667 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4668 frames = ltc & 0xF; 4669 ltc >>= 4; 4670 frames += (ltc & 0x3) * 10; 4671 ltc >>= 4; 4672 seconds = ltc & 0xF; 4673 ltc >>= 4; 4674 seconds += (ltc & 0x7) * 10; 4675 ltc >>= 4; 4676 minutes = ltc & 0xF; 4677 ltc >>= 4; 4678 minutes += (ltc & 0x7) * 10; 4679 ltc >>= 4; 4680 hours = ltc & 0xF; 4681 ltc >>= 4; 4682 hours += (ltc & 0x3) * 10; 4683 snd_iprintf(buffer, 4684 " LTC In: %02d:%02d:%02d:%02d\n", 4685 hours, minutes, seconds, frames); 4686 4687 } else { 4688 snd_iprintf(buffer, "No TCO module detected.\n"); 4689 } 4690 4691 snd_iprintf(buffer, "--- Settings ---\n"); 4692 4693 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & 4694 HDSPM_LatencyMask)); 4695 4696 snd_iprintf(buffer, 4697 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4698 x, (unsigned long) hdspm->period_bytes); 4699 4700 snd_iprintf(buffer, "Line out: %s\n", 4701 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4702 4703 switch (hdspm->control_register & HDSPM_InputMask) { 4704 case HDSPM_InputOptical: 4705 insel = "Optical"; 4706 break; 4707 case HDSPM_InputCoaxial: 4708 insel = "Coaxial"; 4709 break; 4710 default: 4711 insel = "Unkown"; 4712 } 4713 4714 snd_iprintf(buffer, 4715 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4716 "Auto Input %s\n", 4717 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4718 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4719 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4720 4721 4722 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4723 system_clock_mode = "AutoSync"; 4724 else 4725 system_clock_mode = "Master"; 4726 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4727 4728 switch (hdspm_pref_sync_ref(hdspm)) { 4729 case HDSPM_SYNC_FROM_WORD: 4730 pref_sync_ref = "Word Clock"; 4731 break; 4732 case HDSPM_SYNC_FROM_MADI: 4733 pref_sync_ref = "MADI Sync"; 4734 break; 4735 case HDSPM_SYNC_FROM_TCO: 4736 pref_sync_ref = "TCO"; 4737 break; 4738 case HDSPM_SYNC_FROM_SYNC_IN: 4739 pref_sync_ref = "Sync In"; 4740 break; 4741 default: 4742 pref_sync_ref = "XXXX Clock"; 4743 break; 4744 } 4745 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4746 pref_sync_ref); 4747 4748 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4749 hdspm->system_sample_rate); 4750 4751 4752 snd_iprintf(buffer, "--- Status:\n"); 4753 4754 x = status & HDSPM_madiSync; 4755 x2 = status2 & HDSPM_wcSync; 4756 4757 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4758 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4759 "NoLock", 4760 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4761 "NoLock"); 4762 4763 switch (hdspm_autosync_ref(hdspm)) { 4764 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4765 autosync_ref = "Sync In"; 4766 break; 4767 case HDSPM_AUTOSYNC_FROM_TCO: 4768 autosync_ref = "TCO"; 4769 break; 4770 case HDSPM_AUTOSYNC_FROM_WORD: 4771 autosync_ref = "Word Clock"; 4772 break; 4773 case HDSPM_AUTOSYNC_FROM_MADI: 4774 autosync_ref = "MADI Sync"; 4775 break; 4776 case HDSPM_AUTOSYNC_FROM_NONE: 4777 autosync_ref = "Input not valid"; 4778 break; 4779 default: 4780 autosync_ref = "---"; 4781 break; 4782 } 4783 snd_iprintf(buffer, 4784 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4785 autosync_ref, hdspm_external_sample_rate(hdspm), 4786 (status & HDSPM_madiFreqMask) >> 22, 4787 (status2 & HDSPM_wcFreqMask) >> 5); 4788 4789 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4790 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4791 (status & HDSPM_RX_64ch) ? "64 channels" : 4792 "56 channels"); 4793 4794 snd_iprintf(buffer, "\n"); 4795 } 4796 4797 static void 4798 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4799 struct snd_info_buffer *buffer) 4800 { 4801 struct hdspm *hdspm = entry->private_data; 4802 unsigned int status; 4803 unsigned int status2; 4804 unsigned int timecode; 4805 int pref_syncref; 4806 char *autosync_ref; 4807 int x; 4808 4809 status = hdspm_read(hdspm, HDSPM_statusRegister); 4810 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4811 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4812 4813 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4814 hdspm->card_name, hdspm->card->number + 1, 4815 hdspm->firmware_rev); 4816 4817 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4818 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4819 4820 snd_iprintf(buffer, "--- System ---\n"); 4821 4822 snd_iprintf(buffer, 4823 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4824 status & HDSPM_audioIRQPending, 4825 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4826 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4827 hdspm->irq_count); 4828 snd_iprintf(buffer, 4829 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4830 "estimated= %ld (bytes)\n", 4831 ((status & HDSPM_BufferID) ? 1 : 0), 4832 (status & HDSPM_BufferPositionMask), 4833 (status & HDSPM_BufferPositionMask) % 4834 (2 * (int)hdspm->period_bytes), 4835 ((status & HDSPM_BufferPositionMask) - 64) % 4836 (2 * (int)hdspm->period_bytes), 4837 (long) hdspm_hw_pointer(hdspm) * 4); 4838 4839 snd_iprintf(buffer, 4840 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4841 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4842 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4843 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4844 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4845 snd_iprintf(buffer, 4846 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4847 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4848 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4849 snd_iprintf(buffer, 4850 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4851 "status2=0x%x\n", 4852 hdspm->control_register, hdspm->control2_register, 4853 status, status2); 4854 4855 snd_iprintf(buffer, "--- Settings ---\n"); 4856 4857 x = 1 << (6 + hdspm_decode_latency(hdspm->control_register & 4858 HDSPM_LatencyMask)); 4859 4860 snd_iprintf(buffer, 4861 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4862 x, (unsigned long) hdspm->period_bytes); 4863 4864 snd_iprintf(buffer, "Line out: %s\n", 4865 (hdspm-> 4866 control_register & HDSPM_LineOut) ? "on " : "off"); 4867 4868 snd_iprintf(buffer, 4869 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 4870 (hdspm-> 4871 control_register & HDSPM_clr_tms) ? "on" : "off", 4872 (hdspm-> 4873 control_register & HDSPM_Emphasis) ? "on" : "off", 4874 (hdspm-> 4875 control_register & HDSPM_Dolby) ? "on" : "off"); 4876 4877 4878 pref_syncref = hdspm_pref_sync_ref(hdspm); 4879 if (pref_syncref == 0) 4880 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 4881 else 4882 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 4883 pref_syncref); 4884 4885 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4886 hdspm->system_sample_rate); 4887 4888 snd_iprintf(buffer, "Double speed: %s\n", 4889 hdspm->control_register & HDSPM_DS_DoubleWire? 4890 "Double wire" : "Single wire"); 4891 snd_iprintf(buffer, "Quad speed: %s\n", 4892 hdspm->control_register & HDSPM_QS_DoubleWire? 4893 "Double wire" : 4894 hdspm->control_register & HDSPM_QS_QuadWire? 4895 "Quad wire" : "Single wire"); 4896 4897 snd_iprintf(buffer, "--- Status:\n"); 4898 4899 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 4900 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock", 4901 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 4902 4903 for (x = 0; x < 8; x++) { 4904 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 4905 x+1, 4906 (status2 & (HDSPM_LockAES >> x)) ? 4907 "Sync " : "No Lock", 4908 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 4909 } 4910 4911 switch (hdspm_autosync_ref(hdspm)) { 4912 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 4913 autosync_ref = "None"; break; 4914 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 4915 autosync_ref = "Word Clock"; break; 4916 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 4917 autosync_ref = "AES1"; break; 4918 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 4919 autosync_ref = "AES2"; break; 4920 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 4921 autosync_ref = "AES3"; break; 4922 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 4923 autosync_ref = "AES4"; break; 4924 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 4925 autosync_ref = "AES5"; break; 4926 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 4927 autosync_ref = "AES6"; break; 4928 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 4929 autosync_ref = "AES7"; break; 4930 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 4931 autosync_ref = "AES8"; break; 4932 default: 4933 autosync_ref = "---"; break; 4934 } 4935 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 4936 4937 snd_iprintf(buffer, "\n"); 4938 } 4939 4940 static void 4941 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 4942 struct snd_info_buffer *buffer) 4943 { 4944 struct hdspm *hdspm = entry->private_data; 4945 unsigned int status1, status2, status3, control, i; 4946 unsigned int lock, sync; 4947 4948 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 4949 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 4950 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 4951 4952 control = hdspm->control_register; 4953 4954 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 4955 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 4956 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 4957 4958 4959 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 4960 4961 snd_iprintf(buffer, "Clock mode : %s\n", 4962 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 4963 snd_iprintf(buffer, "System frequency: %d Hz\n", 4964 hdspm_get_system_sample_rate(hdspm)); 4965 4966 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 4967 4968 lock = 0x1; 4969 sync = 0x100; 4970 4971 for (i = 0; i < 8; i++) { 4972 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 4973 i, 4974 (status1 & lock) ? 1 : 0, 4975 (status1 & sync) ? 1 : 0, 4976 texts_freq[(status2 >> (i * 4)) & 0xF]); 4977 4978 lock = lock<<1; 4979 sync = sync<<1; 4980 } 4981 4982 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 4983 (status1 & 0x1000000) ? 1 : 0, 4984 (status1 & 0x2000000) ? 1 : 0, 4985 texts_freq[(status1 >> 16) & 0xF]); 4986 4987 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 4988 (status1 & 0x4000000) ? 1 : 0, 4989 (status1 & 0x8000000) ? 1 : 0, 4990 texts_freq[(status1 >> 20) & 0xF]); 4991 4992 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 4993 (status3 & 0x400) ? 1 : 0, 4994 (status3 & 0x800) ? 1 : 0, 4995 texts_freq[(status2 >> 12) & 0xF]); 4996 4997 } 4998 4999 #ifdef CONFIG_SND_DEBUG 5000 static void 5001 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5002 struct snd_info_buffer *buffer) 5003 { 5004 struct hdspm *hdspm = entry->private_data; 5005 5006 int j,i; 5007 5008 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5009 snd_iprintf(buffer, "0x%08X: ", i); 5010 for (j = 0; j < 16; j += 4) 5011 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5012 snd_iprintf(buffer, "\n"); 5013 } 5014 } 5015 #endif 5016 5017 5018 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5019 struct snd_info_buffer *buffer) 5020 { 5021 struct hdspm *hdspm = entry->private_data; 5022 int i; 5023 5024 snd_iprintf(buffer, "# generated by hdspm\n"); 5025 5026 for (i = 0; i < hdspm->max_channels_in; i++) { 5027 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5028 } 5029 } 5030 5031 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5032 struct snd_info_buffer *buffer) 5033 { 5034 struct hdspm *hdspm = entry->private_data; 5035 int i; 5036 5037 snd_iprintf(buffer, "# generated by hdspm\n"); 5038 5039 for (i = 0; i < hdspm->max_channels_out; i++) { 5040 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5041 } 5042 } 5043 5044 5045 static void __devinit snd_hdspm_proc_init(struct hdspm *hdspm) 5046 { 5047 struct snd_info_entry *entry; 5048 5049 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 5050 switch (hdspm->io_type) { 5051 case AES32: 5052 snd_info_set_text_ops(entry, hdspm, 5053 snd_hdspm_proc_read_aes32); 5054 break; 5055 case MADI: 5056 snd_info_set_text_ops(entry, hdspm, 5057 snd_hdspm_proc_read_madi); 5058 break; 5059 case MADIface: 5060 /* snd_info_set_text_ops(entry, hdspm, 5061 snd_hdspm_proc_read_madiface); */ 5062 break; 5063 case RayDAT: 5064 snd_info_set_text_ops(entry, hdspm, 5065 snd_hdspm_proc_read_raydat); 5066 break; 5067 case AIO: 5068 break; 5069 } 5070 } 5071 5072 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 5073 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 5074 } 5075 5076 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 5077 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 5078 } 5079 5080 #ifdef CONFIG_SND_DEBUG 5081 /* debug file to read all hdspm registers */ 5082 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 5083 snd_info_set_text_ops(entry, hdspm, 5084 snd_hdspm_proc_read_debug); 5085 #endif 5086 } 5087 5088 /*------------------------------------------------------------ 5089 hdspm intitialize 5090 ------------------------------------------------------------*/ 5091 5092 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5093 { 5094 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5095 hold it (e.g. during module initialization). 5096 */ 5097 5098 /* set defaults: */ 5099 5100 hdspm->settings_register = 0; 5101 5102 switch (hdspm->io_type) { 5103 case MADI: 5104 case MADIface: 5105 hdspm->control_register = 5106 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5107 break; 5108 5109 case RayDAT: 5110 case AIO: 5111 hdspm->settings_register = 0x1 + 0x1000; 5112 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5113 * line_out */ 5114 hdspm->control_register = 5115 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5116 break; 5117 5118 case AES32: 5119 hdspm->control_register = 5120 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 5121 hdspm_encode_latency(7) | /* latency max=8192samples */ 5122 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5123 HDSPM_LineOut | /* Analog output in */ 5124 HDSPM_Professional; /* Professional mode */ 5125 break; 5126 } 5127 5128 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5129 5130 if (AES32 == hdspm->io_type) { 5131 /* No control2 register for AES32 */ 5132 #ifdef SNDRV_BIG_ENDIAN 5133 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5134 #else 5135 hdspm->control2_register = 0; 5136 #endif 5137 5138 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5139 } 5140 hdspm_compute_period_size(hdspm); 5141 5142 /* silence everything */ 5143 5144 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5145 5146 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { 5147 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5148 } 5149 5150 /* set a default rate so that the channel map is set up. */ 5151 hdspm_set_rate(hdspm, 48000, 1); 5152 5153 return 0; 5154 } 5155 5156 5157 /*------------------------------------------------------------ 5158 interrupt 5159 ------------------------------------------------------------*/ 5160 5161 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5162 { 5163 struct hdspm *hdspm = (struct hdspm *) dev_id; 5164 unsigned int status; 5165 int i, audio, midi, schedule = 0; 5166 /* cycles_t now; */ 5167 5168 status = hdspm_read(hdspm, HDSPM_statusRegister); 5169 5170 audio = status & HDSPM_audioIRQPending; 5171 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5172 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5173 5174 /* now = get_cycles(); */ 5175 /** 5176 * LAT_2..LAT_0 period counter (win) counter (mac) 5177 * 6 4096 ~256053425 ~514672358 5178 * 5 2048 ~128024983 ~257373821 5179 * 4 1024 ~64023706 ~128718089 5180 * 3 512 ~32005945 ~64385999 5181 * 2 256 ~16003039 ~32260176 5182 * 1 128 ~7998738 ~16194507 5183 * 0 64 ~3998231 ~8191558 5184 **/ 5185 /* 5186 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5187 now-hdspm->last_interrupt, status & 0xFFC0); 5188 hdspm->last_interrupt = now; 5189 */ 5190 5191 if (!audio && !midi) 5192 return IRQ_NONE; 5193 5194 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5195 hdspm->irq_count++; 5196 5197 5198 if (audio) { 5199 if (hdspm->capture_substream) 5200 snd_pcm_period_elapsed(hdspm->capture_substream); 5201 5202 if (hdspm->playback_substream) 5203 snd_pcm_period_elapsed(hdspm->playback_substream); 5204 } 5205 5206 if (midi) { 5207 i = 0; 5208 while (i < hdspm->midiPorts) { 5209 if ((hdspm_read(hdspm, 5210 hdspm->midi[i].statusIn) & 0xff) && 5211 (status & hdspm->midi[i].irq)) { 5212 /* we disable interrupts for this input until 5213 * processing is done 5214 */ 5215 hdspm->control_register &= ~hdspm->midi[i].ie; 5216 hdspm_write(hdspm, HDSPM_controlRegister, 5217 hdspm->control_register); 5218 hdspm->midi[i].pending = 1; 5219 schedule = 1; 5220 } 5221 5222 i++; 5223 } 5224 5225 if (schedule) 5226 tasklet_hi_schedule(&hdspm->midi_tasklet); 5227 } 5228 5229 return IRQ_HANDLED; 5230 } 5231 5232 /*------------------------------------------------------------ 5233 pcm interface 5234 ------------------------------------------------------------*/ 5235 5236 5237 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5238 *substream) 5239 { 5240 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5241 return hdspm_hw_pointer(hdspm); 5242 } 5243 5244 5245 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5246 { 5247 struct snd_pcm_runtime *runtime = substream->runtime; 5248 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5249 struct snd_pcm_substream *other; 5250 5251 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5252 other = hdspm->capture_substream; 5253 else 5254 other = hdspm->playback_substream; 5255 5256 if (hdspm->running) 5257 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5258 else 5259 runtime->status->hw_ptr = 0; 5260 if (other) { 5261 struct snd_pcm_substream *s; 5262 struct snd_pcm_runtime *oruntime = other->runtime; 5263 snd_pcm_group_for_each_entry(s, substream) { 5264 if (s == other) { 5265 oruntime->status->hw_ptr = 5266 runtime->status->hw_ptr; 5267 break; 5268 } 5269 } 5270 } 5271 return 0; 5272 } 5273 5274 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5275 struct snd_pcm_hw_params *params) 5276 { 5277 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5278 int err; 5279 int i; 5280 pid_t this_pid; 5281 pid_t other_pid; 5282 5283 spin_lock_irq(&hdspm->lock); 5284 5285 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5286 this_pid = hdspm->playback_pid; 5287 other_pid = hdspm->capture_pid; 5288 } else { 5289 this_pid = hdspm->capture_pid; 5290 other_pid = hdspm->playback_pid; 5291 } 5292 5293 if (other_pid > 0 && this_pid != other_pid) { 5294 5295 /* The other stream is open, and not by the same 5296 task as this one. Make sure that the parameters 5297 that matter are the same. 5298 */ 5299 5300 if (params_rate(params) != hdspm->system_sample_rate) { 5301 spin_unlock_irq(&hdspm->lock); 5302 _snd_pcm_hw_param_setempty(params, 5303 SNDRV_PCM_HW_PARAM_RATE); 5304 return -EBUSY; 5305 } 5306 5307 if (params_period_size(params) != hdspm->period_bytes / 4) { 5308 spin_unlock_irq(&hdspm->lock); 5309 _snd_pcm_hw_param_setempty(params, 5310 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5311 return -EBUSY; 5312 } 5313 5314 } 5315 /* We're fine. */ 5316 spin_unlock_irq(&hdspm->lock); 5317 5318 /* how to make sure that the rate matches an externally-set one ? */ 5319 5320 spin_lock_irq(&hdspm->lock); 5321 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5322 if (err < 0) { 5323 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5324 spin_unlock_irq(&hdspm->lock); 5325 _snd_pcm_hw_param_setempty(params, 5326 SNDRV_PCM_HW_PARAM_RATE); 5327 return err; 5328 } 5329 spin_unlock_irq(&hdspm->lock); 5330 5331 err = hdspm_set_interrupt_interval(hdspm, 5332 params_period_size(params)); 5333 if (err < 0) { 5334 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5335 _snd_pcm_hw_param_setempty(params, 5336 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5337 return err; 5338 } 5339 5340 /* Memory allocation, takashi's method, dont know if we should 5341 * spinlock 5342 */ 5343 /* malloc all buffer even if not enabled to get sure */ 5344 /* Update for MADI rev 204: we need to allocate for all channels, 5345 * otherwise it doesn't work at 96kHz */ 5346 5347 err = 5348 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5349 if (err < 0) { 5350 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5351 return err; 5352 } 5353 5354 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5355 5356 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5357 params_channels(params)); 5358 5359 for (i = 0; i < params_channels(params); ++i) 5360 snd_hdspm_enable_out(hdspm, i, 1); 5361 5362 hdspm->playback_buffer = 5363 (unsigned char *) substream->runtime->dma_area; 5364 snd_printdd("Allocated sample buffer for playback at %p\n", 5365 hdspm->playback_buffer); 5366 } else { 5367 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5368 params_channels(params)); 5369 5370 for (i = 0; i < params_channels(params); ++i) 5371 snd_hdspm_enable_in(hdspm, i, 1); 5372 5373 hdspm->capture_buffer = 5374 (unsigned char *) substream->runtime->dma_area; 5375 snd_printdd("Allocated sample buffer for capture at %p\n", 5376 hdspm->capture_buffer); 5377 } 5378 5379 /* 5380 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5381 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5382 "playback" : "capture", 5383 snd_pcm_sgbuf_get_addr(substream, 0)); 5384 */ 5385 /* 5386 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5387 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5388 "playback" : "capture", 5389 params_rate(params), params_channels(params), 5390 params_buffer_size(params)); 5391 */ 5392 5393 5394 /* Switch to native float format if requested */ 5395 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5396 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5397 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5398 5399 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5400 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5401 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5402 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5403 5404 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5405 } 5406 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5407 5408 return 0; 5409 } 5410 5411 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5412 { 5413 int i; 5414 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5415 5416 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5417 5418 /* params_channels(params) should be enough, 5419 but to get sure in case of error */ 5420 for (i = 0; i < hdspm->max_channels_out; ++i) 5421 snd_hdspm_enable_out(hdspm, i, 0); 5422 5423 hdspm->playback_buffer = NULL; 5424 } else { 5425 for (i = 0; i < hdspm->max_channels_in; ++i) 5426 snd_hdspm_enable_in(hdspm, i, 0); 5427 5428 hdspm->capture_buffer = NULL; 5429 5430 } 5431 5432 snd_pcm_lib_free_pages(substream); 5433 5434 return 0; 5435 } 5436 5437 5438 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5439 struct snd_pcm_channel_info *info) 5440 { 5441 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5442 5443 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5444 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5445 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5446 return -EINVAL; 5447 } 5448 5449 if (hdspm->channel_map_out[info->channel] < 0) { 5450 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5451 return -EINVAL; 5452 } 5453 5454 info->offset = hdspm->channel_map_out[info->channel] * 5455 HDSPM_CHANNEL_BUFFER_BYTES; 5456 } else { 5457 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5458 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5459 return -EINVAL; 5460 } 5461 5462 if (hdspm->channel_map_in[info->channel] < 0) { 5463 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5464 return -EINVAL; 5465 } 5466 5467 info->offset = hdspm->channel_map_in[info->channel] * 5468 HDSPM_CHANNEL_BUFFER_BYTES; 5469 } 5470 5471 info->first = 0; 5472 info->step = 32; 5473 return 0; 5474 } 5475 5476 5477 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5478 unsigned int cmd, void *arg) 5479 { 5480 switch (cmd) { 5481 case SNDRV_PCM_IOCTL1_RESET: 5482 return snd_hdspm_reset(substream); 5483 5484 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5485 { 5486 struct snd_pcm_channel_info *info = arg; 5487 return snd_hdspm_channel_info(substream, info); 5488 } 5489 default: 5490 break; 5491 } 5492 5493 return snd_pcm_lib_ioctl(substream, cmd, arg); 5494 } 5495 5496 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5497 { 5498 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5499 struct snd_pcm_substream *other; 5500 int running; 5501 5502 spin_lock(&hdspm->lock); 5503 running = hdspm->running; 5504 switch (cmd) { 5505 case SNDRV_PCM_TRIGGER_START: 5506 running |= 1 << substream->stream; 5507 break; 5508 case SNDRV_PCM_TRIGGER_STOP: 5509 running &= ~(1 << substream->stream); 5510 break; 5511 default: 5512 snd_BUG(); 5513 spin_unlock(&hdspm->lock); 5514 return -EINVAL; 5515 } 5516 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5517 other = hdspm->capture_substream; 5518 else 5519 other = hdspm->playback_substream; 5520 5521 if (other) { 5522 struct snd_pcm_substream *s; 5523 snd_pcm_group_for_each_entry(s, substream) { 5524 if (s == other) { 5525 snd_pcm_trigger_done(s, substream); 5526 if (cmd == SNDRV_PCM_TRIGGER_START) 5527 running |= 1 << s->stream; 5528 else 5529 running &= ~(1 << s->stream); 5530 goto _ok; 5531 } 5532 } 5533 if (cmd == SNDRV_PCM_TRIGGER_START) { 5534 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5535 && substream->stream == 5536 SNDRV_PCM_STREAM_CAPTURE) 5537 hdspm_silence_playback(hdspm); 5538 } else { 5539 if (running && 5540 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5541 hdspm_silence_playback(hdspm); 5542 } 5543 } else { 5544 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5545 hdspm_silence_playback(hdspm); 5546 } 5547 _ok: 5548 snd_pcm_trigger_done(substream, substream); 5549 if (!hdspm->running && running) 5550 hdspm_start_audio(hdspm); 5551 else if (hdspm->running && !running) 5552 hdspm_stop_audio(hdspm); 5553 hdspm->running = running; 5554 spin_unlock(&hdspm->lock); 5555 5556 return 0; 5557 } 5558 5559 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5560 { 5561 return 0; 5562 } 5563 5564 static unsigned int period_sizes_old[] = { 5565 64, 128, 256, 512, 1024, 2048, 4096 5566 }; 5567 5568 static unsigned int period_sizes_new[] = { 5569 32, 64, 128, 256, 512, 1024, 2048, 4096 5570 }; 5571 5572 /* RayDAT and AIO always have a buffer of 16384 samples per channel */ 5573 static unsigned int raydat_aio_buffer_sizes[] = { 5574 16384 5575 }; 5576 5577 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5578 .info = (SNDRV_PCM_INFO_MMAP | 5579 SNDRV_PCM_INFO_MMAP_VALID | 5580 SNDRV_PCM_INFO_NONINTERLEAVED | 5581 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5582 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5583 .rates = (SNDRV_PCM_RATE_32000 | 5584 SNDRV_PCM_RATE_44100 | 5585 SNDRV_PCM_RATE_48000 | 5586 SNDRV_PCM_RATE_64000 | 5587 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5588 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5589 .rate_min = 32000, 5590 .rate_max = 192000, 5591 .channels_min = 1, 5592 .channels_max = HDSPM_MAX_CHANNELS, 5593 .buffer_bytes_max = 5594 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5595 .period_bytes_min = (64 * 4), 5596 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, 5597 .periods_min = 2, 5598 .periods_max = 512, 5599 .fifo_size = 0 5600 }; 5601 5602 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5603 .info = (SNDRV_PCM_INFO_MMAP | 5604 SNDRV_PCM_INFO_MMAP_VALID | 5605 SNDRV_PCM_INFO_NONINTERLEAVED | 5606 SNDRV_PCM_INFO_SYNC_START), 5607 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5608 .rates = (SNDRV_PCM_RATE_32000 | 5609 SNDRV_PCM_RATE_44100 | 5610 SNDRV_PCM_RATE_48000 | 5611 SNDRV_PCM_RATE_64000 | 5612 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5613 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5614 .rate_min = 32000, 5615 .rate_max = 192000, 5616 .channels_min = 1, 5617 .channels_max = HDSPM_MAX_CHANNELS, 5618 .buffer_bytes_max = 5619 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5620 .period_bytes_min = (64 * 4), 5621 .period_bytes_max = (4096 * 4) * HDSPM_MAX_CHANNELS, 5622 .periods_min = 2, 5623 .periods_max = 512, 5624 .fifo_size = 0 5625 }; 5626 5627 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_old = { 5628 .count = ARRAY_SIZE(period_sizes_old), 5629 .list = period_sizes_old, 5630 .mask = 0 5631 }; 5632 5633 static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes_new = { 5634 .count = ARRAY_SIZE(period_sizes_new), 5635 .list = period_sizes_new, 5636 .mask = 0 5637 }; 5638 5639 static struct snd_pcm_hw_constraint_list hw_constraints_raydat_io_buffer = { 5640 .count = ARRAY_SIZE(raydat_aio_buffer_sizes), 5641 .list = raydat_aio_buffer_sizes, 5642 .mask = 0 5643 }; 5644 5645 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5646 struct snd_pcm_hw_rule *rule) 5647 { 5648 struct hdspm *hdspm = rule->private; 5649 struct snd_interval *c = 5650 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5651 struct snd_interval *r = 5652 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5653 5654 if (r->min > 96000 && r->max <= 192000) { 5655 struct snd_interval t = { 5656 .min = hdspm->qs_in_channels, 5657 .max = hdspm->qs_in_channels, 5658 .integer = 1, 5659 }; 5660 return snd_interval_refine(c, &t); 5661 } else if (r->min > 48000 && r->max <= 96000) { 5662 struct snd_interval t = { 5663 .min = hdspm->ds_in_channels, 5664 .max = hdspm->ds_in_channels, 5665 .integer = 1, 5666 }; 5667 return snd_interval_refine(c, &t); 5668 } else if (r->max < 64000) { 5669 struct snd_interval t = { 5670 .min = hdspm->ss_in_channels, 5671 .max = hdspm->ss_in_channels, 5672 .integer = 1, 5673 }; 5674 return snd_interval_refine(c, &t); 5675 } 5676 5677 return 0; 5678 } 5679 5680 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5681 struct snd_pcm_hw_rule * rule) 5682 { 5683 struct hdspm *hdspm = rule->private; 5684 struct snd_interval *c = 5685 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5686 struct snd_interval *r = 5687 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5688 5689 if (r->min > 96000 && r->max <= 192000) { 5690 struct snd_interval t = { 5691 .min = hdspm->qs_out_channels, 5692 .max = hdspm->qs_out_channels, 5693 .integer = 1, 5694 }; 5695 return snd_interval_refine(c, &t); 5696 } else if (r->min > 48000 && r->max <= 96000) { 5697 struct snd_interval t = { 5698 .min = hdspm->ds_out_channels, 5699 .max = hdspm->ds_out_channels, 5700 .integer = 1, 5701 }; 5702 return snd_interval_refine(c, &t); 5703 } else if (r->max < 64000) { 5704 struct snd_interval t = { 5705 .min = hdspm->ss_out_channels, 5706 .max = hdspm->ss_out_channels, 5707 .integer = 1, 5708 }; 5709 return snd_interval_refine(c, &t); 5710 } else { 5711 } 5712 return 0; 5713 } 5714 5715 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5716 struct snd_pcm_hw_rule * rule) 5717 { 5718 struct hdspm *hdspm = rule->private; 5719 struct snd_interval *c = 5720 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5721 struct snd_interval *r = 5722 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5723 5724 if (c->min >= hdspm->ss_in_channels) { 5725 struct snd_interval t = { 5726 .min = 32000, 5727 .max = 48000, 5728 .integer = 1, 5729 }; 5730 return snd_interval_refine(r, &t); 5731 } else if (c->max <= hdspm->qs_in_channels) { 5732 struct snd_interval t = { 5733 .min = 128000, 5734 .max = 192000, 5735 .integer = 1, 5736 }; 5737 return snd_interval_refine(r, &t); 5738 } else if (c->max <= hdspm->ds_in_channels) { 5739 struct snd_interval t = { 5740 .min = 64000, 5741 .max = 96000, 5742 .integer = 1, 5743 }; 5744 return snd_interval_refine(r, &t); 5745 } 5746 5747 return 0; 5748 } 5749 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5750 struct snd_pcm_hw_rule *rule) 5751 { 5752 struct hdspm *hdspm = rule->private; 5753 struct snd_interval *c = 5754 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5755 struct snd_interval *r = 5756 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5757 5758 if (c->min >= hdspm->ss_out_channels) { 5759 struct snd_interval t = { 5760 .min = 32000, 5761 .max = 48000, 5762 .integer = 1, 5763 }; 5764 return snd_interval_refine(r, &t); 5765 } else if (c->max <= hdspm->qs_out_channels) { 5766 struct snd_interval t = { 5767 .min = 128000, 5768 .max = 192000, 5769 .integer = 1, 5770 }; 5771 return snd_interval_refine(r, &t); 5772 } else if (c->max <= hdspm->ds_out_channels) { 5773 struct snd_interval t = { 5774 .min = 64000, 5775 .max = 96000, 5776 .integer = 1, 5777 }; 5778 return snd_interval_refine(r, &t); 5779 } 5780 5781 return 0; 5782 } 5783 5784 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5785 struct snd_pcm_hw_rule *rule) 5786 { 5787 unsigned int list[3]; 5788 struct hdspm *hdspm = rule->private; 5789 struct snd_interval *c = hw_param_interval(params, 5790 SNDRV_PCM_HW_PARAM_CHANNELS); 5791 5792 list[0] = hdspm->qs_in_channels; 5793 list[1] = hdspm->ds_in_channels; 5794 list[2] = hdspm->ss_in_channels; 5795 return snd_interval_list(c, 3, list, 0); 5796 } 5797 5798 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5799 struct snd_pcm_hw_rule *rule) 5800 { 5801 unsigned int list[3]; 5802 struct hdspm *hdspm = rule->private; 5803 struct snd_interval *c = hw_param_interval(params, 5804 SNDRV_PCM_HW_PARAM_CHANNELS); 5805 5806 list[0] = hdspm->qs_out_channels; 5807 list[1] = hdspm->ds_out_channels; 5808 list[2] = hdspm->ss_out_channels; 5809 return snd_interval_list(c, 3, list, 0); 5810 } 5811 5812 5813 static unsigned int hdspm_aes32_sample_rates[] = { 5814 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5815 }; 5816 5817 static struct snd_pcm_hw_constraint_list 5818 hdspm_hw_constraints_aes32_sample_rates = { 5819 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5820 .list = hdspm_aes32_sample_rates, 5821 .mask = 0 5822 }; 5823 5824 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5825 { 5826 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5827 struct snd_pcm_runtime *runtime = substream->runtime; 5828 5829 spin_lock_irq(&hdspm->lock); 5830 5831 snd_pcm_set_sync(substream); 5832 5833 5834 runtime->hw = snd_hdspm_playback_subinfo; 5835 5836 if (hdspm->capture_substream == NULL) 5837 hdspm_stop_audio(hdspm); 5838 5839 hdspm->playback_pid = current->pid; 5840 hdspm->playback_substream = substream; 5841 5842 spin_unlock_irq(&hdspm->lock); 5843 5844 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5845 5846 switch (hdspm->io_type) { 5847 case AIO: 5848 case RayDAT: 5849 snd_pcm_hw_constraint_list(runtime, 0, 5850 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5851 &hw_constraints_period_sizes_new); 5852 snd_pcm_hw_constraint_list(runtime, 0, 5853 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5854 &hw_constraints_raydat_io_buffer); 5855 5856 break; 5857 5858 default: 5859 snd_pcm_hw_constraint_list(runtime, 0, 5860 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5861 &hw_constraints_period_sizes_old); 5862 } 5863 5864 if (AES32 == hdspm->io_type) { 5865 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5866 &hdspm_hw_constraints_aes32_sample_rates); 5867 } else { 5868 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5869 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5870 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5871 } 5872 5873 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5874 snd_hdspm_hw_rule_out_channels, hdspm, 5875 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5876 5877 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5878 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5879 SNDRV_PCM_HW_PARAM_RATE, -1); 5880 5881 return 0; 5882 } 5883 5884 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5885 { 5886 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5887 5888 spin_lock_irq(&hdspm->lock); 5889 5890 hdspm->playback_pid = -1; 5891 hdspm->playback_substream = NULL; 5892 5893 spin_unlock_irq(&hdspm->lock); 5894 5895 return 0; 5896 } 5897 5898 5899 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 5900 { 5901 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5902 struct snd_pcm_runtime *runtime = substream->runtime; 5903 5904 spin_lock_irq(&hdspm->lock); 5905 snd_pcm_set_sync(substream); 5906 runtime->hw = snd_hdspm_capture_subinfo; 5907 5908 if (hdspm->playback_substream == NULL) 5909 hdspm_stop_audio(hdspm); 5910 5911 hdspm->capture_pid = current->pid; 5912 hdspm->capture_substream = substream; 5913 5914 spin_unlock_irq(&hdspm->lock); 5915 5916 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5917 switch (hdspm->io_type) { 5918 case AIO: 5919 case RayDAT: 5920 snd_pcm_hw_constraint_list(runtime, 0, 5921 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5922 &hw_constraints_period_sizes_new); 5923 snd_pcm_hw_constraint_list(runtime, 0, 5924 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5925 &hw_constraints_raydat_io_buffer); 5926 break; 5927 5928 default: 5929 snd_pcm_hw_constraint_list(runtime, 0, 5930 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5931 &hw_constraints_period_sizes_old); 5932 } 5933 5934 if (AES32 == hdspm->io_type) { 5935 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5936 &hdspm_hw_constraints_aes32_sample_rates); 5937 } else { 5938 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5939 snd_hdspm_hw_rule_rate_in_channels, hdspm, 5940 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5941 } 5942 5943 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5944 snd_hdspm_hw_rule_in_channels, hdspm, 5945 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5946 5947 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5948 snd_hdspm_hw_rule_in_channels_rate, hdspm, 5949 SNDRV_PCM_HW_PARAM_RATE, -1); 5950 5951 return 0; 5952 } 5953 5954 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 5955 { 5956 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5957 5958 spin_lock_irq(&hdspm->lock); 5959 5960 hdspm->capture_pid = -1; 5961 hdspm->capture_substream = NULL; 5962 5963 spin_unlock_irq(&hdspm->lock); 5964 return 0; 5965 } 5966 5967 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 5968 { 5969 /* we have nothing to initialize but the call is required */ 5970 return 0; 5971 } 5972 5973 static inline int copy_u32_le(void __user *dest, void __iomem *src) 5974 { 5975 u32 val = readl(src); 5976 return copy_to_user(dest, &val, 4); 5977 } 5978 5979 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 5980 unsigned int cmd, unsigned long __user arg) 5981 { 5982 void __user *argp = (void __user *)arg; 5983 struct hdspm *hdspm = hw->private_data; 5984 struct hdspm_mixer_ioctl mixer; 5985 struct hdspm_config info; 5986 struct hdspm_status status; 5987 struct hdspm_version hdspm_version; 5988 struct hdspm_peak_rms *levels; 5989 struct hdspm_ltc ltc; 5990 unsigned int statusregister; 5991 long unsigned int s; 5992 int i = 0; 5993 5994 switch (cmd) { 5995 5996 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 5997 levels = &hdspm->peak_rms; 5998 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 5999 levels->input_peaks[i] = 6000 readl(hdspm->iobase + 6001 HDSPM_MADI_INPUT_PEAK + i*4); 6002 levels->playback_peaks[i] = 6003 readl(hdspm->iobase + 6004 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6005 levels->output_peaks[i] = 6006 readl(hdspm->iobase + 6007 HDSPM_MADI_OUTPUT_PEAK + i*4); 6008 6009 levels->input_rms[i] = 6010 ((uint64_t) readl(hdspm->iobase + 6011 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6012 (uint64_t) readl(hdspm->iobase + 6013 HDSPM_MADI_INPUT_RMS_L + i*4); 6014 levels->playback_rms[i] = 6015 ((uint64_t)readl(hdspm->iobase + 6016 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6017 (uint64_t)readl(hdspm->iobase + 6018 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6019 levels->output_rms[i] = 6020 ((uint64_t)readl(hdspm->iobase + 6021 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6022 (uint64_t)readl(hdspm->iobase + 6023 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6024 } 6025 6026 if (hdspm->system_sample_rate > 96000) { 6027 levels->speed = qs; 6028 } else if (hdspm->system_sample_rate > 48000) { 6029 levels->speed = ds; 6030 } else { 6031 levels->speed = ss; 6032 } 6033 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6034 6035 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 6036 if (0 != s) { 6037 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 6038 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6039 */ 6040 return -EFAULT; 6041 } 6042 break; 6043 6044 case SNDRV_HDSPM_IOCTL_GET_LTC: 6045 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6046 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6047 if (i & HDSPM_TCO1_LTC_Input_valid) { 6048 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6049 HDSPM_TCO1_LTC_Format_MSB)) { 6050 case 0: 6051 ltc.format = fps_24; 6052 break; 6053 case HDSPM_TCO1_LTC_Format_LSB: 6054 ltc.format = fps_25; 6055 break; 6056 case HDSPM_TCO1_LTC_Format_MSB: 6057 ltc.format = fps_2997; 6058 break; 6059 default: 6060 ltc.format = 30; 6061 break; 6062 } 6063 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6064 ltc.frame = drop_frame; 6065 } else { 6066 ltc.frame = full_frame; 6067 } 6068 } else { 6069 ltc.format = format_invalid; 6070 ltc.frame = frame_invalid; 6071 } 6072 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6073 ltc.input_format = ntsc; 6074 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6075 ltc.input_format = pal; 6076 } else { 6077 ltc.input_format = no_video; 6078 } 6079 6080 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 6081 if (0 != s) { 6082 /* 6083 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6084 return -EFAULT; 6085 } 6086 6087 break; 6088 6089 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6090 6091 memset(&info, 0, sizeof(info)); 6092 spin_lock_irq(&hdspm->lock); 6093 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6094 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6095 6096 info.system_sample_rate = hdspm->system_sample_rate; 6097 info.autosync_sample_rate = 6098 hdspm_external_sample_rate(hdspm); 6099 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6100 info.clock_source = hdspm_clock_source(hdspm); 6101 info.autosync_ref = hdspm_autosync_ref(hdspm); 6102 info.line_out = hdspm_line_out(hdspm); 6103 info.passthru = 0; 6104 spin_unlock_irq(&hdspm->lock); 6105 if (copy_to_user((void __user *) arg, &info, sizeof(info))) 6106 return -EFAULT; 6107 break; 6108 6109 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6110 status.card_type = hdspm->io_type; 6111 6112 status.autosync_source = hdspm_autosync_ref(hdspm); 6113 6114 status.card_clock = 110069313433624ULL; 6115 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6116 6117 switch (hdspm->io_type) { 6118 case MADI: 6119 case MADIface: 6120 status.card_specific.madi.sync_wc = 6121 hdspm_wc_sync_check(hdspm); 6122 status.card_specific.madi.sync_madi = 6123 hdspm_madi_sync_check(hdspm); 6124 status.card_specific.madi.sync_tco = 6125 hdspm_tco_sync_check(hdspm); 6126 status.card_specific.madi.sync_in = 6127 hdspm_sync_in_sync_check(hdspm); 6128 6129 statusregister = 6130 hdspm_read(hdspm, HDSPM_statusRegister); 6131 status.card_specific.madi.madi_input = 6132 (statusregister & HDSPM_AB_int) ? 1 : 0; 6133 status.card_specific.madi.channel_format = 6134 (statusregister & HDSPM_TX_64ch) ? 1 : 0; 6135 /* TODO: Mac driver sets it when f_s>48kHz */ 6136 status.card_specific.madi.frame_format = 0; 6137 6138 default: 6139 break; 6140 } 6141 6142 if (copy_to_user((void __user *) arg, &status, sizeof(status))) 6143 return -EFAULT; 6144 6145 6146 break; 6147 6148 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6149 hdspm_version.card_type = hdspm->io_type; 6150 strncpy(hdspm_version.cardname, hdspm->card_name, 6151 sizeof(hdspm_version.cardname)); 6152 hdspm_version.serial = (hdspm_read(hdspm, 6153 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6154 hdspm_version.firmware_rev = hdspm->firmware_rev; 6155 hdspm_version.addons = 0; 6156 if (hdspm->tco) 6157 hdspm_version.addons |= HDSPM_ADDON_TCO; 6158 6159 if (copy_to_user((void __user *) arg, &hdspm_version, 6160 sizeof(hdspm_version))) 6161 return -EFAULT; 6162 break; 6163 6164 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6165 if (copy_from_user(&mixer, (void __user *)arg, sizeof(mixer))) 6166 return -EFAULT; 6167 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6168 sizeof(struct hdspm_mixer))) 6169 return -EFAULT; 6170 break; 6171 6172 default: 6173 return -EINVAL; 6174 } 6175 return 0; 6176 } 6177 6178 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6179 .open = snd_hdspm_playback_open, 6180 .close = snd_hdspm_playback_release, 6181 .ioctl = snd_hdspm_ioctl, 6182 .hw_params = snd_hdspm_hw_params, 6183 .hw_free = snd_hdspm_hw_free, 6184 .prepare = snd_hdspm_prepare, 6185 .trigger = snd_hdspm_trigger, 6186 .pointer = snd_hdspm_hw_pointer, 6187 .page = snd_pcm_sgbuf_ops_page, 6188 }; 6189 6190 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6191 .open = snd_hdspm_capture_open, 6192 .close = snd_hdspm_capture_release, 6193 .ioctl = snd_hdspm_ioctl, 6194 .hw_params = snd_hdspm_hw_params, 6195 .hw_free = snd_hdspm_hw_free, 6196 .prepare = snd_hdspm_prepare, 6197 .trigger = snd_hdspm_trigger, 6198 .pointer = snd_hdspm_hw_pointer, 6199 .page = snd_pcm_sgbuf_ops_page, 6200 }; 6201 6202 static int __devinit snd_hdspm_create_hwdep(struct snd_card *card, 6203 struct hdspm * hdspm) 6204 { 6205 struct snd_hwdep *hw; 6206 int err; 6207 6208 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6209 if (err < 0) 6210 return err; 6211 6212 hdspm->hwdep = hw; 6213 hw->private_data = hdspm; 6214 strcpy(hw->name, "HDSPM hwdep interface"); 6215 6216 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6217 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6218 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6219 6220 return 0; 6221 } 6222 6223 6224 /*------------------------------------------------------------ 6225 memory interface 6226 ------------------------------------------------------------*/ 6227 static int __devinit snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6228 { 6229 int err; 6230 struct snd_pcm *pcm; 6231 size_t wanted; 6232 6233 pcm = hdspm->pcm; 6234 6235 wanted = HDSPM_DMA_AREA_BYTES; 6236 6237 err = 6238 snd_pcm_lib_preallocate_pages_for_all(pcm, 6239 SNDRV_DMA_TYPE_DEV_SG, 6240 snd_dma_pci_data(hdspm->pci), 6241 wanted, 6242 wanted); 6243 if (err < 0) { 6244 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6245 6246 return err; 6247 } else 6248 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6249 6250 return 0; 6251 } 6252 6253 6254 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6255 struct snd_pcm_substream *substream, 6256 unsigned int reg, int channels) 6257 { 6258 int i; 6259 6260 /* continuous memory segment */ 6261 for (i = 0; i < (channels * 16); i++) 6262 hdspm_write(hdspm, reg + 4 * i, 6263 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6264 } 6265 6266 6267 /* ------------- ALSA Devices ---------------------------- */ 6268 static int __devinit snd_hdspm_create_pcm(struct snd_card *card, 6269 struct hdspm *hdspm) 6270 { 6271 struct snd_pcm *pcm; 6272 int err; 6273 6274 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6275 if (err < 0) 6276 return err; 6277 6278 hdspm->pcm = pcm; 6279 pcm->private_data = hdspm; 6280 strcpy(pcm->name, hdspm->card_name); 6281 6282 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6283 &snd_hdspm_playback_ops); 6284 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6285 &snd_hdspm_capture_ops); 6286 6287 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6288 6289 err = snd_hdspm_preallocate_memory(hdspm); 6290 if (err < 0) 6291 return err; 6292 6293 return 0; 6294 } 6295 6296 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6297 { 6298 int i; 6299 6300 for (i = 0; i < hdspm->midiPorts; i++) 6301 snd_hdspm_flush_midi_input(hdspm, i); 6302 } 6303 6304 static int __devinit snd_hdspm_create_alsa_devices(struct snd_card *card, 6305 struct hdspm * hdspm) 6306 { 6307 int err, i; 6308 6309 snd_printdd("Create card...\n"); 6310 err = snd_hdspm_create_pcm(card, hdspm); 6311 if (err < 0) 6312 return err; 6313 6314 i = 0; 6315 while (i < hdspm->midiPorts) { 6316 err = snd_hdspm_create_midi(card, hdspm, i); 6317 if (err < 0) { 6318 return err; 6319 } 6320 i++; 6321 } 6322 6323 err = snd_hdspm_create_controls(card, hdspm); 6324 if (err < 0) 6325 return err; 6326 6327 err = snd_hdspm_create_hwdep(card, hdspm); 6328 if (err < 0) 6329 return err; 6330 6331 snd_printdd("proc init...\n"); 6332 snd_hdspm_proc_init(hdspm); 6333 6334 hdspm->system_sample_rate = -1; 6335 hdspm->last_external_sample_rate = -1; 6336 hdspm->last_internal_sample_rate = -1; 6337 hdspm->playback_pid = -1; 6338 hdspm->capture_pid = -1; 6339 hdspm->capture_substream = NULL; 6340 hdspm->playback_substream = NULL; 6341 6342 snd_printdd("Set defaults...\n"); 6343 err = snd_hdspm_set_defaults(hdspm); 6344 if (err < 0) 6345 return err; 6346 6347 snd_printdd("Update mixer controls...\n"); 6348 hdspm_update_simple_mixer_controls(hdspm); 6349 6350 snd_printdd("Initializeing complete ???\n"); 6351 6352 err = snd_card_register(card); 6353 if (err < 0) { 6354 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6355 return err; 6356 } 6357 6358 snd_printdd("... yes now\n"); 6359 6360 return 0; 6361 } 6362 6363 static int __devinit snd_hdspm_create(struct snd_card *card, 6364 struct hdspm *hdspm) { 6365 6366 struct pci_dev *pci = hdspm->pci; 6367 int err; 6368 unsigned long io_extent; 6369 6370 hdspm->irq = -1; 6371 hdspm->card = card; 6372 6373 spin_lock_init(&hdspm->lock); 6374 6375 pci_read_config_word(hdspm->pci, 6376 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6377 6378 strcpy(card->mixername, "Xilinx FPGA"); 6379 strcpy(card->driver, "HDSPM"); 6380 6381 switch (hdspm->firmware_rev) { 6382 case HDSPM_MADI_REV: 6383 case HDSPM_MADI_OLD_REV: 6384 hdspm->io_type = MADI; 6385 hdspm->card_name = "RME MADI"; 6386 hdspm->midiPorts = 3; 6387 break; 6388 case HDSPM_RAYDAT_REV: 6389 hdspm->io_type = RayDAT; 6390 hdspm->card_name = "RME RayDAT"; 6391 hdspm->midiPorts = 2; 6392 break; 6393 case HDSPM_AIO_REV: 6394 hdspm->io_type = AIO; 6395 hdspm->card_name = "RME AIO"; 6396 hdspm->midiPorts = 1; 6397 break; 6398 case HDSPM_MADIFACE_REV: 6399 hdspm->io_type = MADIface; 6400 hdspm->card_name = "RME MADIface"; 6401 hdspm->midiPorts = 1; 6402 break; 6403 case HDSPM_AES_REV: 6404 case HDSPM_AES32_REV: 6405 case HDSPM_AES32_OLD_REV: 6406 hdspm->io_type = AES32; 6407 hdspm->card_name = "RME AES32"; 6408 hdspm->midiPorts = 2; 6409 break; 6410 default: 6411 snd_printk(KERN_ERR "HDSPM: unknown firmware revision %x\n", 6412 hdspm->firmware_rev); 6413 return -ENODEV; 6414 } 6415 6416 err = pci_enable_device(pci); 6417 if (err < 0) 6418 return err; 6419 6420 pci_set_master(hdspm->pci); 6421 6422 err = pci_request_regions(pci, "hdspm"); 6423 if (err < 0) 6424 return err; 6425 6426 hdspm->port = pci_resource_start(pci, 0); 6427 io_extent = pci_resource_len(pci, 0); 6428 6429 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6430 hdspm->port, hdspm->port + io_extent - 1); 6431 6432 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6433 if (!hdspm->iobase) { 6434 snd_printk(KERN_ERR "HDSPM: " 6435 "unable to remap region 0x%lx-0x%lx\n", 6436 hdspm->port, hdspm->port + io_extent - 1); 6437 return -EBUSY; 6438 } 6439 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6440 (unsigned long)hdspm->iobase, hdspm->port, 6441 hdspm->port + io_extent - 1); 6442 6443 if (request_irq(pci->irq, snd_hdspm_interrupt, 6444 IRQF_SHARED, "hdspm", hdspm)) { 6445 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6446 return -EBUSY; 6447 } 6448 6449 snd_printdd("use IRQ %d\n", pci->irq); 6450 6451 hdspm->irq = pci->irq; 6452 6453 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6454 sizeof(struct hdspm_mixer)); 6455 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6456 if (!hdspm->mixer) { 6457 snd_printk(KERN_ERR "HDSPM: " 6458 "unable to kmalloc Mixer memory of %d Bytes\n", 6459 (int)sizeof(struct hdspm_mixer)); 6460 return err; 6461 } 6462 6463 hdspm->port_names_in = NULL; 6464 hdspm->port_names_out = NULL; 6465 6466 switch (hdspm->io_type) { 6467 case AES32: 6468 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6469 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6470 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6471 6472 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6473 channel_map_aes32; 6474 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6475 channel_map_aes32; 6476 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6477 channel_map_aes32; 6478 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6479 texts_ports_aes32; 6480 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6481 texts_ports_aes32; 6482 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6483 texts_ports_aes32; 6484 6485 hdspm->max_channels_out = hdspm->max_channels_in = 6486 AES32_CHANNELS; 6487 hdspm->port_names_in = hdspm->port_names_out = 6488 texts_ports_aes32; 6489 hdspm->channel_map_in = hdspm->channel_map_out = 6490 channel_map_aes32; 6491 6492 break; 6493 6494 case MADI: 6495 case MADIface: 6496 hdspm->ss_in_channels = hdspm->ss_out_channels = 6497 MADI_SS_CHANNELS; 6498 hdspm->ds_in_channels = hdspm->ds_out_channels = 6499 MADI_DS_CHANNELS; 6500 hdspm->qs_in_channels = hdspm->qs_out_channels = 6501 MADI_QS_CHANNELS; 6502 6503 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6504 channel_map_unity_ss; 6505 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6506 channel_map_unity_ss; 6507 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6508 channel_map_unity_ss; 6509 6510 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6511 texts_ports_madi; 6512 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6513 texts_ports_madi; 6514 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6515 texts_ports_madi; 6516 break; 6517 6518 case AIO: 6519 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6520 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6521 } 6522 6523 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6524 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6525 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6526 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6527 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6528 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6529 6530 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6531 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6532 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6533 6534 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6535 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6536 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6537 6538 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6539 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6540 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6541 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6542 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6543 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6544 6545 break; 6546 6547 case RayDAT: 6548 hdspm->ss_in_channels = hdspm->ss_out_channels = 6549 RAYDAT_SS_CHANNELS; 6550 hdspm->ds_in_channels = hdspm->ds_out_channels = 6551 RAYDAT_DS_CHANNELS; 6552 hdspm->qs_in_channels = hdspm->qs_out_channels = 6553 RAYDAT_QS_CHANNELS; 6554 6555 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6556 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6557 6558 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6559 channel_map_raydat_ss; 6560 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6561 channel_map_raydat_ds; 6562 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6563 channel_map_raydat_qs; 6564 hdspm->channel_map_in = hdspm->channel_map_out = 6565 channel_map_raydat_ss; 6566 6567 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6568 texts_ports_raydat_ss; 6569 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6570 texts_ports_raydat_ds; 6571 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6572 texts_ports_raydat_qs; 6573 6574 6575 break; 6576 6577 } 6578 6579 /* TCO detection */ 6580 switch (hdspm->io_type) { 6581 case AIO: 6582 case RayDAT: 6583 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6584 HDSPM_s2_tco_detect) { 6585 hdspm->midiPorts++; 6586 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6587 GFP_KERNEL); 6588 if (NULL != hdspm->tco) { 6589 hdspm_tco_write(hdspm); 6590 } 6591 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6592 } else { 6593 hdspm->tco = NULL; 6594 } 6595 break; 6596 6597 case MADI: 6598 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6599 hdspm->midiPorts++; 6600 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6601 GFP_KERNEL); 6602 if (NULL != hdspm->tco) { 6603 hdspm_tco_write(hdspm); 6604 } 6605 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6606 } else { 6607 hdspm->tco = NULL; 6608 } 6609 break; 6610 6611 default: 6612 hdspm->tco = NULL; 6613 } 6614 6615 /* texts */ 6616 switch (hdspm->io_type) { 6617 case AES32: 6618 if (hdspm->tco) { 6619 hdspm->texts_autosync = texts_autosync_aes_tco; 6620 hdspm->texts_autosync_items = 10; 6621 } else { 6622 hdspm->texts_autosync = texts_autosync_aes; 6623 hdspm->texts_autosync_items = 9; 6624 } 6625 break; 6626 6627 case MADI: 6628 if (hdspm->tco) { 6629 hdspm->texts_autosync = texts_autosync_madi_tco; 6630 hdspm->texts_autosync_items = 4; 6631 } else { 6632 hdspm->texts_autosync = texts_autosync_madi; 6633 hdspm->texts_autosync_items = 3; 6634 } 6635 break; 6636 6637 case MADIface: 6638 6639 break; 6640 6641 case RayDAT: 6642 if (hdspm->tco) { 6643 hdspm->texts_autosync = texts_autosync_raydat_tco; 6644 hdspm->texts_autosync_items = 9; 6645 } else { 6646 hdspm->texts_autosync = texts_autosync_raydat; 6647 hdspm->texts_autosync_items = 8; 6648 } 6649 break; 6650 6651 case AIO: 6652 if (hdspm->tco) { 6653 hdspm->texts_autosync = texts_autosync_aio_tco; 6654 hdspm->texts_autosync_items = 6; 6655 } else { 6656 hdspm->texts_autosync = texts_autosync_aio; 6657 hdspm->texts_autosync_items = 5; 6658 } 6659 break; 6660 6661 } 6662 6663 tasklet_init(&hdspm->midi_tasklet, 6664 hdspm_midi_tasklet, (unsigned long) hdspm); 6665 6666 snd_printdd("create alsa devices.\n"); 6667 err = snd_hdspm_create_alsa_devices(card, hdspm); 6668 if (err < 0) 6669 return err; 6670 6671 snd_hdspm_initialize_midi_flush(hdspm); 6672 6673 return 0; 6674 } 6675 6676 6677 static int snd_hdspm_free(struct hdspm * hdspm) 6678 { 6679 6680 if (hdspm->port) { 6681 6682 /* stop th audio, and cancel all interrupts */ 6683 hdspm->control_register &= 6684 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6685 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6686 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6687 hdspm_write(hdspm, HDSPM_controlRegister, 6688 hdspm->control_register); 6689 } 6690 6691 if (hdspm->irq >= 0) 6692 free_irq(hdspm->irq, (void *) hdspm); 6693 6694 kfree(hdspm->mixer); 6695 6696 if (hdspm->iobase) 6697 iounmap(hdspm->iobase); 6698 6699 if (hdspm->port) 6700 pci_release_regions(hdspm->pci); 6701 6702 pci_disable_device(hdspm->pci); 6703 return 0; 6704 } 6705 6706 6707 static void snd_hdspm_card_free(struct snd_card *card) 6708 { 6709 struct hdspm *hdspm = card->private_data; 6710 6711 if (hdspm) 6712 snd_hdspm_free(hdspm); 6713 } 6714 6715 6716 static int __devinit snd_hdspm_probe(struct pci_dev *pci, 6717 const struct pci_device_id *pci_id) 6718 { 6719 static int dev; 6720 struct hdspm *hdspm; 6721 struct snd_card *card; 6722 int err; 6723 6724 if (dev >= SNDRV_CARDS) 6725 return -ENODEV; 6726 if (!enable[dev]) { 6727 dev++; 6728 return -ENOENT; 6729 } 6730 6731 err = snd_card_create(index[dev], id[dev], 6732 THIS_MODULE, sizeof(struct hdspm), &card); 6733 if (err < 0) 6734 return err; 6735 6736 hdspm = card->private_data; 6737 card->private_free = snd_hdspm_card_free; 6738 hdspm->dev = dev; 6739 hdspm->pci = pci; 6740 6741 snd_card_set_dev(card, &pci->dev); 6742 6743 err = snd_hdspm_create(card, hdspm); 6744 if (err < 0) { 6745 snd_card_free(card); 6746 return err; 6747 } 6748 6749 if (hdspm->io_type != MADIface) { 6750 sprintf(card->shortname, "%s_%x", 6751 hdspm->card_name, 6752 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF); 6753 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6754 hdspm->card_name, 6755 (hdspm_read(hdspm, HDSPM_midiStatusIn0)>>8) & 0xFFFFFF, 6756 hdspm->port, hdspm->irq); 6757 } else { 6758 sprintf(card->shortname, "%s", hdspm->card_name); 6759 sprintf(card->longname, "%s at 0x%lx, irq %d", 6760 hdspm->card_name, hdspm->port, hdspm->irq); 6761 } 6762 6763 err = snd_card_register(card); 6764 if (err < 0) { 6765 snd_card_free(card); 6766 return err; 6767 } 6768 6769 pci_set_drvdata(pci, card); 6770 6771 dev++; 6772 return 0; 6773 } 6774 6775 static void __devexit snd_hdspm_remove(struct pci_dev *pci) 6776 { 6777 snd_card_free(pci_get_drvdata(pci)); 6778 pci_set_drvdata(pci, NULL); 6779 } 6780 6781 static struct pci_driver driver = { 6782 .name = "RME Hammerfall DSP MADI", 6783 .id_table = snd_hdspm_ids, 6784 .probe = snd_hdspm_probe, 6785 .remove = __devexit_p(snd_hdspm_remove), 6786 }; 6787 6788 6789 static int __init alsa_card_hdspm_init(void) 6790 { 6791 return pci_register_driver(&driver); 6792 } 6793 6794 static void __exit alsa_card_hdspm_exit(void) 6795 { 6796 pci_unregister_driver(&driver); 6797 } 6798 6799 module_init(alsa_card_hdspm_init) 6800 module_exit(alsa_card_hdspm_exit) 6801