1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * Modified 2019-05-23 fix AIO single speed ADAT capture and playback 27 * by Philippe.Bekaert@uhasselt.be 28 * 29 * This program is free software; you can redistribute it and/or modify 30 * it under the terms of the GNU General Public License as published by 31 * the Free Software Foundation; either version 2 of the License, or 32 * (at your option) any later version. 33 * 34 * This program is distributed in the hope that it will be useful, 35 * but WITHOUT ANY WARRANTY; without even the implied warranty of 36 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 37 * GNU General Public License for more details. 38 * 39 * You should have received a copy of the GNU General Public License 40 * along with this program; if not, write to the Free Software 41 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 42 * 43 */ 44 45 /* ************* Register Documentation ******************************************************* 46 * 47 * Work in progress! Documentation is based on the code in this file. 48 * 49 * --------- HDSPM_controlRegister --------- 50 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 51 * :||||.||||:||||.||||:||||.||||:||||.||||: 52 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 53 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 54 * :||||.||||:||||.||||:||||.||||:||||.||||: 55 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 56 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits 57 * : . : . : . : . x: HDSPM_Start / enables audio IO 58 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave 59 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency 60 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512, 61 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192 62 * :x . : . : . x:xx . : HDSPM_FrequencyMask 63 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=?? 64 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed 65 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed 66 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask : 67 * : . : . x: . : . : HDSPM_SyncRef0 68 * : . : . x : . : . : HDSPM_SyncRef1 69 * : . : . : x . : . : <AES32> HDSPM_SyncRef2 70 * : . x : . : . : . : <AES32> HDSPM_SyncRef3 71 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn 72 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn? 73 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT 74 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax 75 * : . : . :x . : . : <MADI> HDSPM_InputSelect1 76 * : . : .x : . : . : <MADI> HDSPM_clr_tms 77 * : . : . : . x : . : <MADI> HDSPM_TX_64ch 78 * : . : . : . x : . : <AES32> HDSPM_Emphasis 79 * : . : . : .x : . : <MADI> HDSPM_AutoInp 80 * : . : . x : . : . : <MADI> HDSPM_SMUX 81 * : . : .x : . : . : <MADI> HDSPM_clr_tms 82 * : . : x. : . : . : <MADI> HDSPM_taxi_reset 83 * : . x: . : . : . : <MADI> HDSPM_LineOut 84 * : . x: . : . : . : <AES32> ?????????????????? 85 * : . : x. : . : . : <AES32> HDSPM_WCK48 86 * : . : . : .x : . : <AES32> HDSPM_Dolby 87 * : . : x . : . : . : HDSPM_Midi0InterruptEnable 88 * : . :x . : . : . : HDSPM_Midi1InterruptEnable 89 * : . : x . : . : . : HDSPM_Midi2InterruptEnable 90 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable 91 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire 92 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire 93 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire 94 * : . : . : . x : . : <AES32> HDSPM_Professional 95 * : x . : . : . : . : HDSPM_wclk_sel 96 * : . : . : . : . : 97 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte 98 * :||||.||||:||||.||||:||||.||||:||||.||||: 99 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number 100 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31 101 * :||||.||||:||||.||||:||||.||||:||||.||||: 102 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit 103 * 104 * 105 * 106 * AIO / RayDAT only 107 * 108 * ------------ HDSPM_WR_SETTINGS ---------- 109 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 110 * :1098.7654:3210.9876:5432.1098:7654.3210: 111 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 112 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 113 * :||||.||||:||||.||||:||||.||||:||||.||||: 114 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 115 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave 116 * : . : . : . : . x : HDSPM_c0_SyncRef0 117 * : . : . : . : . x : HDSPM_c0_SyncRef1 118 * : . : . : . : .x : HDSPM_c0_SyncRef2 119 * : . : . : . : x. : HDSPM_c0_SyncRef3 120 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask: 121 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4, 122 * : . : . : . : . : 9:TCO, 10:SyncIn 123 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT, 124 * : . : . : . : . : 9:TCO, 10:SyncIn 125 * : . : . : . : . : 126 * : . : . : . : . : 127 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte 128 * :1098.7654:3210.9876:5432.1098:7654.3210: 129 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number 130 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31 131 * :||||.||||:||||.||||:||||.||||:||||.||||: 132 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit 133 * 134 */ 135 #include <linux/init.h> 136 #include <linux/delay.h> 137 #include <linux/interrupt.h> 138 #include <linux/module.h> 139 #include <linux/slab.h> 140 #include <linux/pci.h> 141 #include <linux/math64.h> 142 #include <linux/io.h> 143 #include <linux/nospec.h> 144 145 #include <sound/core.h> 146 #include <sound/control.h> 147 #include <sound/pcm.h> 148 #include <sound/pcm_params.h> 149 #include <sound/info.h> 150 #include <sound/asoundef.h> 151 #include <sound/rawmidi.h> 152 #include <sound/hwdep.h> 153 #include <sound/initval.h> 154 155 #include <sound/hdspm.h> 156 157 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 158 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 159 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 160 161 module_param_array(index, int, NULL, 0444); 162 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 163 164 module_param_array(id, charp, NULL, 0444); 165 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 166 167 module_param_array(enable, bool, NULL, 0444); 168 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 169 170 171 MODULE_AUTHOR 172 ( 173 "Winfried Ritsch <ritsch_AT_iem.at>, " 174 "Paul Davis <paul@linuxaudiosystems.com>, " 175 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 176 "Remy Bruno <remy.bruno@trinnov.com>, " 177 "Florian Faber <faberman@linuxproaudio.org>, " 178 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 179 ); 180 MODULE_DESCRIPTION("RME HDSPM"); 181 MODULE_LICENSE("GPL"); 182 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 183 184 /* --- Write registers. --- 185 These are defined as byte-offsets from the iobase value. */ 186 187 #define HDSPM_WR_SETTINGS 0 188 #define HDSPM_outputBufferAddress 32 189 #define HDSPM_inputBufferAddress 36 190 #define HDSPM_controlRegister 64 191 #define HDSPM_interruptConfirmation 96 192 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 193 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */ 194 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 195 #define HDSPM_midiDataOut1 356 196 #define HDSPM_eeprom_wr 384 /* for AES32 */ 197 198 /* DMA enable for 64 channels, only Bit 0 is relevant */ 199 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 200 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 201 202 /* 16 page addresses for each of the 64 channels DMA buffer in and out 203 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 204 #define HDSPM_pageAddressBufferOut 8192 205 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 206 207 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 208 209 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 210 211 /* --- Read registers. --- 212 These are defined as byte-offsets from the iobase value */ 213 #define HDSPM_statusRegister 0 214 /*#define HDSPM_statusRegister2 96 */ 215 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 216 * offset 192, for AES32 *and* MADI 217 * => need to check that offset 192 is working on MADI */ 218 #define HDSPM_statusRegister2 192 219 #define HDSPM_timecodeRegister 128 220 221 /* AIO, RayDAT */ 222 #define HDSPM_RD_STATUS_0 0 223 #define HDSPM_RD_STATUS_1 64 224 #define HDSPM_RD_STATUS_2 128 225 #define HDSPM_RD_STATUS_3 192 226 227 #define HDSPM_RD_TCO 256 228 #define HDSPM_RD_PLL_FREQ 512 229 #define HDSPM_WR_TCO 128 230 231 #define HDSPM_TCO1_TCO_lock 0x00000001 232 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 233 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 234 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 235 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 236 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 237 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 238 239 #define HDSPM_TCO1_set_TC 0x00000100 240 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 241 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 242 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 243 244 #define HDSPM_TCO2_TC_run 0x00010000 245 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 246 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 247 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 248 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 249 #define HDSPM_TCO2_set_jam_sync 0x00200000 250 #define HDSPM_TCO2_set_flywheel 0x00400000 251 252 #define HDSPM_TCO2_set_01_4 0x01000000 253 #define HDSPM_TCO2_set_pull_down 0x02000000 254 #define HDSPM_TCO2_set_pull_up 0x04000000 255 #define HDSPM_TCO2_set_freq 0x08000000 256 #define HDSPM_TCO2_set_term_75R 0x10000000 257 #define HDSPM_TCO2_set_input_LSB 0x20000000 258 #define HDSPM_TCO2_set_input_MSB 0x40000000 259 #define HDSPM_TCO2_set_freq_from_app 0x80000000 260 261 262 #define HDSPM_midiDataOut0 352 263 #define HDSPM_midiDataOut1 356 264 #define HDSPM_midiDataOut2 368 265 266 #define HDSPM_midiDataIn0 360 267 #define HDSPM_midiDataIn1 364 268 #define HDSPM_midiDataIn2 372 269 #define HDSPM_midiDataIn3 376 270 271 /* status is data bytes in MIDI-FIFO (0-128) */ 272 #define HDSPM_midiStatusOut0 384 273 #define HDSPM_midiStatusOut1 388 274 #define HDSPM_midiStatusOut2 400 275 276 #define HDSPM_midiStatusIn0 392 277 #define HDSPM_midiStatusIn1 396 278 #define HDSPM_midiStatusIn2 404 279 #define HDSPM_midiStatusIn3 408 280 281 282 /* the meters are regular i/o-mapped registers, but offset 283 considerably from the rest. the peak registers are reset 284 when read; the least-significant 4 bits are full-scale counters; 285 the actual peak value is in the most-significant 24 bits. 286 */ 287 288 #define HDSPM_MADI_INPUT_PEAK 4096 289 #define HDSPM_MADI_PLAYBACK_PEAK 4352 290 #define HDSPM_MADI_OUTPUT_PEAK 4608 291 292 #define HDSPM_MADI_INPUT_RMS_L 6144 293 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 294 #define HDSPM_MADI_OUTPUT_RMS_L 6656 295 296 #define HDSPM_MADI_INPUT_RMS_H 7168 297 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 298 #define HDSPM_MADI_OUTPUT_RMS_H 7680 299 300 /* --- Control Register bits --------- */ 301 #define HDSPM_Start (1<<0) /* start engine */ 302 303 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 304 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 305 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 306 307 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 308 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 309 register [RayDAT, AIO] */ 310 311 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 312 313 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 314 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 315 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 316 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 317 318 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 319 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 320 56channelMODE=0 */ /* MADI ONLY*/ 321 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 322 323 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 324 0=off, 1=on */ /* MADI ONLY */ 325 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 326 327 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 328 * -- MADI ONLY 329 */ 330 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 331 332 #define HDSPM_SyncRef2 (1<<13) 333 #define HDSPM_SyncRef3 (1<<25) 334 335 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 336 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 337 AES additional bits in 338 lower 5 Audiodatabits ??? */ 339 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 340 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 341 342 #define HDSPM_Midi0InterruptEnable 0x0400000 343 #define HDSPM_Midi1InterruptEnable 0x0800000 344 #define HDSPM_Midi2InterruptEnable 0x0200000 345 #define HDSPM_Midi3InterruptEnable 0x4000000 346 347 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 348 #define HDSPe_FLOAT_FORMAT 0x2000000 349 350 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 351 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 352 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 353 354 #define HDSPM_wclk_sel (1<<30) 355 356 /* additional control register bits for AIO*/ 357 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */ 358 #define HDSPM_c0_Input0 0x1000 359 #define HDSPM_c0_Input1 0x2000 360 #define HDSPM_c0_Spdif_Opt 0x4000 361 #define HDSPM_c0_Pro 0x8000 362 #define HDSPM_c0_clr_tms 0x10000 363 #define HDSPM_c0_AEB1 0x20000 364 #define HDSPM_c0_AEB2 0x40000 365 #define HDSPM_c0_LineOut 0x80000 366 #define HDSPM_c0_AD_GAIN0 0x100000 367 #define HDSPM_c0_AD_GAIN1 0x200000 368 #define HDSPM_c0_DA_GAIN0 0x400000 369 #define HDSPM_c0_DA_GAIN1 0x800000 370 #define HDSPM_c0_PH_GAIN0 0x1000000 371 #define HDSPM_c0_PH_GAIN1 0x2000000 372 #define HDSPM_c0_Sym6db 0x4000000 373 374 375 /* --- bit helper defines */ 376 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 377 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 378 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 379 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 380 #define HDSPM_InputOptical 0 381 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 382 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 383 HDSPM_SyncRef2|HDSPM_SyncRef3) 384 385 #define HDSPM_c0_SyncRef0 0x2 386 #define HDSPM_c0_SyncRef1 0x4 387 #define HDSPM_c0_SyncRef2 0x8 388 #define HDSPM_c0_SyncRef3 0x10 389 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 390 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 391 392 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 393 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 394 #define HDSPM_SYNC_FROM_TCO 2 395 #define HDSPM_SYNC_FROM_SYNC_IN 3 396 397 #define HDSPM_Frequency32KHz HDSPM_Frequency0 398 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 399 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 400 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 401 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 402 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 403 HDSPM_Frequency0) 404 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 405 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 406 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 407 HDSPM_Frequency0) 408 409 410 /* Synccheck Status */ 411 #define HDSPM_SYNC_CHECK_NO_LOCK 0 412 #define HDSPM_SYNC_CHECK_LOCK 1 413 #define HDSPM_SYNC_CHECK_SYNC 2 414 415 /* AutoSync References - used by "autosync_ref" control switch */ 416 #define HDSPM_AUTOSYNC_FROM_WORD 0 417 #define HDSPM_AUTOSYNC_FROM_MADI 1 418 #define HDSPM_AUTOSYNC_FROM_TCO 2 419 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 420 #define HDSPM_AUTOSYNC_FROM_NONE 4 421 422 /* Possible sources of MADI input */ 423 #define HDSPM_OPTICAL 0 /* optical */ 424 #define HDSPM_COAXIAL 1 /* BNC */ 425 426 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 427 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 428 429 #define hdspm_encode_in(x) (((x)&0x3)<<14) 430 #define hdspm_decode_in(x) (((x)>>14)&0x3) 431 432 /* --- control2 register bits --- */ 433 #define HDSPM_TMS (1<<0) 434 #define HDSPM_TCK (1<<1) 435 #define HDSPM_TDI (1<<2) 436 #define HDSPM_JTAG (1<<3) 437 #define HDSPM_PWDN (1<<4) 438 #define HDSPM_PROGRAM (1<<5) 439 #define HDSPM_CONFIG_MODE_0 (1<<6) 440 #define HDSPM_CONFIG_MODE_1 (1<<7) 441 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 442 #define HDSPM_BIGENDIAN_MODE (1<<9) 443 #define HDSPM_RD_MULTIPLE (1<<10) 444 445 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 446 that do not conflict with specific bits for AES32 seem to be valid also 447 for the AES32 448 */ 449 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 450 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 451 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 452 * (like inp0) 453 */ 454 455 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 456 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 457 458 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/ 459 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/ 460 461 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */ 462 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */ 463 464 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 465 /* since 64byte accurate, last 6 bits are not used */ 466 467 468 469 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 470 471 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 472 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 473 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 474 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 475 476 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 477 * Interrupt 478 */ 479 #define HDSPM_tco_detect 0x08000000 480 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */ 481 482 #define HDSPM_s2_tco_detect 0x00000040 483 #define HDSPM_s2_AEBO_D 0x00000080 484 #define HDSPM_s2_AEBI_D 0x00000100 485 486 487 #define HDSPM_midi0IRQPending 0x40000000 488 #define HDSPM_midi1IRQPending 0x80000000 489 #define HDSPM_midi2IRQPending 0x20000000 490 #define HDSPM_midi2IRQPendingAES 0x00000020 491 #define HDSPM_midi3IRQPending 0x00200000 492 493 /* --- status bit helpers */ 494 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 495 HDSPM_madiFreq2|HDSPM_madiFreq3) 496 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 497 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 498 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 499 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 500 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 501 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 502 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 503 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 504 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 505 506 /* Status2 Register bits */ /* MADI ONLY */ 507 508 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 509 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 510 #define HDSPM_version2 (1<<2) 511 512 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 513 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 514 515 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 516 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 517 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */ 518 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */ 519 520 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 521 #define HDSPM_SyncRef1 0x20000 522 523 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 524 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 525 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 526 527 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 528 529 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\ 530 HDSPM_wc_freq3) 531 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 532 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 533 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 534 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 535 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 536 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 537 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 538 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3) 539 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3) 540 541 #define HDSPM_status1_F_0 0x0400000 542 #define HDSPM_status1_F_1 0x0800000 543 #define HDSPM_status1_F_2 0x1000000 544 #define HDSPM_status1_F_3 0x2000000 545 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 546 547 548 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 549 HDSPM_SelSyncRef2) 550 #define HDSPM_SelSyncRef_WORD 0 551 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 552 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 553 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 554 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 555 HDSPM_SelSyncRef2) 556 557 /* 558 For AES32, bits for status, status2 and timecode are different 559 */ 560 /* status */ 561 #define HDSPM_AES32_wcLock 0x0200000 562 #define HDSPM_AES32_wcSync 0x0100000 563 #define HDSPM_AES32_wcFreq_bit 22 564 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 565 HDSPM_bit2freq */ 566 #define HDSPM_AES32_syncref_bit 16 567 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 568 569 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 570 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 571 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 572 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 573 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 574 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 575 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 576 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 577 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 578 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9 579 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10 580 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11 581 582 /* status2 */ 583 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 584 #define HDSPM_LockAES 0x80 585 #define HDSPM_LockAES1 0x80 586 #define HDSPM_LockAES2 0x40 587 #define HDSPM_LockAES3 0x20 588 #define HDSPM_LockAES4 0x10 589 #define HDSPM_LockAES5 0x8 590 #define HDSPM_LockAES6 0x4 591 #define HDSPM_LockAES7 0x2 592 #define HDSPM_LockAES8 0x1 593 /* 594 Timecode 595 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 596 AES i+1 597 bits 3210 598 0001 32kHz 599 0010 44.1kHz 600 0011 48kHz 601 0100 64kHz 602 0101 88.2kHz 603 0110 96kHz 604 0111 128kHz 605 1000 176.4kHz 606 1001 192kHz 607 NB: Timecode register doesn't seem to work on AES32 card revision 230 608 */ 609 610 /* Mixer Values */ 611 #define UNITY_GAIN 32768 /* = 65536/2 */ 612 #define MINUS_INFINITY_GAIN 0 613 614 /* Number of channels for different Speed Modes */ 615 #define MADI_SS_CHANNELS 64 616 #define MADI_DS_CHANNELS 32 617 #define MADI_QS_CHANNELS 16 618 619 #define RAYDAT_SS_CHANNELS 36 620 #define RAYDAT_DS_CHANNELS 20 621 #define RAYDAT_QS_CHANNELS 12 622 623 #define AIO_IN_SS_CHANNELS 14 624 #define AIO_IN_DS_CHANNELS 10 625 #define AIO_IN_QS_CHANNELS 8 626 #define AIO_OUT_SS_CHANNELS 16 627 #define AIO_OUT_DS_CHANNELS 12 628 #define AIO_OUT_QS_CHANNELS 10 629 630 #define AES32_CHANNELS 16 631 632 /* the size of a substream (1 mono data stream) */ 633 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 634 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 635 636 /* the size of the area we need to allocate for DMA transfers. the 637 size is the same regardless of the number of channels, and 638 also the latency to use. 639 for one direction !!! 640 */ 641 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 642 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 643 644 #define HDSPM_RAYDAT_REV 211 645 #define HDSPM_AIO_REV 212 646 #define HDSPM_MADIFACE_REV 213 647 648 /* speed factor modes */ 649 #define HDSPM_SPEED_SINGLE 0 650 #define HDSPM_SPEED_DOUBLE 1 651 #define HDSPM_SPEED_QUAD 2 652 653 /* names for speed modes */ 654 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 655 656 static const char *const texts_autosync_aes_tco[] = { "Word Clock", 657 "AES1", "AES2", "AES3", "AES4", 658 "AES5", "AES6", "AES7", "AES8", 659 "TCO", "Sync In" 660 }; 661 static const char *const texts_autosync_aes[] = { "Word Clock", 662 "AES1", "AES2", "AES3", "AES4", 663 "AES5", "AES6", "AES7", "AES8", 664 "Sync In" 665 }; 666 static const char *const texts_autosync_madi_tco[] = { "Word Clock", 667 "MADI", "TCO", "Sync In" }; 668 static const char *const texts_autosync_madi[] = { "Word Clock", 669 "MADI", "Sync In" }; 670 671 static const char *const texts_autosync_raydat_tco[] = { 672 "Word Clock", 673 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 674 "AES", "SPDIF", "TCO", "Sync In" 675 }; 676 static const char *const texts_autosync_raydat[] = { 677 "Word Clock", 678 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 679 "AES", "SPDIF", "Sync In" 680 }; 681 static const char *const texts_autosync_aio_tco[] = { 682 "Word Clock", 683 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 684 }; 685 static const char *const texts_autosync_aio[] = { "Word Clock", 686 "ADAT", "AES", "SPDIF", "Sync In" }; 687 688 static const char *const texts_freq[] = { 689 "No Lock", 690 "32 kHz", 691 "44.1 kHz", 692 "48 kHz", 693 "64 kHz", 694 "88.2 kHz", 695 "96 kHz", 696 "128 kHz", 697 "176.4 kHz", 698 "192 kHz" 699 }; 700 701 static char *texts_ports_madi[] = { 702 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 703 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 704 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 705 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 706 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 707 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 708 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 709 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 710 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 711 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 712 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 713 }; 714 715 716 static char *texts_ports_raydat_ss[] = { 717 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 718 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 719 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 720 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 721 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 722 "ADAT4.7", "ADAT4.8", 723 "AES.L", "AES.R", 724 "SPDIF.L", "SPDIF.R" 725 }; 726 727 static char *texts_ports_raydat_ds[] = { 728 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 729 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 730 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 731 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 732 "AES.L", "AES.R", 733 "SPDIF.L", "SPDIF.R" 734 }; 735 736 static char *texts_ports_raydat_qs[] = { 737 "ADAT1.1", "ADAT1.2", 738 "ADAT2.1", "ADAT2.2", 739 "ADAT3.1", "ADAT3.2", 740 "ADAT4.1", "ADAT4.2", 741 "AES.L", "AES.R", 742 "SPDIF.L", "SPDIF.R" 743 }; 744 745 746 static char *texts_ports_aio_in_ss[] = { 747 "Analogue.L", "Analogue.R", 748 "AES.L", "AES.R", 749 "SPDIF.L", "SPDIF.R", 750 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 751 "ADAT.7", "ADAT.8", 752 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 753 }; 754 755 static char *texts_ports_aio_out_ss[] = { 756 "Analogue.L", "Analogue.R", 757 "AES.L", "AES.R", 758 "SPDIF.L", "SPDIF.R", 759 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 760 "ADAT.7", "ADAT.8", 761 "Phone.L", "Phone.R", 762 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 763 }; 764 765 static char *texts_ports_aio_in_ds[] = { 766 "Analogue.L", "Analogue.R", 767 "AES.L", "AES.R", 768 "SPDIF.L", "SPDIF.R", 769 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 770 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 771 }; 772 773 static char *texts_ports_aio_out_ds[] = { 774 "Analogue.L", "Analogue.R", 775 "AES.L", "AES.R", 776 "SPDIF.L", "SPDIF.R", 777 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 778 "Phone.L", "Phone.R", 779 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 780 }; 781 782 static char *texts_ports_aio_in_qs[] = { 783 "Analogue.L", "Analogue.R", 784 "AES.L", "AES.R", 785 "SPDIF.L", "SPDIF.R", 786 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 787 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 788 }; 789 790 static char *texts_ports_aio_out_qs[] = { 791 "Analogue.L", "Analogue.R", 792 "AES.L", "AES.R", 793 "SPDIF.L", "SPDIF.R", 794 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 795 "Phone.L", "Phone.R", 796 "AEB.1", "AEB.2", "AEB.3", "AEB.4" 797 }; 798 799 static char *texts_ports_aes32[] = { 800 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 801 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 802 "AES.15", "AES.16" 803 }; 804 805 /* These tables map the ALSA channels 1..N to the channels that we 806 need to use in order to find the relevant channel buffer. RME 807 refers to this kind of mapping as between "the ADAT channel and 808 the DMA channel." We index it using the logical audio channel, 809 and the value is the DMA channel (i.e. channel buffer number) 810 where the data for that channel can be read/written from/to. 811 */ 812 813 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 814 0, 1, 2, 3, 4, 5, 6, 7, 815 8, 9, 10, 11, 12, 13, 14, 15, 816 16, 17, 18, 19, 20, 21, 22, 23, 817 24, 25, 26, 27, 28, 29, 30, 31, 818 32, 33, 34, 35, 36, 37, 38, 39, 819 40, 41, 42, 43, 44, 45, 46, 47, 820 48, 49, 50, 51, 52, 53, 54, 55, 821 56, 57, 58, 59, 60, 61, 62, 63 822 }; 823 824 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 825 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 826 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 827 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 828 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 829 0, 1, /* AES */ 830 2, 3, /* SPDIF */ 831 -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1, 833 -1, -1, -1, -1, -1, -1, -1, -1, 834 -1, -1, -1, -1, -1, -1, -1, -1, 835 }; 836 837 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 838 4, 5, 6, 7, /* ADAT 1 */ 839 8, 9, 10, 11, /* ADAT 2 */ 840 12, 13, 14, 15, /* ADAT 3 */ 841 16, 17, 18, 19, /* ADAT 4 */ 842 0, 1, /* AES */ 843 2, 3, /* SPDIF */ 844 -1, -1, -1, -1, 845 -1, -1, -1, -1, -1, -1, -1, -1, 846 -1, -1, -1, -1, -1, -1, -1, -1, 847 -1, -1, -1, -1, -1, -1, -1, -1, 848 -1, -1, -1, -1, -1, -1, -1, -1, 849 -1, -1, -1, -1, -1, -1, -1, -1, 850 }; 851 852 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 853 4, 5, /* ADAT 1 */ 854 6, 7, /* ADAT 2 */ 855 8, 9, /* ADAT 3 */ 856 10, 11, /* ADAT 4 */ 857 0, 1, /* AES */ 858 2, 3, /* SPDIF */ 859 -1, -1, -1, -1, 860 -1, -1, -1, -1, -1, -1, -1, -1, 861 -1, -1, -1, -1, -1, -1, -1, -1, 862 -1, -1, -1, -1, -1, -1, -1, -1, 863 -1, -1, -1, -1, -1, -1, -1, -1, 864 -1, -1, -1, -1, -1, -1, -1, -1, 865 -1, -1, -1, -1, -1, -1, -1, -1, 866 }; 867 868 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 869 0, 1, /* line in */ 870 8, 9, /* aes in, */ 871 10, 11, /* spdif in */ 872 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 873 2, 3, 4, 5, /* AEB */ 874 -1, -1, -1, -1, -1, -1, 875 -1, -1, -1, -1, -1, -1, -1, -1, 876 -1, -1, -1, -1, -1, -1, -1, -1, 877 -1, -1, -1, -1, -1, -1, -1, -1, 878 -1, -1, -1, -1, -1, -1, -1, -1, 879 -1, -1, -1, -1, -1, -1, -1, -1, 880 }; 881 882 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 883 0, 1, /* line out */ 884 8, 9, /* aes out */ 885 10, 11, /* spdif out */ 886 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 887 6, 7, /* phone out */ 888 2, 3, 4, 5, /* AEB */ 889 -1, -1, -1, -1, 890 -1, -1, -1, -1, -1, -1, -1, -1, 891 -1, -1, -1, -1, -1, -1, -1, -1, 892 -1, -1, -1, -1, -1, -1, -1, -1, 893 -1, -1, -1, -1, -1, -1, -1, -1, 894 -1, -1, -1, -1, -1, -1, -1, -1, 895 }; 896 897 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 898 0, 1, /* line in */ 899 8, 9, /* aes in */ 900 10, 11, /* spdif in */ 901 12, 14, 16, 18, /* adat in */ 902 2, 3, 4, 5, /* AEB */ 903 -1, -1, 904 -1, -1, -1, -1, -1, -1, -1, -1, 905 -1, -1, -1, -1, -1, -1, -1, -1, 906 -1, -1, -1, -1, -1, -1, -1, -1, 907 -1, -1, -1, -1, -1, -1, -1, -1, 908 -1, -1, -1, -1, -1, -1, -1, -1, 909 -1, -1, -1, -1, -1, -1, -1, -1 910 }; 911 912 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 913 0, 1, /* line out */ 914 8, 9, /* aes out */ 915 10, 11, /* spdif out */ 916 12, 14, 16, 18, /* adat out */ 917 6, 7, /* phone out */ 918 2, 3, 4, 5, /* AEB */ 919 -1, -1, -1, -1, -1, -1, -1, -1, 920 -1, -1, -1, -1, -1, -1, -1, -1, 921 -1, -1, -1, -1, -1, -1, -1, -1, 922 -1, -1, -1, -1, -1, -1, -1, -1, 923 -1, -1, -1, -1, -1, -1, -1, -1, 924 -1, -1, -1, -1, -1, -1, -1, -1 925 }; 926 927 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 928 0, 1, /* line in */ 929 8, 9, /* aes in */ 930 10, 11, /* spdif in */ 931 12, 16, /* adat in */ 932 2, 3, 4, 5, /* AEB */ 933 -1, -1, -1, -1, 934 -1, -1, -1, -1, -1, -1, -1, -1, 935 -1, -1, -1, -1, -1, -1, -1, -1, 936 -1, -1, -1, -1, -1, -1, -1, -1, 937 -1, -1, -1, -1, -1, -1, -1, -1, 938 -1, -1, -1, -1, -1, -1, -1, -1, 939 -1, -1, -1, -1, -1, -1, -1, -1 940 }; 941 942 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 943 0, 1, /* line out */ 944 8, 9, /* aes out */ 945 10, 11, /* spdif out */ 946 12, 16, /* adat out */ 947 6, 7, /* phone out */ 948 2, 3, 4, 5, /* AEB */ 949 -1, -1, 950 -1, -1, -1, -1, -1, -1, -1, -1, 951 -1, -1, -1, -1, -1, -1, -1, -1, 952 -1, -1, -1, -1, -1, -1, -1, -1, 953 -1, -1, -1, -1, -1, -1, -1, -1, 954 -1, -1, -1, -1, -1, -1, -1, -1, 955 -1, -1, -1, -1, -1, -1, -1, -1 956 }; 957 958 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 959 0, 1, 2, 3, 4, 5, 6, 7, 960 8, 9, 10, 11, 12, 13, 14, 15, 961 -1, -1, -1, -1, -1, -1, -1, -1, 962 -1, -1, -1, -1, -1, -1, -1, -1, 963 -1, -1, -1, -1, -1, -1, -1, -1, 964 -1, -1, -1, -1, -1, -1, -1, -1, 965 -1, -1, -1, -1, -1, -1, -1, -1, 966 -1, -1, -1, -1, -1, -1, -1, -1 967 }; 968 969 struct hdspm_midi { 970 struct hdspm *hdspm; 971 int id; 972 struct snd_rawmidi *rmidi; 973 struct snd_rawmidi_substream *input; 974 struct snd_rawmidi_substream *output; 975 char istimer; /* timer in use */ 976 struct timer_list timer; 977 spinlock_t lock; 978 int pending; 979 int dataIn; 980 int statusIn; 981 int dataOut; 982 int statusOut; 983 int ie; 984 int irq; 985 }; 986 987 struct hdspm_tco { 988 int input; /* 0: LTC, 1:Video, 2: WC*/ 989 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */ 990 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */ 991 int samplerate; /* 0=44.1, 1=48, 2= freq from app */ 992 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/ 993 int term; /* 0 = off, 1 = on */ 994 }; 995 996 struct hdspm { 997 spinlock_t lock; 998 /* only one playback and/or capture stream */ 999 struct snd_pcm_substream *capture_substream; 1000 struct snd_pcm_substream *playback_substream; 1001 1002 char *card_name; /* for procinfo */ 1003 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 1004 1005 uint8_t io_type; 1006 1007 int monitor_outs; /* set up monitoring outs init flag */ 1008 1009 u32 control_register; /* cached value */ 1010 u32 control2_register; /* cached value */ 1011 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */ 1012 1013 struct hdspm_midi midi[4]; 1014 struct tasklet_struct midi_tasklet; 1015 1016 size_t period_bytes; 1017 unsigned char ss_in_channels; 1018 unsigned char ds_in_channels; 1019 unsigned char qs_in_channels; 1020 unsigned char ss_out_channels; 1021 unsigned char ds_out_channels; 1022 unsigned char qs_out_channels; 1023 1024 unsigned char max_channels_in; 1025 unsigned char max_channels_out; 1026 1027 signed char *channel_map_in; 1028 signed char *channel_map_out; 1029 1030 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 1031 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 1032 1033 char **port_names_in; 1034 char **port_names_out; 1035 1036 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 1037 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 1038 1039 unsigned char *playback_buffer; /* suitably aligned address */ 1040 unsigned char *capture_buffer; /* suitably aligned address */ 1041 1042 pid_t capture_pid; /* process id which uses capture */ 1043 pid_t playback_pid; /* process id which uses capture */ 1044 int running; /* running status */ 1045 1046 int last_external_sample_rate; /* samplerate mystic ... */ 1047 int last_internal_sample_rate; 1048 int system_sample_rate; 1049 1050 int dev; /* Hardware vars... */ 1051 int irq; 1052 unsigned long port; 1053 void __iomem *iobase; 1054 1055 int irq_count; /* for debug */ 1056 int midiPorts; 1057 1058 struct snd_card *card; /* one card */ 1059 struct snd_pcm *pcm; /* has one pcm */ 1060 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 1061 struct pci_dev *pci; /* and an pci info */ 1062 1063 /* Mixer vars */ 1064 /* fast alsa mixer */ 1065 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 1066 /* but input to much, so not used */ 1067 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 1068 /* full mixer accessible over mixer ioctl or hwdep-device */ 1069 struct hdspm_mixer *mixer; 1070 1071 struct hdspm_tco *tco; /* NULL if no TCO detected */ 1072 1073 const char *const *texts_autosync; 1074 int texts_autosync_items; 1075 1076 cycles_t last_interrupt; 1077 1078 unsigned int serial; 1079 1080 struct hdspm_peak_rms peak_rms; 1081 }; 1082 1083 1084 static const struct pci_device_id snd_hdspm_ids[] = { 1085 { 1086 .vendor = PCI_VENDOR_ID_XILINX, 1087 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 1088 .subvendor = PCI_ANY_ID, 1089 .subdevice = PCI_ANY_ID, 1090 .class = 0, 1091 .class_mask = 0, 1092 .driver_data = 0}, 1093 {0,} 1094 }; 1095 1096 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 1097 1098 /* prototypes */ 1099 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 1100 struct hdspm *hdspm); 1101 static int snd_hdspm_create_pcm(struct snd_card *card, 1102 struct hdspm *hdspm); 1103 1104 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 1105 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 1106 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 1107 static int hdspm_autosync_ref(struct hdspm *hdspm); 1108 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out); 1109 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 1110 static int hdspm_system_clock_mode(struct hdspm *hdspm); 1111 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 1112 struct snd_pcm_substream *substream, 1113 unsigned int reg, int channels); 1114 1115 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx); 1116 static int hdspm_wc_sync_check(struct hdspm *hdspm); 1117 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1118 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1119 1120 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index); 1121 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm); 1122 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm); 1123 1124 1125 1126 static inline int HDSPM_bit2freq(int n) 1127 { 1128 static const int bit2freq_tab[] = { 1129 0, 32000, 44100, 48000, 64000, 88200, 1130 96000, 128000, 176400, 192000 }; 1131 if (n < 1 || n > 9) 1132 return 0; 1133 return bit2freq_tab[n]; 1134 } 1135 1136 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm) 1137 { 1138 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type)); 1139 } 1140 1141 1142 /* Write/read to/from HDSPM with Adresses in Bytes 1143 not words but only 32Bit writes are allowed */ 1144 1145 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 1146 unsigned int val) 1147 { 1148 writel(val, hdspm->iobase + reg); 1149 } 1150 1151 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1152 { 1153 return readl(hdspm->iobase + reg); 1154 } 1155 1156 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1157 mixer is write only on hardware so we have to cache him for read 1158 each fader is a u32, but uses only the first 16 bit */ 1159 1160 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1161 unsigned int in) 1162 { 1163 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1164 return 0; 1165 1166 return hdspm->mixer->ch[chan].in[in]; 1167 } 1168 1169 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1170 unsigned int pb) 1171 { 1172 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1173 return 0; 1174 return hdspm->mixer->ch[chan].pb[pb]; 1175 } 1176 1177 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1178 unsigned int in, unsigned short data) 1179 { 1180 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1181 return -1; 1182 1183 hdspm_write(hdspm, 1184 HDSPM_MADI_mixerBase + 1185 ((in + 128 * chan) * sizeof(u32)), 1186 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1187 return 0; 1188 } 1189 1190 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1191 unsigned int pb, unsigned short data) 1192 { 1193 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1194 return -1; 1195 1196 hdspm_write(hdspm, 1197 HDSPM_MADI_mixerBase + 1198 ((64 + pb + 128 * chan) * sizeof(u32)), 1199 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1200 return 0; 1201 } 1202 1203 1204 /* enable DMA for specific channels, now available for DSP-MADI */ 1205 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1206 { 1207 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1208 } 1209 1210 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1211 { 1212 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1213 } 1214 1215 /* check if same process is writing and reading */ 1216 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1217 { 1218 unsigned long flags; 1219 int ret = 1; 1220 1221 spin_lock_irqsave(&hdspm->lock, flags); 1222 if ((hdspm->playback_pid != hdspm->capture_pid) && 1223 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1224 ret = 0; 1225 } 1226 spin_unlock_irqrestore(&hdspm->lock, flags); 1227 return ret; 1228 } 1229 1230 /* round arbitary sample rates to commonly known rates */ 1231 static int hdspm_round_frequency(int rate) 1232 { 1233 if (rate < 38050) 1234 return 32000; 1235 if (rate < 46008) 1236 return 44100; 1237 else 1238 return 48000; 1239 } 1240 1241 /* QS and DS rates normally can not be detected 1242 * automatically by the card. Only exception is MADI 1243 * in 96k frame mode. 1244 * 1245 * So if we read SS values (32 .. 48k), check for 1246 * user-provided DS/QS bits in the control register 1247 * and multiply the base frequency accordingly. 1248 */ 1249 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate) 1250 { 1251 if (rate <= 48000) { 1252 if (hdspm->control_register & HDSPM_QuadSpeed) 1253 return rate * 4; 1254 else if (hdspm->control_register & 1255 HDSPM_DoubleSpeed) 1256 return rate * 2; 1257 } 1258 return rate; 1259 } 1260 1261 /* check for external sample rate, returns the sample rate in Hz*/ 1262 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1263 { 1264 unsigned int status, status2; 1265 int syncref, rate = 0, rate_bits; 1266 1267 switch (hdspm->io_type) { 1268 case AES32: 1269 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1270 status = hdspm_read(hdspm, HDSPM_statusRegister); 1271 1272 syncref = hdspm_autosync_ref(hdspm); 1273 switch (syncref) { 1274 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 1275 /* Check WC sync and get sample rate */ 1276 if (hdspm_wc_sync_check(hdspm)) 1277 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm)); 1278 break; 1279 1280 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 1281 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 1282 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 1283 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 1284 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 1285 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 1286 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 1287 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 1288 /* Check AES sync and get sample rate */ 1289 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)) 1290 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm, 1291 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1)); 1292 break; 1293 1294 1295 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 1296 /* Check TCO sync and get sample rate */ 1297 if (hdspm_tco_sync_check(hdspm)) 1298 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm)); 1299 break; 1300 default: 1301 return 0; 1302 } /* end switch(syncref) */ 1303 break; 1304 1305 case MADIface: 1306 status = hdspm_read(hdspm, HDSPM_statusRegister); 1307 1308 if (!(status & HDSPM_madiLock)) { 1309 rate = 0; /* no lock */ 1310 } else { 1311 switch (status & (HDSPM_status1_freqMask)) { 1312 case HDSPM_status1_F_0*1: 1313 rate = 32000; break; 1314 case HDSPM_status1_F_0*2: 1315 rate = 44100; break; 1316 case HDSPM_status1_F_0*3: 1317 rate = 48000; break; 1318 case HDSPM_status1_F_0*4: 1319 rate = 64000; break; 1320 case HDSPM_status1_F_0*5: 1321 rate = 88200; break; 1322 case HDSPM_status1_F_0*6: 1323 rate = 96000; break; 1324 case HDSPM_status1_F_0*7: 1325 rate = 128000; break; 1326 case HDSPM_status1_F_0*8: 1327 rate = 176400; break; 1328 case HDSPM_status1_F_0*9: 1329 rate = 192000; break; 1330 default: 1331 rate = 0; break; 1332 } 1333 } 1334 1335 break; 1336 1337 case MADI: 1338 case AIO: 1339 case RayDAT: 1340 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1341 status = hdspm_read(hdspm, HDSPM_statusRegister); 1342 rate = 0; 1343 1344 /* if wordclock has synced freq and wordclock is valid */ 1345 if ((status2 & HDSPM_wcLock) != 0 && 1346 (status2 & HDSPM_SelSyncRef0) == 0) { 1347 1348 rate_bits = status2 & HDSPM_wcFreqMask; 1349 1350 1351 switch (rate_bits) { 1352 case HDSPM_wcFreq32: 1353 rate = 32000; 1354 break; 1355 case HDSPM_wcFreq44_1: 1356 rate = 44100; 1357 break; 1358 case HDSPM_wcFreq48: 1359 rate = 48000; 1360 break; 1361 case HDSPM_wcFreq64: 1362 rate = 64000; 1363 break; 1364 case HDSPM_wcFreq88_2: 1365 rate = 88200; 1366 break; 1367 case HDSPM_wcFreq96: 1368 rate = 96000; 1369 break; 1370 case HDSPM_wcFreq128: 1371 rate = 128000; 1372 break; 1373 case HDSPM_wcFreq176_4: 1374 rate = 176400; 1375 break; 1376 case HDSPM_wcFreq192: 1377 rate = 192000; 1378 break; 1379 default: 1380 rate = 0; 1381 break; 1382 } 1383 } 1384 1385 /* if rate detected and Syncref is Word than have it, 1386 * word has priority to MADI 1387 */ 1388 if (rate != 0 && 1389 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1390 return hdspm_rate_multiplier(hdspm, rate); 1391 1392 /* maybe a madi input (which is taken if sel sync is madi) */ 1393 if (status & HDSPM_madiLock) { 1394 rate_bits = status & HDSPM_madiFreqMask; 1395 1396 switch (rate_bits) { 1397 case HDSPM_madiFreq32: 1398 rate = 32000; 1399 break; 1400 case HDSPM_madiFreq44_1: 1401 rate = 44100; 1402 break; 1403 case HDSPM_madiFreq48: 1404 rate = 48000; 1405 break; 1406 case HDSPM_madiFreq64: 1407 rate = 64000; 1408 break; 1409 case HDSPM_madiFreq88_2: 1410 rate = 88200; 1411 break; 1412 case HDSPM_madiFreq96: 1413 rate = 96000; 1414 break; 1415 case HDSPM_madiFreq128: 1416 rate = 128000; 1417 break; 1418 case HDSPM_madiFreq176_4: 1419 rate = 176400; 1420 break; 1421 case HDSPM_madiFreq192: 1422 rate = 192000; 1423 break; 1424 default: 1425 rate = 0; 1426 break; 1427 } 1428 1429 } /* endif HDSPM_madiLock */ 1430 1431 /* check sample rate from TCO or SYNC_IN */ 1432 { 1433 bool is_valid_input = 0; 1434 bool has_sync = 0; 1435 1436 syncref = hdspm_autosync_ref(hdspm); 1437 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1438 is_valid_input = 1; 1439 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1440 hdspm_tco_sync_check(hdspm)); 1441 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1442 is_valid_input = 1; 1443 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1444 hdspm_sync_in_sync_check(hdspm)); 1445 } 1446 1447 if (is_valid_input && has_sync) { 1448 rate = hdspm_round_frequency( 1449 hdspm_get_pll_freq(hdspm)); 1450 } 1451 } 1452 1453 rate = hdspm_rate_multiplier(hdspm, rate); 1454 1455 break; 1456 } 1457 1458 return rate; 1459 } 1460 1461 /* return latency in samples per period */ 1462 static int hdspm_get_latency(struct hdspm *hdspm) 1463 { 1464 int n; 1465 1466 n = hdspm_decode_latency(hdspm->control_register); 1467 1468 /* Special case for new RME cards with 32 samples period size. 1469 * The three latency bits in the control register 1470 * (HDSP_LatencyMask) encode latency values of 64 samples as 1471 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1472 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1473 * it corresponds to 32 samples. 1474 */ 1475 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1476 n = -1; 1477 1478 return 1 << (n + 6); 1479 } 1480 1481 /* Latency function */ 1482 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1483 { 1484 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1485 } 1486 1487 1488 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1489 { 1490 int position; 1491 1492 position = hdspm_read(hdspm, HDSPM_statusRegister); 1493 1494 switch (hdspm->io_type) { 1495 case RayDAT: 1496 case AIO: 1497 position &= HDSPM_BufferPositionMask; 1498 position /= 4; /* Bytes per sample */ 1499 break; 1500 default: 1501 position = (position & HDSPM_BufferID) ? 1502 (hdspm->period_bytes / 4) : 0; 1503 } 1504 1505 return position; 1506 } 1507 1508 1509 static inline void hdspm_start_audio(struct hdspm * s) 1510 { 1511 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1512 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1513 } 1514 1515 static inline void hdspm_stop_audio(struct hdspm * s) 1516 { 1517 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1518 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1519 } 1520 1521 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1522 static void hdspm_silence_playback(struct hdspm *hdspm) 1523 { 1524 int i; 1525 int n = hdspm->period_bytes; 1526 void *buf = hdspm->playback_buffer; 1527 1528 if (!buf) 1529 return; 1530 1531 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1532 memset(buf, 0, n); 1533 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1534 } 1535 } 1536 1537 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1538 { 1539 int n; 1540 1541 spin_lock_irq(&s->lock); 1542 1543 if (32 == frames) { 1544 /* Special case for new RME cards like RayDAT/AIO which 1545 * support period sizes of 32 samples. Since latency is 1546 * encoded in the three bits of HDSP_LatencyMask, we can only 1547 * have values from 0 .. 7. While 0 still means 64 samples and 1548 * 6 represents 4096 samples on all cards, 7 represents 8192 1549 * on older cards and 32 samples on new cards. 1550 * 1551 * In other words, period size in samples is calculated by 1552 * 2^(n+6) with n ranging from 0 .. 7. 1553 */ 1554 n = 7; 1555 } else { 1556 frames >>= 7; 1557 n = 0; 1558 while (frames) { 1559 n++; 1560 frames >>= 1; 1561 } 1562 } 1563 1564 s->control_register &= ~HDSPM_LatencyMask; 1565 s->control_register |= hdspm_encode_latency(n); 1566 1567 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1568 1569 hdspm_compute_period_size(s); 1570 1571 spin_unlock_irq(&s->lock); 1572 1573 return 0; 1574 } 1575 1576 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1577 { 1578 u64 freq_const; 1579 1580 if (period == 0) 1581 return 0; 1582 1583 switch (hdspm->io_type) { 1584 case MADI: 1585 case AES32: 1586 freq_const = 110069313433624ULL; 1587 break; 1588 case RayDAT: 1589 case AIO: 1590 freq_const = 104857600000000ULL; 1591 break; 1592 case MADIface: 1593 freq_const = 131072000000000ULL; 1594 break; 1595 default: 1596 snd_BUG(); 1597 return 0; 1598 } 1599 1600 return div_u64(freq_const, period); 1601 } 1602 1603 1604 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1605 { 1606 u64 n; 1607 1608 if (snd_BUG_ON(rate <= 0)) 1609 return; 1610 1611 if (rate >= 112000) 1612 rate /= 4; 1613 else if (rate >= 56000) 1614 rate /= 2; 1615 1616 switch (hdspm->io_type) { 1617 case MADIface: 1618 n = 131072000000000ULL; /* 125 MHz */ 1619 break; 1620 case MADI: 1621 case AES32: 1622 n = 110069313433624ULL; /* 105 MHz */ 1623 break; 1624 case RayDAT: 1625 case AIO: 1626 n = 104857600000000ULL; /* 100 MHz */ 1627 break; 1628 default: 1629 snd_BUG(); 1630 return; 1631 } 1632 1633 n = div_u64(n, rate); 1634 /* n should be less than 2^32 for being written to FREQ register */ 1635 snd_BUG_ON(n >> 32); 1636 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1637 } 1638 1639 /* dummy set rate lets see what happens */ 1640 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1641 { 1642 int current_rate; 1643 int rate_bits; 1644 int not_set = 0; 1645 int current_speed, target_speed; 1646 1647 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1648 it (e.g. during module initialization). 1649 */ 1650 1651 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1652 1653 /* SLAVE --- */ 1654 if (called_internally) { 1655 1656 /* request from ctl or card initialization 1657 just make a warning an remember setting 1658 for future master mode switching */ 1659 1660 dev_warn(hdspm->card->dev, 1661 "Warning: device is not running as a clock master.\n"); 1662 not_set = 1; 1663 } else { 1664 1665 /* hw_param request while in AutoSync mode */ 1666 int external_freq = 1667 hdspm_external_sample_rate(hdspm); 1668 1669 if (hdspm_autosync_ref(hdspm) == 1670 HDSPM_AUTOSYNC_FROM_NONE) { 1671 1672 dev_warn(hdspm->card->dev, 1673 "Detected no External Sync\n"); 1674 not_set = 1; 1675 1676 } else if (rate != external_freq) { 1677 1678 dev_warn(hdspm->card->dev, 1679 "Warning: No AutoSync source for requested rate\n"); 1680 not_set = 1; 1681 } 1682 } 1683 } 1684 1685 current_rate = hdspm->system_sample_rate; 1686 1687 /* Changing between Singe, Double and Quad speed is not 1688 allowed if any substreams are open. This is because such a change 1689 causes a shift in the location of the DMA buffers and a reduction 1690 in the number of available buffers. 1691 1692 Note that a similar but essentially insoluble problem exists for 1693 externally-driven rate changes. All we can do is to flag rate 1694 changes in the read/write routines. 1695 */ 1696 1697 if (current_rate <= 48000) 1698 current_speed = HDSPM_SPEED_SINGLE; 1699 else if (current_rate <= 96000) 1700 current_speed = HDSPM_SPEED_DOUBLE; 1701 else 1702 current_speed = HDSPM_SPEED_QUAD; 1703 1704 if (rate <= 48000) 1705 target_speed = HDSPM_SPEED_SINGLE; 1706 else if (rate <= 96000) 1707 target_speed = HDSPM_SPEED_DOUBLE; 1708 else 1709 target_speed = HDSPM_SPEED_QUAD; 1710 1711 switch (rate) { 1712 case 32000: 1713 rate_bits = HDSPM_Frequency32KHz; 1714 break; 1715 case 44100: 1716 rate_bits = HDSPM_Frequency44_1KHz; 1717 break; 1718 case 48000: 1719 rate_bits = HDSPM_Frequency48KHz; 1720 break; 1721 case 64000: 1722 rate_bits = HDSPM_Frequency64KHz; 1723 break; 1724 case 88200: 1725 rate_bits = HDSPM_Frequency88_2KHz; 1726 break; 1727 case 96000: 1728 rate_bits = HDSPM_Frequency96KHz; 1729 break; 1730 case 128000: 1731 rate_bits = HDSPM_Frequency128KHz; 1732 break; 1733 case 176400: 1734 rate_bits = HDSPM_Frequency176_4KHz; 1735 break; 1736 case 192000: 1737 rate_bits = HDSPM_Frequency192KHz; 1738 break; 1739 default: 1740 return -EINVAL; 1741 } 1742 1743 if (current_speed != target_speed 1744 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1745 dev_err(hdspm->card->dev, 1746 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n", 1747 hdspm_speed_names[current_speed], 1748 hdspm_speed_names[target_speed], 1749 hdspm->capture_pid, hdspm->playback_pid); 1750 return -EBUSY; 1751 } 1752 1753 hdspm->control_register &= ~HDSPM_FrequencyMask; 1754 hdspm->control_register |= rate_bits; 1755 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1756 1757 /* For AES32, need to set DDS value in FREQ register 1758 For MADI, also apparently */ 1759 hdspm_set_dds_value(hdspm, rate); 1760 1761 if (AES32 == hdspm->io_type && rate != current_rate) 1762 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1763 1764 hdspm->system_sample_rate = rate; 1765 1766 if (rate <= 48000) { 1767 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1768 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1769 hdspm->max_channels_in = hdspm->ss_in_channels; 1770 hdspm->max_channels_out = hdspm->ss_out_channels; 1771 hdspm->port_names_in = hdspm->port_names_in_ss; 1772 hdspm->port_names_out = hdspm->port_names_out_ss; 1773 } else if (rate <= 96000) { 1774 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1775 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1776 hdspm->max_channels_in = hdspm->ds_in_channels; 1777 hdspm->max_channels_out = hdspm->ds_out_channels; 1778 hdspm->port_names_in = hdspm->port_names_in_ds; 1779 hdspm->port_names_out = hdspm->port_names_out_ds; 1780 } else { 1781 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1782 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1783 hdspm->max_channels_in = hdspm->qs_in_channels; 1784 hdspm->max_channels_out = hdspm->qs_out_channels; 1785 hdspm->port_names_in = hdspm->port_names_in_qs; 1786 hdspm->port_names_out = hdspm->port_names_out_qs; 1787 } 1788 1789 if (not_set != 0) 1790 return -1; 1791 1792 return 0; 1793 } 1794 1795 /* mainly for init to 0 on load */ 1796 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1797 { 1798 int i, j; 1799 unsigned int gain; 1800 1801 if (sgain > UNITY_GAIN) 1802 gain = UNITY_GAIN; 1803 else if (sgain < 0) 1804 gain = 0; 1805 else 1806 gain = sgain; 1807 1808 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1809 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1810 hdspm_write_in_gain(hdspm, i, j, gain); 1811 hdspm_write_pb_gain(hdspm, i, j, gain); 1812 } 1813 } 1814 1815 /*---------------------------------------------------------------------------- 1816 MIDI 1817 ----------------------------------------------------------------------------*/ 1818 1819 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1820 int id) 1821 { 1822 /* the hardware already does the relevant bit-mask with 0xff */ 1823 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1824 } 1825 1826 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1827 int val) 1828 { 1829 /* the hardware already does the relevant bit-mask with 0xff */ 1830 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1831 } 1832 1833 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1834 { 1835 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1836 } 1837 1838 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1839 { 1840 int fifo_bytes_used; 1841 1842 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1843 1844 if (fifo_bytes_used < 128) 1845 return 128 - fifo_bytes_used; 1846 else 1847 return 0; 1848 } 1849 1850 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1851 { 1852 while (snd_hdspm_midi_input_available (hdspm, id)) 1853 snd_hdspm_midi_read_byte (hdspm, id); 1854 } 1855 1856 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1857 { 1858 unsigned long flags; 1859 int n_pending; 1860 int to_write; 1861 int i; 1862 unsigned char buf[128]; 1863 1864 /* Output is not interrupt driven */ 1865 1866 spin_lock_irqsave (&hmidi->lock, flags); 1867 if (hmidi->output && 1868 !snd_rawmidi_transmit_empty (hmidi->output)) { 1869 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1870 hmidi->id); 1871 if (n_pending > 0) { 1872 if (n_pending > (int)sizeof (buf)) 1873 n_pending = sizeof (buf); 1874 1875 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1876 n_pending); 1877 if (to_write > 0) { 1878 for (i = 0; i < to_write; ++i) 1879 snd_hdspm_midi_write_byte (hmidi->hdspm, 1880 hmidi->id, 1881 buf[i]); 1882 } 1883 } 1884 } 1885 spin_unlock_irqrestore (&hmidi->lock, flags); 1886 return 0; 1887 } 1888 1889 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1890 { 1891 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1892 * input FIFO size 1893 */ 1894 unsigned long flags; 1895 int n_pending; 1896 int i; 1897 1898 spin_lock_irqsave (&hmidi->lock, flags); 1899 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1900 if (n_pending > 0) { 1901 if (hmidi->input) { 1902 if (n_pending > (int)sizeof (buf)) 1903 n_pending = sizeof (buf); 1904 for (i = 0; i < n_pending; ++i) 1905 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1906 hmidi->id); 1907 if (n_pending) 1908 snd_rawmidi_receive (hmidi->input, buf, 1909 n_pending); 1910 } else { 1911 /* flush the MIDI input FIFO */ 1912 while (n_pending--) 1913 snd_hdspm_midi_read_byte (hmidi->hdspm, 1914 hmidi->id); 1915 } 1916 } 1917 hmidi->pending = 0; 1918 spin_unlock_irqrestore(&hmidi->lock, flags); 1919 1920 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1921 hmidi->hdspm->control_register |= hmidi->ie; 1922 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1923 hmidi->hdspm->control_register); 1924 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1925 1926 return snd_hdspm_midi_output_write (hmidi); 1927 } 1928 1929 static void 1930 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1931 { 1932 struct hdspm *hdspm; 1933 struct hdspm_midi *hmidi; 1934 unsigned long flags; 1935 1936 hmidi = substream->rmidi->private_data; 1937 hdspm = hmidi->hdspm; 1938 1939 spin_lock_irqsave (&hdspm->lock, flags); 1940 if (up) { 1941 if (!(hdspm->control_register & hmidi->ie)) { 1942 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1943 hdspm->control_register |= hmidi->ie; 1944 } 1945 } else { 1946 hdspm->control_register &= ~hmidi->ie; 1947 } 1948 1949 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1950 spin_unlock_irqrestore (&hdspm->lock, flags); 1951 } 1952 1953 static void snd_hdspm_midi_output_timer(struct timer_list *t) 1954 { 1955 struct hdspm_midi *hmidi = from_timer(hmidi, t, timer); 1956 unsigned long flags; 1957 1958 snd_hdspm_midi_output_write(hmidi); 1959 spin_lock_irqsave (&hmidi->lock, flags); 1960 1961 /* this does not bump hmidi->istimer, because the 1962 kernel automatically removed the timer when it 1963 expired, and we are now adding it back, thus 1964 leaving istimer wherever it was set before. 1965 */ 1966 1967 if (hmidi->istimer) 1968 mod_timer(&hmidi->timer, 1 + jiffies); 1969 1970 spin_unlock_irqrestore (&hmidi->lock, flags); 1971 } 1972 1973 static void 1974 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1975 { 1976 struct hdspm_midi *hmidi; 1977 unsigned long flags; 1978 1979 hmidi = substream->rmidi->private_data; 1980 spin_lock_irqsave (&hmidi->lock, flags); 1981 if (up) { 1982 if (!hmidi->istimer) { 1983 timer_setup(&hmidi->timer, 1984 snd_hdspm_midi_output_timer, 0); 1985 mod_timer(&hmidi->timer, 1 + jiffies); 1986 hmidi->istimer++; 1987 } 1988 } else { 1989 if (hmidi->istimer && --hmidi->istimer <= 0) 1990 del_timer (&hmidi->timer); 1991 } 1992 spin_unlock_irqrestore (&hmidi->lock, flags); 1993 if (up) 1994 snd_hdspm_midi_output_write(hmidi); 1995 } 1996 1997 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1998 { 1999 struct hdspm_midi *hmidi; 2000 2001 hmidi = substream->rmidi->private_data; 2002 spin_lock_irq (&hmidi->lock); 2003 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 2004 hmidi->input = substream; 2005 spin_unlock_irq (&hmidi->lock); 2006 2007 return 0; 2008 } 2009 2010 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 2011 { 2012 struct hdspm_midi *hmidi; 2013 2014 hmidi = substream->rmidi->private_data; 2015 spin_lock_irq (&hmidi->lock); 2016 hmidi->output = substream; 2017 spin_unlock_irq (&hmidi->lock); 2018 2019 return 0; 2020 } 2021 2022 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 2023 { 2024 struct hdspm_midi *hmidi; 2025 2026 snd_hdspm_midi_input_trigger (substream, 0); 2027 2028 hmidi = substream->rmidi->private_data; 2029 spin_lock_irq (&hmidi->lock); 2030 hmidi->input = NULL; 2031 spin_unlock_irq (&hmidi->lock); 2032 2033 return 0; 2034 } 2035 2036 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 2037 { 2038 struct hdspm_midi *hmidi; 2039 2040 snd_hdspm_midi_output_trigger (substream, 0); 2041 2042 hmidi = substream->rmidi->private_data; 2043 spin_lock_irq (&hmidi->lock); 2044 hmidi->output = NULL; 2045 spin_unlock_irq (&hmidi->lock); 2046 2047 return 0; 2048 } 2049 2050 static const struct snd_rawmidi_ops snd_hdspm_midi_output = 2051 { 2052 .open = snd_hdspm_midi_output_open, 2053 .close = snd_hdspm_midi_output_close, 2054 .trigger = snd_hdspm_midi_output_trigger, 2055 }; 2056 2057 static const struct snd_rawmidi_ops snd_hdspm_midi_input = 2058 { 2059 .open = snd_hdspm_midi_input_open, 2060 .close = snd_hdspm_midi_input_close, 2061 .trigger = snd_hdspm_midi_input_trigger, 2062 }; 2063 2064 static int snd_hdspm_create_midi(struct snd_card *card, 2065 struct hdspm *hdspm, int id) 2066 { 2067 int err; 2068 char buf[64]; 2069 2070 hdspm->midi[id].id = id; 2071 hdspm->midi[id].hdspm = hdspm; 2072 spin_lock_init (&hdspm->midi[id].lock); 2073 2074 if (0 == id) { 2075 if (MADIface == hdspm->io_type) { 2076 /* MIDI-over-MADI on HDSPe MADIface */ 2077 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 2078 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 2079 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 2080 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 2081 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 2082 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 2083 } else { 2084 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 2085 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 2086 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 2087 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 2088 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 2089 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 2090 } 2091 } else if (1 == id) { 2092 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 2093 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 2094 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 2095 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 2096 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 2097 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 2098 } else if ((2 == id) && (MADI == hdspm->io_type)) { 2099 /* MIDI-over-MADI on HDSPe MADI */ 2100 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2101 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2102 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 2103 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 2104 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2105 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 2106 } else if (2 == id) { 2107 /* TCO MTC, read only */ 2108 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 2109 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 2110 hdspm->midi[2].dataOut = -1; 2111 hdspm->midi[2].statusOut = -1; 2112 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 2113 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 2114 } else if (3 == id) { 2115 /* TCO MTC on HDSPe MADI */ 2116 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 2117 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 2118 hdspm->midi[3].dataOut = -1; 2119 hdspm->midi[3].statusOut = -1; 2120 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 2121 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 2122 } 2123 2124 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 2125 (MADIface == hdspm->io_type)))) { 2126 if ((id == 0) && (MADIface == hdspm->io_type)) { 2127 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2128 card->shortname); 2129 } else if ((id == 2) && (MADI == hdspm->io_type)) { 2130 snprintf(buf, sizeof(buf), "%s MIDIoverMADI", 2131 card->shortname); 2132 } else { 2133 snprintf(buf, sizeof(buf), "%s MIDI %d", 2134 card->shortname, id+1); 2135 } 2136 err = snd_rawmidi_new(card, buf, id, 1, 1, 2137 &hdspm->midi[id].rmidi); 2138 if (err < 0) 2139 return err; 2140 2141 snprintf(hdspm->midi[id].rmidi->name, 2142 sizeof(hdspm->midi[id].rmidi->name), 2143 "%s MIDI %d", card->id, id+1); 2144 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2145 2146 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2147 SNDRV_RAWMIDI_STREAM_OUTPUT, 2148 &snd_hdspm_midi_output); 2149 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2150 SNDRV_RAWMIDI_STREAM_INPUT, 2151 &snd_hdspm_midi_input); 2152 2153 hdspm->midi[id].rmidi->info_flags |= 2154 SNDRV_RAWMIDI_INFO_OUTPUT | 2155 SNDRV_RAWMIDI_INFO_INPUT | 2156 SNDRV_RAWMIDI_INFO_DUPLEX; 2157 } else { 2158 /* TCO MTC, read only */ 2159 snprintf(buf, sizeof(buf), "%s MTC %d", 2160 card->shortname, id+1); 2161 err = snd_rawmidi_new(card, buf, id, 1, 1, 2162 &hdspm->midi[id].rmidi); 2163 if (err < 0) 2164 return err; 2165 2166 snprintf(hdspm->midi[id].rmidi->name, 2167 sizeof(hdspm->midi[id].rmidi->name), 2168 "%s MTC %d", card->id, id+1); 2169 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 2170 2171 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 2172 SNDRV_RAWMIDI_STREAM_INPUT, 2173 &snd_hdspm_midi_input); 2174 2175 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 2176 } 2177 2178 return 0; 2179 } 2180 2181 2182 static void hdspm_midi_tasklet(unsigned long arg) 2183 { 2184 struct hdspm *hdspm = (struct hdspm *)arg; 2185 int i = 0; 2186 2187 while (i < hdspm->midiPorts) { 2188 if (hdspm->midi[i].pending) 2189 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2190 2191 i++; 2192 } 2193 } 2194 2195 2196 /*----------------------------------------------------------------------------- 2197 Status Interface 2198 ----------------------------------------------------------------------------*/ 2199 2200 /* get the system sample rate which is set */ 2201 2202 2203 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2204 { 2205 unsigned int period, rate; 2206 2207 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2208 rate = hdspm_calc_dds_value(hdspm, period); 2209 2210 return rate; 2211 } 2212 2213 /* 2214 * Calculate the real sample rate from the 2215 * current DDS value. 2216 */ 2217 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2218 { 2219 unsigned int rate; 2220 2221 rate = hdspm_get_pll_freq(hdspm); 2222 2223 if (rate > 207000) { 2224 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2225 if (0 == hdspm_system_clock_mode(hdspm)) { 2226 /* master mode, return internal sample rate */ 2227 rate = hdspm->system_sample_rate; 2228 } else { 2229 /* slave mode, return external sample rate */ 2230 rate = hdspm_external_sample_rate(hdspm); 2231 if (!rate) 2232 rate = hdspm->system_sample_rate; 2233 } 2234 } 2235 2236 return rate; 2237 } 2238 2239 2240 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2241 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2242 .name = xname, \ 2243 .index = xindex, \ 2244 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2245 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2246 .info = snd_hdspm_info_system_sample_rate, \ 2247 .put = snd_hdspm_put_system_sample_rate, \ 2248 .get = snd_hdspm_get_system_sample_rate \ 2249 } 2250 2251 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2252 struct snd_ctl_elem_info *uinfo) 2253 { 2254 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2255 uinfo->count = 1; 2256 uinfo->value.integer.min = 27000; 2257 uinfo->value.integer.max = 207000; 2258 uinfo->value.integer.step = 1; 2259 return 0; 2260 } 2261 2262 2263 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2264 struct snd_ctl_elem_value * 2265 ucontrol) 2266 { 2267 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2268 2269 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2270 return 0; 2271 } 2272 2273 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2274 struct snd_ctl_elem_value * 2275 ucontrol) 2276 { 2277 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2278 int rate = ucontrol->value.integer.value[0]; 2279 2280 if (rate < 27000 || rate > 207000) 2281 return -EINVAL; 2282 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]); 2283 return 0; 2284 } 2285 2286 2287 /* 2288 * Returns the WordClock sample rate class for the given card. 2289 */ 2290 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2291 { 2292 int status; 2293 2294 switch (hdspm->io_type) { 2295 case RayDAT: 2296 case AIO: 2297 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2298 return (status >> 16) & 0xF; 2299 break; 2300 case AES32: 2301 status = hdspm_read(hdspm, HDSPM_statusRegister); 2302 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF; 2303 default: 2304 break; 2305 } 2306 2307 2308 return 0; 2309 } 2310 2311 2312 /* 2313 * Returns the TCO sample rate class for the given card. 2314 */ 2315 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2316 { 2317 int status; 2318 2319 if (hdspm->tco) { 2320 switch (hdspm->io_type) { 2321 case RayDAT: 2322 case AIO: 2323 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2324 return (status >> 20) & 0xF; 2325 break; 2326 case AES32: 2327 status = hdspm_read(hdspm, HDSPM_statusRegister); 2328 return (status >> 1) & 0xF; 2329 default: 2330 break; 2331 } 2332 } 2333 2334 return 0; 2335 } 2336 2337 2338 /* 2339 * Returns the SYNC_IN sample rate class for the given card. 2340 */ 2341 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2342 { 2343 int status; 2344 2345 if (hdspm->tco) { 2346 switch (hdspm->io_type) { 2347 case RayDAT: 2348 case AIO: 2349 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2350 return (status >> 12) & 0xF; 2351 break; 2352 default: 2353 break; 2354 } 2355 } 2356 2357 return 0; 2358 } 2359 2360 /* 2361 * Returns the AES sample rate class for the given card. 2362 */ 2363 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index) 2364 { 2365 int timecode; 2366 2367 switch (hdspm->io_type) { 2368 case AES32: 2369 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 2370 return (timecode >> (4*index)) & 0xF; 2371 break; 2372 default: 2373 break; 2374 } 2375 return 0; 2376 } 2377 2378 /* 2379 * Returns the sample rate class for input source <idx> for 2380 * 'new style' cards like the AIO and RayDAT. 2381 */ 2382 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2383 { 2384 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2385 2386 return (status >> (idx*4)) & 0xF; 2387 } 2388 2389 #define ENUMERATED_CTL_INFO(info, texts) \ 2390 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts) 2391 2392 2393 /* Helper function to query the external sample rate and return the 2394 * corresponding enum to be returned to userspace. 2395 */ 2396 static int hdspm_external_rate_to_enum(struct hdspm *hdspm) 2397 { 2398 int rate = hdspm_external_sample_rate(hdspm); 2399 int i, selected_rate = 0; 2400 for (i = 1; i < 10; i++) 2401 if (HDSPM_bit2freq(i) == rate) { 2402 selected_rate = i; 2403 break; 2404 } 2405 return selected_rate; 2406 } 2407 2408 2409 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2410 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2411 .name = xname, \ 2412 .private_value = xindex, \ 2413 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2414 .info = snd_hdspm_info_autosync_sample_rate, \ 2415 .get = snd_hdspm_get_autosync_sample_rate \ 2416 } 2417 2418 2419 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2420 struct snd_ctl_elem_info *uinfo) 2421 { 2422 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2423 return 0; 2424 } 2425 2426 2427 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2428 struct snd_ctl_elem_value * 2429 ucontrol) 2430 { 2431 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2432 2433 switch (hdspm->io_type) { 2434 case RayDAT: 2435 switch (kcontrol->private_value) { 2436 case 0: 2437 ucontrol->value.enumerated.item[0] = 2438 hdspm_get_wc_sample_rate(hdspm); 2439 break; 2440 case 7: 2441 ucontrol->value.enumerated.item[0] = 2442 hdspm_get_tco_sample_rate(hdspm); 2443 break; 2444 case 8: 2445 ucontrol->value.enumerated.item[0] = 2446 hdspm_get_sync_in_sample_rate(hdspm); 2447 break; 2448 default: 2449 ucontrol->value.enumerated.item[0] = 2450 hdspm_get_s1_sample_rate(hdspm, 2451 kcontrol->private_value-1); 2452 } 2453 break; 2454 2455 case AIO: 2456 switch (kcontrol->private_value) { 2457 case 0: /* WC */ 2458 ucontrol->value.enumerated.item[0] = 2459 hdspm_get_wc_sample_rate(hdspm); 2460 break; 2461 case 4: /* TCO */ 2462 ucontrol->value.enumerated.item[0] = 2463 hdspm_get_tco_sample_rate(hdspm); 2464 break; 2465 case 5: /* SYNC_IN */ 2466 ucontrol->value.enumerated.item[0] = 2467 hdspm_get_sync_in_sample_rate(hdspm); 2468 break; 2469 default: 2470 ucontrol->value.enumerated.item[0] = 2471 hdspm_get_s1_sample_rate(hdspm, 2472 kcontrol->private_value-1); 2473 } 2474 break; 2475 2476 case AES32: 2477 2478 switch (kcontrol->private_value) { 2479 case 0: /* WC */ 2480 ucontrol->value.enumerated.item[0] = 2481 hdspm_get_wc_sample_rate(hdspm); 2482 break; 2483 case 9: /* TCO */ 2484 ucontrol->value.enumerated.item[0] = 2485 hdspm_get_tco_sample_rate(hdspm); 2486 break; 2487 case 10: /* SYNC_IN */ 2488 ucontrol->value.enumerated.item[0] = 2489 hdspm_get_sync_in_sample_rate(hdspm); 2490 break; 2491 case 11: /* External Rate */ 2492 ucontrol->value.enumerated.item[0] = 2493 hdspm_external_rate_to_enum(hdspm); 2494 break; 2495 default: /* AES1 to AES8 */ 2496 ucontrol->value.enumerated.item[0] = 2497 hdspm_get_aes_sample_rate(hdspm, 2498 kcontrol->private_value - 2499 HDSPM_AES32_AUTOSYNC_FROM_AES1); 2500 break; 2501 } 2502 break; 2503 2504 case MADI: 2505 case MADIface: 2506 ucontrol->value.enumerated.item[0] = 2507 hdspm_external_rate_to_enum(hdspm); 2508 break; 2509 default: 2510 break; 2511 } 2512 2513 return 0; 2514 } 2515 2516 2517 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2518 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2519 .name = xname, \ 2520 .index = xindex, \ 2521 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2522 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2523 .info = snd_hdspm_info_system_clock_mode, \ 2524 .get = snd_hdspm_get_system_clock_mode, \ 2525 .put = snd_hdspm_put_system_clock_mode, \ 2526 } 2527 2528 2529 /* 2530 * Returns the system clock mode for the given card. 2531 * @returns 0 - master, 1 - slave 2532 */ 2533 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2534 { 2535 switch (hdspm->io_type) { 2536 case AIO: 2537 case RayDAT: 2538 if (hdspm->settings_register & HDSPM_c0Master) 2539 return 0; 2540 break; 2541 2542 default: 2543 if (hdspm->control_register & HDSPM_ClockModeMaster) 2544 return 0; 2545 } 2546 2547 return 1; 2548 } 2549 2550 2551 /* 2552 * Sets the system clock mode. 2553 * @param mode 0 - master, 1 - slave 2554 */ 2555 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2556 { 2557 hdspm_set_toggle_setting(hdspm, 2558 (hdspm_is_raydat_or_aio(hdspm)) ? 2559 HDSPM_c0Master : HDSPM_ClockModeMaster, 2560 (0 == mode)); 2561 } 2562 2563 2564 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2565 struct snd_ctl_elem_info *uinfo) 2566 { 2567 static const char *const texts[] = { "Master", "AutoSync" }; 2568 ENUMERATED_CTL_INFO(uinfo, texts); 2569 return 0; 2570 } 2571 2572 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2573 struct snd_ctl_elem_value *ucontrol) 2574 { 2575 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2576 2577 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2578 return 0; 2579 } 2580 2581 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2582 struct snd_ctl_elem_value *ucontrol) 2583 { 2584 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2585 int val; 2586 2587 if (!snd_hdspm_use_is_exclusive(hdspm)) 2588 return -EBUSY; 2589 2590 val = ucontrol->value.enumerated.item[0]; 2591 if (val < 0) 2592 val = 0; 2593 else if (val > 1) 2594 val = 1; 2595 2596 hdspm_set_system_clock_mode(hdspm, val); 2597 2598 return 0; 2599 } 2600 2601 2602 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2603 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2604 .name = xname, \ 2605 .index = xindex, \ 2606 .info = snd_hdspm_info_clock_source, \ 2607 .get = snd_hdspm_get_clock_source, \ 2608 .put = snd_hdspm_put_clock_source \ 2609 } 2610 2611 2612 static int hdspm_clock_source(struct hdspm * hdspm) 2613 { 2614 switch (hdspm->system_sample_rate) { 2615 case 32000: return 0; 2616 case 44100: return 1; 2617 case 48000: return 2; 2618 case 64000: return 3; 2619 case 88200: return 4; 2620 case 96000: return 5; 2621 case 128000: return 6; 2622 case 176400: return 7; 2623 case 192000: return 8; 2624 } 2625 2626 return -1; 2627 } 2628 2629 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2630 { 2631 int rate; 2632 switch (mode) { 2633 case 0: 2634 rate = 32000; break; 2635 case 1: 2636 rate = 44100; break; 2637 case 2: 2638 rate = 48000; break; 2639 case 3: 2640 rate = 64000; break; 2641 case 4: 2642 rate = 88200; break; 2643 case 5: 2644 rate = 96000; break; 2645 case 6: 2646 rate = 128000; break; 2647 case 7: 2648 rate = 176400; break; 2649 case 8: 2650 rate = 192000; break; 2651 default: 2652 rate = 48000; 2653 } 2654 hdspm_set_rate(hdspm, rate, 1); 2655 return 0; 2656 } 2657 2658 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2659 struct snd_ctl_elem_info *uinfo) 2660 { 2661 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1); 2662 } 2663 2664 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2665 struct snd_ctl_elem_value *ucontrol) 2666 { 2667 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2668 2669 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2670 return 0; 2671 } 2672 2673 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2674 struct snd_ctl_elem_value *ucontrol) 2675 { 2676 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2677 int change; 2678 int val; 2679 2680 if (!snd_hdspm_use_is_exclusive(hdspm)) 2681 return -EBUSY; 2682 val = ucontrol->value.enumerated.item[0]; 2683 if (val < 0) 2684 val = 0; 2685 if (val > 9) 2686 val = 9; 2687 spin_lock_irq(&hdspm->lock); 2688 if (val != hdspm_clock_source(hdspm)) 2689 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2690 else 2691 change = 0; 2692 spin_unlock_irq(&hdspm->lock); 2693 return change; 2694 } 2695 2696 2697 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2698 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2699 .name = xname, \ 2700 .index = xindex, \ 2701 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2702 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2703 .info = snd_hdspm_info_pref_sync_ref, \ 2704 .get = snd_hdspm_get_pref_sync_ref, \ 2705 .put = snd_hdspm_put_pref_sync_ref \ 2706 } 2707 2708 2709 /* 2710 * Returns the current preferred sync reference setting. 2711 * The semantics of the return value are depending on the 2712 * card, please see the comments for clarification. 2713 */ 2714 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2715 { 2716 switch (hdspm->io_type) { 2717 case AES32: 2718 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2719 case 0: return 0; /* WC */ 2720 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2721 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2722 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2723 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2724 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2725 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2726 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2727 return 7; /* AES 7 */ 2728 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2729 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2730 } 2731 break; 2732 2733 case MADI: 2734 case MADIface: 2735 if (hdspm->tco) { 2736 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2737 case 0: return 0; /* WC */ 2738 case HDSPM_SyncRef0: return 1; /* MADI */ 2739 case HDSPM_SyncRef1: return 2; /* TCO */ 2740 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2741 return 3; /* SYNC_IN */ 2742 } 2743 } else { 2744 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2745 case 0: return 0; /* WC */ 2746 case HDSPM_SyncRef0: return 1; /* MADI */ 2747 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2748 return 2; /* SYNC_IN */ 2749 } 2750 } 2751 break; 2752 2753 case RayDAT: 2754 if (hdspm->tco) { 2755 switch ((hdspm->settings_register & 2756 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2757 case 0: return 0; /* WC */ 2758 case 3: return 1; /* ADAT 1 */ 2759 case 4: return 2; /* ADAT 2 */ 2760 case 5: return 3; /* ADAT 3 */ 2761 case 6: return 4; /* ADAT 4 */ 2762 case 1: return 5; /* AES */ 2763 case 2: return 6; /* SPDIF */ 2764 case 9: return 7; /* TCO */ 2765 case 10: return 8; /* SYNC_IN */ 2766 } 2767 } else { 2768 switch ((hdspm->settings_register & 2769 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2770 case 0: return 0; /* WC */ 2771 case 3: return 1; /* ADAT 1 */ 2772 case 4: return 2; /* ADAT 2 */ 2773 case 5: return 3; /* ADAT 3 */ 2774 case 6: return 4; /* ADAT 4 */ 2775 case 1: return 5; /* AES */ 2776 case 2: return 6; /* SPDIF */ 2777 case 10: return 7; /* SYNC_IN */ 2778 } 2779 } 2780 2781 break; 2782 2783 case AIO: 2784 if (hdspm->tco) { 2785 switch ((hdspm->settings_register & 2786 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2787 case 0: return 0; /* WC */ 2788 case 3: return 1; /* ADAT */ 2789 case 1: return 2; /* AES */ 2790 case 2: return 3; /* SPDIF */ 2791 case 9: return 4; /* TCO */ 2792 case 10: return 5; /* SYNC_IN */ 2793 } 2794 } else { 2795 switch ((hdspm->settings_register & 2796 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2797 case 0: return 0; /* WC */ 2798 case 3: return 1; /* ADAT */ 2799 case 1: return 2; /* AES */ 2800 case 2: return 3; /* SPDIF */ 2801 case 10: return 4; /* SYNC_IN */ 2802 } 2803 } 2804 2805 break; 2806 } 2807 2808 return -1; 2809 } 2810 2811 2812 /* 2813 * Set the preferred sync reference to <pref>. The semantics 2814 * of <pref> are depending on the card type, see the comments 2815 * for clarification. 2816 */ 2817 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2818 { 2819 int p = 0; 2820 2821 switch (hdspm->io_type) { 2822 case AES32: 2823 hdspm->control_register &= ~HDSPM_SyncRefMask; 2824 switch (pref) { 2825 case 0: /* WC */ 2826 break; 2827 case 1: /* AES 1 */ 2828 hdspm->control_register |= HDSPM_SyncRef0; 2829 break; 2830 case 2: /* AES 2 */ 2831 hdspm->control_register |= HDSPM_SyncRef1; 2832 break; 2833 case 3: /* AES 3 */ 2834 hdspm->control_register |= 2835 HDSPM_SyncRef1+HDSPM_SyncRef0; 2836 break; 2837 case 4: /* AES 4 */ 2838 hdspm->control_register |= HDSPM_SyncRef2; 2839 break; 2840 case 5: /* AES 5 */ 2841 hdspm->control_register |= 2842 HDSPM_SyncRef2+HDSPM_SyncRef0; 2843 break; 2844 case 6: /* AES 6 */ 2845 hdspm->control_register |= 2846 HDSPM_SyncRef2+HDSPM_SyncRef1; 2847 break; 2848 case 7: /* AES 7 */ 2849 hdspm->control_register |= 2850 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2851 break; 2852 case 8: /* AES 8 */ 2853 hdspm->control_register |= HDSPM_SyncRef3; 2854 break; 2855 case 9: /* TCO */ 2856 hdspm->control_register |= 2857 HDSPM_SyncRef3+HDSPM_SyncRef0; 2858 break; 2859 default: 2860 return -1; 2861 } 2862 2863 break; 2864 2865 case MADI: 2866 case MADIface: 2867 hdspm->control_register &= ~HDSPM_SyncRefMask; 2868 if (hdspm->tco) { 2869 switch (pref) { 2870 case 0: /* WC */ 2871 break; 2872 case 1: /* MADI */ 2873 hdspm->control_register |= HDSPM_SyncRef0; 2874 break; 2875 case 2: /* TCO */ 2876 hdspm->control_register |= HDSPM_SyncRef1; 2877 break; 2878 case 3: /* SYNC_IN */ 2879 hdspm->control_register |= 2880 HDSPM_SyncRef0+HDSPM_SyncRef1; 2881 break; 2882 default: 2883 return -1; 2884 } 2885 } else { 2886 switch (pref) { 2887 case 0: /* WC */ 2888 break; 2889 case 1: /* MADI */ 2890 hdspm->control_register |= HDSPM_SyncRef0; 2891 break; 2892 case 2: /* SYNC_IN */ 2893 hdspm->control_register |= 2894 HDSPM_SyncRef0+HDSPM_SyncRef1; 2895 break; 2896 default: 2897 return -1; 2898 } 2899 } 2900 2901 break; 2902 2903 case RayDAT: 2904 if (hdspm->tco) { 2905 switch (pref) { 2906 case 0: p = 0; break; /* WC */ 2907 case 1: p = 3; break; /* ADAT 1 */ 2908 case 2: p = 4; break; /* ADAT 2 */ 2909 case 3: p = 5; break; /* ADAT 3 */ 2910 case 4: p = 6; break; /* ADAT 4 */ 2911 case 5: p = 1; break; /* AES */ 2912 case 6: p = 2; break; /* SPDIF */ 2913 case 7: p = 9; break; /* TCO */ 2914 case 8: p = 10; break; /* SYNC_IN */ 2915 default: return -1; 2916 } 2917 } else { 2918 switch (pref) { 2919 case 0: p = 0; break; /* WC */ 2920 case 1: p = 3; break; /* ADAT 1 */ 2921 case 2: p = 4; break; /* ADAT 2 */ 2922 case 3: p = 5; break; /* ADAT 3 */ 2923 case 4: p = 6; break; /* ADAT 4 */ 2924 case 5: p = 1; break; /* AES */ 2925 case 6: p = 2; break; /* SPDIF */ 2926 case 7: p = 10; break; /* SYNC_IN */ 2927 default: return -1; 2928 } 2929 } 2930 break; 2931 2932 case AIO: 2933 if (hdspm->tco) { 2934 switch (pref) { 2935 case 0: p = 0; break; /* WC */ 2936 case 1: p = 3; break; /* ADAT */ 2937 case 2: p = 1; break; /* AES */ 2938 case 3: p = 2; break; /* SPDIF */ 2939 case 4: p = 9; break; /* TCO */ 2940 case 5: p = 10; break; /* SYNC_IN */ 2941 default: return -1; 2942 } 2943 } else { 2944 switch (pref) { 2945 case 0: p = 0; break; /* WC */ 2946 case 1: p = 3; break; /* ADAT */ 2947 case 2: p = 1; break; /* AES */ 2948 case 3: p = 2; break; /* SPDIF */ 2949 case 4: p = 10; break; /* SYNC_IN */ 2950 default: return -1; 2951 } 2952 } 2953 break; 2954 } 2955 2956 switch (hdspm->io_type) { 2957 case RayDAT: 2958 case AIO: 2959 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2960 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2961 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2962 break; 2963 2964 case MADI: 2965 case MADIface: 2966 case AES32: 2967 hdspm_write(hdspm, HDSPM_controlRegister, 2968 hdspm->control_register); 2969 } 2970 2971 return 0; 2972 } 2973 2974 2975 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2976 struct snd_ctl_elem_info *uinfo) 2977 { 2978 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2979 2980 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync); 2981 2982 return 0; 2983 } 2984 2985 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2986 struct snd_ctl_elem_value *ucontrol) 2987 { 2988 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2989 int psf = hdspm_pref_sync_ref(hdspm); 2990 2991 if (psf >= 0) { 2992 ucontrol->value.enumerated.item[0] = psf; 2993 return 0; 2994 } 2995 2996 return -1; 2997 } 2998 2999 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 3000 struct snd_ctl_elem_value *ucontrol) 3001 { 3002 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3003 int val, change = 0; 3004 3005 if (!snd_hdspm_use_is_exclusive(hdspm)) 3006 return -EBUSY; 3007 3008 val = ucontrol->value.enumerated.item[0]; 3009 3010 if (val < 0) 3011 val = 0; 3012 else if (val >= hdspm->texts_autosync_items) 3013 val = hdspm->texts_autosync_items-1; 3014 3015 spin_lock_irq(&hdspm->lock); 3016 if (val != hdspm_pref_sync_ref(hdspm)) 3017 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 3018 3019 spin_unlock_irq(&hdspm->lock); 3020 return change; 3021 } 3022 3023 3024 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 3025 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3026 .name = xname, \ 3027 .index = xindex, \ 3028 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 3029 .info = snd_hdspm_info_autosync_ref, \ 3030 .get = snd_hdspm_get_autosync_ref, \ 3031 } 3032 3033 static int hdspm_autosync_ref(struct hdspm *hdspm) 3034 { 3035 /* This looks at the autosync selected sync reference */ 3036 if (AES32 == hdspm->io_type) { 3037 3038 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 3039 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF; 3040 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) && 3041 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) { 3042 return syncref; 3043 } 3044 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 3045 3046 } else if (MADI == hdspm->io_type) { 3047 3048 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3049 switch (status2 & HDSPM_SelSyncRefMask) { 3050 case HDSPM_SelSyncRef_WORD: 3051 return HDSPM_AUTOSYNC_FROM_WORD; 3052 case HDSPM_SelSyncRef_MADI: 3053 return HDSPM_AUTOSYNC_FROM_MADI; 3054 case HDSPM_SelSyncRef_TCO: 3055 return HDSPM_AUTOSYNC_FROM_TCO; 3056 case HDSPM_SelSyncRef_SyncIn: 3057 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 3058 case HDSPM_SelSyncRef_NVALID: 3059 return HDSPM_AUTOSYNC_FROM_NONE; 3060 default: 3061 return HDSPM_AUTOSYNC_FROM_NONE; 3062 } 3063 3064 } 3065 return 0; 3066 } 3067 3068 3069 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 3070 struct snd_ctl_elem_info *uinfo) 3071 { 3072 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3073 3074 if (AES32 == hdspm->io_type) { 3075 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3", 3076 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"}; 3077 3078 ENUMERATED_CTL_INFO(uinfo, texts); 3079 } else if (MADI == hdspm->io_type) { 3080 static const char *const texts[] = {"Word Clock", "MADI", "TCO", 3081 "Sync In", "None" }; 3082 3083 ENUMERATED_CTL_INFO(uinfo, texts); 3084 } 3085 return 0; 3086 } 3087 3088 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 3089 struct snd_ctl_elem_value *ucontrol) 3090 { 3091 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3092 3093 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 3094 return 0; 3095 } 3096 3097 3098 3099 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \ 3100 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3101 .name = xname, \ 3102 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3103 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3104 .info = snd_hdspm_info_tco_video_input_format, \ 3105 .get = snd_hdspm_get_tco_video_input_format, \ 3106 } 3107 3108 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol, 3109 struct snd_ctl_elem_info *uinfo) 3110 { 3111 static const char *const texts[] = {"No video", "NTSC", "PAL"}; 3112 ENUMERATED_CTL_INFO(uinfo, texts); 3113 return 0; 3114 } 3115 3116 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol, 3117 struct snd_ctl_elem_value *ucontrol) 3118 { 3119 u32 status; 3120 int ret = 0; 3121 3122 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3123 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3124 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC | 3125 HDSPM_TCO1_Video_Input_Format_PAL)) { 3126 case HDSPM_TCO1_Video_Input_Format_NTSC: 3127 /* ntsc */ 3128 ret = 1; 3129 break; 3130 case HDSPM_TCO1_Video_Input_Format_PAL: 3131 /* pal */ 3132 ret = 2; 3133 break; 3134 default: 3135 /* no video */ 3136 ret = 0; 3137 break; 3138 } 3139 ucontrol->value.enumerated.item[0] = ret; 3140 return 0; 3141 } 3142 3143 3144 3145 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \ 3146 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3147 .name = xname, \ 3148 .access = SNDRV_CTL_ELEM_ACCESS_READ |\ 3149 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3150 .info = snd_hdspm_info_tco_ltc_frames, \ 3151 .get = snd_hdspm_get_tco_ltc_frames, \ 3152 } 3153 3154 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3155 struct snd_ctl_elem_info *uinfo) 3156 { 3157 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps", 3158 "30 fps"}; 3159 ENUMERATED_CTL_INFO(uinfo, texts); 3160 return 0; 3161 } 3162 3163 static int hdspm_tco_ltc_frames(struct hdspm *hdspm) 3164 { 3165 u32 status; 3166 int ret = 0; 3167 3168 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3169 if (status & HDSPM_TCO1_LTC_Input_valid) { 3170 switch (status & (HDSPM_TCO1_LTC_Format_LSB | 3171 HDSPM_TCO1_LTC_Format_MSB)) { 3172 case 0: 3173 /* 24 fps */ 3174 ret = fps_24; 3175 break; 3176 case HDSPM_TCO1_LTC_Format_LSB: 3177 /* 25 fps */ 3178 ret = fps_25; 3179 break; 3180 case HDSPM_TCO1_LTC_Format_MSB: 3181 /* 29.97 fps */ 3182 ret = fps_2997; 3183 break; 3184 default: 3185 /* 30 fps */ 3186 ret = fps_30; 3187 break; 3188 } 3189 } 3190 3191 return ret; 3192 } 3193 3194 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol, 3195 struct snd_ctl_elem_value *ucontrol) 3196 { 3197 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3198 3199 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm); 3200 return 0; 3201 } 3202 3203 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 3204 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3205 .name = xname, \ 3206 .private_value = xindex, \ 3207 .info = snd_hdspm_info_toggle_setting, \ 3208 .get = snd_hdspm_get_toggle_setting, \ 3209 .put = snd_hdspm_put_toggle_setting \ 3210 } 3211 3212 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 3213 { 3214 u32 reg; 3215 3216 if (hdspm_is_raydat_or_aio(hdspm)) 3217 reg = hdspm->settings_register; 3218 else 3219 reg = hdspm->control_register; 3220 3221 return (reg & regmask) ? 1 : 0; 3222 } 3223 3224 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 3225 { 3226 u32 *reg; 3227 u32 target_reg; 3228 3229 if (hdspm_is_raydat_or_aio(hdspm)) { 3230 reg = &(hdspm->settings_register); 3231 target_reg = HDSPM_WR_SETTINGS; 3232 } else { 3233 reg = &(hdspm->control_register); 3234 target_reg = HDSPM_controlRegister; 3235 } 3236 3237 if (out) 3238 *reg |= regmask; 3239 else 3240 *reg &= ~regmask; 3241 3242 hdspm_write(hdspm, target_reg, *reg); 3243 3244 return 0; 3245 } 3246 3247 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 3248 3249 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 3250 struct snd_ctl_elem_value *ucontrol) 3251 { 3252 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3253 u32 regmask = kcontrol->private_value; 3254 3255 spin_lock_irq(&hdspm->lock); 3256 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 3257 spin_unlock_irq(&hdspm->lock); 3258 return 0; 3259 } 3260 3261 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 3262 struct snd_ctl_elem_value *ucontrol) 3263 { 3264 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3265 u32 regmask = kcontrol->private_value; 3266 int change; 3267 unsigned int val; 3268 3269 if (!snd_hdspm_use_is_exclusive(hdspm)) 3270 return -EBUSY; 3271 val = ucontrol->value.integer.value[0] & 1; 3272 spin_lock_irq(&hdspm->lock); 3273 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 3274 hdspm_set_toggle_setting(hdspm, regmask, val); 3275 spin_unlock_irq(&hdspm->lock); 3276 return change; 3277 } 3278 3279 #define HDSPM_INPUT_SELECT(xname, xindex) \ 3280 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3281 .name = xname, \ 3282 .index = xindex, \ 3283 .info = snd_hdspm_info_input_select, \ 3284 .get = snd_hdspm_get_input_select, \ 3285 .put = snd_hdspm_put_input_select \ 3286 } 3287 3288 static int hdspm_input_select(struct hdspm * hdspm) 3289 { 3290 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3291 } 3292 3293 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3294 { 3295 if (out) 3296 hdspm->control_register |= HDSPM_InputSelect0; 3297 else 3298 hdspm->control_register &= ~HDSPM_InputSelect0; 3299 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3300 3301 return 0; 3302 } 3303 3304 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3305 struct snd_ctl_elem_info *uinfo) 3306 { 3307 static const char *const texts[] = { "optical", "coaxial" }; 3308 ENUMERATED_CTL_INFO(uinfo, texts); 3309 return 0; 3310 } 3311 3312 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3313 struct snd_ctl_elem_value *ucontrol) 3314 { 3315 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3316 3317 spin_lock_irq(&hdspm->lock); 3318 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3319 spin_unlock_irq(&hdspm->lock); 3320 return 0; 3321 } 3322 3323 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3324 struct snd_ctl_elem_value *ucontrol) 3325 { 3326 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3327 int change; 3328 unsigned int val; 3329 3330 if (!snd_hdspm_use_is_exclusive(hdspm)) 3331 return -EBUSY; 3332 val = ucontrol->value.integer.value[0] & 1; 3333 spin_lock_irq(&hdspm->lock); 3334 change = (int) val != hdspm_input_select(hdspm); 3335 hdspm_set_input_select(hdspm, val); 3336 spin_unlock_irq(&hdspm->lock); 3337 return change; 3338 } 3339 3340 3341 #define HDSPM_DS_WIRE(xname, xindex) \ 3342 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3343 .name = xname, \ 3344 .index = xindex, \ 3345 .info = snd_hdspm_info_ds_wire, \ 3346 .get = snd_hdspm_get_ds_wire, \ 3347 .put = snd_hdspm_put_ds_wire \ 3348 } 3349 3350 static int hdspm_ds_wire(struct hdspm * hdspm) 3351 { 3352 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3353 } 3354 3355 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3356 { 3357 if (ds) 3358 hdspm->control_register |= HDSPM_DS_DoubleWire; 3359 else 3360 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3361 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3362 3363 return 0; 3364 } 3365 3366 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3367 struct snd_ctl_elem_info *uinfo) 3368 { 3369 static const char *const texts[] = { "Single", "Double" }; 3370 ENUMERATED_CTL_INFO(uinfo, texts); 3371 return 0; 3372 } 3373 3374 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3375 struct snd_ctl_elem_value *ucontrol) 3376 { 3377 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3378 3379 spin_lock_irq(&hdspm->lock); 3380 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3381 spin_unlock_irq(&hdspm->lock); 3382 return 0; 3383 } 3384 3385 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3386 struct snd_ctl_elem_value *ucontrol) 3387 { 3388 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3389 int change; 3390 unsigned int val; 3391 3392 if (!snd_hdspm_use_is_exclusive(hdspm)) 3393 return -EBUSY; 3394 val = ucontrol->value.integer.value[0] & 1; 3395 spin_lock_irq(&hdspm->lock); 3396 change = (int) val != hdspm_ds_wire(hdspm); 3397 hdspm_set_ds_wire(hdspm, val); 3398 spin_unlock_irq(&hdspm->lock); 3399 return change; 3400 } 3401 3402 3403 #define HDSPM_QS_WIRE(xname, xindex) \ 3404 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3405 .name = xname, \ 3406 .index = xindex, \ 3407 .info = snd_hdspm_info_qs_wire, \ 3408 .get = snd_hdspm_get_qs_wire, \ 3409 .put = snd_hdspm_put_qs_wire \ 3410 } 3411 3412 static int hdspm_qs_wire(struct hdspm * hdspm) 3413 { 3414 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3415 return 1; 3416 if (hdspm->control_register & HDSPM_QS_QuadWire) 3417 return 2; 3418 return 0; 3419 } 3420 3421 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3422 { 3423 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3424 switch (mode) { 3425 case 0: 3426 break; 3427 case 1: 3428 hdspm->control_register |= HDSPM_QS_DoubleWire; 3429 break; 3430 case 2: 3431 hdspm->control_register |= HDSPM_QS_QuadWire; 3432 break; 3433 } 3434 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3435 3436 return 0; 3437 } 3438 3439 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3440 struct snd_ctl_elem_info *uinfo) 3441 { 3442 static const char *const texts[] = { "Single", "Double", "Quad" }; 3443 ENUMERATED_CTL_INFO(uinfo, texts); 3444 return 0; 3445 } 3446 3447 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3448 struct snd_ctl_elem_value *ucontrol) 3449 { 3450 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3451 3452 spin_lock_irq(&hdspm->lock); 3453 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3454 spin_unlock_irq(&hdspm->lock); 3455 return 0; 3456 } 3457 3458 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3459 struct snd_ctl_elem_value *ucontrol) 3460 { 3461 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3462 int change; 3463 int val; 3464 3465 if (!snd_hdspm_use_is_exclusive(hdspm)) 3466 return -EBUSY; 3467 val = ucontrol->value.integer.value[0]; 3468 if (val < 0) 3469 val = 0; 3470 if (val > 2) 3471 val = 2; 3472 spin_lock_irq(&hdspm->lock); 3473 change = val != hdspm_qs_wire(hdspm); 3474 hdspm_set_qs_wire(hdspm, val); 3475 spin_unlock_irq(&hdspm->lock); 3476 return change; 3477 } 3478 3479 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \ 3480 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3481 .name = xname, \ 3482 .private_value = xindex, \ 3483 .info = snd_hdspm_info_tristate, \ 3484 .get = snd_hdspm_get_tristate, \ 3485 .put = snd_hdspm_put_tristate \ 3486 } 3487 3488 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask) 3489 { 3490 u32 reg = hdspm->settings_register & (regmask * 3); 3491 return reg / regmask; 3492 } 3493 3494 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask) 3495 { 3496 hdspm->settings_register &= ~(regmask * 3); 3497 hdspm->settings_register |= (regmask * mode); 3498 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 3499 3500 return 0; 3501 } 3502 3503 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol, 3504 struct snd_ctl_elem_info *uinfo) 3505 { 3506 u32 regmask = kcontrol->private_value; 3507 3508 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" }; 3509 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" }; 3510 3511 switch (regmask) { 3512 case HDSPM_c0_Input0: 3513 ENUMERATED_CTL_INFO(uinfo, texts_spdif); 3514 break; 3515 default: 3516 ENUMERATED_CTL_INFO(uinfo, texts_levels); 3517 break; 3518 } 3519 return 0; 3520 } 3521 3522 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol, 3523 struct snd_ctl_elem_value *ucontrol) 3524 { 3525 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3526 u32 regmask = kcontrol->private_value; 3527 3528 spin_lock_irq(&hdspm->lock); 3529 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask); 3530 spin_unlock_irq(&hdspm->lock); 3531 return 0; 3532 } 3533 3534 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol, 3535 struct snd_ctl_elem_value *ucontrol) 3536 { 3537 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3538 u32 regmask = kcontrol->private_value; 3539 int change; 3540 int val; 3541 3542 if (!snd_hdspm_use_is_exclusive(hdspm)) 3543 return -EBUSY; 3544 val = ucontrol->value.integer.value[0]; 3545 if (val < 0) 3546 val = 0; 3547 if (val > 2) 3548 val = 2; 3549 3550 spin_lock_irq(&hdspm->lock); 3551 change = val != hdspm_tristate(hdspm, regmask); 3552 hdspm_set_tristate(hdspm, val, regmask); 3553 spin_unlock_irq(&hdspm->lock); 3554 return change; 3555 } 3556 3557 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3558 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3559 .name = xname, \ 3560 .index = xindex, \ 3561 .info = snd_hdspm_info_madi_speedmode, \ 3562 .get = snd_hdspm_get_madi_speedmode, \ 3563 .put = snd_hdspm_put_madi_speedmode \ 3564 } 3565 3566 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3567 { 3568 if (hdspm->control_register & HDSPM_QuadSpeed) 3569 return 2; 3570 if (hdspm->control_register & HDSPM_DoubleSpeed) 3571 return 1; 3572 return 0; 3573 } 3574 3575 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3576 { 3577 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3578 switch (mode) { 3579 case 0: 3580 break; 3581 case 1: 3582 hdspm->control_register |= HDSPM_DoubleSpeed; 3583 break; 3584 case 2: 3585 hdspm->control_register |= HDSPM_QuadSpeed; 3586 break; 3587 } 3588 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3589 3590 return 0; 3591 } 3592 3593 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3594 struct snd_ctl_elem_info *uinfo) 3595 { 3596 static const char *const texts[] = { "Single", "Double", "Quad" }; 3597 ENUMERATED_CTL_INFO(uinfo, texts); 3598 return 0; 3599 } 3600 3601 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3602 struct snd_ctl_elem_value *ucontrol) 3603 { 3604 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3605 3606 spin_lock_irq(&hdspm->lock); 3607 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3608 spin_unlock_irq(&hdspm->lock); 3609 return 0; 3610 } 3611 3612 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3613 struct snd_ctl_elem_value *ucontrol) 3614 { 3615 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3616 int change; 3617 int val; 3618 3619 if (!snd_hdspm_use_is_exclusive(hdspm)) 3620 return -EBUSY; 3621 val = ucontrol->value.integer.value[0]; 3622 if (val < 0) 3623 val = 0; 3624 if (val > 2) 3625 val = 2; 3626 spin_lock_irq(&hdspm->lock); 3627 change = val != hdspm_madi_speedmode(hdspm); 3628 hdspm_set_madi_speedmode(hdspm, val); 3629 spin_unlock_irq(&hdspm->lock); 3630 return change; 3631 } 3632 3633 #define HDSPM_MIXER(xname, xindex) \ 3634 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3635 .name = xname, \ 3636 .index = xindex, \ 3637 .device = 0, \ 3638 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3639 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3640 .info = snd_hdspm_info_mixer, \ 3641 .get = snd_hdspm_get_mixer, \ 3642 .put = snd_hdspm_put_mixer \ 3643 } 3644 3645 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3646 struct snd_ctl_elem_info *uinfo) 3647 { 3648 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3649 uinfo->count = 3; 3650 uinfo->value.integer.min = 0; 3651 uinfo->value.integer.max = 65535; 3652 uinfo->value.integer.step = 1; 3653 return 0; 3654 } 3655 3656 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3657 struct snd_ctl_elem_value *ucontrol) 3658 { 3659 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3660 int source; 3661 int destination; 3662 3663 source = ucontrol->value.integer.value[0]; 3664 if (source < 0) 3665 source = 0; 3666 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3667 source = 2 * HDSPM_MAX_CHANNELS - 1; 3668 3669 destination = ucontrol->value.integer.value[1]; 3670 if (destination < 0) 3671 destination = 0; 3672 else if (destination >= HDSPM_MAX_CHANNELS) 3673 destination = HDSPM_MAX_CHANNELS - 1; 3674 3675 spin_lock_irq(&hdspm->lock); 3676 if (source >= HDSPM_MAX_CHANNELS) 3677 ucontrol->value.integer.value[2] = 3678 hdspm_read_pb_gain(hdspm, destination, 3679 source - HDSPM_MAX_CHANNELS); 3680 else 3681 ucontrol->value.integer.value[2] = 3682 hdspm_read_in_gain(hdspm, destination, source); 3683 3684 spin_unlock_irq(&hdspm->lock); 3685 3686 return 0; 3687 } 3688 3689 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3690 struct snd_ctl_elem_value *ucontrol) 3691 { 3692 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3693 int change; 3694 int source; 3695 int destination; 3696 int gain; 3697 3698 if (!snd_hdspm_use_is_exclusive(hdspm)) 3699 return -EBUSY; 3700 3701 source = ucontrol->value.integer.value[0]; 3702 destination = ucontrol->value.integer.value[1]; 3703 3704 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3705 return -1; 3706 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3707 return -1; 3708 3709 gain = ucontrol->value.integer.value[2]; 3710 3711 spin_lock_irq(&hdspm->lock); 3712 3713 if (source >= HDSPM_MAX_CHANNELS) 3714 change = gain != hdspm_read_pb_gain(hdspm, destination, 3715 source - 3716 HDSPM_MAX_CHANNELS); 3717 else 3718 change = gain != hdspm_read_in_gain(hdspm, destination, 3719 source); 3720 3721 if (change) { 3722 if (source >= HDSPM_MAX_CHANNELS) 3723 hdspm_write_pb_gain(hdspm, destination, 3724 source - HDSPM_MAX_CHANNELS, 3725 gain); 3726 else 3727 hdspm_write_in_gain(hdspm, destination, source, 3728 gain); 3729 } 3730 spin_unlock_irq(&hdspm->lock); 3731 3732 return change; 3733 } 3734 3735 /* The simple mixer control(s) provide gain control for the 3736 basic 1:1 mappings of playback streams to output 3737 streams. 3738 */ 3739 3740 #define HDSPM_PLAYBACK_MIXER \ 3741 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3742 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3743 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3744 .info = snd_hdspm_info_playback_mixer, \ 3745 .get = snd_hdspm_get_playback_mixer, \ 3746 .put = snd_hdspm_put_playback_mixer \ 3747 } 3748 3749 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3750 struct snd_ctl_elem_info *uinfo) 3751 { 3752 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3753 uinfo->count = 1; 3754 uinfo->value.integer.min = 0; 3755 uinfo->value.integer.max = 64; 3756 uinfo->value.integer.step = 1; 3757 return 0; 3758 } 3759 3760 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3761 struct snd_ctl_elem_value *ucontrol) 3762 { 3763 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3764 int channel; 3765 3766 channel = ucontrol->id.index - 1; 3767 3768 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3769 return -EINVAL; 3770 3771 spin_lock_irq(&hdspm->lock); 3772 ucontrol->value.integer.value[0] = 3773 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3774 spin_unlock_irq(&hdspm->lock); 3775 3776 return 0; 3777 } 3778 3779 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3780 struct snd_ctl_elem_value *ucontrol) 3781 { 3782 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3783 int change; 3784 int channel; 3785 int gain; 3786 3787 if (!snd_hdspm_use_is_exclusive(hdspm)) 3788 return -EBUSY; 3789 3790 channel = ucontrol->id.index - 1; 3791 3792 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3793 return -EINVAL; 3794 3795 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3796 3797 spin_lock_irq(&hdspm->lock); 3798 change = 3799 gain != hdspm_read_pb_gain(hdspm, channel, 3800 channel); 3801 if (change) 3802 hdspm_write_pb_gain(hdspm, channel, channel, 3803 gain); 3804 spin_unlock_irq(&hdspm->lock); 3805 return change; 3806 } 3807 3808 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3809 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3810 .name = xname, \ 3811 .private_value = xindex, \ 3812 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3813 .info = snd_hdspm_info_sync_check, \ 3814 .get = snd_hdspm_get_sync_check \ 3815 } 3816 3817 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3818 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3819 .name = xname, \ 3820 .private_value = xindex, \ 3821 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3822 .info = snd_hdspm_tco_info_lock_check, \ 3823 .get = snd_hdspm_get_sync_check \ 3824 } 3825 3826 3827 3828 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3829 struct snd_ctl_elem_info *uinfo) 3830 { 3831 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3832 ENUMERATED_CTL_INFO(uinfo, texts); 3833 return 0; 3834 } 3835 3836 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3837 struct snd_ctl_elem_info *uinfo) 3838 { 3839 static const char *const texts[] = { "No Lock", "Lock" }; 3840 ENUMERATED_CTL_INFO(uinfo, texts); 3841 return 0; 3842 } 3843 3844 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3845 { 3846 int status, status2; 3847 3848 switch (hdspm->io_type) { 3849 case AES32: 3850 status = hdspm_read(hdspm, HDSPM_statusRegister); 3851 if (status & HDSPM_AES32_wcLock) { 3852 if (status & HDSPM_AES32_wcSync) 3853 return 2; 3854 else 3855 return 1; 3856 } 3857 return 0; 3858 break; 3859 3860 case MADI: 3861 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3862 if (status2 & HDSPM_wcLock) { 3863 if (status2 & HDSPM_wcSync) 3864 return 2; 3865 else 3866 return 1; 3867 } 3868 return 0; 3869 break; 3870 3871 case RayDAT: 3872 case AIO: 3873 status = hdspm_read(hdspm, HDSPM_statusRegister); 3874 3875 if (status & 0x2000000) 3876 return 2; 3877 else if (status & 0x1000000) 3878 return 1; 3879 return 0; 3880 3881 break; 3882 3883 case MADIface: 3884 break; 3885 } 3886 3887 3888 return 3; 3889 } 3890 3891 3892 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3893 { 3894 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3895 if (status & HDSPM_madiLock) { 3896 if (status & HDSPM_madiSync) 3897 return 2; 3898 else 3899 return 1; 3900 } 3901 return 0; 3902 } 3903 3904 3905 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3906 { 3907 int status, lock, sync; 3908 3909 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3910 3911 lock = (status & (0x1<<idx)) ? 1 : 0; 3912 sync = (status & (0x100<<idx)) ? 1 : 0; 3913 3914 if (lock && sync) 3915 return 2; 3916 else if (lock) 3917 return 1; 3918 return 0; 3919 } 3920 3921 3922 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3923 { 3924 int status, lock = 0, sync = 0; 3925 3926 switch (hdspm->io_type) { 3927 case RayDAT: 3928 case AIO: 3929 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3930 lock = (status & 0x400) ? 1 : 0; 3931 sync = (status & 0x800) ? 1 : 0; 3932 break; 3933 3934 case MADI: 3935 status = hdspm_read(hdspm, HDSPM_statusRegister); 3936 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3937 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3938 break; 3939 3940 case AES32: 3941 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3942 lock = (status & 0x100000) ? 1 : 0; 3943 sync = (status & 0x200000) ? 1 : 0; 3944 break; 3945 3946 case MADIface: 3947 break; 3948 } 3949 3950 if (lock && sync) 3951 return 2; 3952 else if (lock) 3953 return 1; 3954 3955 return 0; 3956 } 3957 3958 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3959 { 3960 int status2, lock, sync; 3961 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3962 3963 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3964 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3965 3966 if (sync) 3967 return 2; 3968 else if (lock) 3969 return 1; 3970 return 0; 3971 } 3972 3973 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3974 { 3975 u32 status; 3976 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3977 3978 return (status & mask) ? 1 : 0; 3979 } 3980 3981 3982 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3983 { 3984 int status; 3985 3986 if (hdspm->tco) { 3987 switch (hdspm->io_type) { 3988 case MADI: 3989 status = hdspm_read(hdspm, HDSPM_statusRegister); 3990 if (status & HDSPM_tcoLockMadi) { 3991 if (status & HDSPM_tcoSync) 3992 return 2; 3993 else 3994 return 1; 3995 } 3996 return 0; 3997 case AES32: 3998 status = hdspm_read(hdspm, HDSPM_statusRegister); 3999 if (status & HDSPM_tcoLockAes) { 4000 if (status & HDSPM_tcoSync) 4001 return 2; 4002 else 4003 return 1; 4004 } 4005 return 0; 4006 case RayDAT: 4007 case AIO: 4008 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 4009 4010 if (status & 0x8000000) 4011 return 2; /* Sync */ 4012 if (status & 0x4000000) 4013 return 1; /* Lock */ 4014 return 0; /* No signal */ 4015 4016 default: 4017 break; 4018 } 4019 } 4020 4021 return 3; /* N/A */ 4022 } 4023 4024 4025 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 4026 struct snd_ctl_elem_value *ucontrol) 4027 { 4028 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4029 int val = -1; 4030 4031 switch (hdspm->io_type) { 4032 case RayDAT: 4033 switch (kcontrol->private_value) { 4034 case 0: /* WC */ 4035 val = hdspm_wc_sync_check(hdspm); break; 4036 case 7: /* TCO */ 4037 val = hdspm_tco_sync_check(hdspm); break; 4038 case 8: /* SYNC IN */ 4039 val = hdspm_sync_in_sync_check(hdspm); break; 4040 default: 4041 val = hdspm_s1_sync_check(hdspm, 4042 kcontrol->private_value-1); 4043 } 4044 break; 4045 4046 case AIO: 4047 switch (kcontrol->private_value) { 4048 case 0: /* WC */ 4049 val = hdspm_wc_sync_check(hdspm); break; 4050 case 4: /* TCO */ 4051 val = hdspm_tco_sync_check(hdspm); break; 4052 case 5: /* SYNC IN */ 4053 val = hdspm_sync_in_sync_check(hdspm); break; 4054 default: 4055 val = hdspm_s1_sync_check(hdspm, 4056 kcontrol->private_value-1); 4057 } 4058 break; 4059 4060 case MADI: 4061 switch (kcontrol->private_value) { 4062 case 0: /* WC */ 4063 val = hdspm_wc_sync_check(hdspm); break; 4064 case 1: /* MADI */ 4065 val = hdspm_madi_sync_check(hdspm); break; 4066 case 2: /* TCO */ 4067 val = hdspm_tco_sync_check(hdspm); break; 4068 case 3: /* SYNC_IN */ 4069 val = hdspm_sync_in_sync_check(hdspm); break; 4070 } 4071 break; 4072 4073 case MADIface: 4074 val = hdspm_madi_sync_check(hdspm); /* MADI */ 4075 break; 4076 4077 case AES32: 4078 switch (kcontrol->private_value) { 4079 case 0: /* WC */ 4080 val = hdspm_wc_sync_check(hdspm); break; 4081 case 9: /* TCO */ 4082 val = hdspm_tco_sync_check(hdspm); break; 4083 case 10 /* SYNC IN */: 4084 val = hdspm_sync_in_sync_check(hdspm); break; 4085 default: /* AES1 to AES8 */ 4086 val = hdspm_aes_sync_check(hdspm, 4087 kcontrol->private_value-1); 4088 } 4089 break; 4090 4091 } 4092 4093 if (hdspm->tco) { 4094 switch (kcontrol->private_value) { 4095 case 11: 4096 /* Check TCO for lock state of its current input */ 4097 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 4098 break; 4099 case 12: 4100 /* Check TCO for valid time code on LTC input. */ 4101 val = hdspm_tco_input_check(hdspm, 4102 HDSPM_TCO1_LTC_Input_valid); 4103 break; 4104 default: 4105 break; 4106 } 4107 } 4108 4109 if (-1 == val) 4110 val = 3; 4111 4112 ucontrol->value.enumerated.item[0] = val; 4113 return 0; 4114 } 4115 4116 4117 4118 /* 4119 * TCO controls 4120 */ 4121 static void hdspm_tco_write(struct hdspm *hdspm) 4122 { 4123 unsigned int tc[4] = { 0, 0, 0, 0}; 4124 4125 switch (hdspm->tco->input) { 4126 case 0: 4127 tc[2] |= HDSPM_TCO2_set_input_MSB; 4128 break; 4129 case 1: 4130 tc[2] |= HDSPM_TCO2_set_input_LSB; 4131 break; 4132 default: 4133 break; 4134 } 4135 4136 switch (hdspm->tco->framerate) { 4137 case 1: 4138 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 4139 break; 4140 case 2: 4141 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 4142 break; 4143 case 3: 4144 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 4145 HDSPM_TCO1_set_drop_frame_flag; 4146 break; 4147 case 4: 4148 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4149 HDSPM_TCO1_LTC_Format_MSB; 4150 break; 4151 case 5: 4152 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 4153 HDSPM_TCO1_LTC_Format_MSB + 4154 HDSPM_TCO1_set_drop_frame_flag; 4155 break; 4156 default: 4157 break; 4158 } 4159 4160 switch (hdspm->tco->wordclock) { 4161 case 1: 4162 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 4163 break; 4164 case 2: 4165 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 4166 break; 4167 default: 4168 break; 4169 } 4170 4171 switch (hdspm->tco->samplerate) { 4172 case 1: 4173 tc[2] |= HDSPM_TCO2_set_freq; 4174 break; 4175 case 2: 4176 tc[2] |= HDSPM_TCO2_set_freq_from_app; 4177 break; 4178 default: 4179 break; 4180 } 4181 4182 switch (hdspm->tco->pull) { 4183 case 1: 4184 tc[2] |= HDSPM_TCO2_set_pull_up; 4185 break; 4186 case 2: 4187 tc[2] |= HDSPM_TCO2_set_pull_down; 4188 break; 4189 case 3: 4190 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 4191 break; 4192 case 4: 4193 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 4194 break; 4195 default: 4196 break; 4197 } 4198 4199 if (1 == hdspm->tco->term) { 4200 tc[2] |= HDSPM_TCO2_set_term_75R; 4201 } 4202 4203 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 4204 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 4205 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 4206 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 4207 } 4208 4209 4210 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 4211 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4212 .name = xname, \ 4213 .index = xindex, \ 4214 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4215 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4216 .info = snd_hdspm_info_tco_sample_rate, \ 4217 .get = snd_hdspm_get_tco_sample_rate, \ 4218 .put = snd_hdspm_put_tco_sample_rate \ 4219 } 4220 4221 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 4222 struct snd_ctl_elem_info *uinfo) 4223 { 4224 /* TODO freq from app could be supported here, see tco->samplerate */ 4225 static const char *const texts[] = { "44.1 kHz", "48 kHz" }; 4226 ENUMERATED_CTL_INFO(uinfo, texts); 4227 return 0; 4228 } 4229 4230 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 4231 struct snd_ctl_elem_value *ucontrol) 4232 { 4233 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4234 4235 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 4236 4237 return 0; 4238 } 4239 4240 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 4241 struct snd_ctl_elem_value *ucontrol) 4242 { 4243 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4244 4245 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 4246 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 4247 4248 hdspm_tco_write(hdspm); 4249 4250 return 1; 4251 } 4252 4253 return 0; 4254 } 4255 4256 4257 #define HDSPM_TCO_PULL(xname, xindex) \ 4258 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4259 .name = xname, \ 4260 .index = xindex, \ 4261 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4262 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4263 .info = snd_hdspm_info_tco_pull, \ 4264 .get = snd_hdspm_get_tco_pull, \ 4265 .put = snd_hdspm_put_tco_pull \ 4266 } 4267 4268 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 4269 struct snd_ctl_elem_info *uinfo) 4270 { 4271 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %", 4272 "+ 4 %", "- 4 %" }; 4273 ENUMERATED_CTL_INFO(uinfo, texts); 4274 return 0; 4275 } 4276 4277 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 4278 struct snd_ctl_elem_value *ucontrol) 4279 { 4280 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4281 4282 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 4283 4284 return 0; 4285 } 4286 4287 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 4288 struct snd_ctl_elem_value *ucontrol) 4289 { 4290 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4291 4292 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 4293 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 4294 4295 hdspm_tco_write(hdspm); 4296 4297 return 1; 4298 } 4299 4300 return 0; 4301 } 4302 4303 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 4304 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4305 .name = xname, \ 4306 .index = xindex, \ 4307 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4308 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4309 .info = snd_hdspm_info_tco_wck_conversion, \ 4310 .get = snd_hdspm_get_tco_wck_conversion, \ 4311 .put = snd_hdspm_put_tco_wck_conversion \ 4312 } 4313 4314 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4315 struct snd_ctl_elem_info *uinfo) 4316 { 4317 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 4318 ENUMERATED_CTL_INFO(uinfo, texts); 4319 return 0; 4320 } 4321 4322 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4323 struct snd_ctl_elem_value *ucontrol) 4324 { 4325 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4326 4327 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 4328 4329 return 0; 4330 } 4331 4332 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 4333 struct snd_ctl_elem_value *ucontrol) 4334 { 4335 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4336 4337 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 4338 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 4339 4340 hdspm_tco_write(hdspm); 4341 4342 return 1; 4343 } 4344 4345 return 0; 4346 } 4347 4348 4349 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 4350 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4351 .name = xname, \ 4352 .index = xindex, \ 4353 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4354 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4355 .info = snd_hdspm_info_tco_frame_rate, \ 4356 .get = snd_hdspm_get_tco_frame_rate, \ 4357 .put = snd_hdspm_put_tco_frame_rate \ 4358 } 4359 4360 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 4361 struct snd_ctl_elem_info *uinfo) 4362 { 4363 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps", 4364 "29.97 dfps", "30 fps", "30 dfps" }; 4365 ENUMERATED_CTL_INFO(uinfo, texts); 4366 return 0; 4367 } 4368 4369 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 4370 struct snd_ctl_elem_value *ucontrol) 4371 { 4372 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4373 4374 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4375 4376 return 0; 4377 } 4378 4379 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4380 struct snd_ctl_elem_value *ucontrol) 4381 { 4382 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4383 4384 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4385 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4386 4387 hdspm_tco_write(hdspm); 4388 4389 return 1; 4390 } 4391 4392 return 0; 4393 } 4394 4395 4396 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4397 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4398 .name = xname, \ 4399 .index = xindex, \ 4400 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4401 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4402 .info = snd_hdspm_info_tco_sync_source, \ 4403 .get = snd_hdspm_get_tco_sync_source, \ 4404 .put = snd_hdspm_put_tco_sync_source \ 4405 } 4406 4407 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4408 struct snd_ctl_elem_info *uinfo) 4409 { 4410 static const char *const texts[] = { "LTC", "Video", "WCK" }; 4411 ENUMERATED_CTL_INFO(uinfo, texts); 4412 return 0; 4413 } 4414 4415 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4416 struct snd_ctl_elem_value *ucontrol) 4417 { 4418 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4419 4420 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4421 4422 return 0; 4423 } 4424 4425 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4426 struct snd_ctl_elem_value *ucontrol) 4427 { 4428 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4429 4430 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4431 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4432 4433 hdspm_tco_write(hdspm); 4434 4435 return 1; 4436 } 4437 4438 return 0; 4439 } 4440 4441 4442 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4443 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4444 .name = xname, \ 4445 .index = xindex, \ 4446 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4447 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4448 .info = snd_hdspm_info_tco_word_term, \ 4449 .get = snd_hdspm_get_tco_word_term, \ 4450 .put = snd_hdspm_put_tco_word_term \ 4451 } 4452 4453 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4454 struct snd_ctl_elem_info *uinfo) 4455 { 4456 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4457 uinfo->count = 1; 4458 uinfo->value.integer.min = 0; 4459 uinfo->value.integer.max = 1; 4460 4461 return 0; 4462 } 4463 4464 4465 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4466 struct snd_ctl_elem_value *ucontrol) 4467 { 4468 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4469 4470 ucontrol->value.integer.value[0] = hdspm->tco->term; 4471 4472 return 0; 4473 } 4474 4475 4476 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4477 struct snd_ctl_elem_value *ucontrol) 4478 { 4479 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4480 4481 if (hdspm->tco->term != ucontrol->value.integer.value[0]) { 4482 hdspm->tco->term = ucontrol->value.integer.value[0]; 4483 4484 hdspm_tco_write(hdspm); 4485 4486 return 1; 4487 } 4488 4489 return 0; 4490 } 4491 4492 4493 4494 4495 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4496 HDSPM_MIXER("Mixer", 0), 4497 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4498 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4499 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4500 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4501 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4502 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4503 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4504 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4505 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4506 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4507 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4508 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4509 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4510 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4511 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4512 HDSPM_INPUT_SELECT("Input Select", 0), 4513 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4514 }; 4515 4516 4517 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4518 HDSPM_MIXER("Mixer", 0), 4519 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4520 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4521 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4522 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4523 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4524 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4525 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4526 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4527 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4528 }; 4529 4530 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4531 HDSPM_MIXER("Mixer", 0), 4532 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4533 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4534 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4535 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4536 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4537 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4538 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4539 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4540 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4541 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4542 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4543 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4544 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4545 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4546 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4547 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4548 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5), 4549 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0), 4550 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt), 4551 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4552 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1), 4553 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db), 4554 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48), 4555 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0), 4556 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0), 4557 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0) 4558 4559 /* 4560 HDSPM_INPUT_SELECT("Input Select", 0), 4561 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4562 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4563 HDSPM_SPDIF_IN("SPDIF In", 0); 4564 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4565 HDSPM_INPUT_LEVEL("Input Level", 0); 4566 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4567 HDSPM_PHONES("Phones", 0); 4568 */ 4569 }; 4570 4571 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4572 HDSPM_MIXER("Mixer", 0), 4573 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4574 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4575 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4576 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4577 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4578 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4579 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4580 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4581 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4582 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4583 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4584 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4585 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4586 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4587 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4588 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4589 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4590 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4591 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4592 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4593 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4594 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8), 4595 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro), 4596 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48) 4597 }; 4598 4599 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4600 HDSPM_MIXER("Mixer", 0), 4601 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4602 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4603 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4604 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4605 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4606 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11), 4607 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4608 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4609 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4610 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4611 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4612 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4613 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4614 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4615 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4616 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4617 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4618 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4619 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4620 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4621 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4622 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4623 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4624 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4625 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4626 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4627 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4628 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4629 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4630 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4631 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4632 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4633 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4634 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4635 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4636 }; 4637 4638 4639 4640 /* Control elements for the optional TCO module */ 4641 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4642 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4643 HDSPM_TCO_PULL("TCO Pull", 0), 4644 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4645 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4646 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4647 HDSPM_TCO_WORD_TERM("TCO Word Term", 0), 4648 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11), 4649 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12), 4650 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0), 4651 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0) 4652 }; 4653 4654 4655 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4656 4657 4658 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4659 { 4660 int i; 4661 4662 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4663 if (hdspm->system_sample_rate > 48000) { 4664 hdspm->playback_mixer_ctls[i]->vd[0].access = 4665 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4666 SNDRV_CTL_ELEM_ACCESS_READ | 4667 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4668 } else { 4669 hdspm->playback_mixer_ctls[i]->vd[0].access = 4670 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4671 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4672 } 4673 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4674 SNDRV_CTL_EVENT_MASK_INFO, 4675 &hdspm->playback_mixer_ctls[i]->id); 4676 } 4677 4678 return 0; 4679 } 4680 4681 4682 static int snd_hdspm_create_controls(struct snd_card *card, 4683 struct hdspm *hdspm) 4684 { 4685 unsigned int idx, limit; 4686 int err; 4687 struct snd_kcontrol *kctl; 4688 struct snd_kcontrol_new *list = NULL; 4689 4690 switch (hdspm->io_type) { 4691 case MADI: 4692 list = snd_hdspm_controls_madi; 4693 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4694 break; 4695 case MADIface: 4696 list = snd_hdspm_controls_madiface; 4697 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4698 break; 4699 case AIO: 4700 list = snd_hdspm_controls_aio; 4701 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4702 break; 4703 case RayDAT: 4704 list = snd_hdspm_controls_raydat; 4705 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4706 break; 4707 case AES32: 4708 list = snd_hdspm_controls_aes32; 4709 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4710 break; 4711 } 4712 4713 if (list) { 4714 for (idx = 0; idx < limit; idx++) { 4715 err = snd_ctl_add(card, 4716 snd_ctl_new1(&list[idx], hdspm)); 4717 if (err < 0) 4718 return err; 4719 } 4720 } 4721 4722 4723 /* create simple 1:1 playback mixer controls */ 4724 snd_hdspm_playback_mixer.name = "Chn"; 4725 if (hdspm->system_sample_rate >= 128000) { 4726 limit = hdspm->qs_out_channels; 4727 } else if (hdspm->system_sample_rate >= 64000) { 4728 limit = hdspm->ds_out_channels; 4729 } else { 4730 limit = hdspm->ss_out_channels; 4731 } 4732 for (idx = 0; idx < limit; ++idx) { 4733 snd_hdspm_playback_mixer.index = idx + 1; 4734 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4735 err = snd_ctl_add(card, kctl); 4736 if (err < 0) 4737 return err; 4738 hdspm->playback_mixer_ctls[idx] = kctl; 4739 } 4740 4741 4742 if (hdspm->tco) { 4743 /* add tco control elements */ 4744 list = snd_hdspm_controls_tco; 4745 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4746 for (idx = 0; idx < limit; idx++) { 4747 err = snd_ctl_add(card, 4748 snd_ctl_new1(&list[idx], hdspm)); 4749 if (err < 0) 4750 return err; 4751 } 4752 } 4753 4754 return 0; 4755 } 4756 4757 /*------------------------------------------------------------ 4758 /proc interface 4759 ------------------------------------------------------------*/ 4760 4761 static void 4762 snd_hdspm_proc_read_tco(struct snd_info_entry *entry, 4763 struct snd_info_buffer *buffer) 4764 { 4765 struct hdspm *hdspm = entry->private_data; 4766 unsigned int status, control; 4767 int a, ltc, frames, seconds, minutes, hours; 4768 unsigned int period; 4769 u64 freq_const = 0; 4770 u32 rate; 4771 4772 snd_iprintf(buffer, "--- TCO ---\n"); 4773 4774 status = hdspm_read(hdspm, HDSPM_statusRegister); 4775 control = hdspm->control_register; 4776 4777 4778 if (status & HDSPM_tco_detect) { 4779 snd_iprintf(buffer, "TCO module detected.\n"); 4780 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4781 if (a & HDSPM_TCO1_LTC_Input_valid) { 4782 snd_iprintf(buffer, " LTC valid, "); 4783 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4784 HDSPM_TCO1_LTC_Format_MSB)) { 4785 case 0: 4786 snd_iprintf(buffer, "24 fps, "); 4787 break; 4788 case HDSPM_TCO1_LTC_Format_LSB: 4789 snd_iprintf(buffer, "25 fps, "); 4790 break; 4791 case HDSPM_TCO1_LTC_Format_MSB: 4792 snd_iprintf(buffer, "29.97 fps, "); 4793 break; 4794 default: 4795 snd_iprintf(buffer, "30 fps, "); 4796 break; 4797 } 4798 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4799 snd_iprintf(buffer, "drop frame\n"); 4800 } else { 4801 snd_iprintf(buffer, "full frame\n"); 4802 } 4803 } else { 4804 snd_iprintf(buffer, " no LTC\n"); 4805 } 4806 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4807 snd_iprintf(buffer, " Video: NTSC\n"); 4808 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4809 snd_iprintf(buffer, " Video: PAL\n"); 4810 } else { 4811 snd_iprintf(buffer, " No video\n"); 4812 } 4813 if (a & HDSPM_TCO1_TCO_lock) { 4814 snd_iprintf(buffer, " Sync: lock\n"); 4815 } else { 4816 snd_iprintf(buffer, " Sync: no lock\n"); 4817 } 4818 4819 switch (hdspm->io_type) { 4820 case MADI: 4821 case AES32: 4822 freq_const = 110069313433624ULL; 4823 break; 4824 case RayDAT: 4825 case AIO: 4826 freq_const = 104857600000000ULL; 4827 break; 4828 case MADIface: 4829 break; /* no TCO possible */ 4830 } 4831 4832 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4833 snd_iprintf(buffer, " period: %u\n", period); 4834 4835 4836 /* rate = freq_const/period; */ 4837 rate = div_u64(freq_const, period); 4838 4839 if (control & HDSPM_QuadSpeed) { 4840 rate *= 4; 4841 } else if (control & HDSPM_DoubleSpeed) { 4842 rate *= 2; 4843 } 4844 4845 snd_iprintf(buffer, " Frequency: %u Hz\n", 4846 (unsigned int) rate); 4847 4848 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4849 frames = ltc & 0xF; 4850 ltc >>= 4; 4851 frames += (ltc & 0x3) * 10; 4852 ltc >>= 4; 4853 seconds = ltc & 0xF; 4854 ltc >>= 4; 4855 seconds += (ltc & 0x7) * 10; 4856 ltc >>= 4; 4857 minutes = ltc & 0xF; 4858 ltc >>= 4; 4859 minutes += (ltc & 0x7) * 10; 4860 ltc >>= 4; 4861 hours = ltc & 0xF; 4862 ltc >>= 4; 4863 hours += (ltc & 0x3) * 10; 4864 snd_iprintf(buffer, 4865 " LTC In: %02d:%02d:%02d:%02d\n", 4866 hours, minutes, seconds, frames); 4867 4868 } else { 4869 snd_iprintf(buffer, "No TCO module detected.\n"); 4870 } 4871 } 4872 4873 static void 4874 snd_hdspm_proc_read_madi(struct snd_info_entry *entry, 4875 struct snd_info_buffer *buffer) 4876 { 4877 struct hdspm *hdspm = entry->private_data; 4878 unsigned int status, status2; 4879 4880 char *pref_sync_ref; 4881 char *autosync_ref; 4882 char *system_clock_mode; 4883 int x, x2; 4884 4885 status = hdspm_read(hdspm, HDSPM_statusRegister); 4886 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4887 4888 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4889 hdspm->card_name, hdspm->card->number + 1, 4890 hdspm->firmware_rev, 4891 (status2 & HDSPM_version0) | 4892 (status2 & HDSPM_version1) | (status2 & 4893 HDSPM_version2)); 4894 4895 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4896 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4897 hdspm->serial); 4898 4899 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4900 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4901 4902 snd_iprintf(buffer, "--- System ---\n"); 4903 4904 snd_iprintf(buffer, 4905 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4906 status & HDSPM_audioIRQPending, 4907 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4908 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4909 hdspm->irq_count); 4910 snd_iprintf(buffer, 4911 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4912 "estimated= %ld (bytes)\n", 4913 ((status & HDSPM_BufferID) ? 1 : 0), 4914 (status & HDSPM_BufferPositionMask), 4915 (status & HDSPM_BufferPositionMask) % 4916 (2 * (int)hdspm->period_bytes), 4917 ((status & HDSPM_BufferPositionMask) - 64) % 4918 (2 * (int)hdspm->period_bytes), 4919 (long) hdspm_hw_pointer(hdspm) * 4); 4920 4921 snd_iprintf(buffer, 4922 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4923 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4924 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4925 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4926 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4927 snd_iprintf(buffer, 4928 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4929 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4930 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4931 snd_iprintf(buffer, 4932 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4933 "status2=0x%x\n", 4934 hdspm->control_register, hdspm->control2_register, 4935 status, status2); 4936 4937 4938 snd_iprintf(buffer, "--- Settings ---\n"); 4939 4940 x = hdspm_get_latency(hdspm); 4941 4942 snd_iprintf(buffer, 4943 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4944 x, (unsigned long) hdspm->period_bytes); 4945 4946 snd_iprintf(buffer, "Line out: %s\n", 4947 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4948 4949 snd_iprintf(buffer, 4950 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4951 "Auto Input %s\n", 4952 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4953 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4954 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4955 4956 4957 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4958 system_clock_mode = "AutoSync"; 4959 else 4960 system_clock_mode = "Master"; 4961 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4962 4963 switch (hdspm_pref_sync_ref(hdspm)) { 4964 case HDSPM_SYNC_FROM_WORD: 4965 pref_sync_ref = "Word Clock"; 4966 break; 4967 case HDSPM_SYNC_FROM_MADI: 4968 pref_sync_ref = "MADI Sync"; 4969 break; 4970 case HDSPM_SYNC_FROM_TCO: 4971 pref_sync_ref = "TCO"; 4972 break; 4973 case HDSPM_SYNC_FROM_SYNC_IN: 4974 pref_sync_ref = "Sync In"; 4975 break; 4976 default: 4977 pref_sync_ref = "XXXX Clock"; 4978 break; 4979 } 4980 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4981 pref_sync_ref); 4982 4983 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4984 hdspm->system_sample_rate); 4985 4986 4987 snd_iprintf(buffer, "--- Status:\n"); 4988 4989 x = status & HDSPM_madiSync; 4990 x2 = status2 & HDSPM_wcSync; 4991 4992 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4993 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4994 "NoLock", 4995 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4996 "NoLock"); 4997 4998 switch (hdspm_autosync_ref(hdspm)) { 4999 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 5000 autosync_ref = "Sync In"; 5001 break; 5002 case HDSPM_AUTOSYNC_FROM_TCO: 5003 autosync_ref = "TCO"; 5004 break; 5005 case HDSPM_AUTOSYNC_FROM_WORD: 5006 autosync_ref = "Word Clock"; 5007 break; 5008 case HDSPM_AUTOSYNC_FROM_MADI: 5009 autosync_ref = "MADI Sync"; 5010 break; 5011 case HDSPM_AUTOSYNC_FROM_NONE: 5012 autosync_ref = "Input not valid"; 5013 break; 5014 default: 5015 autosync_ref = "---"; 5016 break; 5017 } 5018 snd_iprintf(buffer, 5019 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 5020 autosync_ref, hdspm_external_sample_rate(hdspm), 5021 (status & HDSPM_madiFreqMask) >> 22, 5022 (status2 & HDSPM_wcFreqMask) >> 5); 5023 5024 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 5025 (status & HDSPM_AB_int) ? "Coax" : "Optical", 5026 (status & HDSPM_RX_64ch) ? "64 channels" : 5027 "56 channels"); 5028 5029 /* call readout function for TCO specific status */ 5030 snd_hdspm_proc_read_tco(entry, buffer); 5031 5032 snd_iprintf(buffer, "\n"); 5033 } 5034 5035 static void 5036 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 5037 struct snd_info_buffer *buffer) 5038 { 5039 struct hdspm *hdspm = entry->private_data; 5040 unsigned int status; 5041 unsigned int status2; 5042 unsigned int timecode; 5043 unsigned int wcLock, wcSync; 5044 int pref_syncref; 5045 char *autosync_ref; 5046 int x; 5047 5048 status = hdspm_read(hdspm, HDSPM_statusRegister); 5049 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 5050 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 5051 5052 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 5053 hdspm->card_name, hdspm->card->number + 1, 5054 hdspm->firmware_rev); 5055 5056 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 5057 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 5058 5059 snd_iprintf(buffer, "--- System ---\n"); 5060 5061 snd_iprintf(buffer, 5062 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 5063 status & HDSPM_audioIRQPending, 5064 (status & HDSPM_midi0IRQPending) ? 1 : 0, 5065 (status & HDSPM_midi1IRQPending) ? 1 : 0, 5066 hdspm->irq_count); 5067 snd_iprintf(buffer, 5068 "HW pointer: id = %d, rawptr = %d (%d->%d) " 5069 "estimated= %ld (bytes)\n", 5070 ((status & HDSPM_BufferID) ? 1 : 0), 5071 (status & HDSPM_BufferPositionMask), 5072 (status & HDSPM_BufferPositionMask) % 5073 (2 * (int)hdspm->period_bytes), 5074 ((status & HDSPM_BufferPositionMask) - 64) % 5075 (2 * (int)hdspm->period_bytes), 5076 (long) hdspm_hw_pointer(hdspm) * 4); 5077 5078 snd_iprintf(buffer, 5079 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 5080 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 5081 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 5082 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 5083 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 5084 snd_iprintf(buffer, 5085 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 5086 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 5087 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 5088 snd_iprintf(buffer, 5089 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 5090 "status2=0x%x\n", 5091 hdspm->control_register, hdspm->control2_register, 5092 status, status2); 5093 5094 snd_iprintf(buffer, "--- Settings ---\n"); 5095 5096 x = hdspm_get_latency(hdspm); 5097 5098 snd_iprintf(buffer, 5099 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 5100 x, (unsigned long) hdspm->period_bytes); 5101 5102 snd_iprintf(buffer, "Line out: %s\n", 5103 (hdspm-> 5104 control_register & HDSPM_LineOut) ? "on " : "off"); 5105 5106 snd_iprintf(buffer, 5107 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 5108 (hdspm-> 5109 control_register & HDSPM_clr_tms) ? "on" : "off", 5110 (hdspm-> 5111 control_register & HDSPM_Emphasis) ? "on" : "off", 5112 (hdspm-> 5113 control_register & HDSPM_Dolby) ? "on" : "off"); 5114 5115 5116 pref_syncref = hdspm_pref_sync_ref(hdspm); 5117 if (pref_syncref == 0) 5118 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 5119 else 5120 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 5121 pref_syncref); 5122 5123 snd_iprintf(buffer, "System Clock Frequency: %d\n", 5124 hdspm->system_sample_rate); 5125 5126 snd_iprintf(buffer, "Double speed: %s\n", 5127 hdspm->control_register & HDSPM_DS_DoubleWire? 5128 "Double wire" : "Single wire"); 5129 snd_iprintf(buffer, "Quad speed: %s\n", 5130 hdspm->control_register & HDSPM_QS_DoubleWire? 5131 "Double wire" : 5132 hdspm->control_register & HDSPM_QS_QuadWire? 5133 "Quad wire" : "Single wire"); 5134 5135 snd_iprintf(buffer, "--- Status:\n"); 5136 5137 wcLock = status & HDSPM_AES32_wcLock; 5138 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 5139 5140 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 5141 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 5142 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 5143 5144 for (x = 0; x < 8; x++) { 5145 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 5146 x+1, 5147 (status2 & (HDSPM_LockAES >> x)) ? 5148 "Sync " : "No Lock", 5149 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 5150 } 5151 5152 switch (hdspm_autosync_ref(hdspm)) { 5153 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 5154 autosync_ref = "None"; break; 5155 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 5156 autosync_ref = "Word Clock"; break; 5157 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 5158 autosync_ref = "AES1"; break; 5159 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 5160 autosync_ref = "AES2"; break; 5161 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 5162 autosync_ref = "AES3"; break; 5163 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 5164 autosync_ref = "AES4"; break; 5165 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 5166 autosync_ref = "AES5"; break; 5167 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 5168 autosync_ref = "AES6"; break; 5169 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 5170 autosync_ref = "AES7"; break; 5171 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 5172 autosync_ref = "AES8"; break; 5173 case HDSPM_AES32_AUTOSYNC_FROM_TCO: 5174 autosync_ref = "TCO"; break; 5175 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN: 5176 autosync_ref = "Sync In"; break; 5177 default: 5178 autosync_ref = "---"; break; 5179 } 5180 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 5181 5182 /* call readout function for TCO specific status */ 5183 snd_hdspm_proc_read_tco(entry, buffer); 5184 5185 snd_iprintf(buffer, "\n"); 5186 } 5187 5188 static void 5189 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 5190 struct snd_info_buffer *buffer) 5191 { 5192 struct hdspm *hdspm = entry->private_data; 5193 unsigned int status1, status2, status3, i; 5194 unsigned int lock, sync; 5195 5196 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 5197 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 5198 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 5199 5200 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 5201 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 5202 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 5203 5204 5205 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 5206 5207 snd_iprintf(buffer, "Clock mode : %s\n", 5208 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 5209 snd_iprintf(buffer, "System frequency: %d Hz\n", 5210 hdspm_get_system_sample_rate(hdspm)); 5211 5212 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 5213 5214 lock = 0x1; 5215 sync = 0x100; 5216 5217 for (i = 0; i < 8; i++) { 5218 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 5219 i, 5220 (status1 & lock) ? 1 : 0, 5221 (status1 & sync) ? 1 : 0, 5222 texts_freq[(status2 >> (i * 4)) & 0xF]); 5223 5224 lock = lock<<1; 5225 sync = sync<<1; 5226 } 5227 5228 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 5229 (status1 & 0x1000000) ? 1 : 0, 5230 (status1 & 0x2000000) ? 1 : 0, 5231 texts_freq[(status1 >> 16) & 0xF]); 5232 5233 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 5234 (status1 & 0x4000000) ? 1 : 0, 5235 (status1 & 0x8000000) ? 1 : 0, 5236 texts_freq[(status1 >> 20) & 0xF]); 5237 5238 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 5239 (status3 & 0x400) ? 1 : 0, 5240 (status3 & 0x800) ? 1 : 0, 5241 texts_freq[(status2 >> 12) & 0xF]); 5242 5243 } 5244 5245 #ifdef CONFIG_SND_DEBUG 5246 static void 5247 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 5248 struct snd_info_buffer *buffer) 5249 { 5250 struct hdspm *hdspm = entry->private_data; 5251 5252 int j,i; 5253 5254 for (i = 0; i < 256 /* 1024*64 */; i += j) { 5255 snd_iprintf(buffer, "0x%08X: ", i); 5256 for (j = 0; j < 16; j += 4) 5257 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 5258 snd_iprintf(buffer, "\n"); 5259 } 5260 } 5261 #endif 5262 5263 5264 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 5265 struct snd_info_buffer *buffer) 5266 { 5267 struct hdspm *hdspm = entry->private_data; 5268 int i; 5269 5270 snd_iprintf(buffer, "# generated by hdspm\n"); 5271 5272 for (i = 0; i < hdspm->max_channels_in; i++) { 5273 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 5274 } 5275 } 5276 5277 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 5278 struct snd_info_buffer *buffer) 5279 { 5280 struct hdspm *hdspm = entry->private_data; 5281 int i; 5282 5283 snd_iprintf(buffer, "# generated by hdspm\n"); 5284 5285 for (i = 0; i < hdspm->max_channels_out; i++) { 5286 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 5287 } 5288 } 5289 5290 5291 static void snd_hdspm_proc_init(struct hdspm *hdspm) 5292 { 5293 void (*read)(struct snd_info_entry *, struct snd_info_buffer *) = NULL; 5294 5295 switch (hdspm->io_type) { 5296 case AES32: 5297 read = snd_hdspm_proc_read_aes32; 5298 break; 5299 case MADI: 5300 read = snd_hdspm_proc_read_madi; 5301 break; 5302 case MADIface: 5303 /* read = snd_hdspm_proc_read_madiface; */ 5304 break; 5305 case RayDAT: 5306 read = snd_hdspm_proc_read_raydat; 5307 break; 5308 case AIO: 5309 break; 5310 } 5311 5312 snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read); 5313 snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm, 5314 snd_hdspm_proc_ports_in); 5315 snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm, 5316 snd_hdspm_proc_ports_out); 5317 5318 #ifdef CONFIG_SND_DEBUG 5319 /* debug file to read all hdspm registers */ 5320 snd_card_ro_proc_new(hdspm->card, "debug", hdspm, 5321 snd_hdspm_proc_read_debug); 5322 #endif 5323 } 5324 5325 /*------------------------------------------------------------ 5326 hdspm intitialize 5327 ------------------------------------------------------------*/ 5328 5329 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 5330 { 5331 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 5332 hold it (e.g. during module initialization). 5333 */ 5334 5335 /* set defaults: */ 5336 5337 hdspm->settings_register = 0; 5338 5339 switch (hdspm->io_type) { 5340 case MADI: 5341 case MADIface: 5342 hdspm->control_register = 5343 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5344 break; 5345 5346 case RayDAT: 5347 case AIO: 5348 hdspm->settings_register = 0x1 + 0x1000; 5349 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 5350 * line_out */ 5351 hdspm->control_register = 5352 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 5353 break; 5354 5355 case AES32: 5356 hdspm->control_register = 5357 HDSPM_ClockModeMaster | /* Master Clock Mode on */ 5358 hdspm_encode_latency(7) | /* latency max=8192samples */ 5359 HDSPM_SyncRef0 | /* AES1 is syncclock */ 5360 HDSPM_LineOut | /* Analog output in */ 5361 HDSPM_Professional; /* Professional mode */ 5362 break; 5363 } 5364 5365 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5366 5367 if (AES32 == hdspm->io_type) { 5368 /* No control2 register for AES32 */ 5369 #ifdef SNDRV_BIG_ENDIAN 5370 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 5371 #else 5372 hdspm->control2_register = 0; 5373 #endif 5374 5375 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 5376 } 5377 hdspm_compute_period_size(hdspm); 5378 5379 /* silence everything */ 5380 5381 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5382 5383 if (hdspm_is_raydat_or_aio(hdspm)) 5384 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5385 5386 /* set a default rate so that the channel map is set up. */ 5387 hdspm_set_rate(hdspm, 48000, 1); 5388 5389 return 0; 5390 } 5391 5392 5393 /*------------------------------------------------------------ 5394 interrupt 5395 ------------------------------------------------------------*/ 5396 5397 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5398 { 5399 struct hdspm *hdspm = (struct hdspm *) dev_id; 5400 unsigned int status; 5401 int i, audio, midi, schedule = 0; 5402 /* cycles_t now; */ 5403 5404 status = hdspm_read(hdspm, HDSPM_statusRegister); 5405 5406 audio = status & HDSPM_audioIRQPending; 5407 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5408 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5409 5410 /* now = get_cycles(); */ 5411 /* 5412 * LAT_2..LAT_0 period counter (win) counter (mac) 5413 * 6 4096 ~256053425 ~514672358 5414 * 5 2048 ~128024983 ~257373821 5415 * 4 1024 ~64023706 ~128718089 5416 * 3 512 ~32005945 ~64385999 5417 * 2 256 ~16003039 ~32260176 5418 * 1 128 ~7998738 ~16194507 5419 * 0 64 ~3998231 ~8191558 5420 */ 5421 /* 5422 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n", 5423 now-hdspm->last_interrupt, status & 0xFFC0); 5424 hdspm->last_interrupt = now; 5425 */ 5426 5427 if (!audio && !midi) 5428 return IRQ_NONE; 5429 5430 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5431 hdspm->irq_count++; 5432 5433 5434 if (audio) { 5435 if (hdspm->capture_substream) 5436 snd_pcm_period_elapsed(hdspm->capture_substream); 5437 5438 if (hdspm->playback_substream) 5439 snd_pcm_period_elapsed(hdspm->playback_substream); 5440 } 5441 5442 if (midi) { 5443 i = 0; 5444 while (i < hdspm->midiPorts) { 5445 if ((hdspm_read(hdspm, 5446 hdspm->midi[i].statusIn) & 0xff) && 5447 (status & hdspm->midi[i].irq)) { 5448 /* we disable interrupts for this input until 5449 * processing is done 5450 */ 5451 hdspm->control_register &= ~hdspm->midi[i].ie; 5452 hdspm_write(hdspm, HDSPM_controlRegister, 5453 hdspm->control_register); 5454 hdspm->midi[i].pending = 1; 5455 schedule = 1; 5456 } 5457 5458 i++; 5459 } 5460 5461 if (schedule) 5462 tasklet_hi_schedule(&hdspm->midi_tasklet); 5463 } 5464 5465 return IRQ_HANDLED; 5466 } 5467 5468 /*------------------------------------------------------------ 5469 pcm interface 5470 ------------------------------------------------------------*/ 5471 5472 5473 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5474 *substream) 5475 { 5476 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5477 return hdspm_hw_pointer(hdspm); 5478 } 5479 5480 5481 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5482 { 5483 struct snd_pcm_runtime *runtime = substream->runtime; 5484 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5485 struct snd_pcm_substream *other; 5486 5487 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5488 other = hdspm->capture_substream; 5489 else 5490 other = hdspm->playback_substream; 5491 5492 if (hdspm->running) 5493 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5494 else 5495 runtime->status->hw_ptr = 0; 5496 if (other) { 5497 struct snd_pcm_substream *s; 5498 struct snd_pcm_runtime *oruntime = other->runtime; 5499 snd_pcm_group_for_each_entry(s, substream) { 5500 if (s == other) { 5501 oruntime->status->hw_ptr = 5502 runtime->status->hw_ptr; 5503 break; 5504 } 5505 } 5506 } 5507 return 0; 5508 } 5509 5510 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5511 struct snd_pcm_hw_params *params) 5512 { 5513 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5514 int err; 5515 int i; 5516 pid_t this_pid; 5517 pid_t other_pid; 5518 5519 spin_lock_irq(&hdspm->lock); 5520 5521 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5522 this_pid = hdspm->playback_pid; 5523 other_pid = hdspm->capture_pid; 5524 } else { 5525 this_pid = hdspm->capture_pid; 5526 other_pid = hdspm->playback_pid; 5527 } 5528 5529 if (other_pid > 0 && this_pid != other_pid) { 5530 5531 /* The other stream is open, and not by the same 5532 task as this one. Make sure that the parameters 5533 that matter are the same. 5534 */ 5535 5536 if (params_rate(params) != hdspm->system_sample_rate) { 5537 spin_unlock_irq(&hdspm->lock); 5538 _snd_pcm_hw_param_setempty(params, 5539 SNDRV_PCM_HW_PARAM_RATE); 5540 return -EBUSY; 5541 } 5542 5543 if (params_period_size(params) != hdspm->period_bytes / 4) { 5544 spin_unlock_irq(&hdspm->lock); 5545 _snd_pcm_hw_param_setempty(params, 5546 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5547 return -EBUSY; 5548 } 5549 5550 } 5551 /* We're fine. */ 5552 spin_unlock_irq(&hdspm->lock); 5553 5554 /* how to make sure that the rate matches an externally-set one ? */ 5555 5556 spin_lock_irq(&hdspm->lock); 5557 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5558 if (err < 0) { 5559 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err); 5560 spin_unlock_irq(&hdspm->lock); 5561 _snd_pcm_hw_param_setempty(params, 5562 SNDRV_PCM_HW_PARAM_RATE); 5563 return err; 5564 } 5565 spin_unlock_irq(&hdspm->lock); 5566 5567 err = hdspm_set_interrupt_interval(hdspm, 5568 params_period_size(params)); 5569 if (err < 0) { 5570 dev_info(hdspm->card->dev, 5571 "err on hdspm_set_interrupt_interval: %d\n", err); 5572 _snd_pcm_hw_param_setempty(params, 5573 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5574 return err; 5575 } 5576 5577 /* Memory allocation, takashi's method, dont know if we should 5578 * spinlock 5579 */ 5580 /* malloc all buffer even if not enabled to get sure */ 5581 /* Update for MADI rev 204: we need to allocate for all channels, 5582 * otherwise it doesn't work at 96kHz */ 5583 5584 err = 5585 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5586 if (err < 0) { 5587 dev_info(hdspm->card->dev, 5588 "err on snd_pcm_lib_malloc_pages: %d\n", err); 5589 return err; 5590 } 5591 5592 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5593 5594 for (i = 0; i < params_channels(params); ++i) { 5595 int c = hdspm->channel_map_out[i]; 5596 5597 if (c < 0) 5598 continue; /* just make sure */ 5599 hdspm_set_channel_dma_addr(hdspm, substream, 5600 HDSPM_pageAddressBufferOut, 5601 c); 5602 snd_hdspm_enable_out(hdspm, c, 1); 5603 } 5604 5605 hdspm->playback_buffer = 5606 (unsigned char *) substream->runtime->dma_area; 5607 dev_dbg(hdspm->card->dev, 5608 "Allocated sample buffer for playback at %p\n", 5609 hdspm->playback_buffer); 5610 } else { 5611 for (i = 0; i < params_channels(params); ++i) { 5612 int c = hdspm->channel_map_in[i]; 5613 5614 if (c < 0) 5615 continue; 5616 hdspm_set_channel_dma_addr(hdspm, substream, 5617 HDSPM_pageAddressBufferIn, 5618 c); 5619 snd_hdspm_enable_in(hdspm, c, 1); 5620 } 5621 5622 hdspm->capture_buffer = 5623 (unsigned char *) substream->runtime->dma_area; 5624 dev_dbg(hdspm->card->dev, 5625 "Allocated sample buffer for capture at %p\n", 5626 hdspm->capture_buffer); 5627 } 5628 5629 /* 5630 dev_dbg(hdspm->card->dev, 5631 "Allocated sample buffer for %s at 0x%08X\n", 5632 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5633 "playback" : "capture", 5634 snd_pcm_sgbuf_get_addr(substream, 0)); 5635 */ 5636 /* 5637 dev_dbg(hdspm->card->dev, 5638 "set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5639 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5640 "playback" : "capture", 5641 params_rate(params), params_channels(params), 5642 params_buffer_size(params)); 5643 */ 5644 5645 5646 /* For AES cards, the float format bit is the same as the 5647 * preferred sync reference. Since we don't want to break 5648 * sync settings, we have to skip the remaining part of this 5649 * function. 5650 */ 5651 if (hdspm->io_type == AES32) { 5652 return 0; 5653 } 5654 5655 5656 /* Switch to native float format if requested */ 5657 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5658 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5659 dev_info(hdspm->card->dev, 5660 "Switching to native 32bit LE float format.\n"); 5661 5662 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5663 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5664 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5665 dev_info(hdspm->card->dev, 5666 "Switching to native 32bit LE integer format.\n"); 5667 5668 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5669 } 5670 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5671 5672 return 0; 5673 } 5674 5675 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5676 { 5677 int i; 5678 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5679 5680 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5681 /* Just disable all channels. The saving when disabling a */ 5682 /* smaller set is not worth the trouble. */ 5683 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5684 snd_hdspm_enable_out(hdspm, i, 0); 5685 5686 hdspm->playback_buffer = NULL; 5687 } else { 5688 for (i = 0; i < HDSPM_MAX_CHANNELS; ++i) 5689 snd_hdspm_enable_in(hdspm, i, 0); 5690 5691 hdspm->capture_buffer = NULL; 5692 } 5693 5694 snd_pcm_lib_free_pages(substream); 5695 5696 return 0; 5697 } 5698 5699 5700 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5701 struct snd_pcm_channel_info *info) 5702 { 5703 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5704 unsigned int channel = info->channel; 5705 5706 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5707 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) { 5708 dev_info(hdspm->card->dev, 5709 "snd_hdspm_channel_info: output channel out of range (%d)\n", 5710 channel); 5711 return -EINVAL; 5712 } 5713 5714 channel = array_index_nospec(channel, hdspm->max_channels_out); 5715 if (hdspm->channel_map_out[channel] < 0) { 5716 dev_info(hdspm->card->dev, 5717 "snd_hdspm_channel_info: output channel %d mapped out\n", 5718 channel); 5719 return -EINVAL; 5720 } 5721 5722 info->offset = hdspm->channel_map_out[channel] * 5723 HDSPM_CHANNEL_BUFFER_BYTES; 5724 } else { 5725 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) { 5726 dev_info(hdspm->card->dev, 5727 "snd_hdspm_channel_info: input channel out of range (%d)\n", 5728 channel); 5729 return -EINVAL; 5730 } 5731 5732 channel = array_index_nospec(channel, hdspm->max_channels_in); 5733 if (hdspm->channel_map_in[channel] < 0) { 5734 dev_info(hdspm->card->dev, 5735 "snd_hdspm_channel_info: input channel %d mapped out\n", 5736 channel); 5737 return -EINVAL; 5738 } 5739 5740 info->offset = hdspm->channel_map_in[channel] * 5741 HDSPM_CHANNEL_BUFFER_BYTES; 5742 } 5743 5744 info->first = 0; 5745 info->step = 32; 5746 return 0; 5747 } 5748 5749 5750 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5751 unsigned int cmd, void *arg) 5752 { 5753 switch (cmd) { 5754 case SNDRV_PCM_IOCTL1_RESET: 5755 return snd_hdspm_reset(substream); 5756 5757 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5758 { 5759 struct snd_pcm_channel_info *info = arg; 5760 return snd_hdspm_channel_info(substream, info); 5761 } 5762 default: 5763 break; 5764 } 5765 5766 return snd_pcm_lib_ioctl(substream, cmd, arg); 5767 } 5768 5769 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5770 { 5771 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5772 struct snd_pcm_substream *other; 5773 int running; 5774 5775 spin_lock(&hdspm->lock); 5776 running = hdspm->running; 5777 switch (cmd) { 5778 case SNDRV_PCM_TRIGGER_START: 5779 running |= 1 << substream->stream; 5780 break; 5781 case SNDRV_PCM_TRIGGER_STOP: 5782 running &= ~(1 << substream->stream); 5783 break; 5784 default: 5785 snd_BUG(); 5786 spin_unlock(&hdspm->lock); 5787 return -EINVAL; 5788 } 5789 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5790 other = hdspm->capture_substream; 5791 else 5792 other = hdspm->playback_substream; 5793 5794 if (other) { 5795 struct snd_pcm_substream *s; 5796 snd_pcm_group_for_each_entry(s, substream) { 5797 if (s == other) { 5798 snd_pcm_trigger_done(s, substream); 5799 if (cmd == SNDRV_PCM_TRIGGER_START) 5800 running |= 1 << s->stream; 5801 else 5802 running &= ~(1 << s->stream); 5803 goto _ok; 5804 } 5805 } 5806 if (cmd == SNDRV_PCM_TRIGGER_START) { 5807 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5808 && substream->stream == 5809 SNDRV_PCM_STREAM_CAPTURE) 5810 hdspm_silence_playback(hdspm); 5811 } else { 5812 if (running && 5813 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5814 hdspm_silence_playback(hdspm); 5815 } 5816 } else { 5817 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5818 hdspm_silence_playback(hdspm); 5819 } 5820 _ok: 5821 snd_pcm_trigger_done(substream, substream); 5822 if (!hdspm->running && running) 5823 hdspm_start_audio(hdspm); 5824 else if (hdspm->running && !running) 5825 hdspm_stop_audio(hdspm); 5826 hdspm->running = running; 5827 spin_unlock(&hdspm->lock); 5828 5829 return 0; 5830 } 5831 5832 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5833 { 5834 return 0; 5835 } 5836 5837 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5838 .info = (SNDRV_PCM_INFO_MMAP | 5839 SNDRV_PCM_INFO_MMAP_VALID | 5840 SNDRV_PCM_INFO_NONINTERLEAVED | 5841 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5842 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5843 .rates = (SNDRV_PCM_RATE_32000 | 5844 SNDRV_PCM_RATE_44100 | 5845 SNDRV_PCM_RATE_48000 | 5846 SNDRV_PCM_RATE_64000 | 5847 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5848 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5849 .rate_min = 32000, 5850 .rate_max = 192000, 5851 .channels_min = 1, 5852 .channels_max = HDSPM_MAX_CHANNELS, 5853 .buffer_bytes_max = 5854 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5855 .period_bytes_min = (32 * 4), 5856 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5857 .periods_min = 2, 5858 .periods_max = 512, 5859 .fifo_size = 0 5860 }; 5861 5862 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5863 .info = (SNDRV_PCM_INFO_MMAP | 5864 SNDRV_PCM_INFO_MMAP_VALID | 5865 SNDRV_PCM_INFO_NONINTERLEAVED | 5866 SNDRV_PCM_INFO_SYNC_START), 5867 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5868 .rates = (SNDRV_PCM_RATE_32000 | 5869 SNDRV_PCM_RATE_44100 | 5870 SNDRV_PCM_RATE_48000 | 5871 SNDRV_PCM_RATE_64000 | 5872 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5873 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5874 .rate_min = 32000, 5875 .rate_max = 192000, 5876 .channels_min = 1, 5877 .channels_max = HDSPM_MAX_CHANNELS, 5878 .buffer_bytes_max = 5879 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5880 .period_bytes_min = (32 * 4), 5881 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5882 .periods_min = 2, 5883 .periods_max = 512, 5884 .fifo_size = 0 5885 }; 5886 5887 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5888 struct snd_pcm_hw_rule *rule) 5889 { 5890 struct hdspm *hdspm = rule->private; 5891 struct snd_interval *c = 5892 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5893 struct snd_interval *r = 5894 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5895 5896 if (r->min > 96000 && r->max <= 192000) { 5897 struct snd_interval t = { 5898 .min = hdspm->qs_in_channels, 5899 .max = hdspm->qs_in_channels, 5900 .integer = 1, 5901 }; 5902 return snd_interval_refine(c, &t); 5903 } else if (r->min > 48000 && r->max <= 96000) { 5904 struct snd_interval t = { 5905 .min = hdspm->ds_in_channels, 5906 .max = hdspm->ds_in_channels, 5907 .integer = 1, 5908 }; 5909 return snd_interval_refine(c, &t); 5910 } else if (r->max < 64000) { 5911 struct snd_interval t = { 5912 .min = hdspm->ss_in_channels, 5913 .max = hdspm->ss_in_channels, 5914 .integer = 1, 5915 }; 5916 return snd_interval_refine(c, &t); 5917 } 5918 5919 return 0; 5920 } 5921 5922 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5923 struct snd_pcm_hw_rule * rule) 5924 { 5925 struct hdspm *hdspm = rule->private; 5926 struct snd_interval *c = 5927 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5928 struct snd_interval *r = 5929 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5930 5931 if (r->min > 96000 && r->max <= 192000) { 5932 struct snd_interval t = { 5933 .min = hdspm->qs_out_channels, 5934 .max = hdspm->qs_out_channels, 5935 .integer = 1, 5936 }; 5937 return snd_interval_refine(c, &t); 5938 } else if (r->min > 48000 && r->max <= 96000) { 5939 struct snd_interval t = { 5940 .min = hdspm->ds_out_channels, 5941 .max = hdspm->ds_out_channels, 5942 .integer = 1, 5943 }; 5944 return snd_interval_refine(c, &t); 5945 } else if (r->max < 64000) { 5946 struct snd_interval t = { 5947 .min = hdspm->ss_out_channels, 5948 .max = hdspm->ss_out_channels, 5949 .integer = 1, 5950 }; 5951 return snd_interval_refine(c, &t); 5952 } else { 5953 } 5954 return 0; 5955 } 5956 5957 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5958 struct snd_pcm_hw_rule * rule) 5959 { 5960 struct hdspm *hdspm = rule->private; 5961 struct snd_interval *c = 5962 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5963 struct snd_interval *r = 5964 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5965 5966 if (c->min >= hdspm->ss_in_channels) { 5967 struct snd_interval t = { 5968 .min = 32000, 5969 .max = 48000, 5970 .integer = 1, 5971 }; 5972 return snd_interval_refine(r, &t); 5973 } else if (c->max <= hdspm->qs_in_channels) { 5974 struct snd_interval t = { 5975 .min = 128000, 5976 .max = 192000, 5977 .integer = 1, 5978 }; 5979 return snd_interval_refine(r, &t); 5980 } else if (c->max <= hdspm->ds_in_channels) { 5981 struct snd_interval t = { 5982 .min = 64000, 5983 .max = 96000, 5984 .integer = 1, 5985 }; 5986 return snd_interval_refine(r, &t); 5987 } 5988 5989 return 0; 5990 } 5991 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5992 struct snd_pcm_hw_rule *rule) 5993 { 5994 struct hdspm *hdspm = rule->private; 5995 struct snd_interval *c = 5996 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5997 struct snd_interval *r = 5998 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5999 6000 if (c->min >= hdspm->ss_out_channels) { 6001 struct snd_interval t = { 6002 .min = 32000, 6003 .max = 48000, 6004 .integer = 1, 6005 }; 6006 return snd_interval_refine(r, &t); 6007 } else if (c->max <= hdspm->qs_out_channels) { 6008 struct snd_interval t = { 6009 .min = 128000, 6010 .max = 192000, 6011 .integer = 1, 6012 }; 6013 return snd_interval_refine(r, &t); 6014 } else if (c->max <= hdspm->ds_out_channels) { 6015 struct snd_interval t = { 6016 .min = 64000, 6017 .max = 96000, 6018 .integer = 1, 6019 }; 6020 return snd_interval_refine(r, &t); 6021 } 6022 6023 return 0; 6024 } 6025 6026 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 6027 struct snd_pcm_hw_rule *rule) 6028 { 6029 unsigned int list[3]; 6030 struct hdspm *hdspm = rule->private; 6031 struct snd_interval *c = hw_param_interval(params, 6032 SNDRV_PCM_HW_PARAM_CHANNELS); 6033 6034 list[0] = hdspm->qs_in_channels; 6035 list[1] = hdspm->ds_in_channels; 6036 list[2] = hdspm->ss_in_channels; 6037 return snd_interval_list(c, 3, list, 0); 6038 } 6039 6040 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 6041 struct snd_pcm_hw_rule *rule) 6042 { 6043 unsigned int list[3]; 6044 struct hdspm *hdspm = rule->private; 6045 struct snd_interval *c = hw_param_interval(params, 6046 SNDRV_PCM_HW_PARAM_CHANNELS); 6047 6048 list[0] = hdspm->qs_out_channels; 6049 list[1] = hdspm->ds_out_channels; 6050 list[2] = hdspm->ss_out_channels; 6051 return snd_interval_list(c, 3, list, 0); 6052 } 6053 6054 6055 static const unsigned int hdspm_aes32_sample_rates[] = { 6056 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 6057 }; 6058 6059 static const struct snd_pcm_hw_constraint_list 6060 hdspm_hw_constraints_aes32_sample_rates = { 6061 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 6062 .list = hdspm_aes32_sample_rates, 6063 .mask = 0 6064 }; 6065 6066 static int snd_hdspm_open(struct snd_pcm_substream *substream) 6067 { 6068 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6069 struct snd_pcm_runtime *runtime = substream->runtime; 6070 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6071 6072 spin_lock_irq(&hdspm->lock); 6073 snd_pcm_set_sync(substream); 6074 runtime->hw = (playback) ? snd_hdspm_playback_subinfo : 6075 snd_hdspm_capture_subinfo; 6076 6077 if (playback) { 6078 if (!hdspm->capture_substream) 6079 hdspm_stop_audio(hdspm); 6080 6081 hdspm->playback_pid = current->pid; 6082 hdspm->playback_substream = substream; 6083 } else { 6084 if (!hdspm->playback_substream) 6085 hdspm_stop_audio(hdspm); 6086 6087 hdspm->capture_pid = current->pid; 6088 hdspm->capture_substream = substream; 6089 } 6090 6091 spin_unlock_irq(&hdspm->lock); 6092 6093 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 6094 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 6095 6096 switch (hdspm->io_type) { 6097 case AIO: 6098 case RayDAT: 6099 snd_pcm_hw_constraint_minmax(runtime, 6100 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6101 32, 4096); 6102 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 6103 snd_pcm_hw_constraint_single(runtime, 6104 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 6105 16384); 6106 break; 6107 6108 default: 6109 snd_pcm_hw_constraint_minmax(runtime, 6110 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 6111 64, 8192); 6112 snd_pcm_hw_constraint_single(runtime, 6113 SNDRV_PCM_HW_PARAM_PERIODS, 2); 6114 break; 6115 } 6116 6117 if (AES32 == hdspm->io_type) { 6118 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 6119 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6120 &hdspm_hw_constraints_aes32_sample_rates); 6121 } else { 6122 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 6123 (playback ? 6124 snd_hdspm_hw_rule_rate_out_channels : 6125 snd_hdspm_hw_rule_rate_in_channels), hdspm, 6126 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6127 } 6128 6129 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6130 (playback ? snd_hdspm_hw_rule_out_channels : 6131 snd_hdspm_hw_rule_in_channels), hdspm, 6132 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 6133 6134 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 6135 (playback ? snd_hdspm_hw_rule_out_channels_rate : 6136 snd_hdspm_hw_rule_in_channels_rate), hdspm, 6137 SNDRV_PCM_HW_PARAM_RATE, -1); 6138 6139 return 0; 6140 } 6141 6142 static int snd_hdspm_release(struct snd_pcm_substream *substream) 6143 { 6144 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 6145 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 6146 6147 spin_lock_irq(&hdspm->lock); 6148 6149 if (playback) { 6150 hdspm->playback_pid = -1; 6151 hdspm->playback_substream = NULL; 6152 } else { 6153 hdspm->capture_pid = -1; 6154 hdspm->capture_substream = NULL; 6155 } 6156 6157 spin_unlock_irq(&hdspm->lock); 6158 6159 return 0; 6160 } 6161 6162 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 6163 { 6164 /* we have nothing to initialize but the call is required */ 6165 return 0; 6166 } 6167 6168 static inline int copy_u32_le(void __user *dest, void __iomem *src) 6169 { 6170 u32 val = readl(src); 6171 return copy_to_user(dest, &val, 4); 6172 } 6173 6174 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 6175 unsigned int cmd, unsigned long arg) 6176 { 6177 void __user *argp = (void __user *)arg; 6178 struct hdspm *hdspm = hw->private_data; 6179 struct hdspm_mixer_ioctl mixer; 6180 struct hdspm_config info; 6181 struct hdspm_status status; 6182 struct hdspm_version hdspm_version; 6183 struct hdspm_peak_rms *levels; 6184 struct hdspm_ltc ltc; 6185 unsigned int statusregister; 6186 long unsigned int s; 6187 int i = 0; 6188 6189 switch (cmd) { 6190 6191 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 6192 levels = &hdspm->peak_rms; 6193 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 6194 levels->input_peaks[i] = 6195 readl(hdspm->iobase + 6196 HDSPM_MADI_INPUT_PEAK + i*4); 6197 levels->playback_peaks[i] = 6198 readl(hdspm->iobase + 6199 HDSPM_MADI_PLAYBACK_PEAK + i*4); 6200 levels->output_peaks[i] = 6201 readl(hdspm->iobase + 6202 HDSPM_MADI_OUTPUT_PEAK + i*4); 6203 6204 levels->input_rms[i] = 6205 ((uint64_t) readl(hdspm->iobase + 6206 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 6207 (uint64_t) readl(hdspm->iobase + 6208 HDSPM_MADI_INPUT_RMS_L + i*4); 6209 levels->playback_rms[i] = 6210 ((uint64_t)readl(hdspm->iobase + 6211 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 6212 (uint64_t)readl(hdspm->iobase + 6213 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 6214 levels->output_rms[i] = 6215 ((uint64_t)readl(hdspm->iobase + 6216 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 6217 (uint64_t)readl(hdspm->iobase + 6218 HDSPM_MADI_OUTPUT_RMS_L + i*4); 6219 } 6220 6221 if (hdspm->system_sample_rate > 96000) { 6222 levels->speed = qs; 6223 } else if (hdspm->system_sample_rate > 48000) { 6224 levels->speed = ds; 6225 } else { 6226 levels->speed = ss; 6227 } 6228 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 6229 6230 s = copy_to_user(argp, levels, sizeof(*levels)); 6231 if (0 != s) { 6232 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu 6233 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 6234 */ 6235 return -EFAULT; 6236 } 6237 break; 6238 6239 case SNDRV_HDSPM_IOCTL_GET_LTC: 6240 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 6241 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 6242 if (i & HDSPM_TCO1_LTC_Input_valid) { 6243 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 6244 HDSPM_TCO1_LTC_Format_MSB)) { 6245 case 0: 6246 ltc.format = fps_24; 6247 break; 6248 case HDSPM_TCO1_LTC_Format_LSB: 6249 ltc.format = fps_25; 6250 break; 6251 case HDSPM_TCO1_LTC_Format_MSB: 6252 ltc.format = fps_2997; 6253 break; 6254 default: 6255 ltc.format = fps_30; 6256 break; 6257 } 6258 if (i & HDSPM_TCO1_set_drop_frame_flag) { 6259 ltc.frame = drop_frame; 6260 } else { 6261 ltc.frame = full_frame; 6262 } 6263 } else { 6264 ltc.format = format_invalid; 6265 ltc.frame = frame_invalid; 6266 } 6267 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 6268 ltc.input_format = ntsc; 6269 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 6270 ltc.input_format = pal; 6271 } else { 6272 ltc.input_format = no_video; 6273 } 6274 6275 s = copy_to_user(argp, <c, sizeof(ltc)); 6276 if (0 != s) { 6277 /* 6278 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 6279 return -EFAULT; 6280 } 6281 6282 break; 6283 6284 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 6285 6286 memset(&info, 0, sizeof(info)); 6287 spin_lock_irq(&hdspm->lock); 6288 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 6289 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 6290 6291 info.system_sample_rate = hdspm->system_sample_rate; 6292 info.autosync_sample_rate = 6293 hdspm_external_sample_rate(hdspm); 6294 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 6295 info.clock_source = hdspm_clock_source(hdspm); 6296 info.autosync_ref = hdspm_autosync_ref(hdspm); 6297 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 6298 info.passthru = 0; 6299 spin_unlock_irq(&hdspm->lock); 6300 if (copy_to_user(argp, &info, sizeof(info))) 6301 return -EFAULT; 6302 break; 6303 6304 case SNDRV_HDSPM_IOCTL_GET_STATUS: 6305 memset(&status, 0, sizeof(status)); 6306 6307 status.card_type = hdspm->io_type; 6308 6309 status.autosync_source = hdspm_autosync_ref(hdspm); 6310 6311 status.card_clock = 110069313433624ULL; 6312 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 6313 6314 switch (hdspm->io_type) { 6315 case MADI: 6316 case MADIface: 6317 status.card_specific.madi.sync_wc = 6318 hdspm_wc_sync_check(hdspm); 6319 status.card_specific.madi.sync_madi = 6320 hdspm_madi_sync_check(hdspm); 6321 status.card_specific.madi.sync_tco = 6322 hdspm_tco_sync_check(hdspm); 6323 status.card_specific.madi.sync_in = 6324 hdspm_sync_in_sync_check(hdspm); 6325 6326 statusregister = 6327 hdspm_read(hdspm, HDSPM_statusRegister); 6328 status.card_specific.madi.madi_input = 6329 (statusregister & HDSPM_AB_int) ? 1 : 0; 6330 status.card_specific.madi.channel_format = 6331 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 6332 /* TODO: Mac driver sets it when f_s>48kHz */ 6333 status.card_specific.madi.frame_format = 0; 6334 6335 default: 6336 break; 6337 } 6338 6339 if (copy_to_user(argp, &status, sizeof(status))) 6340 return -EFAULT; 6341 6342 6343 break; 6344 6345 case SNDRV_HDSPM_IOCTL_GET_VERSION: 6346 memset(&hdspm_version, 0, sizeof(hdspm_version)); 6347 6348 hdspm_version.card_type = hdspm->io_type; 6349 strlcpy(hdspm_version.cardname, hdspm->card_name, 6350 sizeof(hdspm_version.cardname)); 6351 hdspm_version.serial = hdspm->serial; 6352 hdspm_version.firmware_rev = hdspm->firmware_rev; 6353 hdspm_version.addons = 0; 6354 if (hdspm->tco) 6355 hdspm_version.addons |= HDSPM_ADDON_TCO; 6356 6357 if (copy_to_user(argp, &hdspm_version, 6358 sizeof(hdspm_version))) 6359 return -EFAULT; 6360 break; 6361 6362 case SNDRV_HDSPM_IOCTL_GET_MIXER: 6363 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6364 return -EFAULT; 6365 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6366 sizeof(*mixer.mixer))) 6367 return -EFAULT; 6368 break; 6369 6370 default: 6371 return -EINVAL; 6372 } 6373 return 0; 6374 } 6375 6376 static const struct snd_pcm_ops snd_hdspm_ops = { 6377 .open = snd_hdspm_open, 6378 .close = snd_hdspm_release, 6379 .ioctl = snd_hdspm_ioctl, 6380 .hw_params = snd_hdspm_hw_params, 6381 .hw_free = snd_hdspm_hw_free, 6382 .prepare = snd_hdspm_prepare, 6383 .trigger = snd_hdspm_trigger, 6384 .pointer = snd_hdspm_hw_pointer, 6385 .page = snd_pcm_sgbuf_ops_page, 6386 }; 6387 6388 static int snd_hdspm_create_hwdep(struct snd_card *card, 6389 struct hdspm *hdspm) 6390 { 6391 struct snd_hwdep *hw; 6392 int err; 6393 6394 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6395 if (err < 0) 6396 return err; 6397 6398 hdspm->hwdep = hw; 6399 hw->private_data = hdspm; 6400 strcpy(hw->name, "HDSPM hwdep interface"); 6401 6402 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6403 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6404 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6405 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6406 6407 return 0; 6408 } 6409 6410 6411 /*------------------------------------------------------------ 6412 memory interface 6413 ------------------------------------------------------------*/ 6414 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6415 { 6416 struct snd_pcm *pcm; 6417 size_t wanted; 6418 6419 pcm = hdspm->pcm; 6420 6421 wanted = HDSPM_DMA_AREA_BYTES; 6422 6423 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG, 6424 snd_dma_pci_data(hdspm->pci), 6425 wanted, wanted); 6426 dev_dbg(hdspm->card->dev, " Preallocated %zd Bytes\n", wanted); 6427 return 0; 6428 } 6429 6430 /* Inform the card what DMA addresses to use for the indicated channel. */ 6431 /* Each channel got 16 4K pages allocated for DMA transfers. */ 6432 static void hdspm_set_channel_dma_addr(struct hdspm *hdspm, 6433 struct snd_pcm_substream *substream, 6434 unsigned int reg, int channel) 6435 { 6436 int i; 6437 6438 for (i = channel * 16; i < channel * 16 + 16; i++) 6439 hdspm_write(hdspm, reg + 4 * i, 6440 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6441 } 6442 6443 6444 /* ------------- ALSA Devices ---------------------------- */ 6445 static int snd_hdspm_create_pcm(struct snd_card *card, 6446 struct hdspm *hdspm) 6447 { 6448 struct snd_pcm *pcm; 6449 int err; 6450 6451 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6452 if (err < 0) 6453 return err; 6454 6455 hdspm->pcm = pcm; 6456 pcm->private_data = hdspm; 6457 strcpy(pcm->name, hdspm->card_name); 6458 6459 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6460 &snd_hdspm_ops); 6461 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6462 &snd_hdspm_ops); 6463 6464 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6465 6466 err = snd_hdspm_preallocate_memory(hdspm); 6467 if (err < 0) 6468 return err; 6469 6470 return 0; 6471 } 6472 6473 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6474 { 6475 int i; 6476 6477 for (i = 0; i < hdspm->midiPorts; i++) 6478 snd_hdspm_flush_midi_input(hdspm, i); 6479 } 6480 6481 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6482 struct hdspm *hdspm) 6483 { 6484 int err, i; 6485 6486 dev_dbg(card->dev, "Create card...\n"); 6487 err = snd_hdspm_create_pcm(card, hdspm); 6488 if (err < 0) 6489 return err; 6490 6491 i = 0; 6492 while (i < hdspm->midiPorts) { 6493 err = snd_hdspm_create_midi(card, hdspm, i); 6494 if (err < 0) { 6495 return err; 6496 } 6497 i++; 6498 } 6499 6500 err = snd_hdspm_create_controls(card, hdspm); 6501 if (err < 0) 6502 return err; 6503 6504 err = snd_hdspm_create_hwdep(card, hdspm); 6505 if (err < 0) 6506 return err; 6507 6508 dev_dbg(card->dev, "proc init...\n"); 6509 snd_hdspm_proc_init(hdspm); 6510 6511 hdspm->system_sample_rate = -1; 6512 hdspm->last_external_sample_rate = -1; 6513 hdspm->last_internal_sample_rate = -1; 6514 hdspm->playback_pid = -1; 6515 hdspm->capture_pid = -1; 6516 hdspm->capture_substream = NULL; 6517 hdspm->playback_substream = NULL; 6518 6519 dev_dbg(card->dev, "Set defaults...\n"); 6520 err = snd_hdspm_set_defaults(hdspm); 6521 if (err < 0) 6522 return err; 6523 6524 dev_dbg(card->dev, "Update mixer controls...\n"); 6525 hdspm_update_simple_mixer_controls(hdspm); 6526 6527 dev_dbg(card->dev, "Initializing complete?\n"); 6528 6529 err = snd_card_register(card); 6530 if (err < 0) { 6531 dev_err(card->dev, "error registering card\n"); 6532 return err; 6533 } 6534 6535 dev_dbg(card->dev, "... yes now\n"); 6536 6537 return 0; 6538 } 6539 6540 static int snd_hdspm_create(struct snd_card *card, 6541 struct hdspm *hdspm) 6542 { 6543 6544 struct pci_dev *pci = hdspm->pci; 6545 int err; 6546 unsigned long io_extent; 6547 6548 hdspm->irq = -1; 6549 hdspm->card = card; 6550 6551 spin_lock_init(&hdspm->lock); 6552 6553 pci_read_config_word(hdspm->pci, 6554 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6555 6556 strcpy(card->mixername, "Xilinx FPGA"); 6557 strcpy(card->driver, "HDSPM"); 6558 6559 switch (hdspm->firmware_rev) { 6560 case HDSPM_RAYDAT_REV: 6561 hdspm->io_type = RayDAT; 6562 hdspm->card_name = "RME RayDAT"; 6563 hdspm->midiPorts = 2; 6564 break; 6565 case HDSPM_AIO_REV: 6566 hdspm->io_type = AIO; 6567 hdspm->card_name = "RME AIO"; 6568 hdspm->midiPorts = 1; 6569 break; 6570 case HDSPM_MADIFACE_REV: 6571 hdspm->io_type = MADIface; 6572 hdspm->card_name = "RME MADIface"; 6573 hdspm->midiPorts = 1; 6574 break; 6575 default: 6576 if ((hdspm->firmware_rev == 0xf0) || 6577 ((hdspm->firmware_rev >= 0xe6) && 6578 (hdspm->firmware_rev <= 0xea))) { 6579 hdspm->io_type = AES32; 6580 hdspm->card_name = "RME AES32"; 6581 hdspm->midiPorts = 2; 6582 } else if ((hdspm->firmware_rev == 0xd2) || 6583 ((hdspm->firmware_rev >= 0xc8) && 6584 (hdspm->firmware_rev <= 0xcf))) { 6585 hdspm->io_type = MADI; 6586 hdspm->card_name = "RME MADI"; 6587 hdspm->midiPorts = 3; 6588 } else { 6589 dev_err(card->dev, 6590 "unknown firmware revision %x\n", 6591 hdspm->firmware_rev); 6592 return -ENODEV; 6593 } 6594 } 6595 6596 err = pci_enable_device(pci); 6597 if (err < 0) 6598 return err; 6599 6600 pci_set_master(hdspm->pci); 6601 6602 err = pci_request_regions(pci, "hdspm"); 6603 if (err < 0) 6604 return err; 6605 6606 hdspm->port = pci_resource_start(pci, 0); 6607 io_extent = pci_resource_len(pci, 0); 6608 6609 dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n", 6610 hdspm->port, hdspm->port + io_extent - 1); 6611 6612 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6613 if (!hdspm->iobase) { 6614 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n", 6615 hdspm->port, hdspm->port + io_extent - 1); 6616 return -EBUSY; 6617 } 6618 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n", 6619 (unsigned long)hdspm->iobase, hdspm->port, 6620 hdspm->port + io_extent - 1); 6621 6622 if (request_irq(pci->irq, snd_hdspm_interrupt, 6623 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6624 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq); 6625 return -EBUSY; 6626 } 6627 6628 dev_dbg(card->dev, "use IRQ %d\n", pci->irq); 6629 6630 hdspm->irq = pci->irq; 6631 6632 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n", 6633 sizeof(*hdspm->mixer)); 6634 hdspm->mixer = kzalloc(sizeof(*hdspm->mixer), GFP_KERNEL); 6635 if (!hdspm->mixer) 6636 return -ENOMEM; 6637 6638 hdspm->port_names_in = NULL; 6639 hdspm->port_names_out = NULL; 6640 6641 switch (hdspm->io_type) { 6642 case AES32: 6643 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6644 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6645 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6646 6647 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6648 channel_map_aes32; 6649 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6650 channel_map_aes32; 6651 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6652 channel_map_aes32; 6653 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6654 texts_ports_aes32; 6655 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6656 texts_ports_aes32; 6657 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6658 texts_ports_aes32; 6659 6660 hdspm->max_channels_out = hdspm->max_channels_in = 6661 AES32_CHANNELS; 6662 hdspm->port_names_in = hdspm->port_names_out = 6663 texts_ports_aes32; 6664 hdspm->channel_map_in = hdspm->channel_map_out = 6665 channel_map_aes32; 6666 6667 break; 6668 6669 case MADI: 6670 case MADIface: 6671 hdspm->ss_in_channels = hdspm->ss_out_channels = 6672 MADI_SS_CHANNELS; 6673 hdspm->ds_in_channels = hdspm->ds_out_channels = 6674 MADI_DS_CHANNELS; 6675 hdspm->qs_in_channels = hdspm->qs_out_channels = 6676 MADI_QS_CHANNELS; 6677 6678 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6679 channel_map_unity_ss; 6680 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6681 channel_map_unity_ss; 6682 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6683 channel_map_unity_ss; 6684 6685 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6686 texts_ports_madi; 6687 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6688 texts_ports_madi; 6689 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6690 texts_ports_madi; 6691 break; 6692 6693 case AIO: 6694 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6695 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6696 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6697 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6698 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6699 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6700 6701 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6702 dev_info(card->dev, "AEB input board found\n"); 6703 hdspm->ss_in_channels += 4; 6704 hdspm->ds_in_channels += 4; 6705 hdspm->qs_in_channels += 4; 6706 } 6707 6708 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) { 6709 dev_info(card->dev, "AEB output board found\n"); 6710 hdspm->ss_out_channels += 4; 6711 hdspm->ds_out_channels += 4; 6712 hdspm->qs_out_channels += 4; 6713 } 6714 6715 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6716 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6717 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6718 6719 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6720 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6721 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6722 6723 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6724 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6725 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6726 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6727 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6728 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6729 6730 break; 6731 6732 case RayDAT: 6733 hdspm->ss_in_channels = hdspm->ss_out_channels = 6734 RAYDAT_SS_CHANNELS; 6735 hdspm->ds_in_channels = hdspm->ds_out_channels = 6736 RAYDAT_DS_CHANNELS; 6737 hdspm->qs_in_channels = hdspm->qs_out_channels = 6738 RAYDAT_QS_CHANNELS; 6739 6740 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6741 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6742 6743 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6744 channel_map_raydat_ss; 6745 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6746 channel_map_raydat_ds; 6747 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6748 channel_map_raydat_qs; 6749 hdspm->channel_map_in = hdspm->channel_map_out = 6750 channel_map_raydat_ss; 6751 6752 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6753 texts_ports_raydat_ss; 6754 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6755 texts_ports_raydat_ds; 6756 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6757 texts_ports_raydat_qs; 6758 6759 6760 break; 6761 6762 } 6763 6764 /* TCO detection */ 6765 switch (hdspm->io_type) { 6766 case AIO: 6767 case RayDAT: 6768 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6769 HDSPM_s2_tco_detect) { 6770 hdspm->midiPorts++; 6771 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6772 if (hdspm->tco) 6773 hdspm_tco_write(hdspm); 6774 6775 dev_info(card->dev, "AIO/RayDAT TCO module found\n"); 6776 } else { 6777 hdspm->tco = NULL; 6778 } 6779 break; 6780 6781 case MADI: 6782 case AES32: 6783 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6784 hdspm->midiPorts++; 6785 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL); 6786 if (hdspm->tco) 6787 hdspm_tco_write(hdspm); 6788 6789 dev_info(card->dev, "MADI/AES TCO module found\n"); 6790 } else { 6791 hdspm->tco = NULL; 6792 } 6793 break; 6794 6795 default: 6796 hdspm->tco = NULL; 6797 } 6798 6799 /* texts */ 6800 switch (hdspm->io_type) { 6801 case AES32: 6802 if (hdspm->tco) { 6803 hdspm->texts_autosync = texts_autosync_aes_tco; 6804 hdspm->texts_autosync_items = 6805 ARRAY_SIZE(texts_autosync_aes_tco); 6806 } else { 6807 hdspm->texts_autosync = texts_autosync_aes; 6808 hdspm->texts_autosync_items = 6809 ARRAY_SIZE(texts_autosync_aes); 6810 } 6811 break; 6812 6813 case MADI: 6814 if (hdspm->tco) { 6815 hdspm->texts_autosync = texts_autosync_madi_tco; 6816 hdspm->texts_autosync_items = 4; 6817 } else { 6818 hdspm->texts_autosync = texts_autosync_madi; 6819 hdspm->texts_autosync_items = 3; 6820 } 6821 break; 6822 6823 case MADIface: 6824 6825 break; 6826 6827 case RayDAT: 6828 if (hdspm->tco) { 6829 hdspm->texts_autosync = texts_autosync_raydat_tco; 6830 hdspm->texts_autosync_items = 9; 6831 } else { 6832 hdspm->texts_autosync = texts_autosync_raydat; 6833 hdspm->texts_autosync_items = 8; 6834 } 6835 break; 6836 6837 case AIO: 6838 if (hdspm->tco) { 6839 hdspm->texts_autosync = texts_autosync_aio_tco; 6840 hdspm->texts_autosync_items = 6; 6841 } else { 6842 hdspm->texts_autosync = texts_autosync_aio; 6843 hdspm->texts_autosync_items = 5; 6844 } 6845 break; 6846 6847 } 6848 6849 tasklet_init(&hdspm->midi_tasklet, 6850 hdspm_midi_tasklet, (unsigned long) hdspm); 6851 6852 6853 if (hdspm->io_type != MADIface) { 6854 hdspm->serial = (hdspm_read(hdspm, 6855 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6856 /* id contains either a user-provided value or the default 6857 * NULL. If it's the default, we're safe to 6858 * fill card->id with the serial number. 6859 * 6860 * If the serial number is 0xFFFFFF, then we're dealing with 6861 * an old PCI revision that comes without a sane number. In 6862 * this case, we don't set card->id to avoid collisions 6863 * when running with multiple cards. 6864 */ 6865 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6866 snprintf(card->id, sizeof(card->id), 6867 "HDSPMx%06x", hdspm->serial); 6868 snd_card_set_id(card, card->id); 6869 } 6870 } 6871 6872 dev_dbg(card->dev, "create alsa devices.\n"); 6873 err = snd_hdspm_create_alsa_devices(card, hdspm); 6874 if (err < 0) 6875 return err; 6876 6877 snd_hdspm_initialize_midi_flush(hdspm); 6878 6879 return 0; 6880 } 6881 6882 6883 static int snd_hdspm_free(struct hdspm * hdspm) 6884 { 6885 6886 if (hdspm->port) { 6887 6888 /* stop th audio, and cancel all interrupts */ 6889 hdspm->control_register &= 6890 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6891 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6892 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6893 hdspm_write(hdspm, HDSPM_controlRegister, 6894 hdspm->control_register); 6895 } 6896 6897 if (hdspm->irq >= 0) 6898 free_irq(hdspm->irq, (void *) hdspm); 6899 6900 kfree(hdspm->mixer); 6901 iounmap(hdspm->iobase); 6902 6903 if (hdspm->port) 6904 pci_release_regions(hdspm->pci); 6905 6906 pci_disable_device(hdspm->pci); 6907 return 0; 6908 } 6909 6910 6911 static void snd_hdspm_card_free(struct snd_card *card) 6912 { 6913 struct hdspm *hdspm = card->private_data; 6914 6915 if (hdspm) 6916 snd_hdspm_free(hdspm); 6917 } 6918 6919 6920 static int snd_hdspm_probe(struct pci_dev *pci, 6921 const struct pci_device_id *pci_id) 6922 { 6923 static int dev; 6924 struct hdspm *hdspm; 6925 struct snd_card *card; 6926 int err; 6927 6928 if (dev >= SNDRV_CARDS) 6929 return -ENODEV; 6930 if (!enable[dev]) { 6931 dev++; 6932 return -ENOENT; 6933 } 6934 6935 err = snd_card_new(&pci->dev, index[dev], id[dev], 6936 THIS_MODULE, sizeof(*hdspm), &card); 6937 if (err < 0) 6938 return err; 6939 6940 hdspm = card->private_data; 6941 card->private_free = snd_hdspm_card_free; 6942 hdspm->dev = dev; 6943 hdspm->pci = pci; 6944 6945 err = snd_hdspm_create(card, hdspm); 6946 if (err < 0) 6947 goto free_card; 6948 6949 if (hdspm->io_type != MADIface) { 6950 snprintf(card->shortname, sizeof(card->shortname), "%s_%x", 6951 hdspm->card_name, hdspm->serial); 6952 snprintf(card->longname, sizeof(card->longname), 6953 "%s S/N 0x%x at 0x%lx, irq %d", 6954 hdspm->card_name, hdspm->serial, 6955 hdspm->port, hdspm->irq); 6956 } else { 6957 snprintf(card->shortname, sizeof(card->shortname), "%s", 6958 hdspm->card_name); 6959 snprintf(card->longname, sizeof(card->longname), 6960 "%s at 0x%lx, irq %d", 6961 hdspm->card_name, hdspm->port, hdspm->irq); 6962 } 6963 6964 err = snd_card_register(card); 6965 if (err < 0) 6966 goto free_card; 6967 6968 pci_set_drvdata(pci, card); 6969 6970 dev++; 6971 return 0; 6972 6973 free_card: 6974 snd_card_free(card); 6975 return err; 6976 } 6977 6978 static void snd_hdspm_remove(struct pci_dev *pci) 6979 { 6980 snd_card_free(pci_get_drvdata(pci)); 6981 } 6982 6983 static struct pci_driver hdspm_driver = { 6984 .name = KBUILD_MODNAME, 6985 .id_table = snd_hdspm_ids, 6986 .probe = snd_hdspm_probe, 6987 .remove = snd_hdspm_remove, 6988 }; 6989 6990 module_pci_driver(hdspm_driver); 6991