1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 #include <linux/init.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/module.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/math64.h> 48 #include <asm/io.h> 49 50 #include <sound/core.h> 51 #include <sound/control.h> 52 #include <sound/pcm.h> 53 #include <sound/pcm_params.h> 54 #include <sound/info.h> 55 #include <sound/asoundef.h> 56 #include <sound/rawmidi.h> 57 #include <sound/hwdep.h> 58 #include <sound/initval.h> 59 60 #include <sound/hdspm.h> 61 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 68 69 module_param_array(id, charp, NULL, 0444); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 71 72 module_param_array(enable, bool, NULL, 0444); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 74 75 76 MODULE_AUTHOR 77 ( 78 "Winfried Ritsch <ritsch_AT_iem.at>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, " 82 "Florian Faber <faberman@linuxproaudio.org>, " 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 84 ); 85 MODULE_DESCRIPTION("RME HDSPM"); 86 MODULE_LICENSE("GPL"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 88 89 /* --- Write registers. --- 90 These are defined as byte-offsets from the iobase value. */ 91 92 #define HDSPM_WR_SETTINGS 0 93 #define HDSPM_outputBufferAddress 32 94 #define HDSPM_inputBufferAddress 36 95 #define HDSPM_controlRegister 64 96 #define HDSPM_interruptConfirmation 96 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 98 #define HDSPM_freqReg 256 /* for AES32 */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 100 #define HDSPM_midiDataOut1 356 101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 102 103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 106 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 109 #define HDSPM_pageAddressBufferOut 8192 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 111 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 113 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 115 116 /* --- Read registers. --- 117 These are defined as byte-offsets from the iobase value */ 118 #define HDSPM_statusRegister 0 119 /*#define HDSPM_statusRegister2 96 */ 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 121 * offset 192, for AES32 *and* MADI 122 * => need to check that offset 192 is working on MADI */ 123 #define HDSPM_statusRegister2 192 124 #define HDSPM_timecodeRegister 128 125 126 /* AIO, RayDAT */ 127 #define HDSPM_RD_STATUS_0 0 128 #define HDSPM_RD_STATUS_1 64 129 #define HDSPM_RD_STATUS_2 128 130 #define HDSPM_RD_STATUS_3 192 131 132 #define HDSPM_RD_TCO 256 133 #define HDSPM_RD_PLL_FREQ 512 134 #define HDSPM_WR_TCO 128 135 136 #define HDSPM_TCO1_TCO_lock 0x00000001 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 143 144 #define HDSPM_TCO1_set_TC 0x00000100 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 148 149 #define HDSPM_TCO2_TC_run 0x00010000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000 155 #define HDSPM_TCO2_set_flywheel 0x00400000 156 157 #define HDSPM_TCO2_set_01_4 0x01000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000 160 #define HDSPM_TCO2_set_freq 0x08000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 165 166 167 #define HDSPM_midiDataOut0 352 168 #define HDSPM_midiDataOut1 356 169 #define HDSPM_midiDataOut2 368 170 171 #define HDSPM_midiDataIn0 360 172 #define HDSPM_midiDataIn1 364 173 #define HDSPM_midiDataIn2 372 174 #define HDSPM_midiDataIn3 376 175 176 /* status is data bytes in MIDI-FIFO (0-128) */ 177 #define HDSPM_midiStatusOut0 384 178 #define HDSPM_midiStatusOut1 388 179 #define HDSPM_midiStatusOut2 400 180 181 #define HDSPM_midiStatusIn0 392 182 #define HDSPM_midiStatusIn1 396 183 #define HDSPM_midiStatusIn2 404 184 #define HDSPM_midiStatusIn3 408 185 186 187 /* the meters are regular i/o-mapped registers, but offset 188 considerably from the rest. the peak registers are reset 189 when read; the least-significant 4 bits are full-scale counters; 190 the actual peak value is in the most-significant 24 bits. 191 */ 192 193 #define HDSPM_MADI_INPUT_PEAK 4096 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 195 #define HDSPM_MADI_OUTPUT_PEAK 4608 196 197 #define HDSPM_MADI_INPUT_RMS_L 6144 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 200 201 #define HDSPM_MADI_INPUT_RMS_H 7168 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 204 205 /* --- Control Register bits --------- */ 206 #define HDSPM_Start (1<<0) /* start engine */ 207 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 211 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 214 register [RayDAT, AIO] */ 215 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 217 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 222 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 225 56channelMODE=0 */ /* MADI ONLY*/ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 227 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 229 0=off, 1=on */ /* MADI ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 231 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 233 * -- MADI ONLY 234 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 236 237 #define HDSPM_SyncRef2 (1<<13) 238 #define HDSPM_SyncRef3 (1<<25) 239 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 242 AES additional bits in 243 lower 5 Audiodatabits ??? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 246 247 #define HDSPM_Midi0InterruptEnable 0x0400000 248 #define HDSPM_Midi1InterruptEnable 0x0800000 249 #define HDSPM_Midi2InterruptEnable 0x0200000 250 #define HDSPM_Midi3InterruptEnable 0x4000000 251 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 253 #define HDSPe_FLOAT_FORMAT 0x2000000 254 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 258 259 #define HDSPM_wclk_sel (1<<30) 260 261 /* --- bit helper defines */ 262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 266 #define HDSPM_InputOptical 0 267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 269 HDSPM_SyncRef2|HDSPM_SyncRef3) 270 271 #define HDSPM_c0_SyncRef0 0x2 272 #define HDSPM_c0_SyncRef1 0x4 273 #define HDSPM_c0_SyncRef2 0x8 274 #define HDSPM_c0_SyncRef3 0x10 275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 277 278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 280 #define HDSPM_SYNC_FROM_TCO 2 281 #define HDSPM_SYNC_FROM_SYNC_IN 3 282 283 #define HDSPM_Frequency32KHz HDSPM_Frequency0 284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 289 HDSPM_Frequency0) 290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 293 HDSPM_Frequency0) 294 295 296 /* Synccheck Status */ 297 #define HDSPM_SYNC_CHECK_NO_LOCK 0 298 #define HDSPM_SYNC_CHECK_LOCK 1 299 #define HDSPM_SYNC_CHECK_SYNC 2 300 301 /* AutoSync References - used by "autosync_ref" control switch */ 302 #define HDSPM_AUTOSYNC_FROM_WORD 0 303 #define HDSPM_AUTOSYNC_FROM_MADI 1 304 #define HDSPM_AUTOSYNC_FROM_TCO 2 305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 306 #define HDSPM_AUTOSYNC_FROM_NONE 4 307 308 /* Possible sources of MADI input */ 309 #define HDSPM_OPTICAL 0 /* optical */ 310 #define HDSPM_COAXIAL 1 /* BNC */ 311 312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 314 315 #define hdspm_encode_in(x) (((x)&0x3)<<14) 316 #define hdspm_decode_in(x) (((x)>>14)&0x3) 317 318 /* --- control2 register bits --- */ 319 #define HDSPM_TMS (1<<0) 320 #define HDSPM_TCK (1<<1) 321 #define HDSPM_TDI (1<<2) 322 #define HDSPM_JTAG (1<<3) 323 #define HDSPM_PWDN (1<<4) 324 #define HDSPM_PROGRAM (1<<5) 325 #define HDSPM_CONFIG_MODE_0 (1<<6) 326 #define HDSPM_CONFIG_MODE_1 (1<<7) 327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 328 #define HDSPM_BIGENDIAN_MODE (1<<9) 329 #define HDSPM_RD_MULTIPLE (1<<10) 330 331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 332 that do not conflict with specific bits for AES32 seem to be valid also 333 for the AES32 334 */ 335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 338 * (like inp0) 339 */ 340 341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 343 344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 346 347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 349 350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 351 /* since 64byte accurate, last 6 bits are not used */ 352 353 354 355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 356 357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 361 362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 363 * Interrupt 364 */ 365 #define HDSPM_tco_detect 0x08000000 366 #define HDSPM_tco_lock 0x20000000 367 368 #define HDSPM_s2_tco_detect 0x00000040 369 #define HDSPM_s2_AEBO_D 0x00000080 370 #define HDSPM_s2_AEBI_D 0x00000100 371 372 373 #define HDSPM_midi0IRQPending 0x40000000 374 #define HDSPM_midi1IRQPending 0x80000000 375 #define HDSPM_midi2IRQPending 0x20000000 376 #define HDSPM_midi2IRQPendingAES 0x00000020 377 #define HDSPM_midi3IRQPending 0x00200000 378 379 /* --- status bit helpers */ 380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 381 HDSPM_madiFreq2|HDSPM_madiFreq3) 382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 391 392 /* Status2 Register bits */ /* MADI ONLY */ 393 394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 396 #define HDSPM_version2 (1<<2) 397 398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 400 401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ 404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */ 405 406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 407 #define HDSPM_SyncRef1 0x20000 408 409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 412 413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 414 415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 422 423 #define HDSPM_status1_F_0 0x0400000 424 #define HDSPM_status1_F_1 0x0800000 425 #define HDSPM_status1_F_2 0x1000000 426 #define HDSPM_status1_F_3 0x2000000 427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 428 429 430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 431 HDSPM_SelSyncRef2) 432 #define HDSPM_SelSyncRef_WORD 0 433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 437 HDSPM_SelSyncRef2) 438 439 /* 440 For AES32, bits for status, status2 and timecode are different 441 */ 442 /* status */ 443 #define HDSPM_AES32_wcLock 0x0200000 444 #define HDSPM_AES32_wcSync 0x0100000 445 #define HDSPM_AES32_wcFreq_bit 22 446 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 447 HDSPM_bit2freq */ 448 #define HDSPM_AES32_syncref_bit 16 449 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 450 451 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 452 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 453 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 454 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 455 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 456 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 457 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 458 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 459 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 460 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 461 462 /* status2 */ 463 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 464 #define HDSPM_LockAES 0x80 465 #define HDSPM_LockAES1 0x80 466 #define HDSPM_LockAES2 0x40 467 #define HDSPM_LockAES3 0x20 468 #define HDSPM_LockAES4 0x10 469 #define HDSPM_LockAES5 0x8 470 #define HDSPM_LockAES6 0x4 471 #define HDSPM_LockAES7 0x2 472 #define HDSPM_LockAES8 0x1 473 /* 474 Timecode 475 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 476 AES i+1 477 bits 3210 478 0001 32kHz 479 0010 44.1kHz 480 0011 48kHz 481 0100 64kHz 482 0101 88.2kHz 483 0110 96kHz 484 0111 128kHz 485 1000 176.4kHz 486 1001 192kHz 487 NB: Timecode register doesn't seem to work on AES32 card revision 230 488 */ 489 490 /* Mixer Values */ 491 #define UNITY_GAIN 32768 /* = 65536/2 */ 492 #define MINUS_INFINITY_GAIN 0 493 494 /* Number of channels for different Speed Modes */ 495 #define MADI_SS_CHANNELS 64 496 #define MADI_DS_CHANNELS 32 497 #define MADI_QS_CHANNELS 16 498 499 #define RAYDAT_SS_CHANNELS 36 500 #define RAYDAT_DS_CHANNELS 20 501 #define RAYDAT_QS_CHANNELS 12 502 503 #define AIO_IN_SS_CHANNELS 14 504 #define AIO_IN_DS_CHANNELS 10 505 #define AIO_IN_QS_CHANNELS 8 506 #define AIO_OUT_SS_CHANNELS 16 507 #define AIO_OUT_DS_CHANNELS 12 508 #define AIO_OUT_QS_CHANNELS 10 509 510 #define AES32_CHANNELS 16 511 512 /* the size of a substream (1 mono data stream) */ 513 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 514 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 515 516 /* the size of the area we need to allocate for DMA transfers. the 517 size is the same regardless of the number of channels, and 518 also the latency to use. 519 for one direction !!! 520 */ 521 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 522 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 523 524 #define HDSPM_RAYDAT_REV 211 525 #define HDSPM_AIO_REV 212 526 #define HDSPM_MADIFACE_REV 213 527 528 /* speed factor modes */ 529 #define HDSPM_SPEED_SINGLE 0 530 #define HDSPM_SPEED_DOUBLE 1 531 #define HDSPM_SPEED_QUAD 2 532 533 /* names for speed modes */ 534 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 535 536 static char *texts_autosync_aes_tco[] = { "Word Clock", 537 "AES1", "AES2", "AES3", "AES4", 538 "AES5", "AES6", "AES7", "AES8", 539 "TCO" }; 540 static char *texts_autosync_aes[] = { "Word Clock", 541 "AES1", "AES2", "AES3", "AES4", 542 "AES5", "AES6", "AES7", "AES8" }; 543 static char *texts_autosync_madi_tco[] = { "Word Clock", 544 "MADI", "TCO", "Sync In" }; 545 static char *texts_autosync_madi[] = { "Word Clock", 546 "MADI", "Sync In" }; 547 548 static char *texts_autosync_raydat_tco[] = { 549 "Word Clock", 550 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 551 "AES", "SPDIF", "TCO", "Sync In" 552 }; 553 static char *texts_autosync_raydat[] = { 554 "Word Clock", 555 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 556 "AES", "SPDIF", "Sync In" 557 }; 558 static char *texts_autosync_aio_tco[] = { 559 "Word Clock", 560 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 561 }; 562 static char *texts_autosync_aio[] = { "Word Clock", 563 "ADAT", "AES", "SPDIF", "Sync In" }; 564 565 static char *texts_freq[] = { 566 "No Lock", 567 "32 kHz", 568 "44.1 kHz", 569 "48 kHz", 570 "64 kHz", 571 "88.2 kHz", 572 "96 kHz", 573 "128 kHz", 574 "176.4 kHz", 575 "192 kHz" 576 }; 577 578 static char *texts_ports_madi[] = { 579 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 580 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 581 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 582 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 583 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 584 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 585 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 586 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 587 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 588 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 589 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 590 }; 591 592 593 static char *texts_ports_raydat_ss[] = { 594 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 595 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 596 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 597 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 598 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 599 "ADAT4.7", "ADAT4.8", 600 "AES.L", "AES.R", 601 "SPDIF.L", "SPDIF.R" 602 }; 603 604 static char *texts_ports_raydat_ds[] = { 605 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 606 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 607 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 608 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 609 "AES.L", "AES.R", 610 "SPDIF.L", "SPDIF.R" 611 }; 612 613 static char *texts_ports_raydat_qs[] = { 614 "ADAT1.1", "ADAT1.2", 615 "ADAT2.1", "ADAT2.2", 616 "ADAT3.1", "ADAT3.2", 617 "ADAT4.1", "ADAT4.2", 618 "AES.L", "AES.R", 619 "SPDIF.L", "SPDIF.R" 620 }; 621 622 623 static char *texts_ports_aio_in_ss[] = { 624 "Analogue.L", "Analogue.R", 625 "AES.L", "AES.R", 626 "SPDIF.L", "SPDIF.R", 627 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 628 "ADAT.7", "ADAT.8" 629 }; 630 631 static char *texts_ports_aio_out_ss[] = { 632 "Analogue.L", "Analogue.R", 633 "AES.L", "AES.R", 634 "SPDIF.L", "SPDIF.R", 635 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 636 "ADAT.7", "ADAT.8", 637 "Phone.L", "Phone.R" 638 }; 639 640 static char *texts_ports_aio_in_ds[] = { 641 "Analogue.L", "Analogue.R", 642 "AES.L", "AES.R", 643 "SPDIF.L", "SPDIF.R", 644 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 645 }; 646 647 static char *texts_ports_aio_out_ds[] = { 648 "Analogue.L", "Analogue.R", 649 "AES.L", "AES.R", 650 "SPDIF.L", "SPDIF.R", 651 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 652 "Phone.L", "Phone.R" 653 }; 654 655 static char *texts_ports_aio_in_qs[] = { 656 "Analogue.L", "Analogue.R", 657 "AES.L", "AES.R", 658 "SPDIF.L", "SPDIF.R", 659 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 660 }; 661 662 static char *texts_ports_aio_out_qs[] = { 663 "Analogue.L", "Analogue.R", 664 "AES.L", "AES.R", 665 "SPDIF.L", "SPDIF.R", 666 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 667 "Phone.L", "Phone.R" 668 }; 669 670 static char *texts_ports_aes32[] = { 671 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 672 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 673 "AES.15", "AES.16" 674 }; 675 676 /* These tables map the ALSA channels 1..N to the channels that we 677 need to use in order to find the relevant channel buffer. RME 678 refers to this kind of mapping as between "the ADAT channel and 679 the DMA channel." We index it using the logical audio channel, 680 and the value is the DMA channel (i.e. channel buffer number) 681 where the data for that channel can be read/written from/to. 682 */ 683 684 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 685 0, 1, 2, 3, 4, 5, 6, 7, 686 8, 9, 10, 11, 12, 13, 14, 15, 687 16, 17, 18, 19, 20, 21, 22, 23, 688 24, 25, 26, 27, 28, 29, 30, 31, 689 32, 33, 34, 35, 36, 37, 38, 39, 690 40, 41, 42, 43, 44, 45, 46, 47, 691 48, 49, 50, 51, 52, 53, 54, 55, 692 56, 57, 58, 59, 60, 61, 62, 63 693 }; 694 695 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 696 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 697 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 698 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 699 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 700 0, 1, /* AES */ 701 2, 3, /* SPDIF */ 702 -1, -1, -1, -1, 703 -1, -1, -1, -1, -1, -1, -1, -1, 704 -1, -1, -1, -1, -1, -1, -1, -1, 705 -1, -1, -1, -1, -1, -1, -1, -1, 706 }; 707 708 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 709 4, 5, 6, 7, /* ADAT 1 */ 710 8, 9, 10, 11, /* ADAT 2 */ 711 12, 13, 14, 15, /* ADAT 3 */ 712 16, 17, 18, 19, /* ADAT 4 */ 713 0, 1, /* AES */ 714 2, 3, /* SPDIF */ 715 -1, -1, -1, -1, 716 -1, -1, -1, -1, -1, -1, -1, -1, 717 -1, -1, -1, -1, -1, -1, -1, -1, 718 -1, -1, -1, -1, -1, -1, -1, -1, 719 -1, -1, -1, -1, -1, -1, -1, -1, 720 -1, -1, -1, -1, -1, -1, -1, -1, 721 }; 722 723 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 724 4, 5, /* ADAT 1 */ 725 6, 7, /* ADAT 2 */ 726 8, 9, /* ADAT 3 */ 727 10, 11, /* ADAT 4 */ 728 0, 1, /* AES */ 729 2, 3, /* SPDIF */ 730 -1, -1, -1, -1, 731 -1, -1, -1, -1, -1, -1, -1, -1, 732 -1, -1, -1, -1, -1, -1, -1, -1, 733 -1, -1, -1, -1, -1, -1, -1, -1, 734 -1, -1, -1, -1, -1, -1, -1, -1, 735 -1, -1, -1, -1, -1, -1, -1, -1, 736 -1, -1, -1, -1, -1, -1, -1, -1, 737 }; 738 739 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 740 0, 1, /* line in */ 741 8, 9, /* aes in, */ 742 10, 11, /* spdif in */ 743 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 744 -1, -1, 745 -1, -1, -1, -1, -1, -1, -1, -1, 746 -1, -1, -1, -1, -1, -1, -1, -1, 747 -1, -1, -1, -1, -1, -1, -1, -1, 748 -1, -1, -1, -1, -1, -1, -1, -1, 749 -1, -1, -1, -1, -1, -1, -1, -1, 750 -1, -1, -1, -1, -1, -1, -1, -1, 751 }; 752 753 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 754 0, 1, /* line out */ 755 8, 9, /* aes out */ 756 10, 11, /* spdif out */ 757 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 758 6, 7, /* phone out */ 759 -1, -1, -1, -1, -1, -1, -1, -1, 760 -1, -1, -1, -1, -1, -1, -1, -1, 761 -1, -1, -1, -1, -1, -1, -1, -1, 762 -1, -1, -1, -1, -1, -1, -1, -1, 763 -1, -1, -1, -1, -1, -1, -1, -1, 764 -1, -1, -1, -1, -1, -1, -1, -1, 765 }; 766 767 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 768 0, 1, /* line in */ 769 8, 9, /* aes in */ 770 10, 11, /* spdif in */ 771 12, 14, 16, 18, /* adat in */ 772 -1, -1, -1, -1, -1, -1, 773 -1, -1, -1, -1, -1, -1, -1, -1, 774 -1, -1, -1, -1, -1, -1, -1, -1, 775 -1, -1, -1, -1, -1, -1, -1, -1, 776 -1, -1, -1, -1, -1, -1, -1, -1, 777 -1, -1, -1, -1, -1, -1, -1, -1, 778 -1, -1, -1, -1, -1, -1, -1, -1 779 }; 780 781 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 782 0, 1, /* line out */ 783 8, 9, /* aes out */ 784 10, 11, /* spdif out */ 785 12, 14, 16, 18, /* adat out */ 786 6, 7, /* phone out */ 787 -1, -1, -1, -1, 788 -1, -1, -1, -1, -1, -1, -1, -1, 789 -1, -1, -1, -1, -1, -1, -1, -1, 790 -1, -1, -1, -1, -1, -1, -1, -1, 791 -1, -1, -1, -1, -1, -1, -1, -1, 792 -1, -1, -1, -1, -1, -1, -1, -1, 793 -1, -1, -1, -1, -1, -1, -1, -1 794 }; 795 796 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 797 0, 1, /* line in */ 798 8, 9, /* aes in */ 799 10, 11, /* spdif in */ 800 12, 16, /* adat in */ 801 -1, -1, -1, -1, -1, -1, -1, -1, 802 -1, -1, -1, -1, -1, -1, -1, -1, 803 -1, -1, -1, -1, -1, -1, -1, -1, 804 -1, -1, -1, -1, -1, -1, -1, -1, 805 -1, -1, -1, -1, -1, -1, -1, -1, 806 -1, -1, -1, -1, -1, -1, -1, -1, 807 -1, -1, -1, -1, -1, -1, -1, -1 808 }; 809 810 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 811 0, 1, /* line out */ 812 8, 9, /* aes out */ 813 10, 11, /* spdif out */ 814 12, 16, /* adat out */ 815 6, 7, /* phone out */ 816 -1, -1, -1, -1, -1, -1, 817 -1, -1, -1, -1, -1, -1, -1, -1, 818 -1, -1, -1, -1, -1, -1, -1, -1, 819 -1, -1, -1, -1, -1, -1, -1, -1, 820 -1, -1, -1, -1, -1, -1, -1, -1, 821 -1, -1, -1, -1, -1, -1, -1, -1, 822 -1, -1, -1, -1, -1, -1, -1, -1 823 }; 824 825 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 826 0, 1, 2, 3, 4, 5, 6, 7, 827 8, 9, 10, 11, 12, 13, 14, 15, 828 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1, 831 -1, -1, -1, -1, -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1, 833 -1, -1, -1, -1, -1, -1, -1, -1 834 }; 835 836 struct hdspm_midi { 837 struct hdspm *hdspm; 838 int id; 839 struct snd_rawmidi *rmidi; 840 struct snd_rawmidi_substream *input; 841 struct snd_rawmidi_substream *output; 842 char istimer; /* timer in use */ 843 struct timer_list timer; 844 spinlock_t lock; 845 int pending; 846 int dataIn; 847 int statusIn; 848 int dataOut; 849 int statusOut; 850 int ie; 851 int irq; 852 }; 853 854 struct hdspm_tco { 855 int input; 856 int framerate; 857 int wordclock; 858 int samplerate; 859 int pull; 860 int term; /* 0 = off, 1 = on */ 861 }; 862 863 struct hdspm { 864 spinlock_t lock; 865 /* only one playback and/or capture stream */ 866 struct snd_pcm_substream *capture_substream; 867 struct snd_pcm_substream *playback_substream; 868 869 char *card_name; /* for procinfo */ 870 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 871 872 uint8_t io_type; 873 874 int monitor_outs; /* set up monitoring outs init flag */ 875 876 u32 control_register; /* cached value */ 877 u32 control2_register; /* cached value */ 878 u32 settings_register; 879 880 struct hdspm_midi midi[4]; 881 struct tasklet_struct midi_tasklet; 882 883 size_t period_bytes; 884 unsigned char ss_in_channels; 885 unsigned char ds_in_channels; 886 unsigned char qs_in_channels; 887 unsigned char ss_out_channels; 888 unsigned char ds_out_channels; 889 unsigned char qs_out_channels; 890 891 unsigned char max_channels_in; 892 unsigned char max_channels_out; 893 894 signed char *channel_map_in; 895 signed char *channel_map_out; 896 897 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 898 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 899 900 char **port_names_in; 901 char **port_names_out; 902 903 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 904 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 905 906 unsigned char *playback_buffer; /* suitably aligned address */ 907 unsigned char *capture_buffer; /* suitably aligned address */ 908 909 pid_t capture_pid; /* process id which uses capture */ 910 pid_t playback_pid; /* process id which uses capture */ 911 int running; /* running status */ 912 913 int last_external_sample_rate; /* samplerate mystic ... */ 914 int last_internal_sample_rate; 915 int system_sample_rate; 916 917 int dev; /* Hardware vars... */ 918 int irq; 919 unsigned long port; 920 void __iomem *iobase; 921 922 int irq_count; /* for debug */ 923 int midiPorts; 924 925 struct snd_card *card; /* one card */ 926 struct snd_pcm *pcm; /* has one pcm */ 927 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 928 struct pci_dev *pci; /* and an pci info */ 929 930 /* Mixer vars */ 931 /* fast alsa mixer */ 932 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 933 /* but input to much, so not used */ 934 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 935 /* full mixer accessible over mixer ioctl or hwdep-device */ 936 struct hdspm_mixer *mixer; 937 938 struct hdspm_tco *tco; /* NULL if no TCO detected */ 939 940 char **texts_autosync; 941 int texts_autosync_items; 942 943 cycles_t last_interrupt; 944 945 unsigned int serial; 946 947 struct hdspm_peak_rms peak_rms; 948 }; 949 950 951 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 952 { 953 .vendor = PCI_VENDOR_ID_XILINX, 954 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 955 .subvendor = PCI_ANY_ID, 956 .subdevice = PCI_ANY_ID, 957 .class = 0, 958 .class_mask = 0, 959 .driver_data = 0}, 960 {0,} 961 }; 962 963 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 964 965 /* prototypes */ 966 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 967 struct hdspm *hdspm); 968 static int snd_hdspm_create_pcm(struct snd_card *card, 969 struct hdspm *hdspm); 970 971 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 972 static inline int hdspm_get_pll_freq(struct hdspm *hdspm); 973 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 974 static int hdspm_autosync_ref(struct hdspm *hdspm); 975 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 976 static int hdspm_system_clock_mode(struct hdspm *hdspm); 977 static void hdspm_set_sgbuf(struct hdspm *hdspm, 978 struct snd_pcm_substream *substream, 979 unsigned int reg, int channels); 980 981 static inline int HDSPM_bit2freq(int n) 982 { 983 static const int bit2freq_tab[] = { 984 0, 32000, 44100, 48000, 64000, 88200, 985 96000, 128000, 176400, 192000 }; 986 if (n < 1 || n > 9) 987 return 0; 988 return bit2freq_tab[n]; 989 } 990 991 /* Write/read to/from HDSPM with Adresses in Bytes 992 not words but only 32Bit writes are allowed */ 993 994 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 995 unsigned int val) 996 { 997 writel(val, hdspm->iobase + reg); 998 } 999 1000 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 1001 { 1002 return readl(hdspm->iobase + reg); 1003 } 1004 1005 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1006 mixer is write only on hardware so we have to cache him for read 1007 each fader is a u32, but uses only the first 16 bit */ 1008 1009 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1010 unsigned int in) 1011 { 1012 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1013 return 0; 1014 1015 return hdspm->mixer->ch[chan].in[in]; 1016 } 1017 1018 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1019 unsigned int pb) 1020 { 1021 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1022 return 0; 1023 return hdspm->mixer->ch[chan].pb[pb]; 1024 } 1025 1026 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1027 unsigned int in, unsigned short data) 1028 { 1029 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1030 return -1; 1031 1032 hdspm_write(hdspm, 1033 HDSPM_MADI_mixerBase + 1034 ((in + 128 * chan) * sizeof(u32)), 1035 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1036 return 0; 1037 } 1038 1039 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1040 unsigned int pb, unsigned short data) 1041 { 1042 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1043 return -1; 1044 1045 hdspm_write(hdspm, 1046 HDSPM_MADI_mixerBase + 1047 ((64 + pb + 128 * chan) * sizeof(u32)), 1048 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1049 return 0; 1050 } 1051 1052 1053 /* enable DMA for specific channels, now available for DSP-MADI */ 1054 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1055 { 1056 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1057 } 1058 1059 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1060 { 1061 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1062 } 1063 1064 /* check if same process is writing and reading */ 1065 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1066 { 1067 unsigned long flags; 1068 int ret = 1; 1069 1070 spin_lock_irqsave(&hdspm->lock, flags); 1071 if ((hdspm->playback_pid != hdspm->capture_pid) && 1072 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1073 ret = 0; 1074 } 1075 spin_unlock_irqrestore(&hdspm->lock, flags); 1076 return ret; 1077 } 1078 1079 /* round arbitary sample rates to commonly known rates */ 1080 static int hdspm_round_frequency(int rate) 1081 { 1082 if (rate < 38050) 1083 return 32000; 1084 if (rate < 46008) 1085 return 44100; 1086 else 1087 return 48000; 1088 } 1089 1090 static int hdspm_tco_sync_check(struct hdspm *hdspm); 1091 static int hdspm_sync_in_sync_check(struct hdspm *hdspm); 1092 1093 /* check for external sample rate */ 1094 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1095 { 1096 unsigned int status, status2, timecode; 1097 int syncref, rate = 0, rate_bits; 1098 1099 switch (hdspm->io_type) { 1100 case AES32: 1101 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1102 status = hdspm_read(hdspm, HDSPM_statusRegister); 1103 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1104 1105 syncref = hdspm_autosync_ref(hdspm); 1106 1107 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1108 status & HDSPM_AES32_wcLock) 1109 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1110 1111 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1112 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1113 status2 & (HDSPM_LockAES >> 1114 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1115 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1116 return 0; 1117 break; 1118 1119 case MADIface: 1120 status = hdspm_read(hdspm, HDSPM_statusRegister); 1121 1122 if (!(status & HDSPM_madiLock)) { 1123 rate = 0; /* no lock */ 1124 } else { 1125 switch (status & (HDSPM_status1_freqMask)) { 1126 case HDSPM_status1_F_0*1: 1127 rate = 32000; break; 1128 case HDSPM_status1_F_0*2: 1129 rate = 44100; break; 1130 case HDSPM_status1_F_0*3: 1131 rate = 48000; break; 1132 case HDSPM_status1_F_0*4: 1133 rate = 64000; break; 1134 case HDSPM_status1_F_0*5: 1135 rate = 88200; break; 1136 case HDSPM_status1_F_0*6: 1137 rate = 96000; break; 1138 case HDSPM_status1_F_0*7: 1139 rate = 128000; break; 1140 case HDSPM_status1_F_0*8: 1141 rate = 176400; break; 1142 case HDSPM_status1_F_0*9: 1143 rate = 192000; break; 1144 default: 1145 rate = 0; break; 1146 } 1147 } 1148 1149 break; 1150 1151 case MADI: 1152 case AIO: 1153 case RayDAT: 1154 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1155 status = hdspm_read(hdspm, HDSPM_statusRegister); 1156 rate = 0; 1157 1158 /* if wordclock has synced freq and wordclock is valid */ 1159 if ((status2 & HDSPM_wcLock) != 0 && 1160 (status2 & HDSPM_SelSyncRef0) == 0) { 1161 1162 rate_bits = status2 & HDSPM_wcFreqMask; 1163 1164 1165 switch (rate_bits) { 1166 case HDSPM_wcFreq32: 1167 rate = 32000; 1168 break; 1169 case HDSPM_wcFreq44_1: 1170 rate = 44100; 1171 break; 1172 case HDSPM_wcFreq48: 1173 rate = 48000; 1174 break; 1175 case HDSPM_wcFreq64: 1176 rate = 64000; 1177 break; 1178 case HDSPM_wcFreq88_2: 1179 rate = 88200; 1180 break; 1181 case HDSPM_wcFreq96: 1182 rate = 96000; 1183 break; 1184 default: 1185 rate = 0; 1186 break; 1187 } 1188 } 1189 1190 /* if rate detected and Syncref is Word than have it, 1191 * word has priority to MADI 1192 */ 1193 if (rate != 0 && 1194 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1195 return rate; 1196 1197 /* maybe a madi input (which is taken if sel sync is madi) */ 1198 if (status & HDSPM_madiLock) { 1199 rate_bits = status & HDSPM_madiFreqMask; 1200 1201 switch (rate_bits) { 1202 case HDSPM_madiFreq32: 1203 rate = 32000; 1204 break; 1205 case HDSPM_madiFreq44_1: 1206 rate = 44100; 1207 break; 1208 case HDSPM_madiFreq48: 1209 rate = 48000; 1210 break; 1211 case HDSPM_madiFreq64: 1212 rate = 64000; 1213 break; 1214 case HDSPM_madiFreq88_2: 1215 rate = 88200; 1216 break; 1217 case HDSPM_madiFreq96: 1218 rate = 96000; 1219 break; 1220 case HDSPM_madiFreq128: 1221 rate = 128000; 1222 break; 1223 case HDSPM_madiFreq176_4: 1224 rate = 176400; 1225 break; 1226 case HDSPM_madiFreq192: 1227 rate = 192000; 1228 break; 1229 default: 1230 rate = 0; 1231 break; 1232 } 1233 1234 } /* endif HDSPM_madiLock */ 1235 1236 /* check sample rate from TCO or SYNC_IN */ 1237 { 1238 bool is_valid_input = 0; 1239 bool has_sync = 0; 1240 1241 syncref = hdspm_autosync_ref(hdspm); 1242 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) { 1243 is_valid_input = 1; 1244 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1245 hdspm_tco_sync_check(hdspm)); 1246 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) { 1247 is_valid_input = 1; 1248 has_sync = (HDSPM_SYNC_CHECK_SYNC == 1249 hdspm_sync_in_sync_check(hdspm)); 1250 } 1251 1252 if (is_valid_input && has_sync) { 1253 rate = hdspm_round_frequency( 1254 hdspm_get_pll_freq(hdspm)); 1255 } 1256 } 1257 1258 /* QS and DS rates normally can not be detected 1259 * automatically by the card. Only exception is MADI 1260 * in 96k frame mode. 1261 * 1262 * So if we read SS values (32 .. 48k), check for 1263 * user-provided DS/QS bits in the control register 1264 * and multiply the base frequency accordingly. 1265 */ 1266 if (rate <= 48000) { 1267 if (hdspm->control_register & HDSPM_QuadSpeed) 1268 rate *= 4; 1269 else if (hdspm->control_register & 1270 HDSPM_DoubleSpeed) 1271 rate *= 2; 1272 } 1273 break; 1274 } 1275 1276 return rate; 1277 } 1278 1279 /* return latency in samples per period */ 1280 static int hdspm_get_latency(struct hdspm *hdspm) 1281 { 1282 int n; 1283 1284 n = hdspm_decode_latency(hdspm->control_register); 1285 1286 /* Special case for new RME cards with 32 samples period size. 1287 * The three latency bits in the control register 1288 * (HDSP_LatencyMask) encode latency values of 64 samples as 1289 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1290 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1291 * it corresponds to 32 samples. 1292 */ 1293 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1294 n = -1; 1295 1296 return 1 << (n + 6); 1297 } 1298 1299 /* Latency function */ 1300 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1301 { 1302 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1303 } 1304 1305 1306 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1307 { 1308 int position; 1309 1310 position = hdspm_read(hdspm, HDSPM_statusRegister); 1311 1312 switch (hdspm->io_type) { 1313 case RayDAT: 1314 case AIO: 1315 position &= HDSPM_BufferPositionMask; 1316 position /= 4; /* Bytes per sample */ 1317 break; 1318 default: 1319 position = (position & HDSPM_BufferID) ? 1320 (hdspm->period_bytes / 4) : 0; 1321 } 1322 1323 return position; 1324 } 1325 1326 1327 static inline void hdspm_start_audio(struct hdspm * s) 1328 { 1329 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1330 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1331 } 1332 1333 static inline void hdspm_stop_audio(struct hdspm * s) 1334 { 1335 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1336 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1337 } 1338 1339 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1340 static void hdspm_silence_playback(struct hdspm *hdspm) 1341 { 1342 int i; 1343 int n = hdspm->period_bytes; 1344 void *buf = hdspm->playback_buffer; 1345 1346 if (buf == NULL) 1347 return; 1348 1349 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1350 memset(buf, 0, n); 1351 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1352 } 1353 } 1354 1355 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1356 { 1357 int n; 1358 1359 spin_lock_irq(&s->lock); 1360 1361 if (32 == frames) { 1362 /* Special case for new RME cards like RayDAT/AIO which 1363 * support period sizes of 32 samples. Since latency is 1364 * encoded in the three bits of HDSP_LatencyMask, we can only 1365 * have values from 0 .. 7. While 0 still means 64 samples and 1366 * 6 represents 4096 samples on all cards, 7 represents 8192 1367 * on older cards and 32 samples on new cards. 1368 * 1369 * In other words, period size in samples is calculated by 1370 * 2^(n+6) with n ranging from 0 .. 7. 1371 */ 1372 n = 7; 1373 } else { 1374 frames >>= 7; 1375 n = 0; 1376 while (frames) { 1377 n++; 1378 frames >>= 1; 1379 } 1380 } 1381 1382 s->control_register &= ~HDSPM_LatencyMask; 1383 s->control_register |= hdspm_encode_latency(n); 1384 1385 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1386 1387 hdspm_compute_period_size(s); 1388 1389 spin_unlock_irq(&s->lock); 1390 1391 return 0; 1392 } 1393 1394 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1395 { 1396 u64 freq_const; 1397 1398 if (period == 0) 1399 return 0; 1400 1401 switch (hdspm->io_type) { 1402 case MADI: 1403 case AES32: 1404 freq_const = 110069313433624ULL; 1405 break; 1406 case RayDAT: 1407 case AIO: 1408 freq_const = 104857600000000ULL; 1409 break; 1410 case MADIface: 1411 freq_const = 131072000000000ULL; 1412 break; 1413 default: 1414 snd_BUG(); 1415 return 0; 1416 } 1417 1418 return div_u64(freq_const, period); 1419 } 1420 1421 1422 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1423 { 1424 u64 n; 1425 1426 if (rate >= 112000) 1427 rate /= 4; 1428 else if (rate >= 56000) 1429 rate /= 2; 1430 1431 switch (hdspm->io_type) { 1432 case MADIface: 1433 n = 131072000000000ULL; /* 125 MHz */ 1434 break; 1435 case MADI: 1436 case AES32: 1437 n = 110069313433624ULL; /* 105 MHz */ 1438 break; 1439 case RayDAT: 1440 case AIO: 1441 n = 104857600000000ULL; /* 100 MHz */ 1442 break; 1443 default: 1444 snd_BUG(); 1445 return; 1446 } 1447 1448 n = div_u64(n, rate); 1449 /* n should be less than 2^32 for being written to FREQ register */ 1450 snd_BUG_ON(n >> 32); 1451 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1452 } 1453 1454 /* dummy set rate lets see what happens */ 1455 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1456 { 1457 int current_rate; 1458 int rate_bits; 1459 int not_set = 0; 1460 int current_speed, target_speed; 1461 1462 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1463 it (e.g. during module initialization). 1464 */ 1465 1466 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1467 1468 /* SLAVE --- */ 1469 if (called_internally) { 1470 1471 /* request from ctl or card initialization 1472 just make a warning an remember setting 1473 for future master mode switching */ 1474 1475 snd_printk(KERN_WARNING "HDSPM: " 1476 "Warning: device is not running " 1477 "as a clock master.\n"); 1478 not_set = 1; 1479 } else { 1480 1481 /* hw_param request while in AutoSync mode */ 1482 int external_freq = 1483 hdspm_external_sample_rate(hdspm); 1484 1485 if (hdspm_autosync_ref(hdspm) == 1486 HDSPM_AUTOSYNC_FROM_NONE) { 1487 1488 snd_printk(KERN_WARNING "HDSPM: " 1489 "Detected no Externel Sync \n"); 1490 not_set = 1; 1491 1492 } else if (rate != external_freq) { 1493 1494 snd_printk(KERN_WARNING "HDSPM: " 1495 "Warning: No AutoSync source for " 1496 "requested rate\n"); 1497 not_set = 1; 1498 } 1499 } 1500 } 1501 1502 current_rate = hdspm->system_sample_rate; 1503 1504 /* Changing between Singe, Double and Quad speed is not 1505 allowed if any substreams are open. This is because such a change 1506 causes a shift in the location of the DMA buffers and a reduction 1507 in the number of available buffers. 1508 1509 Note that a similar but essentially insoluble problem exists for 1510 externally-driven rate changes. All we can do is to flag rate 1511 changes in the read/write routines. 1512 */ 1513 1514 if (current_rate <= 48000) 1515 current_speed = HDSPM_SPEED_SINGLE; 1516 else if (current_rate <= 96000) 1517 current_speed = HDSPM_SPEED_DOUBLE; 1518 else 1519 current_speed = HDSPM_SPEED_QUAD; 1520 1521 if (rate <= 48000) 1522 target_speed = HDSPM_SPEED_SINGLE; 1523 else if (rate <= 96000) 1524 target_speed = HDSPM_SPEED_DOUBLE; 1525 else 1526 target_speed = HDSPM_SPEED_QUAD; 1527 1528 switch (rate) { 1529 case 32000: 1530 rate_bits = HDSPM_Frequency32KHz; 1531 break; 1532 case 44100: 1533 rate_bits = HDSPM_Frequency44_1KHz; 1534 break; 1535 case 48000: 1536 rate_bits = HDSPM_Frequency48KHz; 1537 break; 1538 case 64000: 1539 rate_bits = HDSPM_Frequency64KHz; 1540 break; 1541 case 88200: 1542 rate_bits = HDSPM_Frequency88_2KHz; 1543 break; 1544 case 96000: 1545 rate_bits = HDSPM_Frequency96KHz; 1546 break; 1547 case 128000: 1548 rate_bits = HDSPM_Frequency128KHz; 1549 break; 1550 case 176400: 1551 rate_bits = HDSPM_Frequency176_4KHz; 1552 break; 1553 case 192000: 1554 rate_bits = HDSPM_Frequency192KHz; 1555 break; 1556 default: 1557 return -EINVAL; 1558 } 1559 1560 if (current_speed != target_speed 1561 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1562 snd_printk 1563 (KERN_ERR "HDSPM: " 1564 "cannot change from %s speed to %s speed mode " 1565 "(capture PID = %d, playback PID = %d)\n", 1566 hdspm_speed_names[current_speed], 1567 hdspm_speed_names[target_speed], 1568 hdspm->capture_pid, hdspm->playback_pid); 1569 return -EBUSY; 1570 } 1571 1572 hdspm->control_register &= ~HDSPM_FrequencyMask; 1573 hdspm->control_register |= rate_bits; 1574 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1575 1576 /* For AES32, need to set DDS value in FREQ register 1577 For MADI, also apparently */ 1578 hdspm_set_dds_value(hdspm, rate); 1579 1580 if (AES32 == hdspm->io_type && rate != current_rate) 1581 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1582 1583 hdspm->system_sample_rate = rate; 1584 1585 if (rate <= 48000) { 1586 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1587 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1588 hdspm->max_channels_in = hdspm->ss_in_channels; 1589 hdspm->max_channels_out = hdspm->ss_out_channels; 1590 hdspm->port_names_in = hdspm->port_names_in_ss; 1591 hdspm->port_names_out = hdspm->port_names_out_ss; 1592 } else if (rate <= 96000) { 1593 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1594 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1595 hdspm->max_channels_in = hdspm->ds_in_channels; 1596 hdspm->max_channels_out = hdspm->ds_out_channels; 1597 hdspm->port_names_in = hdspm->port_names_in_ds; 1598 hdspm->port_names_out = hdspm->port_names_out_ds; 1599 } else { 1600 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1601 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1602 hdspm->max_channels_in = hdspm->qs_in_channels; 1603 hdspm->max_channels_out = hdspm->qs_out_channels; 1604 hdspm->port_names_in = hdspm->port_names_in_qs; 1605 hdspm->port_names_out = hdspm->port_names_out_qs; 1606 } 1607 1608 if (not_set != 0) 1609 return -1; 1610 1611 return 0; 1612 } 1613 1614 /* mainly for init to 0 on load */ 1615 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1616 { 1617 int i, j; 1618 unsigned int gain; 1619 1620 if (sgain > UNITY_GAIN) 1621 gain = UNITY_GAIN; 1622 else if (sgain < 0) 1623 gain = 0; 1624 else 1625 gain = sgain; 1626 1627 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1628 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1629 hdspm_write_in_gain(hdspm, i, j, gain); 1630 hdspm_write_pb_gain(hdspm, i, j, gain); 1631 } 1632 } 1633 1634 /*---------------------------------------------------------------------------- 1635 MIDI 1636 ----------------------------------------------------------------------------*/ 1637 1638 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1639 int id) 1640 { 1641 /* the hardware already does the relevant bit-mask with 0xff */ 1642 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1643 } 1644 1645 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1646 int val) 1647 { 1648 /* the hardware already does the relevant bit-mask with 0xff */ 1649 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1650 } 1651 1652 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1653 { 1654 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1655 } 1656 1657 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1658 { 1659 int fifo_bytes_used; 1660 1661 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1662 1663 if (fifo_bytes_used < 128) 1664 return 128 - fifo_bytes_used; 1665 else 1666 return 0; 1667 } 1668 1669 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1670 { 1671 while (snd_hdspm_midi_input_available (hdspm, id)) 1672 snd_hdspm_midi_read_byte (hdspm, id); 1673 } 1674 1675 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1676 { 1677 unsigned long flags; 1678 int n_pending; 1679 int to_write; 1680 int i; 1681 unsigned char buf[128]; 1682 1683 /* Output is not interrupt driven */ 1684 1685 spin_lock_irqsave (&hmidi->lock, flags); 1686 if (hmidi->output && 1687 !snd_rawmidi_transmit_empty (hmidi->output)) { 1688 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1689 hmidi->id); 1690 if (n_pending > 0) { 1691 if (n_pending > (int)sizeof (buf)) 1692 n_pending = sizeof (buf); 1693 1694 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1695 n_pending); 1696 if (to_write > 0) { 1697 for (i = 0; i < to_write; ++i) 1698 snd_hdspm_midi_write_byte (hmidi->hdspm, 1699 hmidi->id, 1700 buf[i]); 1701 } 1702 } 1703 } 1704 spin_unlock_irqrestore (&hmidi->lock, flags); 1705 return 0; 1706 } 1707 1708 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1709 { 1710 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1711 * input FIFO size 1712 */ 1713 unsigned long flags; 1714 int n_pending; 1715 int i; 1716 1717 spin_lock_irqsave (&hmidi->lock, flags); 1718 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1719 if (n_pending > 0) { 1720 if (hmidi->input) { 1721 if (n_pending > (int)sizeof (buf)) 1722 n_pending = sizeof (buf); 1723 for (i = 0; i < n_pending; ++i) 1724 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1725 hmidi->id); 1726 if (n_pending) 1727 snd_rawmidi_receive (hmidi->input, buf, 1728 n_pending); 1729 } else { 1730 /* flush the MIDI input FIFO */ 1731 while (n_pending--) 1732 snd_hdspm_midi_read_byte (hmidi->hdspm, 1733 hmidi->id); 1734 } 1735 } 1736 hmidi->pending = 0; 1737 spin_unlock_irqrestore(&hmidi->lock, flags); 1738 1739 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1740 hmidi->hdspm->control_register |= hmidi->ie; 1741 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1742 hmidi->hdspm->control_register); 1743 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1744 1745 return snd_hdspm_midi_output_write (hmidi); 1746 } 1747 1748 static void 1749 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1750 { 1751 struct hdspm *hdspm; 1752 struct hdspm_midi *hmidi; 1753 unsigned long flags; 1754 1755 hmidi = substream->rmidi->private_data; 1756 hdspm = hmidi->hdspm; 1757 1758 spin_lock_irqsave (&hdspm->lock, flags); 1759 if (up) { 1760 if (!(hdspm->control_register & hmidi->ie)) { 1761 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1762 hdspm->control_register |= hmidi->ie; 1763 } 1764 } else { 1765 hdspm->control_register &= ~hmidi->ie; 1766 } 1767 1768 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1769 spin_unlock_irqrestore (&hdspm->lock, flags); 1770 } 1771 1772 static void snd_hdspm_midi_output_timer(unsigned long data) 1773 { 1774 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1775 unsigned long flags; 1776 1777 snd_hdspm_midi_output_write(hmidi); 1778 spin_lock_irqsave (&hmidi->lock, flags); 1779 1780 /* this does not bump hmidi->istimer, because the 1781 kernel automatically removed the timer when it 1782 expired, and we are now adding it back, thus 1783 leaving istimer wherever it was set before. 1784 */ 1785 1786 if (hmidi->istimer) { 1787 hmidi->timer.expires = 1 + jiffies; 1788 add_timer(&hmidi->timer); 1789 } 1790 1791 spin_unlock_irqrestore (&hmidi->lock, flags); 1792 } 1793 1794 static void 1795 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1796 { 1797 struct hdspm_midi *hmidi; 1798 unsigned long flags; 1799 1800 hmidi = substream->rmidi->private_data; 1801 spin_lock_irqsave (&hmidi->lock, flags); 1802 if (up) { 1803 if (!hmidi->istimer) { 1804 init_timer(&hmidi->timer); 1805 hmidi->timer.function = snd_hdspm_midi_output_timer; 1806 hmidi->timer.data = (unsigned long) hmidi; 1807 hmidi->timer.expires = 1 + jiffies; 1808 add_timer(&hmidi->timer); 1809 hmidi->istimer++; 1810 } 1811 } else { 1812 if (hmidi->istimer && --hmidi->istimer <= 0) 1813 del_timer (&hmidi->timer); 1814 } 1815 spin_unlock_irqrestore (&hmidi->lock, flags); 1816 if (up) 1817 snd_hdspm_midi_output_write(hmidi); 1818 } 1819 1820 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1821 { 1822 struct hdspm_midi *hmidi; 1823 1824 hmidi = substream->rmidi->private_data; 1825 spin_lock_irq (&hmidi->lock); 1826 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1827 hmidi->input = substream; 1828 spin_unlock_irq (&hmidi->lock); 1829 1830 return 0; 1831 } 1832 1833 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1834 { 1835 struct hdspm_midi *hmidi; 1836 1837 hmidi = substream->rmidi->private_data; 1838 spin_lock_irq (&hmidi->lock); 1839 hmidi->output = substream; 1840 spin_unlock_irq (&hmidi->lock); 1841 1842 return 0; 1843 } 1844 1845 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1846 { 1847 struct hdspm_midi *hmidi; 1848 1849 snd_hdspm_midi_input_trigger (substream, 0); 1850 1851 hmidi = substream->rmidi->private_data; 1852 spin_lock_irq (&hmidi->lock); 1853 hmidi->input = NULL; 1854 spin_unlock_irq (&hmidi->lock); 1855 1856 return 0; 1857 } 1858 1859 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1860 { 1861 struct hdspm_midi *hmidi; 1862 1863 snd_hdspm_midi_output_trigger (substream, 0); 1864 1865 hmidi = substream->rmidi->private_data; 1866 spin_lock_irq (&hmidi->lock); 1867 hmidi->output = NULL; 1868 spin_unlock_irq (&hmidi->lock); 1869 1870 return 0; 1871 } 1872 1873 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1874 { 1875 .open = snd_hdspm_midi_output_open, 1876 .close = snd_hdspm_midi_output_close, 1877 .trigger = snd_hdspm_midi_output_trigger, 1878 }; 1879 1880 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1881 { 1882 .open = snd_hdspm_midi_input_open, 1883 .close = snd_hdspm_midi_input_close, 1884 .trigger = snd_hdspm_midi_input_trigger, 1885 }; 1886 1887 static int snd_hdspm_create_midi(struct snd_card *card, 1888 struct hdspm *hdspm, int id) 1889 { 1890 int err; 1891 char buf[32]; 1892 1893 hdspm->midi[id].id = id; 1894 hdspm->midi[id].hdspm = hdspm; 1895 spin_lock_init (&hdspm->midi[id].lock); 1896 1897 if (0 == id) { 1898 if (MADIface == hdspm->io_type) { 1899 /* MIDI-over-MADI on HDSPe MADIface */ 1900 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1901 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1902 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1903 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1904 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1905 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1906 } else { 1907 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1908 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1909 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1910 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1911 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1912 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1913 } 1914 } else if (1 == id) { 1915 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1916 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1917 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1918 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1919 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1920 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1921 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1922 /* MIDI-over-MADI on HDSPe MADI */ 1923 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1924 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1925 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1926 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1927 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1928 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1929 } else if (2 == id) { 1930 /* TCO MTC, read only */ 1931 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1932 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1933 hdspm->midi[2].dataOut = -1; 1934 hdspm->midi[2].statusOut = -1; 1935 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1936 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1937 } else if (3 == id) { 1938 /* TCO MTC on HDSPe MADI */ 1939 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1940 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1941 hdspm->midi[3].dataOut = -1; 1942 hdspm->midi[3].statusOut = -1; 1943 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1944 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1945 } 1946 1947 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1948 (MADIface == hdspm->io_type)))) { 1949 if ((id == 0) && (MADIface == hdspm->io_type)) { 1950 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1951 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1952 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1953 } else { 1954 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 1955 } 1956 err = snd_rawmidi_new(card, buf, id, 1, 1, 1957 &hdspm->midi[id].rmidi); 1958 if (err < 0) 1959 return err; 1960 1961 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 1962 card->id, id+1); 1963 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1964 1965 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1966 SNDRV_RAWMIDI_STREAM_OUTPUT, 1967 &snd_hdspm_midi_output); 1968 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1969 SNDRV_RAWMIDI_STREAM_INPUT, 1970 &snd_hdspm_midi_input); 1971 1972 hdspm->midi[id].rmidi->info_flags |= 1973 SNDRV_RAWMIDI_INFO_OUTPUT | 1974 SNDRV_RAWMIDI_INFO_INPUT | 1975 SNDRV_RAWMIDI_INFO_DUPLEX; 1976 } else { 1977 /* TCO MTC, read only */ 1978 sprintf(buf, "%s MTC %d", card->shortname, id+1); 1979 err = snd_rawmidi_new(card, buf, id, 1, 1, 1980 &hdspm->midi[id].rmidi); 1981 if (err < 0) 1982 return err; 1983 1984 sprintf(hdspm->midi[id].rmidi->name, 1985 "%s MTC %d", card->id, id+1); 1986 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1987 1988 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1989 SNDRV_RAWMIDI_STREAM_INPUT, 1990 &snd_hdspm_midi_input); 1991 1992 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 1993 } 1994 1995 return 0; 1996 } 1997 1998 1999 static void hdspm_midi_tasklet(unsigned long arg) 2000 { 2001 struct hdspm *hdspm = (struct hdspm *)arg; 2002 int i = 0; 2003 2004 while (i < hdspm->midiPorts) { 2005 if (hdspm->midi[i].pending) 2006 snd_hdspm_midi_input_read(&hdspm->midi[i]); 2007 2008 i++; 2009 } 2010 } 2011 2012 2013 /*----------------------------------------------------------------------------- 2014 Status Interface 2015 ----------------------------------------------------------------------------*/ 2016 2017 /* get the system sample rate which is set */ 2018 2019 2020 static inline int hdspm_get_pll_freq(struct hdspm *hdspm) 2021 { 2022 unsigned int period, rate; 2023 2024 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 2025 rate = hdspm_calc_dds_value(hdspm, period); 2026 2027 return rate; 2028 } 2029 2030 /** 2031 * Calculate the real sample rate from the 2032 * current DDS value. 2033 **/ 2034 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 2035 { 2036 unsigned int rate; 2037 2038 rate = hdspm_get_pll_freq(hdspm); 2039 2040 if (rate > 207000) { 2041 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 2042 if (0 == hdspm_system_clock_mode(hdspm)) { 2043 /* master mode, return internal sample rate */ 2044 rate = hdspm->system_sample_rate; 2045 } else { 2046 /* slave mode, return external sample rate */ 2047 rate = hdspm_external_sample_rate(hdspm); 2048 } 2049 } 2050 2051 return rate; 2052 } 2053 2054 2055 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2056 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2057 .name = xname, \ 2058 .index = xindex, \ 2059 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2060 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2061 .info = snd_hdspm_info_system_sample_rate, \ 2062 .put = snd_hdspm_put_system_sample_rate, \ 2063 .get = snd_hdspm_get_system_sample_rate \ 2064 } 2065 2066 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2067 struct snd_ctl_elem_info *uinfo) 2068 { 2069 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2070 uinfo->count = 1; 2071 uinfo->value.integer.min = 27000; 2072 uinfo->value.integer.max = 207000; 2073 uinfo->value.integer.step = 1; 2074 return 0; 2075 } 2076 2077 2078 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2079 struct snd_ctl_elem_value * 2080 ucontrol) 2081 { 2082 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2083 2084 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2085 return 0; 2086 } 2087 2088 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2089 struct snd_ctl_elem_value * 2090 ucontrol) 2091 { 2092 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2093 2094 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]); 2095 return 0; 2096 } 2097 2098 2099 /** 2100 * Returns the WordClock sample rate class for the given card. 2101 **/ 2102 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2103 { 2104 int status; 2105 2106 switch (hdspm->io_type) { 2107 case RayDAT: 2108 case AIO: 2109 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2110 return (status >> 16) & 0xF; 2111 break; 2112 default: 2113 break; 2114 } 2115 2116 2117 return 0; 2118 } 2119 2120 2121 /** 2122 * Returns the TCO sample rate class for the given card. 2123 **/ 2124 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2125 { 2126 int status; 2127 2128 if (hdspm->tco) { 2129 switch (hdspm->io_type) { 2130 case RayDAT: 2131 case AIO: 2132 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2133 return (status >> 20) & 0xF; 2134 break; 2135 default: 2136 break; 2137 } 2138 } 2139 2140 return 0; 2141 } 2142 2143 2144 /** 2145 * Returns the SYNC_IN sample rate class for the given card. 2146 **/ 2147 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2148 { 2149 int status; 2150 2151 if (hdspm->tco) { 2152 switch (hdspm->io_type) { 2153 case RayDAT: 2154 case AIO: 2155 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2156 return (status >> 12) & 0xF; 2157 break; 2158 default: 2159 break; 2160 } 2161 } 2162 2163 return 0; 2164 } 2165 2166 2167 /** 2168 * Returns the sample rate class for input source <idx> for 2169 * 'new style' cards like the AIO and RayDAT. 2170 **/ 2171 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2172 { 2173 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2174 2175 return (status >> (idx*4)) & 0xF; 2176 } 2177 2178 #define ENUMERATED_CTL_INFO(info, texts) \ 2179 { \ 2180 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; \ 2181 uinfo->count = 1; \ 2182 uinfo->value.enumerated.items = ARRAY_SIZE(texts); \ 2183 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) \ 2184 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; \ 2185 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); \ 2186 } 2187 2188 2189 2190 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2191 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2192 .name = xname, \ 2193 .private_value = xindex, \ 2194 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2195 .info = snd_hdspm_info_autosync_sample_rate, \ 2196 .get = snd_hdspm_get_autosync_sample_rate \ 2197 } 2198 2199 2200 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2201 struct snd_ctl_elem_info *uinfo) 2202 { 2203 ENUMERATED_CTL_INFO(uinfo, texts_freq); 2204 return 0; 2205 } 2206 2207 2208 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2209 struct snd_ctl_elem_value * 2210 ucontrol) 2211 { 2212 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2213 2214 switch (hdspm->io_type) { 2215 case RayDAT: 2216 switch (kcontrol->private_value) { 2217 case 0: 2218 ucontrol->value.enumerated.item[0] = 2219 hdspm_get_wc_sample_rate(hdspm); 2220 break; 2221 case 7: 2222 ucontrol->value.enumerated.item[0] = 2223 hdspm_get_tco_sample_rate(hdspm); 2224 break; 2225 case 8: 2226 ucontrol->value.enumerated.item[0] = 2227 hdspm_get_sync_in_sample_rate(hdspm); 2228 break; 2229 default: 2230 ucontrol->value.enumerated.item[0] = 2231 hdspm_get_s1_sample_rate(hdspm, 2232 kcontrol->private_value-1); 2233 } 2234 break; 2235 2236 case AIO: 2237 switch (kcontrol->private_value) { 2238 case 0: /* WC */ 2239 ucontrol->value.enumerated.item[0] = 2240 hdspm_get_wc_sample_rate(hdspm); 2241 break; 2242 case 4: /* TCO */ 2243 ucontrol->value.enumerated.item[0] = 2244 hdspm_get_tco_sample_rate(hdspm); 2245 break; 2246 case 5: /* SYNC_IN */ 2247 ucontrol->value.enumerated.item[0] = 2248 hdspm_get_sync_in_sample_rate(hdspm); 2249 break; 2250 default: 2251 ucontrol->value.enumerated.item[0] = 2252 hdspm_get_s1_sample_rate(hdspm, 2253 ucontrol->id.index-1); 2254 } 2255 break; 2256 2257 case AES32: 2258 2259 switch (kcontrol->private_value) { 2260 case 0: /* WC */ 2261 ucontrol->value.enumerated.item[0] = 2262 hdspm_get_wc_sample_rate(hdspm); 2263 break; 2264 case 9: /* TCO */ 2265 ucontrol->value.enumerated.item[0] = 2266 hdspm_get_tco_sample_rate(hdspm); 2267 break; 2268 case 10: /* SYNC_IN */ 2269 ucontrol->value.enumerated.item[0] = 2270 hdspm_get_sync_in_sample_rate(hdspm); 2271 break; 2272 default: /* AES1 to AES8 */ 2273 ucontrol->value.enumerated.item[0] = 2274 hdspm_get_s1_sample_rate(hdspm, 2275 kcontrol->private_value-1); 2276 break; 2277 } 2278 break; 2279 2280 case MADI: 2281 case MADIface: 2282 { 2283 int rate = hdspm_external_sample_rate(hdspm); 2284 int i, selected_rate = 0; 2285 for (i = 1; i < 10; i++) 2286 if (HDSPM_bit2freq(i) == rate) { 2287 selected_rate = i; 2288 break; 2289 } 2290 ucontrol->value.enumerated.item[0] = selected_rate; 2291 } 2292 break; 2293 2294 default: 2295 break; 2296 } 2297 2298 return 0; 2299 } 2300 2301 2302 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2303 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2304 .name = xname, \ 2305 .index = xindex, \ 2306 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2307 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2308 .info = snd_hdspm_info_system_clock_mode, \ 2309 .get = snd_hdspm_get_system_clock_mode, \ 2310 .put = snd_hdspm_put_system_clock_mode, \ 2311 } 2312 2313 2314 /** 2315 * Returns the system clock mode for the given card. 2316 * @returns 0 - master, 1 - slave 2317 **/ 2318 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2319 { 2320 switch (hdspm->io_type) { 2321 case AIO: 2322 case RayDAT: 2323 if (hdspm->settings_register & HDSPM_c0Master) 2324 return 0; 2325 break; 2326 2327 default: 2328 if (hdspm->control_register & HDSPM_ClockModeMaster) 2329 return 0; 2330 } 2331 2332 return 1; 2333 } 2334 2335 2336 /** 2337 * Sets the system clock mode. 2338 * @param mode 0 - master, 1 - slave 2339 **/ 2340 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2341 { 2342 switch (hdspm->io_type) { 2343 case AIO: 2344 case RayDAT: 2345 if (0 == mode) 2346 hdspm->settings_register |= HDSPM_c0Master; 2347 else 2348 hdspm->settings_register &= ~HDSPM_c0Master; 2349 2350 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2351 break; 2352 2353 default: 2354 if (0 == mode) 2355 hdspm->control_register |= HDSPM_ClockModeMaster; 2356 else 2357 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2358 2359 hdspm_write(hdspm, HDSPM_controlRegister, 2360 hdspm->control_register); 2361 } 2362 } 2363 2364 2365 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2366 struct snd_ctl_elem_info *uinfo) 2367 { 2368 static char *texts[] = { "Master", "AutoSync" }; 2369 ENUMERATED_CTL_INFO(uinfo, texts); 2370 return 0; 2371 } 2372 2373 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2374 struct snd_ctl_elem_value *ucontrol) 2375 { 2376 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2377 2378 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2379 return 0; 2380 } 2381 2382 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2383 struct snd_ctl_elem_value *ucontrol) 2384 { 2385 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2386 int val; 2387 2388 if (!snd_hdspm_use_is_exclusive(hdspm)) 2389 return -EBUSY; 2390 2391 val = ucontrol->value.enumerated.item[0]; 2392 if (val < 0) 2393 val = 0; 2394 else if (val > 1) 2395 val = 1; 2396 2397 hdspm_set_system_clock_mode(hdspm, val); 2398 2399 return 0; 2400 } 2401 2402 2403 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2404 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2405 .name = xname, \ 2406 .index = xindex, \ 2407 .info = snd_hdspm_info_clock_source, \ 2408 .get = snd_hdspm_get_clock_source, \ 2409 .put = snd_hdspm_put_clock_source \ 2410 } 2411 2412 2413 static int hdspm_clock_source(struct hdspm * hdspm) 2414 { 2415 switch (hdspm->system_sample_rate) { 2416 case 32000: return 0; 2417 case 44100: return 1; 2418 case 48000: return 2; 2419 case 64000: return 3; 2420 case 88200: return 4; 2421 case 96000: return 5; 2422 case 128000: return 6; 2423 case 176400: return 7; 2424 case 192000: return 8; 2425 } 2426 2427 return -1; 2428 } 2429 2430 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2431 { 2432 int rate; 2433 switch (mode) { 2434 case 0: 2435 rate = 32000; break; 2436 case 1: 2437 rate = 44100; break; 2438 case 2: 2439 rate = 48000; break; 2440 case 3: 2441 rate = 64000; break; 2442 case 4: 2443 rate = 88200; break; 2444 case 5: 2445 rate = 96000; break; 2446 case 6: 2447 rate = 128000; break; 2448 case 7: 2449 rate = 176400; break; 2450 case 8: 2451 rate = 192000; break; 2452 default: 2453 rate = 48000; 2454 } 2455 hdspm_set_rate(hdspm, rate, 1); 2456 return 0; 2457 } 2458 2459 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2460 struct snd_ctl_elem_info *uinfo) 2461 { 2462 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2463 uinfo->count = 1; 2464 uinfo->value.enumerated.items = 9; 2465 2466 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2467 uinfo->value.enumerated.item = 2468 uinfo->value.enumerated.items - 1; 2469 2470 strcpy(uinfo->value.enumerated.name, 2471 texts_freq[uinfo->value.enumerated.item+1]); 2472 2473 return 0; 2474 } 2475 2476 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2477 struct snd_ctl_elem_value *ucontrol) 2478 { 2479 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2480 2481 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2482 return 0; 2483 } 2484 2485 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2486 struct snd_ctl_elem_value *ucontrol) 2487 { 2488 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2489 int change; 2490 int val; 2491 2492 if (!snd_hdspm_use_is_exclusive(hdspm)) 2493 return -EBUSY; 2494 val = ucontrol->value.enumerated.item[0]; 2495 if (val < 0) 2496 val = 0; 2497 if (val > 9) 2498 val = 9; 2499 spin_lock_irq(&hdspm->lock); 2500 if (val != hdspm_clock_source(hdspm)) 2501 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2502 else 2503 change = 0; 2504 spin_unlock_irq(&hdspm->lock); 2505 return change; 2506 } 2507 2508 2509 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2510 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2511 .name = xname, \ 2512 .index = xindex, \ 2513 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2514 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2515 .info = snd_hdspm_info_pref_sync_ref, \ 2516 .get = snd_hdspm_get_pref_sync_ref, \ 2517 .put = snd_hdspm_put_pref_sync_ref \ 2518 } 2519 2520 2521 /** 2522 * Returns the current preferred sync reference setting. 2523 * The semantics of the return value are depending on the 2524 * card, please see the comments for clarification. 2525 **/ 2526 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2527 { 2528 switch (hdspm->io_type) { 2529 case AES32: 2530 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2531 case 0: return 0; /* WC */ 2532 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2533 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2534 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2535 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2536 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2537 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2538 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2539 return 7; /* AES 7 */ 2540 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2541 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2542 } 2543 break; 2544 2545 case MADI: 2546 case MADIface: 2547 if (hdspm->tco) { 2548 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2549 case 0: return 0; /* WC */ 2550 case HDSPM_SyncRef0: return 1; /* MADI */ 2551 case HDSPM_SyncRef1: return 2; /* TCO */ 2552 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2553 return 3; /* SYNC_IN */ 2554 } 2555 } else { 2556 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2557 case 0: return 0; /* WC */ 2558 case HDSPM_SyncRef0: return 1; /* MADI */ 2559 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2560 return 2; /* SYNC_IN */ 2561 } 2562 } 2563 break; 2564 2565 case RayDAT: 2566 if (hdspm->tco) { 2567 switch ((hdspm->settings_register & 2568 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2569 case 0: return 0; /* WC */ 2570 case 3: return 1; /* ADAT 1 */ 2571 case 4: return 2; /* ADAT 2 */ 2572 case 5: return 3; /* ADAT 3 */ 2573 case 6: return 4; /* ADAT 4 */ 2574 case 1: return 5; /* AES */ 2575 case 2: return 6; /* SPDIF */ 2576 case 9: return 7; /* TCO */ 2577 case 10: return 8; /* SYNC_IN */ 2578 } 2579 } else { 2580 switch ((hdspm->settings_register & 2581 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2582 case 0: return 0; /* WC */ 2583 case 3: return 1; /* ADAT 1 */ 2584 case 4: return 2; /* ADAT 2 */ 2585 case 5: return 3; /* ADAT 3 */ 2586 case 6: return 4; /* ADAT 4 */ 2587 case 1: return 5; /* AES */ 2588 case 2: return 6; /* SPDIF */ 2589 case 10: return 7; /* SYNC_IN */ 2590 } 2591 } 2592 2593 break; 2594 2595 case AIO: 2596 if (hdspm->tco) { 2597 switch ((hdspm->settings_register & 2598 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2599 case 0: return 0; /* WC */ 2600 case 3: return 1; /* ADAT */ 2601 case 1: return 2; /* AES */ 2602 case 2: return 3; /* SPDIF */ 2603 case 9: return 4; /* TCO */ 2604 case 10: return 5; /* SYNC_IN */ 2605 } 2606 } else { 2607 switch ((hdspm->settings_register & 2608 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2609 case 0: return 0; /* WC */ 2610 case 3: return 1; /* ADAT */ 2611 case 1: return 2; /* AES */ 2612 case 2: return 3; /* SPDIF */ 2613 case 10: return 4; /* SYNC_IN */ 2614 } 2615 } 2616 2617 break; 2618 } 2619 2620 return -1; 2621 } 2622 2623 2624 /** 2625 * Set the preferred sync reference to <pref>. The semantics 2626 * of <pref> are depending on the card type, see the comments 2627 * for clarification. 2628 **/ 2629 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2630 { 2631 int p = 0; 2632 2633 switch (hdspm->io_type) { 2634 case AES32: 2635 hdspm->control_register &= ~HDSPM_SyncRefMask; 2636 switch (pref) { 2637 case 0: /* WC */ 2638 break; 2639 case 1: /* AES 1 */ 2640 hdspm->control_register |= HDSPM_SyncRef0; 2641 break; 2642 case 2: /* AES 2 */ 2643 hdspm->control_register |= HDSPM_SyncRef1; 2644 break; 2645 case 3: /* AES 3 */ 2646 hdspm->control_register |= 2647 HDSPM_SyncRef1+HDSPM_SyncRef0; 2648 break; 2649 case 4: /* AES 4 */ 2650 hdspm->control_register |= HDSPM_SyncRef2; 2651 break; 2652 case 5: /* AES 5 */ 2653 hdspm->control_register |= 2654 HDSPM_SyncRef2+HDSPM_SyncRef0; 2655 break; 2656 case 6: /* AES 6 */ 2657 hdspm->control_register |= 2658 HDSPM_SyncRef2+HDSPM_SyncRef1; 2659 break; 2660 case 7: /* AES 7 */ 2661 hdspm->control_register |= 2662 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2663 break; 2664 case 8: /* AES 8 */ 2665 hdspm->control_register |= HDSPM_SyncRef3; 2666 break; 2667 case 9: /* TCO */ 2668 hdspm->control_register |= 2669 HDSPM_SyncRef3+HDSPM_SyncRef0; 2670 break; 2671 default: 2672 return -1; 2673 } 2674 2675 break; 2676 2677 case MADI: 2678 case MADIface: 2679 hdspm->control_register &= ~HDSPM_SyncRefMask; 2680 if (hdspm->tco) { 2681 switch (pref) { 2682 case 0: /* WC */ 2683 break; 2684 case 1: /* MADI */ 2685 hdspm->control_register |= HDSPM_SyncRef0; 2686 break; 2687 case 2: /* TCO */ 2688 hdspm->control_register |= HDSPM_SyncRef1; 2689 break; 2690 case 3: /* SYNC_IN */ 2691 hdspm->control_register |= 2692 HDSPM_SyncRef0+HDSPM_SyncRef1; 2693 break; 2694 default: 2695 return -1; 2696 } 2697 } else { 2698 switch (pref) { 2699 case 0: /* WC */ 2700 break; 2701 case 1: /* MADI */ 2702 hdspm->control_register |= HDSPM_SyncRef0; 2703 break; 2704 case 2: /* SYNC_IN */ 2705 hdspm->control_register |= 2706 HDSPM_SyncRef0+HDSPM_SyncRef1; 2707 break; 2708 default: 2709 return -1; 2710 } 2711 } 2712 2713 break; 2714 2715 case RayDAT: 2716 if (hdspm->tco) { 2717 switch (pref) { 2718 case 0: p = 0; break; /* WC */ 2719 case 1: p = 3; break; /* ADAT 1 */ 2720 case 2: p = 4; break; /* ADAT 2 */ 2721 case 3: p = 5; break; /* ADAT 3 */ 2722 case 4: p = 6; break; /* ADAT 4 */ 2723 case 5: p = 1; break; /* AES */ 2724 case 6: p = 2; break; /* SPDIF */ 2725 case 7: p = 9; break; /* TCO */ 2726 case 8: p = 10; break; /* SYNC_IN */ 2727 default: return -1; 2728 } 2729 } else { 2730 switch (pref) { 2731 case 0: p = 0; break; /* WC */ 2732 case 1: p = 3; break; /* ADAT 1 */ 2733 case 2: p = 4; break; /* ADAT 2 */ 2734 case 3: p = 5; break; /* ADAT 3 */ 2735 case 4: p = 6; break; /* ADAT 4 */ 2736 case 5: p = 1; break; /* AES */ 2737 case 6: p = 2; break; /* SPDIF */ 2738 case 7: p = 10; break; /* SYNC_IN */ 2739 default: return -1; 2740 } 2741 } 2742 break; 2743 2744 case AIO: 2745 if (hdspm->tco) { 2746 switch (pref) { 2747 case 0: p = 0; break; /* WC */ 2748 case 1: p = 3; break; /* ADAT */ 2749 case 2: p = 1; break; /* AES */ 2750 case 3: p = 2; break; /* SPDIF */ 2751 case 4: p = 9; break; /* TCO */ 2752 case 5: p = 10; break; /* SYNC_IN */ 2753 default: return -1; 2754 } 2755 } else { 2756 switch (pref) { 2757 case 0: p = 0; break; /* WC */ 2758 case 1: p = 3; break; /* ADAT */ 2759 case 2: p = 1; break; /* AES */ 2760 case 3: p = 2; break; /* SPDIF */ 2761 case 4: p = 10; break; /* SYNC_IN */ 2762 default: return -1; 2763 } 2764 } 2765 break; 2766 } 2767 2768 switch (hdspm->io_type) { 2769 case RayDAT: 2770 case AIO: 2771 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2772 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2773 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2774 break; 2775 2776 case MADI: 2777 case MADIface: 2778 case AES32: 2779 hdspm_write(hdspm, HDSPM_controlRegister, 2780 hdspm->control_register); 2781 } 2782 2783 return 0; 2784 } 2785 2786 2787 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2788 struct snd_ctl_elem_info *uinfo) 2789 { 2790 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2791 2792 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2793 uinfo->count = 1; 2794 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2795 2796 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2797 uinfo->value.enumerated.item = 2798 uinfo->value.enumerated.items - 1; 2799 2800 strcpy(uinfo->value.enumerated.name, 2801 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2802 2803 return 0; 2804 } 2805 2806 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2807 struct snd_ctl_elem_value *ucontrol) 2808 { 2809 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2810 int psf = hdspm_pref_sync_ref(hdspm); 2811 2812 if (psf >= 0) { 2813 ucontrol->value.enumerated.item[0] = psf; 2814 return 0; 2815 } 2816 2817 return -1; 2818 } 2819 2820 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2821 struct snd_ctl_elem_value *ucontrol) 2822 { 2823 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2824 int val, change = 0; 2825 2826 if (!snd_hdspm_use_is_exclusive(hdspm)) 2827 return -EBUSY; 2828 2829 val = ucontrol->value.enumerated.item[0]; 2830 2831 if (val < 0) 2832 val = 0; 2833 else if (val >= hdspm->texts_autosync_items) 2834 val = hdspm->texts_autosync_items-1; 2835 2836 spin_lock_irq(&hdspm->lock); 2837 if (val != hdspm_pref_sync_ref(hdspm)) 2838 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2839 2840 spin_unlock_irq(&hdspm->lock); 2841 return change; 2842 } 2843 2844 2845 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2846 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2847 .name = xname, \ 2848 .index = xindex, \ 2849 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2850 .info = snd_hdspm_info_autosync_ref, \ 2851 .get = snd_hdspm_get_autosync_ref, \ 2852 } 2853 2854 static int hdspm_autosync_ref(struct hdspm *hdspm) 2855 { 2856 if (AES32 == hdspm->io_type) { 2857 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2858 unsigned int syncref = 2859 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2860 if (syncref == 0) 2861 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2862 if (syncref <= 8) 2863 return syncref; 2864 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2865 } else if (MADI == hdspm->io_type) { 2866 /* This looks at the autosync selected sync reference */ 2867 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2868 2869 switch (status2 & HDSPM_SelSyncRefMask) { 2870 case HDSPM_SelSyncRef_WORD: 2871 return HDSPM_AUTOSYNC_FROM_WORD; 2872 case HDSPM_SelSyncRef_MADI: 2873 return HDSPM_AUTOSYNC_FROM_MADI; 2874 case HDSPM_SelSyncRef_TCO: 2875 return HDSPM_AUTOSYNC_FROM_TCO; 2876 case HDSPM_SelSyncRef_SyncIn: 2877 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2878 case HDSPM_SelSyncRef_NVALID: 2879 return HDSPM_AUTOSYNC_FROM_NONE; 2880 default: 2881 return 0; 2882 } 2883 2884 } 2885 return 0; 2886 } 2887 2888 2889 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2890 struct snd_ctl_elem_info *uinfo) 2891 { 2892 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2893 2894 if (AES32 == hdspm->io_type) { 2895 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2896 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2897 2898 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2899 uinfo->count = 1; 2900 uinfo->value.enumerated.items = 10; 2901 if (uinfo->value.enumerated.item >= 2902 uinfo->value.enumerated.items) 2903 uinfo->value.enumerated.item = 2904 uinfo->value.enumerated.items - 1; 2905 strcpy(uinfo->value.enumerated.name, 2906 texts[uinfo->value.enumerated.item]); 2907 } else if (MADI == hdspm->io_type) { 2908 static char *texts[] = {"Word Clock", "MADI", "TCO", 2909 "Sync In", "None" }; 2910 2911 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2912 uinfo->count = 1; 2913 uinfo->value.enumerated.items = 5; 2914 if (uinfo->value.enumerated.item >= 2915 uinfo->value.enumerated.items) 2916 uinfo->value.enumerated.item = 2917 uinfo->value.enumerated.items - 1; 2918 strcpy(uinfo->value.enumerated.name, 2919 texts[uinfo->value.enumerated.item]); 2920 } 2921 return 0; 2922 } 2923 2924 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2925 struct snd_ctl_elem_value *ucontrol) 2926 { 2927 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2928 2929 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2930 return 0; 2931 } 2932 2933 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 2934 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2935 .name = xname, \ 2936 .private_value = xindex, \ 2937 .info = snd_hdspm_info_toggle_setting, \ 2938 .get = snd_hdspm_get_toggle_setting, \ 2939 .put = snd_hdspm_put_toggle_setting \ 2940 } 2941 2942 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 2943 { 2944 return (hdspm->control_register & regmask) ? 1 : 0; 2945 } 2946 2947 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 2948 { 2949 if (out) 2950 hdspm->control_register |= regmask; 2951 else 2952 hdspm->control_register &= ~regmask; 2953 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2954 2955 return 0; 2956 } 2957 2958 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 2959 2960 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 2961 struct snd_ctl_elem_value *ucontrol) 2962 { 2963 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2964 u32 regmask = kcontrol->private_value; 2965 2966 spin_lock_irq(&hdspm->lock); 2967 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 2968 spin_unlock_irq(&hdspm->lock); 2969 return 0; 2970 } 2971 2972 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 2973 struct snd_ctl_elem_value *ucontrol) 2974 { 2975 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2976 u32 regmask = kcontrol->private_value; 2977 int change; 2978 unsigned int val; 2979 2980 if (!snd_hdspm_use_is_exclusive(hdspm)) 2981 return -EBUSY; 2982 val = ucontrol->value.integer.value[0] & 1; 2983 spin_lock_irq(&hdspm->lock); 2984 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 2985 hdspm_set_toggle_setting(hdspm, regmask, val); 2986 spin_unlock_irq(&hdspm->lock); 2987 return change; 2988 } 2989 2990 #define HDSPM_INPUT_SELECT(xname, xindex) \ 2991 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2992 .name = xname, \ 2993 .index = xindex, \ 2994 .info = snd_hdspm_info_input_select, \ 2995 .get = snd_hdspm_get_input_select, \ 2996 .put = snd_hdspm_put_input_select \ 2997 } 2998 2999 static int hdspm_input_select(struct hdspm * hdspm) 3000 { 3001 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 3002 } 3003 3004 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 3005 { 3006 if (out) 3007 hdspm->control_register |= HDSPM_InputSelect0; 3008 else 3009 hdspm->control_register &= ~HDSPM_InputSelect0; 3010 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3011 3012 return 0; 3013 } 3014 3015 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 3016 struct snd_ctl_elem_info *uinfo) 3017 { 3018 static char *texts[] = { "optical", "coaxial" }; 3019 ENUMERATED_CTL_INFO(uinfo, texts); 3020 return 0; 3021 } 3022 3023 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 3024 struct snd_ctl_elem_value *ucontrol) 3025 { 3026 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3027 3028 spin_lock_irq(&hdspm->lock); 3029 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 3030 spin_unlock_irq(&hdspm->lock); 3031 return 0; 3032 } 3033 3034 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3035 struct snd_ctl_elem_value *ucontrol) 3036 { 3037 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3038 int change; 3039 unsigned int val; 3040 3041 if (!snd_hdspm_use_is_exclusive(hdspm)) 3042 return -EBUSY; 3043 val = ucontrol->value.integer.value[0] & 1; 3044 spin_lock_irq(&hdspm->lock); 3045 change = (int) val != hdspm_input_select(hdspm); 3046 hdspm_set_input_select(hdspm, val); 3047 spin_unlock_irq(&hdspm->lock); 3048 return change; 3049 } 3050 3051 3052 #define HDSPM_DS_WIRE(xname, xindex) \ 3053 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3054 .name = xname, \ 3055 .index = xindex, \ 3056 .info = snd_hdspm_info_ds_wire, \ 3057 .get = snd_hdspm_get_ds_wire, \ 3058 .put = snd_hdspm_put_ds_wire \ 3059 } 3060 3061 static int hdspm_ds_wire(struct hdspm * hdspm) 3062 { 3063 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3064 } 3065 3066 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3067 { 3068 if (ds) 3069 hdspm->control_register |= HDSPM_DS_DoubleWire; 3070 else 3071 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3072 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3073 3074 return 0; 3075 } 3076 3077 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3078 struct snd_ctl_elem_info *uinfo) 3079 { 3080 static char *texts[] = { "Single", "Double" }; 3081 ENUMERATED_CTL_INFO(uinfo, texts); 3082 return 0; 3083 } 3084 3085 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3086 struct snd_ctl_elem_value *ucontrol) 3087 { 3088 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3089 3090 spin_lock_irq(&hdspm->lock); 3091 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3092 spin_unlock_irq(&hdspm->lock); 3093 return 0; 3094 } 3095 3096 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3097 struct snd_ctl_elem_value *ucontrol) 3098 { 3099 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3100 int change; 3101 unsigned int val; 3102 3103 if (!snd_hdspm_use_is_exclusive(hdspm)) 3104 return -EBUSY; 3105 val = ucontrol->value.integer.value[0] & 1; 3106 spin_lock_irq(&hdspm->lock); 3107 change = (int) val != hdspm_ds_wire(hdspm); 3108 hdspm_set_ds_wire(hdspm, val); 3109 spin_unlock_irq(&hdspm->lock); 3110 return change; 3111 } 3112 3113 3114 #define HDSPM_QS_WIRE(xname, xindex) \ 3115 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3116 .name = xname, \ 3117 .index = xindex, \ 3118 .info = snd_hdspm_info_qs_wire, \ 3119 .get = snd_hdspm_get_qs_wire, \ 3120 .put = snd_hdspm_put_qs_wire \ 3121 } 3122 3123 static int hdspm_qs_wire(struct hdspm * hdspm) 3124 { 3125 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3126 return 1; 3127 if (hdspm->control_register & HDSPM_QS_QuadWire) 3128 return 2; 3129 return 0; 3130 } 3131 3132 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3133 { 3134 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3135 switch (mode) { 3136 case 0: 3137 break; 3138 case 1: 3139 hdspm->control_register |= HDSPM_QS_DoubleWire; 3140 break; 3141 case 2: 3142 hdspm->control_register |= HDSPM_QS_QuadWire; 3143 break; 3144 } 3145 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3146 3147 return 0; 3148 } 3149 3150 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3151 struct snd_ctl_elem_info *uinfo) 3152 { 3153 static char *texts[] = { "Single", "Double", "Quad" }; 3154 ENUMERATED_CTL_INFO(uinfo, texts); 3155 return 0; 3156 } 3157 3158 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3159 struct snd_ctl_elem_value *ucontrol) 3160 { 3161 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3162 3163 spin_lock_irq(&hdspm->lock); 3164 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3165 spin_unlock_irq(&hdspm->lock); 3166 return 0; 3167 } 3168 3169 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3170 struct snd_ctl_elem_value *ucontrol) 3171 { 3172 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3173 int change; 3174 int val; 3175 3176 if (!snd_hdspm_use_is_exclusive(hdspm)) 3177 return -EBUSY; 3178 val = ucontrol->value.integer.value[0]; 3179 if (val < 0) 3180 val = 0; 3181 if (val > 2) 3182 val = 2; 3183 spin_lock_irq(&hdspm->lock); 3184 change = val != hdspm_qs_wire(hdspm); 3185 hdspm_set_qs_wire(hdspm, val); 3186 spin_unlock_irq(&hdspm->lock); 3187 return change; 3188 } 3189 3190 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3191 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3192 .name = xname, \ 3193 .index = xindex, \ 3194 .info = snd_hdspm_info_madi_speedmode, \ 3195 .get = snd_hdspm_get_madi_speedmode, \ 3196 .put = snd_hdspm_put_madi_speedmode \ 3197 } 3198 3199 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3200 { 3201 if (hdspm->control_register & HDSPM_QuadSpeed) 3202 return 2; 3203 if (hdspm->control_register & HDSPM_DoubleSpeed) 3204 return 1; 3205 return 0; 3206 } 3207 3208 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3209 { 3210 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3211 switch (mode) { 3212 case 0: 3213 break; 3214 case 1: 3215 hdspm->control_register |= HDSPM_DoubleSpeed; 3216 break; 3217 case 2: 3218 hdspm->control_register |= HDSPM_QuadSpeed; 3219 break; 3220 } 3221 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3222 3223 return 0; 3224 } 3225 3226 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3227 struct snd_ctl_elem_info *uinfo) 3228 { 3229 static char *texts[] = { "Single", "Double", "Quad" }; 3230 ENUMERATED_CTL_INFO(uinfo, texts); 3231 return 0; 3232 } 3233 3234 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3235 struct snd_ctl_elem_value *ucontrol) 3236 { 3237 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3238 3239 spin_lock_irq(&hdspm->lock); 3240 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3241 spin_unlock_irq(&hdspm->lock); 3242 return 0; 3243 } 3244 3245 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3246 struct snd_ctl_elem_value *ucontrol) 3247 { 3248 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3249 int change; 3250 int val; 3251 3252 if (!snd_hdspm_use_is_exclusive(hdspm)) 3253 return -EBUSY; 3254 val = ucontrol->value.integer.value[0]; 3255 if (val < 0) 3256 val = 0; 3257 if (val > 2) 3258 val = 2; 3259 spin_lock_irq(&hdspm->lock); 3260 change = val != hdspm_madi_speedmode(hdspm); 3261 hdspm_set_madi_speedmode(hdspm, val); 3262 spin_unlock_irq(&hdspm->lock); 3263 return change; 3264 } 3265 3266 #define HDSPM_MIXER(xname, xindex) \ 3267 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3268 .name = xname, \ 3269 .index = xindex, \ 3270 .device = 0, \ 3271 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3272 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3273 .info = snd_hdspm_info_mixer, \ 3274 .get = snd_hdspm_get_mixer, \ 3275 .put = snd_hdspm_put_mixer \ 3276 } 3277 3278 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3279 struct snd_ctl_elem_info *uinfo) 3280 { 3281 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3282 uinfo->count = 3; 3283 uinfo->value.integer.min = 0; 3284 uinfo->value.integer.max = 65535; 3285 uinfo->value.integer.step = 1; 3286 return 0; 3287 } 3288 3289 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3290 struct snd_ctl_elem_value *ucontrol) 3291 { 3292 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3293 int source; 3294 int destination; 3295 3296 source = ucontrol->value.integer.value[0]; 3297 if (source < 0) 3298 source = 0; 3299 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3300 source = 2 * HDSPM_MAX_CHANNELS - 1; 3301 3302 destination = ucontrol->value.integer.value[1]; 3303 if (destination < 0) 3304 destination = 0; 3305 else if (destination >= HDSPM_MAX_CHANNELS) 3306 destination = HDSPM_MAX_CHANNELS - 1; 3307 3308 spin_lock_irq(&hdspm->lock); 3309 if (source >= HDSPM_MAX_CHANNELS) 3310 ucontrol->value.integer.value[2] = 3311 hdspm_read_pb_gain(hdspm, destination, 3312 source - HDSPM_MAX_CHANNELS); 3313 else 3314 ucontrol->value.integer.value[2] = 3315 hdspm_read_in_gain(hdspm, destination, source); 3316 3317 spin_unlock_irq(&hdspm->lock); 3318 3319 return 0; 3320 } 3321 3322 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3323 struct snd_ctl_elem_value *ucontrol) 3324 { 3325 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3326 int change; 3327 int source; 3328 int destination; 3329 int gain; 3330 3331 if (!snd_hdspm_use_is_exclusive(hdspm)) 3332 return -EBUSY; 3333 3334 source = ucontrol->value.integer.value[0]; 3335 destination = ucontrol->value.integer.value[1]; 3336 3337 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3338 return -1; 3339 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3340 return -1; 3341 3342 gain = ucontrol->value.integer.value[2]; 3343 3344 spin_lock_irq(&hdspm->lock); 3345 3346 if (source >= HDSPM_MAX_CHANNELS) 3347 change = gain != hdspm_read_pb_gain(hdspm, destination, 3348 source - 3349 HDSPM_MAX_CHANNELS); 3350 else 3351 change = gain != hdspm_read_in_gain(hdspm, destination, 3352 source); 3353 3354 if (change) { 3355 if (source >= HDSPM_MAX_CHANNELS) 3356 hdspm_write_pb_gain(hdspm, destination, 3357 source - HDSPM_MAX_CHANNELS, 3358 gain); 3359 else 3360 hdspm_write_in_gain(hdspm, destination, source, 3361 gain); 3362 } 3363 spin_unlock_irq(&hdspm->lock); 3364 3365 return change; 3366 } 3367 3368 /* The simple mixer control(s) provide gain control for the 3369 basic 1:1 mappings of playback streams to output 3370 streams. 3371 */ 3372 3373 #define HDSPM_PLAYBACK_MIXER \ 3374 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3375 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3376 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3377 .info = snd_hdspm_info_playback_mixer, \ 3378 .get = snd_hdspm_get_playback_mixer, \ 3379 .put = snd_hdspm_put_playback_mixer \ 3380 } 3381 3382 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3383 struct snd_ctl_elem_info *uinfo) 3384 { 3385 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3386 uinfo->count = 1; 3387 uinfo->value.integer.min = 0; 3388 uinfo->value.integer.max = 64; 3389 uinfo->value.integer.step = 1; 3390 return 0; 3391 } 3392 3393 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3394 struct snd_ctl_elem_value *ucontrol) 3395 { 3396 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3397 int channel; 3398 3399 channel = ucontrol->id.index - 1; 3400 3401 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3402 return -EINVAL; 3403 3404 spin_lock_irq(&hdspm->lock); 3405 ucontrol->value.integer.value[0] = 3406 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3407 spin_unlock_irq(&hdspm->lock); 3408 3409 return 0; 3410 } 3411 3412 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3413 struct snd_ctl_elem_value *ucontrol) 3414 { 3415 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3416 int change; 3417 int channel; 3418 int gain; 3419 3420 if (!snd_hdspm_use_is_exclusive(hdspm)) 3421 return -EBUSY; 3422 3423 channel = ucontrol->id.index - 1; 3424 3425 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3426 return -EINVAL; 3427 3428 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3429 3430 spin_lock_irq(&hdspm->lock); 3431 change = 3432 gain != hdspm_read_pb_gain(hdspm, channel, 3433 channel); 3434 if (change) 3435 hdspm_write_pb_gain(hdspm, channel, channel, 3436 gain); 3437 spin_unlock_irq(&hdspm->lock); 3438 return change; 3439 } 3440 3441 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3442 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3443 .name = xname, \ 3444 .private_value = xindex, \ 3445 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3446 .info = snd_hdspm_info_sync_check, \ 3447 .get = snd_hdspm_get_sync_check \ 3448 } 3449 3450 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \ 3451 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3452 .name = xname, \ 3453 .private_value = xindex, \ 3454 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3455 .info = snd_hdspm_tco_info_lock_check, \ 3456 .get = snd_hdspm_get_sync_check \ 3457 } 3458 3459 3460 3461 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3462 struct snd_ctl_elem_info *uinfo) 3463 { 3464 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3465 ENUMERATED_CTL_INFO(uinfo, texts); 3466 return 0; 3467 } 3468 3469 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol, 3470 struct snd_ctl_elem_info *uinfo) 3471 { 3472 static char *texts[] = { "No Lock", "Lock" }; 3473 ENUMERATED_CTL_INFO(uinfo, texts); 3474 return 0; 3475 } 3476 3477 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3478 { 3479 int status, status2; 3480 3481 switch (hdspm->io_type) { 3482 case AES32: 3483 status = hdspm_read(hdspm, HDSPM_statusRegister); 3484 if (status & HDSPM_AES32_wcLock) { 3485 if (status & HDSPM_AES32_wcSync) 3486 return 2; 3487 else 3488 return 1; 3489 } 3490 return 0; 3491 break; 3492 3493 case MADI: 3494 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3495 if (status2 & HDSPM_wcLock) { 3496 if (status2 & HDSPM_wcSync) 3497 return 2; 3498 else 3499 return 1; 3500 } 3501 return 0; 3502 break; 3503 3504 case RayDAT: 3505 case AIO: 3506 status = hdspm_read(hdspm, HDSPM_statusRegister); 3507 3508 if (status & 0x2000000) 3509 return 2; 3510 else if (status & 0x1000000) 3511 return 1; 3512 return 0; 3513 3514 break; 3515 3516 case MADIface: 3517 break; 3518 } 3519 3520 3521 return 3; 3522 } 3523 3524 3525 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3526 { 3527 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3528 if (status & HDSPM_madiLock) { 3529 if (status & HDSPM_madiSync) 3530 return 2; 3531 else 3532 return 1; 3533 } 3534 return 0; 3535 } 3536 3537 3538 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3539 { 3540 int status, lock, sync; 3541 3542 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3543 3544 lock = (status & (0x1<<idx)) ? 1 : 0; 3545 sync = (status & (0x100<<idx)) ? 1 : 0; 3546 3547 if (lock && sync) 3548 return 2; 3549 else if (lock) 3550 return 1; 3551 return 0; 3552 } 3553 3554 3555 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3556 { 3557 int status, lock = 0, sync = 0; 3558 3559 switch (hdspm->io_type) { 3560 case RayDAT: 3561 case AIO: 3562 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3563 lock = (status & 0x400) ? 1 : 0; 3564 sync = (status & 0x800) ? 1 : 0; 3565 break; 3566 3567 case MADI: 3568 status = hdspm_read(hdspm, HDSPM_statusRegister); 3569 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3570 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3571 break; 3572 3573 case AES32: 3574 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3575 lock = (status & 0x100000) ? 1 : 0; 3576 sync = (status & 0x200000) ? 1 : 0; 3577 break; 3578 3579 case MADIface: 3580 break; 3581 } 3582 3583 if (lock && sync) 3584 return 2; 3585 else if (lock) 3586 return 1; 3587 3588 return 0; 3589 } 3590 3591 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3592 { 3593 int status2, lock, sync; 3594 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3595 3596 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3597 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3598 3599 if (sync) 3600 return 2; 3601 else if (lock) 3602 return 1; 3603 return 0; 3604 } 3605 3606 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask) 3607 { 3608 u32 status; 3609 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 3610 3611 return (status & mask) ? 1 : 0; 3612 } 3613 3614 3615 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3616 { 3617 int status; 3618 3619 if (hdspm->tco) { 3620 switch (hdspm->io_type) { 3621 case MADI: 3622 case AES32: 3623 status = hdspm_read(hdspm, HDSPM_statusRegister); 3624 if (status & HDSPM_tcoLock) { 3625 if (status & HDSPM_tcoSync) 3626 return 2; 3627 else 3628 return 1; 3629 } 3630 return 0; 3631 3632 break; 3633 3634 case RayDAT: 3635 case AIO: 3636 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3637 3638 if (status & 0x8000000) 3639 return 2; /* Sync */ 3640 if (status & 0x4000000) 3641 return 1; /* Lock */ 3642 return 0; /* No signal */ 3643 break; 3644 3645 default: 3646 break; 3647 } 3648 } 3649 3650 return 3; /* N/A */ 3651 } 3652 3653 3654 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3655 struct snd_ctl_elem_value *ucontrol) 3656 { 3657 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3658 int val = -1; 3659 3660 switch (hdspm->io_type) { 3661 case RayDAT: 3662 switch (kcontrol->private_value) { 3663 case 0: /* WC */ 3664 val = hdspm_wc_sync_check(hdspm); break; 3665 case 7: /* TCO */ 3666 val = hdspm_tco_sync_check(hdspm); break; 3667 case 8: /* SYNC IN */ 3668 val = hdspm_sync_in_sync_check(hdspm); break; 3669 default: 3670 val = hdspm_s1_sync_check(hdspm, 3671 kcontrol->private_value-1); 3672 } 3673 break; 3674 3675 case AIO: 3676 switch (kcontrol->private_value) { 3677 case 0: /* WC */ 3678 val = hdspm_wc_sync_check(hdspm); break; 3679 case 4: /* TCO */ 3680 val = hdspm_tco_sync_check(hdspm); break; 3681 case 5: /* SYNC IN */ 3682 val = hdspm_sync_in_sync_check(hdspm); break; 3683 default: 3684 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3685 } 3686 break; 3687 3688 case MADI: 3689 switch (kcontrol->private_value) { 3690 case 0: /* WC */ 3691 val = hdspm_wc_sync_check(hdspm); break; 3692 case 1: /* MADI */ 3693 val = hdspm_madi_sync_check(hdspm); break; 3694 case 2: /* TCO */ 3695 val = hdspm_tco_sync_check(hdspm); break; 3696 case 3: /* SYNC_IN */ 3697 val = hdspm_sync_in_sync_check(hdspm); break; 3698 } 3699 break; 3700 3701 case MADIface: 3702 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3703 break; 3704 3705 case AES32: 3706 switch (kcontrol->private_value) { 3707 case 0: /* WC */ 3708 val = hdspm_wc_sync_check(hdspm); break; 3709 case 9: /* TCO */ 3710 val = hdspm_tco_sync_check(hdspm); break; 3711 case 10 /* SYNC IN */: 3712 val = hdspm_sync_in_sync_check(hdspm); break; 3713 default: /* AES1 to AES8 */ 3714 val = hdspm_aes_sync_check(hdspm, 3715 kcontrol->private_value-1); 3716 } 3717 break; 3718 3719 } 3720 3721 if (hdspm->tco) { 3722 switch (kcontrol->private_value) { 3723 case 11: 3724 /* Check TCO for lock state of its current input */ 3725 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock); 3726 break; 3727 case 12: 3728 /* Check TCO for valid time code on LTC input. */ 3729 val = hdspm_tco_input_check(hdspm, 3730 HDSPM_TCO1_LTC_Input_valid); 3731 break; 3732 default: 3733 break; 3734 } 3735 } 3736 3737 if (-1 == val) 3738 val = 3; 3739 3740 ucontrol->value.enumerated.item[0] = val; 3741 return 0; 3742 } 3743 3744 3745 3746 /** 3747 * TCO controls 3748 **/ 3749 static void hdspm_tco_write(struct hdspm *hdspm) 3750 { 3751 unsigned int tc[4] = { 0, 0, 0, 0}; 3752 3753 switch (hdspm->tco->input) { 3754 case 0: 3755 tc[2] |= HDSPM_TCO2_set_input_MSB; 3756 break; 3757 case 1: 3758 tc[2] |= HDSPM_TCO2_set_input_LSB; 3759 break; 3760 default: 3761 break; 3762 } 3763 3764 switch (hdspm->tco->framerate) { 3765 case 1: 3766 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 3767 break; 3768 case 2: 3769 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 3770 break; 3771 case 3: 3772 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 3773 HDSPM_TCO1_set_drop_frame_flag; 3774 break; 3775 case 4: 3776 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3777 HDSPM_TCO1_LTC_Format_MSB; 3778 break; 3779 case 5: 3780 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3781 HDSPM_TCO1_LTC_Format_MSB + 3782 HDSPM_TCO1_set_drop_frame_flag; 3783 break; 3784 default: 3785 break; 3786 } 3787 3788 switch (hdspm->tco->wordclock) { 3789 case 1: 3790 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 3791 break; 3792 case 2: 3793 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 3794 break; 3795 default: 3796 break; 3797 } 3798 3799 switch (hdspm->tco->samplerate) { 3800 case 1: 3801 tc[2] |= HDSPM_TCO2_set_freq; 3802 break; 3803 case 2: 3804 tc[2] |= HDSPM_TCO2_set_freq_from_app; 3805 break; 3806 default: 3807 break; 3808 } 3809 3810 switch (hdspm->tco->pull) { 3811 case 1: 3812 tc[2] |= HDSPM_TCO2_set_pull_up; 3813 break; 3814 case 2: 3815 tc[2] |= HDSPM_TCO2_set_pull_down; 3816 break; 3817 case 3: 3818 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 3819 break; 3820 case 4: 3821 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 3822 break; 3823 default: 3824 break; 3825 } 3826 3827 if (1 == hdspm->tco->term) { 3828 tc[2] |= HDSPM_TCO2_set_term_75R; 3829 } 3830 3831 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 3832 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 3833 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 3834 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 3835 } 3836 3837 3838 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 3839 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3840 .name = xname, \ 3841 .index = xindex, \ 3842 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3843 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3844 .info = snd_hdspm_info_tco_sample_rate, \ 3845 .get = snd_hdspm_get_tco_sample_rate, \ 3846 .put = snd_hdspm_put_tco_sample_rate \ 3847 } 3848 3849 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 3850 struct snd_ctl_elem_info *uinfo) 3851 { 3852 static char *texts[] = { "44.1 kHz", "48 kHz" }; 3853 ENUMERATED_CTL_INFO(uinfo, texts); 3854 return 0; 3855 } 3856 3857 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 3858 struct snd_ctl_elem_value *ucontrol) 3859 { 3860 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3861 3862 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 3863 3864 return 0; 3865 } 3866 3867 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 3868 struct snd_ctl_elem_value *ucontrol) 3869 { 3870 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3871 3872 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 3873 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 3874 3875 hdspm_tco_write(hdspm); 3876 3877 return 1; 3878 } 3879 3880 return 0; 3881 } 3882 3883 3884 #define HDSPM_TCO_PULL(xname, xindex) \ 3885 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3886 .name = xname, \ 3887 .index = xindex, \ 3888 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3889 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3890 .info = snd_hdspm_info_tco_pull, \ 3891 .get = snd_hdspm_get_tco_pull, \ 3892 .put = snd_hdspm_put_tco_pull \ 3893 } 3894 3895 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 3896 struct snd_ctl_elem_info *uinfo) 3897 { 3898 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 3899 ENUMERATED_CTL_INFO(uinfo, texts); 3900 return 0; 3901 } 3902 3903 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 3904 struct snd_ctl_elem_value *ucontrol) 3905 { 3906 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3907 3908 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 3909 3910 return 0; 3911 } 3912 3913 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 3914 struct snd_ctl_elem_value *ucontrol) 3915 { 3916 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3917 3918 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 3919 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 3920 3921 hdspm_tco_write(hdspm); 3922 3923 return 1; 3924 } 3925 3926 return 0; 3927 } 3928 3929 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 3930 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3931 .name = xname, \ 3932 .index = xindex, \ 3933 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3934 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3935 .info = snd_hdspm_info_tco_wck_conversion, \ 3936 .get = snd_hdspm_get_tco_wck_conversion, \ 3937 .put = snd_hdspm_put_tco_wck_conversion \ 3938 } 3939 3940 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 3941 struct snd_ctl_elem_info *uinfo) 3942 { 3943 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 3944 ENUMERATED_CTL_INFO(uinfo, texts); 3945 return 0; 3946 } 3947 3948 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 3949 struct snd_ctl_elem_value *ucontrol) 3950 { 3951 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3952 3953 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 3954 3955 return 0; 3956 } 3957 3958 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 3959 struct snd_ctl_elem_value *ucontrol) 3960 { 3961 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3962 3963 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 3964 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 3965 3966 hdspm_tco_write(hdspm); 3967 3968 return 1; 3969 } 3970 3971 return 0; 3972 } 3973 3974 3975 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 3976 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3977 .name = xname, \ 3978 .index = xindex, \ 3979 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3980 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3981 .info = snd_hdspm_info_tco_frame_rate, \ 3982 .get = snd_hdspm_get_tco_frame_rate, \ 3983 .put = snd_hdspm_put_tco_frame_rate \ 3984 } 3985 3986 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 3987 struct snd_ctl_elem_info *uinfo) 3988 { 3989 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 3990 "29.97 dfps", "30 fps", "30 dfps" }; 3991 ENUMERATED_CTL_INFO(uinfo, texts); 3992 return 0; 3993 } 3994 3995 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 3996 struct snd_ctl_elem_value *ucontrol) 3997 { 3998 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3999 4000 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4001 4002 return 0; 4003 } 4004 4005 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4006 struct snd_ctl_elem_value *ucontrol) 4007 { 4008 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4009 4010 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4011 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4012 4013 hdspm_tco_write(hdspm); 4014 4015 return 1; 4016 } 4017 4018 return 0; 4019 } 4020 4021 4022 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4023 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4024 .name = xname, \ 4025 .index = xindex, \ 4026 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4027 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4028 .info = snd_hdspm_info_tco_sync_source, \ 4029 .get = snd_hdspm_get_tco_sync_source, \ 4030 .put = snd_hdspm_put_tco_sync_source \ 4031 } 4032 4033 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4034 struct snd_ctl_elem_info *uinfo) 4035 { 4036 static char *texts[] = { "LTC", "Video", "WCK" }; 4037 ENUMERATED_CTL_INFO(uinfo, texts); 4038 return 0; 4039 } 4040 4041 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4042 struct snd_ctl_elem_value *ucontrol) 4043 { 4044 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4045 4046 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4047 4048 return 0; 4049 } 4050 4051 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4052 struct snd_ctl_elem_value *ucontrol) 4053 { 4054 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4055 4056 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4057 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4058 4059 hdspm_tco_write(hdspm); 4060 4061 return 1; 4062 } 4063 4064 return 0; 4065 } 4066 4067 4068 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4069 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4070 .name = xname, \ 4071 .index = xindex, \ 4072 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4073 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4074 .info = snd_hdspm_info_tco_word_term, \ 4075 .get = snd_hdspm_get_tco_word_term, \ 4076 .put = snd_hdspm_put_tco_word_term \ 4077 } 4078 4079 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4080 struct snd_ctl_elem_info *uinfo) 4081 { 4082 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4083 uinfo->count = 1; 4084 uinfo->value.integer.min = 0; 4085 uinfo->value.integer.max = 1; 4086 4087 return 0; 4088 } 4089 4090 4091 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4092 struct snd_ctl_elem_value *ucontrol) 4093 { 4094 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4095 4096 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4097 4098 return 0; 4099 } 4100 4101 4102 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4103 struct snd_ctl_elem_value *ucontrol) 4104 { 4105 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4106 4107 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4108 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4109 4110 hdspm_tco_write(hdspm); 4111 4112 return 1; 4113 } 4114 4115 return 0; 4116 } 4117 4118 4119 4120 4121 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4122 HDSPM_MIXER("Mixer", 0), 4123 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4124 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4125 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4126 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4127 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4128 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4129 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4130 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4131 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4132 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4133 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4134 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4135 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX), 4136 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4137 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4138 HDSPM_INPUT_SELECT("Input Select", 0), 4139 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4140 }; 4141 4142 4143 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4144 HDSPM_MIXER("Mixer", 0), 4145 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4146 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4147 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4148 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4149 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4150 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4151 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4152 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4153 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4154 }; 4155 4156 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4157 HDSPM_MIXER("Mixer", 0), 4158 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4159 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4160 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4161 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4162 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4163 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4164 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4165 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4166 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4167 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4168 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4169 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4170 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4171 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4172 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4173 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4174 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4175 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4176 4177 /* 4178 HDSPM_INPUT_SELECT("Input Select", 0), 4179 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4180 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4181 HDSPM_SPDIF_IN("SPDIF In", 0); 4182 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4183 HDSPM_INPUT_LEVEL("Input Level", 0); 4184 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4185 HDSPM_PHONES("Phones", 0); 4186 */ 4187 }; 4188 4189 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4190 HDSPM_MIXER("Mixer", 0), 4191 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4192 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4193 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4194 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4195 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4196 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4197 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4198 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4199 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4200 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4201 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4202 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4203 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4204 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4205 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4206 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4207 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4208 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4209 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4210 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4211 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4212 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4213 }; 4214 4215 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4216 HDSPM_MIXER("Mixer", 0), 4217 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4218 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4219 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4220 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4221 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4222 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4223 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4224 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4225 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4226 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4227 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4228 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4229 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4230 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4231 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4232 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4233 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4234 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4235 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4236 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4237 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4238 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4239 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4240 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4241 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4242 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4243 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4244 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4245 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4246 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4247 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4248 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4249 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4250 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4251 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4252 }; 4253 4254 4255 4256 /* Control elements for the optional TCO module */ 4257 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4258 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4259 HDSPM_TCO_PULL("TCO Pull", 0), 4260 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4261 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4262 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4263 HDSPM_TCO_WORD_TERM("TCO Word Term", 0) 4264 }; 4265 4266 4267 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4268 4269 4270 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4271 { 4272 int i; 4273 4274 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4275 if (hdspm->system_sample_rate > 48000) { 4276 hdspm->playback_mixer_ctls[i]->vd[0].access = 4277 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4278 SNDRV_CTL_ELEM_ACCESS_READ | 4279 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4280 } else { 4281 hdspm->playback_mixer_ctls[i]->vd[0].access = 4282 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4283 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4284 } 4285 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4286 SNDRV_CTL_EVENT_MASK_INFO, 4287 &hdspm->playback_mixer_ctls[i]->id); 4288 } 4289 4290 return 0; 4291 } 4292 4293 4294 static int snd_hdspm_create_controls(struct snd_card *card, 4295 struct hdspm *hdspm) 4296 { 4297 unsigned int idx, limit; 4298 int err; 4299 struct snd_kcontrol *kctl; 4300 struct snd_kcontrol_new *list = NULL; 4301 4302 switch (hdspm->io_type) { 4303 case MADI: 4304 list = snd_hdspm_controls_madi; 4305 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4306 break; 4307 case MADIface: 4308 list = snd_hdspm_controls_madiface; 4309 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4310 break; 4311 case AIO: 4312 list = snd_hdspm_controls_aio; 4313 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4314 break; 4315 case RayDAT: 4316 list = snd_hdspm_controls_raydat; 4317 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4318 break; 4319 case AES32: 4320 list = snd_hdspm_controls_aes32; 4321 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4322 break; 4323 } 4324 4325 if (NULL != list) { 4326 for (idx = 0; idx < limit; idx++) { 4327 err = snd_ctl_add(card, 4328 snd_ctl_new1(&list[idx], hdspm)); 4329 if (err < 0) 4330 return err; 4331 } 4332 } 4333 4334 4335 /* create simple 1:1 playback mixer controls */ 4336 snd_hdspm_playback_mixer.name = "Chn"; 4337 if (hdspm->system_sample_rate >= 128000) { 4338 limit = hdspm->qs_out_channels; 4339 } else if (hdspm->system_sample_rate >= 64000) { 4340 limit = hdspm->ds_out_channels; 4341 } else { 4342 limit = hdspm->ss_out_channels; 4343 } 4344 for (idx = 0; idx < limit; ++idx) { 4345 snd_hdspm_playback_mixer.index = idx + 1; 4346 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4347 err = snd_ctl_add(card, kctl); 4348 if (err < 0) 4349 return err; 4350 hdspm->playback_mixer_ctls[idx] = kctl; 4351 } 4352 4353 4354 if (hdspm->tco) { 4355 /* add tco control elements */ 4356 list = snd_hdspm_controls_tco; 4357 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4358 for (idx = 0; idx < limit; idx++) { 4359 err = snd_ctl_add(card, 4360 snd_ctl_new1(&list[idx], hdspm)); 4361 if (err < 0) 4362 return err; 4363 } 4364 } 4365 4366 return 0; 4367 } 4368 4369 /*------------------------------------------------------------ 4370 /proc interface 4371 ------------------------------------------------------------*/ 4372 4373 static void 4374 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4375 struct snd_info_buffer *buffer) 4376 { 4377 struct hdspm *hdspm = entry->private_data; 4378 unsigned int status, status2, control, freq; 4379 4380 char *pref_sync_ref; 4381 char *autosync_ref; 4382 char *system_clock_mode; 4383 char *insel; 4384 int x, x2; 4385 4386 /* TCO stuff */ 4387 int a, ltc, frames, seconds, minutes, hours; 4388 unsigned int period; 4389 u64 freq_const = 0; 4390 u32 rate; 4391 4392 status = hdspm_read(hdspm, HDSPM_statusRegister); 4393 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4394 control = hdspm->control_register; 4395 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4396 4397 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4398 hdspm->card_name, hdspm->card->number + 1, 4399 hdspm->firmware_rev, 4400 (status2 & HDSPM_version0) | 4401 (status2 & HDSPM_version1) | (status2 & 4402 HDSPM_version2)); 4403 4404 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4405 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4406 hdspm->serial); 4407 4408 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4409 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4410 4411 snd_iprintf(buffer, "--- System ---\n"); 4412 4413 snd_iprintf(buffer, 4414 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4415 status & HDSPM_audioIRQPending, 4416 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4417 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4418 hdspm->irq_count); 4419 snd_iprintf(buffer, 4420 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4421 "estimated= %ld (bytes)\n", 4422 ((status & HDSPM_BufferID) ? 1 : 0), 4423 (status & HDSPM_BufferPositionMask), 4424 (status & HDSPM_BufferPositionMask) % 4425 (2 * (int)hdspm->period_bytes), 4426 ((status & HDSPM_BufferPositionMask) - 64) % 4427 (2 * (int)hdspm->period_bytes), 4428 (long) hdspm_hw_pointer(hdspm) * 4); 4429 4430 snd_iprintf(buffer, 4431 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4432 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4433 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4434 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4435 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4436 snd_iprintf(buffer, 4437 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4438 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4439 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4440 snd_iprintf(buffer, 4441 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4442 "status2=0x%x\n", 4443 hdspm->control_register, hdspm->control2_register, 4444 status, status2); 4445 if (status & HDSPM_tco_detect) { 4446 snd_iprintf(buffer, "TCO module detected.\n"); 4447 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4448 if (a & HDSPM_TCO1_LTC_Input_valid) { 4449 snd_iprintf(buffer, " LTC valid, "); 4450 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4451 HDSPM_TCO1_LTC_Format_MSB)) { 4452 case 0: 4453 snd_iprintf(buffer, "24 fps, "); 4454 break; 4455 case HDSPM_TCO1_LTC_Format_LSB: 4456 snd_iprintf(buffer, "25 fps, "); 4457 break; 4458 case HDSPM_TCO1_LTC_Format_MSB: 4459 snd_iprintf(buffer, "29.97 fps, "); 4460 break; 4461 default: 4462 snd_iprintf(buffer, "30 fps, "); 4463 break; 4464 } 4465 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4466 snd_iprintf(buffer, "drop frame\n"); 4467 } else { 4468 snd_iprintf(buffer, "full frame\n"); 4469 } 4470 } else { 4471 snd_iprintf(buffer, " no LTC\n"); 4472 } 4473 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4474 snd_iprintf(buffer, " Video: NTSC\n"); 4475 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4476 snd_iprintf(buffer, " Video: PAL\n"); 4477 } else { 4478 snd_iprintf(buffer, " No video\n"); 4479 } 4480 if (a & HDSPM_TCO1_TCO_lock) { 4481 snd_iprintf(buffer, " Sync: lock\n"); 4482 } else { 4483 snd_iprintf(buffer, " Sync: no lock\n"); 4484 } 4485 4486 switch (hdspm->io_type) { 4487 case MADI: 4488 case AES32: 4489 freq_const = 110069313433624ULL; 4490 break; 4491 case RayDAT: 4492 case AIO: 4493 freq_const = 104857600000000ULL; 4494 break; 4495 case MADIface: 4496 break; /* no TCO possible */ 4497 } 4498 4499 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4500 snd_iprintf(buffer, " period: %u\n", period); 4501 4502 4503 /* rate = freq_const/period; */ 4504 rate = div_u64(freq_const, period); 4505 4506 if (control & HDSPM_QuadSpeed) { 4507 rate *= 4; 4508 } else if (control & HDSPM_DoubleSpeed) { 4509 rate *= 2; 4510 } 4511 4512 snd_iprintf(buffer, " Frequency: %u Hz\n", 4513 (unsigned int) rate); 4514 4515 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4516 frames = ltc & 0xF; 4517 ltc >>= 4; 4518 frames += (ltc & 0x3) * 10; 4519 ltc >>= 4; 4520 seconds = ltc & 0xF; 4521 ltc >>= 4; 4522 seconds += (ltc & 0x7) * 10; 4523 ltc >>= 4; 4524 minutes = ltc & 0xF; 4525 ltc >>= 4; 4526 minutes += (ltc & 0x7) * 10; 4527 ltc >>= 4; 4528 hours = ltc & 0xF; 4529 ltc >>= 4; 4530 hours += (ltc & 0x3) * 10; 4531 snd_iprintf(buffer, 4532 " LTC In: %02d:%02d:%02d:%02d\n", 4533 hours, minutes, seconds, frames); 4534 4535 } else { 4536 snd_iprintf(buffer, "No TCO module detected.\n"); 4537 } 4538 4539 snd_iprintf(buffer, "--- Settings ---\n"); 4540 4541 x = hdspm_get_latency(hdspm); 4542 4543 snd_iprintf(buffer, 4544 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4545 x, (unsigned long) hdspm->period_bytes); 4546 4547 snd_iprintf(buffer, "Line out: %s\n", 4548 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4549 4550 switch (hdspm->control_register & HDSPM_InputMask) { 4551 case HDSPM_InputOptical: 4552 insel = "Optical"; 4553 break; 4554 case HDSPM_InputCoaxial: 4555 insel = "Coaxial"; 4556 break; 4557 default: 4558 insel = "Unknown"; 4559 } 4560 4561 snd_iprintf(buffer, 4562 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4563 "Auto Input %s\n", 4564 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4565 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4566 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4567 4568 4569 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4570 system_clock_mode = "AutoSync"; 4571 else 4572 system_clock_mode = "Master"; 4573 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4574 4575 switch (hdspm_pref_sync_ref(hdspm)) { 4576 case HDSPM_SYNC_FROM_WORD: 4577 pref_sync_ref = "Word Clock"; 4578 break; 4579 case HDSPM_SYNC_FROM_MADI: 4580 pref_sync_ref = "MADI Sync"; 4581 break; 4582 case HDSPM_SYNC_FROM_TCO: 4583 pref_sync_ref = "TCO"; 4584 break; 4585 case HDSPM_SYNC_FROM_SYNC_IN: 4586 pref_sync_ref = "Sync In"; 4587 break; 4588 default: 4589 pref_sync_ref = "XXXX Clock"; 4590 break; 4591 } 4592 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4593 pref_sync_ref); 4594 4595 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4596 hdspm->system_sample_rate); 4597 4598 4599 snd_iprintf(buffer, "--- Status:\n"); 4600 4601 x = status & HDSPM_madiSync; 4602 x2 = status2 & HDSPM_wcSync; 4603 4604 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4605 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4606 "NoLock", 4607 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4608 "NoLock"); 4609 4610 switch (hdspm_autosync_ref(hdspm)) { 4611 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4612 autosync_ref = "Sync In"; 4613 break; 4614 case HDSPM_AUTOSYNC_FROM_TCO: 4615 autosync_ref = "TCO"; 4616 break; 4617 case HDSPM_AUTOSYNC_FROM_WORD: 4618 autosync_ref = "Word Clock"; 4619 break; 4620 case HDSPM_AUTOSYNC_FROM_MADI: 4621 autosync_ref = "MADI Sync"; 4622 break; 4623 case HDSPM_AUTOSYNC_FROM_NONE: 4624 autosync_ref = "Input not valid"; 4625 break; 4626 default: 4627 autosync_ref = "---"; 4628 break; 4629 } 4630 snd_iprintf(buffer, 4631 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4632 autosync_ref, hdspm_external_sample_rate(hdspm), 4633 (status & HDSPM_madiFreqMask) >> 22, 4634 (status2 & HDSPM_wcFreqMask) >> 5); 4635 4636 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4637 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4638 (status & HDSPM_RX_64ch) ? "64 channels" : 4639 "56 channels"); 4640 4641 snd_iprintf(buffer, "\n"); 4642 } 4643 4644 static void 4645 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4646 struct snd_info_buffer *buffer) 4647 { 4648 struct hdspm *hdspm = entry->private_data; 4649 unsigned int status; 4650 unsigned int status2; 4651 unsigned int timecode; 4652 unsigned int wcLock, wcSync; 4653 int pref_syncref; 4654 char *autosync_ref; 4655 int x; 4656 4657 status = hdspm_read(hdspm, HDSPM_statusRegister); 4658 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4659 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4660 4661 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4662 hdspm->card_name, hdspm->card->number + 1, 4663 hdspm->firmware_rev); 4664 4665 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4666 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4667 4668 snd_iprintf(buffer, "--- System ---\n"); 4669 4670 snd_iprintf(buffer, 4671 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4672 status & HDSPM_audioIRQPending, 4673 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4674 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4675 hdspm->irq_count); 4676 snd_iprintf(buffer, 4677 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4678 "estimated= %ld (bytes)\n", 4679 ((status & HDSPM_BufferID) ? 1 : 0), 4680 (status & HDSPM_BufferPositionMask), 4681 (status & HDSPM_BufferPositionMask) % 4682 (2 * (int)hdspm->period_bytes), 4683 ((status & HDSPM_BufferPositionMask) - 64) % 4684 (2 * (int)hdspm->period_bytes), 4685 (long) hdspm_hw_pointer(hdspm) * 4); 4686 4687 snd_iprintf(buffer, 4688 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4689 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4690 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4691 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4692 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4693 snd_iprintf(buffer, 4694 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4695 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4696 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4697 snd_iprintf(buffer, 4698 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4699 "status2=0x%x\n", 4700 hdspm->control_register, hdspm->control2_register, 4701 status, status2); 4702 4703 snd_iprintf(buffer, "--- Settings ---\n"); 4704 4705 x = hdspm_get_latency(hdspm); 4706 4707 snd_iprintf(buffer, 4708 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4709 x, (unsigned long) hdspm->period_bytes); 4710 4711 snd_iprintf(buffer, "Line out: %s\n", 4712 (hdspm-> 4713 control_register & HDSPM_LineOut) ? "on " : "off"); 4714 4715 snd_iprintf(buffer, 4716 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 4717 (hdspm-> 4718 control_register & HDSPM_clr_tms) ? "on" : "off", 4719 (hdspm-> 4720 control_register & HDSPM_Emphasis) ? "on" : "off", 4721 (hdspm-> 4722 control_register & HDSPM_Dolby) ? "on" : "off"); 4723 4724 4725 pref_syncref = hdspm_pref_sync_ref(hdspm); 4726 if (pref_syncref == 0) 4727 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 4728 else 4729 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 4730 pref_syncref); 4731 4732 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4733 hdspm->system_sample_rate); 4734 4735 snd_iprintf(buffer, "Double speed: %s\n", 4736 hdspm->control_register & HDSPM_DS_DoubleWire? 4737 "Double wire" : "Single wire"); 4738 snd_iprintf(buffer, "Quad speed: %s\n", 4739 hdspm->control_register & HDSPM_QS_DoubleWire? 4740 "Double wire" : 4741 hdspm->control_register & HDSPM_QS_QuadWire? 4742 "Quad wire" : "Single wire"); 4743 4744 snd_iprintf(buffer, "--- Status:\n"); 4745 4746 wcLock = status & HDSPM_AES32_wcLock; 4747 wcSync = wcLock && (status & HDSPM_AES32_wcSync); 4748 4749 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 4750 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock", 4751 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 4752 4753 for (x = 0; x < 8; x++) { 4754 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 4755 x+1, 4756 (status2 & (HDSPM_LockAES >> x)) ? 4757 "Sync " : "No Lock", 4758 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 4759 } 4760 4761 switch (hdspm_autosync_ref(hdspm)) { 4762 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 4763 autosync_ref = "None"; break; 4764 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 4765 autosync_ref = "Word Clock"; break; 4766 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 4767 autosync_ref = "AES1"; break; 4768 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 4769 autosync_ref = "AES2"; break; 4770 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 4771 autosync_ref = "AES3"; break; 4772 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 4773 autosync_ref = "AES4"; break; 4774 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 4775 autosync_ref = "AES5"; break; 4776 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 4777 autosync_ref = "AES6"; break; 4778 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 4779 autosync_ref = "AES7"; break; 4780 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 4781 autosync_ref = "AES8"; break; 4782 default: 4783 autosync_ref = "---"; break; 4784 } 4785 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 4786 4787 snd_iprintf(buffer, "\n"); 4788 } 4789 4790 static void 4791 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 4792 struct snd_info_buffer *buffer) 4793 { 4794 struct hdspm *hdspm = entry->private_data; 4795 unsigned int status1, status2, status3, control, i; 4796 unsigned int lock, sync; 4797 4798 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 4799 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 4800 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 4801 4802 control = hdspm->control_register; 4803 4804 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 4805 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 4806 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 4807 4808 4809 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 4810 4811 snd_iprintf(buffer, "Clock mode : %s\n", 4812 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 4813 snd_iprintf(buffer, "System frequency: %d Hz\n", 4814 hdspm_get_system_sample_rate(hdspm)); 4815 4816 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 4817 4818 lock = 0x1; 4819 sync = 0x100; 4820 4821 for (i = 0; i < 8; i++) { 4822 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 4823 i, 4824 (status1 & lock) ? 1 : 0, 4825 (status1 & sync) ? 1 : 0, 4826 texts_freq[(status2 >> (i * 4)) & 0xF]); 4827 4828 lock = lock<<1; 4829 sync = sync<<1; 4830 } 4831 4832 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 4833 (status1 & 0x1000000) ? 1 : 0, 4834 (status1 & 0x2000000) ? 1 : 0, 4835 texts_freq[(status1 >> 16) & 0xF]); 4836 4837 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 4838 (status1 & 0x4000000) ? 1 : 0, 4839 (status1 & 0x8000000) ? 1 : 0, 4840 texts_freq[(status1 >> 20) & 0xF]); 4841 4842 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 4843 (status3 & 0x400) ? 1 : 0, 4844 (status3 & 0x800) ? 1 : 0, 4845 texts_freq[(status2 >> 12) & 0xF]); 4846 4847 } 4848 4849 #ifdef CONFIG_SND_DEBUG 4850 static void 4851 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 4852 struct snd_info_buffer *buffer) 4853 { 4854 struct hdspm *hdspm = entry->private_data; 4855 4856 int j,i; 4857 4858 for (i = 0; i < 256 /* 1024*64 */; i += j) { 4859 snd_iprintf(buffer, "0x%08X: ", i); 4860 for (j = 0; j < 16; j += 4) 4861 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 4862 snd_iprintf(buffer, "\n"); 4863 } 4864 } 4865 #endif 4866 4867 4868 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 4869 struct snd_info_buffer *buffer) 4870 { 4871 struct hdspm *hdspm = entry->private_data; 4872 int i; 4873 4874 snd_iprintf(buffer, "# generated by hdspm\n"); 4875 4876 for (i = 0; i < hdspm->max_channels_in; i++) { 4877 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 4878 } 4879 } 4880 4881 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 4882 struct snd_info_buffer *buffer) 4883 { 4884 struct hdspm *hdspm = entry->private_data; 4885 int i; 4886 4887 snd_iprintf(buffer, "# generated by hdspm\n"); 4888 4889 for (i = 0; i < hdspm->max_channels_out; i++) { 4890 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 4891 } 4892 } 4893 4894 4895 static void snd_hdspm_proc_init(struct hdspm *hdspm) 4896 { 4897 struct snd_info_entry *entry; 4898 4899 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 4900 switch (hdspm->io_type) { 4901 case AES32: 4902 snd_info_set_text_ops(entry, hdspm, 4903 snd_hdspm_proc_read_aes32); 4904 break; 4905 case MADI: 4906 snd_info_set_text_ops(entry, hdspm, 4907 snd_hdspm_proc_read_madi); 4908 break; 4909 case MADIface: 4910 /* snd_info_set_text_ops(entry, hdspm, 4911 snd_hdspm_proc_read_madiface); */ 4912 break; 4913 case RayDAT: 4914 snd_info_set_text_ops(entry, hdspm, 4915 snd_hdspm_proc_read_raydat); 4916 break; 4917 case AIO: 4918 break; 4919 } 4920 } 4921 4922 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 4923 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 4924 } 4925 4926 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 4927 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 4928 } 4929 4930 #ifdef CONFIG_SND_DEBUG 4931 /* debug file to read all hdspm registers */ 4932 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 4933 snd_info_set_text_ops(entry, hdspm, 4934 snd_hdspm_proc_read_debug); 4935 #endif 4936 } 4937 4938 /*------------------------------------------------------------ 4939 hdspm intitialize 4940 ------------------------------------------------------------*/ 4941 4942 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 4943 { 4944 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 4945 hold it (e.g. during module initialization). 4946 */ 4947 4948 /* set defaults: */ 4949 4950 hdspm->settings_register = 0; 4951 4952 switch (hdspm->io_type) { 4953 case MADI: 4954 case MADIface: 4955 hdspm->control_register = 4956 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 4957 break; 4958 4959 case RayDAT: 4960 case AIO: 4961 hdspm->settings_register = 0x1 + 0x1000; 4962 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 4963 * line_out */ 4964 hdspm->control_register = 4965 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 4966 break; 4967 4968 case AES32: 4969 hdspm->control_register = 4970 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 4971 hdspm_encode_latency(7) | /* latency max=8192samples */ 4972 HDSPM_SyncRef0 | /* AES1 is syncclock */ 4973 HDSPM_LineOut | /* Analog output in */ 4974 HDSPM_Professional; /* Professional mode */ 4975 break; 4976 } 4977 4978 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 4979 4980 if (AES32 == hdspm->io_type) { 4981 /* No control2 register for AES32 */ 4982 #ifdef SNDRV_BIG_ENDIAN 4983 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 4984 #else 4985 hdspm->control2_register = 0; 4986 #endif 4987 4988 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 4989 } 4990 hdspm_compute_period_size(hdspm); 4991 4992 /* silence everything */ 4993 4994 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 4995 4996 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { 4997 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 4998 } 4999 5000 /* set a default rate so that the channel map is set up. */ 5001 hdspm_set_rate(hdspm, 48000, 1); 5002 5003 return 0; 5004 } 5005 5006 5007 /*------------------------------------------------------------ 5008 interrupt 5009 ------------------------------------------------------------*/ 5010 5011 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5012 { 5013 struct hdspm *hdspm = (struct hdspm *) dev_id; 5014 unsigned int status; 5015 int i, audio, midi, schedule = 0; 5016 /* cycles_t now; */ 5017 5018 status = hdspm_read(hdspm, HDSPM_statusRegister); 5019 5020 audio = status & HDSPM_audioIRQPending; 5021 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5022 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5023 5024 /* now = get_cycles(); */ 5025 /** 5026 * LAT_2..LAT_0 period counter (win) counter (mac) 5027 * 6 4096 ~256053425 ~514672358 5028 * 5 2048 ~128024983 ~257373821 5029 * 4 1024 ~64023706 ~128718089 5030 * 3 512 ~32005945 ~64385999 5031 * 2 256 ~16003039 ~32260176 5032 * 1 128 ~7998738 ~16194507 5033 * 0 64 ~3998231 ~8191558 5034 **/ 5035 /* 5036 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5037 now-hdspm->last_interrupt, status & 0xFFC0); 5038 hdspm->last_interrupt = now; 5039 */ 5040 5041 if (!audio && !midi) 5042 return IRQ_NONE; 5043 5044 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5045 hdspm->irq_count++; 5046 5047 5048 if (audio) { 5049 if (hdspm->capture_substream) 5050 snd_pcm_period_elapsed(hdspm->capture_substream); 5051 5052 if (hdspm->playback_substream) 5053 snd_pcm_period_elapsed(hdspm->playback_substream); 5054 } 5055 5056 if (midi) { 5057 i = 0; 5058 while (i < hdspm->midiPorts) { 5059 if ((hdspm_read(hdspm, 5060 hdspm->midi[i].statusIn) & 0xff) && 5061 (status & hdspm->midi[i].irq)) { 5062 /* we disable interrupts for this input until 5063 * processing is done 5064 */ 5065 hdspm->control_register &= ~hdspm->midi[i].ie; 5066 hdspm_write(hdspm, HDSPM_controlRegister, 5067 hdspm->control_register); 5068 hdspm->midi[i].pending = 1; 5069 schedule = 1; 5070 } 5071 5072 i++; 5073 } 5074 5075 if (schedule) 5076 tasklet_hi_schedule(&hdspm->midi_tasklet); 5077 } 5078 5079 return IRQ_HANDLED; 5080 } 5081 5082 /*------------------------------------------------------------ 5083 pcm interface 5084 ------------------------------------------------------------*/ 5085 5086 5087 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5088 *substream) 5089 { 5090 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5091 return hdspm_hw_pointer(hdspm); 5092 } 5093 5094 5095 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5096 { 5097 struct snd_pcm_runtime *runtime = substream->runtime; 5098 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5099 struct snd_pcm_substream *other; 5100 5101 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5102 other = hdspm->capture_substream; 5103 else 5104 other = hdspm->playback_substream; 5105 5106 if (hdspm->running) 5107 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5108 else 5109 runtime->status->hw_ptr = 0; 5110 if (other) { 5111 struct snd_pcm_substream *s; 5112 struct snd_pcm_runtime *oruntime = other->runtime; 5113 snd_pcm_group_for_each_entry(s, substream) { 5114 if (s == other) { 5115 oruntime->status->hw_ptr = 5116 runtime->status->hw_ptr; 5117 break; 5118 } 5119 } 5120 } 5121 return 0; 5122 } 5123 5124 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5125 struct snd_pcm_hw_params *params) 5126 { 5127 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5128 int err; 5129 int i; 5130 pid_t this_pid; 5131 pid_t other_pid; 5132 5133 spin_lock_irq(&hdspm->lock); 5134 5135 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5136 this_pid = hdspm->playback_pid; 5137 other_pid = hdspm->capture_pid; 5138 } else { 5139 this_pid = hdspm->capture_pid; 5140 other_pid = hdspm->playback_pid; 5141 } 5142 5143 if (other_pid > 0 && this_pid != other_pid) { 5144 5145 /* The other stream is open, and not by the same 5146 task as this one. Make sure that the parameters 5147 that matter are the same. 5148 */ 5149 5150 if (params_rate(params) != hdspm->system_sample_rate) { 5151 spin_unlock_irq(&hdspm->lock); 5152 _snd_pcm_hw_param_setempty(params, 5153 SNDRV_PCM_HW_PARAM_RATE); 5154 return -EBUSY; 5155 } 5156 5157 if (params_period_size(params) != hdspm->period_bytes / 4) { 5158 spin_unlock_irq(&hdspm->lock); 5159 _snd_pcm_hw_param_setempty(params, 5160 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5161 return -EBUSY; 5162 } 5163 5164 } 5165 /* We're fine. */ 5166 spin_unlock_irq(&hdspm->lock); 5167 5168 /* how to make sure that the rate matches an externally-set one ? */ 5169 5170 spin_lock_irq(&hdspm->lock); 5171 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5172 if (err < 0) { 5173 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5174 spin_unlock_irq(&hdspm->lock); 5175 _snd_pcm_hw_param_setempty(params, 5176 SNDRV_PCM_HW_PARAM_RATE); 5177 return err; 5178 } 5179 spin_unlock_irq(&hdspm->lock); 5180 5181 err = hdspm_set_interrupt_interval(hdspm, 5182 params_period_size(params)); 5183 if (err < 0) { 5184 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5185 _snd_pcm_hw_param_setempty(params, 5186 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5187 return err; 5188 } 5189 5190 /* Memory allocation, takashi's method, dont know if we should 5191 * spinlock 5192 */ 5193 /* malloc all buffer even if not enabled to get sure */ 5194 /* Update for MADI rev 204: we need to allocate for all channels, 5195 * otherwise it doesn't work at 96kHz */ 5196 5197 err = 5198 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5199 if (err < 0) { 5200 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5201 return err; 5202 } 5203 5204 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5205 5206 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5207 params_channels(params)); 5208 5209 for (i = 0; i < params_channels(params); ++i) 5210 snd_hdspm_enable_out(hdspm, i, 1); 5211 5212 hdspm->playback_buffer = 5213 (unsigned char *) substream->runtime->dma_area; 5214 snd_printdd("Allocated sample buffer for playback at %p\n", 5215 hdspm->playback_buffer); 5216 } else { 5217 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5218 params_channels(params)); 5219 5220 for (i = 0; i < params_channels(params); ++i) 5221 snd_hdspm_enable_in(hdspm, i, 1); 5222 5223 hdspm->capture_buffer = 5224 (unsigned char *) substream->runtime->dma_area; 5225 snd_printdd("Allocated sample buffer for capture at %p\n", 5226 hdspm->capture_buffer); 5227 } 5228 5229 /* 5230 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5231 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5232 "playback" : "capture", 5233 snd_pcm_sgbuf_get_addr(substream, 0)); 5234 */ 5235 /* 5236 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5237 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5238 "playback" : "capture", 5239 params_rate(params), params_channels(params), 5240 params_buffer_size(params)); 5241 */ 5242 5243 5244 /* Switch to native float format if requested */ 5245 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5246 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5247 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5248 5249 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5250 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5251 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5252 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5253 5254 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5255 } 5256 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5257 5258 return 0; 5259 } 5260 5261 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5262 { 5263 int i; 5264 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5265 5266 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5267 5268 /* params_channels(params) should be enough, 5269 but to get sure in case of error */ 5270 for (i = 0; i < hdspm->max_channels_out; ++i) 5271 snd_hdspm_enable_out(hdspm, i, 0); 5272 5273 hdspm->playback_buffer = NULL; 5274 } else { 5275 for (i = 0; i < hdspm->max_channels_in; ++i) 5276 snd_hdspm_enable_in(hdspm, i, 0); 5277 5278 hdspm->capture_buffer = NULL; 5279 5280 } 5281 5282 snd_pcm_lib_free_pages(substream); 5283 5284 return 0; 5285 } 5286 5287 5288 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5289 struct snd_pcm_channel_info *info) 5290 { 5291 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5292 5293 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5294 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5295 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5296 return -EINVAL; 5297 } 5298 5299 if (hdspm->channel_map_out[info->channel] < 0) { 5300 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5301 return -EINVAL; 5302 } 5303 5304 info->offset = hdspm->channel_map_out[info->channel] * 5305 HDSPM_CHANNEL_BUFFER_BYTES; 5306 } else { 5307 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5308 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5309 return -EINVAL; 5310 } 5311 5312 if (hdspm->channel_map_in[info->channel] < 0) { 5313 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5314 return -EINVAL; 5315 } 5316 5317 info->offset = hdspm->channel_map_in[info->channel] * 5318 HDSPM_CHANNEL_BUFFER_BYTES; 5319 } 5320 5321 info->first = 0; 5322 info->step = 32; 5323 return 0; 5324 } 5325 5326 5327 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5328 unsigned int cmd, void *arg) 5329 { 5330 switch (cmd) { 5331 case SNDRV_PCM_IOCTL1_RESET: 5332 return snd_hdspm_reset(substream); 5333 5334 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5335 { 5336 struct snd_pcm_channel_info *info = arg; 5337 return snd_hdspm_channel_info(substream, info); 5338 } 5339 default: 5340 break; 5341 } 5342 5343 return snd_pcm_lib_ioctl(substream, cmd, arg); 5344 } 5345 5346 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5347 { 5348 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5349 struct snd_pcm_substream *other; 5350 int running; 5351 5352 spin_lock(&hdspm->lock); 5353 running = hdspm->running; 5354 switch (cmd) { 5355 case SNDRV_PCM_TRIGGER_START: 5356 running |= 1 << substream->stream; 5357 break; 5358 case SNDRV_PCM_TRIGGER_STOP: 5359 running &= ~(1 << substream->stream); 5360 break; 5361 default: 5362 snd_BUG(); 5363 spin_unlock(&hdspm->lock); 5364 return -EINVAL; 5365 } 5366 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5367 other = hdspm->capture_substream; 5368 else 5369 other = hdspm->playback_substream; 5370 5371 if (other) { 5372 struct snd_pcm_substream *s; 5373 snd_pcm_group_for_each_entry(s, substream) { 5374 if (s == other) { 5375 snd_pcm_trigger_done(s, substream); 5376 if (cmd == SNDRV_PCM_TRIGGER_START) 5377 running |= 1 << s->stream; 5378 else 5379 running &= ~(1 << s->stream); 5380 goto _ok; 5381 } 5382 } 5383 if (cmd == SNDRV_PCM_TRIGGER_START) { 5384 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5385 && substream->stream == 5386 SNDRV_PCM_STREAM_CAPTURE) 5387 hdspm_silence_playback(hdspm); 5388 } else { 5389 if (running && 5390 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5391 hdspm_silence_playback(hdspm); 5392 } 5393 } else { 5394 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5395 hdspm_silence_playback(hdspm); 5396 } 5397 _ok: 5398 snd_pcm_trigger_done(substream, substream); 5399 if (!hdspm->running && running) 5400 hdspm_start_audio(hdspm); 5401 else if (hdspm->running && !running) 5402 hdspm_stop_audio(hdspm); 5403 hdspm->running = running; 5404 spin_unlock(&hdspm->lock); 5405 5406 return 0; 5407 } 5408 5409 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5410 { 5411 return 0; 5412 } 5413 5414 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5415 .info = (SNDRV_PCM_INFO_MMAP | 5416 SNDRV_PCM_INFO_MMAP_VALID | 5417 SNDRV_PCM_INFO_NONINTERLEAVED | 5418 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5419 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5420 .rates = (SNDRV_PCM_RATE_32000 | 5421 SNDRV_PCM_RATE_44100 | 5422 SNDRV_PCM_RATE_48000 | 5423 SNDRV_PCM_RATE_64000 | 5424 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5425 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5426 .rate_min = 32000, 5427 .rate_max = 192000, 5428 .channels_min = 1, 5429 .channels_max = HDSPM_MAX_CHANNELS, 5430 .buffer_bytes_max = 5431 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5432 .period_bytes_min = (32 * 4), 5433 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5434 .periods_min = 2, 5435 .periods_max = 512, 5436 .fifo_size = 0 5437 }; 5438 5439 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5440 .info = (SNDRV_PCM_INFO_MMAP | 5441 SNDRV_PCM_INFO_MMAP_VALID | 5442 SNDRV_PCM_INFO_NONINTERLEAVED | 5443 SNDRV_PCM_INFO_SYNC_START), 5444 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5445 .rates = (SNDRV_PCM_RATE_32000 | 5446 SNDRV_PCM_RATE_44100 | 5447 SNDRV_PCM_RATE_48000 | 5448 SNDRV_PCM_RATE_64000 | 5449 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5450 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5451 .rate_min = 32000, 5452 .rate_max = 192000, 5453 .channels_min = 1, 5454 .channels_max = HDSPM_MAX_CHANNELS, 5455 .buffer_bytes_max = 5456 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5457 .period_bytes_min = (32 * 4), 5458 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5459 .periods_min = 2, 5460 .periods_max = 512, 5461 .fifo_size = 0 5462 }; 5463 5464 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5465 struct snd_pcm_hw_rule *rule) 5466 { 5467 struct hdspm *hdspm = rule->private; 5468 struct snd_interval *c = 5469 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5470 struct snd_interval *r = 5471 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5472 5473 if (r->min > 96000 && r->max <= 192000) { 5474 struct snd_interval t = { 5475 .min = hdspm->qs_in_channels, 5476 .max = hdspm->qs_in_channels, 5477 .integer = 1, 5478 }; 5479 return snd_interval_refine(c, &t); 5480 } else if (r->min > 48000 && r->max <= 96000) { 5481 struct snd_interval t = { 5482 .min = hdspm->ds_in_channels, 5483 .max = hdspm->ds_in_channels, 5484 .integer = 1, 5485 }; 5486 return snd_interval_refine(c, &t); 5487 } else if (r->max < 64000) { 5488 struct snd_interval t = { 5489 .min = hdspm->ss_in_channels, 5490 .max = hdspm->ss_in_channels, 5491 .integer = 1, 5492 }; 5493 return snd_interval_refine(c, &t); 5494 } 5495 5496 return 0; 5497 } 5498 5499 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5500 struct snd_pcm_hw_rule * rule) 5501 { 5502 struct hdspm *hdspm = rule->private; 5503 struct snd_interval *c = 5504 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5505 struct snd_interval *r = 5506 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5507 5508 if (r->min > 96000 && r->max <= 192000) { 5509 struct snd_interval t = { 5510 .min = hdspm->qs_out_channels, 5511 .max = hdspm->qs_out_channels, 5512 .integer = 1, 5513 }; 5514 return snd_interval_refine(c, &t); 5515 } else if (r->min > 48000 && r->max <= 96000) { 5516 struct snd_interval t = { 5517 .min = hdspm->ds_out_channels, 5518 .max = hdspm->ds_out_channels, 5519 .integer = 1, 5520 }; 5521 return snd_interval_refine(c, &t); 5522 } else if (r->max < 64000) { 5523 struct snd_interval t = { 5524 .min = hdspm->ss_out_channels, 5525 .max = hdspm->ss_out_channels, 5526 .integer = 1, 5527 }; 5528 return snd_interval_refine(c, &t); 5529 } else { 5530 } 5531 return 0; 5532 } 5533 5534 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5535 struct snd_pcm_hw_rule * rule) 5536 { 5537 struct hdspm *hdspm = rule->private; 5538 struct snd_interval *c = 5539 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5540 struct snd_interval *r = 5541 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5542 5543 if (c->min >= hdspm->ss_in_channels) { 5544 struct snd_interval t = { 5545 .min = 32000, 5546 .max = 48000, 5547 .integer = 1, 5548 }; 5549 return snd_interval_refine(r, &t); 5550 } else if (c->max <= hdspm->qs_in_channels) { 5551 struct snd_interval t = { 5552 .min = 128000, 5553 .max = 192000, 5554 .integer = 1, 5555 }; 5556 return snd_interval_refine(r, &t); 5557 } else if (c->max <= hdspm->ds_in_channels) { 5558 struct snd_interval t = { 5559 .min = 64000, 5560 .max = 96000, 5561 .integer = 1, 5562 }; 5563 return snd_interval_refine(r, &t); 5564 } 5565 5566 return 0; 5567 } 5568 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5569 struct snd_pcm_hw_rule *rule) 5570 { 5571 struct hdspm *hdspm = rule->private; 5572 struct snd_interval *c = 5573 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5574 struct snd_interval *r = 5575 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5576 5577 if (c->min >= hdspm->ss_out_channels) { 5578 struct snd_interval t = { 5579 .min = 32000, 5580 .max = 48000, 5581 .integer = 1, 5582 }; 5583 return snd_interval_refine(r, &t); 5584 } else if (c->max <= hdspm->qs_out_channels) { 5585 struct snd_interval t = { 5586 .min = 128000, 5587 .max = 192000, 5588 .integer = 1, 5589 }; 5590 return snd_interval_refine(r, &t); 5591 } else if (c->max <= hdspm->ds_out_channels) { 5592 struct snd_interval t = { 5593 .min = 64000, 5594 .max = 96000, 5595 .integer = 1, 5596 }; 5597 return snd_interval_refine(r, &t); 5598 } 5599 5600 return 0; 5601 } 5602 5603 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5604 struct snd_pcm_hw_rule *rule) 5605 { 5606 unsigned int list[3]; 5607 struct hdspm *hdspm = rule->private; 5608 struct snd_interval *c = hw_param_interval(params, 5609 SNDRV_PCM_HW_PARAM_CHANNELS); 5610 5611 list[0] = hdspm->qs_in_channels; 5612 list[1] = hdspm->ds_in_channels; 5613 list[2] = hdspm->ss_in_channels; 5614 return snd_interval_list(c, 3, list, 0); 5615 } 5616 5617 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5618 struct snd_pcm_hw_rule *rule) 5619 { 5620 unsigned int list[3]; 5621 struct hdspm *hdspm = rule->private; 5622 struct snd_interval *c = hw_param_interval(params, 5623 SNDRV_PCM_HW_PARAM_CHANNELS); 5624 5625 list[0] = hdspm->qs_out_channels; 5626 list[1] = hdspm->ds_out_channels; 5627 list[2] = hdspm->ss_out_channels; 5628 return snd_interval_list(c, 3, list, 0); 5629 } 5630 5631 5632 static unsigned int hdspm_aes32_sample_rates[] = { 5633 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5634 }; 5635 5636 static struct snd_pcm_hw_constraint_list 5637 hdspm_hw_constraints_aes32_sample_rates = { 5638 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5639 .list = hdspm_aes32_sample_rates, 5640 .mask = 0 5641 }; 5642 5643 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5644 { 5645 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5646 struct snd_pcm_runtime *runtime = substream->runtime; 5647 5648 spin_lock_irq(&hdspm->lock); 5649 5650 snd_pcm_set_sync(substream); 5651 5652 5653 runtime->hw = snd_hdspm_playback_subinfo; 5654 5655 if (hdspm->capture_substream == NULL) 5656 hdspm_stop_audio(hdspm); 5657 5658 hdspm->playback_pid = current->pid; 5659 hdspm->playback_substream = substream; 5660 5661 spin_unlock_irq(&hdspm->lock); 5662 5663 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5664 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5665 5666 switch (hdspm->io_type) { 5667 case AIO: 5668 case RayDAT: 5669 snd_pcm_hw_constraint_minmax(runtime, 5670 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5671 32, 4096); 5672 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 5673 snd_pcm_hw_constraint_minmax(runtime, 5674 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5675 16384, 16384); 5676 break; 5677 5678 default: 5679 snd_pcm_hw_constraint_minmax(runtime, 5680 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5681 64, 8192); 5682 break; 5683 } 5684 5685 if (AES32 == hdspm->io_type) { 5686 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5687 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5688 &hdspm_hw_constraints_aes32_sample_rates); 5689 } else { 5690 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5691 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5692 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5693 } 5694 5695 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5696 snd_hdspm_hw_rule_out_channels, hdspm, 5697 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5698 5699 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5700 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5701 SNDRV_PCM_HW_PARAM_RATE, -1); 5702 5703 return 0; 5704 } 5705 5706 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5707 { 5708 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5709 5710 spin_lock_irq(&hdspm->lock); 5711 5712 hdspm->playback_pid = -1; 5713 hdspm->playback_substream = NULL; 5714 5715 spin_unlock_irq(&hdspm->lock); 5716 5717 return 0; 5718 } 5719 5720 5721 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 5722 { 5723 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5724 struct snd_pcm_runtime *runtime = substream->runtime; 5725 5726 spin_lock_irq(&hdspm->lock); 5727 snd_pcm_set_sync(substream); 5728 runtime->hw = snd_hdspm_capture_subinfo; 5729 5730 if (hdspm->playback_substream == NULL) 5731 hdspm_stop_audio(hdspm); 5732 5733 hdspm->capture_pid = current->pid; 5734 hdspm->capture_substream = substream; 5735 5736 spin_unlock_irq(&hdspm->lock); 5737 5738 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5739 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5740 5741 switch (hdspm->io_type) { 5742 case AIO: 5743 case RayDAT: 5744 snd_pcm_hw_constraint_minmax(runtime, 5745 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5746 32, 4096); 5747 snd_pcm_hw_constraint_minmax(runtime, 5748 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5749 16384, 16384); 5750 break; 5751 5752 default: 5753 snd_pcm_hw_constraint_minmax(runtime, 5754 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5755 64, 8192); 5756 break; 5757 } 5758 5759 if (AES32 == hdspm->io_type) { 5760 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5761 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5762 &hdspm_hw_constraints_aes32_sample_rates); 5763 } else { 5764 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5765 snd_hdspm_hw_rule_rate_in_channels, hdspm, 5766 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5767 } 5768 5769 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5770 snd_hdspm_hw_rule_in_channels, hdspm, 5771 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5772 5773 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5774 snd_hdspm_hw_rule_in_channels_rate, hdspm, 5775 SNDRV_PCM_HW_PARAM_RATE, -1); 5776 5777 return 0; 5778 } 5779 5780 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 5781 { 5782 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5783 5784 spin_lock_irq(&hdspm->lock); 5785 5786 hdspm->capture_pid = -1; 5787 hdspm->capture_substream = NULL; 5788 5789 spin_unlock_irq(&hdspm->lock); 5790 return 0; 5791 } 5792 5793 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 5794 { 5795 /* we have nothing to initialize but the call is required */ 5796 return 0; 5797 } 5798 5799 static inline int copy_u32_le(void __user *dest, void __iomem *src) 5800 { 5801 u32 val = readl(src); 5802 return copy_to_user(dest, &val, 4); 5803 } 5804 5805 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 5806 unsigned int cmd, unsigned long arg) 5807 { 5808 void __user *argp = (void __user *)arg; 5809 struct hdspm *hdspm = hw->private_data; 5810 struct hdspm_mixer_ioctl mixer; 5811 struct hdspm_config info; 5812 struct hdspm_status status; 5813 struct hdspm_version hdspm_version; 5814 struct hdspm_peak_rms *levels; 5815 struct hdspm_ltc ltc; 5816 unsigned int statusregister; 5817 long unsigned int s; 5818 int i = 0; 5819 5820 switch (cmd) { 5821 5822 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 5823 levels = &hdspm->peak_rms; 5824 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 5825 levels->input_peaks[i] = 5826 readl(hdspm->iobase + 5827 HDSPM_MADI_INPUT_PEAK + i*4); 5828 levels->playback_peaks[i] = 5829 readl(hdspm->iobase + 5830 HDSPM_MADI_PLAYBACK_PEAK + i*4); 5831 levels->output_peaks[i] = 5832 readl(hdspm->iobase + 5833 HDSPM_MADI_OUTPUT_PEAK + i*4); 5834 5835 levels->input_rms[i] = 5836 ((uint64_t) readl(hdspm->iobase + 5837 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 5838 (uint64_t) readl(hdspm->iobase + 5839 HDSPM_MADI_INPUT_RMS_L + i*4); 5840 levels->playback_rms[i] = 5841 ((uint64_t)readl(hdspm->iobase + 5842 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 5843 (uint64_t)readl(hdspm->iobase + 5844 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 5845 levels->output_rms[i] = 5846 ((uint64_t)readl(hdspm->iobase + 5847 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 5848 (uint64_t)readl(hdspm->iobase + 5849 HDSPM_MADI_OUTPUT_RMS_L + i*4); 5850 } 5851 5852 if (hdspm->system_sample_rate > 96000) { 5853 levels->speed = qs; 5854 } else if (hdspm->system_sample_rate > 48000) { 5855 levels->speed = ds; 5856 } else { 5857 levels->speed = ss; 5858 } 5859 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 5860 5861 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 5862 if (0 != s) { 5863 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 5864 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 5865 */ 5866 return -EFAULT; 5867 } 5868 break; 5869 5870 case SNDRV_HDSPM_IOCTL_GET_LTC: 5871 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 5872 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 5873 if (i & HDSPM_TCO1_LTC_Input_valid) { 5874 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 5875 HDSPM_TCO1_LTC_Format_MSB)) { 5876 case 0: 5877 ltc.format = fps_24; 5878 break; 5879 case HDSPM_TCO1_LTC_Format_LSB: 5880 ltc.format = fps_25; 5881 break; 5882 case HDSPM_TCO1_LTC_Format_MSB: 5883 ltc.format = fps_2997; 5884 break; 5885 default: 5886 ltc.format = 30; 5887 break; 5888 } 5889 if (i & HDSPM_TCO1_set_drop_frame_flag) { 5890 ltc.frame = drop_frame; 5891 } else { 5892 ltc.frame = full_frame; 5893 } 5894 } else { 5895 ltc.format = format_invalid; 5896 ltc.frame = frame_invalid; 5897 } 5898 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 5899 ltc.input_format = ntsc; 5900 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 5901 ltc.input_format = pal; 5902 } else { 5903 ltc.input_format = no_video; 5904 } 5905 5906 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 5907 if (0 != s) { 5908 /* 5909 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 5910 return -EFAULT; 5911 } 5912 5913 break; 5914 5915 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 5916 5917 memset(&info, 0, sizeof(info)); 5918 spin_lock_irq(&hdspm->lock); 5919 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 5920 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 5921 5922 info.system_sample_rate = hdspm->system_sample_rate; 5923 info.autosync_sample_rate = 5924 hdspm_external_sample_rate(hdspm); 5925 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 5926 info.clock_source = hdspm_clock_source(hdspm); 5927 info.autosync_ref = hdspm_autosync_ref(hdspm); 5928 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 5929 info.passthru = 0; 5930 spin_unlock_irq(&hdspm->lock); 5931 if (copy_to_user(argp, &info, sizeof(info))) 5932 return -EFAULT; 5933 break; 5934 5935 case SNDRV_HDSPM_IOCTL_GET_STATUS: 5936 memset(&status, 0, sizeof(status)); 5937 5938 status.card_type = hdspm->io_type; 5939 5940 status.autosync_source = hdspm_autosync_ref(hdspm); 5941 5942 status.card_clock = 110069313433624ULL; 5943 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 5944 5945 switch (hdspm->io_type) { 5946 case MADI: 5947 case MADIface: 5948 status.card_specific.madi.sync_wc = 5949 hdspm_wc_sync_check(hdspm); 5950 status.card_specific.madi.sync_madi = 5951 hdspm_madi_sync_check(hdspm); 5952 status.card_specific.madi.sync_tco = 5953 hdspm_tco_sync_check(hdspm); 5954 status.card_specific.madi.sync_in = 5955 hdspm_sync_in_sync_check(hdspm); 5956 5957 statusregister = 5958 hdspm_read(hdspm, HDSPM_statusRegister); 5959 status.card_specific.madi.madi_input = 5960 (statusregister & HDSPM_AB_int) ? 1 : 0; 5961 status.card_specific.madi.channel_format = 5962 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 5963 /* TODO: Mac driver sets it when f_s>48kHz */ 5964 status.card_specific.madi.frame_format = 0; 5965 5966 default: 5967 break; 5968 } 5969 5970 if (copy_to_user(argp, &status, sizeof(status))) 5971 return -EFAULT; 5972 5973 5974 break; 5975 5976 case SNDRV_HDSPM_IOCTL_GET_VERSION: 5977 memset(&hdspm_version, 0, sizeof(hdspm_version)); 5978 5979 hdspm_version.card_type = hdspm->io_type; 5980 strncpy(hdspm_version.cardname, hdspm->card_name, 5981 sizeof(hdspm_version.cardname)); 5982 hdspm_version.serial = hdspm->serial; 5983 hdspm_version.firmware_rev = hdspm->firmware_rev; 5984 hdspm_version.addons = 0; 5985 if (hdspm->tco) 5986 hdspm_version.addons |= HDSPM_ADDON_TCO; 5987 5988 if (copy_to_user(argp, &hdspm_version, 5989 sizeof(hdspm_version))) 5990 return -EFAULT; 5991 break; 5992 5993 case SNDRV_HDSPM_IOCTL_GET_MIXER: 5994 if (copy_from_user(&mixer, argp, sizeof(mixer))) 5995 return -EFAULT; 5996 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 5997 sizeof(struct hdspm_mixer))) 5998 return -EFAULT; 5999 break; 6000 6001 default: 6002 return -EINVAL; 6003 } 6004 return 0; 6005 } 6006 6007 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6008 .open = snd_hdspm_playback_open, 6009 .close = snd_hdspm_playback_release, 6010 .ioctl = snd_hdspm_ioctl, 6011 .hw_params = snd_hdspm_hw_params, 6012 .hw_free = snd_hdspm_hw_free, 6013 .prepare = snd_hdspm_prepare, 6014 .trigger = snd_hdspm_trigger, 6015 .pointer = snd_hdspm_hw_pointer, 6016 .page = snd_pcm_sgbuf_ops_page, 6017 }; 6018 6019 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6020 .open = snd_hdspm_capture_open, 6021 .close = snd_hdspm_capture_release, 6022 .ioctl = snd_hdspm_ioctl, 6023 .hw_params = snd_hdspm_hw_params, 6024 .hw_free = snd_hdspm_hw_free, 6025 .prepare = snd_hdspm_prepare, 6026 .trigger = snd_hdspm_trigger, 6027 .pointer = snd_hdspm_hw_pointer, 6028 .page = snd_pcm_sgbuf_ops_page, 6029 }; 6030 6031 static int snd_hdspm_create_hwdep(struct snd_card *card, 6032 struct hdspm *hdspm) 6033 { 6034 struct snd_hwdep *hw; 6035 int err; 6036 6037 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6038 if (err < 0) 6039 return err; 6040 6041 hdspm->hwdep = hw; 6042 hw->private_data = hdspm; 6043 strcpy(hw->name, "HDSPM hwdep interface"); 6044 6045 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6046 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6047 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6048 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6049 6050 return 0; 6051 } 6052 6053 6054 /*------------------------------------------------------------ 6055 memory interface 6056 ------------------------------------------------------------*/ 6057 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6058 { 6059 int err; 6060 struct snd_pcm *pcm; 6061 size_t wanted; 6062 6063 pcm = hdspm->pcm; 6064 6065 wanted = HDSPM_DMA_AREA_BYTES; 6066 6067 err = 6068 snd_pcm_lib_preallocate_pages_for_all(pcm, 6069 SNDRV_DMA_TYPE_DEV_SG, 6070 snd_dma_pci_data(hdspm->pci), 6071 wanted, 6072 wanted); 6073 if (err < 0) { 6074 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6075 6076 return err; 6077 } else 6078 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6079 6080 return 0; 6081 } 6082 6083 6084 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6085 struct snd_pcm_substream *substream, 6086 unsigned int reg, int channels) 6087 { 6088 int i; 6089 6090 /* continuous memory segment */ 6091 for (i = 0; i < (channels * 16); i++) 6092 hdspm_write(hdspm, reg + 4 * i, 6093 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6094 } 6095 6096 6097 /* ------------- ALSA Devices ---------------------------- */ 6098 static int snd_hdspm_create_pcm(struct snd_card *card, 6099 struct hdspm *hdspm) 6100 { 6101 struct snd_pcm *pcm; 6102 int err; 6103 6104 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6105 if (err < 0) 6106 return err; 6107 6108 hdspm->pcm = pcm; 6109 pcm->private_data = hdspm; 6110 strcpy(pcm->name, hdspm->card_name); 6111 6112 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6113 &snd_hdspm_playback_ops); 6114 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6115 &snd_hdspm_capture_ops); 6116 6117 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6118 6119 err = snd_hdspm_preallocate_memory(hdspm); 6120 if (err < 0) 6121 return err; 6122 6123 return 0; 6124 } 6125 6126 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6127 { 6128 int i; 6129 6130 for (i = 0; i < hdspm->midiPorts; i++) 6131 snd_hdspm_flush_midi_input(hdspm, i); 6132 } 6133 6134 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6135 struct hdspm *hdspm) 6136 { 6137 int err, i; 6138 6139 snd_printdd("Create card...\n"); 6140 err = snd_hdspm_create_pcm(card, hdspm); 6141 if (err < 0) 6142 return err; 6143 6144 i = 0; 6145 while (i < hdspm->midiPorts) { 6146 err = snd_hdspm_create_midi(card, hdspm, i); 6147 if (err < 0) { 6148 return err; 6149 } 6150 i++; 6151 } 6152 6153 err = snd_hdspm_create_controls(card, hdspm); 6154 if (err < 0) 6155 return err; 6156 6157 err = snd_hdspm_create_hwdep(card, hdspm); 6158 if (err < 0) 6159 return err; 6160 6161 snd_printdd("proc init...\n"); 6162 snd_hdspm_proc_init(hdspm); 6163 6164 hdspm->system_sample_rate = -1; 6165 hdspm->last_external_sample_rate = -1; 6166 hdspm->last_internal_sample_rate = -1; 6167 hdspm->playback_pid = -1; 6168 hdspm->capture_pid = -1; 6169 hdspm->capture_substream = NULL; 6170 hdspm->playback_substream = NULL; 6171 6172 snd_printdd("Set defaults...\n"); 6173 err = snd_hdspm_set_defaults(hdspm); 6174 if (err < 0) 6175 return err; 6176 6177 snd_printdd("Update mixer controls...\n"); 6178 hdspm_update_simple_mixer_controls(hdspm); 6179 6180 snd_printdd("Initializeing complete ???\n"); 6181 6182 err = snd_card_register(card); 6183 if (err < 0) { 6184 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6185 return err; 6186 } 6187 6188 snd_printdd("... yes now\n"); 6189 6190 return 0; 6191 } 6192 6193 static int snd_hdspm_create(struct snd_card *card, 6194 struct hdspm *hdspm) 6195 { 6196 6197 struct pci_dev *pci = hdspm->pci; 6198 int err; 6199 unsigned long io_extent; 6200 6201 hdspm->irq = -1; 6202 hdspm->card = card; 6203 6204 spin_lock_init(&hdspm->lock); 6205 6206 pci_read_config_word(hdspm->pci, 6207 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6208 6209 strcpy(card->mixername, "Xilinx FPGA"); 6210 strcpy(card->driver, "HDSPM"); 6211 6212 switch (hdspm->firmware_rev) { 6213 case HDSPM_RAYDAT_REV: 6214 hdspm->io_type = RayDAT; 6215 hdspm->card_name = "RME RayDAT"; 6216 hdspm->midiPorts = 2; 6217 break; 6218 case HDSPM_AIO_REV: 6219 hdspm->io_type = AIO; 6220 hdspm->card_name = "RME AIO"; 6221 hdspm->midiPorts = 1; 6222 break; 6223 case HDSPM_MADIFACE_REV: 6224 hdspm->io_type = MADIface; 6225 hdspm->card_name = "RME MADIface"; 6226 hdspm->midiPorts = 1; 6227 break; 6228 default: 6229 if ((hdspm->firmware_rev == 0xf0) || 6230 ((hdspm->firmware_rev >= 0xe6) && 6231 (hdspm->firmware_rev <= 0xea))) { 6232 hdspm->io_type = AES32; 6233 hdspm->card_name = "RME AES32"; 6234 hdspm->midiPorts = 2; 6235 } else if ((hdspm->firmware_rev == 0xd2) || 6236 ((hdspm->firmware_rev >= 0xc8) && 6237 (hdspm->firmware_rev <= 0xcf))) { 6238 hdspm->io_type = MADI; 6239 hdspm->card_name = "RME MADI"; 6240 hdspm->midiPorts = 3; 6241 } else { 6242 snd_printk(KERN_ERR 6243 "HDSPM: unknown firmware revision %x\n", 6244 hdspm->firmware_rev); 6245 return -ENODEV; 6246 } 6247 } 6248 6249 err = pci_enable_device(pci); 6250 if (err < 0) 6251 return err; 6252 6253 pci_set_master(hdspm->pci); 6254 6255 err = pci_request_regions(pci, "hdspm"); 6256 if (err < 0) 6257 return err; 6258 6259 hdspm->port = pci_resource_start(pci, 0); 6260 io_extent = pci_resource_len(pci, 0); 6261 6262 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6263 hdspm->port, hdspm->port + io_extent - 1); 6264 6265 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6266 if (!hdspm->iobase) { 6267 snd_printk(KERN_ERR "HDSPM: " 6268 "unable to remap region 0x%lx-0x%lx\n", 6269 hdspm->port, hdspm->port + io_extent - 1); 6270 return -EBUSY; 6271 } 6272 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6273 (unsigned long)hdspm->iobase, hdspm->port, 6274 hdspm->port + io_extent - 1); 6275 6276 if (request_irq(pci->irq, snd_hdspm_interrupt, 6277 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6278 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6279 return -EBUSY; 6280 } 6281 6282 snd_printdd("use IRQ %d\n", pci->irq); 6283 6284 hdspm->irq = pci->irq; 6285 6286 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6287 sizeof(struct hdspm_mixer)); 6288 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6289 if (!hdspm->mixer) { 6290 snd_printk(KERN_ERR "HDSPM: " 6291 "unable to kmalloc Mixer memory of %d Bytes\n", 6292 (int)sizeof(struct hdspm_mixer)); 6293 return -ENOMEM; 6294 } 6295 6296 hdspm->port_names_in = NULL; 6297 hdspm->port_names_out = NULL; 6298 6299 switch (hdspm->io_type) { 6300 case AES32: 6301 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6302 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6303 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6304 6305 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6306 channel_map_aes32; 6307 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6308 channel_map_aes32; 6309 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6310 channel_map_aes32; 6311 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6312 texts_ports_aes32; 6313 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6314 texts_ports_aes32; 6315 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6316 texts_ports_aes32; 6317 6318 hdspm->max_channels_out = hdspm->max_channels_in = 6319 AES32_CHANNELS; 6320 hdspm->port_names_in = hdspm->port_names_out = 6321 texts_ports_aes32; 6322 hdspm->channel_map_in = hdspm->channel_map_out = 6323 channel_map_aes32; 6324 6325 break; 6326 6327 case MADI: 6328 case MADIface: 6329 hdspm->ss_in_channels = hdspm->ss_out_channels = 6330 MADI_SS_CHANNELS; 6331 hdspm->ds_in_channels = hdspm->ds_out_channels = 6332 MADI_DS_CHANNELS; 6333 hdspm->qs_in_channels = hdspm->qs_out_channels = 6334 MADI_QS_CHANNELS; 6335 6336 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6337 channel_map_unity_ss; 6338 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6339 channel_map_unity_ss; 6340 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6341 channel_map_unity_ss; 6342 6343 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6344 texts_ports_madi; 6345 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6346 texts_ports_madi; 6347 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6348 texts_ports_madi; 6349 break; 6350 6351 case AIO: 6352 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6353 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6354 } 6355 6356 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6357 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6358 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6359 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6360 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6361 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6362 6363 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6364 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6365 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6366 6367 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6368 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6369 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6370 6371 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6372 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6373 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6374 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6375 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6376 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6377 6378 break; 6379 6380 case RayDAT: 6381 hdspm->ss_in_channels = hdspm->ss_out_channels = 6382 RAYDAT_SS_CHANNELS; 6383 hdspm->ds_in_channels = hdspm->ds_out_channels = 6384 RAYDAT_DS_CHANNELS; 6385 hdspm->qs_in_channels = hdspm->qs_out_channels = 6386 RAYDAT_QS_CHANNELS; 6387 6388 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6389 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6390 6391 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6392 channel_map_raydat_ss; 6393 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6394 channel_map_raydat_ds; 6395 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6396 channel_map_raydat_qs; 6397 hdspm->channel_map_in = hdspm->channel_map_out = 6398 channel_map_raydat_ss; 6399 6400 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6401 texts_ports_raydat_ss; 6402 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6403 texts_ports_raydat_ds; 6404 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6405 texts_ports_raydat_qs; 6406 6407 6408 break; 6409 6410 } 6411 6412 /* TCO detection */ 6413 switch (hdspm->io_type) { 6414 case AIO: 6415 case RayDAT: 6416 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6417 HDSPM_s2_tco_detect) { 6418 hdspm->midiPorts++; 6419 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6420 GFP_KERNEL); 6421 if (NULL != hdspm->tco) { 6422 hdspm_tco_write(hdspm); 6423 } 6424 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6425 } else { 6426 hdspm->tco = NULL; 6427 } 6428 break; 6429 6430 case MADI: 6431 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6432 hdspm->midiPorts++; 6433 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6434 GFP_KERNEL); 6435 if (NULL != hdspm->tco) { 6436 hdspm_tco_write(hdspm); 6437 } 6438 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6439 } else { 6440 hdspm->tco = NULL; 6441 } 6442 break; 6443 6444 default: 6445 hdspm->tco = NULL; 6446 } 6447 6448 /* texts */ 6449 switch (hdspm->io_type) { 6450 case AES32: 6451 if (hdspm->tco) { 6452 hdspm->texts_autosync = texts_autosync_aes_tco; 6453 hdspm->texts_autosync_items = 10; 6454 } else { 6455 hdspm->texts_autosync = texts_autosync_aes; 6456 hdspm->texts_autosync_items = 9; 6457 } 6458 break; 6459 6460 case MADI: 6461 if (hdspm->tco) { 6462 hdspm->texts_autosync = texts_autosync_madi_tco; 6463 hdspm->texts_autosync_items = 4; 6464 } else { 6465 hdspm->texts_autosync = texts_autosync_madi; 6466 hdspm->texts_autosync_items = 3; 6467 } 6468 break; 6469 6470 case MADIface: 6471 6472 break; 6473 6474 case RayDAT: 6475 if (hdspm->tco) { 6476 hdspm->texts_autosync = texts_autosync_raydat_tco; 6477 hdspm->texts_autosync_items = 9; 6478 } else { 6479 hdspm->texts_autosync = texts_autosync_raydat; 6480 hdspm->texts_autosync_items = 8; 6481 } 6482 break; 6483 6484 case AIO: 6485 if (hdspm->tco) { 6486 hdspm->texts_autosync = texts_autosync_aio_tco; 6487 hdspm->texts_autosync_items = 6; 6488 } else { 6489 hdspm->texts_autosync = texts_autosync_aio; 6490 hdspm->texts_autosync_items = 5; 6491 } 6492 break; 6493 6494 } 6495 6496 tasklet_init(&hdspm->midi_tasklet, 6497 hdspm_midi_tasklet, (unsigned long) hdspm); 6498 6499 6500 if (hdspm->io_type != MADIface) { 6501 hdspm->serial = (hdspm_read(hdspm, 6502 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6503 /* id contains either a user-provided value or the default 6504 * NULL. If it's the default, we're safe to 6505 * fill card->id with the serial number. 6506 * 6507 * If the serial number is 0xFFFFFF, then we're dealing with 6508 * an old PCI revision that comes without a sane number. In 6509 * this case, we don't set card->id to avoid collisions 6510 * when running with multiple cards. 6511 */ 6512 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6513 sprintf(card->id, "HDSPMx%06x", hdspm->serial); 6514 snd_card_set_id(card, card->id); 6515 } 6516 } 6517 6518 snd_printdd("create alsa devices.\n"); 6519 err = snd_hdspm_create_alsa_devices(card, hdspm); 6520 if (err < 0) 6521 return err; 6522 6523 snd_hdspm_initialize_midi_flush(hdspm); 6524 6525 return 0; 6526 } 6527 6528 6529 static int snd_hdspm_free(struct hdspm * hdspm) 6530 { 6531 6532 if (hdspm->port) { 6533 6534 /* stop th audio, and cancel all interrupts */ 6535 hdspm->control_register &= 6536 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6537 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6538 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6539 hdspm_write(hdspm, HDSPM_controlRegister, 6540 hdspm->control_register); 6541 } 6542 6543 if (hdspm->irq >= 0) 6544 free_irq(hdspm->irq, (void *) hdspm); 6545 6546 kfree(hdspm->mixer); 6547 6548 if (hdspm->iobase) 6549 iounmap(hdspm->iobase); 6550 6551 if (hdspm->port) 6552 pci_release_regions(hdspm->pci); 6553 6554 pci_disable_device(hdspm->pci); 6555 return 0; 6556 } 6557 6558 6559 static void snd_hdspm_card_free(struct snd_card *card) 6560 { 6561 struct hdspm *hdspm = card->private_data; 6562 6563 if (hdspm) 6564 snd_hdspm_free(hdspm); 6565 } 6566 6567 6568 static int snd_hdspm_probe(struct pci_dev *pci, 6569 const struct pci_device_id *pci_id) 6570 { 6571 static int dev; 6572 struct hdspm *hdspm; 6573 struct snd_card *card; 6574 int err; 6575 6576 if (dev >= SNDRV_CARDS) 6577 return -ENODEV; 6578 if (!enable[dev]) { 6579 dev++; 6580 return -ENOENT; 6581 } 6582 6583 err = snd_card_create(index[dev], id[dev], 6584 THIS_MODULE, sizeof(struct hdspm), &card); 6585 if (err < 0) 6586 return err; 6587 6588 hdspm = card->private_data; 6589 card->private_free = snd_hdspm_card_free; 6590 hdspm->dev = dev; 6591 hdspm->pci = pci; 6592 6593 snd_card_set_dev(card, &pci->dev); 6594 6595 err = snd_hdspm_create(card, hdspm); 6596 if (err < 0) { 6597 snd_card_free(card); 6598 return err; 6599 } 6600 6601 if (hdspm->io_type != MADIface) { 6602 sprintf(card->shortname, "%s_%x", 6603 hdspm->card_name, 6604 hdspm->serial); 6605 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6606 hdspm->card_name, 6607 hdspm->serial, 6608 hdspm->port, hdspm->irq); 6609 } else { 6610 sprintf(card->shortname, "%s", hdspm->card_name); 6611 sprintf(card->longname, "%s at 0x%lx, irq %d", 6612 hdspm->card_name, hdspm->port, hdspm->irq); 6613 } 6614 6615 err = snd_card_register(card); 6616 if (err < 0) { 6617 snd_card_free(card); 6618 return err; 6619 } 6620 6621 pci_set_drvdata(pci, card); 6622 6623 dev++; 6624 return 0; 6625 } 6626 6627 static void snd_hdspm_remove(struct pci_dev *pci) 6628 { 6629 snd_card_free(pci_get_drvdata(pci)); 6630 pci_set_drvdata(pci, NULL); 6631 } 6632 6633 static struct pci_driver hdspm_driver = { 6634 .name = KBUILD_MODNAME, 6635 .id_table = snd_hdspm_ids, 6636 .probe = snd_hdspm_probe, 6637 .remove = snd_hdspm_remove, 6638 }; 6639 6640 module_pci_driver(hdspm_driver); 6641