1 /* 2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s) 3 * 4 * Copyright (c) 2003 Winfried Ritsch (IEM) 5 * code based on hdsp.c Paul Davis 6 * Marcus Andersson 7 * Thomas Charbonnel 8 * Modified 2006-06-01 for AES32 support by Remy Bruno 9 * <remy.bruno@trinnov.com> 10 * 11 * Modified 2009-04-13 for proper metering by Florian Faber 12 * <faber@faberman.de> 13 * 14 * Modified 2009-04-14 for native float support by Florian Faber 15 * <faber@faberman.de> 16 * 17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber 18 * <faber@faberman.de> 19 * 20 * Modified 2009-04-30 added hw serial number support by Florian Faber 21 * 22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth 23 * 24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth 25 * 26 * This program is free software; you can redistribute it and/or modify 27 * it under the terms of the GNU General Public License as published by 28 * the Free Software Foundation; either version 2 of the License, or 29 * (at your option) any later version. 30 * 31 * This program is distributed in the hope that it will be useful, 32 * but WITHOUT ANY WARRANTY; without even the implied warranty of 33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 34 * GNU General Public License for more details. 35 * 36 * You should have received a copy of the GNU General Public License 37 * along with this program; if not, write to the Free Software 38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 39 * 40 */ 41 #include <linux/init.h> 42 #include <linux/delay.h> 43 #include <linux/interrupt.h> 44 #include <linux/module.h> 45 #include <linux/slab.h> 46 #include <linux/pci.h> 47 #include <linux/math64.h> 48 #include <asm/io.h> 49 50 #include <sound/core.h> 51 #include <sound/control.h> 52 #include <sound/pcm.h> 53 #include <sound/pcm_params.h> 54 #include <sound/info.h> 55 #include <sound/asoundef.h> 56 #include <sound/rawmidi.h> 57 #include <sound/hwdep.h> 58 #include <sound/initval.h> 59 60 #include <sound/hdspm.h> 61 62 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 63 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 64 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 65 66 module_param_array(index, int, NULL, 0444); 67 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface."); 68 69 module_param_array(id, charp, NULL, 0444); 70 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface."); 71 72 module_param_array(enable, bool, NULL, 0444); 73 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards."); 74 75 76 MODULE_AUTHOR 77 ( 78 "Winfried Ritsch <ritsch_AT_iem.at>, " 79 "Paul Davis <paul@linuxaudiosystems.com>, " 80 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, " 81 "Remy Bruno <remy.bruno@trinnov.com>, " 82 "Florian Faber <faberman@linuxproaudio.org>, " 83 "Adrian Knoth <adi@drcomp.erfurt.thur.de>" 84 ); 85 MODULE_DESCRIPTION("RME HDSPM"); 86 MODULE_LICENSE("GPL"); 87 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}"); 88 89 /* --- Write registers. --- 90 These are defined as byte-offsets from the iobase value. */ 91 92 #define HDSPM_WR_SETTINGS 0 93 #define HDSPM_outputBufferAddress 32 94 #define HDSPM_inputBufferAddress 36 95 #define HDSPM_controlRegister 64 96 #define HDSPM_interruptConfirmation 96 97 #define HDSPM_control2Reg 256 /* not in specs ???????? */ 98 #define HDSPM_freqReg 256 /* for AES32 */ 99 #define HDSPM_midiDataOut0 352 /* just believe in old code */ 100 #define HDSPM_midiDataOut1 356 101 #define HDSPM_eeprom_wr 384 /* for AES32 */ 102 103 /* DMA enable for 64 channels, only Bit 0 is relevant */ 104 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */ 105 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */ 106 107 /* 16 page addresses for each of the 64 channels DMA buffer in and out 108 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */ 109 #define HDSPM_pageAddressBufferOut 8192 110 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4) 111 112 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */ 113 114 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */ 115 116 /* --- Read registers. --- 117 These are defined as byte-offsets from the iobase value */ 118 #define HDSPM_statusRegister 0 119 /*#define HDSPM_statusRegister2 96 */ 120 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at 121 * offset 192, for AES32 *and* MADI 122 * => need to check that offset 192 is working on MADI */ 123 #define HDSPM_statusRegister2 192 124 #define HDSPM_timecodeRegister 128 125 126 /* AIO, RayDAT */ 127 #define HDSPM_RD_STATUS_0 0 128 #define HDSPM_RD_STATUS_1 64 129 #define HDSPM_RD_STATUS_2 128 130 #define HDSPM_RD_STATUS_3 192 131 132 #define HDSPM_RD_TCO 256 133 #define HDSPM_RD_PLL_FREQ 512 134 #define HDSPM_WR_TCO 128 135 136 #define HDSPM_TCO1_TCO_lock 0x00000001 137 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002 138 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004 139 #define HDSPM_TCO1_LTC_Input_valid 0x00000008 140 #define HDSPM_TCO1_WCK_Input_valid 0x00000010 141 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020 142 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040 143 144 #define HDSPM_TCO1_set_TC 0x00000100 145 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200 146 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400 147 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800 148 149 #define HDSPM_TCO2_TC_run 0x00010000 150 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000 151 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000 152 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000 153 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000 154 #define HDSPM_TCO2_set_jam_sync 0x00200000 155 #define HDSPM_TCO2_set_flywheel 0x00400000 156 157 #define HDSPM_TCO2_set_01_4 0x01000000 158 #define HDSPM_TCO2_set_pull_down 0x02000000 159 #define HDSPM_TCO2_set_pull_up 0x04000000 160 #define HDSPM_TCO2_set_freq 0x08000000 161 #define HDSPM_TCO2_set_term_75R 0x10000000 162 #define HDSPM_TCO2_set_input_LSB 0x20000000 163 #define HDSPM_TCO2_set_input_MSB 0x40000000 164 #define HDSPM_TCO2_set_freq_from_app 0x80000000 165 166 167 #define HDSPM_midiDataOut0 352 168 #define HDSPM_midiDataOut1 356 169 #define HDSPM_midiDataOut2 368 170 171 #define HDSPM_midiDataIn0 360 172 #define HDSPM_midiDataIn1 364 173 #define HDSPM_midiDataIn2 372 174 #define HDSPM_midiDataIn3 376 175 176 /* status is data bytes in MIDI-FIFO (0-128) */ 177 #define HDSPM_midiStatusOut0 384 178 #define HDSPM_midiStatusOut1 388 179 #define HDSPM_midiStatusOut2 400 180 181 #define HDSPM_midiStatusIn0 392 182 #define HDSPM_midiStatusIn1 396 183 #define HDSPM_midiStatusIn2 404 184 #define HDSPM_midiStatusIn3 408 185 186 187 /* the meters are regular i/o-mapped registers, but offset 188 considerably from the rest. the peak registers are reset 189 when read; the least-significant 4 bits are full-scale counters; 190 the actual peak value is in the most-significant 24 bits. 191 */ 192 193 #define HDSPM_MADI_INPUT_PEAK 4096 194 #define HDSPM_MADI_PLAYBACK_PEAK 4352 195 #define HDSPM_MADI_OUTPUT_PEAK 4608 196 197 #define HDSPM_MADI_INPUT_RMS_L 6144 198 #define HDSPM_MADI_PLAYBACK_RMS_L 6400 199 #define HDSPM_MADI_OUTPUT_RMS_L 6656 200 201 #define HDSPM_MADI_INPUT_RMS_H 7168 202 #define HDSPM_MADI_PLAYBACK_RMS_H 7424 203 #define HDSPM_MADI_OUTPUT_RMS_H 7680 204 205 /* --- Control Register bits --------- */ 206 #define HDSPM_Start (1<<0) /* start engine */ 207 208 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */ 209 #define HDSPM_Latency1 (1<<2) /* where n is defined */ 210 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */ 211 212 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */ 213 #define HDSPM_c0Master 0x1 /* Master clock bit in settings 214 register [RayDAT, AIO] */ 215 216 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */ 217 218 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */ 219 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */ 220 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 221 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */ 222 223 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */ 224 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1, 225 56channelMODE=0 */ /* MADI ONLY*/ 226 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */ 227 228 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode, 229 0=off, 1=on */ /* MADI ONLY */ 230 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */ 231 232 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax 233 * -- MADI ONLY 234 */ 235 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */ 236 237 #define HDSPM_SyncRef2 (1<<13) 238 #define HDSPM_SyncRef3 (1<<25) 239 240 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */ 241 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use 242 AES additional bits in 243 lower 5 Audiodatabits ??? */ 244 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */ 245 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */ 246 247 #define HDSPM_Midi0InterruptEnable 0x0400000 248 #define HDSPM_Midi1InterruptEnable 0x0800000 249 #define HDSPM_Midi2InterruptEnable 0x0200000 250 #define HDSPM_Midi3InterruptEnable 0x4000000 251 252 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */ 253 #define HDSPe_FLOAT_FORMAT 0x2000000 254 255 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */ 256 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */ 257 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */ 258 259 #define HDSPM_wclk_sel (1<<30) 260 261 /* --- bit helper defines */ 262 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2) 263 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\ 264 HDSPM_DoubleSpeed|HDSPM_QuadSpeed) 265 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1) 266 #define HDSPM_InputOptical 0 267 #define HDSPM_InputCoaxial (HDSPM_InputSelect0) 268 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\ 269 HDSPM_SyncRef2|HDSPM_SyncRef3) 270 271 #define HDSPM_c0_SyncRef0 0x2 272 #define HDSPM_c0_SyncRef1 0x4 273 #define HDSPM_c0_SyncRef2 0x8 274 #define HDSPM_c0_SyncRef3 0x10 275 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\ 276 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3) 277 278 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */ 279 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */ 280 #define HDSPM_SYNC_FROM_TCO 2 281 #define HDSPM_SYNC_FROM_SYNC_IN 3 282 283 #define HDSPM_Frequency32KHz HDSPM_Frequency0 284 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1 285 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0) 286 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0) 287 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1) 288 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\ 289 HDSPM_Frequency0) 290 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0) 291 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1) 292 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\ 293 HDSPM_Frequency0) 294 295 296 /* Synccheck Status */ 297 #define HDSPM_SYNC_CHECK_NO_LOCK 0 298 #define HDSPM_SYNC_CHECK_LOCK 1 299 #define HDSPM_SYNC_CHECK_SYNC 2 300 301 /* AutoSync References - used by "autosync_ref" control switch */ 302 #define HDSPM_AUTOSYNC_FROM_WORD 0 303 #define HDSPM_AUTOSYNC_FROM_MADI 1 304 #define HDSPM_AUTOSYNC_FROM_TCO 2 305 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3 306 #define HDSPM_AUTOSYNC_FROM_NONE 4 307 308 /* Possible sources of MADI input */ 309 #define HDSPM_OPTICAL 0 /* optical */ 310 #define HDSPM_COAXIAL 1 /* BNC */ 311 312 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask) 313 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1)) 314 315 #define hdspm_encode_in(x) (((x)&0x3)<<14) 316 #define hdspm_decode_in(x) (((x)>>14)&0x3) 317 318 /* --- control2 register bits --- */ 319 #define HDSPM_TMS (1<<0) 320 #define HDSPM_TCK (1<<1) 321 #define HDSPM_TDI (1<<2) 322 #define HDSPM_JTAG (1<<3) 323 #define HDSPM_PWDN (1<<4) 324 #define HDSPM_PROGRAM (1<<5) 325 #define HDSPM_CONFIG_MODE_0 (1<<6) 326 #define HDSPM_CONFIG_MODE_1 (1<<7) 327 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/ 328 #define HDSPM_BIGENDIAN_MODE (1<<9) 329 #define HDSPM_RD_MULTIPLE (1<<10) 330 331 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and 332 that do not conflict with specific bits for AES32 seem to be valid also 333 for the AES32 334 */ 335 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */ 336 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */ 337 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1 338 * (like inp0) 339 */ 340 341 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */ 342 #define HDSPM_madiSync (1<<18) /* MADI is in sync */ 343 344 #define HDSPM_tcoLock 0x00000020 /* Optional TCO locked status FOR HDSPe MADI! */ 345 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status */ 346 347 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status FOR HDSPe MADI! */ 348 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status FOR HDSPe MADI! */ 349 350 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 351 /* since 64byte accurate, last 6 bits are not used */ 352 353 354 355 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */ 356 357 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */ 358 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */ 359 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */ 360 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */ 361 362 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with 363 * Interrupt 364 */ 365 #define HDSPM_tco_detect 0x08000000 366 #define HDSPM_tco_lock 0x20000000 367 368 #define HDSPM_s2_tco_detect 0x00000040 369 #define HDSPM_s2_AEBO_D 0x00000080 370 #define HDSPM_s2_AEBI_D 0x00000100 371 372 373 #define HDSPM_midi0IRQPending 0x40000000 374 #define HDSPM_midi1IRQPending 0x80000000 375 #define HDSPM_midi2IRQPending 0x20000000 376 #define HDSPM_midi2IRQPendingAES 0x00000020 377 #define HDSPM_midi3IRQPending 0x00200000 378 379 /* --- status bit helpers */ 380 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\ 381 HDSPM_madiFreq2|HDSPM_madiFreq3) 382 #define HDSPM_madiFreq32 (HDSPM_madiFreq0) 383 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1) 384 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1) 385 #define HDSPM_madiFreq64 (HDSPM_madiFreq2) 386 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2) 387 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2) 388 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2) 389 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3) 390 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0) 391 392 /* Status2 Register bits */ /* MADI ONLY */ 393 394 #define HDSPM_version0 (1<<0) /* not really defined but I guess */ 395 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */ 396 #define HDSPM_version2 (1<<2) 397 398 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */ 399 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */ 400 401 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */ 402 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */ 403 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, */ 404 /* missing Bit for 111=128, 1000=176.4, 1001=192 */ 405 406 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */ 407 #define HDSPM_SyncRef1 0x20000 408 409 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */ 410 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */ 411 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */ 412 413 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync) 414 415 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2) 416 #define HDSPM_wcFreq32 (HDSPM_wc_freq0) 417 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1) 418 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1) 419 #define HDSPM_wcFreq64 (HDSPM_wc_freq2) 420 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2) 421 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2) 422 423 #define HDSPM_status1_F_0 0x0400000 424 #define HDSPM_status1_F_1 0x0800000 425 #define HDSPM_status1_F_2 0x1000000 426 #define HDSPM_status1_F_3 0x2000000 427 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3) 428 429 430 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 431 HDSPM_SelSyncRef2) 432 #define HDSPM_SelSyncRef_WORD 0 433 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0) 434 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1) 435 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1) 436 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\ 437 HDSPM_SelSyncRef2) 438 439 /* 440 For AES32, bits for status, status2 and timecode are different 441 */ 442 /* status */ 443 #define HDSPM_AES32_wcLock 0x0200000 444 #define HDSPM_AES32_wcFreq_bit 22 445 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function 446 HDSPM_bit2freq */ 447 #define HDSPM_AES32_syncref_bit 16 448 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */ 449 450 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0 451 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1 452 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2 453 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3 454 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4 455 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5 456 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6 457 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7 458 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8 459 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 9 460 461 /* status2 */ 462 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */ 463 #define HDSPM_LockAES 0x80 464 #define HDSPM_LockAES1 0x80 465 #define HDSPM_LockAES2 0x40 466 #define HDSPM_LockAES3 0x20 467 #define HDSPM_LockAES4 0x10 468 #define HDSPM_LockAES5 0x8 469 #define HDSPM_LockAES6 0x4 470 #define HDSPM_LockAES7 0x2 471 #define HDSPM_LockAES8 0x1 472 /* 473 Timecode 474 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on 475 AES i+1 476 bits 3210 477 0001 32kHz 478 0010 44.1kHz 479 0011 48kHz 480 0100 64kHz 481 0101 88.2kHz 482 0110 96kHz 483 0111 128kHz 484 1000 176.4kHz 485 1001 192kHz 486 NB: Timecode register doesn't seem to work on AES32 card revision 230 487 */ 488 489 /* Mixer Values */ 490 #define UNITY_GAIN 32768 /* = 65536/2 */ 491 #define MINUS_INFINITY_GAIN 0 492 493 /* Number of channels for different Speed Modes */ 494 #define MADI_SS_CHANNELS 64 495 #define MADI_DS_CHANNELS 32 496 #define MADI_QS_CHANNELS 16 497 498 #define RAYDAT_SS_CHANNELS 36 499 #define RAYDAT_DS_CHANNELS 20 500 #define RAYDAT_QS_CHANNELS 12 501 502 #define AIO_IN_SS_CHANNELS 14 503 #define AIO_IN_DS_CHANNELS 10 504 #define AIO_IN_QS_CHANNELS 8 505 #define AIO_OUT_SS_CHANNELS 16 506 #define AIO_OUT_DS_CHANNELS 12 507 #define AIO_OUT_QS_CHANNELS 10 508 509 #define AES32_CHANNELS 16 510 511 /* the size of a substream (1 mono data stream) */ 512 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024) 513 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES) 514 515 /* the size of the area we need to allocate for DMA transfers. the 516 size is the same regardless of the number of channels, and 517 also the latency to use. 518 for one direction !!! 519 */ 520 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES) 521 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024) 522 523 #define HDSPM_RAYDAT_REV 211 524 #define HDSPM_AIO_REV 212 525 #define HDSPM_MADIFACE_REV 213 526 527 /* speed factor modes */ 528 #define HDSPM_SPEED_SINGLE 0 529 #define HDSPM_SPEED_DOUBLE 1 530 #define HDSPM_SPEED_QUAD 2 531 532 /* names for speed modes */ 533 static char *hdspm_speed_names[] = { "single", "double", "quad" }; 534 535 static char *texts_autosync_aes_tco[] = { "Word Clock", 536 "AES1", "AES2", "AES3", "AES4", 537 "AES5", "AES6", "AES7", "AES8", 538 "TCO" }; 539 static char *texts_autosync_aes[] = { "Word Clock", 540 "AES1", "AES2", "AES3", "AES4", 541 "AES5", "AES6", "AES7", "AES8" }; 542 static char *texts_autosync_madi_tco[] = { "Word Clock", 543 "MADI", "TCO", "Sync In" }; 544 static char *texts_autosync_madi[] = { "Word Clock", 545 "MADI", "Sync In" }; 546 547 static char *texts_autosync_raydat_tco[] = { 548 "Word Clock", 549 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 550 "AES", "SPDIF", "TCO", "Sync In" 551 }; 552 static char *texts_autosync_raydat[] = { 553 "Word Clock", 554 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4", 555 "AES", "SPDIF", "Sync In" 556 }; 557 static char *texts_autosync_aio_tco[] = { 558 "Word Clock", 559 "ADAT", "AES", "SPDIF", "TCO", "Sync In" 560 }; 561 static char *texts_autosync_aio[] = { "Word Clock", 562 "ADAT", "AES", "SPDIF", "Sync In" }; 563 564 static char *texts_freq[] = { 565 "No Lock", 566 "32 kHz", 567 "44.1 kHz", 568 "48 kHz", 569 "64 kHz", 570 "88.2 kHz", 571 "96 kHz", 572 "128 kHz", 573 "176.4 kHz", 574 "192 kHz" 575 }; 576 577 static char *texts_ports_madi[] = { 578 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6", 579 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12", 580 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18", 581 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24", 582 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30", 583 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36", 584 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42", 585 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48", 586 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54", 587 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60", 588 "MADI.61", "MADI.62", "MADI.63", "MADI.64", 589 }; 590 591 592 static char *texts_ports_raydat_ss[] = { 593 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6", 594 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 595 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2", 596 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8", 597 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6", 598 "ADAT4.7", "ADAT4.8", 599 "AES.L", "AES.R", 600 "SPDIF.L", "SPDIF.R" 601 }; 602 603 static char *texts_ports_raydat_ds[] = { 604 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", 605 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4", 606 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4", 607 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", 608 "AES.L", "AES.R", 609 "SPDIF.L", "SPDIF.R" 610 }; 611 612 static char *texts_ports_raydat_qs[] = { 613 "ADAT1.1", "ADAT1.2", 614 "ADAT2.1", "ADAT2.2", 615 "ADAT3.1", "ADAT3.2", 616 "ADAT4.1", "ADAT4.2", 617 "AES.L", "AES.R", 618 "SPDIF.L", "SPDIF.R" 619 }; 620 621 622 static char *texts_ports_aio_in_ss[] = { 623 "Analogue.L", "Analogue.R", 624 "AES.L", "AES.R", 625 "SPDIF.L", "SPDIF.R", 626 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 627 "ADAT.7", "ADAT.8" 628 }; 629 630 static char *texts_ports_aio_out_ss[] = { 631 "Analogue.L", "Analogue.R", 632 "AES.L", "AES.R", 633 "SPDIF.L", "SPDIF.R", 634 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6", 635 "ADAT.7", "ADAT.8", 636 "Phone.L", "Phone.R" 637 }; 638 639 static char *texts_ports_aio_in_ds[] = { 640 "Analogue.L", "Analogue.R", 641 "AES.L", "AES.R", 642 "SPDIF.L", "SPDIF.R", 643 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 644 }; 645 646 static char *texts_ports_aio_out_ds[] = { 647 "Analogue.L", "Analogue.R", 648 "AES.L", "AES.R", 649 "SPDIF.L", "SPDIF.R", 650 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 651 "Phone.L", "Phone.R" 652 }; 653 654 static char *texts_ports_aio_in_qs[] = { 655 "Analogue.L", "Analogue.R", 656 "AES.L", "AES.R", 657 "SPDIF.L", "SPDIF.R", 658 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4" 659 }; 660 661 static char *texts_ports_aio_out_qs[] = { 662 "Analogue.L", "Analogue.R", 663 "AES.L", "AES.R", 664 "SPDIF.L", "SPDIF.R", 665 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", 666 "Phone.L", "Phone.R" 667 }; 668 669 static char *texts_ports_aes32[] = { 670 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7", 671 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14", 672 "AES.15", "AES.16" 673 }; 674 675 /* These tables map the ALSA channels 1..N to the channels that we 676 need to use in order to find the relevant channel buffer. RME 677 refers to this kind of mapping as between "the ADAT channel and 678 the DMA channel." We index it using the logical audio channel, 679 and the value is the DMA channel (i.e. channel buffer number) 680 where the data for that channel can be read/written from/to. 681 */ 682 683 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = { 684 0, 1, 2, 3, 4, 5, 6, 7, 685 8, 9, 10, 11, 12, 13, 14, 15, 686 16, 17, 18, 19, 20, 21, 22, 23, 687 24, 25, 26, 27, 28, 29, 30, 31, 688 32, 33, 34, 35, 36, 37, 38, 39, 689 40, 41, 42, 43, 44, 45, 46, 47, 690 48, 49, 50, 51, 52, 53, 54, 55, 691 56, 57, 58, 59, 60, 61, 62, 63 692 }; 693 694 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = { 695 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */ 696 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */ 697 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */ 698 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */ 699 0, 1, /* AES */ 700 2, 3, /* SPDIF */ 701 -1, -1, -1, -1, 702 -1, -1, -1, -1, -1, -1, -1, -1, 703 -1, -1, -1, -1, -1, -1, -1, -1, 704 -1, -1, -1, -1, -1, -1, -1, -1, 705 }; 706 707 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = { 708 4, 5, 6, 7, /* ADAT 1 */ 709 8, 9, 10, 11, /* ADAT 2 */ 710 12, 13, 14, 15, /* ADAT 3 */ 711 16, 17, 18, 19, /* ADAT 4 */ 712 0, 1, /* AES */ 713 2, 3, /* SPDIF */ 714 -1, -1, -1, -1, 715 -1, -1, -1, -1, -1, -1, -1, -1, 716 -1, -1, -1, -1, -1, -1, -1, -1, 717 -1, -1, -1, -1, -1, -1, -1, -1, 718 -1, -1, -1, -1, -1, -1, -1, -1, 719 -1, -1, -1, -1, -1, -1, -1, -1, 720 }; 721 722 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = { 723 4, 5, /* ADAT 1 */ 724 6, 7, /* ADAT 2 */ 725 8, 9, /* ADAT 3 */ 726 10, 11, /* ADAT 4 */ 727 0, 1, /* AES */ 728 2, 3, /* SPDIF */ 729 -1, -1, -1, -1, 730 -1, -1, -1, -1, -1, -1, -1, -1, 731 -1, -1, -1, -1, -1, -1, -1, -1, 732 -1, -1, -1, -1, -1, -1, -1, -1, 733 -1, -1, -1, -1, -1, -1, -1, -1, 734 -1, -1, -1, -1, -1, -1, -1, -1, 735 -1, -1, -1, -1, -1, -1, -1, -1, 736 }; 737 738 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = { 739 0, 1, /* line in */ 740 8, 9, /* aes in, */ 741 10, 11, /* spdif in */ 742 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */ 743 -1, -1, 744 -1, -1, -1, -1, -1, -1, -1, -1, 745 -1, -1, -1, -1, -1, -1, -1, -1, 746 -1, -1, -1, -1, -1, -1, -1, -1, 747 -1, -1, -1, -1, -1, -1, -1, -1, 748 -1, -1, -1, -1, -1, -1, -1, -1, 749 -1, -1, -1, -1, -1, -1, -1, -1, 750 }; 751 752 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = { 753 0, 1, /* line out */ 754 8, 9, /* aes out */ 755 10, 11, /* spdif out */ 756 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */ 757 6, 7, /* phone out */ 758 -1, -1, -1, -1, -1, -1, -1, -1, 759 -1, -1, -1, -1, -1, -1, -1, -1, 760 -1, -1, -1, -1, -1, -1, -1, -1, 761 -1, -1, -1, -1, -1, -1, -1, -1, 762 -1, -1, -1, -1, -1, -1, -1, -1, 763 -1, -1, -1, -1, -1, -1, -1, -1, 764 }; 765 766 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = { 767 0, 1, /* line in */ 768 8, 9, /* aes in */ 769 10, 11, /* spdif in */ 770 12, 14, 16, 18, /* adat in */ 771 -1, -1, -1, -1, -1, -1, 772 -1, -1, -1, -1, -1, -1, -1, -1, 773 -1, -1, -1, -1, -1, -1, -1, -1, 774 -1, -1, -1, -1, -1, -1, -1, -1, 775 -1, -1, -1, -1, -1, -1, -1, -1, 776 -1, -1, -1, -1, -1, -1, -1, -1, 777 -1, -1, -1, -1, -1, -1, -1, -1 778 }; 779 780 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = { 781 0, 1, /* line out */ 782 8, 9, /* aes out */ 783 10, 11, /* spdif out */ 784 12, 14, 16, 18, /* adat out */ 785 6, 7, /* phone out */ 786 -1, -1, -1, -1, 787 -1, -1, -1, -1, -1, -1, -1, -1, 788 -1, -1, -1, -1, -1, -1, -1, -1, 789 -1, -1, -1, -1, -1, -1, -1, -1, 790 -1, -1, -1, -1, -1, -1, -1, -1, 791 -1, -1, -1, -1, -1, -1, -1, -1, 792 -1, -1, -1, -1, -1, -1, -1, -1 793 }; 794 795 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = { 796 0, 1, /* line in */ 797 8, 9, /* aes in */ 798 10, 11, /* spdif in */ 799 12, 16, /* adat in */ 800 -1, -1, -1, -1, -1, -1, -1, -1, 801 -1, -1, -1, -1, -1, -1, -1, -1, 802 -1, -1, -1, -1, -1, -1, -1, -1, 803 -1, -1, -1, -1, -1, -1, -1, -1, 804 -1, -1, -1, -1, -1, -1, -1, -1, 805 -1, -1, -1, -1, -1, -1, -1, -1, 806 -1, -1, -1, -1, -1, -1, -1, -1 807 }; 808 809 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = { 810 0, 1, /* line out */ 811 8, 9, /* aes out */ 812 10, 11, /* spdif out */ 813 12, 16, /* adat out */ 814 6, 7, /* phone out */ 815 -1, -1, -1, -1, -1, -1, 816 -1, -1, -1, -1, -1, -1, -1, -1, 817 -1, -1, -1, -1, -1, -1, -1, -1, 818 -1, -1, -1, -1, -1, -1, -1, -1, 819 -1, -1, -1, -1, -1, -1, -1, -1, 820 -1, -1, -1, -1, -1, -1, -1, -1, 821 -1, -1, -1, -1, -1, -1, -1, -1 822 }; 823 824 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = { 825 0, 1, 2, 3, 4, 5, 6, 7, 826 8, 9, 10, 11, 12, 13, 14, 15, 827 -1, -1, -1, -1, -1, -1, -1, -1, 828 -1, -1, -1, -1, -1, -1, -1, -1, 829 -1, -1, -1, -1, -1, -1, -1, -1, 830 -1, -1, -1, -1, -1, -1, -1, -1, 831 -1, -1, -1, -1, -1, -1, -1, -1, 832 -1, -1, -1, -1, -1, -1, -1, -1 833 }; 834 835 struct hdspm_midi { 836 struct hdspm *hdspm; 837 int id; 838 struct snd_rawmidi *rmidi; 839 struct snd_rawmidi_substream *input; 840 struct snd_rawmidi_substream *output; 841 char istimer; /* timer in use */ 842 struct timer_list timer; 843 spinlock_t lock; 844 int pending; 845 int dataIn; 846 int statusIn; 847 int dataOut; 848 int statusOut; 849 int ie; 850 int irq; 851 }; 852 853 struct hdspm_tco { 854 int input; 855 int framerate; 856 int wordclock; 857 int samplerate; 858 int pull; 859 int term; /* 0 = off, 1 = on */ 860 }; 861 862 struct hdspm { 863 spinlock_t lock; 864 /* only one playback and/or capture stream */ 865 struct snd_pcm_substream *capture_substream; 866 struct snd_pcm_substream *playback_substream; 867 868 char *card_name; /* for procinfo */ 869 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/ 870 871 uint8_t io_type; 872 873 int monitor_outs; /* set up monitoring outs init flag */ 874 875 u32 control_register; /* cached value */ 876 u32 control2_register; /* cached value */ 877 u32 settings_register; 878 879 struct hdspm_midi midi[4]; 880 struct tasklet_struct midi_tasklet; 881 882 size_t period_bytes; 883 unsigned char ss_in_channels; 884 unsigned char ds_in_channels; 885 unsigned char qs_in_channels; 886 unsigned char ss_out_channels; 887 unsigned char ds_out_channels; 888 unsigned char qs_out_channels; 889 890 unsigned char max_channels_in; 891 unsigned char max_channels_out; 892 893 signed char *channel_map_in; 894 signed char *channel_map_out; 895 896 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs; 897 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs; 898 899 char **port_names_in; 900 char **port_names_out; 901 902 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs; 903 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs; 904 905 unsigned char *playback_buffer; /* suitably aligned address */ 906 unsigned char *capture_buffer; /* suitably aligned address */ 907 908 pid_t capture_pid; /* process id which uses capture */ 909 pid_t playback_pid; /* process id which uses capture */ 910 int running; /* running status */ 911 912 int last_external_sample_rate; /* samplerate mystic ... */ 913 int last_internal_sample_rate; 914 int system_sample_rate; 915 916 int dev; /* Hardware vars... */ 917 int irq; 918 unsigned long port; 919 void __iomem *iobase; 920 921 int irq_count; /* for debug */ 922 int midiPorts; 923 924 struct snd_card *card; /* one card */ 925 struct snd_pcm *pcm; /* has one pcm */ 926 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */ 927 struct pci_dev *pci; /* and an pci info */ 928 929 /* Mixer vars */ 930 /* fast alsa mixer */ 931 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS]; 932 /* but input to much, so not used */ 933 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS]; 934 /* full mixer accessible over mixer ioctl or hwdep-device */ 935 struct hdspm_mixer *mixer; 936 937 struct hdspm_tco *tco; /* NULL if no TCO detected */ 938 939 char **texts_autosync; 940 int texts_autosync_items; 941 942 cycles_t last_interrupt; 943 944 unsigned int serial; 945 946 struct hdspm_peak_rms peak_rms; 947 }; 948 949 950 static DEFINE_PCI_DEVICE_TABLE(snd_hdspm_ids) = { 951 { 952 .vendor = PCI_VENDOR_ID_XILINX, 953 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI, 954 .subvendor = PCI_ANY_ID, 955 .subdevice = PCI_ANY_ID, 956 .class = 0, 957 .class_mask = 0, 958 .driver_data = 0}, 959 {0,} 960 }; 961 962 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids); 963 964 /* prototypes */ 965 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 966 struct hdspm *hdspm); 967 static int snd_hdspm_create_pcm(struct snd_card *card, 968 struct hdspm *hdspm); 969 970 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm); 971 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm); 972 static int hdspm_autosync_ref(struct hdspm *hdspm); 973 static int snd_hdspm_set_defaults(struct hdspm *hdspm); 974 static int hdspm_system_clock_mode(struct hdspm *hdspm); 975 static void hdspm_set_sgbuf(struct hdspm *hdspm, 976 struct snd_pcm_substream *substream, 977 unsigned int reg, int channels); 978 979 static inline int HDSPM_bit2freq(int n) 980 { 981 static const int bit2freq_tab[] = { 982 0, 32000, 44100, 48000, 64000, 88200, 983 96000, 128000, 176400, 192000 }; 984 if (n < 1 || n > 9) 985 return 0; 986 return bit2freq_tab[n]; 987 } 988 989 /* Write/read to/from HDSPM with Adresses in Bytes 990 not words but only 32Bit writes are allowed */ 991 992 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg, 993 unsigned int val) 994 { 995 writel(val, hdspm->iobase + reg); 996 } 997 998 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg) 999 { 1000 return readl(hdspm->iobase + reg); 1001 } 1002 1003 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader 1004 mixer is write only on hardware so we have to cache him for read 1005 each fader is a u32, but uses only the first 16 bit */ 1006 1007 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan, 1008 unsigned int in) 1009 { 1010 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1011 return 0; 1012 1013 return hdspm->mixer->ch[chan].in[in]; 1014 } 1015 1016 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan, 1017 unsigned int pb) 1018 { 1019 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1020 return 0; 1021 return hdspm->mixer->ch[chan].pb[pb]; 1022 } 1023 1024 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan, 1025 unsigned int in, unsigned short data) 1026 { 1027 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS) 1028 return -1; 1029 1030 hdspm_write(hdspm, 1031 HDSPM_MADI_mixerBase + 1032 ((in + 128 * chan) * sizeof(u32)), 1033 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF)); 1034 return 0; 1035 } 1036 1037 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan, 1038 unsigned int pb, unsigned short data) 1039 { 1040 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS) 1041 return -1; 1042 1043 hdspm_write(hdspm, 1044 HDSPM_MADI_mixerBase + 1045 ((64 + pb + 128 * chan) * sizeof(u32)), 1046 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF)); 1047 return 0; 1048 } 1049 1050 1051 /* enable DMA for specific channels, now available for DSP-MADI */ 1052 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v) 1053 { 1054 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v); 1055 } 1056 1057 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v) 1058 { 1059 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v); 1060 } 1061 1062 /* check if same process is writing and reading */ 1063 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm) 1064 { 1065 unsigned long flags; 1066 int ret = 1; 1067 1068 spin_lock_irqsave(&hdspm->lock, flags); 1069 if ((hdspm->playback_pid != hdspm->capture_pid) && 1070 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) { 1071 ret = 0; 1072 } 1073 spin_unlock_irqrestore(&hdspm->lock, flags); 1074 return ret; 1075 } 1076 1077 /* check for external sample rate */ 1078 static int hdspm_external_sample_rate(struct hdspm *hdspm) 1079 { 1080 unsigned int status, status2, timecode; 1081 int syncref, rate = 0, rate_bits; 1082 1083 switch (hdspm->io_type) { 1084 case AES32: 1085 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1086 status = hdspm_read(hdspm, HDSPM_statusRegister); 1087 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 1088 1089 syncref = hdspm_autosync_ref(hdspm); 1090 1091 if (syncref == HDSPM_AES32_AUTOSYNC_FROM_WORD && 1092 status & HDSPM_AES32_wcLock) 1093 return HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF); 1094 1095 if (syncref >= HDSPM_AES32_AUTOSYNC_FROM_AES1 && 1096 syncref <= HDSPM_AES32_AUTOSYNC_FROM_AES8 && 1097 status2 & (HDSPM_LockAES >> 1098 (syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))) 1099 return HDSPM_bit2freq((timecode >> (4*(syncref-HDSPM_AES32_AUTOSYNC_FROM_AES1))) & 0xF); 1100 return 0; 1101 break; 1102 1103 case MADIface: 1104 status = hdspm_read(hdspm, HDSPM_statusRegister); 1105 1106 if (!(status & HDSPM_madiLock)) { 1107 rate = 0; /* no lock */ 1108 } else { 1109 switch (status & (HDSPM_status1_freqMask)) { 1110 case HDSPM_status1_F_0*1: 1111 rate = 32000; break; 1112 case HDSPM_status1_F_0*2: 1113 rate = 44100; break; 1114 case HDSPM_status1_F_0*3: 1115 rate = 48000; break; 1116 case HDSPM_status1_F_0*4: 1117 rate = 64000; break; 1118 case HDSPM_status1_F_0*5: 1119 rate = 88200; break; 1120 case HDSPM_status1_F_0*6: 1121 rate = 96000; break; 1122 case HDSPM_status1_F_0*7: 1123 rate = 128000; break; 1124 case HDSPM_status1_F_0*8: 1125 rate = 176400; break; 1126 case HDSPM_status1_F_0*9: 1127 rate = 192000; break; 1128 default: 1129 rate = 0; break; 1130 } 1131 } 1132 1133 break; 1134 1135 case MADI: 1136 case AIO: 1137 case RayDAT: 1138 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 1139 status = hdspm_read(hdspm, HDSPM_statusRegister); 1140 rate = 0; 1141 1142 /* if wordclock has synced freq and wordclock is valid */ 1143 if ((status2 & HDSPM_wcLock) != 0 && 1144 (status2 & HDSPM_SelSyncRef0) == 0) { 1145 1146 rate_bits = status2 & HDSPM_wcFreqMask; 1147 1148 1149 switch (rate_bits) { 1150 case HDSPM_wcFreq32: 1151 rate = 32000; 1152 break; 1153 case HDSPM_wcFreq44_1: 1154 rate = 44100; 1155 break; 1156 case HDSPM_wcFreq48: 1157 rate = 48000; 1158 break; 1159 case HDSPM_wcFreq64: 1160 rate = 64000; 1161 break; 1162 case HDSPM_wcFreq88_2: 1163 rate = 88200; 1164 break; 1165 case HDSPM_wcFreq96: 1166 rate = 96000; 1167 break; 1168 default: 1169 rate = 0; 1170 break; 1171 } 1172 } 1173 1174 /* if rate detected and Syncref is Word than have it, 1175 * word has priority to MADI 1176 */ 1177 if (rate != 0 && 1178 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD) 1179 return rate; 1180 1181 /* maybe a madi input (which is taken if sel sync is madi) */ 1182 if (status & HDSPM_madiLock) { 1183 rate_bits = status & HDSPM_madiFreqMask; 1184 1185 switch (rate_bits) { 1186 case HDSPM_madiFreq32: 1187 rate = 32000; 1188 break; 1189 case HDSPM_madiFreq44_1: 1190 rate = 44100; 1191 break; 1192 case HDSPM_madiFreq48: 1193 rate = 48000; 1194 break; 1195 case HDSPM_madiFreq64: 1196 rate = 64000; 1197 break; 1198 case HDSPM_madiFreq88_2: 1199 rate = 88200; 1200 break; 1201 case HDSPM_madiFreq96: 1202 rate = 96000; 1203 break; 1204 case HDSPM_madiFreq128: 1205 rate = 128000; 1206 break; 1207 case HDSPM_madiFreq176_4: 1208 rate = 176400; 1209 break; 1210 case HDSPM_madiFreq192: 1211 rate = 192000; 1212 break; 1213 default: 1214 rate = 0; 1215 break; 1216 } 1217 1218 /* QS and DS rates normally can not be detected 1219 * automatically by the card. Only exception is MADI 1220 * in 96k frame mode. 1221 * 1222 * So if we read SS values (32 .. 48k), check for 1223 * user-provided DS/QS bits in the control register 1224 * and multiply the base frequency accordingly. 1225 */ 1226 if (rate <= 48000) { 1227 if (hdspm->control_register & HDSPM_QuadSpeed) 1228 rate *= 4; 1229 else if (hdspm->control_register & 1230 HDSPM_DoubleSpeed) 1231 rate *= 2; 1232 } 1233 } 1234 break; 1235 } 1236 1237 return rate; 1238 } 1239 1240 /* return latency in samples per period */ 1241 static int hdspm_get_latency(struct hdspm *hdspm) 1242 { 1243 int n; 1244 1245 n = hdspm_decode_latency(hdspm->control_register); 1246 1247 /* Special case for new RME cards with 32 samples period size. 1248 * The three latency bits in the control register 1249 * (HDSP_LatencyMask) encode latency values of 64 samples as 1250 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7 1251 * denotes 8192 samples, but on new cards like RayDAT or AIO, 1252 * it corresponds to 32 samples. 1253 */ 1254 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type)) 1255 n = -1; 1256 1257 return 1 << (n + 6); 1258 } 1259 1260 /* Latency function */ 1261 static inline void hdspm_compute_period_size(struct hdspm *hdspm) 1262 { 1263 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm); 1264 } 1265 1266 1267 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm) 1268 { 1269 int position; 1270 1271 position = hdspm_read(hdspm, HDSPM_statusRegister); 1272 1273 switch (hdspm->io_type) { 1274 case RayDAT: 1275 case AIO: 1276 position &= HDSPM_BufferPositionMask; 1277 position /= 4; /* Bytes per sample */ 1278 break; 1279 default: 1280 position = (position & HDSPM_BufferID) ? 1281 (hdspm->period_bytes / 4) : 0; 1282 } 1283 1284 return position; 1285 } 1286 1287 1288 static inline void hdspm_start_audio(struct hdspm * s) 1289 { 1290 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start); 1291 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1292 } 1293 1294 static inline void hdspm_stop_audio(struct hdspm * s) 1295 { 1296 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable); 1297 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1298 } 1299 1300 /* should I silence all or only opened ones ? doit all for first even is 4MB*/ 1301 static void hdspm_silence_playback(struct hdspm *hdspm) 1302 { 1303 int i; 1304 int n = hdspm->period_bytes; 1305 void *buf = hdspm->playback_buffer; 1306 1307 if (buf == NULL) 1308 return; 1309 1310 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 1311 memset(buf, 0, n); 1312 buf += HDSPM_CHANNEL_BUFFER_BYTES; 1313 } 1314 } 1315 1316 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames) 1317 { 1318 int n; 1319 1320 spin_lock_irq(&s->lock); 1321 1322 if (32 == frames) { 1323 /* Special case for new RME cards like RayDAT/AIO which 1324 * support period sizes of 32 samples. Since latency is 1325 * encoded in the three bits of HDSP_LatencyMask, we can only 1326 * have values from 0 .. 7. While 0 still means 64 samples and 1327 * 6 represents 4096 samples on all cards, 7 represents 8192 1328 * on older cards and 32 samples on new cards. 1329 * 1330 * In other words, period size in samples is calculated by 1331 * 2^(n+6) with n ranging from 0 .. 7. 1332 */ 1333 n = 7; 1334 } else { 1335 frames >>= 7; 1336 n = 0; 1337 while (frames) { 1338 n++; 1339 frames >>= 1; 1340 } 1341 } 1342 1343 s->control_register &= ~HDSPM_LatencyMask; 1344 s->control_register |= hdspm_encode_latency(n); 1345 1346 hdspm_write(s, HDSPM_controlRegister, s->control_register); 1347 1348 hdspm_compute_period_size(s); 1349 1350 spin_unlock_irq(&s->lock); 1351 1352 return 0; 1353 } 1354 1355 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period) 1356 { 1357 u64 freq_const; 1358 1359 if (period == 0) 1360 return 0; 1361 1362 switch (hdspm->io_type) { 1363 case MADI: 1364 case AES32: 1365 freq_const = 110069313433624ULL; 1366 break; 1367 case RayDAT: 1368 case AIO: 1369 freq_const = 104857600000000ULL; 1370 break; 1371 case MADIface: 1372 freq_const = 131072000000000ULL; 1373 break; 1374 default: 1375 snd_BUG(); 1376 return 0; 1377 } 1378 1379 return div_u64(freq_const, period); 1380 } 1381 1382 1383 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate) 1384 { 1385 u64 n; 1386 1387 if (rate >= 112000) 1388 rate /= 4; 1389 else if (rate >= 56000) 1390 rate /= 2; 1391 1392 switch (hdspm->io_type) { 1393 case MADIface: 1394 n = 131072000000000ULL; /* 125 MHz */ 1395 break; 1396 case MADI: 1397 case AES32: 1398 n = 110069313433624ULL; /* 105 MHz */ 1399 break; 1400 case RayDAT: 1401 case AIO: 1402 n = 104857600000000ULL; /* 100 MHz */ 1403 break; 1404 default: 1405 snd_BUG(); 1406 return; 1407 } 1408 1409 n = div_u64(n, rate); 1410 /* n should be less than 2^32 for being written to FREQ register */ 1411 snd_BUG_ON(n >> 32); 1412 hdspm_write(hdspm, HDSPM_freqReg, (u32)n); 1413 } 1414 1415 /* dummy set rate lets see what happens */ 1416 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally) 1417 { 1418 int current_rate; 1419 int rate_bits; 1420 int not_set = 0; 1421 int current_speed, target_speed; 1422 1423 /* ASSUMPTION: hdspm->lock is either set, or there is no need for 1424 it (e.g. during module initialization). 1425 */ 1426 1427 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) { 1428 1429 /* SLAVE --- */ 1430 if (called_internally) { 1431 1432 /* request from ctl or card initialization 1433 just make a warning an remember setting 1434 for future master mode switching */ 1435 1436 snd_printk(KERN_WARNING "HDSPM: " 1437 "Warning: device is not running " 1438 "as a clock master.\n"); 1439 not_set = 1; 1440 } else { 1441 1442 /* hw_param request while in AutoSync mode */ 1443 int external_freq = 1444 hdspm_external_sample_rate(hdspm); 1445 1446 if (hdspm_autosync_ref(hdspm) == 1447 HDSPM_AUTOSYNC_FROM_NONE) { 1448 1449 snd_printk(KERN_WARNING "HDSPM: " 1450 "Detected no Externel Sync \n"); 1451 not_set = 1; 1452 1453 } else if (rate != external_freq) { 1454 1455 snd_printk(KERN_WARNING "HDSPM: " 1456 "Warning: No AutoSync source for " 1457 "requested rate\n"); 1458 not_set = 1; 1459 } 1460 } 1461 } 1462 1463 current_rate = hdspm->system_sample_rate; 1464 1465 /* Changing between Singe, Double and Quad speed is not 1466 allowed if any substreams are open. This is because such a change 1467 causes a shift in the location of the DMA buffers and a reduction 1468 in the number of available buffers. 1469 1470 Note that a similar but essentially insoluble problem exists for 1471 externally-driven rate changes. All we can do is to flag rate 1472 changes in the read/write routines. 1473 */ 1474 1475 if (current_rate <= 48000) 1476 current_speed = HDSPM_SPEED_SINGLE; 1477 else if (current_rate <= 96000) 1478 current_speed = HDSPM_SPEED_DOUBLE; 1479 else 1480 current_speed = HDSPM_SPEED_QUAD; 1481 1482 if (rate <= 48000) 1483 target_speed = HDSPM_SPEED_SINGLE; 1484 else if (rate <= 96000) 1485 target_speed = HDSPM_SPEED_DOUBLE; 1486 else 1487 target_speed = HDSPM_SPEED_QUAD; 1488 1489 switch (rate) { 1490 case 32000: 1491 rate_bits = HDSPM_Frequency32KHz; 1492 break; 1493 case 44100: 1494 rate_bits = HDSPM_Frequency44_1KHz; 1495 break; 1496 case 48000: 1497 rate_bits = HDSPM_Frequency48KHz; 1498 break; 1499 case 64000: 1500 rate_bits = HDSPM_Frequency64KHz; 1501 break; 1502 case 88200: 1503 rate_bits = HDSPM_Frequency88_2KHz; 1504 break; 1505 case 96000: 1506 rate_bits = HDSPM_Frequency96KHz; 1507 break; 1508 case 128000: 1509 rate_bits = HDSPM_Frequency128KHz; 1510 break; 1511 case 176400: 1512 rate_bits = HDSPM_Frequency176_4KHz; 1513 break; 1514 case 192000: 1515 rate_bits = HDSPM_Frequency192KHz; 1516 break; 1517 default: 1518 return -EINVAL; 1519 } 1520 1521 if (current_speed != target_speed 1522 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) { 1523 snd_printk 1524 (KERN_ERR "HDSPM: " 1525 "cannot change from %s speed to %s speed mode " 1526 "(capture PID = %d, playback PID = %d)\n", 1527 hdspm_speed_names[current_speed], 1528 hdspm_speed_names[target_speed], 1529 hdspm->capture_pid, hdspm->playback_pid); 1530 return -EBUSY; 1531 } 1532 1533 hdspm->control_register &= ~HDSPM_FrequencyMask; 1534 hdspm->control_register |= rate_bits; 1535 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1536 1537 /* For AES32, need to set DDS value in FREQ register 1538 For MADI, also apparently */ 1539 hdspm_set_dds_value(hdspm, rate); 1540 1541 if (AES32 == hdspm->io_type && rate != current_rate) 1542 hdspm_write(hdspm, HDSPM_eeprom_wr, 0); 1543 1544 hdspm->system_sample_rate = rate; 1545 1546 if (rate <= 48000) { 1547 hdspm->channel_map_in = hdspm->channel_map_in_ss; 1548 hdspm->channel_map_out = hdspm->channel_map_out_ss; 1549 hdspm->max_channels_in = hdspm->ss_in_channels; 1550 hdspm->max_channels_out = hdspm->ss_out_channels; 1551 hdspm->port_names_in = hdspm->port_names_in_ss; 1552 hdspm->port_names_out = hdspm->port_names_out_ss; 1553 } else if (rate <= 96000) { 1554 hdspm->channel_map_in = hdspm->channel_map_in_ds; 1555 hdspm->channel_map_out = hdspm->channel_map_out_ds; 1556 hdspm->max_channels_in = hdspm->ds_in_channels; 1557 hdspm->max_channels_out = hdspm->ds_out_channels; 1558 hdspm->port_names_in = hdspm->port_names_in_ds; 1559 hdspm->port_names_out = hdspm->port_names_out_ds; 1560 } else { 1561 hdspm->channel_map_in = hdspm->channel_map_in_qs; 1562 hdspm->channel_map_out = hdspm->channel_map_out_qs; 1563 hdspm->max_channels_in = hdspm->qs_in_channels; 1564 hdspm->max_channels_out = hdspm->qs_out_channels; 1565 hdspm->port_names_in = hdspm->port_names_in_qs; 1566 hdspm->port_names_out = hdspm->port_names_out_qs; 1567 } 1568 1569 if (not_set != 0) 1570 return -1; 1571 1572 return 0; 1573 } 1574 1575 /* mainly for init to 0 on load */ 1576 static void all_in_all_mixer(struct hdspm * hdspm, int sgain) 1577 { 1578 int i, j; 1579 unsigned int gain; 1580 1581 if (sgain > UNITY_GAIN) 1582 gain = UNITY_GAIN; 1583 else if (sgain < 0) 1584 gain = 0; 1585 else 1586 gain = sgain; 1587 1588 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++) 1589 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) { 1590 hdspm_write_in_gain(hdspm, i, j, gain); 1591 hdspm_write_pb_gain(hdspm, i, j, gain); 1592 } 1593 } 1594 1595 /*---------------------------------------------------------------------------- 1596 MIDI 1597 ----------------------------------------------------------------------------*/ 1598 1599 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm, 1600 int id) 1601 { 1602 /* the hardware already does the relevant bit-mask with 0xff */ 1603 return hdspm_read(hdspm, hdspm->midi[id].dataIn); 1604 } 1605 1606 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id, 1607 int val) 1608 { 1609 /* the hardware already does the relevant bit-mask with 0xff */ 1610 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val); 1611 } 1612 1613 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id) 1614 { 1615 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF; 1616 } 1617 1618 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id) 1619 { 1620 int fifo_bytes_used; 1621 1622 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF; 1623 1624 if (fifo_bytes_used < 128) 1625 return 128 - fifo_bytes_used; 1626 else 1627 return 0; 1628 } 1629 1630 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id) 1631 { 1632 while (snd_hdspm_midi_input_available (hdspm, id)) 1633 snd_hdspm_midi_read_byte (hdspm, id); 1634 } 1635 1636 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi) 1637 { 1638 unsigned long flags; 1639 int n_pending; 1640 int to_write; 1641 int i; 1642 unsigned char buf[128]; 1643 1644 /* Output is not interrupt driven */ 1645 1646 spin_lock_irqsave (&hmidi->lock, flags); 1647 if (hmidi->output && 1648 !snd_rawmidi_transmit_empty (hmidi->output)) { 1649 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm, 1650 hmidi->id); 1651 if (n_pending > 0) { 1652 if (n_pending > (int)sizeof (buf)) 1653 n_pending = sizeof (buf); 1654 1655 to_write = snd_rawmidi_transmit (hmidi->output, buf, 1656 n_pending); 1657 if (to_write > 0) { 1658 for (i = 0; i < to_write; ++i) 1659 snd_hdspm_midi_write_byte (hmidi->hdspm, 1660 hmidi->id, 1661 buf[i]); 1662 } 1663 } 1664 } 1665 spin_unlock_irqrestore (&hmidi->lock, flags); 1666 return 0; 1667 } 1668 1669 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi) 1670 { 1671 unsigned char buf[128]; /* this buffer is designed to match the MIDI 1672 * input FIFO size 1673 */ 1674 unsigned long flags; 1675 int n_pending; 1676 int i; 1677 1678 spin_lock_irqsave (&hmidi->lock, flags); 1679 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id); 1680 if (n_pending > 0) { 1681 if (hmidi->input) { 1682 if (n_pending > (int)sizeof (buf)) 1683 n_pending = sizeof (buf); 1684 for (i = 0; i < n_pending; ++i) 1685 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm, 1686 hmidi->id); 1687 if (n_pending) 1688 snd_rawmidi_receive (hmidi->input, buf, 1689 n_pending); 1690 } else { 1691 /* flush the MIDI input FIFO */ 1692 while (n_pending--) 1693 snd_hdspm_midi_read_byte (hmidi->hdspm, 1694 hmidi->id); 1695 } 1696 } 1697 hmidi->pending = 0; 1698 spin_unlock_irqrestore(&hmidi->lock, flags); 1699 1700 spin_lock_irqsave(&hmidi->hdspm->lock, flags); 1701 hmidi->hdspm->control_register |= hmidi->ie; 1702 hdspm_write(hmidi->hdspm, HDSPM_controlRegister, 1703 hmidi->hdspm->control_register); 1704 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags); 1705 1706 return snd_hdspm_midi_output_write (hmidi); 1707 } 1708 1709 static void 1710 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1711 { 1712 struct hdspm *hdspm; 1713 struct hdspm_midi *hmidi; 1714 unsigned long flags; 1715 1716 hmidi = substream->rmidi->private_data; 1717 hdspm = hmidi->hdspm; 1718 1719 spin_lock_irqsave (&hdspm->lock, flags); 1720 if (up) { 1721 if (!(hdspm->control_register & hmidi->ie)) { 1722 snd_hdspm_flush_midi_input (hdspm, hmidi->id); 1723 hdspm->control_register |= hmidi->ie; 1724 } 1725 } else { 1726 hdspm->control_register &= ~hmidi->ie; 1727 } 1728 1729 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 1730 spin_unlock_irqrestore (&hdspm->lock, flags); 1731 } 1732 1733 static void snd_hdspm_midi_output_timer(unsigned long data) 1734 { 1735 struct hdspm_midi *hmidi = (struct hdspm_midi *) data; 1736 unsigned long flags; 1737 1738 snd_hdspm_midi_output_write(hmidi); 1739 spin_lock_irqsave (&hmidi->lock, flags); 1740 1741 /* this does not bump hmidi->istimer, because the 1742 kernel automatically removed the timer when it 1743 expired, and we are now adding it back, thus 1744 leaving istimer wherever it was set before. 1745 */ 1746 1747 if (hmidi->istimer) { 1748 hmidi->timer.expires = 1 + jiffies; 1749 add_timer(&hmidi->timer); 1750 } 1751 1752 spin_unlock_irqrestore (&hmidi->lock, flags); 1753 } 1754 1755 static void 1756 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1757 { 1758 struct hdspm_midi *hmidi; 1759 unsigned long flags; 1760 1761 hmidi = substream->rmidi->private_data; 1762 spin_lock_irqsave (&hmidi->lock, flags); 1763 if (up) { 1764 if (!hmidi->istimer) { 1765 init_timer(&hmidi->timer); 1766 hmidi->timer.function = snd_hdspm_midi_output_timer; 1767 hmidi->timer.data = (unsigned long) hmidi; 1768 hmidi->timer.expires = 1 + jiffies; 1769 add_timer(&hmidi->timer); 1770 hmidi->istimer++; 1771 } 1772 } else { 1773 if (hmidi->istimer && --hmidi->istimer <= 0) 1774 del_timer (&hmidi->timer); 1775 } 1776 spin_unlock_irqrestore (&hmidi->lock, flags); 1777 if (up) 1778 snd_hdspm_midi_output_write(hmidi); 1779 } 1780 1781 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream) 1782 { 1783 struct hdspm_midi *hmidi; 1784 1785 hmidi = substream->rmidi->private_data; 1786 spin_lock_irq (&hmidi->lock); 1787 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id); 1788 hmidi->input = substream; 1789 spin_unlock_irq (&hmidi->lock); 1790 1791 return 0; 1792 } 1793 1794 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream) 1795 { 1796 struct hdspm_midi *hmidi; 1797 1798 hmidi = substream->rmidi->private_data; 1799 spin_lock_irq (&hmidi->lock); 1800 hmidi->output = substream; 1801 spin_unlock_irq (&hmidi->lock); 1802 1803 return 0; 1804 } 1805 1806 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream) 1807 { 1808 struct hdspm_midi *hmidi; 1809 1810 snd_hdspm_midi_input_trigger (substream, 0); 1811 1812 hmidi = substream->rmidi->private_data; 1813 spin_lock_irq (&hmidi->lock); 1814 hmidi->input = NULL; 1815 spin_unlock_irq (&hmidi->lock); 1816 1817 return 0; 1818 } 1819 1820 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream) 1821 { 1822 struct hdspm_midi *hmidi; 1823 1824 snd_hdspm_midi_output_trigger (substream, 0); 1825 1826 hmidi = substream->rmidi->private_data; 1827 spin_lock_irq (&hmidi->lock); 1828 hmidi->output = NULL; 1829 spin_unlock_irq (&hmidi->lock); 1830 1831 return 0; 1832 } 1833 1834 static struct snd_rawmidi_ops snd_hdspm_midi_output = 1835 { 1836 .open = snd_hdspm_midi_output_open, 1837 .close = snd_hdspm_midi_output_close, 1838 .trigger = snd_hdspm_midi_output_trigger, 1839 }; 1840 1841 static struct snd_rawmidi_ops snd_hdspm_midi_input = 1842 { 1843 .open = snd_hdspm_midi_input_open, 1844 .close = snd_hdspm_midi_input_close, 1845 .trigger = snd_hdspm_midi_input_trigger, 1846 }; 1847 1848 static int snd_hdspm_create_midi(struct snd_card *card, 1849 struct hdspm *hdspm, int id) 1850 { 1851 int err; 1852 char buf[32]; 1853 1854 hdspm->midi[id].id = id; 1855 hdspm->midi[id].hdspm = hdspm; 1856 spin_lock_init (&hdspm->midi[id].lock); 1857 1858 if (0 == id) { 1859 if (MADIface == hdspm->io_type) { 1860 /* MIDI-over-MADI on HDSPe MADIface */ 1861 hdspm->midi[0].dataIn = HDSPM_midiDataIn2; 1862 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2; 1863 hdspm->midi[0].dataOut = HDSPM_midiDataOut2; 1864 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2; 1865 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable; 1866 hdspm->midi[0].irq = HDSPM_midi2IRQPending; 1867 } else { 1868 hdspm->midi[0].dataIn = HDSPM_midiDataIn0; 1869 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0; 1870 hdspm->midi[0].dataOut = HDSPM_midiDataOut0; 1871 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0; 1872 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable; 1873 hdspm->midi[0].irq = HDSPM_midi0IRQPending; 1874 } 1875 } else if (1 == id) { 1876 hdspm->midi[1].dataIn = HDSPM_midiDataIn1; 1877 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1; 1878 hdspm->midi[1].dataOut = HDSPM_midiDataOut1; 1879 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1; 1880 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable; 1881 hdspm->midi[1].irq = HDSPM_midi1IRQPending; 1882 } else if ((2 == id) && (MADI == hdspm->io_type)) { 1883 /* MIDI-over-MADI on HDSPe MADI */ 1884 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1885 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1886 hdspm->midi[2].dataOut = HDSPM_midiDataOut2; 1887 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2; 1888 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1889 hdspm->midi[2].irq = HDSPM_midi2IRQPending; 1890 } else if (2 == id) { 1891 /* TCO MTC, read only */ 1892 hdspm->midi[2].dataIn = HDSPM_midiDataIn2; 1893 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2; 1894 hdspm->midi[2].dataOut = -1; 1895 hdspm->midi[2].statusOut = -1; 1896 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable; 1897 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES; 1898 } else if (3 == id) { 1899 /* TCO MTC on HDSPe MADI */ 1900 hdspm->midi[3].dataIn = HDSPM_midiDataIn3; 1901 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3; 1902 hdspm->midi[3].dataOut = -1; 1903 hdspm->midi[3].statusOut = -1; 1904 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable; 1905 hdspm->midi[3].irq = HDSPM_midi3IRQPending; 1906 } 1907 1908 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) || 1909 (MADIface == hdspm->io_type)))) { 1910 if ((id == 0) && (MADIface == hdspm->io_type)) { 1911 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1912 } else if ((id == 2) && (MADI == hdspm->io_type)) { 1913 sprintf(buf, "%s MIDIoverMADI", card->shortname); 1914 } else { 1915 sprintf(buf, "%s MIDI %d", card->shortname, id+1); 1916 } 1917 err = snd_rawmidi_new(card, buf, id, 1, 1, 1918 &hdspm->midi[id].rmidi); 1919 if (err < 0) 1920 return err; 1921 1922 sprintf(hdspm->midi[id].rmidi->name, "%s MIDI %d", 1923 card->id, id+1); 1924 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1925 1926 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1927 SNDRV_RAWMIDI_STREAM_OUTPUT, 1928 &snd_hdspm_midi_output); 1929 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1930 SNDRV_RAWMIDI_STREAM_INPUT, 1931 &snd_hdspm_midi_input); 1932 1933 hdspm->midi[id].rmidi->info_flags |= 1934 SNDRV_RAWMIDI_INFO_OUTPUT | 1935 SNDRV_RAWMIDI_INFO_INPUT | 1936 SNDRV_RAWMIDI_INFO_DUPLEX; 1937 } else { 1938 /* TCO MTC, read only */ 1939 sprintf(buf, "%s MTC %d", card->shortname, id+1); 1940 err = snd_rawmidi_new(card, buf, id, 1, 1, 1941 &hdspm->midi[id].rmidi); 1942 if (err < 0) 1943 return err; 1944 1945 sprintf(hdspm->midi[id].rmidi->name, 1946 "%s MTC %d", card->id, id+1); 1947 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id]; 1948 1949 snd_rawmidi_set_ops(hdspm->midi[id].rmidi, 1950 SNDRV_RAWMIDI_STREAM_INPUT, 1951 &snd_hdspm_midi_input); 1952 1953 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT; 1954 } 1955 1956 return 0; 1957 } 1958 1959 1960 static void hdspm_midi_tasklet(unsigned long arg) 1961 { 1962 struct hdspm *hdspm = (struct hdspm *)arg; 1963 int i = 0; 1964 1965 while (i < hdspm->midiPorts) { 1966 if (hdspm->midi[i].pending) 1967 snd_hdspm_midi_input_read(&hdspm->midi[i]); 1968 1969 i++; 1970 } 1971 } 1972 1973 1974 /*----------------------------------------------------------------------------- 1975 Status Interface 1976 ----------------------------------------------------------------------------*/ 1977 1978 /* get the system sample rate which is set */ 1979 1980 1981 /** 1982 * Calculate the real sample rate from the 1983 * current DDS value. 1984 **/ 1985 static int hdspm_get_system_sample_rate(struct hdspm *hdspm) 1986 { 1987 unsigned int period, rate; 1988 1989 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 1990 rate = hdspm_calc_dds_value(hdspm, period); 1991 1992 if (rate > 207000) { 1993 /* Unreasonable high sample rate as seen on PCI MADI cards. */ 1994 if (0 == hdspm_system_clock_mode(hdspm)) { 1995 /* master mode, return internal sample rate */ 1996 rate = hdspm->system_sample_rate; 1997 } else { 1998 /* slave mode, return external sample rate */ 1999 rate = hdspm_external_sample_rate(hdspm); 2000 } 2001 } 2002 2003 return rate; 2004 } 2005 2006 2007 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \ 2008 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2009 .name = xname, \ 2010 .index = xindex, \ 2011 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2012 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2013 .info = snd_hdspm_info_system_sample_rate, \ 2014 .put = snd_hdspm_put_system_sample_rate, \ 2015 .get = snd_hdspm_get_system_sample_rate \ 2016 } 2017 2018 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol, 2019 struct snd_ctl_elem_info *uinfo) 2020 { 2021 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2022 uinfo->count = 1; 2023 uinfo->value.integer.min = 27000; 2024 uinfo->value.integer.max = 207000; 2025 uinfo->value.integer.step = 1; 2026 return 0; 2027 } 2028 2029 2030 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol, 2031 struct snd_ctl_elem_value * 2032 ucontrol) 2033 { 2034 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2035 2036 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm); 2037 return 0; 2038 } 2039 2040 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol, 2041 struct snd_ctl_elem_value * 2042 ucontrol) 2043 { 2044 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2045 2046 hdspm_set_dds_value(hdspm, ucontrol->value.enumerated.item[0]); 2047 return 0; 2048 } 2049 2050 2051 /** 2052 * Returns the WordClock sample rate class for the given card. 2053 **/ 2054 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm) 2055 { 2056 int status; 2057 2058 switch (hdspm->io_type) { 2059 case RayDAT: 2060 case AIO: 2061 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2062 return (status >> 16) & 0xF; 2063 break; 2064 default: 2065 break; 2066 } 2067 2068 2069 return 0; 2070 } 2071 2072 2073 /** 2074 * Returns the TCO sample rate class for the given card. 2075 **/ 2076 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm) 2077 { 2078 int status; 2079 2080 if (hdspm->tco) { 2081 switch (hdspm->io_type) { 2082 case RayDAT: 2083 case AIO: 2084 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 2085 return (status >> 20) & 0xF; 2086 break; 2087 default: 2088 break; 2089 } 2090 } 2091 2092 return 0; 2093 } 2094 2095 2096 /** 2097 * Returns the SYNC_IN sample rate class for the given card. 2098 **/ 2099 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm) 2100 { 2101 int status; 2102 2103 if (hdspm->tco) { 2104 switch (hdspm->io_type) { 2105 case RayDAT: 2106 case AIO: 2107 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2108 return (status >> 12) & 0xF; 2109 break; 2110 default: 2111 break; 2112 } 2113 } 2114 2115 return 0; 2116 } 2117 2118 2119 /** 2120 * Returns the sample rate class for input source <idx> for 2121 * 'new style' cards like the AIO and RayDAT. 2122 **/ 2123 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx) 2124 { 2125 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2); 2126 2127 return (status >> (idx*4)) & 0xF; 2128 } 2129 2130 2131 2132 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 2133 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2134 .name = xname, \ 2135 .private_value = xindex, \ 2136 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2137 .info = snd_hdspm_info_autosync_sample_rate, \ 2138 .get = snd_hdspm_get_autosync_sample_rate \ 2139 } 2140 2141 2142 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2143 struct snd_ctl_elem_info *uinfo) 2144 { 2145 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2146 uinfo->count = 1; 2147 uinfo->value.enumerated.items = 10; 2148 2149 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2150 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2151 strcpy(uinfo->value.enumerated.name, 2152 texts_freq[uinfo->value.enumerated.item]); 2153 return 0; 2154 } 2155 2156 2157 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, 2158 struct snd_ctl_elem_value * 2159 ucontrol) 2160 { 2161 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2162 2163 switch (hdspm->io_type) { 2164 case RayDAT: 2165 switch (kcontrol->private_value) { 2166 case 0: 2167 ucontrol->value.enumerated.item[0] = 2168 hdspm_get_wc_sample_rate(hdspm); 2169 break; 2170 case 7: 2171 ucontrol->value.enumerated.item[0] = 2172 hdspm_get_tco_sample_rate(hdspm); 2173 break; 2174 case 8: 2175 ucontrol->value.enumerated.item[0] = 2176 hdspm_get_sync_in_sample_rate(hdspm); 2177 break; 2178 default: 2179 ucontrol->value.enumerated.item[0] = 2180 hdspm_get_s1_sample_rate(hdspm, 2181 kcontrol->private_value-1); 2182 } 2183 break; 2184 2185 case AIO: 2186 switch (kcontrol->private_value) { 2187 case 0: /* WC */ 2188 ucontrol->value.enumerated.item[0] = 2189 hdspm_get_wc_sample_rate(hdspm); 2190 break; 2191 case 4: /* TCO */ 2192 ucontrol->value.enumerated.item[0] = 2193 hdspm_get_tco_sample_rate(hdspm); 2194 break; 2195 case 5: /* SYNC_IN */ 2196 ucontrol->value.enumerated.item[0] = 2197 hdspm_get_sync_in_sample_rate(hdspm); 2198 break; 2199 default: 2200 ucontrol->value.enumerated.item[0] = 2201 hdspm_get_s1_sample_rate(hdspm, 2202 ucontrol->id.index-1); 2203 } 2204 break; 2205 2206 case AES32: 2207 2208 switch (kcontrol->private_value) { 2209 case 0: /* WC */ 2210 ucontrol->value.enumerated.item[0] = 2211 hdspm_get_wc_sample_rate(hdspm); 2212 break; 2213 case 9: /* TCO */ 2214 ucontrol->value.enumerated.item[0] = 2215 hdspm_get_tco_sample_rate(hdspm); 2216 break; 2217 case 10: /* SYNC_IN */ 2218 ucontrol->value.enumerated.item[0] = 2219 hdspm_get_sync_in_sample_rate(hdspm); 2220 break; 2221 default: /* AES1 to AES8 */ 2222 ucontrol->value.enumerated.item[0] = 2223 hdspm_get_s1_sample_rate(hdspm, 2224 kcontrol->private_value-1); 2225 break; 2226 } 2227 break; 2228 2229 case MADI: 2230 case MADIface: 2231 { 2232 int rate = hdspm_external_sample_rate(hdspm); 2233 int i, selected_rate = 0; 2234 for (i = 1; i < 10; i++) 2235 if (HDSPM_bit2freq(i) == rate) { 2236 selected_rate = i; 2237 break; 2238 } 2239 ucontrol->value.enumerated.item[0] = selected_rate; 2240 } 2241 break; 2242 2243 default: 2244 break; 2245 } 2246 2247 return 0; 2248 } 2249 2250 2251 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \ 2252 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2253 .name = xname, \ 2254 .index = xindex, \ 2255 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2256 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2257 .info = snd_hdspm_info_system_clock_mode, \ 2258 .get = snd_hdspm_get_system_clock_mode, \ 2259 .put = snd_hdspm_put_system_clock_mode, \ 2260 } 2261 2262 2263 /** 2264 * Returns the system clock mode for the given card. 2265 * @returns 0 - master, 1 - slave 2266 **/ 2267 static int hdspm_system_clock_mode(struct hdspm *hdspm) 2268 { 2269 switch (hdspm->io_type) { 2270 case AIO: 2271 case RayDAT: 2272 if (hdspm->settings_register & HDSPM_c0Master) 2273 return 0; 2274 break; 2275 2276 default: 2277 if (hdspm->control_register & HDSPM_ClockModeMaster) 2278 return 0; 2279 } 2280 2281 return 1; 2282 } 2283 2284 2285 /** 2286 * Sets the system clock mode. 2287 * @param mode 0 - master, 1 - slave 2288 **/ 2289 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode) 2290 { 2291 switch (hdspm->io_type) { 2292 case AIO: 2293 case RayDAT: 2294 if (0 == mode) 2295 hdspm->settings_register |= HDSPM_c0Master; 2296 else 2297 hdspm->settings_register &= ~HDSPM_c0Master; 2298 2299 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2300 break; 2301 2302 default: 2303 if (0 == mode) 2304 hdspm->control_register |= HDSPM_ClockModeMaster; 2305 else 2306 hdspm->control_register &= ~HDSPM_ClockModeMaster; 2307 2308 hdspm_write(hdspm, HDSPM_controlRegister, 2309 hdspm->control_register); 2310 } 2311 } 2312 2313 2314 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol, 2315 struct snd_ctl_elem_info *uinfo) 2316 { 2317 static char *texts[] = { "Master", "AutoSync" }; 2318 2319 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2320 uinfo->count = 1; 2321 uinfo->value.enumerated.items = 2; 2322 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2323 uinfo->value.enumerated.item = 2324 uinfo->value.enumerated.items - 1; 2325 strcpy(uinfo->value.enumerated.name, 2326 texts[uinfo->value.enumerated.item]); 2327 return 0; 2328 } 2329 2330 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol, 2331 struct snd_ctl_elem_value *ucontrol) 2332 { 2333 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2334 2335 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm); 2336 return 0; 2337 } 2338 2339 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol, 2340 struct snd_ctl_elem_value *ucontrol) 2341 { 2342 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2343 int val; 2344 2345 if (!snd_hdspm_use_is_exclusive(hdspm)) 2346 return -EBUSY; 2347 2348 val = ucontrol->value.enumerated.item[0]; 2349 if (val < 0) 2350 val = 0; 2351 else if (val > 1) 2352 val = 1; 2353 2354 hdspm_set_system_clock_mode(hdspm, val); 2355 2356 return 0; 2357 } 2358 2359 2360 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \ 2361 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2362 .name = xname, \ 2363 .index = xindex, \ 2364 .info = snd_hdspm_info_clock_source, \ 2365 .get = snd_hdspm_get_clock_source, \ 2366 .put = snd_hdspm_put_clock_source \ 2367 } 2368 2369 2370 static int hdspm_clock_source(struct hdspm * hdspm) 2371 { 2372 switch (hdspm->system_sample_rate) { 2373 case 32000: return 0; 2374 case 44100: return 1; 2375 case 48000: return 2; 2376 case 64000: return 3; 2377 case 88200: return 4; 2378 case 96000: return 5; 2379 case 128000: return 6; 2380 case 176400: return 7; 2381 case 192000: return 8; 2382 } 2383 2384 return -1; 2385 } 2386 2387 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode) 2388 { 2389 int rate; 2390 switch (mode) { 2391 case 0: 2392 rate = 32000; break; 2393 case 1: 2394 rate = 44100; break; 2395 case 2: 2396 rate = 48000; break; 2397 case 3: 2398 rate = 64000; break; 2399 case 4: 2400 rate = 88200; break; 2401 case 5: 2402 rate = 96000; break; 2403 case 6: 2404 rate = 128000; break; 2405 case 7: 2406 rate = 176400; break; 2407 case 8: 2408 rate = 192000; break; 2409 default: 2410 rate = 48000; 2411 } 2412 hdspm_set_rate(hdspm, rate, 1); 2413 return 0; 2414 } 2415 2416 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol, 2417 struct snd_ctl_elem_info *uinfo) 2418 { 2419 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2420 uinfo->count = 1; 2421 uinfo->value.enumerated.items = 9; 2422 2423 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2424 uinfo->value.enumerated.item = 2425 uinfo->value.enumerated.items - 1; 2426 2427 strcpy(uinfo->value.enumerated.name, 2428 texts_freq[uinfo->value.enumerated.item+1]); 2429 2430 return 0; 2431 } 2432 2433 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol, 2434 struct snd_ctl_elem_value *ucontrol) 2435 { 2436 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2437 2438 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm); 2439 return 0; 2440 } 2441 2442 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol, 2443 struct snd_ctl_elem_value *ucontrol) 2444 { 2445 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2446 int change; 2447 int val; 2448 2449 if (!snd_hdspm_use_is_exclusive(hdspm)) 2450 return -EBUSY; 2451 val = ucontrol->value.enumerated.item[0]; 2452 if (val < 0) 2453 val = 0; 2454 if (val > 9) 2455 val = 9; 2456 spin_lock_irq(&hdspm->lock); 2457 if (val != hdspm_clock_source(hdspm)) 2458 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0; 2459 else 2460 change = 0; 2461 spin_unlock_irq(&hdspm->lock); 2462 return change; 2463 } 2464 2465 2466 #define HDSPM_PREF_SYNC_REF(xname, xindex) \ 2467 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2468 .name = xname, \ 2469 .index = xindex, \ 2470 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 2471 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2472 .info = snd_hdspm_info_pref_sync_ref, \ 2473 .get = snd_hdspm_get_pref_sync_ref, \ 2474 .put = snd_hdspm_put_pref_sync_ref \ 2475 } 2476 2477 2478 /** 2479 * Returns the current preferred sync reference setting. 2480 * The semantics of the return value are depending on the 2481 * card, please see the comments for clarification. 2482 **/ 2483 static int hdspm_pref_sync_ref(struct hdspm * hdspm) 2484 { 2485 switch (hdspm->io_type) { 2486 case AES32: 2487 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2488 case 0: return 0; /* WC */ 2489 case HDSPM_SyncRef0: return 1; /* AES 1 */ 2490 case HDSPM_SyncRef1: return 2; /* AES 2 */ 2491 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */ 2492 case HDSPM_SyncRef2: return 4; /* AES 4 */ 2493 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */ 2494 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */ 2495 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0: 2496 return 7; /* AES 7 */ 2497 case HDSPM_SyncRef3: return 8; /* AES 8 */ 2498 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */ 2499 } 2500 break; 2501 2502 case MADI: 2503 case MADIface: 2504 if (hdspm->tco) { 2505 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2506 case 0: return 0; /* WC */ 2507 case HDSPM_SyncRef0: return 1; /* MADI */ 2508 case HDSPM_SyncRef1: return 2; /* TCO */ 2509 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2510 return 3; /* SYNC_IN */ 2511 } 2512 } else { 2513 switch (hdspm->control_register & HDSPM_SyncRefMask) { 2514 case 0: return 0; /* WC */ 2515 case HDSPM_SyncRef0: return 1; /* MADI */ 2516 case HDSPM_SyncRef1+HDSPM_SyncRef0: 2517 return 2; /* SYNC_IN */ 2518 } 2519 } 2520 break; 2521 2522 case RayDAT: 2523 if (hdspm->tco) { 2524 switch ((hdspm->settings_register & 2525 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2526 case 0: return 0; /* WC */ 2527 case 3: return 1; /* ADAT 1 */ 2528 case 4: return 2; /* ADAT 2 */ 2529 case 5: return 3; /* ADAT 3 */ 2530 case 6: return 4; /* ADAT 4 */ 2531 case 1: return 5; /* AES */ 2532 case 2: return 6; /* SPDIF */ 2533 case 9: return 7; /* TCO */ 2534 case 10: return 8; /* SYNC_IN */ 2535 } 2536 } else { 2537 switch ((hdspm->settings_register & 2538 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2539 case 0: return 0; /* WC */ 2540 case 3: return 1; /* ADAT 1 */ 2541 case 4: return 2; /* ADAT 2 */ 2542 case 5: return 3; /* ADAT 3 */ 2543 case 6: return 4; /* ADAT 4 */ 2544 case 1: return 5; /* AES */ 2545 case 2: return 6; /* SPDIF */ 2546 case 10: return 7; /* SYNC_IN */ 2547 } 2548 } 2549 2550 break; 2551 2552 case AIO: 2553 if (hdspm->tco) { 2554 switch ((hdspm->settings_register & 2555 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2556 case 0: return 0; /* WC */ 2557 case 3: return 1; /* ADAT */ 2558 case 1: return 2; /* AES */ 2559 case 2: return 3; /* SPDIF */ 2560 case 9: return 4; /* TCO */ 2561 case 10: return 5; /* SYNC_IN */ 2562 } 2563 } else { 2564 switch ((hdspm->settings_register & 2565 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) { 2566 case 0: return 0; /* WC */ 2567 case 3: return 1; /* ADAT */ 2568 case 1: return 2; /* AES */ 2569 case 2: return 3; /* SPDIF */ 2570 case 10: return 4; /* SYNC_IN */ 2571 } 2572 } 2573 2574 break; 2575 } 2576 2577 return -1; 2578 } 2579 2580 2581 /** 2582 * Set the preferred sync reference to <pref>. The semantics 2583 * of <pref> are depending on the card type, see the comments 2584 * for clarification. 2585 **/ 2586 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref) 2587 { 2588 int p = 0; 2589 2590 switch (hdspm->io_type) { 2591 case AES32: 2592 hdspm->control_register &= ~HDSPM_SyncRefMask; 2593 switch (pref) { 2594 case 0: /* WC */ 2595 break; 2596 case 1: /* AES 1 */ 2597 hdspm->control_register |= HDSPM_SyncRef0; 2598 break; 2599 case 2: /* AES 2 */ 2600 hdspm->control_register |= HDSPM_SyncRef1; 2601 break; 2602 case 3: /* AES 3 */ 2603 hdspm->control_register |= 2604 HDSPM_SyncRef1+HDSPM_SyncRef0; 2605 break; 2606 case 4: /* AES 4 */ 2607 hdspm->control_register |= HDSPM_SyncRef2; 2608 break; 2609 case 5: /* AES 5 */ 2610 hdspm->control_register |= 2611 HDSPM_SyncRef2+HDSPM_SyncRef0; 2612 break; 2613 case 6: /* AES 6 */ 2614 hdspm->control_register |= 2615 HDSPM_SyncRef2+HDSPM_SyncRef1; 2616 break; 2617 case 7: /* AES 7 */ 2618 hdspm->control_register |= 2619 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0; 2620 break; 2621 case 8: /* AES 8 */ 2622 hdspm->control_register |= HDSPM_SyncRef3; 2623 break; 2624 case 9: /* TCO */ 2625 hdspm->control_register |= 2626 HDSPM_SyncRef3+HDSPM_SyncRef0; 2627 break; 2628 default: 2629 return -1; 2630 } 2631 2632 break; 2633 2634 case MADI: 2635 case MADIface: 2636 hdspm->control_register &= ~HDSPM_SyncRefMask; 2637 if (hdspm->tco) { 2638 switch (pref) { 2639 case 0: /* WC */ 2640 break; 2641 case 1: /* MADI */ 2642 hdspm->control_register |= HDSPM_SyncRef0; 2643 break; 2644 case 2: /* TCO */ 2645 hdspm->control_register |= HDSPM_SyncRef1; 2646 break; 2647 case 3: /* SYNC_IN */ 2648 hdspm->control_register |= 2649 HDSPM_SyncRef0+HDSPM_SyncRef1; 2650 break; 2651 default: 2652 return -1; 2653 } 2654 } else { 2655 switch (pref) { 2656 case 0: /* WC */ 2657 break; 2658 case 1: /* MADI */ 2659 hdspm->control_register |= HDSPM_SyncRef0; 2660 break; 2661 case 2: /* SYNC_IN */ 2662 hdspm->control_register |= 2663 HDSPM_SyncRef0+HDSPM_SyncRef1; 2664 break; 2665 default: 2666 return -1; 2667 } 2668 } 2669 2670 break; 2671 2672 case RayDAT: 2673 if (hdspm->tco) { 2674 switch (pref) { 2675 case 0: p = 0; break; /* WC */ 2676 case 1: p = 3; break; /* ADAT 1 */ 2677 case 2: p = 4; break; /* ADAT 2 */ 2678 case 3: p = 5; break; /* ADAT 3 */ 2679 case 4: p = 6; break; /* ADAT 4 */ 2680 case 5: p = 1; break; /* AES */ 2681 case 6: p = 2; break; /* SPDIF */ 2682 case 7: p = 9; break; /* TCO */ 2683 case 8: p = 10; break; /* SYNC_IN */ 2684 default: return -1; 2685 } 2686 } else { 2687 switch (pref) { 2688 case 0: p = 0; break; /* WC */ 2689 case 1: p = 3; break; /* ADAT 1 */ 2690 case 2: p = 4; break; /* ADAT 2 */ 2691 case 3: p = 5; break; /* ADAT 3 */ 2692 case 4: p = 6; break; /* ADAT 4 */ 2693 case 5: p = 1; break; /* AES */ 2694 case 6: p = 2; break; /* SPDIF */ 2695 case 7: p = 10; break; /* SYNC_IN */ 2696 default: return -1; 2697 } 2698 } 2699 break; 2700 2701 case AIO: 2702 if (hdspm->tco) { 2703 switch (pref) { 2704 case 0: p = 0; break; /* WC */ 2705 case 1: p = 3; break; /* ADAT */ 2706 case 2: p = 1; break; /* AES */ 2707 case 3: p = 2; break; /* SPDIF */ 2708 case 4: p = 9; break; /* TCO */ 2709 case 5: p = 10; break; /* SYNC_IN */ 2710 default: return -1; 2711 } 2712 } else { 2713 switch (pref) { 2714 case 0: p = 0; break; /* WC */ 2715 case 1: p = 3; break; /* ADAT */ 2716 case 2: p = 1; break; /* AES */ 2717 case 3: p = 2; break; /* SPDIF */ 2718 case 4: p = 10; break; /* SYNC_IN */ 2719 default: return -1; 2720 } 2721 } 2722 break; 2723 } 2724 2725 switch (hdspm->io_type) { 2726 case RayDAT: 2727 case AIO: 2728 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask; 2729 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p; 2730 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 2731 break; 2732 2733 case MADI: 2734 case MADIface: 2735 case AES32: 2736 hdspm_write(hdspm, HDSPM_controlRegister, 2737 hdspm->control_register); 2738 } 2739 2740 return 0; 2741 } 2742 2743 2744 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol, 2745 struct snd_ctl_elem_info *uinfo) 2746 { 2747 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2748 2749 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2750 uinfo->count = 1; 2751 uinfo->value.enumerated.items = hdspm->texts_autosync_items; 2752 2753 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2754 uinfo->value.enumerated.item = 2755 uinfo->value.enumerated.items - 1; 2756 2757 strcpy(uinfo->value.enumerated.name, 2758 hdspm->texts_autosync[uinfo->value.enumerated.item]); 2759 2760 return 0; 2761 } 2762 2763 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol, 2764 struct snd_ctl_elem_value *ucontrol) 2765 { 2766 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2767 int psf = hdspm_pref_sync_ref(hdspm); 2768 2769 if (psf >= 0) { 2770 ucontrol->value.enumerated.item[0] = psf; 2771 return 0; 2772 } 2773 2774 return -1; 2775 } 2776 2777 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol, 2778 struct snd_ctl_elem_value *ucontrol) 2779 { 2780 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2781 int val, change = 0; 2782 2783 if (!snd_hdspm_use_is_exclusive(hdspm)) 2784 return -EBUSY; 2785 2786 val = ucontrol->value.enumerated.item[0]; 2787 2788 if (val < 0) 2789 val = 0; 2790 else if (val >= hdspm->texts_autosync_items) 2791 val = hdspm->texts_autosync_items-1; 2792 2793 spin_lock_irq(&hdspm->lock); 2794 if (val != hdspm_pref_sync_ref(hdspm)) 2795 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0; 2796 2797 spin_unlock_irq(&hdspm->lock); 2798 return change; 2799 } 2800 2801 2802 #define HDSPM_AUTOSYNC_REF(xname, xindex) \ 2803 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2804 .name = xname, \ 2805 .index = xindex, \ 2806 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2807 .info = snd_hdspm_info_autosync_ref, \ 2808 .get = snd_hdspm_get_autosync_ref, \ 2809 } 2810 2811 static int hdspm_autosync_ref(struct hdspm *hdspm) 2812 { 2813 if (AES32 == hdspm->io_type) { 2814 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister); 2815 unsigned int syncref = 2816 (status >> HDSPM_AES32_syncref_bit) & 0xF; 2817 if (syncref == 0) 2818 return HDSPM_AES32_AUTOSYNC_FROM_WORD; 2819 if (syncref <= 8) 2820 return syncref; 2821 return HDSPM_AES32_AUTOSYNC_FROM_NONE; 2822 } else if (MADI == hdspm->io_type) { 2823 /* This looks at the autosync selected sync reference */ 2824 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 2825 2826 switch (status2 & HDSPM_SelSyncRefMask) { 2827 case HDSPM_SelSyncRef_WORD: 2828 return HDSPM_AUTOSYNC_FROM_WORD; 2829 case HDSPM_SelSyncRef_MADI: 2830 return HDSPM_AUTOSYNC_FROM_MADI; 2831 case HDSPM_SelSyncRef_TCO: 2832 return HDSPM_AUTOSYNC_FROM_TCO; 2833 case HDSPM_SelSyncRef_SyncIn: 2834 return HDSPM_AUTOSYNC_FROM_SYNC_IN; 2835 case HDSPM_SelSyncRef_NVALID: 2836 return HDSPM_AUTOSYNC_FROM_NONE; 2837 default: 2838 return 0; 2839 } 2840 2841 } 2842 return 0; 2843 } 2844 2845 2846 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol, 2847 struct snd_ctl_elem_info *uinfo) 2848 { 2849 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2850 2851 if (AES32 == hdspm->io_type) { 2852 static char *texts[] = { "WordClock", "AES1", "AES2", "AES3", 2853 "AES4", "AES5", "AES6", "AES7", "AES8", "None"}; 2854 2855 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2856 uinfo->count = 1; 2857 uinfo->value.enumerated.items = 10; 2858 if (uinfo->value.enumerated.item >= 2859 uinfo->value.enumerated.items) 2860 uinfo->value.enumerated.item = 2861 uinfo->value.enumerated.items - 1; 2862 strcpy(uinfo->value.enumerated.name, 2863 texts[uinfo->value.enumerated.item]); 2864 } else if (MADI == hdspm->io_type) { 2865 static char *texts[] = {"Word Clock", "MADI", "TCO", 2866 "Sync In", "None" }; 2867 2868 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2869 uinfo->count = 1; 2870 uinfo->value.enumerated.items = 5; 2871 if (uinfo->value.enumerated.item >= 2872 uinfo->value.enumerated.items) 2873 uinfo->value.enumerated.item = 2874 uinfo->value.enumerated.items - 1; 2875 strcpy(uinfo->value.enumerated.name, 2876 texts[uinfo->value.enumerated.item]); 2877 } 2878 return 0; 2879 } 2880 2881 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol, 2882 struct snd_ctl_elem_value *ucontrol) 2883 { 2884 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2885 2886 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm); 2887 return 0; 2888 } 2889 2890 #define HDSPM_TOGGLE_SETTING(xname, xindex) \ 2891 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2892 .name = xname, \ 2893 .private_value = xindex, \ 2894 .info = snd_hdspm_info_toggle_setting, \ 2895 .get = snd_hdspm_get_toggle_setting, \ 2896 .put = snd_hdspm_put_toggle_setting \ 2897 } 2898 2899 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask) 2900 { 2901 return (hdspm->control_register & regmask) ? 1 : 0; 2902 } 2903 2904 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out) 2905 { 2906 if (out) 2907 hdspm->control_register |= regmask; 2908 else 2909 hdspm->control_register &= ~regmask; 2910 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2911 2912 return 0; 2913 } 2914 2915 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info 2916 2917 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol, 2918 struct snd_ctl_elem_value *ucontrol) 2919 { 2920 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2921 u32 regmask = kcontrol->private_value; 2922 2923 spin_lock_irq(&hdspm->lock); 2924 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask); 2925 spin_unlock_irq(&hdspm->lock); 2926 return 0; 2927 } 2928 2929 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol, 2930 struct snd_ctl_elem_value *ucontrol) 2931 { 2932 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2933 u32 regmask = kcontrol->private_value; 2934 int change; 2935 unsigned int val; 2936 2937 if (!snd_hdspm_use_is_exclusive(hdspm)) 2938 return -EBUSY; 2939 val = ucontrol->value.integer.value[0] & 1; 2940 spin_lock_irq(&hdspm->lock); 2941 change = (int) val != hdspm_toggle_setting(hdspm, regmask); 2942 hdspm_set_toggle_setting(hdspm, regmask, val); 2943 spin_unlock_irq(&hdspm->lock); 2944 return change; 2945 } 2946 2947 #define HDSPM_INPUT_SELECT(xname, xindex) \ 2948 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2949 .name = xname, \ 2950 .index = xindex, \ 2951 .info = snd_hdspm_info_input_select, \ 2952 .get = snd_hdspm_get_input_select, \ 2953 .put = snd_hdspm_put_input_select \ 2954 } 2955 2956 static int hdspm_input_select(struct hdspm * hdspm) 2957 { 2958 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0; 2959 } 2960 2961 static int hdspm_set_input_select(struct hdspm * hdspm, int out) 2962 { 2963 if (out) 2964 hdspm->control_register |= HDSPM_InputSelect0; 2965 else 2966 hdspm->control_register &= ~HDSPM_InputSelect0; 2967 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 2968 2969 return 0; 2970 } 2971 2972 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol, 2973 struct snd_ctl_elem_info *uinfo) 2974 { 2975 static char *texts[] = { "optical", "coaxial" }; 2976 2977 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2978 uinfo->count = 1; 2979 uinfo->value.enumerated.items = 2; 2980 2981 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2982 uinfo->value.enumerated.item = 2983 uinfo->value.enumerated.items - 1; 2984 strcpy(uinfo->value.enumerated.name, 2985 texts[uinfo->value.enumerated.item]); 2986 2987 return 0; 2988 } 2989 2990 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol, 2991 struct snd_ctl_elem_value *ucontrol) 2992 { 2993 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 2994 2995 spin_lock_irq(&hdspm->lock); 2996 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm); 2997 spin_unlock_irq(&hdspm->lock); 2998 return 0; 2999 } 3000 3001 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol, 3002 struct snd_ctl_elem_value *ucontrol) 3003 { 3004 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3005 int change; 3006 unsigned int val; 3007 3008 if (!snd_hdspm_use_is_exclusive(hdspm)) 3009 return -EBUSY; 3010 val = ucontrol->value.integer.value[0] & 1; 3011 spin_lock_irq(&hdspm->lock); 3012 change = (int) val != hdspm_input_select(hdspm); 3013 hdspm_set_input_select(hdspm, val); 3014 spin_unlock_irq(&hdspm->lock); 3015 return change; 3016 } 3017 3018 3019 #define HDSPM_DS_WIRE(xname, xindex) \ 3020 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3021 .name = xname, \ 3022 .index = xindex, \ 3023 .info = snd_hdspm_info_ds_wire, \ 3024 .get = snd_hdspm_get_ds_wire, \ 3025 .put = snd_hdspm_put_ds_wire \ 3026 } 3027 3028 static int hdspm_ds_wire(struct hdspm * hdspm) 3029 { 3030 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0; 3031 } 3032 3033 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds) 3034 { 3035 if (ds) 3036 hdspm->control_register |= HDSPM_DS_DoubleWire; 3037 else 3038 hdspm->control_register &= ~HDSPM_DS_DoubleWire; 3039 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3040 3041 return 0; 3042 } 3043 3044 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol, 3045 struct snd_ctl_elem_info *uinfo) 3046 { 3047 static char *texts[] = { "Single", "Double" }; 3048 3049 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3050 uinfo->count = 1; 3051 uinfo->value.enumerated.items = 2; 3052 3053 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3054 uinfo->value.enumerated.item = 3055 uinfo->value.enumerated.items - 1; 3056 strcpy(uinfo->value.enumerated.name, 3057 texts[uinfo->value.enumerated.item]); 3058 3059 return 0; 3060 } 3061 3062 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol, 3063 struct snd_ctl_elem_value *ucontrol) 3064 { 3065 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3066 3067 spin_lock_irq(&hdspm->lock); 3068 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm); 3069 spin_unlock_irq(&hdspm->lock); 3070 return 0; 3071 } 3072 3073 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol, 3074 struct snd_ctl_elem_value *ucontrol) 3075 { 3076 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3077 int change; 3078 unsigned int val; 3079 3080 if (!snd_hdspm_use_is_exclusive(hdspm)) 3081 return -EBUSY; 3082 val = ucontrol->value.integer.value[0] & 1; 3083 spin_lock_irq(&hdspm->lock); 3084 change = (int) val != hdspm_ds_wire(hdspm); 3085 hdspm_set_ds_wire(hdspm, val); 3086 spin_unlock_irq(&hdspm->lock); 3087 return change; 3088 } 3089 3090 3091 #define HDSPM_QS_WIRE(xname, xindex) \ 3092 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3093 .name = xname, \ 3094 .index = xindex, \ 3095 .info = snd_hdspm_info_qs_wire, \ 3096 .get = snd_hdspm_get_qs_wire, \ 3097 .put = snd_hdspm_put_qs_wire \ 3098 } 3099 3100 static int hdspm_qs_wire(struct hdspm * hdspm) 3101 { 3102 if (hdspm->control_register & HDSPM_QS_DoubleWire) 3103 return 1; 3104 if (hdspm->control_register & HDSPM_QS_QuadWire) 3105 return 2; 3106 return 0; 3107 } 3108 3109 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode) 3110 { 3111 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire); 3112 switch (mode) { 3113 case 0: 3114 break; 3115 case 1: 3116 hdspm->control_register |= HDSPM_QS_DoubleWire; 3117 break; 3118 case 2: 3119 hdspm->control_register |= HDSPM_QS_QuadWire; 3120 break; 3121 } 3122 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3123 3124 return 0; 3125 } 3126 3127 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol, 3128 struct snd_ctl_elem_info *uinfo) 3129 { 3130 static char *texts[] = { "Single", "Double", "Quad" }; 3131 3132 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3133 uinfo->count = 1; 3134 uinfo->value.enumerated.items = 3; 3135 3136 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3137 uinfo->value.enumerated.item = 3138 uinfo->value.enumerated.items - 1; 3139 strcpy(uinfo->value.enumerated.name, 3140 texts[uinfo->value.enumerated.item]); 3141 3142 return 0; 3143 } 3144 3145 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol, 3146 struct snd_ctl_elem_value *ucontrol) 3147 { 3148 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3149 3150 spin_lock_irq(&hdspm->lock); 3151 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm); 3152 spin_unlock_irq(&hdspm->lock); 3153 return 0; 3154 } 3155 3156 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol, 3157 struct snd_ctl_elem_value *ucontrol) 3158 { 3159 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3160 int change; 3161 int val; 3162 3163 if (!snd_hdspm_use_is_exclusive(hdspm)) 3164 return -EBUSY; 3165 val = ucontrol->value.integer.value[0]; 3166 if (val < 0) 3167 val = 0; 3168 if (val > 2) 3169 val = 2; 3170 spin_lock_irq(&hdspm->lock); 3171 change = val != hdspm_qs_wire(hdspm); 3172 hdspm_set_qs_wire(hdspm, val); 3173 spin_unlock_irq(&hdspm->lock); 3174 return change; 3175 } 3176 3177 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \ 3178 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3179 .name = xname, \ 3180 .index = xindex, \ 3181 .info = snd_hdspm_info_madi_speedmode, \ 3182 .get = snd_hdspm_get_madi_speedmode, \ 3183 .put = snd_hdspm_put_madi_speedmode \ 3184 } 3185 3186 static int hdspm_madi_speedmode(struct hdspm *hdspm) 3187 { 3188 if (hdspm->control_register & HDSPM_QuadSpeed) 3189 return 2; 3190 if (hdspm->control_register & HDSPM_DoubleSpeed) 3191 return 1; 3192 return 0; 3193 } 3194 3195 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode) 3196 { 3197 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed); 3198 switch (mode) { 3199 case 0: 3200 break; 3201 case 1: 3202 hdspm->control_register |= HDSPM_DoubleSpeed; 3203 break; 3204 case 2: 3205 hdspm->control_register |= HDSPM_QuadSpeed; 3206 break; 3207 } 3208 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 3209 3210 return 0; 3211 } 3212 3213 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol, 3214 struct snd_ctl_elem_info *uinfo) 3215 { 3216 static char *texts[] = { "Single", "Double", "Quad" }; 3217 3218 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3219 uinfo->count = 1; 3220 uinfo->value.enumerated.items = 3; 3221 3222 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3223 uinfo->value.enumerated.item = 3224 uinfo->value.enumerated.items - 1; 3225 strcpy(uinfo->value.enumerated.name, 3226 texts[uinfo->value.enumerated.item]); 3227 3228 return 0; 3229 } 3230 3231 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol, 3232 struct snd_ctl_elem_value *ucontrol) 3233 { 3234 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3235 3236 spin_lock_irq(&hdspm->lock); 3237 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm); 3238 spin_unlock_irq(&hdspm->lock); 3239 return 0; 3240 } 3241 3242 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol, 3243 struct snd_ctl_elem_value *ucontrol) 3244 { 3245 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3246 int change; 3247 int val; 3248 3249 if (!snd_hdspm_use_is_exclusive(hdspm)) 3250 return -EBUSY; 3251 val = ucontrol->value.integer.value[0]; 3252 if (val < 0) 3253 val = 0; 3254 if (val > 2) 3255 val = 2; 3256 spin_lock_irq(&hdspm->lock); 3257 change = val != hdspm_madi_speedmode(hdspm); 3258 hdspm_set_madi_speedmode(hdspm, val); 3259 spin_unlock_irq(&hdspm->lock); 3260 return change; 3261 } 3262 3263 #define HDSPM_MIXER(xname, xindex) \ 3264 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 3265 .name = xname, \ 3266 .index = xindex, \ 3267 .device = 0, \ 3268 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 3269 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3270 .info = snd_hdspm_info_mixer, \ 3271 .get = snd_hdspm_get_mixer, \ 3272 .put = snd_hdspm_put_mixer \ 3273 } 3274 3275 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol, 3276 struct snd_ctl_elem_info *uinfo) 3277 { 3278 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3279 uinfo->count = 3; 3280 uinfo->value.integer.min = 0; 3281 uinfo->value.integer.max = 65535; 3282 uinfo->value.integer.step = 1; 3283 return 0; 3284 } 3285 3286 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol, 3287 struct snd_ctl_elem_value *ucontrol) 3288 { 3289 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3290 int source; 3291 int destination; 3292 3293 source = ucontrol->value.integer.value[0]; 3294 if (source < 0) 3295 source = 0; 3296 else if (source >= 2 * HDSPM_MAX_CHANNELS) 3297 source = 2 * HDSPM_MAX_CHANNELS - 1; 3298 3299 destination = ucontrol->value.integer.value[1]; 3300 if (destination < 0) 3301 destination = 0; 3302 else if (destination >= HDSPM_MAX_CHANNELS) 3303 destination = HDSPM_MAX_CHANNELS - 1; 3304 3305 spin_lock_irq(&hdspm->lock); 3306 if (source >= HDSPM_MAX_CHANNELS) 3307 ucontrol->value.integer.value[2] = 3308 hdspm_read_pb_gain(hdspm, destination, 3309 source - HDSPM_MAX_CHANNELS); 3310 else 3311 ucontrol->value.integer.value[2] = 3312 hdspm_read_in_gain(hdspm, destination, source); 3313 3314 spin_unlock_irq(&hdspm->lock); 3315 3316 return 0; 3317 } 3318 3319 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol, 3320 struct snd_ctl_elem_value *ucontrol) 3321 { 3322 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3323 int change; 3324 int source; 3325 int destination; 3326 int gain; 3327 3328 if (!snd_hdspm_use_is_exclusive(hdspm)) 3329 return -EBUSY; 3330 3331 source = ucontrol->value.integer.value[0]; 3332 destination = ucontrol->value.integer.value[1]; 3333 3334 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS) 3335 return -1; 3336 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS) 3337 return -1; 3338 3339 gain = ucontrol->value.integer.value[2]; 3340 3341 spin_lock_irq(&hdspm->lock); 3342 3343 if (source >= HDSPM_MAX_CHANNELS) 3344 change = gain != hdspm_read_pb_gain(hdspm, destination, 3345 source - 3346 HDSPM_MAX_CHANNELS); 3347 else 3348 change = gain != hdspm_read_in_gain(hdspm, destination, 3349 source); 3350 3351 if (change) { 3352 if (source >= HDSPM_MAX_CHANNELS) 3353 hdspm_write_pb_gain(hdspm, destination, 3354 source - HDSPM_MAX_CHANNELS, 3355 gain); 3356 else 3357 hdspm_write_in_gain(hdspm, destination, source, 3358 gain); 3359 } 3360 spin_unlock_irq(&hdspm->lock); 3361 3362 return change; 3363 } 3364 3365 /* The simple mixer control(s) provide gain control for the 3366 basic 1:1 mappings of playback streams to output 3367 streams. 3368 */ 3369 3370 #define HDSPM_PLAYBACK_MIXER \ 3371 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3372 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \ 3373 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3374 .info = snd_hdspm_info_playback_mixer, \ 3375 .get = snd_hdspm_get_playback_mixer, \ 3376 .put = snd_hdspm_put_playback_mixer \ 3377 } 3378 3379 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol, 3380 struct snd_ctl_elem_info *uinfo) 3381 { 3382 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3383 uinfo->count = 1; 3384 uinfo->value.integer.min = 0; 3385 uinfo->value.integer.max = 64; 3386 uinfo->value.integer.step = 1; 3387 return 0; 3388 } 3389 3390 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol, 3391 struct snd_ctl_elem_value *ucontrol) 3392 { 3393 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3394 int channel; 3395 3396 channel = ucontrol->id.index - 1; 3397 3398 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3399 return -EINVAL; 3400 3401 spin_lock_irq(&hdspm->lock); 3402 ucontrol->value.integer.value[0] = 3403 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN; 3404 spin_unlock_irq(&hdspm->lock); 3405 3406 return 0; 3407 } 3408 3409 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol, 3410 struct snd_ctl_elem_value *ucontrol) 3411 { 3412 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3413 int change; 3414 int channel; 3415 int gain; 3416 3417 if (!snd_hdspm_use_is_exclusive(hdspm)) 3418 return -EBUSY; 3419 3420 channel = ucontrol->id.index - 1; 3421 3422 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS)) 3423 return -EINVAL; 3424 3425 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64; 3426 3427 spin_lock_irq(&hdspm->lock); 3428 change = 3429 gain != hdspm_read_pb_gain(hdspm, channel, 3430 channel); 3431 if (change) 3432 hdspm_write_pb_gain(hdspm, channel, channel, 3433 gain); 3434 spin_unlock_irq(&hdspm->lock); 3435 return change; 3436 } 3437 3438 #define HDSPM_SYNC_CHECK(xname, xindex) \ 3439 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3440 .name = xname, \ 3441 .private_value = xindex, \ 3442 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3443 .info = snd_hdspm_info_sync_check, \ 3444 .get = snd_hdspm_get_sync_check \ 3445 } 3446 3447 3448 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol, 3449 struct snd_ctl_elem_info *uinfo) 3450 { 3451 static char *texts[] = { "No Lock", "Lock", "Sync", "N/A" }; 3452 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3453 uinfo->count = 1; 3454 uinfo->value.enumerated.items = 4; 3455 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3456 uinfo->value.enumerated.item = 3457 uinfo->value.enumerated.items - 1; 3458 strcpy(uinfo->value.enumerated.name, 3459 texts[uinfo->value.enumerated.item]); 3460 return 0; 3461 } 3462 3463 static int hdspm_wc_sync_check(struct hdspm *hdspm) 3464 { 3465 int status, status2; 3466 3467 switch (hdspm->io_type) { 3468 case AES32: 3469 status = hdspm_read(hdspm, HDSPM_statusRegister); 3470 if (status & HDSPM_wcSync) 3471 return 2; 3472 else if (status & HDSPM_wcLock) 3473 return 1; 3474 return 0; 3475 break; 3476 3477 case MADI: 3478 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3479 if (status2 & HDSPM_wcLock) { 3480 if (status2 & HDSPM_wcSync) 3481 return 2; 3482 else 3483 return 1; 3484 } 3485 return 0; 3486 break; 3487 3488 case RayDAT: 3489 case AIO: 3490 status = hdspm_read(hdspm, HDSPM_statusRegister); 3491 3492 if (status & 0x2000000) 3493 return 2; 3494 else if (status & 0x1000000) 3495 return 1; 3496 return 0; 3497 3498 break; 3499 3500 case MADIface: 3501 break; 3502 } 3503 3504 3505 return 3; 3506 } 3507 3508 3509 static int hdspm_madi_sync_check(struct hdspm *hdspm) 3510 { 3511 int status = hdspm_read(hdspm, HDSPM_statusRegister); 3512 if (status & HDSPM_madiLock) { 3513 if (status & HDSPM_madiSync) 3514 return 2; 3515 else 3516 return 1; 3517 } 3518 return 0; 3519 } 3520 3521 3522 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx) 3523 { 3524 int status, lock, sync; 3525 3526 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3527 3528 lock = (status & (0x1<<idx)) ? 1 : 0; 3529 sync = (status & (0x100<<idx)) ? 1 : 0; 3530 3531 if (lock && sync) 3532 return 2; 3533 else if (lock) 3534 return 1; 3535 return 0; 3536 } 3537 3538 3539 static int hdspm_sync_in_sync_check(struct hdspm *hdspm) 3540 { 3541 int status, lock = 0, sync = 0; 3542 3543 switch (hdspm->io_type) { 3544 case RayDAT: 3545 case AIO: 3546 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3); 3547 lock = (status & 0x400) ? 1 : 0; 3548 sync = (status & 0x800) ? 1 : 0; 3549 break; 3550 3551 case MADI: 3552 status = hdspm_read(hdspm, HDSPM_statusRegister); 3553 lock = (status & HDSPM_syncInLock) ? 1 : 0; 3554 sync = (status & HDSPM_syncInSync) ? 1 : 0; 3555 break; 3556 3557 case AES32: 3558 status = hdspm_read(hdspm, HDSPM_statusRegister2); 3559 lock = (status & 0x100000) ? 1 : 0; 3560 sync = (status & 0x200000) ? 1 : 0; 3561 break; 3562 3563 case MADIface: 3564 break; 3565 } 3566 3567 if (lock && sync) 3568 return 2; 3569 else if (lock) 3570 return 1; 3571 3572 return 0; 3573 } 3574 3575 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx) 3576 { 3577 int status2, lock, sync; 3578 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 3579 3580 lock = (status2 & (0x0080 >> idx)) ? 1 : 0; 3581 sync = (status2 & (0x8000 >> idx)) ? 1 : 0; 3582 3583 if (sync) 3584 return 2; 3585 else if (lock) 3586 return 1; 3587 return 0; 3588 } 3589 3590 3591 static int hdspm_tco_sync_check(struct hdspm *hdspm) 3592 { 3593 int status; 3594 3595 if (hdspm->tco) { 3596 switch (hdspm->io_type) { 3597 case MADI: 3598 case AES32: 3599 status = hdspm_read(hdspm, HDSPM_statusRegister); 3600 if (status & HDSPM_tcoLock) { 3601 if (status & HDSPM_tcoSync) 3602 return 2; 3603 else 3604 return 1; 3605 } 3606 return 0; 3607 3608 break; 3609 3610 case RayDAT: 3611 case AIO: 3612 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1); 3613 3614 if (status & 0x8000000) 3615 return 2; /* Sync */ 3616 if (status & 0x4000000) 3617 return 1; /* Lock */ 3618 return 0; /* No signal */ 3619 break; 3620 3621 default: 3622 break; 3623 } 3624 } 3625 3626 return 3; /* N/A */ 3627 } 3628 3629 3630 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol, 3631 struct snd_ctl_elem_value *ucontrol) 3632 { 3633 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3634 int val = -1; 3635 3636 switch (hdspm->io_type) { 3637 case RayDAT: 3638 switch (kcontrol->private_value) { 3639 case 0: /* WC */ 3640 val = hdspm_wc_sync_check(hdspm); break; 3641 case 7: /* TCO */ 3642 val = hdspm_tco_sync_check(hdspm); break; 3643 case 8: /* SYNC IN */ 3644 val = hdspm_sync_in_sync_check(hdspm); break; 3645 default: 3646 val = hdspm_s1_sync_check(hdspm, 3647 kcontrol->private_value-1); 3648 } 3649 break; 3650 3651 case AIO: 3652 switch (kcontrol->private_value) { 3653 case 0: /* WC */ 3654 val = hdspm_wc_sync_check(hdspm); break; 3655 case 4: /* TCO */ 3656 val = hdspm_tco_sync_check(hdspm); break; 3657 case 5: /* SYNC IN */ 3658 val = hdspm_sync_in_sync_check(hdspm); break; 3659 default: 3660 val = hdspm_s1_sync_check(hdspm, ucontrol->id.index-1); 3661 } 3662 break; 3663 3664 case MADI: 3665 switch (kcontrol->private_value) { 3666 case 0: /* WC */ 3667 val = hdspm_wc_sync_check(hdspm); break; 3668 case 1: /* MADI */ 3669 val = hdspm_madi_sync_check(hdspm); break; 3670 case 2: /* TCO */ 3671 val = hdspm_tco_sync_check(hdspm); break; 3672 case 3: /* SYNC_IN */ 3673 val = hdspm_sync_in_sync_check(hdspm); break; 3674 } 3675 break; 3676 3677 case MADIface: 3678 val = hdspm_madi_sync_check(hdspm); /* MADI */ 3679 break; 3680 3681 case AES32: 3682 switch (kcontrol->private_value) { 3683 case 0: /* WC */ 3684 val = hdspm_wc_sync_check(hdspm); break; 3685 case 9: /* TCO */ 3686 val = hdspm_tco_sync_check(hdspm); break; 3687 case 10 /* SYNC IN */: 3688 val = hdspm_sync_in_sync_check(hdspm); break; 3689 default: /* AES1 to AES8 */ 3690 val = hdspm_aes_sync_check(hdspm, 3691 kcontrol->private_value-1); 3692 } 3693 break; 3694 3695 } 3696 3697 if (-1 == val) 3698 val = 3; 3699 3700 ucontrol->value.enumerated.item[0] = val; 3701 return 0; 3702 } 3703 3704 3705 3706 /** 3707 * TCO controls 3708 **/ 3709 static void hdspm_tco_write(struct hdspm *hdspm) 3710 { 3711 unsigned int tc[4] = { 0, 0, 0, 0}; 3712 3713 switch (hdspm->tco->input) { 3714 case 0: 3715 tc[2] |= HDSPM_TCO2_set_input_MSB; 3716 break; 3717 case 1: 3718 tc[2] |= HDSPM_TCO2_set_input_LSB; 3719 break; 3720 default: 3721 break; 3722 } 3723 3724 switch (hdspm->tco->framerate) { 3725 case 1: 3726 tc[1] |= HDSPM_TCO1_LTC_Format_LSB; 3727 break; 3728 case 2: 3729 tc[1] |= HDSPM_TCO1_LTC_Format_MSB; 3730 break; 3731 case 3: 3732 tc[1] |= HDSPM_TCO1_LTC_Format_MSB + 3733 HDSPM_TCO1_set_drop_frame_flag; 3734 break; 3735 case 4: 3736 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3737 HDSPM_TCO1_LTC_Format_MSB; 3738 break; 3739 case 5: 3740 tc[1] |= HDSPM_TCO1_LTC_Format_LSB + 3741 HDSPM_TCO1_LTC_Format_MSB + 3742 HDSPM_TCO1_set_drop_frame_flag; 3743 break; 3744 default: 3745 break; 3746 } 3747 3748 switch (hdspm->tco->wordclock) { 3749 case 1: 3750 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB; 3751 break; 3752 case 2: 3753 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB; 3754 break; 3755 default: 3756 break; 3757 } 3758 3759 switch (hdspm->tco->samplerate) { 3760 case 1: 3761 tc[2] |= HDSPM_TCO2_set_freq; 3762 break; 3763 case 2: 3764 tc[2] |= HDSPM_TCO2_set_freq_from_app; 3765 break; 3766 default: 3767 break; 3768 } 3769 3770 switch (hdspm->tco->pull) { 3771 case 1: 3772 tc[2] |= HDSPM_TCO2_set_pull_up; 3773 break; 3774 case 2: 3775 tc[2] |= HDSPM_TCO2_set_pull_down; 3776 break; 3777 case 3: 3778 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4; 3779 break; 3780 case 4: 3781 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4; 3782 break; 3783 default: 3784 break; 3785 } 3786 3787 if (1 == hdspm->tco->term) { 3788 tc[2] |= HDSPM_TCO2_set_term_75R; 3789 } 3790 3791 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]); 3792 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]); 3793 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]); 3794 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]); 3795 } 3796 3797 3798 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \ 3799 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3800 .name = xname, \ 3801 .index = xindex, \ 3802 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3803 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3804 .info = snd_hdspm_info_tco_sample_rate, \ 3805 .get = snd_hdspm_get_tco_sample_rate, \ 3806 .put = snd_hdspm_put_tco_sample_rate \ 3807 } 3808 3809 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol, 3810 struct snd_ctl_elem_info *uinfo) 3811 { 3812 static char *texts[] = { "44.1 kHz", "48 kHz" }; 3813 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3814 uinfo->count = 1; 3815 uinfo->value.enumerated.items = 2; 3816 3817 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3818 uinfo->value.enumerated.item = 3819 uinfo->value.enumerated.items - 1; 3820 3821 strcpy(uinfo->value.enumerated.name, 3822 texts[uinfo->value.enumerated.item]); 3823 3824 return 0; 3825 } 3826 3827 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol, 3828 struct snd_ctl_elem_value *ucontrol) 3829 { 3830 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3831 3832 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate; 3833 3834 return 0; 3835 } 3836 3837 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol, 3838 struct snd_ctl_elem_value *ucontrol) 3839 { 3840 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3841 3842 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) { 3843 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0]; 3844 3845 hdspm_tco_write(hdspm); 3846 3847 return 1; 3848 } 3849 3850 return 0; 3851 } 3852 3853 3854 #define HDSPM_TCO_PULL(xname, xindex) \ 3855 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3856 .name = xname, \ 3857 .index = xindex, \ 3858 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3859 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3860 .info = snd_hdspm_info_tco_pull, \ 3861 .get = snd_hdspm_get_tco_pull, \ 3862 .put = snd_hdspm_put_tco_pull \ 3863 } 3864 3865 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol, 3866 struct snd_ctl_elem_info *uinfo) 3867 { 3868 static char *texts[] = { "0", "+ 0.1 %", "- 0.1 %", "+ 4 %", "- 4 %" }; 3869 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3870 uinfo->count = 1; 3871 uinfo->value.enumerated.items = 5; 3872 3873 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3874 uinfo->value.enumerated.item = 3875 uinfo->value.enumerated.items - 1; 3876 3877 strcpy(uinfo->value.enumerated.name, 3878 texts[uinfo->value.enumerated.item]); 3879 3880 return 0; 3881 } 3882 3883 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol, 3884 struct snd_ctl_elem_value *ucontrol) 3885 { 3886 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3887 3888 ucontrol->value.enumerated.item[0] = hdspm->tco->pull; 3889 3890 return 0; 3891 } 3892 3893 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol, 3894 struct snd_ctl_elem_value *ucontrol) 3895 { 3896 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3897 3898 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) { 3899 hdspm->tco->pull = ucontrol->value.enumerated.item[0]; 3900 3901 hdspm_tco_write(hdspm); 3902 3903 return 1; 3904 } 3905 3906 return 0; 3907 } 3908 3909 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \ 3910 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3911 .name = xname, \ 3912 .index = xindex, \ 3913 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3914 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3915 .info = snd_hdspm_info_tco_wck_conversion, \ 3916 .get = snd_hdspm_get_tco_wck_conversion, \ 3917 .put = snd_hdspm_put_tco_wck_conversion \ 3918 } 3919 3920 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol, 3921 struct snd_ctl_elem_info *uinfo) 3922 { 3923 static char *texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" }; 3924 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3925 uinfo->count = 1; 3926 uinfo->value.enumerated.items = 3; 3927 3928 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3929 uinfo->value.enumerated.item = 3930 uinfo->value.enumerated.items - 1; 3931 3932 strcpy(uinfo->value.enumerated.name, 3933 texts[uinfo->value.enumerated.item]); 3934 3935 return 0; 3936 } 3937 3938 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol, 3939 struct snd_ctl_elem_value *ucontrol) 3940 { 3941 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3942 3943 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock; 3944 3945 return 0; 3946 } 3947 3948 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol, 3949 struct snd_ctl_elem_value *ucontrol) 3950 { 3951 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3952 3953 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) { 3954 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0]; 3955 3956 hdspm_tco_write(hdspm); 3957 3958 return 1; 3959 } 3960 3961 return 0; 3962 } 3963 3964 3965 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \ 3966 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3967 .name = xname, \ 3968 .index = xindex, \ 3969 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 3970 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3971 .info = snd_hdspm_info_tco_frame_rate, \ 3972 .get = snd_hdspm_get_tco_frame_rate, \ 3973 .put = snd_hdspm_put_tco_frame_rate \ 3974 } 3975 3976 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol, 3977 struct snd_ctl_elem_info *uinfo) 3978 { 3979 static char *texts[] = { "24 fps", "25 fps", "29.97fps", 3980 "29.97 dfps", "30 fps", "30 dfps" }; 3981 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 3982 uinfo->count = 1; 3983 uinfo->value.enumerated.items = 6; 3984 3985 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 3986 uinfo->value.enumerated.item = 3987 uinfo->value.enumerated.items - 1; 3988 3989 strcpy(uinfo->value.enumerated.name, 3990 texts[uinfo->value.enumerated.item]); 3991 3992 return 0; 3993 } 3994 3995 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol, 3996 struct snd_ctl_elem_value *ucontrol) 3997 { 3998 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 3999 4000 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate; 4001 4002 return 0; 4003 } 4004 4005 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol, 4006 struct snd_ctl_elem_value *ucontrol) 4007 { 4008 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4009 4010 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) { 4011 hdspm->tco->framerate = ucontrol->value.enumerated.item[0]; 4012 4013 hdspm_tco_write(hdspm); 4014 4015 return 1; 4016 } 4017 4018 return 0; 4019 } 4020 4021 4022 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \ 4023 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4024 .name = xname, \ 4025 .index = xindex, \ 4026 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4027 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4028 .info = snd_hdspm_info_tco_sync_source, \ 4029 .get = snd_hdspm_get_tco_sync_source, \ 4030 .put = snd_hdspm_put_tco_sync_source \ 4031 } 4032 4033 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol, 4034 struct snd_ctl_elem_info *uinfo) 4035 { 4036 static char *texts[] = { "LTC", "Video", "WCK" }; 4037 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 4038 uinfo->count = 1; 4039 uinfo->value.enumerated.items = 3; 4040 4041 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 4042 uinfo->value.enumerated.item = 4043 uinfo->value.enumerated.items - 1; 4044 4045 strcpy(uinfo->value.enumerated.name, 4046 texts[uinfo->value.enumerated.item]); 4047 4048 return 0; 4049 } 4050 4051 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol, 4052 struct snd_ctl_elem_value *ucontrol) 4053 { 4054 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4055 4056 ucontrol->value.enumerated.item[0] = hdspm->tco->input; 4057 4058 return 0; 4059 } 4060 4061 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol, 4062 struct snd_ctl_elem_value *ucontrol) 4063 { 4064 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4065 4066 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) { 4067 hdspm->tco->input = ucontrol->value.enumerated.item[0]; 4068 4069 hdspm_tco_write(hdspm); 4070 4071 return 1; 4072 } 4073 4074 return 0; 4075 } 4076 4077 4078 #define HDSPM_TCO_WORD_TERM(xname, xindex) \ 4079 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 4080 .name = xname, \ 4081 .index = xindex, \ 4082 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\ 4083 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 4084 .info = snd_hdspm_info_tco_word_term, \ 4085 .get = snd_hdspm_get_tco_word_term, \ 4086 .put = snd_hdspm_put_tco_word_term \ 4087 } 4088 4089 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol, 4090 struct snd_ctl_elem_info *uinfo) 4091 { 4092 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; 4093 uinfo->count = 1; 4094 uinfo->value.integer.min = 0; 4095 uinfo->value.integer.max = 1; 4096 4097 return 0; 4098 } 4099 4100 4101 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol, 4102 struct snd_ctl_elem_value *ucontrol) 4103 { 4104 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4105 4106 ucontrol->value.enumerated.item[0] = hdspm->tco->term; 4107 4108 return 0; 4109 } 4110 4111 4112 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol, 4113 struct snd_ctl_elem_value *ucontrol) 4114 { 4115 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol); 4116 4117 if (hdspm->tco->term != ucontrol->value.enumerated.item[0]) { 4118 hdspm->tco->term = ucontrol->value.enumerated.item[0]; 4119 4120 hdspm_tco_write(hdspm); 4121 4122 return 1; 4123 } 4124 4125 return 0; 4126 } 4127 4128 4129 4130 4131 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = { 4132 HDSPM_MIXER("Mixer", 0), 4133 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4134 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4135 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4136 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4137 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4138 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4139 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4140 HDSPM_SYNC_CHECK("MADI SyncCheck", 1), 4141 HDSPM_SYNC_CHECK("TCO SyncCheck", 2), 4142 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3), 4143 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4144 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4145 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4146 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4147 HDSPM_INPUT_SELECT("Input Select", 0), 4148 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4149 }; 4150 4151 4152 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = { 4153 HDSPM_MIXER("Mixer", 0), 4154 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4155 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4156 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4157 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4158 HDSPM_SYNC_CHECK("MADI SyncCheck", 0), 4159 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch), 4160 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4161 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp), 4162 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0) 4163 }; 4164 4165 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = { 4166 HDSPM_MIXER("Mixer", 0), 4167 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4168 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4169 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4170 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4171 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4172 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4173 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4174 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4175 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4176 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3), 4177 HDSPM_SYNC_CHECK("TCO SyncCheck", 4), 4178 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5), 4179 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4180 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4181 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4182 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3), 4183 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4), 4184 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5) 4185 4186 /* 4187 HDSPM_INPUT_SELECT("Input Select", 0), 4188 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0), 4189 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0); 4190 HDSPM_SPDIF_IN("SPDIF In", 0); 4191 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0); 4192 HDSPM_INPUT_LEVEL("Input Level", 0); 4193 HDSPM_OUTPUT_LEVEL("Output Level", 0); 4194 HDSPM_PHONES("Phones", 0); 4195 */ 4196 }; 4197 4198 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = { 4199 HDSPM_MIXER("Mixer", 0), 4200 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4201 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0), 4202 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0), 4203 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4204 HDSPM_SYNC_CHECK("WC SyncCheck", 0), 4205 HDSPM_SYNC_CHECK("AES SyncCheck", 1), 4206 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2), 4207 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3), 4208 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4), 4209 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5), 4210 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6), 4211 HDSPM_SYNC_CHECK("TCO SyncCheck", 7), 4212 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8), 4213 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4214 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1), 4215 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2), 4216 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3), 4217 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4), 4218 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5), 4219 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6), 4220 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7), 4221 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8) 4222 }; 4223 4224 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = { 4225 HDSPM_MIXER("Mixer", 0), 4226 HDSPM_INTERNAL_CLOCK("Internal Clock", 0), 4227 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 4228 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0), 4229 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0), 4230 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 4231 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 4232 HDSPM_SYNC_CHECK("WC Sync Check", 0), 4233 HDSPM_SYNC_CHECK("AES1 Sync Check", 1), 4234 HDSPM_SYNC_CHECK("AES2 Sync Check", 2), 4235 HDSPM_SYNC_CHECK("AES3 Sync Check", 3), 4236 HDSPM_SYNC_CHECK("AES4 Sync Check", 4), 4237 HDSPM_SYNC_CHECK("AES5 Sync Check", 5), 4238 HDSPM_SYNC_CHECK("AES6 Sync Check", 6), 4239 HDSPM_SYNC_CHECK("AES7 Sync Check", 7), 4240 HDSPM_SYNC_CHECK("AES8 Sync Check", 8), 4241 HDSPM_SYNC_CHECK("TCO Sync Check", 9), 4242 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10), 4243 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0), 4244 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1), 4245 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2), 4246 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3), 4247 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4), 4248 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5), 4249 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6), 4250 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7), 4251 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8), 4252 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9), 4253 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10), 4254 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut), 4255 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis), 4256 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby), 4257 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional), 4258 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms), 4259 HDSPM_DS_WIRE("Double Speed Wire Mode", 0), 4260 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0), 4261 }; 4262 4263 4264 4265 /* Control elements for the optional TCO module */ 4266 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = { 4267 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0), 4268 HDSPM_TCO_PULL("TCO Pull", 0), 4269 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0), 4270 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0), 4271 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0), 4272 HDSPM_TCO_WORD_TERM("TCO Word Term", 0) 4273 }; 4274 4275 4276 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER; 4277 4278 4279 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm) 4280 { 4281 int i; 4282 4283 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) { 4284 if (hdspm->system_sample_rate > 48000) { 4285 hdspm->playback_mixer_ctls[i]->vd[0].access = 4286 SNDRV_CTL_ELEM_ACCESS_INACTIVE | 4287 SNDRV_CTL_ELEM_ACCESS_READ | 4288 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4289 } else { 4290 hdspm->playback_mixer_ctls[i]->vd[0].access = 4291 SNDRV_CTL_ELEM_ACCESS_READWRITE | 4292 SNDRV_CTL_ELEM_ACCESS_VOLATILE; 4293 } 4294 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE | 4295 SNDRV_CTL_EVENT_MASK_INFO, 4296 &hdspm->playback_mixer_ctls[i]->id); 4297 } 4298 4299 return 0; 4300 } 4301 4302 4303 static int snd_hdspm_create_controls(struct snd_card *card, 4304 struct hdspm *hdspm) 4305 { 4306 unsigned int idx, limit; 4307 int err; 4308 struct snd_kcontrol *kctl; 4309 struct snd_kcontrol_new *list = NULL; 4310 4311 switch (hdspm->io_type) { 4312 case MADI: 4313 list = snd_hdspm_controls_madi; 4314 limit = ARRAY_SIZE(snd_hdspm_controls_madi); 4315 break; 4316 case MADIface: 4317 list = snd_hdspm_controls_madiface; 4318 limit = ARRAY_SIZE(snd_hdspm_controls_madiface); 4319 break; 4320 case AIO: 4321 list = snd_hdspm_controls_aio; 4322 limit = ARRAY_SIZE(snd_hdspm_controls_aio); 4323 break; 4324 case RayDAT: 4325 list = snd_hdspm_controls_raydat; 4326 limit = ARRAY_SIZE(snd_hdspm_controls_raydat); 4327 break; 4328 case AES32: 4329 list = snd_hdspm_controls_aes32; 4330 limit = ARRAY_SIZE(snd_hdspm_controls_aes32); 4331 break; 4332 } 4333 4334 if (NULL != list) { 4335 for (idx = 0; idx < limit; idx++) { 4336 err = snd_ctl_add(card, 4337 snd_ctl_new1(&list[idx], hdspm)); 4338 if (err < 0) 4339 return err; 4340 } 4341 } 4342 4343 4344 /* create simple 1:1 playback mixer controls */ 4345 snd_hdspm_playback_mixer.name = "Chn"; 4346 if (hdspm->system_sample_rate >= 128000) { 4347 limit = hdspm->qs_out_channels; 4348 } else if (hdspm->system_sample_rate >= 64000) { 4349 limit = hdspm->ds_out_channels; 4350 } else { 4351 limit = hdspm->ss_out_channels; 4352 } 4353 for (idx = 0; idx < limit; ++idx) { 4354 snd_hdspm_playback_mixer.index = idx + 1; 4355 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm); 4356 err = snd_ctl_add(card, kctl); 4357 if (err < 0) 4358 return err; 4359 hdspm->playback_mixer_ctls[idx] = kctl; 4360 } 4361 4362 4363 if (hdspm->tco) { 4364 /* add tco control elements */ 4365 list = snd_hdspm_controls_tco; 4366 limit = ARRAY_SIZE(snd_hdspm_controls_tco); 4367 for (idx = 0; idx < limit; idx++) { 4368 err = snd_ctl_add(card, 4369 snd_ctl_new1(&list[idx], hdspm)); 4370 if (err < 0) 4371 return err; 4372 } 4373 } 4374 4375 return 0; 4376 } 4377 4378 /*------------------------------------------------------------ 4379 /proc interface 4380 ------------------------------------------------------------*/ 4381 4382 static void 4383 snd_hdspm_proc_read_madi(struct snd_info_entry * entry, 4384 struct snd_info_buffer *buffer) 4385 { 4386 struct hdspm *hdspm = entry->private_data; 4387 unsigned int status, status2, control, freq; 4388 4389 char *pref_sync_ref; 4390 char *autosync_ref; 4391 char *system_clock_mode; 4392 char *insel; 4393 int x, x2; 4394 4395 /* TCO stuff */ 4396 int a, ltc, frames, seconds, minutes, hours; 4397 unsigned int period; 4398 u64 freq_const = 0; 4399 u32 rate; 4400 4401 status = hdspm_read(hdspm, HDSPM_statusRegister); 4402 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4403 control = hdspm->control_register; 4404 freq = hdspm_read(hdspm, HDSPM_timecodeRegister); 4405 4406 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n", 4407 hdspm->card_name, hdspm->card->number + 1, 4408 hdspm->firmware_rev, 4409 (status2 & HDSPM_version0) | 4410 (status2 & HDSPM_version1) | (status2 & 4411 HDSPM_version2)); 4412 4413 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n", 4414 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF, 4415 hdspm->serial); 4416 4417 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4418 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4419 4420 snd_iprintf(buffer, "--- System ---\n"); 4421 4422 snd_iprintf(buffer, 4423 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4424 status & HDSPM_audioIRQPending, 4425 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4426 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4427 hdspm->irq_count); 4428 snd_iprintf(buffer, 4429 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4430 "estimated= %ld (bytes)\n", 4431 ((status & HDSPM_BufferID) ? 1 : 0), 4432 (status & HDSPM_BufferPositionMask), 4433 (status & HDSPM_BufferPositionMask) % 4434 (2 * (int)hdspm->period_bytes), 4435 ((status & HDSPM_BufferPositionMask) - 64) % 4436 (2 * (int)hdspm->period_bytes), 4437 (long) hdspm_hw_pointer(hdspm) * 4); 4438 4439 snd_iprintf(buffer, 4440 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4441 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4442 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4443 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4444 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4445 snd_iprintf(buffer, 4446 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4447 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4448 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4449 snd_iprintf(buffer, 4450 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4451 "status2=0x%x\n", 4452 hdspm->control_register, hdspm->control2_register, 4453 status, status2); 4454 if (status & HDSPM_tco_detect) { 4455 snd_iprintf(buffer, "TCO module detected.\n"); 4456 a = hdspm_read(hdspm, HDSPM_RD_TCO+4); 4457 if (a & HDSPM_TCO1_LTC_Input_valid) { 4458 snd_iprintf(buffer, " LTC valid, "); 4459 switch (a & (HDSPM_TCO1_LTC_Format_LSB | 4460 HDSPM_TCO1_LTC_Format_MSB)) { 4461 case 0: 4462 snd_iprintf(buffer, "24 fps, "); 4463 break; 4464 case HDSPM_TCO1_LTC_Format_LSB: 4465 snd_iprintf(buffer, "25 fps, "); 4466 break; 4467 case HDSPM_TCO1_LTC_Format_MSB: 4468 snd_iprintf(buffer, "29.97 fps, "); 4469 break; 4470 default: 4471 snd_iprintf(buffer, "30 fps, "); 4472 break; 4473 } 4474 if (a & HDSPM_TCO1_set_drop_frame_flag) { 4475 snd_iprintf(buffer, "drop frame\n"); 4476 } else { 4477 snd_iprintf(buffer, "full frame\n"); 4478 } 4479 } else { 4480 snd_iprintf(buffer, " no LTC\n"); 4481 } 4482 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) { 4483 snd_iprintf(buffer, " Video: NTSC\n"); 4484 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) { 4485 snd_iprintf(buffer, " Video: PAL\n"); 4486 } else { 4487 snd_iprintf(buffer, " No video\n"); 4488 } 4489 if (a & HDSPM_TCO1_TCO_lock) { 4490 snd_iprintf(buffer, " Sync: lock\n"); 4491 } else { 4492 snd_iprintf(buffer, " Sync: no lock\n"); 4493 } 4494 4495 switch (hdspm->io_type) { 4496 case MADI: 4497 case AES32: 4498 freq_const = 110069313433624ULL; 4499 break; 4500 case RayDAT: 4501 case AIO: 4502 freq_const = 104857600000000ULL; 4503 break; 4504 case MADIface: 4505 break; /* no TCO possible */ 4506 } 4507 4508 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 4509 snd_iprintf(buffer, " period: %u\n", period); 4510 4511 4512 /* rate = freq_const/period; */ 4513 rate = div_u64(freq_const, period); 4514 4515 if (control & HDSPM_QuadSpeed) { 4516 rate *= 4; 4517 } else if (control & HDSPM_DoubleSpeed) { 4518 rate *= 2; 4519 } 4520 4521 snd_iprintf(buffer, " Frequency: %u Hz\n", 4522 (unsigned int) rate); 4523 4524 ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 4525 frames = ltc & 0xF; 4526 ltc >>= 4; 4527 frames += (ltc & 0x3) * 10; 4528 ltc >>= 4; 4529 seconds = ltc & 0xF; 4530 ltc >>= 4; 4531 seconds += (ltc & 0x7) * 10; 4532 ltc >>= 4; 4533 minutes = ltc & 0xF; 4534 ltc >>= 4; 4535 minutes += (ltc & 0x7) * 10; 4536 ltc >>= 4; 4537 hours = ltc & 0xF; 4538 ltc >>= 4; 4539 hours += (ltc & 0x3) * 10; 4540 snd_iprintf(buffer, 4541 " LTC In: %02d:%02d:%02d:%02d\n", 4542 hours, minutes, seconds, frames); 4543 4544 } else { 4545 snd_iprintf(buffer, "No TCO module detected.\n"); 4546 } 4547 4548 snd_iprintf(buffer, "--- Settings ---\n"); 4549 4550 x = hdspm_get_latency(hdspm); 4551 4552 snd_iprintf(buffer, 4553 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4554 x, (unsigned long) hdspm->period_bytes); 4555 4556 snd_iprintf(buffer, "Line out: %s\n", 4557 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off"); 4558 4559 switch (hdspm->control_register & HDSPM_InputMask) { 4560 case HDSPM_InputOptical: 4561 insel = "Optical"; 4562 break; 4563 case HDSPM_InputCoaxial: 4564 insel = "Coaxial"; 4565 break; 4566 default: 4567 insel = "Unknown"; 4568 } 4569 4570 snd_iprintf(buffer, 4571 "ClearTrackMarker = %s, Transmit in %s Channel Mode, " 4572 "Auto Input %s\n", 4573 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off", 4574 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56", 4575 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off"); 4576 4577 4578 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) 4579 system_clock_mode = "AutoSync"; 4580 else 4581 system_clock_mode = "Master"; 4582 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode); 4583 4584 switch (hdspm_pref_sync_ref(hdspm)) { 4585 case HDSPM_SYNC_FROM_WORD: 4586 pref_sync_ref = "Word Clock"; 4587 break; 4588 case HDSPM_SYNC_FROM_MADI: 4589 pref_sync_ref = "MADI Sync"; 4590 break; 4591 case HDSPM_SYNC_FROM_TCO: 4592 pref_sync_ref = "TCO"; 4593 break; 4594 case HDSPM_SYNC_FROM_SYNC_IN: 4595 pref_sync_ref = "Sync In"; 4596 break; 4597 default: 4598 pref_sync_ref = "XXXX Clock"; 4599 break; 4600 } 4601 snd_iprintf(buffer, "Preferred Sync Reference: %s\n", 4602 pref_sync_ref); 4603 4604 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4605 hdspm->system_sample_rate); 4606 4607 4608 snd_iprintf(buffer, "--- Status:\n"); 4609 4610 x = status & HDSPM_madiSync; 4611 x2 = status2 & HDSPM_wcSync; 4612 4613 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n", 4614 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") : 4615 "NoLock", 4616 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") : 4617 "NoLock"); 4618 4619 switch (hdspm_autosync_ref(hdspm)) { 4620 case HDSPM_AUTOSYNC_FROM_SYNC_IN: 4621 autosync_ref = "Sync In"; 4622 break; 4623 case HDSPM_AUTOSYNC_FROM_TCO: 4624 autosync_ref = "TCO"; 4625 break; 4626 case HDSPM_AUTOSYNC_FROM_WORD: 4627 autosync_ref = "Word Clock"; 4628 break; 4629 case HDSPM_AUTOSYNC_FROM_MADI: 4630 autosync_ref = "MADI Sync"; 4631 break; 4632 case HDSPM_AUTOSYNC_FROM_NONE: 4633 autosync_ref = "Input not valid"; 4634 break; 4635 default: 4636 autosync_ref = "---"; 4637 break; 4638 } 4639 snd_iprintf(buffer, 4640 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n", 4641 autosync_ref, hdspm_external_sample_rate(hdspm), 4642 (status & HDSPM_madiFreqMask) >> 22, 4643 (status2 & HDSPM_wcFreqMask) >> 5); 4644 4645 snd_iprintf(buffer, "Input: %s, Mode=%s\n", 4646 (status & HDSPM_AB_int) ? "Coax" : "Optical", 4647 (status & HDSPM_RX_64ch) ? "64 channels" : 4648 "56 channels"); 4649 4650 snd_iprintf(buffer, "\n"); 4651 } 4652 4653 static void 4654 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry, 4655 struct snd_info_buffer *buffer) 4656 { 4657 struct hdspm *hdspm = entry->private_data; 4658 unsigned int status; 4659 unsigned int status2; 4660 unsigned int timecode; 4661 int pref_syncref; 4662 char *autosync_ref; 4663 int x; 4664 4665 status = hdspm_read(hdspm, HDSPM_statusRegister); 4666 status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 4667 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister); 4668 4669 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n", 4670 hdspm->card_name, hdspm->card->number + 1, 4671 hdspm->firmware_rev); 4672 4673 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 4674 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase); 4675 4676 snd_iprintf(buffer, "--- System ---\n"); 4677 4678 snd_iprintf(buffer, 4679 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n", 4680 status & HDSPM_audioIRQPending, 4681 (status & HDSPM_midi0IRQPending) ? 1 : 0, 4682 (status & HDSPM_midi1IRQPending) ? 1 : 0, 4683 hdspm->irq_count); 4684 snd_iprintf(buffer, 4685 "HW pointer: id = %d, rawptr = %d (%d->%d) " 4686 "estimated= %ld (bytes)\n", 4687 ((status & HDSPM_BufferID) ? 1 : 0), 4688 (status & HDSPM_BufferPositionMask), 4689 (status & HDSPM_BufferPositionMask) % 4690 (2 * (int)hdspm->period_bytes), 4691 ((status & HDSPM_BufferPositionMask) - 64) % 4692 (2 * (int)hdspm->period_bytes), 4693 (long) hdspm_hw_pointer(hdspm) * 4); 4694 4695 snd_iprintf(buffer, 4696 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n", 4697 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF, 4698 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF, 4699 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF, 4700 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF); 4701 snd_iprintf(buffer, 4702 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n", 4703 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF, 4704 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF); 4705 snd_iprintf(buffer, 4706 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, " 4707 "status2=0x%x\n", 4708 hdspm->control_register, hdspm->control2_register, 4709 status, status2); 4710 4711 snd_iprintf(buffer, "--- Settings ---\n"); 4712 4713 x = hdspm_get_latency(hdspm); 4714 4715 snd_iprintf(buffer, 4716 "Size (Latency): %d samples (2 periods of %lu bytes)\n", 4717 x, (unsigned long) hdspm->period_bytes); 4718 4719 snd_iprintf(buffer, "Line out: %s\n", 4720 (hdspm-> 4721 control_register & HDSPM_LineOut) ? "on " : "off"); 4722 4723 snd_iprintf(buffer, 4724 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n", 4725 (hdspm-> 4726 control_register & HDSPM_clr_tms) ? "on" : "off", 4727 (hdspm-> 4728 control_register & HDSPM_Emphasis) ? "on" : "off", 4729 (hdspm-> 4730 control_register & HDSPM_Dolby) ? "on" : "off"); 4731 4732 4733 pref_syncref = hdspm_pref_sync_ref(hdspm); 4734 if (pref_syncref == 0) 4735 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n"); 4736 else 4737 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n", 4738 pref_syncref); 4739 4740 snd_iprintf(buffer, "System Clock Frequency: %d\n", 4741 hdspm->system_sample_rate); 4742 4743 snd_iprintf(buffer, "Double speed: %s\n", 4744 hdspm->control_register & HDSPM_DS_DoubleWire? 4745 "Double wire" : "Single wire"); 4746 snd_iprintf(buffer, "Quad speed: %s\n", 4747 hdspm->control_register & HDSPM_QS_DoubleWire? 4748 "Double wire" : 4749 hdspm->control_register & HDSPM_QS_QuadWire? 4750 "Quad wire" : "Single wire"); 4751 4752 snd_iprintf(buffer, "--- Status:\n"); 4753 4754 snd_iprintf(buffer, "Word: %s Frequency: %d\n", 4755 (status & HDSPM_AES32_wcLock) ? "Sync " : "No Lock", 4756 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF)); 4757 4758 for (x = 0; x < 8; x++) { 4759 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n", 4760 x+1, 4761 (status2 & (HDSPM_LockAES >> x)) ? 4762 "Sync " : "No Lock", 4763 HDSPM_bit2freq((timecode >> (4*x)) & 0xF)); 4764 } 4765 4766 switch (hdspm_autosync_ref(hdspm)) { 4767 case HDSPM_AES32_AUTOSYNC_FROM_NONE: 4768 autosync_ref = "None"; break; 4769 case HDSPM_AES32_AUTOSYNC_FROM_WORD: 4770 autosync_ref = "Word Clock"; break; 4771 case HDSPM_AES32_AUTOSYNC_FROM_AES1: 4772 autosync_ref = "AES1"; break; 4773 case HDSPM_AES32_AUTOSYNC_FROM_AES2: 4774 autosync_ref = "AES2"; break; 4775 case HDSPM_AES32_AUTOSYNC_FROM_AES3: 4776 autosync_ref = "AES3"; break; 4777 case HDSPM_AES32_AUTOSYNC_FROM_AES4: 4778 autosync_ref = "AES4"; break; 4779 case HDSPM_AES32_AUTOSYNC_FROM_AES5: 4780 autosync_ref = "AES5"; break; 4781 case HDSPM_AES32_AUTOSYNC_FROM_AES6: 4782 autosync_ref = "AES6"; break; 4783 case HDSPM_AES32_AUTOSYNC_FROM_AES7: 4784 autosync_ref = "AES7"; break; 4785 case HDSPM_AES32_AUTOSYNC_FROM_AES8: 4786 autosync_ref = "AES8"; break; 4787 default: 4788 autosync_ref = "---"; break; 4789 } 4790 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref); 4791 4792 snd_iprintf(buffer, "\n"); 4793 } 4794 4795 static void 4796 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry, 4797 struct snd_info_buffer *buffer) 4798 { 4799 struct hdspm *hdspm = entry->private_data; 4800 unsigned int status1, status2, status3, control, i; 4801 unsigned int lock, sync; 4802 4803 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */ 4804 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */ 4805 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */ 4806 4807 control = hdspm->control_register; 4808 4809 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1); 4810 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2); 4811 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3); 4812 4813 4814 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n"); 4815 4816 snd_iprintf(buffer, "Clock mode : %s\n", 4817 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave"); 4818 snd_iprintf(buffer, "System frequency: %d Hz\n", 4819 hdspm_get_system_sample_rate(hdspm)); 4820 4821 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n"); 4822 4823 lock = 0x1; 4824 sync = 0x100; 4825 4826 for (i = 0; i < 8; i++) { 4827 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n", 4828 i, 4829 (status1 & lock) ? 1 : 0, 4830 (status1 & sync) ? 1 : 0, 4831 texts_freq[(status2 >> (i * 4)) & 0xF]); 4832 4833 lock = lock<<1; 4834 sync = sync<<1; 4835 } 4836 4837 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n", 4838 (status1 & 0x1000000) ? 1 : 0, 4839 (status1 & 0x2000000) ? 1 : 0, 4840 texts_freq[(status1 >> 16) & 0xF]); 4841 4842 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n", 4843 (status1 & 0x4000000) ? 1 : 0, 4844 (status1 & 0x8000000) ? 1 : 0, 4845 texts_freq[(status1 >> 20) & 0xF]); 4846 4847 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n", 4848 (status3 & 0x400) ? 1 : 0, 4849 (status3 & 0x800) ? 1 : 0, 4850 texts_freq[(status2 >> 12) & 0xF]); 4851 4852 } 4853 4854 #ifdef CONFIG_SND_DEBUG 4855 static void 4856 snd_hdspm_proc_read_debug(struct snd_info_entry *entry, 4857 struct snd_info_buffer *buffer) 4858 { 4859 struct hdspm *hdspm = entry->private_data; 4860 4861 int j,i; 4862 4863 for (i = 0; i < 256 /* 1024*64 */; i += j) { 4864 snd_iprintf(buffer, "0x%08X: ", i); 4865 for (j = 0; j < 16; j += 4) 4866 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j)); 4867 snd_iprintf(buffer, "\n"); 4868 } 4869 } 4870 #endif 4871 4872 4873 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry, 4874 struct snd_info_buffer *buffer) 4875 { 4876 struct hdspm *hdspm = entry->private_data; 4877 int i; 4878 4879 snd_iprintf(buffer, "# generated by hdspm\n"); 4880 4881 for (i = 0; i < hdspm->max_channels_in; i++) { 4882 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]); 4883 } 4884 } 4885 4886 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry, 4887 struct snd_info_buffer *buffer) 4888 { 4889 struct hdspm *hdspm = entry->private_data; 4890 int i; 4891 4892 snd_iprintf(buffer, "# generated by hdspm\n"); 4893 4894 for (i = 0; i < hdspm->max_channels_out; i++) { 4895 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]); 4896 } 4897 } 4898 4899 4900 static void snd_hdspm_proc_init(struct hdspm *hdspm) 4901 { 4902 struct snd_info_entry *entry; 4903 4904 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) { 4905 switch (hdspm->io_type) { 4906 case AES32: 4907 snd_info_set_text_ops(entry, hdspm, 4908 snd_hdspm_proc_read_aes32); 4909 break; 4910 case MADI: 4911 snd_info_set_text_ops(entry, hdspm, 4912 snd_hdspm_proc_read_madi); 4913 break; 4914 case MADIface: 4915 /* snd_info_set_text_ops(entry, hdspm, 4916 snd_hdspm_proc_read_madiface); */ 4917 break; 4918 case RayDAT: 4919 snd_info_set_text_ops(entry, hdspm, 4920 snd_hdspm_proc_read_raydat); 4921 break; 4922 case AIO: 4923 break; 4924 } 4925 } 4926 4927 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) { 4928 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in); 4929 } 4930 4931 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) { 4932 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out); 4933 } 4934 4935 #ifdef CONFIG_SND_DEBUG 4936 /* debug file to read all hdspm registers */ 4937 if (!snd_card_proc_new(hdspm->card, "debug", &entry)) 4938 snd_info_set_text_ops(entry, hdspm, 4939 snd_hdspm_proc_read_debug); 4940 #endif 4941 } 4942 4943 /*------------------------------------------------------------ 4944 hdspm intitialize 4945 ------------------------------------------------------------*/ 4946 4947 static int snd_hdspm_set_defaults(struct hdspm * hdspm) 4948 { 4949 /* ASSUMPTION: hdspm->lock is either held, or there is no need to 4950 hold it (e.g. during module initialization). 4951 */ 4952 4953 /* set defaults: */ 4954 4955 hdspm->settings_register = 0; 4956 4957 switch (hdspm->io_type) { 4958 case MADI: 4959 case MADIface: 4960 hdspm->control_register = 4961 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 4962 break; 4963 4964 case RayDAT: 4965 case AIO: 4966 hdspm->settings_register = 0x1 + 0x1000; 4967 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0, 4968 * line_out */ 4969 hdspm->control_register = 4970 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000; 4971 break; 4972 4973 case AES32: 4974 hdspm->control_register = 4975 HDSPM_ClockModeMaster | /* Master Cloack Mode on */ 4976 hdspm_encode_latency(7) | /* latency max=8192samples */ 4977 HDSPM_SyncRef0 | /* AES1 is syncclock */ 4978 HDSPM_LineOut | /* Analog output in */ 4979 HDSPM_Professional; /* Professional mode */ 4980 break; 4981 } 4982 4983 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 4984 4985 if (AES32 == hdspm->io_type) { 4986 /* No control2 register for AES32 */ 4987 #ifdef SNDRV_BIG_ENDIAN 4988 hdspm->control2_register = HDSPM_BIGENDIAN_MODE; 4989 #else 4990 hdspm->control2_register = 0; 4991 #endif 4992 4993 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register); 4994 } 4995 hdspm_compute_period_size(hdspm); 4996 4997 /* silence everything */ 4998 4999 all_in_all_mixer(hdspm, 0 * UNITY_GAIN); 5000 5001 if (hdspm->io_type == AIO || hdspm->io_type == RayDAT) { 5002 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register); 5003 } 5004 5005 /* set a default rate so that the channel map is set up. */ 5006 hdspm_set_rate(hdspm, 48000, 1); 5007 5008 return 0; 5009 } 5010 5011 5012 /*------------------------------------------------------------ 5013 interrupt 5014 ------------------------------------------------------------*/ 5015 5016 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id) 5017 { 5018 struct hdspm *hdspm = (struct hdspm *) dev_id; 5019 unsigned int status; 5020 int i, audio, midi, schedule = 0; 5021 /* cycles_t now; */ 5022 5023 status = hdspm_read(hdspm, HDSPM_statusRegister); 5024 5025 audio = status & HDSPM_audioIRQPending; 5026 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending | 5027 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending); 5028 5029 /* now = get_cycles(); */ 5030 /** 5031 * LAT_2..LAT_0 period counter (win) counter (mac) 5032 * 6 4096 ~256053425 ~514672358 5033 * 5 2048 ~128024983 ~257373821 5034 * 4 1024 ~64023706 ~128718089 5035 * 3 512 ~32005945 ~64385999 5036 * 2 256 ~16003039 ~32260176 5037 * 1 128 ~7998738 ~16194507 5038 * 0 64 ~3998231 ~8191558 5039 **/ 5040 /* 5041 snd_printk(KERN_INFO "snd_hdspm_interrupt %llu @ %llx\n", 5042 now-hdspm->last_interrupt, status & 0xFFC0); 5043 hdspm->last_interrupt = now; 5044 */ 5045 5046 if (!audio && !midi) 5047 return IRQ_NONE; 5048 5049 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0); 5050 hdspm->irq_count++; 5051 5052 5053 if (audio) { 5054 if (hdspm->capture_substream) 5055 snd_pcm_period_elapsed(hdspm->capture_substream); 5056 5057 if (hdspm->playback_substream) 5058 snd_pcm_period_elapsed(hdspm->playback_substream); 5059 } 5060 5061 if (midi) { 5062 i = 0; 5063 while (i < hdspm->midiPorts) { 5064 if ((hdspm_read(hdspm, 5065 hdspm->midi[i].statusIn) & 0xff) && 5066 (status & hdspm->midi[i].irq)) { 5067 /* we disable interrupts for this input until 5068 * processing is done 5069 */ 5070 hdspm->control_register &= ~hdspm->midi[i].ie; 5071 hdspm_write(hdspm, HDSPM_controlRegister, 5072 hdspm->control_register); 5073 hdspm->midi[i].pending = 1; 5074 schedule = 1; 5075 } 5076 5077 i++; 5078 } 5079 5080 if (schedule) 5081 tasklet_hi_schedule(&hdspm->midi_tasklet); 5082 } 5083 5084 return IRQ_HANDLED; 5085 } 5086 5087 /*------------------------------------------------------------ 5088 pcm interface 5089 ------------------------------------------------------------*/ 5090 5091 5092 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream 5093 *substream) 5094 { 5095 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5096 return hdspm_hw_pointer(hdspm); 5097 } 5098 5099 5100 static int snd_hdspm_reset(struct snd_pcm_substream *substream) 5101 { 5102 struct snd_pcm_runtime *runtime = substream->runtime; 5103 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5104 struct snd_pcm_substream *other; 5105 5106 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5107 other = hdspm->capture_substream; 5108 else 5109 other = hdspm->playback_substream; 5110 5111 if (hdspm->running) 5112 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm); 5113 else 5114 runtime->status->hw_ptr = 0; 5115 if (other) { 5116 struct snd_pcm_substream *s; 5117 struct snd_pcm_runtime *oruntime = other->runtime; 5118 snd_pcm_group_for_each_entry(s, substream) { 5119 if (s == other) { 5120 oruntime->status->hw_ptr = 5121 runtime->status->hw_ptr; 5122 break; 5123 } 5124 } 5125 } 5126 return 0; 5127 } 5128 5129 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream, 5130 struct snd_pcm_hw_params *params) 5131 { 5132 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5133 int err; 5134 int i; 5135 pid_t this_pid; 5136 pid_t other_pid; 5137 5138 spin_lock_irq(&hdspm->lock); 5139 5140 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5141 this_pid = hdspm->playback_pid; 5142 other_pid = hdspm->capture_pid; 5143 } else { 5144 this_pid = hdspm->capture_pid; 5145 other_pid = hdspm->playback_pid; 5146 } 5147 5148 if (other_pid > 0 && this_pid != other_pid) { 5149 5150 /* The other stream is open, and not by the same 5151 task as this one. Make sure that the parameters 5152 that matter are the same. 5153 */ 5154 5155 if (params_rate(params) != hdspm->system_sample_rate) { 5156 spin_unlock_irq(&hdspm->lock); 5157 _snd_pcm_hw_param_setempty(params, 5158 SNDRV_PCM_HW_PARAM_RATE); 5159 return -EBUSY; 5160 } 5161 5162 if (params_period_size(params) != hdspm->period_bytes / 4) { 5163 spin_unlock_irq(&hdspm->lock); 5164 _snd_pcm_hw_param_setempty(params, 5165 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5166 return -EBUSY; 5167 } 5168 5169 } 5170 /* We're fine. */ 5171 spin_unlock_irq(&hdspm->lock); 5172 5173 /* how to make sure that the rate matches an externally-set one ? */ 5174 5175 spin_lock_irq(&hdspm->lock); 5176 err = hdspm_set_rate(hdspm, params_rate(params), 0); 5177 if (err < 0) { 5178 snd_printk(KERN_INFO "err on hdspm_set_rate: %d\n", err); 5179 spin_unlock_irq(&hdspm->lock); 5180 _snd_pcm_hw_param_setempty(params, 5181 SNDRV_PCM_HW_PARAM_RATE); 5182 return err; 5183 } 5184 spin_unlock_irq(&hdspm->lock); 5185 5186 err = hdspm_set_interrupt_interval(hdspm, 5187 params_period_size(params)); 5188 if (err < 0) { 5189 snd_printk(KERN_INFO "err on hdspm_set_interrupt_interval: %d\n", err); 5190 _snd_pcm_hw_param_setempty(params, 5191 SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5192 return err; 5193 } 5194 5195 /* Memory allocation, takashi's method, dont know if we should 5196 * spinlock 5197 */ 5198 /* malloc all buffer even if not enabled to get sure */ 5199 /* Update for MADI rev 204: we need to allocate for all channels, 5200 * otherwise it doesn't work at 96kHz */ 5201 5202 err = 5203 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES); 5204 if (err < 0) { 5205 snd_printk(KERN_INFO "err on snd_pcm_lib_malloc_pages: %d\n", err); 5206 return err; 5207 } 5208 5209 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5210 5211 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut, 5212 params_channels(params)); 5213 5214 for (i = 0; i < params_channels(params); ++i) 5215 snd_hdspm_enable_out(hdspm, i, 1); 5216 5217 hdspm->playback_buffer = 5218 (unsigned char *) substream->runtime->dma_area; 5219 snd_printdd("Allocated sample buffer for playback at %p\n", 5220 hdspm->playback_buffer); 5221 } else { 5222 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn, 5223 params_channels(params)); 5224 5225 for (i = 0; i < params_channels(params); ++i) 5226 snd_hdspm_enable_in(hdspm, i, 1); 5227 5228 hdspm->capture_buffer = 5229 (unsigned char *) substream->runtime->dma_area; 5230 snd_printdd("Allocated sample buffer for capture at %p\n", 5231 hdspm->capture_buffer); 5232 } 5233 5234 /* 5235 snd_printdd("Allocated sample buffer for %s at 0x%08X\n", 5236 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5237 "playback" : "capture", 5238 snd_pcm_sgbuf_get_addr(substream, 0)); 5239 */ 5240 /* 5241 snd_printdd("set_hwparams: %s %d Hz, %d channels, bs = %d\n", 5242 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 5243 "playback" : "capture", 5244 params_rate(params), params_channels(params), 5245 params_buffer_size(params)); 5246 */ 5247 5248 5249 /* Switch to native float format if requested */ 5250 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) { 5251 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT)) 5252 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE float format.\n"); 5253 5254 hdspm->control_register |= HDSPe_FLOAT_FORMAT; 5255 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) { 5256 if (hdspm->control_register & HDSPe_FLOAT_FORMAT) 5257 snd_printk(KERN_INFO "hdspm: Switching to native 32bit LE integer format.\n"); 5258 5259 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT; 5260 } 5261 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register); 5262 5263 return 0; 5264 } 5265 5266 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream) 5267 { 5268 int i; 5269 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5270 5271 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5272 5273 /* params_channels(params) should be enough, 5274 but to get sure in case of error */ 5275 for (i = 0; i < hdspm->max_channels_out; ++i) 5276 snd_hdspm_enable_out(hdspm, i, 0); 5277 5278 hdspm->playback_buffer = NULL; 5279 } else { 5280 for (i = 0; i < hdspm->max_channels_in; ++i) 5281 snd_hdspm_enable_in(hdspm, i, 0); 5282 5283 hdspm->capture_buffer = NULL; 5284 5285 } 5286 5287 snd_pcm_lib_free_pages(substream); 5288 5289 return 0; 5290 } 5291 5292 5293 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream, 5294 struct snd_pcm_channel_info *info) 5295 { 5296 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5297 5298 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 5299 if (snd_BUG_ON(info->channel >= hdspm->max_channels_out)) { 5300 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel out of range (%d)\n", info->channel); 5301 return -EINVAL; 5302 } 5303 5304 if (hdspm->channel_map_out[info->channel] < 0) { 5305 snd_printk(KERN_INFO "snd_hdspm_channel_info: output channel %d mapped out\n", info->channel); 5306 return -EINVAL; 5307 } 5308 5309 info->offset = hdspm->channel_map_out[info->channel] * 5310 HDSPM_CHANNEL_BUFFER_BYTES; 5311 } else { 5312 if (snd_BUG_ON(info->channel >= hdspm->max_channels_in)) { 5313 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel out of range (%d)\n", info->channel); 5314 return -EINVAL; 5315 } 5316 5317 if (hdspm->channel_map_in[info->channel] < 0) { 5318 snd_printk(KERN_INFO "snd_hdspm_channel_info: input channel %d mapped out\n", info->channel); 5319 return -EINVAL; 5320 } 5321 5322 info->offset = hdspm->channel_map_in[info->channel] * 5323 HDSPM_CHANNEL_BUFFER_BYTES; 5324 } 5325 5326 info->first = 0; 5327 info->step = 32; 5328 return 0; 5329 } 5330 5331 5332 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream, 5333 unsigned int cmd, void *arg) 5334 { 5335 switch (cmd) { 5336 case SNDRV_PCM_IOCTL1_RESET: 5337 return snd_hdspm_reset(substream); 5338 5339 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 5340 { 5341 struct snd_pcm_channel_info *info = arg; 5342 return snd_hdspm_channel_info(substream, info); 5343 } 5344 default: 5345 break; 5346 } 5347 5348 return snd_pcm_lib_ioctl(substream, cmd, arg); 5349 } 5350 5351 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd) 5352 { 5353 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5354 struct snd_pcm_substream *other; 5355 int running; 5356 5357 spin_lock(&hdspm->lock); 5358 running = hdspm->running; 5359 switch (cmd) { 5360 case SNDRV_PCM_TRIGGER_START: 5361 running |= 1 << substream->stream; 5362 break; 5363 case SNDRV_PCM_TRIGGER_STOP: 5364 running &= ~(1 << substream->stream); 5365 break; 5366 default: 5367 snd_BUG(); 5368 spin_unlock(&hdspm->lock); 5369 return -EINVAL; 5370 } 5371 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5372 other = hdspm->capture_substream; 5373 else 5374 other = hdspm->playback_substream; 5375 5376 if (other) { 5377 struct snd_pcm_substream *s; 5378 snd_pcm_group_for_each_entry(s, substream) { 5379 if (s == other) { 5380 snd_pcm_trigger_done(s, substream); 5381 if (cmd == SNDRV_PCM_TRIGGER_START) 5382 running |= 1 << s->stream; 5383 else 5384 running &= ~(1 << s->stream); 5385 goto _ok; 5386 } 5387 } 5388 if (cmd == SNDRV_PCM_TRIGGER_START) { 5389 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) 5390 && substream->stream == 5391 SNDRV_PCM_STREAM_CAPTURE) 5392 hdspm_silence_playback(hdspm); 5393 } else { 5394 if (running && 5395 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 5396 hdspm_silence_playback(hdspm); 5397 } 5398 } else { 5399 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 5400 hdspm_silence_playback(hdspm); 5401 } 5402 _ok: 5403 snd_pcm_trigger_done(substream, substream); 5404 if (!hdspm->running && running) 5405 hdspm_start_audio(hdspm); 5406 else if (hdspm->running && !running) 5407 hdspm_stop_audio(hdspm); 5408 hdspm->running = running; 5409 spin_unlock(&hdspm->lock); 5410 5411 return 0; 5412 } 5413 5414 static int snd_hdspm_prepare(struct snd_pcm_substream *substream) 5415 { 5416 return 0; 5417 } 5418 5419 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = { 5420 .info = (SNDRV_PCM_INFO_MMAP | 5421 SNDRV_PCM_INFO_MMAP_VALID | 5422 SNDRV_PCM_INFO_NONINTERLEAVED | 5423 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE), 5424 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5425 .rates = (SNDRV_PCM_RATE_32000 | 5426 SNDRV_PCM_RATE_44100 | 5427 SNDRV_PCM_RATE_48000 | 5428 SNDRV_PCM_RATE_64000 | 5429 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5430 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ), 5431 .rate_min = 32000, 5432 .rate_max = 192000, 5433 .channels_min = 1, 5434 .channels_max = HDSPM_MAX_CHANNELS, 5435 .buffer_bytes_max = 5436 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5437 .period_bytes_min = (32 * 4), 5438 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5439 .periods_min = 2, 5440 .periods_max = 512, 5441 .fifo_size = 0 5442 }; 5443 5444 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = { 5445 .info = (SNDRV_PCM_INFO_MMAP | 5446 SNDRV_PCM_INFO_MMAP_VALID | 5447 SNDRV_PCM_INFO_NONINTERLEAVED | 5448 SNDRV_PCM_INFO_SYNC_START), 5449 .formats = SNDRV_PCM_FMTBIT_S32_LE, 5450 .rates = (SNDRV_PCM_RATE_32000 | 5451 SNDRV_PCM_RATE_44100 | 5452 SNDRV_PCM_RATE_48000 | 5453 SNDRV_PCM_RATE_64000 | 5454 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | 5455 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000), 5456 .rate_min = 32000, 5457 .rate_max = 192000, 5458 .channels_min = 1, 5459 .channels_max = HDSPM_MAX_CHANNELS, 5460 .buffer_bytes_max = 5461 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS, 5462 .period_bytes_min = (32 * 4), 5463 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS, 5464 .periods_min = 2, 5465 .periods_max = 512, 5466 .fifo_size = 0 5467 }; 5468 5469 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 5470 struct snd_pcm_hw_rule *rule) 5471 { 5472 struct hdspm *hdspm = rule->private; 5473 struct snd_interval *c = 5474 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5475 struct snd_interval *r = 5476 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5477 5478 if (r->min > 96000 && r->max <= 192000) { 5479 struct snd_interval t = { 5480 .min = hdspm->qs_in_channels, 5481 .max = hdspm->qs_in_channels, 5482 .integer = 1, 5483 }; 5484 return snd_interval_refine(c, &t); 5485 } else if (r->min > 48000 && r->max <= 96000) { 5486 struct snd_interval t = { 5487 .min = hdspm->ds_in_channels, 5488 .max = hdspm->ds_in_channels, 5489 .integer = 1, 5490 }; 5491 return snd_interval_refine(c, &t); 5492 } else if (r->max < 64000) { 5493 struct snd_interval t = { 5494 .min = hdspm->ss_in_channels, 5495 .max = hdspm->ss_in_channels, 5496 .integer = 1, 5497 }; 5498 return snd_interval_refine(c, &t); 5499 } 5500 5501 return 0; 5502 } 5503 5504 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 5505 struct snd_pcm_hw_rule * rule) 5506 { 5507 struct hdspm *hdspm = rule->private; 5508 struct snd_interval *c = 5509 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5510 struct snd_interval *r = 5511 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5512 5513 if (r->min > 96000 && r->max <= 192000) { 5514 struct snd_interval t = { 5515 .min = hdspm->qs_out_channels, 5516 .max = hdspm->qs_out_channels, 5517 .integer = 1, 5518 }; 5519 return snd_interval_refine(c, &t); 5520 } else if (r->min > 48000 && r->max <= 96000) { 5521 struct snd_interval t = { 5522 .min = hdspm->ds_out_channels, 5523 .max = hdspm->ds_out_channels, 5524 .integer = 1, 5525 }; 5526 return snd_interval_refine(c, &t); 5527 } else if (r->max < 64000) { 5528 struct snd_interval t = { 5529 .min = hdspm->ss_out_channels, 5530 .max = hdspm->ss_out_channels, 5531 .integer = 1, 5532 }; 5533 return snd_interval_refine(c, &t); 5534 } else { 5535 } 5536 return 0; 5537 } 5538 5539 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 5540 struct snd_pcm_hw_rule * rule) 5541 { 5542 struct hdspm *hdspm = rule->private; 5543 struct snd_interval *c = 5544 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5545 struct snd_interval *r = 5546 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5547 5548 if (c->min >= hdspm->ss_in_channels) { 5549 struct snd_interval t = { 5550 .min = 32000, 5551 .max = 48000, 5552 .integer = 1, 5553 }; 5554 return snd_interval_refine(r, &t); 5555 } else if (c->max <= hdspm->qs_in_channels) { 5556 struct snd_interval t = { 5557 .min = 128000, 5558 .max = 192000, 5559 .integer = 1, 5560 }; 5561 return snd_interval_refine(r, &t); 5562 } else if (c->max <= hdspm->ds_in_channels) { 5563 struct snd_interval t = { 5564 .min = 64000, 5565 .max = 96000, 5566 .integer = 1, 5567 }; 5568 return snd_interval_refine(r, &t); 5569 } 5570 5571 return 0; 5572 } 5573 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 5574 struct snd_pcm_hw_rule *rule) 5575 { 5576 struct hdspm *hdspm = rule->private; 5577 struct snd_interval *c = 5578 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 5579 struct snd_interval *r = 5580 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 5581 5582 if (c->min >= hdspm->ss_out_channels) { 5583 struct snd_interval t = { 5584 .min = 32000, 5585 .max = 48000, 5586 .integer = 1, 5587 }; 5588 return snd_interval_refine(r, &t); 5589 } else if (c->max <= hdspm->qs_out_channels) { 5590 struct snd_interval t = { 5591 .min = 128000, 5592 .max = 192000, 5593 .integer = 1, 5594 }; 5595 return snd_interval_refine(r, &t); 5596 } else if (c->max <= hdspm->ds_out_channels) { 5597 struct snd_interval t = { 5598 .min = 64000, 5599 .max = 96000, 5600 .integer = 1, 5601 }; 5602 return snd_interval_refine(r, &t); 5603 } 5604 5605 return 0; 5606 } 5607 5608 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params, 5609 struct snd_pcm_hw_rule *rule) 5610 { 5611 unsigned int list[3]; 5612 struct hdspm *hdspm = rule->private; 5613 struct snd_interval *c = hw_param_interval(params, 5614 SNDRV_PCM_HW_PARAM_CHANNELS); 5615 5616 list[0] = hdspm->qs_in_channels; 5617 list[1] = hdspm->ds_in_channels; 5618 list[2] = hdspm->ss_in_channels; 5619 return snd_interval_list(c, 3, list, 0); 5620 } 5621 5622 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params, 5623 struct snd_pcm_hw_rule *rule) 5624 { 5625 unsigned int list[3]; 5626 struct hdspm *hdspm = rule->private; 5627 struct snd_interval *c = hw_param_interval(params, 5628 SNDRV_PCM_HW_PARAM_CHANNELS); 5629 5630 list[0] = hdspm->qs_out_channels; 5631 list[1] = hdspm->ds_out_channels; 5632 list[2] = hdspm->ss_out_channels; 5633 return snd_interval_list(c, 3, list, 0); 5634 } 5635 5636 5637 static unsigned int hdspm_aes32_sample_rates[] = { 5638 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 5639 }; 5640 5641 static struct snd_pcm_hw_constraint_list 5642 hdspm_hw_constraints_aes32_sample_rates = { 5643 .count = ARRAY_SIZE(hdspm_aes32_sample_rates), 5644 .list = hdspm_aes32_sample_rates, 5645 .mask = 0 5646 }; 5647 5648 static int snd_hdspm_playback_open(struct snd_pcm_substream *substream) 5649 { 5650 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5651 struct snd_pcm_runtime *runtime = substream->runtime; 5652 5653 spin_lock_irq(&hdspm->lock); 5654 5655 snd_pcm_set_sync(substream); 5656 5657 5658 runtime->hw = snd_hdspm_playback_subinfo; 5659 5660 if (hdspm->capture_substream == NULL) 5661 hdspm_stop_audio(hdspm); 5662 5663 hdspm->playback_pid = current->pid; 5664 hdspm->playback_substream = substream; 5665 5666 spin_unlock_irq(&hdspm->lock); 5667 5668 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5669 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5670 5671 switch (hdspm->io_type) { 5672 case AIO: 5673 case RayDAT: 5674 snd_pcm_hw_constraint_minmax(runtime, 5675 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5676 32, 4096); 5677 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */ 5678 snd_pcm_hw_constraint_minmax(runtime, 5679 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5680 16384, 16384); 5681 break; 5682 5683 default: 5684 snd_pcm_hw_constraint_minmax(runtime, 5685 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5686 64, 8192); 5687 break; 5688 } 5689 5690 if (AES32 == hdspm->io_type) { 5691 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5692 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5693 &hdspm_hw_constraints_aes32_sample_rates); 5694 } else { 5695 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5696 snd_hdspm_hw_rule_rate_out_channels, hdspm, 5697 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5698 } 5699 5700 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5701 snd_hdspm_hw_rule_out_channels, hdspm, 5702 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5703 5704 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5705 snd_hdspm_hw_rule_out_channels_rate, hdspm, 5706 SNDRV_PCM_HW_PARAM_RATE, -1); 5707 5708 return 0; 5709 } 5710 5711 static int snd_hdspm_playback_release(struct snd_pcm_substream *substream) 5712 { 5713 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5714 5715 spin_lock_irq(&hdspm->lock); 5716 5717 hdspm->playback_pid = -1; 5718 hdspm->playback_substream = NULL; 5719 5720 spin_unlock_irq(&hdspm->lock); 5721 5722 return 0; 5723 } 5724 5725 5726 static int snd_hdspm_capture_open(struct snd_pcm_substream *substream) 5727 { 5728 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5729 struct snd_pcm_runtime *runtime = substream->runtime; 5730 5731 spin_lock_irq(&hdspm->lock); 5732 snd_pcm_set_sync(substream); 5733 runtime->hw = snd_hdspm_capture_subinfo; 5734 5735 if (hdspm->playback_substream == NULL) 5736 hdspm_stop_audio(hdspm); 5737 5738 hdspm->capture_pid = current->pid; 5739 hdspm->capture_substream = substream; 5740 5741 spin_unlock_irq(&hdspm->lock); 5742 5743 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 5744 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 5745 5746 switch (hdspm->io_type) { 5747 case AIO: 5748 case RayDAT: 5749 snd_pcm_hw_constraint_minmax(runtime, 5750 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5751 32, 4096); 5752 snd_pcm_hw_constraint_minmax(runtime, 5753 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 5754 16384, 16384); 5755 break; 5756 5757 default: 5758 snd_pcm_hw_constraint_minmax(runtime, 5759 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 5760 64, 8192); 5761 break; 5762 } 5763 5764 if (AES32 == hdspm->io_type) { 5765 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT; 5766 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5767 &hdspm_hw_constraints_aes32_sample_rates); 5768 } else { 5769 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 5770 snd_hdspm_hw_rule_rate_in_channels, hdspm, 5771 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5772 } 5773 5774 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5775 snd_hdspm_hw_rule_in_channels, hdspm, 5776 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 5777 5778 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 5779 snd_hdspm_hw_rule_in_channels_rate, hdspm, 5780 SNDRV_PCM_HW_PARAM_RATE, -1); 5781 5782 return 0; 5783 } 5784 5785 static int snd_hdspm_capture_release(struct snd_pcm_substream *substream) 5786 { 5787 struct hdspm *hdspm = snd_pcm_substream_chip(substream); 5788 5789 spin_lock_irq(&hdspm->lock); 5790 5791 hdspm->capture_pid = -1; 5792 hdspm->capture_substream = NULL; 5793 5794 spin_unlock_irq(&hdspm->lock); 5795 return 0; 5796 } 5797 5798 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 5799 { 5800 /* we have nothing to initialize but the call is required */ 5801 return 0; 5802 } 5803 5804 static inline int copy_u32_le(void __user *dest, void __iomem *src) 5805 { 5806 u32 val = readl(src); 5807 return copy_to_user(dest, &val, 4); 5808 } 5809 5810 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, 5811 unsigned int cmd, unsigned long arg) 5812 { 5813 void __user *argp = (void __user *)arg; 5814 struct hdspm *hdspm = hw->private_data; 5815 struct hdspm_mixer_ioctl mixer; 5816 struct hdspm_config info; 5817 struct hdspm_status status; 5818 struct hdspm_version hdspm_version; 5819 struct hdspm_peak_rms *levels; 5820 struct hdspm_ltc ltc; 5821 unsigned int statusregister; 5822 long unsigned int s; 5823 int i = 0; 5824 5825 switch (cmd) { 5826 5827 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS: 5828 levels = &hdspm->peak_rms; 5829 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) { 5830 levels->input_peaks[i] = 5831 readl(hdspm->iobase + 5832 HDSPM_MADI_INPUT_PEAK + i*4); 5833 levels->playback_peaks[i] = 5834 readl(hdspm->iobase + 5835 HDSPM_MADI_PLAYBACK_PEAK + i*4); 5836 levels->output_peaks[i] = 5837 readl(hdspm->iobase + 5838 HDSPM_MADI_OUTPUT_PEAK + i*4); 5839 5840 levels->input_rms[i] = 5841 ((uint64_t) readl(hdspm->iobase + 5842 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) | 5843 (uint64_t) readl(hdspm->iobase + 5844 HDSPM_MADI_INPUT_RMS_L + i*4); 5845 levels->playback_rms[i] = 5846 ((uint64_t)readl(hdspm->iobase + 5847 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) | 5848 (uint64_t)readl(hdspm->iobase + 5849 HDSPM_MADI_PLAYBACK_RMS_L + i*4); 5850 levels->output_rms[i] = 5851 ((uint64_t)readl(hdspm->iobase + 5852 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) | 5853 (uint64_t)readl(hdspm->iobase + 5854 HDSPM_MADI_OUTPUT_RMS_L + i*4); 5855 } 5856 5857 if (hdspm->system_sample_rate > 96000) { 5858 levels->speed = qs; 5859 } else if (hdspm->system_sample_rate > 48000) { 5860 levels->speed = ds; 5861 } else { 5862 levels->speed = ss; 5863 } 5864 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2); 5865 5866 s = copy_to_user(argp, levels, sizeof(struct hdspm_peak_rms)); 5867 if (0 != s) { 5868 /* snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu 5869 [Levels]\n", sizeof(struct hdspm_peak_rms), s); 5870 */ 5871 return -EFAULT; 5872 } 5873 break; 5874 5875 case SNDRV_HDSPM_IOCTL_GET_LTC: 5876 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO); 5877 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4); 5878 if (i & HDSPM_TCO1_LTC_Input_valid) { 5879 switch (i & (HDSPM_TCO1_LTC_Format_LSB | 5880 HDSPM_TCO1_LTC_Format_MSB)) { 5881 case 0: 5882 ltc.format = fps_24; 5883 break; 5884 case HDSPM_TCO1_LTC_Format_LSB: 5885 ltc.format = fps_25; 5886 break; 5887 case HDSPM_TCO1_LTC_Format_MSB: 5888 ltc.format = fps_2997; 5889 break; 5890 default: 5891 ltc.format = 30; 5892 break; 5893 } 5894 if (i & HDSPM_TCO1_set_drop_frame_flag) { 5895 ltc.frame = drop_frame; 5896 } else { 5897 ltc.frame = full_frame; 5898 } 5899 } else { 5900 ltc.format = format_invalid; 5901 ltc.frame = frame_invalid; 5902 } 5903 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) { 5904 ltc.input_format = ntsc; 5905 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) { 5906 ltc.input_format = pal; 5907 } else { 5908 ltc.input_format = no_video; 5909 } 5910 5911 s = copy_to_user(argp, <c, sizeof(struct hdspm_ltc)); 5912 if (0 != s) { 5913 /* 5914 snd_printk(KERN_ERR "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */ 5915 return -EFAULT; 5916 } 5917 5918 break; 5919 5920 case SNDRV_HDSPM_IOCTL_GET_CONFIG: 5921 5922 memset(&info, 0, sizeof(info)); 5923 spin_lock_irq(&hdspm->lock); 5924 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm); 5925 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm); 5926 5927 info.system_sample_rate = hdspm->system_sample_rate; 5928 info.autosync_sample_rate = 5929 hdspm_external_sample_rate(hdspm); 5930 info.system_clock_mode = hdspm_system_clock_mode(hdspm); 5931 info.clock_source = hdspm_clock_source(hdspm); 5932 info.autosync_ref = hdspm_autosync_ref(hdspm); 5933 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut); 5934 info.passthru = 0; 5935 spin_unlock_irq(&hdspm->lock); 5936 if (copy_to_user(argp, &info, sizeof(info))) 5937 return -EFAULT; 5938 break; 5939 5940 case SNDRV_HDSPM_IOCTL_GET_STATUS: 5941 memset(&status, 0, sizeof(status)); 5942 5943 status.card_type = hdspm->io_type; 5944 5945 status.autosync_source = hdspm_autosync_ref(hdspm); 5946 5947 status.card_clock = 110069313433624ULL; 5948 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ); 5949 5950 switch (hdspm->io_type) { 5951 case MADI: 5952 case MADIface: 5953 status.card_specific.madi.sync_wc = 5954 hdspm_wc_sync_check(hdspm); 5955 status.card_specific.madi.sync_madi = 5956 hdspm_madi_sync_check(hdspm); 5957 status.card_specific.madi.sync_tco = 5958 hdspm_tco_sync_check(hdspm); 5959 status.card_specific.madi.sync_in = 5960 hdspm_sync_in_sync_check(hdspm); 5961 5962 statusregister = 5963 hdspm_read(hdspm, HDSPM_statusRegister); 5964 status.card_specific.madi.madi_input = 5965 (statusregister & HDSPM_AB_int) ? 1 : 0; 5966 status.card_specific.madi.channel_format = 5967 (statusregister & HDSPM_RX_64ch) ? 1 : 0; 5968 /* TODO: Mac driver sets it when f_s>48kHz */ 5969 status.card_specific.madi.frame_format = 0; 5970 5971 default: 5972 break; 5973 } 5974 5975 if (copy_to_user(argp, &status, sizeof(status))) 5976 return -EFAULT; 5977 5978 5979 break; 5980 5981 case SNDRV_HDSPM_IOCTL_GET_VERSION: 5982 memset(&hdspm_version, 0, sizeof(hdspm_version)); 5983 5984 hdspm_version.card_type = hdspm->io_type; 5985 strncpy(hdspm_version.cardname, hdspm->card_name, 5986 sizeof(hdspm_version.cardname)); 5987 hdspm_version.serial = hdspm->serial; 5988 hdspm_version.firmware_rev = hdspm->firmware_rev; 5989 hdspm_version.addons = 0; 5990 if (hdspm->tco) 5991 hdspm_version.addons |= HDSPM_ADDON_TCO; 5992 5993 if (copy_to_user(argp, &hdspm_version, 5994 sizeof(hdspm_version))) 5995 return -EFAULT; 5996 break; 5997 5998 case SNDRV_HDSPM_IOCTL_GET_MIXER: 5999 if (copy_from_user(&mixer, argp, sizeof(mixer))) 6000 return -EFAULT; 6001 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer, 6002 sizeof(struct hdspm_mixer))) 6003 return -EFAULT; 6004 break; 6005 6006 default: 6007 return -EINVAL; 6008 } 6009 return 0; 6010 } 6011 6012 static struct snd_pcm_ops snd_hdspm_playback_ops = { 6013 .open = snd_hdspm_playback_open, 6014 .close = snd_hdspm_playback_release, 6015 .ioctl = snd_hdspm_ioctl, 6016 .hw_params = snd_hdspm_hw_params, 6017 .hw_free = snd_hdspm_hw_free, 6018 .prepare = snd_hdspm_prepare, 6019 .trigger = snd_hdspm_trigger, 6020 .pointer = snd_hdspm_hw_pointer, 6021 .page = snd_pcm_sgbuf_ops_page, 6022 }; 6023 6024 static struct snd_pcm_ops snd_hdspm_capture_ops = { 6025 .open = snd_hdspm_capture_open, 6026 .close = snd_hdspm_capture_release, 6027 .ioctl = snd_hdspm_ioctl, 6028 .hw_params = snd_hdspm_hw_params, 6029 .hw_free = snd_hdspm_hw_free, 6030 .prepare = snd_hdspm_prepare, 6031 .trigger = snd_hdspm_trigger, 6032 .pointer = snd_hdspm_hw_pointer, 6033 .page = snd_pcm_sgbuf_ops_page, 6034 }; 6035 6036 static int snd_hdspm_create_hwdep(struct snd_card *card, 6037 struct hdspm *hdspm) 6038 { 6039 struct snd_hwdep *hw; 6040 int err; 6041 6042 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw); 6043 if (err < 0) 6044 return err; 6045 6046 hdspm->hwdep = hw; 6047 hw->private_data = hdspm; 6048 strcpy(hw->name, "HDSPM hwdep interface"); 6049 6050 hw->ops.open = snd_hdspm_hwdep_dummy_op; 6051 hw->ops.ioctl = snd_hdspm_hwdep_ioctl; 6052 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl; 6053 hw->ops.release = snd_hdspm_hwdep_dummy_op; 6054 6055 return 0; 6056 } 6057 6058 6059 /*------------------------------------------------------------ 6060 memory interface 6061 ------------------------------------------------------------*/ 6062 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm) 6063 { 6064 int err; 6065 struct snd_pcm *pcm; 6066 size_t wanted; 6067 6068 pcm = hdspm->pcm; 6069 6070 wanted = HDSPM_DMA_AREA_BYTES; 6071 6072 err = 6073 snd_pcm_lib_preallocate_pages_for_all(pcm, 6074 SNDRV_DMA_TYPE_DEV_SG, 6075 snd_dma_pci_data(hdspm->pci), 6076 wanted, 6077 wanted); 6078 if (err < 0) { 6079 snd_printdd("Could not preallocate %zd Bytes\n", wanted); 6080 6081 return err; 6082 } else 6083 snd_printdd(" Preallocated %zd Bytes\n", wanted); 6084 6085 return 0; 6086 } 6087 6088 6089 static void hdspm_set_sgbuf(struct hdspm *hdspm, 6090 struct snd_pcm_substream *substream, 6091 unsigned int reg, int channels) 6092 { 6093 int i; 6094 6095 /* continuous memory segment */ 6096 for (i = 0; i < (channels * 16); i++) 6097 hdspm_write(hdspm, reg + 4 * i, 6098 snd_pcm_sgbuf_get_addr(substream, 4096 * i)); 6099 } 6100 6101 6102 /* ------------- ALSA Devices ---------------------------- */ 6103 static int snd_hdspm_create_pcm(struct snd_card *card, 6104 struct hdspm *hdspm) 6105 { 6106 struct snd_pcm *pcm; 6107 int err; 6108 6109 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm); 6110 if (err < 0) 6111 return err; 6112 6113 hdspm->pcm = pcm; 6114 pcm->private_data = hdspm; 6115 strcpy(pcm->name, hdspm->card_name); 6116 6117 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, 6118 &snd_hdspm_playback_ops); 6119 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, 6120 &snd_hdspm_capture_ops); 6121 6122 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 6123 6124 err = snd_hdspm_preallocate_memory(hdspm); 6125 if (err < 0) 6126 return err; 6127 6128 return 0; 6129 } 6130 6131 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm) 6132 { 6133 int i; 6134 6135 for (i = 0; i < hdspm->midiPorts; i++) 6136 snd_hdspm_flush_midi_input(hdspm, i); 6137 } 6138 6139 static int snd_hdspm_create_alsa_devices(struct snd_card *card, 6140 struct hdspm *hdspm) 6141 { 6142 int err, i; 6143 6144 snd_printdd("Create card...\n"); 6145 err = snd_hdspm_create_pcm(card, hdspm); 6146 if (err < 0) 6147 return err; 6148 6149 i = 0; 6150 while (i < hdspm->midiPorts) { 6151 err = snd_hdspm_create_midi(card, hdspm, i); 6152 if (err < 0) { 6153 return err; 6154 } 6155 i++; 6156 } 6157 6158 err = snd_hdspm_create_controls(card, hdspm); 6159 if (err < 0) 6160 return err; 6161 6162 err = snd_hdspm_create_hwdep(card, hdspm); 6163 if (err < 0) 6164 return err; 6165 6166 snd_printdd("proc init...\n"); 6167 snd_hdspm_proc_init(hdspm); 6168 6169 hdspm->system_sample_rate = -1; 6170 hdspm->last_external_sample_rate = -1; 6171 hdspm->last_internal_sample_rate = -1; 6172 hdspm->playback_pid = -1; 6173 hdspm->capture_pid = -1; 6174 hdspm->capture_substream = NULL; 6175 hdspm->playback_substream = NULL; 6176 6177 snd_printdd("Set defaults...\n"); 6178 err = snd_hdspm_set_defaults(hdspm); 6179 if (err < 0) 6180 return err; 6181 6182 snd_printdd("Update mixer controls...\n"); 6183 hdspm_update_simple_mixer_controls(hdspm); 6184 6185 snd_printdd("Initializeing complete ???\n"); 6186 6187 err = snd_card_register(card); 6188 if (err < 0) { 6189 snd_printk(KERN_ERR "HDSPM: error registering card\n"); 6190 return err; 6191 } 6192 6193 snd_printdd("... yes now\n"); 6194 6195 return 0; 6196 } 6197 6198 static int snd_hdspm_create(struct snd_card *card, 6199 struct hdspm *hdspm) 6200 { 6201 6202 struct pci_dev *pci = hdspm->pci; 6203 int err; 6204 unsigned long io_extent; 6205 6206 hdspm->irq = -1; 6207 hdspm->card = card; 6208 6209 spin_lock_init(&hdspm->lock); 6210 6211 pci_read_config_word(hdspm->pci, 6212 PCI_CLASS_REVISION, &hdspm->firmware_rev); 6213 6214 strcpy(card->mixername, "Xilinx FPGA"); 6215 strcpy(card->driver, "HDSPM"); 6216 6217 switch (hdspm->firmware_rev) { 6218 case HDSPM_RAYDAT_REV: 6219 hdspm->io_type = RayDAT; 6220 hdspm->card_name = "RME RayDAT"; 6221 hdspm->midiPorts = 2; 6222 break; 6223 case HDSPM_AIO_REV: 6224 hdspm->io_type = AIO; 6225 hdspm->card_name = "RME AIO"; 6226 hdspm->midiPorts = 1; 6227 break; 6228 case HDSPM_MADIFACE_REV: 6229 hdspm->io_type = MADIface; 6230 hdspm->card_name = "RME MADIface"; 6231 hdspm->midiPorts = 1; 6232 break; 6233 default: 6234 if ((hdspm->firmware_rev == 0xf0) || 6235 ((hdspm->firmware_rev >= 0xe6) && 6236 (hdspm->firmware_rev <= 0xea))) { 6237 hdspm->io_type = AES32; 6238 hdspm->card_name = "RME AES32"; 6239 hdspm->midiPorts = 2; 6240 } else if ((hdspm->firmware_rev == 0xd2) || 6241 ((hdspm->firmware_rev >= 0xc8) && 6242 (hdspm->firmware_rev <= 0xcf))) { 6243 hdspm->io_type = MADI; 6244 hdspm->card_name = "RME MADI"; 6245 hdspm->midiPorts = 3; 6246 } else { 6247 snd_printk(KERN_ERR 6248 "HDSPM: unknown firmware revision %x\n", 6249 hdspm->firmware_rev); 6250 return -ENODEV; 6251 } 6252 } 6253 6254 err = pci_enable_device(pci); 6255 if (err < 0) 6256 return err; 6257 6258 pci_set_master(hdspm->pci); 6259 6260 err = pci_request_regions(pci, "hdspm"); 6261 if (err < 0) 6262 return err; 6263 6264 hdspm->port = pci_resource_start(pci, 0); 6265 io_extent = pci_resource_len(pci, 0); 6266 6267 snd_printdd("grabbed memory region 0x%lx-0x%lx\n", 6268 hdspm->port, hdspm->port + io_extent - 1); 6269 6270 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent); 6271 if (!hdspm->iobase) { 6272 snd_printk(KERN_ERR "HDSPM: " 6273 "unable to remap region 0x%lx-0x%lx\n", 6274 hdspm->port, hdspm->port + io_extent - 1); 6275 return -EBUSY; 6276 } 6277 snd_printdd("remapped region (0x%lx) 0x%lx-0x%lx\n", 6278 (unsigned long)hdspm->iobase, hdspm->port, 6279 hdspm->port + io_extent - 1); 6280 6281 if (request_irq(pci->irq, snd_hdspm_interrupt, 6282 IRQF_SHARED, KBUILD_MODNAME, hdspm)) { 6283 snd_printk(KERN_ERR "HDSPM: unable to use IRQ %d\n", pci->irq); 6284 return -EBUSY; 6285 } 6286 6287 snd_printdd("use IRQ %d\n", pci->irq); 6288 6289 hdspm->irq = pci->irq; 6290 6291 snd_printdd("kmalloc Mixer memory of %zd Bytes\n", 6292 sizeof(struct hdspm_mixer)); 6293 hdspm->mixer = kzalloc(sizeof(struct hdspm_mixer), GFP_KERNEL); 6294 if (!hdspm->mixer) { 6295 snd_printk(KERN_ERR "HDSPM: " 6296 "unable to kmalloc Mixer memory of %d Bytes\n", 6297 (int)sizeof(struct hdspm_mixer)); 6298 return -ENOMEM; 6299 } 6300 6301 hdspm->port_names_in = NULL; 6302 hdspm->port_names_out = NULL; 6303 6304 switch (hdspm->io_type) { 6305 case AES32: 6306 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS; 6307 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS; 6308 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS; 6309 6310 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6311 channel_map_aes32; 6312 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6313 channel_map_aes32; 6314 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6315 channel_map_aes32; 6316 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6317 texts_ports_aes32; 6318 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6319 texts_ports_aes32; 6320 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6321 texts_ports_aes32; 6322 6323 hdspm->max_channels_out = hdspm->max_channels_in = 6324 AES32_CHANNELS; 6325 hdspm->port_names_in = hdspm->port_names_out = 6326 texts_ports_aes32; 6327 hdspm->channel_map_in = hdspm->channel_map_out = 6328 channel_map_aes32; 6329 6330 break; 6331 6332 case MADI: 6333 case MADIface: 6334 hdspm->ss_in_channels = hdspm->ss_out_channels = 6335 MADI_SS_CHANNELS; 6336 hdspm->ds_in_channels = hdspm->ds_out_channels = 6337 MADI_DS_CHANNELS; 6338 hdspm->qs_in_channels = hdspm->qs_out_channels = 6339 MADI_QS_CHANNELS; 6340 6341 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6342 channel_map_unity_ss; 6343 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6344 channel_map_unity_ss; 6345 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6346 channel_map_unity_ss; 6347 6348 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6349 texts_ports_madi; 6350 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6351 texts_ports_madi; 6352 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6353 texts_ports_madi; 6354 break; 6355 6356 case AIO: 6357 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) { 6358 snd_printk(KERN_INFO "HDSPM: AEB input board found, but not supported\n"); 6359 } 6360 6361 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS; 6362 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS; 6363 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS; 6364 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS; 6365 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS; 6366 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS; 6367 6368 hdspm->channel_map_out_ss = channel_map_aio_out_ss; 6369 hdspm->channel_map_out_ds = channel_map_aio_out_ds; 6370 hdspm->channel_map_out_qs = channel_map_aio_out_qs; 6371 6372 hdspm->channel_map_in_ss = channel_map_aio_in_ss; 6373 hdspm->channel_map_in_ds = channel_map_aio_in_ds; 6374 hdspm->channel_map_in_qs = channel_map_aio_in_qs; 6375 6376 hdspm->port_names_in_ss = texts_ports_aio_in_ss; 6377 hdspm->port_names_out_ss = texts_ports_aio_out_ss; 6378 hdspm->port_names_in_ds = texts_ports_aio_in_ds; 6379 hdspm->port_names_out_ds = texts_ports_aio_out_ds; 6380 hdspm->port_names_in_qs = texts_ports_aio_in_qs; 6381 hdspm->port_names_out_qs = texts_ports_aio_out_qs; 6382 6383 break; 6384 6385 case RayDAT: 6386 hdspm->ss_in_channels = hdspm->ss_out_channels = 6387 RAYDAT_SS_CHANNELS; 6388 hdspm->ds_in_channels = hdspm->ds_out_channels = 6389 RAYDAT_DS_CHANNELS; 6390 hdspm->qs_in_channels = hdspm->qs_out_channels = 6391 RAYDAT_QS_CHANNELS; 6392 6393 hdspm->max_channels_in = RAYDAT_SS_CHANNELS; 6394 hdspm->max_channels_out = RAYDAT_SS_CHANNELS; 6395 6396 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss = 6397 channel_map_raydat_ss; 6398 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds = 6399 channel_map_raydat_ds; 6400 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs = 6401 channel_map_raydat_qs; 6402 hdspm->channel_map_in = hdspm->channel_map_out = 6403 channel_map_raydat_ss; 6404 6405 hdspm->port_names_in_ss = hdspm->port_names_out_ss = 6406 texts_ports_raydat_ss; 6407 hdspm->port_names_in_ds = hdspm->port_names_out_ds = 6408 texts_ports_raydat_ds; 6409 hdspm->port_names_in_qs = hdspm->port_names_out_qs = 6410 texts_ports_raydat_qs; 6411 6412 6413 break; 6414 6415 } 6416 6417 /* TCO detection */ 6418 switch (hdspm->io_type) { 6419 case AIO: 6420 case RayDAT: 6421 if (hdspm_read(hdspm, HDSPM_statusRegister2) & 6422 HDSPM_s2_tco_detect) { 6423 hdspm->midiPorts++; 6424 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6425 GFP_KERNEL); 6426 if (NULL != hdspm->tco) { 6427 hdspm_tco_write(hdspm); 6428 } 6429 snd_printk(KERN_INFO "HDSPM: AIO/RayDAT TCO module found\n"); 6430 } else { 6431 hdspm->tco = NULL; 6432 } 6433 break; 6434 6435 case MADI: 6436 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) { 6437 hdspm->midiPorts++; 6438 hdspm->tco = kzalloc(sizeof(struct hdspm_tco), 6439 GFP_KERNEL); 6440 if (NULL != hdspm->tco) { 6441 hdspm_tco_write(hdspm); 6442 } 6443 snd_printk(KERN_INFO "HDSPM: MADI TCO module found\n"); 6444 } else { 6445 hdspm->tco = NULL; 6446 } 6447 break; 6448 6449 default: 6450 hdspm->tco = NULL; 6451 } 6452 6453 /* texts */ 6454 switch (hdspm->io_type) { 6455 case AES32: 6456 if (hdspm->tco) { 6457 hdspm->texts_autosync = texts_autosync_aes_tco; 6458 hdspm->texts_autosync_items = 10; 6459 } else { 6460 hdspm->texts_autosync = texts_autosync_aes; 6461 hdspm->texts_autosync_items = 9; 6462 } 6463 break; 6464 6465 case MADI: 6466 if (hdspm->tco) { 6467 hdspm->texts_autosync = texts_autosync_madi_tco; 6468 hdspm->texts_autosync_items = 4; 6469 } else { 6470 hdspm->texts_autosync = texts_autosync_madi; 6471 hdspm->texts_autosync_items = 3; 6472 } 6473 break; 6474 6475 case MADIface: 6476 6477 break; 6478 6479 case RayDAT: 6480 if (hdspm->tco) { 6481 hdspm->texts_autosync = texts_autosync_raydat_tco; 6482 hdspm->texts_autosync_items = 9; 6483 } else { 6484 hdspm->texts_autosync = texts_autosync_raydat; 6485 hdspm->texts_autosync_items = 8; 6486 } 6487 break; 6488 6489 case AIO: 6490 if (hdspm->tco) { 6491 hdspm->texts_autosync = texts_autosync_aio_tco; 6492 hdspm->texts_autosync_items = 6; 6493 } else { 6494 hdspm->texts_autosync = texts_autosync_aio; 6495 hdspm->texts_autosync_items = 5; 6496 } 6497 break; 6498 6499 } 6500 6501 tasklet_init(&hdspm->midi_tasklet, 6502 hdspm_midi_tasklet, (unsigned long) hdspm); 6503 6504 6505 if (hdspm->io_type != MADIface) { 6506 hdspm->serial = (hdspm_read(hdspm, 6507 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF; 6508 /* id contains either a user-provided value or the default 6509 * NULL. If it's the default, we're safe to 6510 * fill card->id with the serial number. 6511 * 6512 * If the serial number is 0xFFFFFF, then we're dealing with 6513 * an old PCI revision that comes without a sane number. In 6514 * this case, we don't set card->id to avoid collisions 6515 * when running with multiple cards. 6516 */ 6517 if (NULL == id[hdspm->dev] && hdspm->serial != 0xFFFFFF) { 6518 sprintf(card->id, "HDSPMx%06x", hdspm->serial); 6519 snd_card_set_id(card, card->id); 6520 } 6521 } 6522 6523 snd_printdd("create alsa devices.\n"); 6524 err = snd_hdspm_create_alsa_devices(card, hdspm); 6525 if (err < 0) 6526 return err; 6527 6528 snd_hdspm_initialize_midi_flush(hdspm); 6529 6530 return 0; 6531 } 6532 6533 6534 static int snd_hdspm_free(struct hdspm * hdspm) 6535 { 6536 6537 if (hdspm->port) { 6538 6539 /* stop th audio, and cancel all interrupts */ 6540 hdspm->control_register &= 6541 ~(HDSPM_Start | HDSPM_AudioInterruptEnable | 6542 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable | 6543 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable); 6544 hdspm_write(hdspm, HDSPM_controlRegister, 6545 hdspm->control_register); 6546 } 6547 6548 if (hdspm->irq >= 0) 6549 free_irq(hdspm->irq, (void *) hdspm); 6550 6551 kfree(hdspm->mixer); 6552 6553 if (hdspm->iobase) 6554 iounmap(hdspm->iobase); 6555 6556 if (hdspm->port) 6557 pci_release_regions(hdspm->pci); 6558 6559 pci_disable_device(hdspm->pci); 6560 return 0; 6561 } 6562 6563 6564 static void snd_hdspm_card_free(struct snd_card *card) 6565 { 6566 struct hdspm *hdspm = card->private_data; 6567 6568 if (hdspm) 6569 snd_hdspm_free(hdspm); 6570 } 6571 6572 6573 static int snd_hdspm_probe(struct pci_dev *pci, 6574 const struct pci_device_id *pci_id) 6575 { 6576 static int dev; 6577 struct hdspm *hdspm; 6578 struct snd_card *card; 6579 int err; 6580 6581 if (dev >= SNDRV_CARDS) 6582 return -ENODEV; 6583 if (!enable[dev]) { 6584 dev++; 6585 return -ENOENT; 6586 } 6587 6588 err = snd_card_create(index[dev], id[dev], 6589 THIS_MODULE, sizeof(struct hdspm), &card); 6590 if (err < 0) 6591 return err; 6592 6593 hdspm = card->private_data; 6594 card->private_free = snd_hdspm_card_free; 6595 hdspm->dev = dev; 6596 hdspm->pci = pci; 6597 6598 snd_card_set_dev(card, &pci->dev); 6599 6600 err = snd_hdspm_create(card, hdspm); 6601 if (err < 0) { 6602 snd_card_free(card); 6603 return err; 6604 } 6605 6606 if (hdspm->io_type != MADIface) { 6607 sprintf(card->shortname, "%s_%x", 6608 hdspm->card_name, 6609 hdspm->serial); 6610 sprintf(card->longname, "%s S/N 0x%x at 0x%lx, irq %d", 6611 hdspm->card_name, 6612 hdspm->serial, 6613 hdspm->port, hdspm->irq); 6614 } else { 6615 sprintf(card->shortname, "%s", hdspm->card_name); 6616 sprintf(card->longname, "%s at 0x%lx, irq %d", 6617 hdspm->card_name, hdspm->port, hdspm->irq); 6618 } 6619 6620 err = snd_card_register(card); 6621 if (err < 0) { 6622 snd_card_free(card); 6623 return err; 6624 } 6625 6626 pci_set_drvdata(pci, card); 6627 6628 dev++; 6629 return 0; 6630 } 6631 6632 static void snd_hdspm_remove(struct pci_dev *pci) 6633 { 6634 snd_card_free(pci_get_drvdata(pci)); 6635 pci_set_drvdata(pci, NULL); 6636 } 6637 6638 static struct pci_driver hdspm_driver = { 6639 .name = KBUILD_MODNAME, 6640 .id_table = snd_hdspm_ids, 6641 .probe = snd_hdspm_probe, 6642 .remove = snd_hdspm_remove, 6643 }; 6644 6645 module_pci_driver(hdspm_driver); 6646