1 /* 2 * ALSA driver for RME Hammerfall DSP audio interface(s) 3 * 4 * Copyright (c) 2002 Paul Davis 5 * Marcus Andersson 6 * Thomas Charbonnel 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/slab.h> 28 #include <linux/pci.h> 29 #include <linux/firmware.h> 30 #include <linux/moduleparam.h> 31 32 #include <sound/core.h> 33 #include <sound/control.h> 34 #include <sound/pcm.h> 35 #include <sound/info.h> 36 #include <sound/asoundef.h> 37 #include <sound/rawmidi.h> 38 #include <sound/hwdep.h> 39 #include <sound/initval.h> 40 #include <sound/hdsp.h> 41 42 #include <asm/byteorder.h> 43 #include <asm/current.h> 44 #include <asm/io.h> 45 46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 49 50 module_param_array(index, int, NULL, 0444); 51 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); 52 module_param_array(id, charp, NULL, 0444); 53 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); 54 module_param_array(enable, bool, NULL, 0444); 55 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); 56 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); 57 MODULE_DESCRIPTION("RME Hammerfall DSP"); 58 MODULE_LICENSE("GPL"); 59 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP}," 60 "{RME HDSP-9652}," 61 "{RME HDSP-9632}}"); 62 #ifdef HDSP_FW_LOADER 63 MODULE_FIRMWARE("multiface_firmware.bin"); 64 MODULE_FIRMWARE("multiface_firmware_rev11.bin"); 65 MODULE_FIRMWARE("digiface_firmware.bin"); 66 MODULE_FIRMWARE("digiface_firmware_rev11.bin"); 67 #endif 68 69 #define HDSP_MAX_CHANNELS 26 70 #define HDSP_MAX_DS_CHANNELS 14 71 #define HDSP_MAX_QS_CHANNELS 8 72 #define DIGIFACE_SS_CHANNELS 26 73 #define DIGIFACE_DS_CHANNELS 14 74 #define MULTIFACE_SS_CHANNELS 18 75 #define MULTIFACE_DS_CHANNELS 14 76 #define H9652_SS_CHANNELS 26 77 #define H9652_DS_CHANNELS 14 78 /* This does not include possible Analog Extension Boards 79 AEBs are detected at card initialization 80 */ 81 #define H9632_SS_CHANNELS 12 82 #define H9632_DS_CHANNELS 8 83 #define H9632_QS_CHANNELS 4 84 85 /* Write registers. These are defined as byte-offsets from the iobase value. 86 */ 87 #define HDSP_resetPointer 0 88 #define HDSP_freqReg 0 89 #define HDSP_outputBufferAddress 32 90 #define HDSP_inputBufferAddress 36 91 #define HDSP_controlRegister 64 92 #define HDSP_interruptConfirmation 96 93 #define HDSP_outputEnable 128 94 #define HDSP_control2Reg 256 95 #define HDSP_midiDataOut0 352 96 #define HDSP_midiDataOut1 356 97 #define HDSP_fifoData 368 98 #define HDSP_inputEnable 384 99 100 /* Read registers. These are defined as byte-offsets from the iobase value 101 */ 102 103 #define HDSP_statusRegister 0 104 #define HDSP_timecode 128 105 #define HDSP_status2Register 192 106 #define HDSP_midiDataIn0 360 107 #define HDSP_midiDataIn1 364 108 #define HDSP_midiStatusOut0 384 109 #define HDSP_midiStatusOut1 388 110 #define HDSP_midiStatusIn0 392 111 #define HDSP_midiStatusIn1 396 112 #define HDSP_fifoStatus 400 113 114 /* the meters are regular i/o-mapped registers, but offset 115 considerably from the rest. the peak registers are reset 116 when read; the least-significant 4 bits are full-scale counters; 117 the actual peak value is in the most-significant 24 bits. 118 */ 119 120 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ 121 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ 122 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ 123 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ 124 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ 125 126 127 /* This is for H9652 cards 128 Peak values are read downward from the base 129 Rms values are read upward 130 There are rms values for the outputs too 131 26*3 values are read in ss mode 132 14*3 in ds mode, with no gap between values 133 */ 134 #define HDSP_9652_peakBase 7164 135 #define HDSP_9652_rmsBase 4096 136 137 /* c.f. the hdsp_9632_meters_t struct */ 138 #define HDSP_9632_metersBase 4096 139 140 #define HDSP_IO_EXTENT 7168 141 142 /* control2 register bits */ 143 144 #define HDSP_TMS 0x01 145 #define HDSP_TCK 0x02 146 #define HDSP_TDI 0x04 147 #define HDSP_JTAG 0x08 148 #define HDSP_PWDN 0x10 149 #define HDSP_PROGRAM 0x020 150 #define HDSP_CONFIG_MODE_0 0x040 151 #define HDSP_CONFIG_MODE_1 0x080 152 #define HDSP_VERSION_BIT 0x100 153 #define HDSP_BIGENDIAN_MODE 0x200 154 #define HDSP_RD_MULTIPLE 0x400 155 #define HDSP_9652_ENABLE_MIXER 0x800 156 #define HDSP_TDO 0x10000000 157 158 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0) 159 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1) 160 161 /* Control Register bits */ 162 163 #define HDSP_Start (1<<0) /* start engine */ 164 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ 165 #define HDSP_Latency1 (1<<2) /* [ see above ] */ 166 #define HDSP_Latency2 (1<<3) /* [ see above ] */ 167 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ 168 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ 169 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ 170 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ 171 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 172 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ 173 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ 174 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ 175 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ 176 #define HDSP_SyncRef2 (1<<13) 177 #define HDSP_SPDIFInputSelect0 (1<<14) 178 #define HDSP_SPDIFInputSelect1 (1<<15) 179 #define HDSP_SyncRef0 (1<<16) 180 #define HDSP_SyncRef1 (1<<17) 181 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ 182 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ 183 #define HDSP_Midi0InterruptEnable (1<<22) 184 #define HDSP_Midi1InterruptEnable (1<<23) 185 #define HDSP_LineOut (1<<24) 186 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ 187 #define HDSP_ADGain1 (1<<26) 188 #define HDSP_DAGain0 (1<<27) 189 #define HDSP_DAGain1 (1<<28) 190 #define HDSP_PhoneGain0 (1<<29) 191 #define HDSP_PhoneGain1 (1<<30) 192 #define HDSP_QuadSpeed (1<<31) 193 194 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) 195 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask 196 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 197 #define HDSP_ADGainLowGain 0 198 199 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) 200 #define HDSP_DAGainHighGain HDSP_DAGainMask 201 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 202 #define HDSP_DAGainMinus10dBV 0 203 204 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 205 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 206 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 207 #define HDSP_PhoneGainMinus12dB 0 208 209 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) 210 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) 211 212 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 213 #define HDSP_SPDIFInputADAT1 0 214 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) 215 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) 216 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 217 218 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) 219 #define HDSP_SyncRef_ADAT1 0 220 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) 221 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) 222 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) 223 #define HDSP_SyncRef_WORD (HDSP_SyncRef2) 224 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) 225 226 /* Sample Clock Sources */ 227 228 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 229 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 230 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 231 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 232 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 233 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 234 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 235 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 236 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 237 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 238 239 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ 240 241 #define HDSP_SYNC_FROM_WORD 0 242 #define HDSP_SYNC_FROM_SPDIF 1 243 #define HDSP_SYNC_FROM_ADAT1 2 244 #define HDSP_SYNC_FROM_ADAT_SYNC 3 245 #define HDSP_SYNC_FROM_ADAT2 4 246 #define HDSP_SYNC_FROM_ADAT3 5 247 248 /* SyncCheck status */ 249 250 #define HDSP_SYNC_CHECK_NO_LOCK 0 251 #define HDSP_SYNC_CHECK_LOCK 1 252 #define HDSP_SYNC_CHECK_SYNC 2 253 254 /* AutoSync references - used by "autosync_ref" control switch */ 255 256 #define HDSP_AUTOSYNC_FROM_WORD 0 257 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 258 #define HDSP_AUTOSYNC_FROM_SPDIF 2 259 #define HDSP_AUTOSYNC_FROM_NONE 3 260 #define HDSP_AUTOSYNC_FROM_ADAT1 4 261 #define HDSP_AUTOSYNC_FROM_ADAT2 5 262 #define HDSP_AUTOSYNC_FROM_ADAT3 6 263 264 /* Possible sources of S/PDIF input */ 265 266 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ 267 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ 268 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ 269 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ 270 271 #define HDSP_Frequency32KHz HDSP_Frequency0 272 #define HDSP_Frequency44_1KHz HDSP_Frequency1 273 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) 274 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) 275 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) 276 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 277 /* For H9632 cards */ 278 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) 279 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) 280 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 281 /* RME says n = 104857600000000, but in the windows MADI driver, I see: 282 return 104857600000000 / rate; // 100 MHz 283 return 110100480000000 / rate; // 105 MHz 284 */ 285 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */ 286 287 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) 288 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) 289 290 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) 291 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) 292 293 /* Status Register bits */ 294 295 #define HDSP_audioIRQPending (1<<0) 296 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ 297 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ 298 #define HDSP_Lock1 (1<<2) 299 #define HDSP_Lock0 (1<<3) 300 #define HDSP_SPDIFSync (1<<4) 301 #define HDSP_TimecodeLock (1<<5) 302 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 303 #define HDSP_Sync2 (1<<16) 304 #define HDSP_Sync1 (1<<17) 305 #define HDSP_Sync0 (1<<18) 306 #define HDSP_DoubleSpeedStatus (1<<19) 307 #define HDSP_ConfigError (1<<20) 308 #define HDSP_DllError (1<<21) 309 #define HDSP_spdifFrequency0 (1<<22) 310 #define HDSP_spdifFrequency1 (1<<23) 311 #define HDSP_spdifFrequency2 (1<<24) 312 #define HDSP_SPDIFErrorFlag (1<<25) 313 #define HDSP_BufferID (1<<26) 314 #define HDSP_TimecodeSync (1<<27) 315 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ 316 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ 317 #define HDSP_midi0IRQPending (1<<30) 318 #define HDSP_midi1IRQPending (1<<31) 319 320 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) 321 322 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) 323 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) 324 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) 325 326 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) 327 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) 328 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) 329 330 /* This is for H9632 cards */ 331 #define HDSP_spdifFrequency128KHz HDSP_spdifFrequencyMask 332 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 333 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) 334 335 /* Status2 Register bits */ 336 337 #define HDSP_version0 (1<<0) 338 #define HDSP_version1 (1<<1) 339 #define HDSP_version2 (1<<2) 340 #define HDSP_wc_lock (1<<3) 341 #define HDSP_wc_sync (1<<4) 342 #define HDSP_inp_freq0 (1<<5) 343 #define HDSP_inp_freq1 (1<<6) 344 #define HDSP_inp_freq2 (1<<7) 345 #define HDSP_SelSyncRef0 (1<<8) 346 #define HDSP_SelSyncRef1 (1<<9) 347 #define HDSP_SelSyncRef2 (1<<10) 348 349 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) 350 351 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) 352 #define HDSP_systemFrequency32 (HDSP_inp_freq0) 353 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1) 354 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) 355 #define HDSP_systemFrequency64 (HDSP_inp_freq2) 356 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) 357 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) 358 /* FIXME : more values for 9632 cards ? */ 359 360 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) 361 #define HDSP_SelSyncRef_ADAT1 0 362 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) 363 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) 364 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) 365 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) 366 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) 367 368 /* Card state flags */ 369 370 #define HDSP_InitializationComplete (1<<0) 371 #define HDSP_FirmwareLoaded (1<<1) 372 #define HDSP_FirmwareCached (1<<2) 373 374 /* FIFO wait times, defined in terms of 1/10ths of msecs */ 375 376 #define HDSP_LONG_WAIT 5000 377 #define HDSP_SHORT_WAIT 30 378 379 #define UNITY_GAIN 32768 380 #define MINUS_INFINITY_GAIN 0 381 382 /* the size of a substream (1 mono data stream) */ 383 384 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) 385 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) 386 387 /* the size of the area we need to allocate for DMA transfers. the 388 size is the same regardless of the number of channels - the 389 Multiface still uses the same memory area. 390 391 Note that we allocate 1 more channel than is apparently needed 392 because the h/w seems to write 1 byte beyond the end of the last 393 page. Sigh. 394 */ 395 396 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) 397 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 398 399 /* use hotplug firmeare loader? */ 400 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) 401 #if !defined(HDSP_USE_HWDEP_LOADER) && !defined(CONFIG_SND_HDSP) 402 #define HDSP_FW_LOADER 403 #endif 404 #endif 405 406 struct hdsp_9632_meters { 407 u32 input_peak[16]; 408 u32 playback_peak[16]; 409 u32 output_peak[16]; 410 u32 xxx_peak[16]; 411 u32 padding[64]; 412 u32 input_rms_low[16]; 413 u32 playback_rms_low[16]; 414 u32 output_rms_low[16]; 415 u32 xxx_rms_low[16]; 416 u32 input_rms_high[16]; 417 u32 playback_rms_high[16]; 418 u32 output_rms_high[16]; 419 u32 xxx_rms_high[16]; 420 }; 421 422 struct hdsp_midi { 423 struct hdsp *hdsp; 424 int id; 425 struct snd_rawmidi *rmidi; 426 struct snd_rawmidi_substream *input; 427 struct snd_rawmidi_substream *output; 428 char istimer; /* timer in use */ 429 struct timer_list timer; 430 spinlock_t lock; 431 int pending; 432 }; 433 434 struct hdsp { 435 spinlock_t lock; 436 struct snd_pcm_substream *capture_substream; 437 struct snd_pcm_substream *playback_substream; 438 struct hdsp_midi midi[2]; 439 struct tasklet_struct midi_tasklet; 440 int use_midi_tasklet; 441 int precise_ptr; 442 u32 control_register; /* cached value */ 443 u32 control2_register; /* cached value */ 444 u32 creg_spdif; 445 u32 creg_spdif_stream; 446 int clock_source_locked; 447 char *card_name; /* digiface/multiface */ 448 enum HDSP_IO_Type io_type; /* ditto, but for code use */ 449 unsigned short firmware_rev; 450 unsigned short state; /* stores state bits */ 451 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */ 452 size_t period_bytes; /* guess what this is */ 453 unsigned char max_channels; 454 unsigned char qs_in_channels; /* quad speed mode for H9632 */ 455 unsigned char ds_in_channels; 456 unsigned char ss_in_channels; /* different for multiface/digiface */ 457 unsigned char qs_out_channels; 458 unsigned char ds_out_channels; 459 unsigned char ss_out_channels; 460 461 struct snd_dma_buffer capture_dma_buf; 462 struct snd_dma_buffer playback_dma_buf; 463 unsigned char *capture_buffer; /* suitably aligned address */ 464 unsigned char *playback_buffer; /* suitably aligned address */ 465 466 pid_t capture_pid; 467 pid_t playback_pid; 468 int running; 469 int system_sample_rate; 470 char *channel_map; 471 int dev; 472 int irq; 473 unsigned long port; 474 void __iomem *iobase; 475 struct snd_card *card; 476 struct snd_pcm *pcm; 477 struct snd_hwdep *hwdep; 478 struct pci_dev *pci; 479 struct snd_kcontrol *spdif_ctl; 480 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 481 unsigned int dds_value; /* last value written to freq register */ 482 }; 483 484 /* These tables map the ALSA channels 1..N to the channels that we 485 need to use in order to find the relevant channel buffer. RME 486 refer to this kind of mapping as between "the ADAT channel and 487 the DMA channel." We index it using the logical audio channel, 488 and the value is the DMA channel (i.e. channel buffer number) 489 where the data for that channel can be read/written from/to. 490 */ 491 492 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = { 493 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 494 18, 19, 20, 21, 22, 23, 24, 25 495 }; 496 497 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ 498 /* Analog */ 499 0, 1, 2, 3, 4, 5, 6, 7, 500 /* ADAT 2 */ 501 16, 17, 18, 19, 20, 21, 22, 23, 502 /* SPDIF */ 503 24, 25, 504 -1, -1, -1, -1, -1, -1, -1, -1 505 }; 506 507 static char channel_map_ds[HDSP_MAX_CHANNELS] = { 508 /* ADAT channels are remapped */ 509 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 510 /* channels 12 and 13 are S/PDIF */ 511 24, 25, 512 /* others don't exist */ 513 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 514 }; 515 516 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { 517 /* ADAT channels */ 518 0, 1, 2, 3, 4, 5, 6, 7, 519 /* SPDIF */ 520 8, 9, 521 /* Analog */ 522 10, 11, 523 /* AO4S-192 and AI4S-192 extension boards */ 524 12, 13, 14, 15, 525 /* others don't exist */ 526 -1, -1, -1, -1, -1, -1, -1, -1, 527 -1, -1 528 }; 529 530 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { 531 /* ADAT */ 532 1, 3, 5, 7, 533 /* SPDIF */ 534 8, 9, 535 /* Analog */ 536 10, 11, 537 /* AO4S-192 and AI4S-192 extension boards */ 538 12, 13, 14, 15, 539 /* others don't exist */ 540 -1, -1, -1, -1, -1, -1, -1, -1, 541 -1, -1, -1, -1, -1, -1 542 }; 543 544 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { 545 /* ADAT is disabled in this mode */ 546 /* SPDIF */ 547 8, 9, 548 /* Analog */ 549 10, 11, 550 /* AO4S-192 and AI4S-192 extension boards */ 551 12, 13, 14, 15, 552 /* others don't exist */ 553 -1, -1, -1, -1, -1, -1, -1, -1, 554 -1, -1, -1, -1, -1, -1, -1, -1, 555 -1, -1 556 }; 557 558 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size) 559 { 560 dmab->dev.type = SNDRV_DMA_TYPE_DEV; 561 dmab->dev.dev = snd_dma_pci_data(pci); 562 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) { 563 if (dmab->bytes >= size) 564 return 0; 565 } 566 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 567 size, dmab) < 0) 568 return -ENOMEM; 569 return 0; 570 } 571 572 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci) 573 { 574 if (dmab->area) { 575 dmab->dev.dev = NULL; /* make it anonymous */ 576 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci)); 577 } 578 } 579 580 581 static struct pci_device_id snd_hdsp_ids[] = { 582 { 583 .vendor = PCI_VENDOR_ID_XILINX, 584 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 585 .subvendor = PCI_ANY_ID, 586 .subdevice = PCI_ANY_ID, 587 }, /* RME Hammerfall-DSP */ 588 { 0, }, 589 }; 590 591 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); 592 593 /* prototypes */ 594 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp); 595 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp); 596 static int snd_hdsp_enable_io (struct hdsp *hdsp); 597 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp); 598 static void snd_hdsp_initialize_channels (struct hdsp *hdsp); 599 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout); 600 static int hdsp_autosync_ref(struct hdsp *hdsp); 601 static int snd_hdsp_set_defaults(struct hdsp *hdsp); 602 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp); 603 604 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out) 605 { 606 switch (hdsp->io_type) { 607 case Multiface: 608 case Digiface: 609 default: 610 if (hdsp->firmware_rev == 0xa) 611 return (64 * out) + (32 + (in)); 612 else 613 return (52 * out) + (26 + (in)); 614 case H9632: 615 return (32 * out) + (16 + (in)); 616 case H9652: 617 return (52 * out) + (26 + (in)); 618 } 619 } 620 621 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out) 622 { 623 switch (hdsp->io_type) { 624 case Multiface: 625 case Digiface: 626 default: 627 if (hdsp->firmware_rev == 0xa) 628 return (64 * out) + in; 629 else 630 return (52 * out) + in; 631 case H9632: 632 return (32 * out) + in; 633 case H9652: 634 return (52 * out) + in; 635 } 636 } 637 638 static void hdsp_write(struct hdsp *hdsp, int reg, int val) 639 { 640 writel(val, hdsp->iobase + reg); 641 } 642 643 static unsigned int hdsp_read(struct hdsp *hdsp, int reg) 644 { 645 return readl (hdsp->iobase + reg); 646 } 647 648 static int hdsp_check_for_iobox (struct hdsp *hdsp) 649 { 650 651 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; 652 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) { 653 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n"); 654 hdsp->state &= ~HDSP_FirmwareLoaded; 655 return -EIO; 656 } 657 return 0; 658 659 } 660 661 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) { 662 663 int i; 664 unsigned long flags; 665 666 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 667 668 snd_printk ("Hammerfall-DSP: loading firmware\n"); 669 670 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); 671 hdsp_write (hdsp, HDSP_fifoData, 0); 672 673 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 674 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n"); 675 return -EIO; 676 } 677 678 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 679 680 for (i = 0; i < 24413; ++i) { 681 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]); 682 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { 683 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n"); 684 return -EIO; 685 } 686 } 687 688 ssleep(3); 689 690 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 691 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n"); 692 return -EIO; 693 } 694 695 #ifdef SNDRV_BIG_ENDIAN 696 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 697 #else 698 hdsp->control2_register = 0; 699 #endif 700 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 701 snd_printk ("Hammerfall-DSP: finished firmware loading\n"); 702 703 } 704 if (hdsp->state & HDSP_InitializationComplete) { 705 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n"); 706 spin_lock_irqsave(&hdsp->lock, flags); 707 snd_hdsp_set_defaults(hdsp); 708 spin_unlock_irqrestore(&hdsp->lock, flags); 709 } 710 711 hdsp->state |= HDSP_FirmwareLoaded; 712 713 return 0; 714 } 715 716 static int hdsp_get_iobox_version (struct hdsp *hdsp) 717 { 718 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 719 720 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM); 721 hdsp_write (hdsp, HDSP_fifoData, 0); 722 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) 723 return -EIO; 724 725 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 726 hdsp_write (hdsp, HDSP_fifoData, 0); 727 728 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) { 729 hdsp->io_type = Multiface; 730 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT); 731 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 732 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT); 733 } else { 734 hdsp->io_type = Digiface; 735 } 736 } else { 737 /* firmware was already loaded, get iobox type */ 738 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 739 hdsp->io_type = Multiface; 740 else 741 hdsp->io_type = Digiface; 742 } 743 return 0; 744 } 745 746 747 #ifdef HDSP_FW_LOADER 748 static int hdsp_request_fw_loader(struct hdsp *hdsp); 749 #endif 750 751 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand) 752 { 753 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 754 return 0; 755 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 756 hdsp->state &= ~HDSP_FirmwareLoaded; 757 if (! load_on_demand) 758 return -EIO; 759 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n"); 760 /* try to load firmware */ 761 if (! (hdsp->state & HDSP_FirmwareCached)) { 762 #ifdef HDSP_FW_LOADER 763 if (! hdsp_request_fw_loader(hdsp)) 764 return 0; 765 #endif 766 snd_printk(KERN_ERR 767 "Hammerfall-DSP: No firmware loaded nor " 768 "cached, please upload firmware.\n"); 769 return -EIO; 770 } 771 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 772 snd_printk(KERN_ERR 773 "Hammerfall-DSP: Firmware loading from " 774 "cache failed, please upload manually.\n"); 775 return -EIO; 776 } 777 } 778 return 0; 779 } 780 781 782 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout) 783 { 784 int i; 785 786 /* the fifoStatus registers reports on how many words 787 are available in the command FIFO. 788 */ 789 790 for (i = 0; i < timeout; i++) { 791 792 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) 793 return 0; 794 795 /* not very friendly, but we only do this during a firmware 796 load and changing the mixer, so we just put up with it. 797 */ 798 799 udelay (100); 800 } 801 802 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n", 803 count, timeout); 804 return -1; 805 } 806 807 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr) 808 { 809 if (addr >= HDSP_MATRIX_MIXER_SIZE) 810 return 0; 811 812 return hdsp->mixer_matrix[addr]; 813 } 814 815 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data) 816 { 817 unsigned int ad; 818 819 if (addr >= HDSP_MATRIX_MIXER_SIZE) 820 return -1; 821 822 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { 823 824 /* from martin bjornsen: 825 826 "You can only write dwords to the 827 mixer memory which contain two 828 mixer values in the low and high 829 word. So if you want to change 830 value 0 you have to read value 1 831 from the cache and write both to 832 the first dword in the mixer 833 memory." 834 */ 835 836 if (hdsp->io_type == H9632 && addr >= 512) 837 return 0; 838 839 if (hdsp->io_type == H9652 && addr >= 1352) 840 return 0; 841 842 hdsp->mixer_matrix[addr] = data; 843 844 845 /* `addr' addresses a 16-bit wide address, but 846 the address space accessed via hdsp_write 847 uses byte offsets. put another way, addr 848 varies from 0 to 1351, but to access the 849 corresponding memory location, we need 850 to access 0 to 2703 ... 851 */ 852 ad = addr/2; 853 854 hdsp_write (hdsp, 4096 + (ad*4), 855 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 856 hdsp->mixer_matrix[addr&0x7fe]); 857 858 return 0; 859 860 } else { 861 862 ad = (addr << 16) + data; 863 864 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) 865 return -1; 866 867 hdsp_write (hdsp, HDSP_fifoData, ad); 868 hdsp->mixer_matrix[addr] = data; 869 870 } 871 872 return 0; 873 } 874 875 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp) 876 { 877 unsigned long flags; 878 int ret = 1; 879 880 spin_lock_irqsave(&hdsp->lock, flags); 881 if ((hdsp->playback_pid != hdsp->capture_pid) && 882 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) 883 ret = 0; 884 spin_unlock_irqrestore(&hdsp->lock, flags); 885 return ret; 886 } 887 888 static int hdsp_external_sample_rate (struct hdsp *hdsp) 889 { 890 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 891 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; 892 893 switch (rate_bits) { 894 case HDSP_systemFrequency32: return 32000; 895 case HDSP_systemFrequency44_1: return 44100; 896 case HDSP_systemFrequency48: return 48000; 897 case HDSP_systemFrequency64: return 64000; 898 case HDSP_systemFrequency88_2: return 88200; 899 case HDSP_systemFrequency96: return 96000; 900 default: 901 return 0; 902 } 903 } 904 905 static int hdsp_spdif_sample_rate(struct hdsp *hdsp) 906 { 907 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); 908 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); 909 910 if (status & HDSP_SPDIFErrorFlag) 911 return 0; 912 913 switch (rate_bits) { 914 case HDSP_spdifFrequency32KHz: return 32000; 915 case HDSP_spdifFrequency44_1KHz: return 44100; 916 case HDSP_spdifFrequency48KHz: return 48000; 917 case HDSP_spdifFrequency64KHz: return 64000; 918 case HDSP_spdifFrequency88_2KHz: return 88200; 919 case HDSP_spdifFrequency96KHz: return 96000; 920 case HDSP_spdifFrequency128KHz: 921 if (hdsp->io_type == H9632) return 128000; 922 break; 923 case HDSP_spdifFrequency176_4KHz: 924 if (hdsp->io_type == H9632) return 176400; 925 break; 926 case HDSP_spdifFrequency192KHz: 927 if (hdsp->io_type == H9632) return 192000; 928 break; 929 default: 930 break; 931 } 932 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); 933 return 0; 934 } 935 936 static void hdsp_compute_period_size(struct hdsp *hdsp) 937 { 938 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); 939 } 940 941 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp) 942 { 943 int position; 944 945 position = hdsp_read(hdsp, HDSP_statusRegister); 946 947 if (!hdsp->precise_ptr) 948 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; 949 950 position &= HDSP_BufferPositionMask; 951 position /= 4; 952 position &= (hdsp->period_bytes/2) - 1; 953 return position; 954 } 955 956 static void hdsp_reset_hw_pointer(struct hdsp *hdsp) 957 { 958 hdsp_write (hdsp, HDSP_resetPointer, 0); 959 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 960 /* HDSP_resetPointer = HDSP_freqReg, which is strange and 961 * requires (?) to write again DDS value after a reset pointer 962 * (at least, it works like this) */ 963 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value); 964 } 965 966 static void hdsp_start_audio(struct hdsp *s) 967 { 968 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); 969 hdsp_write(s, HDSP_controlRegister, s->control_register); 970 } 971 972 static void hdsp_stop_audio(struct hdsp *s) 973 { 974 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); 975 hdsp_write(s, HDSP_controlRegister, s->control_register); 976 } 977 978 static void hdsp_silence_playback(struct hdsp *hdsp) 979 { 980 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); 981 } 982 983 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames) 984 { 985 int n; 986 987 spin_lock_irq(&s->lock); 988 989 frames >>= 7; 990 n = 0; 991 while (frames) { 992 n++; 993 frames >>= 1; 994 } 995 996 s->control_register &= ~HDSP_LatencyMask; 997 s->control_register |= hdsp_encode_latency(n); 998 999 hdsp_write(s, HDSP_controlRegister, s->control_register); 1000 1001 hdsp_compute_period_size(s); 1002 1003 spin_unlock_irq(&s->lock); 1004 1005 return 0; 1006 } 1007 1008 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) 1009 { 1010 u64 n; 1011 u32 r; 1012 1013 if (rate >= 112000) 1014 rate /= 4; 1015 else if (rate >= 56000) 1016 rate /= 2; 1017 1018 n = DDS_NUMERATOR; 1019 div64_32(&n, rate, &r); 1020 /* n should be less than 2^32 for being written to FREQ register */ 1021 snd_assert((n >> 32) == 0); 1022 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS 1023 value to write it after a reset */ 1024 hdsp->dds_value = n; 1025 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value); 1026 } 1027 1028 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally) 1029 { 1030 int reject_if_open = 0; 1031 int current_rate; 1032 int rate_bits; 1033 1034 /* ASSUMPTION: hdsp->lock is either held, or 1035 there is no need for it (e.g. during module 1036 initialization). 1037 */ 1038 1039 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 1040 if (called_internally) { 1041 /* request from ctl or card initialization */ 1042 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n"); 1043 return -1; 1044 } else { 1045 /* hw_param request while in AutoSync mode */ 1046 int external_freq = hdsp_external_sample_rate(hdsp); 1047 int spdif_freq = hdsp_spdif_sample_rate(hdsp); 1048 1049 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1050 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n"); 1051 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1052 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n"); 1053 else if (rate != external_freq) { 1054 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n"); 1055 return -1; 1056 } 1057 } 1058 } 1059 1060 current_rate = hdsp->system_sample_rate; 1061 1062 /* Changing from a "single speed" to a "double speed" rate is 1063 not allowed if any substreams are open. This is because 1064 such a change causes a shift in the location of 1065 the DMA buffers and a reduction in the number of available 1066 buffers. 1067 1068 Note that a similar but essentially insoluble problem 1069 exists for externally-driven rate changes. All we can do 1070 is to flag rate changes in the read/write routines. */ 1071 1072 if (rate > 96000 && hdsp->io_type != H9632) 1073 return -EINVAL; 1074 1075 switch (rate) { 1076 case 32000: 1077 if (current_rate > 48000) 1078 reject_if_open = 1; 1079 rate_bits = HDSP_Frequency32KHz; 1080 break; 1081 case 44100: 1082 if (current_rate > 48000) 1083 reject_if_open = 1; 1084 rate_bits = HDSP_Frequency44_1KHz; 1085 break; 1086 case 48000: 1087 if (current_rate > 48000) 1088 reject_if_open = 1; 1089 rate_bits = HDSP_Frequency48KHz; 1090 break; 1091 case 64000: 1092 if (current_rate <= 48000 || current_rate > 96000) 1093 reject_if_open = 1; 1094 rate_bits = HDSP_Frequency64KHz; 1095 break; 1096 case 88200: 1097 if (current_rate <= 48000 || current_rate > 96000) 1098 reject_if_open = 1; 1099 rate_bits = HDSP_Frequency88_2KHz; 1100 break; 1101 case 96000: 1102 if (current_rate <= 48000 || current_rate > 96000) 1103 reject_if_open = 1; 1104 rate_bits = HDSP_Frequency96KHz; 1105 break; 1106 case 128000: 1107 if (current_rate < 128000) 1108 reject_if_open = 1; 1109 rate_bits = HDSP_Frequency128KHz; 1110 break; 1111 case 176400: 1112 if (current_rate < 128000) 1113 reject_if_open = 1; 1114 rate_bits = HDSP_Frequency176_4KHz; 1115 break; 1116 case 192000: 1117 if (current_rate < 128000) 1118 reject_if_open = 1; 1119 rate_bits = HDSP_Frequency192KHz; 1120 break; 1121 default: 1122 return -EINVAL; 1123 } 1124 1125 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { 1126 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n", 1127 hdsp->capture_pid, 1128 hdsp->playback_pid); 1129 return -EBUSY; 1130 } 1131 1132 hdsp->control_register &= ~HDSP_FrequencyMask; 1133 hdsp->control_register |= rate_bits; 1134 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1135 1136 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */ 1137 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 1138 hdsp_set_dds_value(hdsp, rate); 1139 1140 if (rate >= 128000) { 1141 hdsp->channel_map = channel_map_H9632_qs; 1142 } else if (rate > 48000) { 1143 if (hdsp->io_type == H9632) 1144 hdsp->channel_map = channel_map_H9632_ds; 1145 else 1146 hdsp->channel_map = channel_map_ds; 1147 } else { 1148 switch (hdsp->io_type) { 1149 case Multiface: 1150 hdsp->channel_map = channel_map_mf_ss; 1151 break; 1152 case Digiface: 1153 case H9652: 1154 hdsp->channel_map = channel_map_df_ss; 1155 break; 1156 case H9632: 1157 hdsp->channel_map = channel_map_H9632_ss; 1158 break; 1159 default: 1160 /* should never happen */ 1161 break; 1162 } 1163 } 1164 1165 hdsp->system_sample_rate = rate; 1166 1167 return 0; 1168 } 1169 1170 /*---------------------------------------------------------------------------- 1171 MIDI 1172 ----------------------------------------------------------------------------*/ 1173 1174 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id) 1175 { 1176 /* the hardware already does the relevant bit-mask with 0xff */ 1177 if (id) 1178 return hdsp_read(hdsp, HDSP_midiDataIn1); 1179 else 1180 return hdsp_read(hdsp, HDSP_midiDataIn0); 1181 } 1182 1183 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) 1184 { 1185 /* the hardware already does the relevant bit-mask with 0xff */ 1186 if (id) 1187 hdsp_write(hdsp, HDSP_midiDataOut1, val); 1188 else 1189 hdsp_write(hdsp, HDSP_midiDataOut0, val); 1190 } 1191 1192 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id) 1193 { 1194 if (id) 1195 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); 1196 else 1197 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); 1198 } 1199 1200 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id) 1201 { 1202 int fifo_bytes_used; 1203 1204 if (id) 1205 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; 1206 else 1207 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; 1208 1209 if (fifo_bytes_used < 128) 1210 return 128 - fifo_bytes_used; 1211 else 1212 return 0; 1213 } 1214 1215 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id) 1216 { 1217 while (snd_hdsp_midi_input_available (hdsp, id)) 1218 snd_hdsp_midi_read_byte (hdsp, id); 1219 } 1220 1221 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi) 1222 { 1223 unsigned long flags; 1224 int n_pending; 1225 int to_write; 1226 int i; 1227 unsigned char buf[128]; 1228 1229 /* Output is not interrupt driven */ 1230 1231 spin_lock_irqsave (&hmidi->lock, flags); 1232 if (hmidi->output) { 1233 if (!snd_rawmidi_transmit_empty (hmidi->output)) { 1234 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) { 1235 if (n_pending > (int)sizeof (buf)) 1236 n_pending = sizeof (buf); 1237 1238 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) { 1239 for (i = 0; i < to_write; ++i) 1240 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); 1241 } 1242 } 1243 } 1244 } 1245 spin_unlock_irqrestore (&hmidi->lock, flags); 1246 return 0; 1247 } 1248 1249 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi) 1250 { 1251 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ 1252 unsigned long flags; 1253 int n_pending; 1254 int i; 1255 1256 spin_lock_irqsave (&hmidi->lock, flags); 1257 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) { 1258 if (hmidi->input) { 1259 if (n_pending > (int)sizeof (buf)) 1260 n_pending = sizeof (buf); 1261 for (i = 0; i < n_pending; ++i) 1262 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1263 if (n_pending) 1264 snd_rawmidi_receive (hmidi->input, buf, n_pending); 1265 } else { 1266 /* flush the MIDI input FIFO */ 1267 while (--n_pending) 1268 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1269 } 1270 } 1271 hmidi->pending = 0; 1272 if (hmidi->id) 1273 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; 1274 else 1275 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; 1276 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); 1277 spin_unlock_irqrestore (&hmidi->lock, flags); 1278 return snd_hdsp_midi_output_write (hmidi); 1279 } 1280 1281 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1282 { 1283 struct hdsp *hdsp; 1284 struct hdsp_midi *hmidi; 1285 unsigned long flags; 1286 u32 ie; 1287 1288 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1289 hdsp = hmidi->hdsp; 1290 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; 1291 spin_lock_irqsave (&hdsp->lock, flags); 1292 if (up) { 1293 if (!(hdsp->control_register & ie)) { 1294 snd_hdsp_flush_midi_input (hdsp, hmidi->id); 1295 hdsp->control_register |= ie; 1296 } 1297 } else { 1298 hdsp->control_register &= ~ie; 1299 tasklet_kill(&hdsp->midi_tasklet); 1300 } 1301 1302 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1303 spin_unlock_irqrestore (&hdsp->lock, flags); 1304 } 1305 1306 static void snd_hdsp_midi_output_timer(unsigned long data) 1307 { 1308 struct hdsp_midi *hmidi = (struct hdsp_midi *) data; 1309 unsigned long flags; 1310 1311 snd_hdsp_midi_output_write(hmidi); 1312 spin_lock_irqsave (&hmidi->lock, flags); 1313 1314 /* this does not bump hmidi->istimer, because the 1315 kernel automatically removed the timer when it 1316 expired, and we are now adding it back, thus 1317 leaving istimer wherever it was set before. 1318 */ 1319 1320 if (hmidi->istimer) { 1321 hmidi->timer.expires = 1 + jiffies; 1322 add_timer(&hmidi->timer); 1323 } 1324 1325 spin_unlock_irqrestore (&hmidi->lock, flags); 1326 } 1327 1328 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1329 { 1330 struct hdsp_midi *hmidi; 1331 unsigned long flags; 1332 1333 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1334 spin_lock_irqsave (&hmidi->lock, flags); 1335 if (up) { 1336 if (!hmidi->istimer) { 1337 init_timer(&hmidi->timer); 1338 hmidi->timer.function = snd_hdsp_midi_output_timer; 1339 hmidi->timer.data = (unsigned long) hmidi; 1340 hmidi->timer.expires = 1 + jiffies; 1341 add_timer(&hmidi->timer); 1342 hmidi->istimer++; 1343 } 1344 } else { 1345 if (hmidi->istimer && --hmidi->istimer <= 0) 1346 del_timer (&hmidi->timer); 1347 } 1348 spin_unlock_irqrestore (&hmidi->lock, flags); 1349 if (up) 1350 snd_hdsp_midi_output_write(hmidi); 1351 } 1352 1353 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream) 1354 { 1355 struct hdsp_midi *hmidi; 1356 1357 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1358 spin_lock_irq (&hmidi->lock); 1359 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); 1360 hmidi->input = substream; 1361 spin_unlock_irq (&hmidi->lock); 1362 1363 return 0; 1364 } 1365 1366 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream) 1367 { 1368 struct hdsp_midi *hmidi; 1369 1370 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1371 spin_lock_irq (&hmidi->lock); 1372 hmidi->output = substream; 1373 spin_unlock_irq (&hmidi->lock); 1374 1375 return 0; 1376 } 1377 1378 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream) 1379 { 1380 struct hdsp_midi *hmidi; 1381 1382 snd_hdsp_midi_input_trigger (substream, 0); 1383 1384 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1385 spin_lock_irq (&hmidi->lock); 1386 hmidi->input = NULL; 1387 spin_unlock_irq (&hmidi->lock); 1388 1389 return 0; 1390 } 1391 1392 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream) 1393 { 1394 struct hdsp_midi *hmidi; 1395 1396 snd_hdsp_midi_output_trigger (substream, 0); 1397 1398 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1399 spin_lock_irq (&hmidi->lock); 1400 hmidi->output = NULL; 1401 spin_unlock_irq (&hmidi->lock); 1402 1403 return 0; 1404 } 1405 1406 static struct snd_rawmidi_ops snd_hdsp_midi_output = 1407 { 1408 .open = snd_hdsp_midi_output_open, 1409 .close = snd_hdsp_midi_output_close, 1410 .trigger = snd_hdsp_midi_output_trigger, 1411 }; 1412 1413 static struct snd_rawmidi_ops snd_hdsp_midi_input = 1414 { 1415 .open = snd_hdsp_midi_input_open, 1416 .close = snd_hdsp_midi_input_close, 1417 .trigger = snd_hdsp_midi_input_trigger, 1418 }; 1419 1420 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id) 1421 { 1422 char buf[32]; 1423 1424 hdsp->midi[id].id = id; 1425 hdsp->midi[id].rmidi = NULL; 1426 hdsp->midi[id].input = NULL; 1427 hdsp->midi[id].output = NULL; 1428 hdsp->midi[id].hdsp = hdsp; 1429 hdsp->midi[id].istimer = 0; 1430 hdsp->midi[id].pending = 0; 1431 spin_lock_init (&hdsp->midi[id].lock); 1432 1433 sprintf (buf, "%s MIDI %d", card->shortname, id+1); 1434 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) 1435 return -1; 1436 1437 sprintf (hdsp->midi[id].rmidi->name, "%s MIDI %d", card->id, id+1); 1438 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; 1439 1440 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); 1441 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); 1442 1443 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | 1444 SNDRV_RAWMIDI_INFO_INPUT | 1445 SNDRV_RAWMIDI_INFO_DUPLEX; 1446 1447 return 0; 1448 } 1449 1450 /*----------------------------------------------------------------------------- 1451 Control Interface 1452 ----------------------------------------------------------------------------*/ 1453 1454 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes) 1455 { 1456 u32 val = 0; 1457 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; 1458 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; 1459 if (val & HDSP_SPDIFProfessional) 1460 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1461 else 1462 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1463 return val; 1464 } 1465 1466 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 1467 { 1468 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | 1469 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); 1470 if (val & HDSP_SPDIFProfessional) 1471 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1472 else 1473 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1474 } 1475 1476 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1477 { 1478 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1479 uinfo->count = 1; 1480 return 0; 1481 } 1482 1483 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1484 { 1485 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1486 1487 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); 1488 return 0; 1489 } 1490 1491 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1492 { 1493 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1494 int change; 1495 u32 val; 1496 1497 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1498 spin_lock_irq(&hdsp->lock); 1499 change = val != hdsp->creg_spdif; 1500 hdsp->creg_spdif = val; 1501 spin_unlock_irq(&hdsp->lock); 1502 return change; 1503 } 1504 1505 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1506 { 1507 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1508 uinfo->count = 1; 1509 return 0; 1510 } 1511 1512 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1513 { 1514 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1515 1516 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); 1517 return 0; 1518 } 1519 1520 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1521 { 1522 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1523 int change; 1524 u32 val; 1525 1526 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1527 spin_lock_irq(&hdsp->lock); 1528 change = val != hdsp->creg_spdif_stream; 1529 hdsp->creg_spdif_stream = val; 1530 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 1531 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); 1532 spin_unlock_irq(&hdsp->lock); 1533 return change; 1534 } 1535 1536 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1537 { 1538 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1539 uinfo->count = 1; 1540 return 0; 1541 } 1542 1543 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1544 { 1545 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1546 return 0; 1547 } 1548 1549 #define HDSP_SPDIF_IN(xname, xindex) \ 1550 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1551 .name = xname, \ 1552 .index = xindex, \ 1553 .info = snd_hdsp_info_spdif_in, \ 1554 .get = snd_hdsp_get_spdif_in, \ 1555 .put = snd_hdsp_put_spdif_in } 1556 1557 static unsigned int hdsp_spdif_in(struct hdsp *hdsp) 1558 { 1559 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); 1560 } 1561 1562 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in) 1563 { 1564 hdsp->control_register &= ~HDSP_SPDIFInputMask; 1565 hdsp->control_register |= hdsp_encode_spdif_in(in); 1566 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1567 return 0; 1568 } 1569 1570 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1571 { 1572 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"}; 1573 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1574 1575 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1576 uinfo->count = 1; 1577 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3); 1578 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2)) 1579 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2); 1580 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1581 return 0; 1582 } 1583 1584 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1585 { 1586 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1587 1588 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); 1589 return 0; 1590 } 1591 1592 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1593 { 1594 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1595 int change; 1596 unsigned int val; 1597 1598 if (!snd_hdsp_use_is_exclusive(hdsp)) 1599 return -EBUSY; 1600 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); 1601 spin_lock_irq(&hdsp->lock); 1602 change = val != hdsp_spdif_in(hdsp); 1603 if (change) 1604 hdsp_set_spdif_input(hdsp, val); 1605 spin_unlock_irq(&hdsp->lock); 1606 return change; 1607 } 1608 1609 #define HDSP_SPDIF_OUT(xname, xindex) \ 1610 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1611 .info = snd_hdsp_info_spdif_bits, \ 1612 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out } 1613 1614 static int hdsp_spdif_out(struct hdsp *hdsp) 1615 { 1616 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0; 1617 } 1618 1619 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out) 1620 { 1621 if (out) 1622 hdsp->control_register |= HDSP_SPDIFOpticalOut; 1623 else 1624 hdsp->control_register &= ~HDSP_SPDIFOpticalOut; 1625 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1626 return 0; 1627 } 1628 1629 #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info 1630 1631 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1632 { 1633 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1634 1635 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp); 1636 return 0; 1637 } 1638 1639 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1640 { 1641 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1642 int change; 1643 unsigned int val; 1644 1645 if (!snd_hdsp_use_is_exclusive(hdsp)) 1646 return -EBUSY; 1647 val = ucontrol->value.integer.value[0] & 1; 1648 spin_lock_irq(&hdsp->lock); 1649 change = (int)val != hdsp_spdif_out(hdsp); 1650 hdsp_set_spdif_output(hdsp, val); 1651 spin_unlock_irq(&hdsp->lock); 1652 return change; 1653 } 1654 1655 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \ 1656 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1657 .info = snd_hdsp_info_spdif_bits, \ 1658 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional } 1659 1660 static int hdsp_spdif_professional(struct hdsp *hdsp) 1661 { 1662 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0; 1663 } 1664 1665 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val) 1666 { 1667 if (val) 1668 hdsp->control_register |= HDSP_SPDIFProfessional; 1669 else 1670 hdsp->control_register &= ~HDSP_SPDIFProfessional; 1671 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1672 return 0; 1673 } 1674 1675 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1676 { 1677 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1678 1679 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp); 1680 return 0; 1681 } 1682 1683 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1684 { 1685 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1686 int change; 1687 unsigned int val; 1688 1689 if (!snd_hdsp_use_is_exclusive(hdsp)) 1690 return -EBUSY; 1691 val = ucontrol->value.integer.value[0] & 1; 1692 spin_lock_irq(&hdsp->lock); 1693 change = (int)val != hdsp_spdif_professional(hdsp); 1694 hdsp_set_spdif_professional(hdsp, val); 1695 spin_unlock_irq(&hdsp->lock); 1696 return change; 1697 } 1698 1699 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \ 1700 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1701 .info = snd_hdsp_info_spdif_bits, \ 1702 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis } 1703 1704 static int hdsp_spdif_emphasis(struct hdsp *hdsp) 1705 { 1706 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0; 1707 } 1708 1709 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val) 1710 { 1711 if (val) 1712 hdsp->control_register |= HDSP_SPDIFEmphasis; 1713 else 1714 hdsp->control_register &= ~HDSP_SPDIFEmphasis; 1715 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1716 return 0; 1717 } 1718 1719 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1720 { 1721 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1722 1723 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp); 1724 return 0; 1725 } 1726 1727 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1728 { 1729 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1730 int change; 1731 unsigned int val; 1732 1733 if (!snd_hdsp_use_is_exclusive(hdsp)) 1734 return -EBUSY; 1735 val = ucontrol->value.integer.value[0] & 1; 1736 spin_lock_irq(&hdsp->lock); 1737 change = (int)val != hdsp_spdif_emphasis(hdsp); 1738 hdsp_set_spdif_emphasis(hdsp, val); 1739 spin_unlock_irq(&hdsp->lock); 1740 return change; 1741 } 1742 1743 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \ 1744 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1745 .info = snd_hdsp_info_spdif_bits, \ 1746 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio } 1747 1748 static int hdsp_spdif_nonaudio(struct hdsp *hdsp) 1749 { 1750 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0; 1751 } 1752 1753 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val) 1754 { 1755 if (val) 1756 hdsp->control_register |= HDSP_SPDIFNonAudio; 1757 else 1758 hdsp->control_register &= ~HDSP_SPDIFNonAudio; 1759 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1760 return 0; 1761 } 1762 1763 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1764 { 1765 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1766 1767 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp); 1768 return 0; 1769 } 1770 1771 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1772 { 1773 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1774 int change; 1775 unsigned int val; 1776 1777 if (!snd_hdsp_use_is_exclusive(hdsp)) 1778 return -EBUSY; 1779 val = ucontrol->value.integer.value[0] & 1; 1780 spin_lock_irq(&hdsp->lock); 1781 change = (int)val != hdsp_spdif_nonaudio(hdsp); 1782 hdsp_set_spdif_nonaudio(hdsp, val); 1783 spin_unlock_irq(&hdsp->lock); 1784 return change; 1785 } 1786 1787 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ 1788 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1789 .name = xname, \ 1790 .index = xindex, \ 1791 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1792 .info = snd_hdsp_info_spdif_sample_rate, \ 1793 .get = snd_hdsp_get_spdif_sample_rate \ 1794 } 1795 1796 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1797 { 1798 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1799 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1800 1801 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1802 uinfo->count = 1; 1803 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7; 1804 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1805 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1806 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1807 return 0; 1808 } 1809 1810 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1811 { 1812 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1813 1814 switch (hdsp_spdif_sample_rate(hdsp)) { 1815 case 32000: 1816 ucontrol->value.enumerated.item[0] = 0; 1817 break; 1818 case 44100: 1819 ucontrol->value.enumerated.item[0] = 1; 1820 break; 1821 case 48000: 1822 ucontrol->value.enumerated.item[0] = 2; 1823 break; 1824 case 64000: 1825 ucontrol->value.enumerated.item[0] = 3; 1826 break; 1827 case 88200: 1828 ucontrol->value.enumerated.item[0] = 4; 1829 break; 1830 case 96000: 1831 ucontrol->value.enumerated.item[0] = 5; 1832 break; 1833 case 128000: 1834 ucontrol->value.enumerated.item[0] = 7; 1835 break; 1836 case 176400: 1837 ucontrol->value.enumerated.item[0] = 8; 1838 break; 1839 case 192000: 1840 ucontrol->value.enumerated.item[0] = 9; 1841 break; 1842 default: 1843 ucontrol->value.enumerated.item[0] = 6; 1844 } 1845 return 0; 1846 } 1847 1848 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1849 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1850 .name = xname, \ 1851 .index = xindex, \ 1852 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1853 .info = snd_hdsp_info_system_sample_rate, \ 1854 .get = snd_hdsp_get_system_sample_rate \ 1855 } 1856 1857 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1858 { 1859 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1860 uinfo->count = 1; 1861 return 0; 1862 } 1863 1864 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1865 { 1866 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1867 1868 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; 1869 return 0; 1870 } 1871 1872 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 1873 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1874 .name = xname, \ 1875 .index = xindex, \ 1876 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1877 .info = snd_hdsp_info_autosync_sample_rate, \ 1878 .get = snd_hdsp_get_autosync_sample_rate \ 1879 } 1880 1881 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1882 { 1883 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1884 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1885 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1886 uinfo->count = 1; 1887 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ; 1888 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1889 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1890 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1891 return 0; 1892 } 1893 1894 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1895 { 1896 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1897 1898 switch (hdsp_external_sample_rate(hdsp)) { 1899 case 32000: 1900 ucontrol->value.enumerated.item[0] = 0; 1901 break; 1902 case 44100: 1903 ucontrol->value.enumerated.item[0] = 1; 1904 break; 1905 case 48000: 1906 ucontrol->value.enumerated.item[0] = 2; 1907 break; 1908 case 64000: 1909 ucontrol->value.enumerated.item[0] = 3; 1910 break; 1911 case 88200: 1912 ucontrol->value.enumerated.item[0] = 4; 1913 break; 1914 case 96000: 1915 ucontrol->value.enumerated.item[0] = 5; 1916 break; 1917 case 128000: 1918 ucontrol->value.enumerated.item[0] = 7; 1919 break; 1920 case 176400: 1921 ucontrol->value.enumerated.item[0] = 8; 1922 break; 1923 case 192000: 1924 ucontrol->value.enumerated.item[0] = 9; 1925 break; 1926 default: 1927 ucontrol->value.enumerated.item[0] = 6; 1928 } 1929 return 0; 1930 } 1931 1932 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ 1933 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1934 .name = xname, \ 1935 .index = xindex, \ 1936 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1937 .info = snd_hdsp_info_system_clock_mode, \ 1938 .get = snd_hdsp_get_system_clock_mode \ 1939 } 1940 1941 static int hdsp_system_clock_mode(struct hdsp *hdsp) 1942 { 1943 if (hdsp->control_register & HDSP_ClockModeMaster) 1944 return 0; 1945 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) 1946 return 0; 1947 return 1; 1948 } 1949 1950 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1951 { 1952 static char *texts[] = {"Master", "Slave" }; 1953 1954 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1955 uinfo->count = 1; 1956 uinfo->value.enumerated.items = 2; 1957 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1958 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1959 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1960 return 0; 1961 } 1962 1963 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1964 { 1965 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1966 1967 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); 1968 return 0; 1969 } 1970 1971 #define HDSP_CLOCK_SOURCE(xname, xindex) \ 1972 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1973 .name = xname, \ 1974 .index = xindex, \ 1975 .info = snd_hdsp_info_clock_source, \ 1976 .get = snd_hdsp_get_clock_source, \ 1977 .put = snd_hdsp_put_clock_source \ 1978 } 1979 1980 static int hdsp_clock_source(struct hdsp *hdsp) 1981 { 1982 if (hdsp->control_register & HDSP_ClockModeMaster) { 1983 switch (hdsp->system_sample_rate) { 1984 case 32000: 1985 return 1; 1986 case 44100: 1987 return 2; 1988 case 48000: 1989 return 3; 1990 case 64000: 1991 return 4; 1992 case 88200: 1993 return 5; 1994 case 96000: 1995 return 6; 1996 case 128000: 1997 return 7; 1998 case 176400: 1999 return 8; 2000 case 192000: 2001 return 9; 2002 default: 2003 return 3; 2004 } 2005 } else { 2006 return 0; 2007 } 2008 } 2009 2010 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode) 2011 { 2012 int rate; 2013 switch (mode) { 2014 case HDSP_CLOCK_SOURCE_AUTOSYNC: 2015 if (hdsp_external_sample_rate(hdsp) != 0) { 2016 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { 2017 hdsp->control_register &= ~HDSP_ClockModeMaster; 2018 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2019 return 0; 2020 } 2021 } 2022 return -1; 2023 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 2024 rate = 32000; 2025 break; 2026 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 2027 rate = 44100; 2028 break; 2029 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 2030 rate = 48000; 2031 break; 2032 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 2033 rate = 64000; 2034 break; 2035 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 2036 rate = 88200; 2037 break; 2038 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 2039 rate = 96000; 2040 break; 2041 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 2042 rate = 128000; 2043 break; 2044 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 2045 rate = 176400; 2046 break; 2047 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 2048 rate = 192000; 2049 break; 2050 default: 2051 rate = 48000; 2052 } 2053 hdsp->control_register |= HDSP_ClockModeMaster; 2054 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2055 hdsp_set_rate(hdsp, rate, 1); 2056 return 0; 2057 } 2058 2059 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2060 { 2061 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" }; 2062 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2063 2064 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2065 uinfo->count = 1; 2066 if (hdsp->io_type == H9632) 2067 uinfo->value.enumerated.items = 10; 2068 else 2069 uinfo->value.enumerated.items = 7; 2070 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2071 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2072 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2073 return 0; 2074 } 2075 2076 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2077 { 2078 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2079 2080 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); 2081 return 0; 2082 } 2083 2084 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2085 { 2086 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2087 int change; 2088 int val; 2089 2090 if (!snd_hdsp_use_is_exclusive(hdsp)) 2091 return -EBUSY; 2092 val = ucontrol->value.enumerated.item[0]; 2093 if (val < 0) val = 0; 2094 if (hdsp->io_type == H9632) { 2095 if (val > 9) 2096 val = 9; 2097 } else { 2098 if (val > 6) 2099 val = 6; 2100 } 2101 spin_lock_irq(&hdsp->lock); 2102 if (val != hdsp_clock_source(hdsp)) 2103 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; 2104 else 2105 change = 0; 2106 spin_unlock_irq(&hdsp->lock); 2107 return change; 2108 } 2109 2110 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info 2111 2112 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2113 { 2114 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2115 2116 ucontrol->value.integer.value[0] = hdsp->clock_source_locked; 2117 return 0; 2118 } 2119 2120 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2121 { 2122 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2123 int change; 2124 2125 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; 2126 if (change) 2127 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0]; 2128 return change; 2129 } 2130 2131 #define HDSP_DA_GAIN(xname, xindex) \ 2132 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2133 .name = xname, \ 2134 .index = xindex, \ 2135 .info = snd_hdsp_info_da_gain, \ 2136 .get = snd_hdsp_get_da_gain, \ 2137 .put = snd_hdsp_put_da_gain \ 2138 } 2139 2140 static int hdsp_da_gain(struct hdsp *hdsp) 2141 { 2142 switch (hdsp->control_register & HDSP_DAGainMask) { 2143 case HDSP_DAGainHighGain: 2144 return 0; 2145 case HDSP_DAGainPlus4dBu: 2146 return 1; 2147 case HDSP_DAGainMinus10dBV: 2148 return 2; 2149 default: 2150 return 1; 2151 } 2152 } 2153 2154 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode) 2155 { 2156 hdsp->control_register &= ~HDSP_DAGainMask; 2157 switch (mode) { 2158 case 0: 2159 hdsp->control_register |= HDSP_DAGainHighGain; 2160 break; 2161 case 1: 2162 hdsp->control_register |= HDSP_DAGainPlus4dBu; 2163 break; 2164 case 2: 2165 hdsp->control_register |= HDSP_DAGainMinus10dBV; 2166 break; 2167 default: 2168 return -1; 2169 2170 } 2171 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2172 return 0; 2173 } 2174 2175 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2176 { 2177 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; 2178 2179 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2180 uinfo->count = 1; 2181 uinfo->value.enumerated.items = 3; 2182 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2183 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2184 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2185 return 0; 2186 } 2187 2188 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2189 { 2190 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2191 2192 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); 2193 return 0; 2194 } 2195 2196 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2197 { 2198 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2199 int change; 2200 int val; 2201 2202 if (!snd_hdsp_use_is_exclusive(hdsp)) 2203 return -EBUSY; 2204 val = ucontrol->value.enumerated.item[0]; 2205 if (val < 0) val = 0; 2206 if (val > 2) val = 2; 2207 spin_lock_irq(&hdsp->lock); 2208 if (val != hdsp_da_gain(hdsp)) 2209 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; 2210 else 2211 change = 0; 2212 spin_unlock_irq(&hdsp->lock); 2213 return change; 2214 } 2215 2216 #define HDSP_AD_GAIN(xname, xindex) \ 2217 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2218 .name = xname, \ 2219 .index = xindex, \ 2220 .info = snd_hdsp_info_ad_gain, \ 2221 .get = snd_hdsp_get_ad_gain, \ 2222 .put = snd_hdsp_put_ad_gain \ 2223 } 2224 2225 static int hdsp_ad_gain(struct hdsp *hdsp) 2226 { 2227 switch (hdsp->control_register & HDSP_ADGainMask) { 2228 case HDSP_ADGainMinus10dBV: 2229 return 0; 2230 case HDSP_ADGainPlus4dBu: 2231 return 1; 2232 case HDSP_ADGainLowGain: 2233 return 2; 2234 default: 2235 return 1; 2236 } 2237 } 2238 2239 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode) 2240 { 2241 hdsp->control_register &= ~HDSP_ADGainMask; 2242 switch (mode) { 2243 case 0: 2244 hdsp->control_register |= HDSP_ADGainMinus10dBV; 2245 break; 2246 case 1: 2247 hdsp->control_register |= HDSP_ADGainPlus4dBu; 2248 break; 2249 case 2: 2250 hdsp->control_register |= HDSP_ADGainLowGain; 2251 break; 2252 default: 2253 return -1; 2254 2255 } 2256 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2257 return 0; 2258 } 2259 2260 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2261 { 2262 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; 2263 2264 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2265 uinfo->count = 1; 2266 uinfo->value.enumerated.items = 3; 2267 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2268 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2269 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2270 return 0; 2271 } 2272 2273 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2274 { 2275 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2276 2277 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); 2278 return 0; 2279 } 2280 2281 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2282 { 2283 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2284 int change; 2285 int val; 2286 2287 if (!snd_hdsp_use_is_exclusive(hdsp)) 2288 return -EBUSY; 2289 val = ucontrol->value.enumerated.item[0]; 2290 if (val < 0) val = 0; 2291 if (val > 2) val = 2; 2292 spin_lock_irq(&hdsp->lock); 2293 if (val != hdsp_ad_gain(hdsp)) 2294 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; 2295 else 2296 change = 0; 2297 spin_unlock_irq(&hdsp->lock); 2298 return change; 2299 } 2300 2301 #define HDSP_PHONE_GAIN(xname, xindex) \ 2302 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2303 .name = xname, \ 2304 .index = xindex, \ 2305 .info = snd_hdsp_info_phone_gain, \ 2306 .get = snd_hdsp_get_phone_gain, \ 2307 .put = snd_hdsp_put_phone_gain \ 2308 } 2309 2310 static int hdsp_phone_gain(struct hdsp *hdsp) 2311 { 2312 switch (hdsp->control_register & HDSP_PhoneGainMask) { 2313 case HDSP_PhoneGain0dB: 2314 return 0; 2315 case HDSP_PhoneGainMinus6dB: 2316 return 1; 2317 case HDSP_PhoneGainMinus12dB: 2318 return 2; 2319 default: 2320 return 0; 2321 } 2322 } 2323 2324 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode) 2325 { 2326 hdsp->control_register &= ~HDSP_PhoneGainMask; 2327 switch (mode) { 2328 case 0: 2329 hdsp->control_register |= HDSP_PhoneGain0dB; 2330 break; 2331 case 1: 2332 hdsp->control_register |= HDSP_PhoneGainMinus6dB; 2333 break; 2334 case 2: 2335 hdsp->control_register |= HDSP_PhoneGainMinus12dB; 2336 break; 2337 default: 2338 return -1; 2339 2340 } 2341 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2342 return 0; 2343 } 2344 2345 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2346 { 2347 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"}; 2348 2349 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2350 uinfo->count = 1; 2351 uinfo->value.enumerated.items = 3; 2352 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2353 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2354 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2355 return 0; 2356 } 2357 2358 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2359 { 2360 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2361 2362 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); 2363 return 0; 2364 } 2365 2366 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2367 { 2368 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2369 int change; 2370 int val; 2371 2372 if (!snd_hdsp_use_is_exclusive(hdsp)) 2373 return -EBUSY; 2374 val = ucontrol->value.enumerated.item[0]; 2375 if (val < 0) val = 0; 2376 if (val > 2) val = 2; 2377 spin_lock_irq(&hdsp->lock); 2378 if (val != hdsp_phone_gain(hdsp)) 2379 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; 2380 else 2381 change = 0; 2382 spin_unlock_irq(&hdsp->lock); 2383 return change; 2384 } 2385 2386 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \ 2387 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2388 .name = xname, \ 2389 .index = xindex, \ 2390 .info = snd_hdsp_info_xlr_breakout_cable, \ 2391 .get = snd_hdsp_get_xlr_breakout_cable, \ 2392 .put = snd_hdsp_put_xlr_breakout_cable \ 2393 } 2394 2395 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp) 2396 { 2397 if (hdsp->control_register & HDSP_XLRBreakoutCable) 2398 return 1; 2399 return 0; 2400 } 2401 2402 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode) 2403 { 2404 if (mode) 2405 hdsp->control_register |= HDSP_XLRBreakoutCable; 2406 else 2407 hdsp->control_register &= ~HDSP_XLRBreakoutCable; 2408 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2409 return 0; 2410 } 2411 2412 #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info 2413 2414 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2415 { 2416 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2417 2418 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp); 2419 return 0; 2420 } 2421 2422 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2423 { 2424 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2425 int change; 2426 int val; 2427 2428 if (!snd_hdsp_use_is_exclusive(hdsp)) 2429 return -EBUSY; 2430 val = ucontrol->value.integer.value[0] & 1; 2431 spin_lock_irq(&hdsp->lock); 2432 change = (int)val != hdsp_xlr_breakout_cable(hdsp); 2433 hdsp_set_xlr_breakout_cable(hdsp, val); 2434 spin_unlock_irq(&hdsp->lock); 2435 return change; 2436 } 2437 2438 /* (De)activates old RME Analog Extension Board 2439 These are connected to the internal ADAT connector 2440 Switching this on desactivates external ADAT 2441 */ 2442 #define HDSP_AEB(xname, xindex) \ 2443 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2444 .name = xname, \ 2445 .index = xindex, \ 2446 .info = snd_hdsp_info_aeb, \ 2447 .get = snd_hdsp_get_aeb, \ 2448 .put = snd_hdsp_put_aeb \ 2449 } 2450 2451 static int hdsp_aeb(struct hdsp *hdsp) 2452 { 2453 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 2454 return 1; 2455 return 0; 2456 } 2457 2458 static int hdsp_set_aeb(struct hdsp *hdsp, int mode) 2459 { 2460 if (mode) 2461 hdsp->control_register |= HDSP_AnalogExtensionBoard; 2462 else 2463 hdsp->control_register &= ~HDSP_AnalogExtensionBoard; 2464 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2465 return 0; 2466 } 2467 2468 #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info 2469 2470 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2471 { 2472 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2473 2474 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp); 2475 return 0; 2476 } 2477 2478 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2479 { 2480 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2481 int change; 2482 int val; 2483 2484 if (!snd_hdsp_use_is_exclusive(hdsp)) 2485 return -EBUSY; 2486 val = ucontrol->value.integer.value[0] & 1; 2487 spin_lock_irq(&hdsp->lock); 2488 change = (int)val != hdsp_aeb(hdsp); 2489 hdsp_set_aeb(hdsp, val); 2490 spin_unlock_irq(&hdsp->lock); 2491 return change; 2492 } 2493 2494 #define HDSP_PREF_SYNC_REF(xname, xindex) \ 2495 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2496 .name = xname, \ 2497 .index = xindex, \ 2498 .info = snd_hdsp_info_pref_sync_ref, \ 2499 .get = snd_hdsp_get_pref_sync_ref, \ 2500 .put = snd_hdsp_put_pref_sync_ref \ 2501 } 2502 2503 static int hdsp_pref_sync_ref(struct hdsp *hdsp) 2504 { 2505 /* Notice that this looks at the requested sync source, 2506 not the one actually in use. 2507 */ 2508 2509 switch (hdsp->control_register & HDSP_SyncRefMask) { 2510 case HDSP_SyncRef_ADAT1: 2511 return HDSP_SYNC_FROM_ADAT1; 2512 case HDSP_SyncRef_ADAT2: 2513 return HDSP_SYNC_FROM_ADAT2; 2514 case HDSP_SyncRef_ADAT3: 2515 return HDSP_SYNC_FROM_ADAT3; 2516 case HDSP_SyncRef_SPDIF: 2517 return HDSP_SYNC_FROM_SPDIF; 2518 case HDSP_SyncRef_WORD: 2519 return HDSP_SYNC_FROM_WORD; 2520 case HDSP_SyncRef_ADAT_SYNC: 2521 return HDSP_SYNC_FROM_ADAT_SYNC; 2522 default: 2523 return HDSP_SYNC_FROM_WORD; 2524 } 2525 return 0; 2526 } 2527 2528 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref) 2529 { 2530 hdsp->control_register &= ~HDSP_SyncRefMask; 2531 switch (pref) { 2532 case HDSP_SYNC_FROM_ADAT1: 2533 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ 2534 break; 2535 case HDSP_SYNC_FROM_ADAT2: 2536 hdsp->control_register |= HDSP_SyncRef_ADAT2; 2537 break; 2538 case HDSP_SYNC_FROM_ADAT3: 2539 hdsp->control_register |= HDSP_SyncRef_ADAT3; 2540 break; 2541 case HDSP_SYNC_FROM_SPDIF: 2542 hdsp->control_register |= HDSP_SyncRef_SPDIF; 2543 break; 2544 case HDSP_SYNC_FROM_WORD: 2545 hdsp->control_register |= HDSP_SyncRef_WORD; 2546 break; 2547 case HDSP_SYNC_FROM_ADAT_SYNC: 2548 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; 2549 break; 2550 default: 2551 return -1; 2552 } 2553 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2554 return 0; 2555 } 2556 2557 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2558 { 2559 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" }; 2560 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2561 2562 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2563 uinfo->count = 1; 2564 2565 switch (hdsp->io_type) { 2566 case Digiface: 2567 case H9652: 2568 uinfo->value.enumerated.items = 6; 2569 break; 2570 case Multiface: 2571 uinfo->value.enumerated.items = 4; 2572 break; 2573 case H9632: 2574 uinfo->value.enumerated.items = 3; 2575 break; 2576 default: 2577 uinfo->value.enumerated.items = 0; 2578 break; 2579 } 2580 2581 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2582 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2583 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2584 return 0; 2585 } 2586 2587 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2588 { 2589 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2590 2591 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); 2592 return 0; 2593 } 2594 2595 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2596 { 2597 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2598 int change, max; 2599 unsigned int val; 2600 2601 if (!snd_hdsp_use_is_exclusive(hdsp)) 2602 return -EBUSY; 2603 2604 switch (hdsp->io_type) { 2605 case Digiface: 2606 case H9652: 2607 max = 6; 2608 break; 2609 case Multiface: 2610 max = 4; 2611 break; 2612 case H9632: 2613 max = 3; 2614 break; 2615 default: 2616 return -EIO; 2617 } 2618 2619 val = ucontrol->value.enumerated.item[0] % max; 2620 spin_lock_irq(&hdsp->lock); 2621 change = (int)val != hdsp_pref_sync_ref(hdsp); 2622 hdsp_set_pref_sync_ref(hdsp, val); 2623 spin_unlock_irq(&hdsp->lock); 2624 return change; 2625 } 2626 2627 #define HDSP_AUTOSYNC_REF(xname, xindex) \ 2628 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2629 .name = xname, \ 2630 .index = xindex, \ 2631 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2632 .info = snd_hdsp_info_autosync_ref, \ 2633 .get = snd_hdsp_get_autosync_ref, \ 2634 } 2635 2636 static int hdsp_autosync_ref(struct hdsp *hdsp) 2637 { 2638 /* This looks at the autosync selected sync reference */ 2639 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 2640 2641 switch (status2 & HDSP_SelSyncRefMask) { 2642 case HDSP_SelSyncRef_WORD: 2643 return HDSP_AUTOSYNC_FROM_WORD; 2644 case HDSP_SelSyncRef_ADAT_SYNC: 2645 return HDSP_AUTOSYNC_FROM_ADAT_SYNC; 2646 case HDSP_SelSyncRef_SPDIF: 2647 return HDSP_AUTOSYNC_FROM_SPDIF; 2648 case HDSP_SelSyncRefMask: 2649 return HDSP_AUTOSYNC_FROM_NONE; 2650 case HDSP_SelSyncRef_ADAT1: 2651 return HDSP_AUTOSYNC_FROM_ADAT1; 2652 case HDSP_SelSyncRef_ADAT2: 2653 return HDSP_AUTOSYNC_FROM_ADAT2; 2654 case HDSP_SelSyncRef_ADAT3: 2655 return HDSP_AUTOSYNC_FROM_ADAT3; 2656 default: 2657 return HDSP_AUTOSYNC_FROM_WORD; 2658 } 2659 return 0; 2660 } 2661 2662 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2663 { 2664 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" }; 2665 2666 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2667 uinfo->count = 1; 2668 uinfo->value.enumerated.items = 7; 2669 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2670 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2671 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2672 return 0; 2673 } 2674 2675 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2676 { 2677 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2678 2679 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); 2680 return 0; 2681 } 2682 2683 #define HDSP_LINE_OUT(xname, xindex) \ 2684 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2685 .name = xname, \ 2686 .index = xindex, \ 2687 .info = snd_hdsp_info_line_out, \ 2688 .get = snd_hdsp_get_line_out, \ 2689 .put = snd_hdsp_put_line_out \ 2690 } 2691 2692 static int hdsp_line_out(struct hdsp *hdsp) 2693 { 2694 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0; 2695 } 2696 2697 static int hdsp_set_line_output(struct hdsp *hdsp, int out) 2698 { 2699 if (out) 2700 hdsp->control_register |= HDSP_LineOut; 2701 else 2702 hdsp->control_register &= ~HDSP_LineOut; 2703 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2704 return 0; 2705 } 2706 2707 #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info 2708 2709 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2710 { 2711 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2712 2713 spin_lock_irq(&hdsp->lock); 2714 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp); 2715 spin_unlock_irq(&hdsp->lock); 2716 return 0; 2717 } 2718 2719 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2720 { 2721 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2722 int change; 2723 unsigned int val; 2724 2725 if (!snd_hdsp_use_is_exclusive(hdsp)) 2726 return -EBUSY; 2727 val = ucontrol->value.integer.value[0] & 1; 2728 spin_lock_irq(&hdsp->lock); 2729 change = (int)val != hdsp_line_out(hdsp); 2730 hdsp_set_line_output(hdsp, val); 2731 spin_unlock_irq(&hdsp->lock); 2732 return change; 2733 } 2734 2735 #define HDSP_PRECISE_POINTER(xname, xindex) \ 2736 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2737 .name = xname, \ 2738 .index = xindex, \ 2739 .info = snd_hdsp_info_precise_pointer, \ 2740 .get = snd_hdsp_get_precise_pointer, \ 2741 .put = snd_hdsp_put_precise_pointer \ 2742 } 2743 2744 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise) 2745 { 2746 if (precise) 2747 hdsp->precise_ptr = 1; 2748 else 2749 hdsp->precise_ptr = 0; 2750 return 0; 2751 } 2752 2753 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info 2754 2755 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2756 { 2757 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2758 2759 spin_lock_irq(&hdsp->lock); 2760 ucontrol->value.integer.value[0] = hdsp->precise_ptr; 2761 spin_unlock_irq(&hdsp->lock); 2762 return 0; 2763 } 2764 2765 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2766 { 2767 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2768 int change; 2769 unsigned int val; 2770 2771 if (!snd_hdsp_use_is_exclusive(hdsp)) 2772 return -EBUSY; 2773 val = ucontrol->value.integer.value[0] & 1; 2774 spin_lock_irq(&hdsp->lock); 2775 change = (int)val != hdsp->precise_ptr; 2776 hdsp_set_precise_pointer(hdsp, val); 2777 spin_unlock_irq(&hdsp->lock); 2778 return change; 2779 } 2780 2781 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \ 2782 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2783 .name = xname, \ 2784 .index = xindex, \ 2785 .info = snd_hdsp_info_use_midi_tasklet, \ 2786 .get = snd_hdsp_get_use_midi_tasklet, \ 2787 .put = snd_hdsp_put_use_midi_tasklet \ 2788 } 2789 2790 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet) 2791 { 2792 if (use_tasklet) 2793 hdsp->use_midi_tasklet = 1; 2794 else 2795 hdsp->use_midi_tasklet = 0; 2796 return 0; 2797 } 2798 2799 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info 2800 2801 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2802 { 2803 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2804 2805 spin_lock_irq(&hdsp->lock); 2806 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet; 2807 spin_unlock_irq(&hdsp->lock); 2808 return 0; 2809 } 2810 2811 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2812 { 2813 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2814 int change; 2815 unsigned int val; 2816 2817 if (!snd_hdsp_use_is_exclusive(hdsp)) 2818 return -EBUSY; 2819 val = ucontrol->value.integer.value[0] & 1; 2820 spin_lock_irq(&hdsp->lock); 2821 change = (int)val != hdsp->use_midi_tasklet; 2822 hdsp_set_use_midi_tasklet(hdsp, val); 2823 spin_unlock_irq(&hdsp->lock); 2824 return change; 2825 } 2826 2827 #define HDSP_MIXER(xname, xindex) \ 2828 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2829 .name = xname, \ 2830 .index = xindex, \ 2831 .device = 0, \ 2832 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2833 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2834 .info = snd_hdsp_info_mixer, \ 2835 .get = snd_hdsp_get_mixer, \ 2836 .put = snd_hdsp_put_mixer \ 2837 } 2838 2839 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2840 { 2841 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2842 uinfo->count = 3; 2843 uinfo->value.integer.min = 0; 2844 uinfo->value.integer.max = 65536; 2845 uinfo->value.integer.step = 1; 2846 return 0; 2847 } 2848 2849 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2850 { 2851 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2852 int source; 2853 int destination; 2854 int addr; 2855 2856 source = ucontrol->value.integer.value[0]; 2857 destination = ucontrol->value.integer.value[1]; 2858 2859 if (source >= hdsp->max_channels) 2860 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); 2861 else 2862 addr = hdsp_input_to_output_key(hdsp,source, destination); 2863 2864 spin_lock_irq(&hdsp->lock); 2865 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); 2866 spin_unlock_irq(&hdsp->lock); 2867 return 0; 2868 } 2869 2870 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2871 { 2872 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2873 int change; 2874 int source; 2875 int destination; 2876 int gain; 2877 int addr; 2878 2879 if (!snd_hdsp_use_is_exclusive(hdsp)) 2880 return -EBUSY; 2881 2882 source = ucontrol->value.integer.value[0]; 2883 destination = ucontrol->value.integer.value[1]; 2884 2885 if (source >= hdsp->max_channels) 2886 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); 2887 else 2888 addr = hdsp_input_to_output_key(hdsp,source, destination); 2889 2890 gain = ucontrol->value.integer.value[2]; 2891 2892 spin_lock_irq(&hdsp->lock); 2893 change = gain != hdsp_read_gain(hdsp, addr); 2894 if (change) 2895 hdsp_write_gain(hdsp, addr, gain); 2896 spin_unlock_irq(&hdsp->lock); 2897 return change; 2898 } 2899 2900 #define HDSP_WC_SYNC_CHECK(xname, xindex) \ 2901 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2902 .name = xname, \ 2903 .index = xindex, \ 2904 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2905 .info = snd_hdsp_info_sync_check, \ 2906 .get = snd_hdsp_get_wc_sync_check \ 2907 } 2908 2909 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2910 { 2911 static char *texts[] = {"No Lock", "Lock", "Sync" }; 2912 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2913 uinfo->count = 1; 2914 uinfo->value.enumerated.items = 3; 2915 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2916 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2917 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2918 return 0; 2919 } 2920 2921 static int hdsp_wc_sync_check(struct hdsp *hdsp) 2922 { 2923 int status2 = hdsp_read(hdsp, HDSP_status2Register); 2924 if (status2 & HDSP_wc_lock) { 2925 if (status2 & HDSP_wc_sync) 2926 return 2; 2927 else 2928 return 1; 2929 } else 2930 return 0; 2931 return 0; 2932 } 2933 2934 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2935 { 2936 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2937 2938 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); 2939 return 0; 2940 } 2941 2942 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ 2943 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2944 .name = xname, \ 2945 .index = xindex, \ 2946 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2947 .info = snd_hdsp_info_sync_check, \ 2948 .get = snd_hdsp_get_spdif_sync_check \ 2949 } 2950 2951 static int hdsp_spdif_sync_check(struct hdsp *hdsp) 2952 { 2953 int status = hdsp_read(hdsp, HDSP_statusRegister); 2954 if (status & HDSP_SPDIFErrorFlag) 2955 return 0; 2956 else { 2957 if (status & HDSP_SPDIFSync) 2958 return 2; 2959 else 2960 return 1; 2961 } 2962 return 0; 2963 } 2964 2965 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2966 { 2967 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2968 2969 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); 2970 return 0; 2971 } 2972 2973 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ 2974 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2975 .name = xname, \ 2976 .index = xindex, \ 2977 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2978 .info = snd_hdsp_info_sync_check, \ 2979 .get = snd_hdsp_get_adatsync_sync_check \ 2980 } 2981 2982 static int hdsp_adatsync_sync_check(struct hdsp *hdsp) 2983 { 2984 int status = hdsp_read(hdsp, HDSP_statusRegister); 2985 if (status & HDSP_TimecodeLock) { 2986 if (status & HDSP_TimecodeSync) 2987 return 2; 2988 else 2989 return 1; 2990 } else 2991 return 0; 2992 } 2993 2994 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2995 { 2996 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2997 2998 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); 2999 return 0; 3000 } 3001 3002 #define HDSP_ADAT_SYNC_CHECK \ 3003 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3004 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3005 .info = snd_hdsp_info_sync_check, \ 3006 .get = snd_hdsp_get_adat_sync_check \ 3007 } 3008 3009 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx) 3010 { 3011 int status = hdsp_read(hdsp, HDSP_statusRegister); 3012 3013 if (status & (HDSP_Lock0>>idx)) { 3014 if (status & (HDSP_Sync0>>idx)) 3015 return 2; 3016 else 3017 return 1; 3018 } else 3019 return 0; 3020 } 3021 3022 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3023 { 3024 int offset; 3025 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3026 3027 offset = ucontrol->id.index - 1; 3028 snd_assert(offset >= 0); 3029 3030 switch (hdsp->io_type) { 3031 case Digiface: 3032 case H9652: 3033 if (offset >= 3) 3034 return -EINVAL; 3035 break; 3036 case Multiface: 3037 case H9632: 3038 if (offset >= 1) 3039 return -EINVAL; 3040 break; 3041 default: 3042 return -EIO; 3043 } 3044 3045 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); 3046 return 0; 3047 } 3048 3049 #define HDSP_DDS_OFFSET(xname, xindex) \ 3050 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3051 .name = xname, \ 3052 .index = xindex, \ 3053 .info = snd_hdsp_info_dds_offset, \ 3054 .get = snd_hdsp_get_dds_offset, \ 3055 .put = snd_hdsp_put_dds_offset \ 3056 } 3057 3058 static int hdsp_dds_offset(struct hdsp *hdsp) 3059 { 3060 u64 n; 3061 u32 r; 3062 unsigned int dds_value = hdsp->dds_value; 3063 int system_sample_rate = hdsp->system_sample_rate; 3064 3065 if (!dds_value) 3066 return 0; 3067 3068 n = DDS_NUMERATOR; 3069 /* 3070 * dds_value = n / rate 3071 * rate = n / dds_value 3072 */ 3073 div64_32(&n, dds_value, &r); 3074 if (system_sample_rate >= 112000) 3075 n *= 4; 3076 else if (system_sample_rate >= 56000) 3077 n *= 2; 3078 return ((int)n) - system_sample_rate; 3079 } 3080 3081 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz) 3082 { 3083 int rate = hdsp->system_sample_rate + offset_hz; 3084 hdsp_set_dds_value(hdsp, rate); 3085 return 0; 3086 } 3087 3088 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3089 { 3090 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3091 uinfo->count = 1; 3092 uinfo->value.integer.min = -5000; 3093 uinfo->value.integer.max = 5000; 3094 return 0; 3095 } 3096 3097 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3098 { 3099 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3100 3101 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp); 3102 return 0; 3103 } 3104 3105 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3106 { 3107 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3108 int change; 3109 int val; 3110 3111 if (!snd_hdsp_use_is_exclusive(hdsp)) 3112 return -EBUSY; 3113 val = ucontrol->value.enumerated.item[0]; 3114 spin_lock_irq(&hdsp->lock); 3115 if (val != hdsp_dds_offset(hdsp)) 3116 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; 3117 else 3118 change = 0; 3119 spin_unlock_irq(&hdsp->lock); 3120 return change; 3121 } 3122 3123 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = { 3124 HDSP_DA_GAIN("DA Gain", 0), 3125 HDSP_AD_GAIN("AD Gain", 0), 3126 HDSP_PHONE_GAIN("Phones Gain", 0), 3127 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0), 3128 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0) 3129 }; 3130 3131 static struct snd_kcontrol_new snd_hdsp_controls[] = { 3132 { 3133 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3134 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 3135 .info = snd_hdsp_control_spdif_info, 3136 .get = snd_hdsp_control_spdif_get, 3137 .put = snd_hdsp_control_spdif_put, 3138 }, 3139 { 3140 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 3141 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3142 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 3143 .info = snd_hdsp_control_spdif_stream_info, 3144 .get = snd_hdsp_control_spdif_stream_get, 3145 .put = snd_hdsp_control_spdif_stream_put, 3146 }, 3147 { 3148 .access = SNDRV_CTL_ELEM_ACCESS_READ, 3149 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3150 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 3151 .info = snd_hdsp_control_spdif_mask_info, 3152 .get = snd_hdsp_control_spdif_mask_get, 3153 .private_value = IEC958_AES0_NONAUDIO | 3154 IEC958_AES0_PROFESSIONAL | 3155 IEC958_AES0_CON_EMPHASIS, 3156 }, 3157 { 3158 .access = SNDRV_CTL_ELEM_ACCESS_READ, 3159 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3160 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 3161 .info = snd_hdsp_control_spdif_mask_info, 3162 .get = snd_hdsp_control_spdif_mask_get, 3163 .private_value = IEC958_AES0_NONAUDIO | 3164 IEC958_AES0_PROFESSIONAL | 3165 IEC958_AES0_PRO_EMPHASIS, 3166 }, 3167 HDSP_MIXER("Mixer", 0), 3168 HDSP_SPDIF_IN("IEC958 Input Connector", 0), 3169 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0), 3170 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0), 3171 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0), 3172 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), 3173 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 3174 HDSP_CLOCK_SOURCE("Sample Clock Source", 0), 3175 { 3176 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3177 .name = "Sample Clock Source Locking", 3178 .info = snd_hdsp_info_clock_source_lock, 3179 .get = snd_hdsp_get_clock_source_lock, 3180 .put = snd_hdsp_put_clock_source_lock, 3181 }, 3182 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 3183 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), 3184 HDSP_AUTOSYNC_REF("AutoSync Reference", 0), 3185 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), 3186 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 3187 /* 'External Rate' complies with the alsa control naming scheme */ 3188 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 3189 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), 3190 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), 3191 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), 3192 HDSP_LINE_OUT("Line Out", 0), 3193 HDSP_PRECISE_POINTER("Precise Pointer", 0), 3194 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0), 3195 }; 3196 3197 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0); 3198 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; 3199 3200 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp) 3201 { 3202 unsigned int idx; 3203 int err; 3204 struct snd_kcontrol *kctl; 3205 3206 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { 3207 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) 3208 return err; 3209 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 3210 hdsp->spdif_ctl = kctl; 3211 } 3212 3213 /* ADAT SyncCheck status */ 3214 snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; 3215 snd_hdsp_adat_sync_check.index = 1; 3216 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) 3217 return err; 3218 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 3219 for (idx = 1; idx < 3; ++idx) { 3220 snd_hdsp_adat_sync_check.index = idx+1; 3221 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) 3222 return err; 3223 } 3224 } 3225 3226 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ 3227 if (hdsp->io_type == H9632) { 3228 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { 3229 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) 3230 return err; 3231 } 3232 } 3233 3234 /* AEB control for H96xx card */ 3235 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { 3236 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) 3237 return err; 3238 } 3239 3240 return 0; 3241 } 3242 3243 /*------------------------------------------------------------ 3244 /proc interface 3245 ------------------------------------------------------------*/ 3246 3247 static void 3248 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 3249 { 3250 struct hdsp *hdsp = (struct hdsp *) entry->private_data; 3251 unsigned int status; 3252 unsigned int status2; 3253 char *pref_sync_ref; 3254 char *autosync_ref; 3255 char *system_clock_mode; 3256 char *clock_source; 3257 int x; 3258 3259 if (hdsp_check_for_iobox (hdsp)) { 3260 snd_iprintf(buffer, "No I/O box connected.\nPlease connect one and upload firmware.\n"); 3261 return; 3262 } 3263 3264 if (hdsp_check_for_firmware(hdsp, 0)) { 3265 if (hdsp->state & HDSP_FirmwareCached) { 3266 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3267 snd_iprintf(buffer, "Firmware loading from cache failed, please upload manually.\n"); 3268 return; 3269 } 3270 } else { 3271 int err = -EINVAL; 3272 #ifdef HDSP_FW_LOADER 3273 err = hdsp_request_fw_loader(hdsp); 3274 #endif 3275 if (err < 0) { 3276 snd_iprintf(buffer, 3277 "No firmware loaded nor cached, " 3278 "please upload firmware.\n"); 3279 return; 3280 } 3281 } 3282 } 3283 3284 status = hdsp_read(hdsp, HDSP_statusRegister); 3285 status2 = hdsp_read(hdsp, HDSP_status2Register); 3286 3287 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, hdsp->card->number + 1); 3288 snd_iprintf(buffer, "Buffers: capture %p playback %p\n", 3289 hdsp->capture_buffer, hdsp->playback_buffer); 3290 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 3291 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); 3292 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); 3293 snd_iprintf(buffer, "Control2 register: 0x%x\n", hdsp->control2_register); 3294 snd_iprintf(buffer, "Status register: 0x%x\n", status); 3295 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); 3296 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); 3297 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); 3298 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); 3299 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); 3300 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); 3301 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off"); 3302 3303 snd_iprintf(buffer, "\n"); 3304 3305 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); 3306 3307 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); 3308 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); 3309 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off"); 3310 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); 3311 3312 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); 3313 3314 snd_iprintf(buffer, "\n"); 3315 3316 3317 switch (hdsp_clock_source(hdsp)) { 3318 case HDSP_CLOCK_SOURCE_AUTOSYNC: 3319 clock_source = "AutoSync"; 3320 break; 3321 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 3322 clock_source = "Internal 32 kHz"; 3323 break; 3324 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 3325 clock_source = "Internal 44.1 kHz"; 3326 break; 3327 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 3328 clock_source = "Internal 48 kHz"; 3329 break; 3330 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 3331 clock_source = "Internal 64 kHz"; 3332 break; 3333 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 3334 clock_source = "Internal 88.2 kHz"; 3335 break; 3336 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 3337 clock_source = "Internal 96 kHz"; 3338 break; 3339 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 3340 clock_source = "Internal 128 kHz"; 3341 break; 3342 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 3343 clock_source = "Internal 176.4 kHz"; 3344 break; 3345 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 3346 clock_source = "Internal 192 kHz"; 3347 break; 3348 default: 3349 clock_source = "Error"; 3350 } 3351 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); 3352 3353 if (hdsp_system_clock_mode(hdsp)) 3354 system_clock_mode = "Slave"; 3355 else 3356 system_clock_mode = "Master"; 3357 3358 switch (hdsp_pref_sync_ref (hdsp)) { 3359 case HDSP_SYNC_FROM_WORD: 3360 pref_sync_ref = "Word Clock"; 3361 break; 3362 case HDSP_SYNC_FROM_ADAT_SYNC: 3363 pref_sync_ref = "ADAT Sync"; 3364 break; 3365 case HDSP_SYNC_FROM_SPDIF: 3366 pref_sync_ref = "SPDIF"; 3367 break; 3368 case HDSP_SYNC_FROM_ADAT1: 3369 pref_sync_ref = "ADAT1"; 3370 break; 3371 case HDSP_SYNC_FROM_ADAT2: 3372 pref_sync_ref = "ADAT2"; 3373 break; 3374 case HDSP_SYNC_FROM_ADAT3: 3375 pref_sync_ref = "ADAT3"; 3376 break; 3377 default: 3378 pref_sync_ref = "Word Clock"; 3379 break; 3380 } 3381 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); 3382 3383 switch (hdsp_autosync_ref (hdsp)) { 3384 case HDSP_AUTOSYNC_FROM_WORD: 3385 autosync_ref = "Word Clock"; 3386 break; 3387 case HDSP_AUTOSYNC_FROM_ADAT_SYNC: 3388 autosync_ref = "ADAT Sync"; 3389 break; 3390 case HDSP_AUTOSYNC_FROM_SPDIF: 3391 autosync_ref = "SPDIF"; 3392 break; 3393 case HDSP_AUTOSYNC_FROM_NONE: 3394 autosync_ref = "None"; 3395 break; 3396 case HDSP_AUTOSYNC_FROM_ADAT1: 3397 autosync_ref = "ADAT1"; 3398 break; 3399 case HDSP_AUTOSYNC_FROM_ADAT2: 3400 autosync_ref = "ADAT2"; 3401 break; 3402 case HDSP_AUTOSYNC_FROM_ADAT3: 3403 autosync_ref = "ADAT3"; 3404 break; 3405 default: 3406 autosync_ref = "---"; 3407 break; 3408 } 3409 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); 3410 3411 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); 3412 3413 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); 3414 3415 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); 3416 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); 3417 3418 snd_iprintf(buffer, "\n"); 3419 3420 switch (hdsp_spdif_in(hdsp)) { 3421 case HDSP_SPDIFIN_OPTICAL: 3422 snd_iprintf(buffer, "IEC958 input: Optical\n"); 3423 break; 3424 case HDSP_SPDIFIN_COAXIAL: 3425 snd_iprintf(buffer, "IEC958 input: Coaxial\n"); 3426 break; 3427 case HDSP_SPDIFIN_INTERNAL: 3428 snd_iprintf(buffer, "IEC958 input: Internal\n"); 3429 break; 3430 case HDSP_SPDIFIN_AES: 3431 snd_iprintf(buffer, "IEC958 input: AES\n"); 3432 break; 3433 default: 3434 snd_iprintf(buffer, "IEC958 input: ???\n"); 3435 break; 3436 } 3437 3438 if (hdsp->control_register & HDSP_SPDIFOpticalOut) 3439 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); 3440 else 3441 snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); 3442 3443 if (hdsp->control_register & HDSP_SPDIFProfessional) 3444 snd_iprintf(buffer, "IEC958 quality: Professional\n"); 3445 else 3446 snd_iprintf(buffer, "IEC958 quality: Consumer\n"); 3447 3448 if (hdsp->control_register & HDSP_SPDIFEmphasis) 3449 snd_iprintf(buffer, "IEC958 emphasis: on\n"); 3450 else 3451 snd_iprintf(buffer, "IEC958 emphasis: off\n"); 3452 3453 if (hdsp->control_register & HDSP_SPDIFNonAudio) 3454 snd_iprintf(buffer, "IEC958 NonAudio: on\n"); 3455 else 3456 snd_iprintf(buffer, "IEC958 NonAudio: off\n"); 3457 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) 3458 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x); 3459 else 3460 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n"); 3461 3462 snd_iprintf(buffer, "\n"); 3463 3464 /* Sync Check */ 3465 x = status & HDSP_Sync0; 3466 if (status & HDSP_Lock0) 3467 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); 3468 else 3469 snd_iprintf(buffer, "ADAT1: No Lock\n"); 3470 3471 switch (hdsp->io_type) { 3472 case Digiface: 3473 case H9652: 3474 x = status & HDSP_Sync1; 3475 if (status & HDSP_Lock1) 3476 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); 3477 else 3478 snd_iprintf(buffer, "ADAT2: No Lock\n"); 3479 x = status & HDSP_Sync2; 3480 if (status & HDSP_Lock2) 3481 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); 3482 else 3483 snd_iprintf(buffer, "ADAT3: No Lock\n"); 3484 break; 3485 default: 3486 /* relax */ 3487 break; 3488 } 3489 3490 x = status & HDSP_SPDIFSync; 3491 if (status & HDSP_SPDIFErrorFlag) 3492 snd_iprintf (buffer, "SPDIF: No Lock\n"); 3493 else 3494 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); 3495 3496 x = status2 & HDSP_wc_sync; 3497 if (status2 & HDSP_wc_lock) 3498 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); 3499 else 3500 snd_iprintf (buffer, "Word Clock: No Lock\n"); 3501 3502 x = status & HDSP_TimecodeSync; 3503 if (status & HDSP_TimecodeLock) 3504 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); 3505 else 3506 snd_iprintf(buffer, "ADAT Sync: No Lock\n"); 3507 3508 snd_iprintf(buffer, "\n"); 3509 3510 /* Informations about H9632 specific controls */ 3511 if (hdsp->io_type == H9632) { 3512 char *tmp; 3513 3514 switch (hdsp_ad_gain(hdsp)) { 3515 case 0: 3516 tmp = "-10 dBV"; 3517 break; 3518 case 1: 3519 tmp = "+4 dBu"; 3520 break; 3521 default: 3522 tmp = "Lo Gain"; 3523 break; 3524 } 3525 snd_iprintf(buffer, "AD Gain : %s\n", tmp); 3526 3527 switch (hdsp_da_gain(hdsp)) { 3528 case 0: 3529 tmp = "Hi Gain"; 3530 break; 3531 case 1: 3532 tmp = "+4 dBu"; 3533 break; 3534 default: 3535 tmp = "-10 dBV"; 3536 break; 3537 } 3538 snd_iprintf(buffer, "DA Gain : %s\n", tmp); 3539 3540 switch (hdsp_phone_gain(hdsp)) { 3541 case 0: 3542 tmp = "0 dB"; 3543 break; 3544 case 1: 3545 tmp = "-6 dB"; 3546 break; 3547 default: 3548 tmp = "-12 dB"; 3549 break; 3550 } 3551 snd_iprintf(buffer, "Phones Gain : %s\n", tmp); 3552 3553 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); 3554 3555 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 3556 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); 3557 else 3558 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); 3559 snd_iprintf(buffer, "\n"); 3560 } 3561 3562 } 3563 3564 static void snd_hdsp_proc_init(struct hdsp *hdsp) 3565 { 3566 struct snd_info_entry *entry; 3567 3568 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) 3569 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read); 3570 } 3571 3572 static void snd_hdsp_free_buffers(struct hdsp *hdsp) 3573 { 3574 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci); 3575 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci); 3576 } 3577 3578 static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp) 3579 { 3580 unsigned long pb_bus, cb_bus; 3581 3582 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 || 3583 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) { 3584 if (hdsp->capture_dma_buf.area) 3585 snd_dma_free_pages(&hdsp->capture_dma_buf); 3586 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name); 3587 return -ENOMEM; 3588 } 3589 3590 /* Align to bus-space 64K boundary */ 3591 3592 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul); 3593 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul); 3594 3595 /* Tell the card where it is */ 3596 3597 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus); 3598 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus); 3599 3600 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr); 3601 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr); 3602 3603 return 0; 3604 } 3605 3606 static int snd_hdsp_set_defaults(struct hdsp *hdsp) 3607 { 3608 unsigned int i; 3609 3610 /* ASSUMPTION: hdsp->lock is either held, or 3611 there is no need to hold it (e.g. during module 3612 initialization). 3613 */ 3614 3615 /* set defaults: 3616 3617 SPDIF Input via Coax 3618 Master clock mode 3619 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, 3620 which implies 2 4096 sample, 32Kbyte periods). 3621 Enable line out. 3622 */ 3623 3624 hdsp->control_register = HDSP_ClockModeMaster | 3625 HDSP_SPDIFInputCoaxial | 3626 hdsp_encode_latency(7) | 3627 HDSP_LineOut; 3628 3629 3630 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3631 3632 #ifdef SNDRV_BIG_ENDIAN 3633 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 3634 #else 3635 hdsp->control2_register = 0; 3636 #endif 3637 if (hdsp->io_type == H9652) 3638 snd_hdsp_9652_enable_mixer (hdsp); 3639 else 3640 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 3641 3642 hdsp_reset_hw_pointer(hdsp); 3643 hdsp_compute_period_size(hdsp); 3644 3645 /* silence everything */ 3646 3647 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) 3648 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; 3649 3650 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { 3651 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) 3652 return -EIO; 3653 } 3654 3655 /* H9632 specific defaults */ 3656 if (hdsp->io_type == H9632) { 3657 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); 3658 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3659 } 3660 3661 /* set a default rate so that the channel map is set up. 3662 */ 3663 3664 hdsp_set_rate(hdsp, 48000, 1); 3665 3666 return 0; 3667 } 3668 3669 static void hdsp_midi_tasklet(unsigned long arg) 3670 { 3671 struct hdsp *hdsp = (struct hdsp *)arg; 3672 3673 if (hdsp->midi[0].pending) 3674 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3675 if (hdsp->midi[1].pending) 3676 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3677 } 3678 3679 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id) 3680 { 3681 struct hdsp *hdsp = (struct hdsp *) dev_id; 3682 unsigned int status; 3683 int audio; 3684 int midi0; 3685 int midi1; 3686 unsigned int midi0status; 3687 unsigned int midi1status; 3688 int schedule = 0; 3689 3690 status = hdsp_read(hdsp, HDSP_statusRegister); 3691 3692 audio = status & HDSP_audioIRQPending; 3693 midi0 = status & HDSP_midi0IRQPending; 3694 midi1 = status & HDSP_midi1IRQPending; 3695 3696 if (!audio && !midi0 && !midi1) 3697 return IRQ_NONE; 3698 3699 hdsp_write(hdsp, HDSP_interruptConfirmation, 0); 3700 3701 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; 3702 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; 3703 3704 if (audio) { 3705 if (hdsp->capture_substream) 3706 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); 3707 3708 if (hdsp->playback_substream) 3709 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); 3710 } 3711 3712 if (midi0 && midi0status) { 3713 if (hdsp->use_midi_tasklet) { 3714 /* we disable interrupts for this input until processing is done */ 3715 hdsp->control_register &= ~HDSP_Midi0InterruptEnable; 3716 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3717 hdsp->midi[0].pending = 1; 3718 schedule = 1; 3719 } else { 3720 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3721 } 3722 } 3723 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) { 3724 if (hdsp->use_midi_tasklet) { 3725 /* we disable interrupts for this input until processing is done */ 3726 hdsp->control_register &= ~HDSP_Midi1InterruptEnable; 3727 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3728 hdsp->midi[1].pending = 1; 3729 schedule = 1; 3730 } else { 3731 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3732 } 3733 } 3734 if (hdsp->use_midi_tasklet && schedule) 3735 tasklet_hi_schedule(&hdsp->midi_tasklet); 3736 return IRQ_HANDLED; 3737 } 3738 3739 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream) 3740 { 3741 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3742 return hdsp_hw_pointer(hdsp); 3743 } 3744 3745 static char *hdsp_channel_buffer_location(struct hdsp *hdsp, 3746 int stream, 3747 int channel) 3748 3749 { 3750 int mapped_channel; 3751 3752 snd_assert(channel >= 0 && channel < hdsp->max_channels, return NULL); 3753 3754 if ((mapped_channel = hdsp->channel_map[channel]) < 0) 3755 return NULL; 3756 3757 if (stream == SNDRV_PCM_STREAM_CAPTURE) 3758 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3759 else 3760 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3761 } 3762 3763 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel, 3764 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count) 3765 { 3766 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3767 char *channel_buf; 3768 3769 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); 3770 3771 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3772 snd_assert(channel_buf != NULL, return -EIO); 3773 if (copy_from_user(channel_buf + pos * 4, src, count * 4)) 3774 return -EFAULT; 3775 return count; 3776 } 3777 3778 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel, 3779 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count) 3780 { 3781 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3782 char *channel_buf; 3783 3784 snd_assert(pos + count <= HDSP_CHANNEL_BUFFER_BYTES / 4, return -EINVAL); 3785 3786 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3787 snd_assert(channel_buf != NULL, return -EIO); 3788 if (copy_to_user(dst, channel_buf + pos * 4, count * 4)) 3789 return -EFAULT; 3790 return count; 3791 } 3792 3793 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel, 3794 snd_pcm_uframes_t pos, snd_pcm_uframes_t count) 3795 { 3796 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3797 char *channel_buf; 3798 3799 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3800 snd_assert(channel_buf != NULL, return -EIO); 3801 memset(channel_buf + pos * 4, 0, count * 4); 3802 return count; 3803 } 3804 3805 static int snd_hdsp_reset(struct snd_pcm_substream *substream) 3806 { 3807 struct snd_pcm_runtime *runtime = substream->runtime; 3808 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3809 struct snd_pcm_substream *other; 3810 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 3811 other = hdsp->capture_substream; 3812 else 3813 other = hdsp->playback_substream; 3814 if (hdsp->running) 3815 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); 3816 else 3817 runtime->status->hw_ptr = 0; 3818 if (other) { 3819 struct snd_pcm_substream *s; 3820 struct snd_pcm_runtime *oruntime = other->runtime; 3821 snd_pcm_group_for_each_entry(s, substream) { 3822 if (s == other) { 3823 oruntime->status->hw_ptr = runtime->status->hw_ptr; 3824 break; 3825 } 3826 } 3827 } 3828 return 0; 3829 } 3830 3831 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream, 3832 struct snd_pcm_hw_params *params) 3833 { 3834 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3835 int err; 3836 pid_t this_pid; 3837 pid_t other_pid; 3838 3839 if (hdsp_check_for_iobox (hdsp)) 3840 return -EIO; 3841 3842 if (hdsp_check_for_firmware(hdsp, 1)) 3843 return -EIO; 3844 3845 spin_lock_irq(&hdsp->lock); 3846 3847 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3848 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 3849 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); 3850 this_pid = hdsp->playback_pid; 3851 other_pid = hdsp->capture_pid; 3852 } else { 3853 this_pid = hdsp->capture_pid; 3854 other_pid = hdsp->playback_pid; 3855 } 3856 3857 if ((other_pid > 0) && (this_pid != other_pid)) { 3858 3859 /* The other stream is open, and not by the same 3860 task as this one. Make sure that the parameters 3861 that matter are the same. 3862 */ 3863 3864 if (params_rate(params) != hdsp->system_sample_rate) { 3865 spin_unlock_irq(&hdsp->lock); 3866 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3867 return -EBUSY; 3868 } 3869 3870 if (params_period_size(params) != hdsp->period_bytes / 4) { 3871 spin_unlock_irq(&hdsp->lock); 3872 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 3873 return -EBUSY; 3874 } 3875 3876 /* We're fine. */ 3877 3878 spin_unlock_irq(&hdsp->lock); 3879 return 0; 3880 3881 } else { 3882 spin_unlock_irq(&hdsp->lock); 3883 } 3884 3885 /* how to make sure that the rate matches an externally-set one ? 3886 */ 3887 3888 spin_lock_irq(&hdsp->lock); 3889 if (! hdsp->clock_source_locked) { 3890 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { 3891 spin_unlock_irq(&hdsp->lock); 3892 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3893 return err; 3894 } 3895 } 3896 spin_unlock_irq(&hdsp->lock); 3897 3898 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) { 3899 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 3900 return err; 3901 } 3902 3903 return 0; 3904 } 3905 3906 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream, 3907 struct snd_pcm_channel_info *info) 3908 { 3909 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3910 int mapped_channel; 3911 3912 snd_assert(info->channel < hdsp->max_channels, return -EINVAL); 3913 3914 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) 3915 return -EINVAL; 3916 3917 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES; 3918 info->first = 0; 3919 info->step = 32; 3920 return 0; 3921 } 3922 3923 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream, 3924 unsigned int cmd, void *arg) 3925 { 3926 switch (cmd) { 3927 case SNDRV_PCM_IOCTL1_RESET: 3928 return snd_hdsp_reset(substream); 3929 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 3930 return snd_hdsp_channel_info(substream, arg); 3931 default: 3932 break; 3933 } 3934 3935 return snd_pcm_lib_ioctl(substream, cmd, arg); 3936 } 3937 3938 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd) 3939 { 3940 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3941 struct snd_pcm_substream *other; 3942 int running; 3943 3944 if (hdsp_check_for_iobox (hdsp)) 3945 return -EIO; 3946 3947 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */ 3948 return -EIO; 3949 3950 spin_lock(&hdsp->lock); 3951 running = hdsp->running; 3952 switch (cmd) { 3953 case SNDRV_PCM_TRIGGER_START: 3954 running |= 1 << substream->stream; 3955 break; 3956 case SNDRV_PCM_TRIGGER_STOP: 3957 running &= ~(1 << substream->stream); 3958 break; 3959 default: 3960 snd_BUG(); 3961 spin_unlock(&hdsp->lock); 3962 return -EINVAL; 3963 } 3964 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 3965 other = hdsp->capture_substream; 3966 else 3967 other = hdsp->playback_substream; 3968 3969 if (other) { 3970 struct snd_pcm_substream *s; 3971 snd_pcm_group_for_each_entry(s, substream) { 3972 if (s == other) { 3973 snd_pcm_trigger_done(s, substream); 3974 if (cmd == SNDRV_PCM_TRIGGER_START) 3975 running |= 1 << s->stream; 3976 else 3977 running &= ~(1 << s->stream); 3978 goto _ok; 3979 } 3980 } 3981 if (cmd == SNDRV_PCM_TRIGGER_START) { 3982 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && 3983 substream->stream == SNDRV_PCM_STREAM_CAPTURE) 3984 hdsp_silence_playback(hdsp); 3985 } else { 3986 if (running && 3987 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 3988 hdsp_silence_playback(hdsp); 3989 } 3990 } else { 3991 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 3992 hdsp_silence_playback(hdsp); 3993 } 3994 _ok: 3995 snd_pcm_trigger_done(substream, substream); 3996 if (!hdsp->running && running) 3997 hdsp_start_audio(hdsp); 3998 else if (hdsp->running && !running) 3999 hdsp_stop_audio(hdsp); 4000 hdsp->running = running; 4001 spin_unlock(&hdsp->lock); 4002 4003 return 0; 4004 } 4005 4006 static int snd_hdsp_prepare(struct snd_pcm_substream *substream) 4007 { 4008 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4009 int result = 0; 4010 4011 if (hdsp_check_for_iobox (hdsp)) 4012 return -EIO; 4013 4014 if (hdsp_check_for_firmware(hdsp, 1)) 4015 return -EIO; 4016 4017 spin_lock_irq(&hdsp->lock); 4018 if (!hdsp->running) 4019 hdsp_reset_hw_pointer(hdsp); 4020 spin_unlock_irq(&hdsp->lock); 4021 return result; 4022 } 4023 4024 static struct snd_pcm_hardware snd_hdsp_playback_subinfo = 4025 { 4026 .info = (SNDRV_PCM_INFO_MMAP | 4027 SNDRV_PCM_INFO_MMAP_VALID | 4028 SNDRV_PCM_INFO_NONINTERLEAVED | 4029 SNDRV_PCM_INFO_SYNC_START | 4030 SNDRV_PCM_INFO_DOUBLE), 4031 #ifdef SNDRV_BIG_ENDIAN 4032 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4033 #else 4034 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4035 #endif 4036 .rates = (SNDRV_PCM_RATE_32000 | 4037 SNDRV_PCM_RATE_44100 | 4038 SNDRV_PCM_RATE_48000 | 4039 SNDRV_PCM_RATE_64000 | 4040 SNDRV_PCM_RATE_88200 | 4041 SNDRV_PCM_RATE_96000), 4042 .rate_min = 32000, 4043 .rate_max = 96000, 4044 .channels_min = 14, 4045 .channels_max = HDSP_MAX_CHANNELS, 4046 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4047 .period_bytes_min = (64 * 4) * 10, 4048 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4049 .periods_min = 2, 4050 .periods_max = 2, 4051 .fifo_size = 0 4052 }; 4053 4054 static struct snd_pcm_hardware snd_hdsp_capture_subinfo = 4055 { 4056 .info = (SNDRV_PCM_INFO_MMAP | 4057 SNDRV_PCM_INFO_MMAP_VALID | 4058 SNDRV_PCM_INFO_NONINTERLEAVED | 4059 SNDRV_PCM_INFO_SYNC_START), 4060 #ifdef SNDRV_BIG_ENDIAN 4061 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4062 #else 4063 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4064 #endif 4065 .rates = (SNDRV_PCM_RATE_32000 | 4066 SNDRV_PCM_RATE_44100 | 4067 SNDRV_PCM_RATE_48000 | 4068 SNDRV_PCM_RATE_64000 | 4069 SNDRV_PCM_RATE_88200 | 4070 SNDRV_PCM_RATE_96000), 4071 .rate_min = 32000, 4072 .rate_max = 96000, 4073 .channels_min = 14, 4074 .channels_max = HDSP_MAX_CHANNELS, 4075 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4076 .period_bytes_min = (64 * 4) * 10, 4077 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4078 .periods_min = 2, 4079 .periods_max = 2, 4080 .fifo_size = 0 4081 }; 4082 4083 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; 4084 4085 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = { 4086 .count = ARRAY_SIZE(hdsp_period_sizes), 4087 .list = hdsp_period_sizes, 4088 .mask = 0 4089 }; 4090 4091 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; 4092 4093 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = { 4094 .count = ARRAY_SIZE(hdsp_9632_sample_rates), 4095 .list = hdsp_9632_sample_rates, 4096 .mask = 0 4097 }; 4098 4099 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params, 4100 struct snd_pcm_hw_rule *rule) 4101 { 4102 struct hdsp *hdsp = rule->private; 4103 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4104 if (hdsp->io_type == H9632) { 4105 unsigned int list[3]; 4106 list[0] = hdsp->qs_in_channels; 4107 list[1] = hdsp->ds_in_channels; 4108 list[2] = hdsp->ss_in_channels; 4109 return snd_interval_list(c, 3, list, 0); 4110 } else { 4111 unsigned int list[2]; 4112 list[0] = hdsp->ds_in_channels; 4113 list[1] = hdsp->ss_in_channels; 4114 return snd_interval_list(c, 2, list, 0); 4115 } 4116 } 4117 4118 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params, 4119 struct snd_pcm_hw_rule *rule) 4120 { 4121 unsigned int list[3]; 4122 struct hdsp *hdsp = rule->private; 4123 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4124 if (hdsp->io_type == H9632) { 4125 list[0] = hdsp->qs_out_channels; 4126 list[1] = hdsp->ds_out_channels; 4127 list[2] = hdsp->ss_out_channels; 4128 return snd_interval_list(c, 3, list, 0); 4129 } else { 4130 list[0] = hdsp->ds_out_channels; 4131 list[1] = hdsp->ss_out_channels; 4132 } 4133 return snd_interval_list(c, 2, list, 0); 4134 } 4135 4136 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 4137 struct snd_pcm_hw_rule *rule) 4138 { 4139 struct hdsp *hdsp = rule->private; 4140 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4141 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4142 if (r->min > 96000 && hdsp->io_type == H9632) { 4143 struct snd_interval t = { 4144 .min = hdsp->qs_in_channels, 4145 .max = hdsp->qs_in_channels, 4146 .integer = 1, 4147 }; 4148 return snd_interval_refine(c, &t); 4149 } else if (r->min > 48000 && r->max <= 96000) { 4150 struct snd_interval t = { 4151 .min = hdsp->ds_in_channels, 4152 .max = hdsp->ds_in_channels, 4153 .integer = 1, 4154 }; 4155 return snd_interval_refine(c, &t); 4156 } else if (r->max < 64000) { 4157 struct snd_interval t = { 4158 .min = hdsp->ss_in_channels, 4159 .max = hdsp->ss_in_channels, 4160 .integer = 1, 4161 }; 4162 return snd_interval_refine(c, &t); 4163 } 4164 return 0; 4165 } 4166 4167 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 4168 struct snd_pcm_hw_rule *rule) 4169 { 4170 struct hdsp *hdsp = rule->private; 4171 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4172 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4173 if (r->min > 96000 && hdsp->io_type == H9632) { 4174 struct snd_interval t = { 4175 .min = hdsp->qs_out_channels, 4176 .max = hdsp->qs_out_channels, 4177 .integer = 1, 4178 }; 4179 return snd_interval_refine(c, &t); 4180 } else if (r->min > 48000 && r->max <= 96000) { 4181 struct snd_interval t = { 4182 .min = hdsp->ds_out_channels, 4183 .max = hdsp->ds_out_channels, 4184 .integer = 1, 4185 }; 4186 return snd_interval_refine(c, &t); 4187 } else if (r->max < 64000) { 4188 struct snd_interval t = { 4189 .min = hdsp->ss_out_channels, 4190 .max = hdsp->ss_out_channels, 4191 .integer = 1, 4192 }; 4193 return snd_interval_refine(c, &t); 4194 } 4195 return 0; 4196 } 4197 4198 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 4199 struct snd_pcm_hw_rule *rule) 4200 { 4201 struct hdsp *hdsp = rule->private; 4202 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4203 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4204 if (c->min >= hdsp->ss_out_channels) { 4205 struct snd_interval t = { 4206 .min = 32000, 4207 .max = 48000, 4208 .integer = 1, 4209 }; 4210 return snd_interval_refine(r, &t); 4211 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { 4212 struct snd_interval t = { 4213 .min = 128000, 4214 .max = 192000, 4215 .integer = 1, 4216 }; 4217 return snd_interval_refine(r, &t); 4218 } else if (c->max <= hdsp->ds_out_channels) { 4219 struct snd_interval t = { 4220 .min = 64000, 4221 .max = 96000, 4222 .integer = 1, 4223 }; 4224 return snd_interval_refine(r, &t); 4225 } 4226 return 0; 4227 } 4228 4229 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 4230 struct snd_pcm_hw_rule *rule) 4231 { 4232 struct hdsp *hdsp = rule->private; 4233 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4234 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4235 if (c->min >= hdsp->ss_in_channels) { 4236 struct snd_interval t = { 4237 .min = 32000, 4238 .max = 48000, 4239 .integer = 1, 4240 }; 4241 return snd_interval_refine(r, &t); 4242 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { 4243 struct snd_interval t = { 4244 .min = 128000, 4245 .max = 192000, 4246 .integer = 1, 4247 }; 4248 return snd_interval_refine(r, &t); 4249 } else if (c->max <= hdsp->ds_in_channels) { 4250 struct snd_interval t = { 4251 .min = 64000, 4252 .max = 96000, 4253 .integer = 1, 4254 }; 4255 return snd_interval_refine(r, &t); 4256 } 4257 return 0; 4258 } 4259 4260 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream) 4261 { 4262 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4263 struct snd_pcm_runtime *runtime = substream->runtime; 4264 4265 if (hdsp_check_for_iobox (hdsp)) 4266 return -EIO; 4267 4268 if (hdsp_check_for_firmware(hdsp, 1)) 4269 return -EIO; 4270 4271 spin_lock_irq(&hdsp->lock); 4272 4273 snd_pcm_set_sync(substream); 4274 4275 runtime->hw = snd_hdsp_playback_subinfo; 4276 runtime->dma_area = hdsp->playback_buffer; 4277 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4278 4279 hdsp->playback_pid = current->pid; 4280 hdsp->playback_substream = substream; 4281 4282 spin_unlock_irq(&hdsp->lock); 4283 4284 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4285 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4286 if (hdsp->clock_source_locked) { 4287 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; 4288 } else if (hdsp->io_type == H9632) { 4289 runtime->hw.rate_max = 192000; 4290 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4291 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4292 } 4293 if (hdsp->io_type == H9632) { 4294 runtime->hw.channels_min = hdsp->qs_out_channels; 4295 runtime->hw.channels_max = hdsp->ss_out_channels; 4296 } 4297 4298 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4299 snd_hdsp_hw_rule_out_channels, hdsp, 4300 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4301 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4302 snd_hdsp_hw_rule_out_channels_rate, hdsp, 4303 SNDRV_PCM_HW_PARAM_RATE, -1); 4304 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4305 snd_hdsp_hw_rule_rate_out_channels, hdsp, 4306 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4307 4308 hdsp->creg_spdif_stream = hdsp->creg_spdif; 4309 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4310 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4311 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4312 return 0; 4313 } 4314 4315 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream) 4316 { 4317 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4318 4319 spin_lock_irq(&hdsp->lock); 4320 4321 hdsp->playback_pid = -1; 4322 hdsp->playback_substream = NULL; 4323 4324 spin_unlock_irq(&hdsp->lock); 4325 4326 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4327 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4328 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4329 return 0; 4330 } 4331 4332 4333 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream) 4334 { 4335 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4336 struct snd_pcm_runtime *runtime = substream->runtime; 4337 4338 if (hdsp_check_for_iobox (hdsp)) 4339 return -EIO; 4340 4341 if (hdsp_check_for_firmware(hdsp, 1)) 4342 return -EIO; 4343 4344 spin_lock_irq(&hdsp->lock); 4345 4346 snd_pcm_set_sync(substream); 4347 4348 runtime->hw = snd_hdsp_capture_subinfo; 4349 runtime->dma_area = hdsp->capture_buffer; 4350 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4351 4352 hdsp->capture_pid = current->pid; 4353 hdsp->capture_substream = substream; 4354 4355 spin_unlock_irq(&hdsp->lock); 4356 4357 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4358 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4359 if (hdsp->io_type == H9632) { 4360 runtime->hw.channels_min = hdsp->qs_in_channels; 4361 runtime->hw.channels_max = hdsp->ss_in_channels; 4362 runtime->hw.rate_max = 192000; 4363 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4364 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4365 } 4366 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4367 snd_hdsp_hw_rule_in_channels, hdsp, 4368 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4369 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4370 snd_hdsp_hw_rule_in_channels_rate, hdsp, 4371 SNDRV_PCM_HW_PARAM_RATE, -1); 4372 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4373 snd_hdsp_hw_rule_rate_in_channels, hdsp, 4374 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4375 return 0; 4376 } 4377 4378 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) 4379 { 4380 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4381 4382 spin_lock_irq(&hdsp->lock); 4383 4384 hdsp->capture_pid = -1; 4385 hdsp->capture_substream = NULL; 4386 4387 spin_unlock_irq(&hdsp->lock); 4388 return 0; 4389 } 4390 4391 static int snd_hdsp_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file) 4392 { 4393 /* we have nothing to initialize but the call is required */ 4394 return 0; 4395 } 4396 4397 4398 /* helper functions for copying meter values */ 4399 static inline int copy_u32_le(void __user *dest, void __iomem *src) 4400 { 4401 u32 val = readl(src); 4402 return copy_to_user(dest, &val, 4); 4403 } 4404 4405 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4406 { 4407 u32 rms_low, rms_high; 4408 u64 rms; 4409 rms_low = readl(src_low); 4410 rms_high = readl(src_high); 4411 rms = ((u64)rms_high << 32) | rms_low; 4412 return copy_to_user(dest, &rms, 8); 4413 } 4414 4415 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4416 { 4417 u32 rms_low, rms_high; 4418 u64 rms; 4419 rms_low = readl(src_low) & 0xffffff00; 4420 rms_high = readl(src_high) & 0xffffff00; 4421 rms = ((u64)rms_high << 32) | rms_low; 4422 return copy_to_user(dest, &rms, 8); 4423 } 4424 4425 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4426 { 4427 int doublespeed = 0; 4428 int i, j, channels, ofs; 4429 4430 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4431 doublespeed = 1; 4432 channels = doublespeed ? 14 : 26; 4433 for (i = 0, j = 0; i < 26; ++i) { 4434 if (doublespeed && (i & 4)) 4435 continue; 4436 ofs = HDSP_9652_peakBase - j * 4; 4437 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) 4438 return -EFAULT; 4439 ofs -= channels * 4; 4440 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) 4441 return -EFAULT; 4442 ofs -= channels * 4; 4443 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) 4444 return -EFAULT; 4445 ofs = HDSP_9652_rmsBase + j * 8; 4446 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, 4447 hdsp->iobase + ofs + 4)) 4448 return -EFAULT; 4449 ofs += channels * 8; 4450 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, 4451 hdsp->iobase + ofs + 4)) 4452 return -EFAULT; 4453 ofs += channels * 8; 4454 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, 4455 hdsp->iobase + ofs + 4)) 4456 return -EFAULT; 4457 j++; 4458 } 4459 return 0; 4460 } 4461 4462 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4463 { 4464 int i, j; 4465 struct hdsp_9632_meters __iomem *m; 4466 int doublespeed = 0; 4467 4468 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4469 doublespeed = 1; 4470 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase); 4471 for (i = 0, j = 0; i < 16; ++i, ++j) { 4472 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) 4473 return -EFAULT; 4474 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) 4475 return -EFAULT; 4476 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) 4477 return -EFAULT; 4478 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], 4479 &m->input_rms_high[j])) 4480 return -EFAULT; 4481 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], 4482 &m->playback_rms_high[j])) 4483 return -EFAULT; 4484 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], 4485 &m->output_rms_high[j])) 4486 return -EFAULT; 4487 if (doublespeed && i == 3) i += 4; 4488 } 4489 return 0; 4490 } 4491 4492 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4493 { 4494 int i; 4495 4496 for (i = 0; i < 26; i++) { 4497 if (copy_u32_le(&peak_rms->playback_peaks[i], 4498 hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) 4499 return -EFAULT; 4500 if (copy_u32_le(&peak_rms->input_peaks[i], 4501 hdsp->iobase + HDSP_inputPeakLevel + i * 4)) 4502 return -EFAULT; 4503 } 4504 for (i = 0; i < 28; i++) { 4505 if (copy_u32_le(&peak_rms->output_peaks[i], 4506 hdsp->iobase + HDSP_outputPeakLevel + i * 4)) 4507 return -EFAULT; 4508 } 4509 for (i = 0; i < 26; ++i) { 4510 if (copy_u64_le(&peak_rms->playback_rms[i], 4511 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, 4512 hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) 4513 return -EFAULT; 4514 if (copy_u64_le(&peak_rms->input_rms[i], 4515 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, 4516 hdsp->iobase + HDSP_inputRmsLevel + i * 8)) 4517 return -EFAULT; 4518 } 4519 return 0; 4520 } 4521 4522 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) 4523 { 4524 struct hdsp *hdsp = (struct hdsp *)hw->private_data; 4525 void __user *argp = (void __user *)arg; 4526 4527 switch (cmd) { 4528 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { 4529 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; 4530 4531 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 4532 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n"); 4533 return -EINVAL; 4534 } 4535 4536 switch (hdsp->io_type) { 4537 case H9652: 4538 return hdsp_9652_get_peak(hdsp, peak_rms); 4539 case H9632: 4540 return hdsp_9632_get_peak(hdsp, peak_rms); 4541 default: 4542 return hdsp_get_peak(hdsp, peak_rms); 4543 } 4544 } 4545 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { 4546 struct hdsp_config_info info; 4547 unsigned long flags; 4548 int i; 4549 4550 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 4551 snd_printk(KERN_ERR "Hammerfall-DSP: Firmware needs to be uploaded to the card.\n"); 4552 return -EINVAL; 4553 } 4554 spin_lock_irqsave(&hdsp->lock, flags); 4555 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); 4556 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); 4557 if (hdsp->io_type != H9632) 4558 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 4559 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); 4560 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) 4561 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); 4562 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); 4563 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp); 4564 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp); 4565 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp); 4566 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp); 4567 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); 4568 info.system_sample_rate = hdsp->system_sample_rate; 4569 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); 4570 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); 4571 info.clock_source = (unsigned char)hdsp_clock_source(hdsp); 4572 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); 4573 info.line_out = (unsigned char)hdsp_line_out(hdsp); 4574 if (hdsp->io_type == H9632) { 4575 info.da_gain = (unsigned char)hdsp_da_gain(hdsp); 4576 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); 4577 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); 4578 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp); 4579 4580 } 4581 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) 4582 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp); 4583 spin_unlock_irqrestore(&hdsp->lock, flags); 4584 if (copy_to_user(argp, &info, sizeof(info))) 4585 return -EFAULT; 4586 break; 4587 } 4588 case SNDRV_HDSP_IOCTL_GET_9632_AEB: { 4589 struct hdsp_9632_aeb h9632_aeb; 4590 4591 if (hdsp->io_type != H9632) return -EINVAL; 4592 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; 4593 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; 4594 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) 4595 return -EFAULT; 4596 break; 4597 } 4598 case SNDRV_HDSP_IOCTL_GET_VERSION: { 4599 struct hdsp_version hdsp_version; 4600 int err; 4601 4602 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4603 if (hdsp->io_type == Undefined) { 4604 if ((err = hdsp_get_iobox_version(hdsp)) < 0) 4605 return err; 4606 } 4607 hdsp_version.io_type = hdsp->io_type; 4608 hdsp_version.firmware_rev = hdsp->firmware_rev; 4609 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) 4610 return -EFAULT; 4611 break; 4612 } 4613 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { 4614 struct hdsp_firmware __user *firmware; 4615 u32 __user *firmware_data; 4616 int err; 4617 4618 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4619 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ 4620 if (hdsp->io_type == Undefined) return -EINVAL; 4621 4622 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) 4623 return -EBUSY; 4624 4625 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n"); 4626 firmware = (struct hdsp_firmware __user *)argp; 4627 4628 if (get_user(firmware_data, &firmware->firmware_data)) 4629 return -EFAULT; 4630 4631 if (hdsp_check_for_iobox (hdsp)) 4632 return -EIO; 4633 4634 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) 4635 return -EFAULT; 4636 4637 hdsp->state |= HDSP_FirmwareCached; 4638 4639 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) 4640 return err; 4641 4642 if (!(hdsp->state & HDSP_InitializationComplete)) { 4643 if ((err = snd_hdsp_enable_io(hdsp)) < 0) 4644 return err; 4645 4646 snd_hdsp_initialize_channels(hdsp); 4647 snd_hdsp_initialize_midi_flush(hdsp); 4648 4649 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { 4650 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); 4651 return err; 4652 } 4653 } 4654 break; 4655 } 4656 case SNDRV_HDSP_IOCTL_GET_MIXER: { 4657 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp; 4658 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) 4659 return -EFAULT; 4660 break; 4661 } 4662 default: 4663 return -EINVAL; 4664 } 4665 return 0; 4666 } 4667 4668 static struct snd_pcm_ops snd_hdsp_playback_ops = { 4669 .open = snd_hdsp_playback_open, 4670 .close = snd_hdsp_playback_release, 4671 .ioctl = snd_hdsp_ioctl, 4672 .hw_params = snd_hdsp_hw_params, 4673 .prepare = snd_hdsp_prepare, 4674 .trigger = snd_hdsp_trigger, 4675 .pointer = snd_hdsp_hw_pointer, 4676 .copy = snd_hdsp_playback_copy, 4677 .silence = snd_hdsp_hw_silence, 4678 }; 4679 4680 static struct snd_pcm_ops snd_hdsp_capture_ops = { 4681 .open = snd_hdsp_capture_open, 4682 .close = snd_hdsp_capture_release, 4683 .ioctl = snd_hdsp_ioctl, 4684 .hw_params = snd_hdsp_hw_params, 4685 .prepare = snd_hdsp_prepare, 4686 .trigger = snd_hdsp_trigger, 4687 .pointer = snd_hdsp_hw_pointer, 4688 .copy = snd_hdsp_capture_copy, 4689 }; 4690 4691 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp) 4692 { 4693 struct snd_hwdep *hw; 4694 int err; 4695 4696 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0) 4697 return err; 4698 4699 hdsp->hwdep = hw; 4700 hw->private_data = hdsp; 4701 strcpy(hw->name, "HDSP hwdep interface"); 4702 4703 hw->ops.open = snd_hdsp_hwdep_dummy_op; 4704 hw->ops.ioctl = snd_hdsp_hwdep_ioctl; 4705 hw->ops.release = snd_hdsp_hwdep_dummy_op; 4706 4707 return 0; 4708 } 4709 4710 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp) 4711 { 4712 struct snd_pcm *pcm; 4713 int err; 4714 4715 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0) 4716 return err; 4717 4718 hdsp->pcm = pcm; 4719 pcm->private_data = hdsp; 4720 strcpy(pcm->name, hdsp->card_name); 4721 4722 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); 4723 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); 4724 4725 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 4726 4727 return 0; 4728 } 4729 4730 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp) 4731 { 4732 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; 4733 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 4734 } 4735 4736 static int snd_hdsp_enable_io (struct hdsp *hdsp) 4737 { 4738 int i; 4739 4740 if (hdsp_fifo_wait (hdsp, 0, 100)) { 4741 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n"); 4742 return -EIO; 4743 } 4744 4745 for (i = 0; i < hdsp->max_channels; ++i) { 4746 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); 4747 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); 4748 } 4749 4750 return 0; 4751 } 4752 4753 static void snd_hdsp_initialize_channels(struct hdsp *hdsp) 4754 { 4755 int status, aebi_channels, aebo_channels; 4756 4757 switch (hdsp->io_type) { 4758 case Digiface: 4759 hdsp->card_name = "RME Hammerfall DSP + Digiface"; 4760 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; 4761 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; 4762 break; 4763 4764 case H9652: 4765 hdsp->card_name = "RME Hammerfall HDSP 9652"; 4766 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; 4767 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; 4768 break; 4769 4770 case H9632: 4771 status = hdsp_read(hdsp, HDSP_statusRegister); 4772 /* HDSP_AEBx bits are low when AEB are connected */ 4773 aebi_channels = (status & HDSP_AEBI) ? 0 : 4; 4774 aebo_channels = (status & HDSP_AEBO) ? 0 : 4; 4775 hdsp->card_name = "RME Hammerfall HDSP 9632"; 4776 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; 4777 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; 4778 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; 4779 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; 4780 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; 4781 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; 4782 break; 4783 4784 case Multiface: 4785 hdsp->card_name = "RME Hammerfall DSP + Multiface"; 4786 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; 4787 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; 4788 break; 4789 4790 default: 4791 /* should never get here */ 4792 break; 4793 } 4794 } 4795 4796 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp) 4797 { 4798 snd_hdsp_flush_midi_input (hdsp, 0); 4799 snd_hdsp_flush_midi_input (hdsp, 1); 4800 } 4801 4802 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp) 4803 { 4804 int err; 4805 4806 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { 4807 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n"); 4808 return err; 4809 } 4810 4811 4812 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { 4813 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n"); 4814 return err; 4815 } 4816 4817 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 4818 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { 4819 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n"); 4820 return err; 4821 } 4822 } 4823 4824 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { 4825 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n"); 4826 return err; 4827 } 4828 4829 snd_hdsp_proc_init(hdsp); 4830 4831 hdsp->system_sample_rate = -1; 4832 hdsp->playback_pid = -1; 4833 hdsp->capture_pid = -1; 4834 hdsp->capture_substream = NULL; 4835 hdsp->playback_substream = NULL; 4836 4837 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { 4838 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n"); 4839 return err; 4840 } 4841 4842 if (!(hdsp->state & HDSP_InitializationComplete)) { 4843 strcpy(card->shortname, "Hammerfall DSP"); 4844 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 4845 hdsp->port, hdsp->irq); 4846 4847 if ((err = snd_card_register(card)) < 0) { 4848 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n"); 4849 return err; 4850 } 4851 hdsp->state |= HDSP_InitializationComplete; 4852 } 4853 4854 return 0; 4855 } 4856 4857 #ifdef HDSP_FW_LOADER 4858 /* load firmware via hotplug fw loader */ 4859 static int hdsp_request_fw_loader(struct hdsp *hdsp) 4860 { 4861 const char *fwfile; 4862 const struct firmware *fw; 4863 int err; 4864 4865 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 4866 return 0; 4867 if (hdsp->io_type == Undefined) { 4868 if ((err = hdsp_get_iobox_version(hdsp)) < 0) 4869 return err; 4870 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 4871 return 0; 4872 } 4873 4874 /* caution: max length of firmware filename is 30! */ 4875 switch (hdsp->io_type) { 4876 case Multiface: 4877 if (hdsp->firmware_rev == 0xa) 4878 fwfile = "multiface_firmware.bin"; 4879 else 4880 fwfile = "multiface_firmware_rev11.bin"; 4881 break; 4882 case Digiface: 4883 if (hdsp->firmware_rev == 0xa) 4884 fwfile = "digiface_firmware.bin"; 4885 else 4886 fwfile = "digiface_firmware_rev11.bin"; 4887 break; 4888 default: 4889 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type); 4890 return -EINVAL; 4891 } 4892 4893 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { 4894 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile); 4895 return -ENOENT; 4896 } 4897 if (fw->size < sizeof(hdsp->firmware_cache)) { 4898 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n", 4899 (int)fw->size, (int)sizeof(hdsp->firmware_cache)); 4900 release_firmware(fw); 4901 return -EINVAL; 4902 } 4903 4904 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache)); 4905 4906 release_firmware(fw); 4907 4908 hdsp->state |= HDSP_FirmwareCached; 4909 4910 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) 4911 return err; 4912 4913 if (!(hdsp->state & HDSP_InitializationComplete)) { 4914 if ((err = snd_hdsp_enable_io(hdsp)) < 0) 4915 return err; 4916 4917 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) { 4918 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n"); 4919 return err; 4920 } 4921 snd_hdsp_initialize_channels(hdsp); 4922 snd_hdsp_initialize_midi_flush(hdsp); 4923 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { 4924 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); 4925 return err; 4926 } 4927 } 4928 return 0; 4929 } 4930 #endif 4931 4932 static int __devinit snd_hdsp_create(struct snd_card *card, 4933 struct hdsp *hdsp) 4934 { 4935 struct pci_dev *pci = hdsp->pci; 4936 int err; 4937 int is_9652 = 0; 4938 int is_9632 = 0; 4939 4940 hdsp->irq = -1; 4941 hdsp->state = 0; 4942 hdsp->midi[0].rmidi = NULL; 4943 hdsp->midi[1].rmidi = NULL; 4944 hdsp->midi[0].input = NULL; 4945 hdsp->midi[1].input = NULL; 4946 hdsp->midi[0].output = NULL; 4947 hdsp->midi[1].output = NULL; 4948 hdsp->midi[0].pending = 0; 4949 hdsp->midi[1].pending = 0; 4950 spin_lock_init(&hdsp->midi[0].lock); 4951 spin_lock_init(&hdsp->midi[1].lock); 4952 hdsp->iobase = NULL; 4953 hdsp->control_register = 0; 4954 hdsp->control2_register = 0; 4955 hdsp->io_type = Undefined; 4956 hdsp->max_channels = 26; 4957 4958 hdsp->card = card; 4959 4960 spin_lock_init(&hdsp->lock); 4961 4962 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp); 4963 4964 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); 4965 hdsp->firmware_rev &= 0xff; 4966 4967 /* From Martin Bjoernsen : 4968 "It is important that the card's latency timer register in 4969 the PCI configuration space is set to a value much larger 4970 than 0 by the computer's BIOS or the driver. 4971 The windows driver always sets this 8 bit register [...] 4972 to its maximum 255 to avoid problems with some computers." 4973 */ 4974 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); 4975 4976 strcpy(card->driver, "H-DSP"); 4977 strcpy(card->mixername, "Xilinx FPGA"); 4978 4979 if (hdsp->firmware_rev < 0xa) 4980 return -ENODEV; 4981 else if (hdsp->firmware_rev < 0x64) 4982 hdsp->card_name = "RME Hammerfall DSP"; 4983 else if (hdsp->firmware_rev < 0x96) { 4984 hdsp->card_name = "RME HDSP 9652"; 4985 is_9652 = 1; 4986 } else { 4987 hdsp->card_name = "RME HDSP 9632"; 4988 hdsp->max_channels = 16; 4989 is_9632 = 1; 4990 } 4991 4992 if ((err = pci_enable_device(pci)) < 0) 4993 return err; 4994 4995 pci_set_master(hdsp->pci); 4996 4997 if ((err = pci_request_regions(pci, "hdsp")) < 0) 4998 return err; 4999 hdsp->port = pci_resource_start(pci, 0); 5000 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) { 5001 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); 5002 return -EBUSY; 5003 } 5004 5005 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED, 5006 "hdsp", hdsp)) { 5007 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq); 5008 return -EBUSY; 5009 } 5010 5011 hdsp->irq = pci->irq; 5012 hdsp->precise_ptr = 0; 5013 hdsp->use_midi_tasklet = 1; 5014 hdsp->dds_value = 0; 5015 5016 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) 5017 return err; 5018 5019 if (!is_9652 && !is_9632) { 5020 /* we wait 2 seconds to let freshly inserted cardbus cards do their hardware init */ 5021 ssleep(2); 5022 5023 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 5024 #ifdef HDSP_FW_LOADER 5025 if ((err = hdsp_request_fw_loader(hdsp)) < 0) 5026 /* we don't fail as this can happen 5027 if userspace is not ready for 5028 firmware upload 5029 */ 5030 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n"); 5031 else 5032 /* init is complete, we return */ 5033 return 0; 5034 #endif 5035 /* no iobox connected, we defer initialization */ 5036 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n"); 5037 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) 5038 return err; 5039 return 0; 5040 } else { 5041 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n"); 5042 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 5043 hdsp->io_type = Multiface; 5044 else 5045 hdsp->io_type = Digiface; 5046 } 5047 } 5048 5049 if ((err = snd_hdsp_enable_io(hdsp)) != 0) 5050 return err; 5051 5052 if (is_9652) 5053 hdsp->io_type = H9652; 5054 5055 if (is_9632) 5056 hdsp->io_type = H9632; 5057 5058 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) 5059 return err; 5060 5061 snd_hdsp_initialize_channels(hdsp); 5062 snd_hdsp_initialize_midi_flush(hdsp); 5063 5064 hdsp->state |= HDSP_FirmwareLoaded; 5065 5066 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) 5067 return err; 5068 5069 return 0; 5070 } 5071 5072 static int snd_hdsp_free(struct hdsp *hdsp) 5073 { 5074 if (hdsp->port) { 5075 /* stop the audio, and cancel all interrupts */ 5076 tasklet_kill(&hdsp->midi_tasklet); 5077 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); 5078 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); 5079 } 5080 5081 if (hdsp->irq >= 0) 5082 free_irq(hdsp->irq, (void *)hdsp); 5083 5084 snd_hdsp_free_buffers(hdsp); 5085 5086 if (hdsp->iobase) 5087 iounmap(hdsp->iobase); 5088 5089 if (hdsp->port) 5090 pci_release_regions(hdsp->pci); 5091 5092 pci_disable_device(hdsp->pci); 5093 return 0; 5094 } 5095 5096 static void snd_hdsp_card_free(struct snd_card *card) 5097 { 5098 struct hdsp *hdsp = (struct hdsp *) card->private_data; 5099 5100 if (hdsp) 5101 snd_hdsp_free(hdsp); 5102 } 5103 5104 static int __devinit snd_hdsp_probe(struct pci_dev *pci, 5105 const struct pci_device_id *pci_id) 5106 { 5107 static int dev; 5108 struct hdsp *hdsp; 5109 struct snd_card *card; 5110 int err; 5111 5112 if (dev >= SNDRV_CARDS) 5113 return -ENODEV; 5114 if (!enable[dev]) { 5115 dev++; 5116 return -ENOENT; 5117 } 5118 5119 if (!(card = snd_card_new(index[dev], id[dev], THIS_MODULE, sizeof(struct hdsp)))) 5120 return -ENOMEM; 5121 5122 hdsp = (struct hdsp *) card->private_data; 5123 card->private_free = snd_hdsp_card_free; 5124 hdsp->dev = dev; 5125 hdsp->pci = pci; 5126 snd_card_set_dev(card, &pci->dev); 5127 5128 if ((err = snd_hdsp_create(card, hdsp)) < 0) { 5129 snd_card_free(card); 5130 return err; 5131 } 5132 5133 strcpy(card->shortname, "Hammerfall DSP"); 5134 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 5135 hdsp->port, hdsp->irq); 5136 5137 if ((err = snd_card_register(card)) < 0) { 5138 snd_card_free(card); 5139 return err; 5140 } 5141 pci_set_drvdata(pci, card); 5142 dev++; 5143 return 0; 5144 } 5145 5146 static void __devexit snd_hdsp_remove(struct pci_dev *pci) 5147 { 5148 snd_card_free(pci_get_drvdata(pci)); 5149 pci_set_drvdata(pci, NULL); 5150 } 5151 5152 static struct pci_driver driver = { 5153 .name = "RME Hammerfall DSP", 5154 .id_table = snd_hdsp_ids, 5155 .probe = snd_hdsp_probe, 5156 .remove = __devexit_p(snd_hdsp_remove), 5157 }; 5158 5159 static int __init alsa_card_hdsp_init(void) 5160 { 5161 return pci_register_driver(&driver); 5162 } 5163 5164 static void __exit alsa_card_hdsp_exit(void) 5165 { 5166 pci_unregister_driver(&driver); 5167 } 5168 5169 module_init(alsa_card_hdsp_init) 5170 module_exit(alsa_card_hdsp_exit) 5171