1 /* 2 * ALSA driver for RME Hammerfall DSP audio interface(s) 3 * 4 * Copyright (c) 2002 Paul Davis 5 * Marcus Andersson 6 * Thomas Charbonnel 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 * 22 */ 23 24 #include <linux/init.h> 25 #include <linux/delay.h> 26 #include <linux/interrupt.h> 27 #include <linux/pci.h> 28 #include <linux/firmware.h> 29 #include <linux/moduleparam.h> 30 #include <linux/math64.h> 31 32 #include <sound/core.h> 33 #include <sound/control.h> 34 #include <sound/pcm.h> 35 #include <sound/info.h> 36 #include <sound/asoundef.h> 37 #include <sound/rawmidi.h> 38 #include <sound/hwdep.h> 39 #include <sound/initval.h> 40 #include <sound/hdsp.h> 41 42 #include <asm/byteorder.h> 43 #include <asm/current.h> 44 #include <asm/io.h> 45 46 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 47 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 48 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 49 50 module_param_array(index, int, NULL, 0444); 51 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface."); 52 module_param_array(id, charp, NULL, 0444); 53 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface."); 54 module_param_array(enable, bool, NULL, 0444); 55 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards."); 56 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>"); 57 MODULE_DESCRIPTION("RME Hammerfall DSP"); 58 MODULE_LICENSE("GPL"); 59 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP}," 60 "{RME HDSP-9652}," 61 "{RME HDSP-9632}}"); 62 #ifdef HDSP_FW_LOADER 63 MODULE_FIRMWARE("multiface_firmware.bin"); 64 MODULE_FIRMWARE("multiface_firmware_rev11.bin"); 65 MODULE_FIRMWARE("digiface_firmware.bin"); 66 MODULE_FIRMWARE("digiface_firmware_rev11.bin"); 67 #endif 68 69 #define HDSP_MAX_CHANNELS 26 70 #define HDSP_MAX_DS_CHANNELS 14 71 #define HDSP_MAX_QS_CHANNELS 8 72 #define DIGIFACE_SS_CHANNELS 26 73 #define DIGIFACE_DS_CHANNELS 14 74 #define MULTIFACE_SS_CHANNELS 18 75 #define MULTIFACE_DS_CHANNELS 14 76 #define H9652_SS_CHANNELS 26 77 #define H9652_DS_CHANNELS 14 78 /* This does not include possible Analog Extension Boards 79 AEBs are detected at card initialization 80 */ 81 #define H9632_SS_CHANNELS 12 82 #define H9632_DS_CHANNELS 8 83 #define H9632_QS_CHANNELS 4 84 85 /* Write registers. These are defined as byte-offsets from the iobase value. 86 */ 87 #define HDSP_resetPointer 0 88 #define HDSP_freqReg 0 89 #define HDSP_outputBufferAddress 32 90 #define HDSP_inputBufferAddress 36 91 #define HDSP_controlRegister 64 92 #define HDSP_interruptConfirmation 96 93 #define HDSP_outputEnable 128 94 #define HDSP_control2Reg 256 95 #define HDSP_midiDataOut0 352 96 #define HDSP_midiDataOut1 356 97 #define HDSP_fifoData 368 98 #define HDSP_inputEnable 384 99 100 /* Read registers. These are defined as byte-offsets from the iobase value 101 */ 102 103 #define HDSP_statusRegister 0 104 #define HDSP_timecode 128 105 #define HDSP_status2Register 192 106 #define HDSP_midiDataIn0 360 107 #define HDSP_midiDataIn1 364 108 #define HDSP_midiStatusOut0 384 109 #define HDSP_midiStatusOut1 388 110 #define HDSP_midiStatusIn0 392 111 #define HDSP_midiStatusIn1 396 112 #define HDSP_fifoStatus 400 113 114 /* the meters are regular i/o-mapped registers, but offset 115 considerably from the rest. the peak registers are reset 116 when read; the least-significant 4 bits are full-scale counters; 117 the actual peak value is in the most-significant 24 bits. 118 */ 119 120 #define HDSP_playbackPeakLevel 4096 /* 26 * 32 bit values */ 121 #define HDSP_inputPeakLevel 4224 /* 26 * 32 bit values */ 122 #define HDSP_outputPeakLevel 4352 /* (26+2) * 32 bit values */ 123 #define HDSP_playbackRmsLevel 4612 /* 26 * 64 bit values */ 124 #define HDSP_inputRmsLevel 4868 /* 26 * 64 bit values */ 125 126 127 /* This is for H9652 cards 128 Peak values are read downward from the base 129 Rms values are read upward 130 There are rms values for the outputs too 131 26*3 values are read in ss mode 132 14*3 in ds mode, with no gap between values 133 */ 134 #define HDSP_9652_peakBase 7164 135 #define HDSP_9652_rmsBase 4096 136 137 /* c.f. the hdsp_9632_meters_t struct */ 138 #define HDSP_9632_metersBase 4096 139 140 #define HDSP_IO_EXTENT 7168 141 142 /* control2 register bits */ 143 144 #define HDSP_TMS 0x01 145 #define HDSP_TCK 0x02 146 #define HDSP_TDI 0x04 147 #define HDSP_JTAG 0x08 148 #define HDSP_PWDN 0x10 149 #define HDSP_PROGRAM 0x020 150 #define HDSP_CONFIG_MODE_0 0x040 151 #define HDSP_CONFIG_MODE_1 0x080 152 #define HDSP_VERSION_BIT 0x100 153 #define HDSP_BIGENDIAN_MODE 0x200 154 #define HDSP_RD_MULTIPLE 0x400 155 #define HDSP_9652_ENABLE_MIXER 0x800 156 #define HDSP_TDO 0x10000000 157 158 #define HDSP_S_PROGRAM (HDSP_PROGRAM|HDSP_CONFIG_MODE_0) 159 #define HDSP_S_LOAD (HDSP_PROGRAM|HDSP_CONFIG_MODE_1) 160 161 /* Control Register bits */ 162 163 #define HDSP_Start (1<<0) /* start engine */ 164 #define HDSP_Latency0 (1<<1) /* buffer size = 2^n where n is defined by Latency{2,1,0} */ 165 #define HDSP_Latency1 (1<<2) /* [ see above ] */ 166 #define HDSP_Latency2 (1<<3) /* [ see above ] */ 167 #define HDSP_ClockModeMaster (1<<4) /* 1=Master, 0=Slave/Autosync */ 168 #define HDSP_AudioInterruptEnable (1<<5) /* what do you think ? */ 169 #define HDSP_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */ 170 #define HDSP_Frequency1 (1<<7) /* 0=32kHz/64kHz/128kHz */ 171 #define HDSP_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */ 172 #define HDSP_SPDIFProfessional (1<<9) /* 0=consumer, 1=professional */ 173 #define HDSP_SPDIFEmphasis (1<<10) /* 0=none, 1=on */ 174 #define HDSP_SPDIFNonAudio (1<<11) /* 0=off, 1=on */ 175 #define HDSP_SPDIFOpticalOut (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */ 176 #define HDSP_SyncRef2 (1<<13) 177 #define HDSP_SPDIFInputSelect0 (1<<14) 178 #define HDSP_SPDIFInputSelect1 (1<<15) 179 #define HDSP_SyncRef0 (1<<16) 180 #define HDSP_SyncRef1 (1<<17) 181 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */ 182 #define HDSP_XLRBreakoutCable (1<<20) /* For H9632 cards */ 183 #define HDSP_Midi0InterruptEnable (1<<22) 184 #define HDSP_Midi1InterruptEnable (1<<23) 185 #define HDSP_LineOut (1<<24) 186 #define HDSP_ADGain0 (1<<25) /* From here : H9632 specific */ 187 #define HDSP_ADGain1 (1<<26) 188 #define HDSP_DAGain0 (1<<27) 189 #define HDSP_DAGain1 (1<<28) 190 #define HDSP_PhoneGain0 (1<<29) 191 #define HDSP_PhoneGain1 (1<<30) 192 #define HDSP_QuadSpeed (1<<31) 193 194 #define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1) 195 #define HDSP_ADGainMinus10dBV HDSP_ADGainMask 196 #define HDSP_ADGainPlus4dBu (HDSP_ADGain0) 197 #define HDSP_ADGainLowGain 0 198 199 #define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1) 200 #define HDSP_DAGainHighGain HDSP_DAGainMask 201 #define HDSP_DAGainPlus4dBu (HDSP_DAGain0) 202 #define HDSP_DAGainMinus10dBV 0 203 204 #define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1) 205 #define HDSP_PhoneGain0dB HDSP_PhoneGainMask 206 #define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0) 207 #define HDSP_PhoneGainMinus12dB 0 208 209 #define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2) 210 #define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed) 211 212 #define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 213 #define HDSP_SPDIFInputADAT1 0 214 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0) 215 #define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1) 216 #define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1) 217 218 #define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2) 219 #define HDSP_SyncRef_ADAT1 0 220 #define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0) 221 #define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1) 222 #define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1) 223 #define HDSP_SyncRef_WORD (HDSP_SyncRef2) 224 #define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2) 225 226 /* Sample Clock Sources */ 227 228 #define HDSP_CLOCK_SOURCE_AUTOSYNC 0 229 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1 230 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2 231 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3 232 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4 233 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5 234 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6 235 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7 236 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8 237 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9 238 239 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */ 240 241 #define HDSP_SYNC_FROM_WORD 0 242 #define HDSP_SYNC_FROM_SPDIF 1 243 #define HDSP_SYNC_FROM_ADAT1 2 244 #define HDSP_SYNC_FROM_ADAT_SYNC 3 245 #define HDSP_SYNC_FROM_ADAT2 4 246 #define HDSP_SYNC_FROM_ADAT3 5 247 248 /* SyncCheck status */ 249 250 #define HDSP_SYNC_CHECK_NO_LOCK 0 251 #define HDSP_SYNC_CHECK_LOCK 1 252 #define HDSP_SYNC_CHECK_SYNC 2 253 254 /* AutoSync references - used by "autosync_ref" control switch */ 255 256 #define HDSP_AUTOSYNC_FROM_WORD 0 257 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1 258 #define HDSP_AUTOSYNC_FROM_SPDIF 2 259 #define HDSP_AUTOSYNC_FROM_NONE 3 260 #define HDSP_AUTOSYNC_FROM_ADAT1 4 261 #define HDSP_AUTOSYNC_FROM_ADAT2 5 262 #define HDSP_AUTOSYNC_FROM_ADAT3 6 263 264 /* Possible sources of S/PDIF input */ 265 266 #define HDSP_SPDIFIN_OPTICAL 0 /* optical (ADAT1) */ 267 #define HDSP_SPDIFIN_COAXIAL 1 /* coaxial (RCA) */ 268 #define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */ 269 #define HDSP_SPDIFIN_AES 3 /* xlr for H9632 (AES)*/ 270 271 #define HDSP_Frequency32KHz HDSP_Frequency0 272 #define HDSP_Frequency44_1KHz HDSP_Frequency1 273 #define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0) 274 #define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0) 275 #define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1) 276 #define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 277 /* For H9632 cards */ 278 #define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0) 279 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1) 280 #define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0) 281 /* RME says n = 104857600000000, but in the windows MADI driver, I see: 282 return 104857600000000 / rate; // 100 MHz 283 return 110100480000000 / rate; // 105 MHz 284 */ 285 #define DDS_NUMERATOR 104857600000000ULL; /* = 2^20 * 10^8 */ 286 287 #define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask) 288 #define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1) 289 290 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14) 291 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3) 292 293 /* Status Register bits */ 294 295 #define HDSP_audioIRQPending (1<<0) 296 #define HDSP_Lock2 (1<<1) /* this is for Digiface and H9652 */ 297 #define HDSP_spdifFrequency3 HDSP_Lock2 /* this is for H9632 only */ 298 #define HDSP_Lock1 (1<<2) 299 #define HDSP_Lock0 (1<<3) 300 #define HDSP_SPDIFSync (1<<4) 301 #define HDSP_TimecodeLock (1<<5) 302 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */ 303 #define HDSP_Sync2 (1<<16) 304 #define HDSP_Sync1 (1<<17) 305 #define HDSP_Sync0 (1<<18) 306 #define HDSP_DoubleSpeedStatus (1<<19) 307 #define HDSP_ConfigError (1<<20) 308 #define HDSP_DllError (1<<21) 309 #define HDSP_spdifFrequency0 (1<<22) 310 #define HDSP_spdifFrequency1 (1<<23) 311 #define HDSP_spdifFrequency2 (1<<24) 312 #define HDSP_SPDIFErrorFlag (1<<25) 313 #define HDSP_BufferID (1<<26) 314 #define HDSP_TimecodeSync (1<<27) 315 #define HDSP_AEBO (1<<28) /* H9632 specific Analog Extension Boards */ 316 #define HDSP_AEBI (1<<29) /* 0 = present, 1 = absent */ 317 #define HDSP_midi0IRQPending (1<<30) 318 #define HDSP_midi1IRQPending (1<<31) 319 320 #define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2) 321 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\ 322 HDSP_spdifFrequency1|\ 323 HDSP_spdifFrequency2|\ 324 HDSP_spdifFrequency3) 325 326 #define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0) 327 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1) 328 #define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1) 329 330 #define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2) 331 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2) 332 #define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1) 333 334 /* This is for H9632 cards */ 335 #define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\ 336 HDSP_spdifFrequency1|\ 337 HDSP_spdifFrequency2) 338 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3 339 #define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0) 340 341 /* Status2 Register bits */ 342 343 #define HDSP_version0 (1<<0) 344 #define HDSP_version1 (1<<1) 345 #define HDSP_version2 (1<<2) 346 #define HDSP_wc_lock (1<<3) 347 #define HDSP_wc_sync (1<<4) 348 #define HDSP_inp_freq0 (1<<5) 349 #define HDSP_inp_freq1 (1<<6) 350 #define HDSP_inp_freq2 (1<<7) 351 #define HDSP_SelSyncRef0 (1<<8) 352 #define HDSP_SelSyncRef1 (1<<9) 353 #define HDSP_SelSyncRef2 (1<<10) 354 355 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync) 356 357 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2) 358 #define HDSP_systemFrequency32 (HDSP_inp_freq0) 359 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1) 360 #define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1) 361 #define HDSP_systemFrequency64 (HDSP_inp_freq2) 362 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2) 363 #define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2) 364 /* FIXME : more values for 9632 cards ? */ 365 366 #define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2) 367 #define HDSP_SelSyncRef_ADAT1 0 368 #define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0) 369 #define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1) 370 #define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1) 371 #define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2) 372 #define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2) 373 374 /* Card state flags */ 375 376 #define HDSP_InitializationComplete (1<<0) 377 #define HDSP_FirmwareLoaded (1<<1) 378 #define HDSP_FirmwareCached (1<<2) 379 380 /* FIFO wait times, defined in terms of 1/10ths of msecs */ 381 382 #define HDSP_LONG_WAIT 5000 383 #define HDSP_SHORT_WAIT 30 384 385 #define UNITY_GAIN 32768 386 #define MINUS_INFINITY_GAIN 0 387 388 /* the size of a substream (1 mono data stream) */ 389 390 #define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024) 391 #define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES) 392 393 /* the size of the area we need to allocate for DMA transfers. the 394 size is the same regardless of the number of channels - the 395 Multiface still uses the same memory area. 396 397 Note that we allocate 1 more channel than is apparently needed 398 because the h/w seems to write 1 byte beyond the end of the last 399 page. Sigh. 400 */ 401 402 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES) 403 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024) 404 405 /* use hotplug firmware loader? */ 406 #if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE) 407 #if !defined(HDSP_USE_HWDEP_LOADER) 408 #define HDSP_FW_LOADER 409 #endif 410 #endif 411 412 struct hdsp_9632_meters { 413 u32 input_peak[16]; 414 u32 playback_peak[16]; 415 u32 output_peak[16]; 416 u32 xxx_peak[16]; 417 u32 padding[64]; 418 u32 input_rms_low[16]; 419 u32 playback_rms_low[16]; 420 u32 output_rms_low[16]; 421 u32 xxx_rms_low[16]; 422 u32 input_rms_high[16]; 423 u32 playback_rms_high[16]; 424 u32 output_rms_high[16]; 425 u32 xxx_rms_high[16]; 426 }; 427 428 struct hdsp_midi { 429 struct hdsp *hdsp; 430 int id; 431 struct snd_rawmidi *rmidi; 432 struct snd_rawmidi_substream *input; 433 struct snd_rawmidi_substream *output; 434 char istimer; /* timer in use */ 435 struct timer_list timer; 436 spinlock_t lock; 437 int pending; 438 }; 439 440 struct hdsp { 441 spinlock_t lock; 442 struct snd_pcm_substream *capture_substream; 443 struct snd_pcm_substream *playback_substream; 444 struct hdsp_midi midi[2]; 445 struct tasklet_struct midi_tasklet; 446 int use_midi_tasklet; 447 int precise_ptr; 448 u32 control_register; /* cached value */ 449 u32 control2_register; /* cached value */ 450 u32 creg_spdif; 451 u32 creg_spdif_stream; 452 int clock_source_locked; 453 char *card_name; /* digiface/multiface */ 454 enum HDSP_IO_Type io_type; /* ditto, but for code use */ 455 unsigned short firmware_rev; 456 unsigned short state; /* stores state bits */ 457 u32 firmware_cache[24413]; /* this helps recover from accidental iobox power failure */ 458 size_t period_bytes; /* guess what this is */ 459 unsigned char max_channels; 460 unsigned char qs_in_channels; /* quad speed mode for H9632 */ 461 unsigned char ds_in_channels; 462 unsigned char ss_in_channels; /* different for multiface/digiface */ 463 unsigned char qs_out_channels; 464 unsigned char ds_out_channels; 465 unsigned char ss_out_channels; 466 467 struct snd_dma_buffer capture_dma_buf; 468 struct snd_dma_buffer playback_dma_buf; 469 unsigned char *capture_buffer; /* suitably aligned address */ 470 unsigned char *playback_buffer; /* suitably aligned address */ 471 472 pid_t capture_pid; 473 pid_t playback_pid; 474 int running; 475 int system_sample_rate; 476 char *channel_map; 477 int dev; 478 int irq; 479 unsigned long port; 480 void __iomem *iobase; 481 struct snd_card *card; 482 struct snd_pcm *pcm; 483 struct snd_hwdep *hwdep; 484 struct pci_dev *pci; 485 struct snd_kcontrol *spdif_ctl; 486 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE]; 487 unsigned int dds_value; /* last value written to freq register */ 488 }; 489 490 /* These tables map the ALSA channels 1..N to the channels that we 491 need to use in order to find the relevant channel buffer. RME 492 refer to this kind of mapping as between "the ADAT channel and 493 the DMA channel." We index it using the logical audio channel, 494 and the value is the DMA channel (i.e. channel buffer number) 495 where the data for that channel can be read/written from/to. 496 */ 497 498 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = { 499 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 500 18, 19, 20, 21, 22, 23, 24, 25 501 }; 502 503 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */ 504 /* Analog */ 505 0, 1, 2, 3, 4, 5, 6, 7, 506 /* ADAT 2 */ 507 16, 17, 18, 19, 20, 21, 22, 23, 508 /* SPDIF */ 509 24, 25, 510 -1, -1, -1, -1, -1, -1, -1, -1 511 }; 512 513 static char channel_map_ds[HDSP_MAX_CHANNELS] = { 514 /* ADAT channels are remapped */ 515 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 516 /* channels 12 and 13 are S/PDIF */ 517 24, 25, 518 /* others don't exist */ 519 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 520 }; 521 522 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = { 523 /* ADAT channels */ 524 0, 1, 2, 3, 4, 5, 6, 7, 525 /* SPDIF */ 526 8, 9, 527 /* Analog */ 528 10, 11, 529 /* AO4S-192 and AI4S-192 extension boards */ 530 12, 13, 14, 15, 531 /* others don't exist */ 532 -1, -1, -1, -1, -1, -1, -1, -1, 533 -1, -1 534 }; 535 536 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = { 537 /* ADAT */ 538 1, 3, 5, 7, 539 /* SPDIF */ 540 8, 9, 541 /* Analog */ 542 10, 11, 543 /* AO4S-192 and AI4S-192 extension boards */ 544 12, 13, 14, 15, 545 /* others don't exist */ 546 -1, -1, -1, -1, -1, -1, -1, -1, 547 -1, -1, -1, -1, -1, -1 548 }; 549 550 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = { 551 /* ADAT is disabled in this mode */ 552 /* SPDIF */ 553 8, 9, 554 /* Analog */ 555 10, 11, 556 /* AO4S-192 and AI4S-192 extension boards */ 557 12, 13, 14, 15, 558 /* others don't exist */ 559 -1, -1, -1, -1, -1, -1, -1, -1, 560 -1, -1, -1, -1, -1, -1, -1, -1, 561 -1, -1 562 }; 563 564 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size) 565 { 566 dmab->dev.type = SNDRV_DMA_TYPE_DEV; 567 dmab->dev.dev = snd_dma_pci_data(pci); 568 if (snd_dma_get_reserved_buf(dmab, snd_dma_pci_buf_id(pci))) { 569 if (dmab->bytes >= size) 570 return 0; 571 } 572 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 573 size, dmab) < 0) 574 return -ENOMEM; 575 return 0; 576 } 577 578 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci) 579 { 580 if (dmab->area) { 581 dmab->dev.dev = NULL; /* make it anonymous */ 582 snd_dma_reserve_buf(dmab, snd_dma_pci_buf_id(pci)); 583 } 584 } 585 586 587 static DEFINE_PCI_DEVICE_TABLE(snd_hdsp_ids) = { 588 { 589 .vendor = PCI_VENDOR_ID_XILINX, 590 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP, 591 .subvendor = PCI_ANY_ID, 592 .subdevice = PCI_ANY_ID, 593 }, /* RME Hammerfall-DSP */ 594 { 0, }, 595 }; 596 597 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids); 598 599 /* prototypes */ 600 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp); 601 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp); 602 static int snd_hdsp_enable_io (struct hdsp *hdsp); 603 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp); 604 static void snd_hdsp_initialize_channels (struct hdsp *hdsp); 605 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout); 606 static int hdsp_autosync_ref(struct hdsp *hdsp); 607 static int snd_hdsp_set_defaults(struct hdsp *hdsp); 608 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp); 609 610 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out) 611 { 612 switch (hdsp->io_type) { 613 case Multiface: 614 case Digiface: 615 default: 616 if (hdsp->firmware_rev == 0xa) 617 return (64 * out) + (32 + (in)); 618 else 619 return (52 * out) + (26 + (in)); 620 case H9632: 621 return (32 * out) + (16 + (in)); 622 case H9652: 623 return (52 * out) + (26 + (in)); 624 } 625 } 626 627 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out) 628 { 629 switch (hdsp->io_type) { 630 case Multiface: 631 case Digiface: 632 default: 633 if (hdsp->firmware_rev == 0xa) 634 return (64 * out) + in; 635 else 636 return (52 * out) + in; 637 case H9632: 638 return (32 * out) + in; 639 case H9652: 640 return (52 * out) + in; 641 } 642 } 643 644 static void hdsp_write(struct hdsp *hdsp, int reg, int val) 645 { 646 writel(val, hdsp->iobase + reg); 647 } 648 649 static unsigned int hdsp_read(struct hdsp *hdsp, int reg) 650 { 651 return readl (hdsp->iobase + reg); 652 } 653 654 static int hdsp_check_for_iobox (struct hdsp *hdsp) 655 { 656 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0; 657 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_ConfigError) { 658 snd_printk ("Hammerfall-DSP: no Digiface or Multiface connected!\n"); 659 hdsp->state &= ~HDSP_FirmwareLoaded; 660 return -EIO; 661 } 662 return 0; 663 } 664 665 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops, 666 unsigned int delay) 667 { 668 unsigned int i; 669 670 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 671 return 0; 672 673 for (i = 0; i != loops; ++i) { 674 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError) 675 msleep(delay); 676 else { 677 snd_printd("Hammerfall-DSP: iobox found after %ums!\n", 678 i * delay); 679 return 0; 680 } 681 } 682 683 snd_printk("Hammerfall-DSP: no Digiface or Multiface connected!\n"); 684 hdsp->state &= ~HDSP_FirmwareLoaded; 685 return -EIO; 686 } 687 688 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) { 689 690 int i; 691 unsigned long flags; 692 693 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 694 695 snd_printk ("Hammerfall-DSP: loading firmware\n"); 696 697 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM); 698 hdsp_write (hdsp, HDSP_fifoData, 0); 699 700 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 701 snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n"); 702 return -EIO; 703 } 704 705 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 706 707 for (i = 0; i < 24413; ++i) { 708 hdsp_write(hdsp, HDSP_fifoData, hdsp->firmware_cache[i]); 709 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) { 710 snd_printk ("Hammerfall-DSP: timeout during firmware loading\n"); 711 return -EIO; 712 } 713 } 714 715 ssleep(3); 716 717 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) { 718 snd_printk ("Hammerfall-DSP: timeout at end of firmware loading\n"); 719 return -EIO; 720 } 721 722 #ifdef SNDRV_BIG_ENDIAN 723 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 724 #else 725 hdsp->control2_register = 0; 726 #endif 727 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 728 snd_printk ("Hammerfall-DSP: finished firmware loading\n"); 729 730 } 731 if (hdsp->state & HDSP_InitializationComplete) { 732 snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n"); 733 spin_lock_irqsave(&hdsp->lock, flags); 734 snd_hdsp_set_defaults(hdsp); 735 spin_unlock_irqrestore(&hdsp->lock, flags); 736 } 737 738 hdsp->state |= HDSP_FirmwareLoaded; 739 740 return 0; 741 } 742 743 static int hdsp_get_iobox_version (struct hdsp *hdsp) 744 { 745 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 746 747 hdsp_write (hdsp, HDSP_control2Reg, HDSP_PROGRAM); 748 hdsp_write (hdsp, HDSP_fifoData, 0); 749 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT) < 0) 750 return -EIO; 751 752 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 753 hdsp_write (hdsp, HDSP_fifoData, 0); 754 755 if (hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT)) { 756 hdsp->io_type = Multiface; 757 hdsp_write (hdsp, HDSP_control2Reg, HDSP_VERSION_BIT); 758 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD); 759 hdsp_fifo_wait (hdsp, 0, HDSP_SHORT_WAIT); 760 } else { 761 hdsp->io_type = Digiface; 762 } 763 } else { 764 /* firmware was already loaded, get iobox type */ 765 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 766 hdsp->io_type = Multiface; 767 else 768 hdsp->io_type = Digiface; 769 } 770 return 0; 771 } 772 773 774 #ifdef HDSP_FW_LOADER 775 static int hdsp_request_fw_loader(struct hdsp *hdsp); 776 #endif 777 778 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand) 779 { 780 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 781 return 0; 782 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 783 hdsp->state &= ~HDSP_FirmwareLoaded; 784 if (! load_on_demand) 785 return -EIO; 786 snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n"); 787 /* try to load firmware */ 788 if (! (hdsp->state & HDSP_FirmwareCached)) { 789 #ifdef HDSP_FW_LOADER 790 if (! hdsp_request_fw_loader(hdsp)) 791 return 0; 792 #endif 793 snd_printk(KERN_ERR 794 "Hammerfall-DSP: No firmware loaded nor " 795 "cached, please upload firmware.\n"); 796 return -EIO; 797 } 798 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 799 snd_printk(KERN_ERR 800 "Hammerfall-DSP: Firmware loading from " 801 "cache failed, please upload manually.\n"); 802 return -EIO; 803 } 804 } 805 return 0; 806 } 807 808 809 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout) 810 { 811 int i; 812 813 /* the fifoStatus registers reports on how many words 814 are available in the command FIFO. 815 */ 816 817 for (i = 0; i < timeout; i++) { 818 819 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count) 820 return 0; 821 822 /* not very friendly, but we only do this during a firmware 823 load and changing the mixer, so we just put up with it. 824 */ 825 826 udelay (100); 827 } 828 829 snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n", 830 count, timeout); 831 return -1; 832 } 833 834 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr) 835 { 836 if (addr >= HDSP_MATRIX_MIXER_SIZE) 837 return 0; 838 839 return hdsp->mixer_matrix[addr]; 840 } 841 842 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data) 843 { 844 unsigned int ad; 845 846 if (addr >= HDSP_MATRIX_MIXER_SIZE) 847 return -1; 848 849 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) { 850 851 /* from martin bjornsen: 852 853 "You can only write dwords to the 854 mixer memory which contain two 855 mixer values in the low and high 856 word. So if you want to change 857 value 0 you have to read value 1 858 from the cache and write both to 859 the first dword in the mixer 860 memory." 861 */ 862 863 if (hdsp->io_type == H9632 && addr >= 512) 864 return 0; 865 866 if (hdsp->io_type == H9652 && addr >= 1352) 867 return 0; 868 869 hdsp->mixer_matrix[addr] = data; 870 871 872 /* `addr' addresses a 16-bit wide address, but 873 the address space accessed via hdsp_write 874 uses byte offsets. put another way, addr 875 varies from 0 to 1351, but to access the 876 corresponding memory location, we need 877 to access 0 to 2703 ... 878 */ 879 ad = addr/2; 880 881 hdsp_write (hdsp, 4096 + (ad*4), 882 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) + 883 hdsp->mixer_matrix[addr&0x7fe]); 884 885 return 0; 886 887 } else { 888 889 ad = (addr << 16) + data; 890 891 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT)) 892 return -1; 893 894 hdsp_write (hdsp, HDSP_fifoData, ad); 895 hdsp->mixer_matrix[addr] = data; 896 897 } 898 899 return 0; 900 } 901 902 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp) 903 { 904 unsigned long flags; 905 int ret = 1; 906 907 spin_lock_irqsave(&hdsp->lock, flags); 908 if ((hdsp->playback_pid != hdsp->capture_pid) && 909 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0)) 910 ret = 0; 911 spin_unlock_irqrestore(&hdsp->lock, flags); 912 return ret; 913 } 914 915 static int hdsp_spdif_sample_rate(struct hdsp *hdsp) 916 { 917 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister); 918 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask); 919 920 /* For the 9632, the mask is different */ 921 if (hdsp->io_type == H9632) 922 rate_bits = (status & HDSP_spdifFrequencyMask_9632); 923 924 if (status & HDSP_SPDIFErrorFlag) 925 return 0; 926 927 switch (rate_bits) { 928 case HDSP_spdifFrequency32KHz: return 32000; 929 case HDSP_spdifFrequency44_1KHz: return 44100; 930 case HDSP_spdifFrequency48KHz: return 48000; 931 case HDSP_spdifFrequency64KHz: return 64000; 932 case HDSP_spdifFrequency88_2KHz: return 88200; 933 case HDSP_spdifFrequency96KHz: return 96000; 934 case HDSP_spdifFrequency128KHz: 935 if (hdsp->io_type == H9632) return 128000; 936 break; 937 case HDSP_spdifFrequency176_4KHz: 938 if (hdsp->io_type == H9632) return 176400; 939 break; 940 case HDSP_spdifFrequency192KHz: 941 if (hdsp->io_type == H9632) return 192000; 942 break; 943 default: 944 break; 945 } 946 snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status); 947 return 0; 948 } 949 950 static int hdsp_external_sample_rate(struct hdsp *hdsp) 951 { 952 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 953 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask; 954 955 /* For the 9632 card, there seems to be no bit for indicating external 956 * sample rate greater than 96kHz. The card reports the corresponding 957 * single speed. So the best means seems to get spdif rate when 958 * autosync reference is spdif */ 959 if (hdsp->io_type == H9632 && 960 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF) 961 return hdsp_spdif_sample_rate(hdsp); 962 963 switch (rate_bits) { 964 case HDSP_systemFrequency32: return 32000; 965 case HDSP_systemFrequency44_1: return 44100; 966 case HDSP_systemFrequency48: return 48000; 967 case HDSP_systemFrequency64: return 64000; 968 case HDSP_systemFrequency88_2: return 88200; 969 case HDSP_systemFrequency96: return 96000; 970 default: 971 return 0; 972 } 973 } 974 975 static void hdsp_compute_period_size(struct hdsp *hdsp) 976 { 977 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8)); 978 } 979 980 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp) 981 { 982 int position; 983 984 position = hdsp_read(hdsp, HDSP_statusRegister); 985 986 if (!hdsp->precise_ptr) 987 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0; 988 989 position &= HDSP_BufferPositionMask; 990 position /= 4; 991 position &= (hdsp->period_bytes/2) - 1; 992 return position; 993 } 994 995 static void hdsp_reset_hw_pointer(struct hdsp *hdsp) 996 { 997 hdsp_write (hdsp, HDSP_resetPointer, 0); 998 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 999 /* HDSP_resetPointer = HDSP_freqReg, which is strange and 1000 * requires (?) to write again DDS value after a reset pointer 1001 * (at least, it works like this) */ 1002 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value); 1003 } 1004 1005 static void hdsp_start_audio(struct hdsp *s) 1006 { 1007 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start); 1008 hdsp_write(s, HDSP_controlRegister, s->control_register); 1009 } 1010 1011 static void hdsp_stop_audio(struct hdsp *s) 1012 { 1013 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable); 1014 hdsp_write(s, HDSP_controlRegister, s->control_register); 1015 } 1016 1017 static void hdsp_silence_playback(struct hdsp *hdsp) 1018 { 1019 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES); 1020 } 1021 1022 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames) 1023 { 1024 int n; 1025 1026 spin_lock_irq(&s->lock); 1027 1028 frames >>= 7; 1029 n = 0; 1030 while (frames) { 1031 n++; 1032 frames >>= 1; 1033 } 1034 1035 s->control_register &= ~HDSP_LatencyMask; 1036 s->control_register |= hdsp_encode_latency(n); 1037 1038 hdsp_write(s, HDSP_controlRegister, s->control_register); 1039 1040 hdsp_compute_period_size(s); 1041 1042 spin_unlock_irq(&s->lock); 1043 1044 return 0; 1045 } 1046 1047 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate) 1048 { 1049 u64 n; 1050 1051 if (rate >= 112000) 1052 rate /= 4; 1053 else if (rate >= 56000) 1054 rate /= 2; 1055 1056 n = DDS_NUMERATOR; 1057 n = div_u64(n, rate); 1058 /* n should be less than 2^32 for being written to FREQ register */ 1059 snd_BUG_ON(n >> 32); 1060 /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS 1061 value to write it after a reset */ 1062 hdsp->dds_value = n; 1063 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value); 1064 } 1065 1066 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally) 1067 { 1068 int reject_if_open = 0; 1069 int current_rate; 1070 int rate_bits; 1071 1072 /* ASSUMPTION: hdsp->lock is either held, or 1073 there is no need for it (e.g. during module 1074 initialization). 1075 */ 1076 1077 if (!(hdsp->control_register & HDSP_ClockModeMaster)) { 1078 if (called_internally) { 1079 /* request from ctl or card initialization */ 1080 snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n"); 1081 return -1; 1082 } else { 1083 /* hw_param request while in AutoSync mode */ 1084 int external_freq = hdsp_external_sample_rate(hdsp); 1085 int spdif_freq = hdsp_spdif_sample_rate(hdsp); 1086 1087 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1088 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n"); 1089 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1)) 1090 snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n"); 1091 else if (rate != external_freq) { 1092 snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n"); 1093 return -1; 1094 } 1095 } 1096 } 1097 1098 current_rate = hdsp->system_sample_rate; 1099 1100 /* Changing from a "single speed" to a "double speed" rate is 1101 not allowed if any substreams are open. This is because 1102 such a change causes a shift in the location of 1103 the DMA buffers and a reduction in the number of available 1104 buffers. 1105 1106 Note that a similar but essentially insoluble problem 1107 exists for externally-driven rate changes. All we can do 1108 is to flag rate changes in the read/write routines. */ 1109 1110 if (rate > 96000 && hdsp->io_type != H9632) 1111 return -EINVAL; 1112 1113 switch (rate) { 1114 case 32000: 1115 if (current_rate > 48000) 1116 reject_if_open = 1; 1117 rate_bits = HDSP_Frequency32KHz; 1118 break; 1119 case 44100: 1120 if (current_rate > 48000) 1121 reject_if_open = 1; 1122 rate_bits = HDSP_Frequency44_1KHz; 1123 break; 1124 case 48000: 1125 if (current_rate > 48000) 1126 reject_if_open = 1; 1127 rate_bits = HDSP_Frequency48KHz; 1128 break; 1129 case 64000: 1130 if (current_rate <= 48000 || current_rate > 96000) 1131 reject_if_open = 1; 1132 rate_bits = HDSP_Frequency64KHz; 1133 break; 1134 case 88200: 1135 if (current_rate <= 48000 || current_rate > 96000) 1136 reject_if_open = 1; 1137 rate_bits = HDSP_Frequency88_2KHz; 1138 break; 1139 case 96000: 1140 if (current_rate <= 48000 || current_rate > 96000) 1141 reject_if_open = 1; 1142 rate_bits = HDSP_Frequency96KHz; 1143 break; 1144 case 128000: 1145 if (current_rate < 128000) 1146 reject_if_open = 1; 1147 rate_bits = HDSP_Frequency128KHz; 1148 break; 1149 case 176400: 1150 if (current_rate < 128000) 1151 reject_if_open = 1; 1152 rate_bits = HDSP_Frequency176_4KHz; 1153 break; 1154 case 192000: 1155 if (current_rate < 128000) 1156 reject_if_open = 1; 1157 rate_bits = HDSP_Frequency192KHz; 1158 break; 1159 default: 1160 return -EINVAL; 1161 } 1162 1163 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) { 1164 snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n", 1165 hdsp->capture_pid, 1166 hdsp->playback_pid); 1167 return -EBUSY; 1168 } 1169 1170 hdsp->control_register &= ~HDSP_FrequencyMask; 1171 hdsp->control_register |= rate_bits; 1172 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1173 1174 /* For HDSP9632 rev 152, need to set DDS value in FREQ register */ 1175 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152) 1176 hdsp_set_dds_value(hdsp, rate); 1177 1178 if (rate >= 128000) { 1179 hdsp->channel_map = channel_map_H9632_qs; 1180 } else if (rate > 48000) { 1181 if (hdsp->io_type == H9632) 1182 hdsp->channel_map = channel_map_H9632_ds; 1183 else 1184 hdsp->channel_map = channel_map_ds; 1185 } else { 1186 switch (hdsp->io_type) { 1187 case Multiface: 1188 hdsp->channel_map = channel_map_mf_ss; 1189 break; 1190 case Digiface: 1191 case H9652: 1192 hdsp->channel_map = channel_map_df_ss; 1193 break; 1194 case H9632: 1195 hdsp->channel_map = channel_map_H9632_ss; 1196 break; 1197 default: 1198 /* should never happen */ 1199 break; 1200 } 1201 } 1202 1203 hdsp->system_sample_rate = rate; 1204 1205 return 0; 1206 } 1207 1208 /*---------------------------------------------------------------------------- 1209 MIDI 1210 ----------------------------------------------------------------------------*/ 1211 1212 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id) 1213 { 1214 /* the hardware already does the relevant bit-mask with 0xff */ 1215 if (id) 1216 return hdsp_read(hdsp, HDSP_midiDataIn1); 1217 else 1218 return hdsp_read(hdsp, HDSP_midiDataIn0); 1219 } 1220 1221 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val) 1222 { 1223 /* the hardware already does the relevant bit-mask with 0xff */ 1224 if (id) 1225 hdsp_write(hdsp, HDSP_midiDataOut1, val); 1226 else 1227 hdsp_write(hdsp, HDSP_midiDataOut0, val); 1228 } 1229 1230 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id) 1231 { 1232 if (id) 1233 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff); 1234 else 1235 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff); 1236 } 1237 1238 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id) 1239 { 1240 int fifo_bytes_used; 1241 1242 if (id) 1243 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff; 1244 else 1245 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff; 1246 1247 if (fifo_bytes_used < 128) 1248 return 128 - fifo_bytes_used; 1249 else 1250 return 0; 1251 } 1252 1253 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id) 1254 { 1255 while (snd_hdsp_midi_input_available (hdsp, id)) 1256 snd_hdsp_midi_read_byte (hdsp, id); 1257 } 1258 1259 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi) 1260 { 1261 unsigned long flags; 1262 int n_pending; 1263 int to_write; 1264 int i; 1265 unsigned char buf[128]; 1266 1267 /* Output is not interrupt driven */ 1268 1269 spin_lock_irqsave (&hmidi->lock, flags); 1270 if (hmidi->output) { 1271 if (!snd_rawmidi_transmit_empty (hmidi->output)) { 1272 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) { 1273 if (n_pending > (int)sizeof (buf)) 1274 n_pending = sizeof (buf); 1275 1276 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) { 1277 for (i = 0; i < to_write; ++i) 1278 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]); 1279 } 1280 } 1281 } 1282 } 1283 spin_unlock_irqrestore (&hmidi->lock, flags); 1284 return 0; 1285 } 1286 1287 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi) 1288 { 1289 unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */ 1290 unsigned long flags; 1291 int n_pending; 1292 int i; 1293 1294 spin_lock_irqsave (&hmidi->lock, flags); 1295 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) { 1296 if (hmidi->input) { 1297 if (n_pending > (int)sizeof (buf)) 1298 n_pending = sizeof (buf); 1299 for (i = 0; i < n_pending; ++i) 1300 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1301 if (n_pending) 1302 snd_rawmidi_receive (hmidi->input, buf, n_pending); 1303 } else { 1304 /* flush the MIDI input FIFO */ 1305 while (--n_pending) 1306 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id); 1307 } 1308 } 1309 hmidi->pending = 0; 1310 if (hmidi->id) 1311 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable; 1312 else 1313 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable; 1314 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register); 1315 spin_unlock_irqrestore (&hmidi->lock, flags); 1316 return snd_hdsp_midi_output_write (hmidi); 1317 } 1318 1319 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up) 1320 { 1321 struct hdsp *hdsp; 1322 struct hdsp_midi *hmidi; 1323 unsigned long flags; 1324 u32 ie; 1325 1326 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1327 hdsp = hmidi->hdsp; 1328 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable; 1329 spin_lock_irqsave (&hdsp->lock, flags); 1330 if (up) { 1331 if (!(hdsp->control_register & ie)) { 1332 snd_hdsp_flush_midi_input (hdsp, hmidi->id); 1333 hdsp->control_register |= ie; 1334 } 1335 } else { 1336 hdsp->control_register &= ~ie; 1337 tasklet_kill(&hdsp->midi_tasklet); 1338 } 1339 1340 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1341 spin_unlock_irqrestore (&hdsp->lock, flags); 1342 } 1343 1344 static void snd_hdsp_midi_output_timer(unsigned long data) 1345 { 1346 struct hdsp_midi *hmidi = (struct hdsp_midi *) data; 1347 unsigned long flags; 1348 1349 snd_hdsp_midi_output_write(hmidi); 1350 spin_lock_irqsave (&hmidi->lock, flags); 1351 1352 /* this does not bump hmidi->istimer, because the 1353 kernel automatically removed the timer when it 1354 expired, and we are now adding it back, thus 1355 leaving istimer wherever it was set before. 1356 */ 1357 1358 if (hmidi->istimer) { 1359 hmidi->timer.expires = 1 + jiffies; 1360 add_timer(&hmidi->timer); 1361 } 1362 1363 spin_unlock_irqrestore (&hmidi->lock, flags); 1364 } 1365 1366 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) 1367 { 1368 struct hdsp_midi *hmidi; 1369 unsigned long flags; 1370 1371 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1372 spin_lock_irqsave (&hmidi->lock, flags); 1373 if (up) { 1374 if (!hmidi->istimer) { 1375 init_timer(&hmidi->timer); 1376 hmidi->timer.function = snd_hdsp_midi_output_timer; 1377 hmidi->timer.data = (unsigned long) hmidi; 1378 hmidi->timer.expires = 1 + jiffies; 1379 add_timer(&hmidi->timer); 1380 hmidi->istimer++; 1381 } 1382 } else { 1383 if (hmidi->istimer && --hmidi->istimer <= 0) 1384 del_timer (&hmidi->timer); 1385 } 1386 spin_unlock_irqrestore (&hmidi->lock, flags); 1387 if (up) 1388 snd_hdsp_midi_output_write(hmidi); 1389 } 1390 1391 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream) 1392 { 1393 struct hdsp_midi *hmidi; 1394 1395 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1396 spin_lock_irq (&hmidi->lock); 1397 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id); 1398 hmidi->input = substream; 1399 spin_unlock_irq (&hmidi->lock); 1400 1401 return 0; 1402 } 1403 1404 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream) 1405 { 1406 struct hdsp_midi *hmidi; 1407 1408 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1409 spin_lock_irq (&hmidi->lock); 1410 hmidi->output = substream; 1411 spin_unlock_irq (&hmidi->lock); 1412 1413 return 0; 1414 } 1415 1416 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream) 1417 { 1418 struct hdsp_midi *hmidi; 1419 1420 snd_hdsp_midi_input_trigger (substream, 0); 1421 1422 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1423 spin_lock_irq (&hmidi->lock); 1424 hmidi->input = NULL; 1425 spin_unlock_irq (&hmidi->lock); 1426 1427 return 0; 1428 } 1429 1430 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream) 1431 { 1432 struct hdsp_midi *hmidi; 1433 1434 snd_hdsp_midi_output_trigger (substream, 0); 1435 1436 hmidi = (struct hdsp_midi *) substream->rmidi->private_data; 1437 spin_lock_irq (&hmidi->lock); 1438 hmidi->output = NULL; 1439 spin_unlock_irq (&hmidi->lock); 1440 1441 return 0; 1442 } 1443 1444 static struct snd_rawmidi_ops snd_hdsp_midi_output = 1445 { 1446 .open = snd_hdsp_midi_output_open, 1447 .close = snd_hdsp_midi_output_close, 1448 .trigger = snd_hdsp_midi_output_trigger, 1449 }; 1450 1451 static struct snd_rawmidi_ops snd_hdsp_midi_input = 1452 { 1453 .open = snd_hdsp_midi_input_open, 1454 .close = snd_hdsp_midi_input_close, 1455 .trigger = snd_hdsp_midi_input_trigger, 1456 }; 1457 1458 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id) 1459 { 1460 char buf[32]; 1461 1462 hdsp->midi[id].id = id; 1463 hdsp->midi[id].rmidi = NULL; 1464 hdsp->midi[id].input = NULL; 1465 hdsp->midi[id].output = NULL; 1466 hdsp->midi[id].hdsp = hdsp; 1467 hdsp->midi[id].istimer = 0; 1468 hdsp->midi[id].pending = 0; 1469 spin_lock_init (&hdsp->midi[id].lock); 1470 1471 sprintf (buf, "%s MIDI %d", card->shortname, id+1); 1472 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0) 1473 return -1; 1474 1475 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1); 1476 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id]; 1477 1478 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output); 1479 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input); 1480 1481 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | 1482 SNDRV_RAWMIDI_INFO_INPUT | 1483 SNDRV_RAWMIDI_INFO_DUPLEX; 1484 1485 return 0; 1486 } 1487 1488 /*----------------------------------------------------------------------------- 1489 Control Interface 1490 ----------------------------------------------------------------------------*/ 1491 1492 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes) 1493 { 1494 u32 val = 0; 1495 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0; 1496 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0; 1497 if (val & HDSP_SPDIFProfessional) 1498 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1499 else 1500 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0; 1501 return val; 1502 } 1503 1504 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 1505 { 1506 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) | 1507 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0); 1508 if (val & HDSP_SPDIFProfessional) 1509 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1510 else 1511 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1512 } 1513 1514 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1515 { 1516 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1517 uinfo->count = 1; 1518 return 0; 1519 } 1520 1521 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1522 { 1523 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1524 1525 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif); 1526 return 0; 1527 } 1528 1529 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1530 { 1531 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1532 int change; 1533 u32 val; 1534 1535 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1536 spin_lock_irq(&hdsp->lock); 1537 change = val != hdsp->creg_spdif; 1538 hdsp->creg_spdif = val; 1539 spin_unlock_irq(&hdsp->lock); 1540 return change; 1541 } 1542 1543 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1544 { 1545 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1546 uinfo->count = 1; 1547 return 0; 1548 } 1549 1550 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1551 { 1552 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1553 1554 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream); 1555 return 0; 1556 } 1557 1558 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1559 { 1560 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1561 int change; 1562 u32 val; 1563 1564 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958); 1565 spin_lock_irq(&hdsp->lock); 1566 change = val != hdsp->creg_spdif_stream; 1567 hdsp->creg_spdif_stream = val; 1568 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 1569 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val); 1570 spin_unlock_irq(&hdsp->lock); 1571 return change; 1572 } 1573 1574 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1575 { 1576 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1577 uinfo->count = 1; 1578 return 0; 1579 } 1580 1581 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1582 { 1583 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1584 return 0; 1585 } 1586 1587 #define HDSP_SPDIF_IN(xname, xindex) \ 1588 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1589 .name = xname, \ 1590 .index = xindex, \ 1591 .info = snd_hdsp_info_spdif_in, \ 1592 .get = snd_hdsp_get_spdif_in, \ 1593 .put = snd_hdsp_put_spdif_in } 1594 1595 static unsigned int hdsp_spdif_in(struct hdsp *hdsp) 1596 { 1597 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask); 1598 } 1599 1600 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in) 1601 { 1602 hdsp->control_register &= ~HDSP_SPDIFInputMask; 1603 hdsp->control_register |= hdsp_encode_spdif_in(in); 1604 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1605 return 0; 1606 } 1607 1608 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1609 { 1610 static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"}; 1611 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1612 1613 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1614 uinfo->count = 1; 1615 uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3); 1616 if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2)) 1617 uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2); 1618 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1619 return 0; 1620 } 1621 1622 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1623 { 1624 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1625 1626 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp); 1627 return 0; 1628 } 1629 1630 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1631 { 1632 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1633 int change; 1634 unsigned int val; 1635 1636 if (!snd_hdsp_use_is_exclusive(hdsp)) 1637 return -EBUSY; 1638 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3); 1639 spin_lock_irq(&hdsp->lock); 1640 change = val != hdsp_spdif_in(hdsp); 1641 if (change) 1642 hdsp_set_spdif_input(hdsp, val); 1643 spin_unlock_irq(&hdsp->lock); 1644 return change; 1645 } 1646 1647 #define HDSP_SPDIF_OUT(xname, xindex) \ 1648 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1649 .info = snd_hdsp_info_spdif_bits, \ 1650 .get = snd_hdsp_get_spdif_out, .put = snd_hdsp_put_spdif_out } 1651 1652 static int hdsp_spdif_out(struct hdsp *hdsp) 1653 { 1654 return (hdsp->control_register & HDSP_SPDIFOpticalOut) ? 1 : 0; 1655 } 1656 1657 static int hdsp_set_spdif_output(struct hdsp *hdsp, int out) 1658 { 1659 if (out) 1660 hdsp->control_register |= HDSP_SPDIFOpticalOut; 1661 else 1662 hdsp->control_register &= ~HDSP_SPDIFOpticalOut; 1663 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1664 return 0; 1665 } 1666 1667 #define snd_hdsp_info_spdif_bits snd_ctl_boolean_mono_info 1668 1669 static int snd_hdsp_get_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1670 { 1671 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1672 1673 ucontrol->value.integer.value[0] = hdsp_spdif_out(hdsp); 1674 return 0; 1675 } 1676 1677 static int snd_hdsp_put_spdif_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1678 { 1679 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1680 int change; 1681 unsigned int val; 1682 1683 if (!snd_hdsp_use_is_exclusive(hdsp)) 1684 return -EBUSY; 1685 val = ucontrol->value.integer.value[0] & 1; 1686 spin_lock_irq(&hdsp->lock); 1687 change = (int)val != hdsp_spdif_out(hdsp); 1688 hdsp_set_spdif_output(hdsp, val); 1689 spin_unlock_irq(&hdsp->lock); 1690 return change; 1691 } 1692 1693 #define HDSP_SPDIF_PROFESSIONAL(xname, xindex) \ 1694 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1695 .info = snd_hdsp_info_spdif_bits, \ 1696 .get = snd_hdsp_get_spdif_professional, .put = snd_hdsp_put_spdif_professional } 1697 1698 static int hdsp_spdif_professional(struct hdsp *hdsp) 1699 { 1700 return (hdsp->control_register & HDSP_SPDIFProfessional) ? 1 : 0; 1701 } 1702 1703 static int hdsp_set_spdif_professional(struct hdsp *hdsp, int val) 1704 { 1705 if (val) 1706 hdsp->control_register |= HDSP_SPDIFProfessional; 1707 else 1708 hdsp->control_register &= ~HDSP_SPDIFProfessional; 1709 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1710 return 0; 1711 } 1712 1713 static int snd_hdsp_get_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1714 { 1715 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1716 1717 ucontrol->value.integer.value[0] = hdsp_spdif_professional(hdsp); 1718 return 0; 1719 } 1720 1721 static int snd_hdsp_put_spdif_professional(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1722 { 1723 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1724 int change; 1725 unsigned int val; 1726 1727 if (!snd_hdsp_use_is_exclusive(hdsp)) 1728 return -EBUSY; 1729 val = ucontrol->value.integer.value[0] & 1; 1730 spin_lock_irq(&hdsp->lock); 1731 change = (int)val != hdsp_spdif_professional(hdsp); 1732 hdsp_set_spdif_professional(hdsp, val); 1733 spin_unlock_irq(&hdsp->lock); 1734 return change; 1735 } 1736 1737 #define HDSP_SPDIF_EMPHASIS(xname, xindex) \ 1738 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1739 .info = snd_hdsp_info_spdif_bits, \ 1740 .get = snd_hdsp_get_spdif_emphasis, .put = snd_hdsp_put_spdif_emphasis } 1741 1742 static int hdsp_spdif_emphasis(struct hdsp *hdsp) 1743 { 1744 return (hdsp->control_register & HDSP_SPDIFEmphasis) ? 1 : 0; 1745 } 1746 1747 static int hdsp_set_spdif_emphasis(struct hdsp *hdsp, int val) 1748 { 1749 if (val) 1750 hdsp->control_register |= HDSP_SPDIFEmphasis; 1751 else 1752 hdsp->control_register &= ~HDSP_SPDIFEmphasis; 1753 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1754 return 0; 1755 } 1756 1757 static int snd_hdsp_get_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1758 { 1759 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1760 1761 ucontrol->value.integer.value[0] = hdsp_spdif_emphasis(hdsp); 1762 return 0; 1763 } 1764 1765 static int snd_hdsp_put_spdif_emphasis(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1766 { 1767 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1768 int change; 1769 unsigned int val; 1770 1771 if (!snd_hdsp_use_is_exclusive(hdsp)) 1772 return -EBUSY; 1773 val = ucontrol->value.integer.value[0] & 1; 1774 spin_lock_irq(&hdsp->lock); 1775 change = (int)val != hdsp_spdif_emphasis(hdsp); 1776 hdsp_set_spdif_emphasis(hdsp, val); 1777 spin_unlock_irq(&hdsp->lock); 1778 return change; 1779 } 1780 1781 #define HDSP_SPDIF_NON_AUDIO(xname, xindex) \ 1782 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \ 1783 .info = snd_hdsp_info_spdif_bits, \ 1784 .get = snd_hdsp_get_spdif_nonaudio, .put = snd_hdsp_put_spdif_nonaudio } 1785 1786 static int hdsp_spdif_nonaudio(struct hdsp *hdsp) 1787 { 1788 return (hdsp->control_register & HDSP_SPDIFNonAudio) ? 1 : 0; 1789 } 1790 1791 static int hdsp_set_spdif_nonaudio(struct hdsp *hdsp, int val) 1792 { 1793 if (val) 1794 hdsp->control_register |= HDSP_SPDIFNonAudio; 1795 else 1796 hdsp->control_register &= ~HDSP_SPDIFNonAudio; 1797 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 1798 return 0; 1799 } 1800 1801 static int snd_hdsp_get_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1802 { 1803 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1804 1805 ucontrol->value.integer.value[0] = hdsp_spdif_nonaudio(hdsp); 1806 return 0; 1807 } 1808 1809 static int snd_hdsp_put_spdif_nonaudio(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1810 { 1811 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1812 int change; 1813 unsigned int val; 1814 1815 if (!snd_hdsp_use_is_exclusive(hdsp)) 1816 return -EBUSY; 1817 val = ucontrol->value.integer.value[0] & 1; 1818 spin_lock_irq(&hdsp->lock); 1819 change = (int)val != hdsp_spdif_nonaudio(hdsp); 1820 hdsp_set_spdif_nonaudio(hdsp, val); 1821 spin_unlock_irq(&hdsp->lock); 1822 return change; 1823 } 1824 1825 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \ 1826 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1827 .name = xname, \ 1828 .index = xindex, \ 1829 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1830 .info = snd_hdsp_info_spdif_sample_rate, \ 1831 .get = snd_hdsp_get_spdif_sample_rate \ 1832 } 1833 1834 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1835 { 1836 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1837 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1838 1839 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1840 uinfo->count = 1; 1841 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7; 1842 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1843 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1844 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1845 return 0; 1846 } 1847 1848 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1849 { 1850 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1851 1852 switch (hdsp_spdif_sample_rate(hdsp)) { 1853 case 32000: 1854 ucontrol->value.enumerated.item[0] = 0; 1855 break; 1856 case 44100: 1857 ucontrol->value.enumerated.item[0] = 1; 1858 break; 1859 case 48000: 1860 ucontrol->value.enumerated.item[0] = 2; 1861 break; 1862 case 64000: 1863 ucontrol->value.enumerated.item[0] = 3; 1864 break; 1865 case 88200: 1866 ucontrol->value.enumerated.item[0] = 4; 1867 break; 1868 case 96000: 1869 ucontrol->value.enumerated.item[0] = 5; 1870 break; 1871 case 128000: 1872 ucontrol->value.enumerated.item[0] = 7; 1873 break; 1874 case 176400: 1875 ucontrol->value.enumerated.item[0] = 8; 1876 break; 1877 case 192000: 1878 ucontrol->value.enumerated.item[0] = 9; 1879 break; 1880 default: 1881 ucontrol->value.enumerated.item[0] = 6; 1882 } 1883 return 0; 1884 } 1885 1886 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \ 1887 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1888 .name = xname, \ 1889 .index = xindex, \ 1890 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1891 .info = snd_hdsp_info_system_sample_rate, \ 1892 .get = snd_hdsp_get_system_sample_rate \ 1893 } 1894 1895 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1896 { 1897 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1898 uinfo->count = 1; 1899 return 0; 1900 } 1901 1902 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1903 { 1904 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1905 1906 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate; 1907 return 0; 1908 } 1909 1910 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \ 1911 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1912 .name = xname, \ 1913 .index = xindex, \ 1914 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1915 .info = snd_hdsp_info_autosync_sample_rate, \ 1916 .get = snd_hdsp_get_autosync_sample_rate \ 1917 } 1918 1919 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1920 { 1921 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1922 static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"}; 1923 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1924 uinfo->count = 1; 1925 uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ; 1926 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1927 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1928 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1929 return 0; 1930 } 1931 1932 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1933 { 1934 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 1935 1936 switch (hdsp_external_sample_rate(hdsp)) { 1937 case 32000: 1938 ucontrol->value.enumerated.item[0] = 0; 1939 break; 1940 case 44100: 1941 ucontrol->value.enumerated.item[0] = 1; 1942 break; 1943 case 48000: 1944 ucontrol->value.enumerated.item[0] = 2; 1945 break; 1946 case 64000: 1947 ucontrol->value.enumerated.item[0] = 3; 1948 break; 1949 case 88200: 1950 ucontrol->value.enumerated.item[0] = 4; 1951 break; 1952 case 96000: 1953 ucontrol->value.enumerated.item[0] = 5; 1954 break; 1955 case 128000: 1956 ucontrol->value.enumerated.item[0] = 7; 1957 break; 1958 case 176400: 1959 ucontrol->value.enumerated.item[0] = 8; 1960 break; 1961 case 192000: 1962 ucontrol->value.enumerated.item[0] = 9; 1963 break; 1964 default: 1965 ucontrol->value.enumerated.item[0] = 6; 1966 } 1967 return 0; 1968 } 1969 1970 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \ 1971 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 1972 .name = xname, \ 1973 .index = xindex, \ 1974 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 1975 .info = snd_hdsp_info_system_clock_mode, \ 1976 .get = snd_hdsp_get_system_clock_mode \ 1977 } 1978 1979 static int hdsp_system_clock_mode(struct hdsp *hdsp) 1980 { 1981 if (hdsp->control_register & HDSP_ClockModeMaster) 1982 return 0; 1983 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate) 1984 return 0; 1985 return 1; 1986 } 1987 1988 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1989 { 1990 static char *texts[] = {"Master", "Slave" }; 1991 1992 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1993 uinfo->count = 1; 1994 uinfo->value.enumerated.items = 2; 1995 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 1996 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1997 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1998 return 0; 1999 } 2000 2001 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2002 { 2003 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2004 2005 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp); 2006 return 0; 2007 } 2008 2009 #define HDSP_CLOCK_SOURCE(xname, xindex) \ 2010 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2011 .name = xname, \ 2012 .index = xindex, \ 2013 .info = snd_hdsp_info_clock_source, \ 2014 .get = snd_hdsp_get_clock_source, \ 2015 .put = snd_hdsp_put_clock_source \ 2016 } 2017 2018 static int hdsp_clock_source(struct hdsp *hdsp) 2019 { 2020 if (hdsp->control_register & HDSP_ClockModeMaster) { 2021 switch (hdsp->system_sample_rate) { 2022 case 32000: 2023 return 1; 2024 case 44100: 2025 return 2; 2026 case 48000: 2027 return 3; 2028 case 64000: 2029 return 4; 2030 case 88200: 2031 return 5; 2032 case 96000: 2033 return 6; 2034 case 128000: 2035 return 7; 2036 case 176400: 2037 return 8; 2038 case 192000: 2039 return 9; 2040 default: 2041 return 3; 2042 } 2043 } else { 2044 return 0; 2045 } 2046 } 2047 2048 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode) 2049 { 2050 int rate; 2051 switch (mode) { 2052 case HDSP_CLOCK_SOURCE_AUTOSYNC: 2053 if (hdsp_external_sample_rate(hdsp) != 0) { 2054 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) { 2055 hdsp->control_register &= ~HDSP_ClockModeMaster; 2056 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2057 return 0; 2058 } 2059 } 2060 return -1; 2061 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 2062 rate = 32000; 2063 break; 2064 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 2065 rate = 44100; 2066 break; 2067 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 2068 rate = 48000; 2069 break; 2070 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 2071 rate = 64000; 2072 break; 2073 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 2074 rate = 88200; 2075 break; 2076 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 2077 rate = 96000; 2078 break; 2079 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 2080 rate = 128000; 2081 break; 2082 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 2083 rate = 176400; 2084 break; 2085 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 2086 rate = 192000; 2087 break; 2088 default: 2089 rate = 48000; 2090 } 2091 hdsp->control_register |= HDSP_ClockModeMaster; 2092 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2093 hdsp_set_rate(hdsp, rate, 1); 2094 return 0; 2095 } 2096 2097 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2098 { 2099 static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" }; 2100 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2101 2102 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2103 uinfo->count = 1; 2104 if (hdsp->io_type == H9632) 2105 uinfo->value.enumerated.items = 10; 2106 else 2107 uinfo->value.enumerated.items = 7; 2108 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2109 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2110 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2111 return 0; 2112 } 2113 2114 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2115 { 2116 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2117 2118 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp); 2119 return 0; 2120 } 2121 2122 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2123 { 2124 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2125 int change; 2126 int val; 2127 2128 if (!snd_hdsp_use_is_exclusive(hdsp)) 2129 return -EBUSY; 2130 val = ucontrol->value.enumerated.item[0]; 2131 if (val < 0) val = 0; 2132 if (hdsp->io_type == H9632) { 2133 if (val > 9) 2134 val = 9; 2135 } else { 2136 if (val > 6) 2137 val = 6; 2138 } 2139 spin_lock_irq(&hdsp->lock); 2140 if (val != hdsp_clock_source(hdsp)) 2141 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0; 2142 else 2143 change = 0; 2144 spin_unlock_irq(&hdsp->lock); 2145 return change; 2146 } 2147 2148 #define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info 2149 2150 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2151 { 2152 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2153 2154 ucontrol->value.integer.value[0] = hdsp->clock_source_locked; 2155 return 0; 2156 } 2157 2158 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2159 { 2160 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2161 int change; 2162 2163 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked; 2164 if (change) 2165 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0]; 2166 return change; 2167 } 2168 2169 #define HDSP_DA_GAIN(xname, xindex) \ 2170 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2171 .name = xname, \ 2172 .index = xindex, \ 2173 .info = snd_hdsp_info_da_gain, \ 2174 .get = snd_hdsp_get_da_gain, \ 2175 .put = snd_hdsp_put_da_gain \ 2176 } 2177 2178 static int hdsp_da_gain(struct hdsp *hdsp) 2179 { 2180 switch (hdsp->control_register & HDSP_DAGainMask) { 2181 case HDSP_DAGainHighGain: 2182 return 0; 2183 case HDSP_DAGainPlus4dBu: 2184 return 1; 2185 case HDSP_DAGainMinus10dBV: 2186 return 2; 2187 default: 2188 return 1; 2189 } 2190 } 2191 2192 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode) 2193 { 2194 hdsp->control_register &= ~HDSP_DAGainMask; 2195 switch (mode) { 2196 case 0: 2197 hdsp->control_register |= HDSP_DAGainHighGain; 2198 break; 2199 case 1: 2200 hdsp->control_register |= HDSP_DAGainPlus4dBu; 2201 break; 2202 case 2: 2203 hdsp->control_register |= HDSP_DAGainMinus10dBV; 2204 break; 2205 default: 2206 return -1; 2207 2208 } 2209 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2210 return 0; 2211 } 2212 2213 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2214 { 2215 static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"}; 2216 2217 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2218 uinfo->count = 1; 2219 uinfo->value.enumerated.items = 3; 2220 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2221 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2222 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2223 return 0; 2224 } 2225 2226 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2227 { 2228 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2229 2230 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp); 2231 return 0; 2232 } 2233 2234 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2235 { 2236 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2237 int change; 2238 int val; 2239 2240 if (!snd_hdsp_use_is_exclusive(hdsp)) 2241 return -EBUSY; 2242 val = ucontrol->value.enumerated.item[0]; 2243 if (val < 0) val = 0; 2244 if (val > 2) val = 2; 2245 spin_lock_irq(&hdsp->lock); 2246 if (val != hdsp_da_gain(hdsp)) 2247 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0; 2248 else 2249 change = 0; 2250 spin_unlock_irq(&hdsp->lock); 2251 return change; 2252 } 2253 2254 #define HDSP_AD_GAIN(xname, xindex) \ 2255 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2256 .name = xname, \ 2257 .index = xindex, \ 2258 .info = snd_hdsp_info_ad_gain, \ 2259 .get = snd_hdsp_get_ad_gain, \ 2260 .put = snd_hdsp_put_ad_gain \ 2261 } 2262 2263 static int hdsp_ad_gain(struct hdsp *hdsp) 2264 { 2265 switch (hdsp->control_register & HDSP_ADGainMask) { 2266 case HDSP_ADGainMinus10dBV: 2267 return 0; 2268 case HDSP_ADGainPlus4dBu: 2269 return 1; 2270 case HDSP_ADGainLowGain: 2271 return 2; 2272 default: 2273 return 1; 2274 } 2275 } 2276 2277 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode) 2278 { 2279 hdsp->control_register &= ~HDSP_ADGainMask; 2280 switch (mode) { 2281 case 0: 2282 hdsp->control_register |= HDSP_ADGainMinus10dBV; 2283 break; 2284 case 1: 2285 hdsp->control_register |= HDSP_ADGainPlus4dBu; 2286 break; 2287 case 2: 2288 hdsp->control_register |= HDSP_ADGainLowGain; 2289 break; 2290 default: 2291 return -1; 2292 2293 } 2294 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2295 return 0; 2296 } 2297 2298 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2299 { 2300 static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"}; 2301 2302 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2303 uinfo->count = 1; 2304 uinfo->value.enumerated.items = 3; 2305 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2306 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2307 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2308 return 0; 2309 } 2310 2311 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2312 { 2313 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2314 2315 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp); 2316 return 0; 2317 } 2318 2319 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2320 { 2321 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2322 int change; 2323 int val; 2324 2325 if (!snd_hdsp_use_is_exclusive(hdsp)) 2326 return -EBUSY; 2327 val = ucontrol->value.enumerated.item[0]; 2328 if (val < 0) val = 0; 2329 if (val > 2) val = 2; 2330 spin_lock_irq(&hdsp->lock); 2331 if (val != hdsp_ad_gain(hdsp)) 2332 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0; 2333 else 2334 change = 0; 2335 spin_unlock_irq(&hdsp->lock); 2336 return change; 2337 } 2338 2339 #define HDSP_PHONE_GAIN(xname, xindex) \ 2340 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2341 .name = xname, \ 2342 .index = xindex, \ 2343 .info = snd_hdsp_info_phone_gain, \ 2344 .get = snd_hdsp_get_phone_gain, \ 2345 .put = snd_hdsp_put_phone_gain \ 2346 } 2347 2348 static int hdsp_phone_gain(struct hdsp *hdsp) 2349 { 2350 switch (hdsp->control_register & HDSP_PhoneGainMask) { 2351 case HDSP_PhoneGain0dB: 2352 return 0; 2353 case HDSP_PhoneGainMinus6dB: 2354 return 1; 2355 case HDSP_PhoneGainMinus12dB: 2356 return 2; 2357 default: 2358 return 0; 2359 } 2360 } 2361 2362 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode) 2363 { 2364 hdsp->control_register &= ~HDSP_PhoneGainMask; 2365 switch (mode) { 2366 case 0: 2367 hdsp->control_register |= HDSP_PhoneGain0dB; 2368 break; 2369 case 1: 2370 hdsp->control_register |= HDSP_PhoneGainMinus6dB; 2371 break; 2372 case 2: 2373 hdsp->control_register |= HDSP_PhoneGainMinus12dB; 2374 break; 2375 default: 2376 return -1; 2377 2378 } 2379 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2380 return 0; 2381 } 2382 2383 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2384 { 2385 static char *texts[] = {"0 dB", "-6 dB", "-12 dB"}; 2386 2387 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2388 uinfo->count = 1; 2389 uinfo->value.enumerated.items = 3; 2390 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2391 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2392 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2393 return 0; 2394 } 2395 2396 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2397 { 2398 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2399 2400 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp); 2401 return 0; 2402 } 2403 2404 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2405 { 2406 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2407 int change; 2408 int val; 2409 2410 if (!snd_hdsp_use_is_exclusive(hdsp)) 2411 return -EBUSY; 2412 val = ucontrol->value.enumerated.item[0]; 2413 if (val < 0) val = 0; 2414 if (val > 2) val = 2; 2415 spin_lock_irq(&hdsp->lock); 2416 if (val != hdsp_phone_gain(hdsp)) 2417 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0; 2418 else 2419 change = 0; 2420 spin_unlock_irq(&hdsp->lock); 2421 return change; 2422 } 2423 2424 #define HDSP_XLR_BREAKOUT_CABLE(xname, xindex) \ 2425 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2426 .name = xname, \ 2427 .index = xindex, \ 2428 .info = snd_hdsp_info_xlr_breakout_cable, \ 2429 .get = snd_hdsp_get_xlr_breakout_cable, \ 2430 .put = snd_hdsp_put_xlr_breakout_cable \ 2431 } 2432 2433 static int hdsp_xlr_breakout_cable(struct hdsp *hdsp) 2434 { 2435 if (hdsp->control_register & HDSP_XLRBreakoutCable) 2436 return 1; 2437 return 0; 2438 } 2439 2440 static int hdsp_set_xlr_breakout_cable(struct hdsp *hdsp, int mode) 2441 { 2442 if (mode) 2443 hdsp->control_register |= HDSP_XLRBreakoutCable; 2444 else 2445 hdsp->control_register &= ~HDSP_XLRBreakoutCable; 2446 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2447 return 0; 2448 } 2449 2450 #define snd_hdsp_info_xlr_breakout_cable snd_ctl_boolean_mono_info 2451 2452 static int snd_hdsp_get_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2453 { 2454 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2455 2456 ucontrol->value.enumerated.item[0] = hdsp_xlr_breakout_cable(hdsp); 2457 return 0; 2458 } 2459 2460 static int snd_hdsp_put_xlr_breakout_cable(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2461 { 2462 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2463 int change; 2464 int val; 2465 2466 if (!snd_hdsp_use_is_exclusive(hdsp)) 2467 return -EBUSY; 2468 val = ucontrol->value.integer.value[0] & 1; 2469 spin_lock_irq(&hdsp->lock); 2470 change = (int)val != hdsp_xlr_breakout_cable(hdsp); 2471 hdsp_set_xlr_breakout_cable(hdsp, val); 2472 spin_unlock_irq(&hdsp->lock); 2473 return change; 2474 } 2475 2476 /* (De)activates old RME Analog Extension Board 2477 These are connected to the internal ADAT connector 2478 Switching this on desactivates external ADAT 2479 */ 2480 #define HDSP_AEB(xname, xindex) \ 2481 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2482 .name = xname, \ 2483 .index = xindex, \ 2484 .info = snd_hdsp_info_aeb, \ 2485 .get = snd_hdsp_get_aeb, \ 2486 .put = snd_hdsp_put_aeb \ 2487 } 2488 2489 static int hdsp_aeb(struct hdsp *hdsp) 2490 { 2491 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 2492 return 1; 2493 return 0; 2494 } 2495 2496 static int hdsp_set_aeb(struct hdsp *hdsp, int mode) 2497 { 2498 if (mode) 2499 hdsp->control_register |= HDSP_AnalogExtensionBoard; 2500 else 2501 hdsp->control_register &= ~HDSP_AnalogExtensionBoard; 2502 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2503 return 0; 2504 } 2505 2506 #define snd_hdsp_info_aeb snd_ctl_boolean_mono_info 2507 2508 static int snd_hdsp_get_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2509 { 2510 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2511 2512 ucontrol->value.enumerated.item[0] = hdsp_aeb(hdsp); 2513 return 0; 2514 } 2515 2516 static int snd_hdsp_put_aeb(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2517 { 2518 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2519 int change; 2520 int val; 2521 2522 if (!snd_hdsp_use_is_exclusive(hdsp)) 2523 return -EBUSY; 2524 val = ucontrol->value.integer.value[0] & 1; 2525 spin_lock_irq(&hdsp->lock); 2526 change = (int)val != hdsp_aeb(hdsp); 2527 hdsp_set_aeb(hdsp, val); 2528 spin_unlock_irq(&hdsp->lock); 2529 return change; 2530 } 2531 2532 #define HDSP_PREF_SYNC_REF(xname, xindex) \ 2533 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2534 .name = xname, \ 2535 .index = xindex, \ 2536 .info = snd_hdsp_info_pref_sync_ref, \ 2537 .get = snd_hdsp_get_pref_sync_ref, \ 2538 .put = snd_hdsp_put_pref_sync_ref \ 2539 } 2540 2541 static int hdsp_pref_sync_ref(struct hdsp *hdsp) 2542 { 2543 /* Notice that this looks at the requested sync source, 2544 not the one actually in use. 2545 */ 2546 2547 switch (hdsp->control_register & HDSP_SyncRefMask) { 2548 case HDSP_SyncRef_ADAT1: 2549 return HDSP_SYNC_FROM_ADAT1; 2550 case HDSP_SyncRef_ADAT2: 2551 return HDSP_SYNC_FROM_ADAT2; 2552 case HDSP_SyncRef_ADAT3: 2553 return HDSP_SYNC_FROM_ADAT3; 2554 case HDSP_SyncRef_SPDIF: 2555 return HDSP_SYNC_FROM_SPDIF; 2556 case HDSP_SyncRef_WORD: 2557 return HDSP_SYNC_FROM_WORD; 2558 case HDSP_SyncRef_ADAT_SYNC: 2559 return HDSP_SYNC_FROM_ADAT_SYNC; 2560 default: 2561 return HDSP_SYNC_FROM_WORD; 2562 } 2563 return 0; 2564 } 2565 2566 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref) 2567 { 2568 hdsp->control_register &= ~HDSP_SyncRefMask; 2569 switch (pref) { 2570 case HDSP_SYNC_FROM_ADAT1: 2571 hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */ 2572 break; 2573 case HDSP_SYNC_FROM_ADAT2: 2574 hdsp->control_register |= HDSP_SyncRef_ADAT2; 2575 break; 2576 case HDSP_SYNC_FROM_ADAT3: 2577 hdsp->control_register |= HDSP_SyncRef_ADAT3; 2578 break; 2579 case HDSP_SYNC_FROM_SPDIF: 2580 hdsp->control_register |= HDSP_SyncRef_SPDIF; 2581 break; 2582 case HDSP_SYNC_FROM_WORD: 2583 hdsp->control_register |= HDSP_SyncRef_WORD; 2584 break; 2585 case HDSP_SYNC_FROM_ADAT_SYNC: 2586 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC; 2587 break; 2588 default: 2589 return -1; 2590 } 2591 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2592 return 0; 2593 } 2594 2595 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2596 { 2597 static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" }; 2598 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2599 2600 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2601 uinfo->count = 1; 2602 2603 switch (hdsp->io_type) { 2604 case Digiface: 2605 case H9652: 2606 uinfo->value.enumerated.items = 6; 2607 break; 2608 case Multiface: 2609 uinfo->value.enumerated.items = 4; 2610 break; 2611 case H9632: 2612 uinfo->value.enumerated.items = 3; 2613 break; 2614 default: 2615 uinfo->value.enumerated.items = 0; 2616 break; 2617 } 2618 2619 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2620 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2621 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2622 return 0; 2623 } 2624 2625 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2626 { 2627 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2628 2629 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp); 2630 return 0; 2631 } 2632 2633 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2634 { 2635 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2636 int change, max; 2637 unsigned int val; 2638 2639 if (!snd_hdsp_use_is_exclusive(hdsp)) 2640 return -EBUSY; 2641 2642 switch (hdsp->io_type) { 2643 case Digiface: 2644 case H9652: 2645 max = 6; 2646 break; 2647 case Multiface: 2648 max = 4; 2649 break; 2650 case H9632: 2651 max = 3; 2652 break; 2653 default: 2654 return -EIO; 2655 } 2656 2657 val = ucontrol->value.enumerated.item[0] % max; 2658 spin_lock_irq(&hdsp->lock); 2659 change = (int)val != hdsp_pref_sync_ref(hdsp); 2660 hdsp_set_pref_sync_ref(hdsp, val); 2661 spin_unlock_irq(&hdsp->lock); 2662 return change; 2663 } 2664 2665 #define HDSP_AUTOSYNC_REF(xname, xindex) \ 2666 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2667 .name = xname, \ 2668 .index = xindex, \ 2669 .access = SNDRV_CTL_ELEM_ACCESS_READ, \ 2670 .info = snd_hdsp_info_autosync_ref, \ 2671 .get = snd_hdsp_get_autosync_ref, \ 2672 } 2673 2674 static int hdsp_autosync_ref(struct hdsp *hdsp) 2675 { 2676 /* This looks at the autosync selected sync reference */ 2677 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register); 2678 2679 switch (status2 & HDSP_SelSyncRefMask) { 2680 case HDSP_SelSyncRef_WORD: 2681 return HDSP_AUTOSYNC_FROM_WORD; 2682 case HDSP_SelSyncRef_ADAT_SYNC: 2683 return HDSP_AUTOSYNC_FROM_ADAT_SYNC; 2684 case HDSP_SelSyncRef_SPDIF: 2685 return HDSP_AUTOSYNC_FROM_SPDIF; 2686 case HDSP_SelSyncRefMask: 2687 return HDSP_AUTOSYNC_FROM_NONE; 2688 case HDSP_SelSyncRef_ADAT1: 2689 return HDSP_AUTOSYNC_FROM_ADAT1; 2690 case HDSP_SelSyncRef_ADAT2: 2691 return HDSP_AUTOSYNC_FROM_ADAT2; 2692 case HDSP_SelSyncRef_ADAT3: 2693 return HDSP_AUTOSYNC_FROM_ADAT3; 2694 default: 2695 return HDSP_AUTOSYNC_FROM_WORD; 2696 } 2697 return 0; 2698 } 2699 2700 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2701 { 2702 static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" }; 2703 2704 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2705 uinfo->count = 1; 2706 uinfo->value.enumerated.items = 7; 2707 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2708 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2709 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2710 return 0; 2711 } 2712 2713 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2714 { 2715 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2716 2717 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp); 2718 return 0; 2719 } 2720 2721 #define HDSP_LINE_OUT(xname, xindex) \ 2722 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2723 .name = xname, \ 2724 .index = xindex, \ 2725 .info = snd_hdsp_info_line_out, \ 2726 .get = snd_hdsp_get_line_out, \ 2727 .put = snd_hdsp_put_line_out \ 2728 } 2729 2730 static int hdsp_line_out(struct hdsp *hdsp) 2731 { 2732 return (hdsp->control_register & HDSP_LineOut) ? 1 : 0; 2733 } 2734 2735 static int hdsp_set_line_output(struct hdsp *hdsp, int out) 2736 { 2737 if (out) 2738 hdsp->control_register |= HDSP_LineOut; 2739 else 2740 hdsp->control_register &= ~HDSP_LineOut; 2741 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 2742 return 0; 2743 } 2744 2745 #define snd_hdsp_info_line_out snd_ctl_boolean_mono_info 2746 2747 static int snd_hdsp_get_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2748 { 2749 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2750 2751 spin_lock_irq(&hdsp->lock); 2752 ucontrol->value.integer.value[0] = hdsp_line_out(hdsp); 2753 spin_unlock_irq(&hdsp->lock); 2754 return 0; 2755 } 2756 2757 static int snd_hdsp_put_line_out(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2758 { 2759 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2760 int change; 2761 unsigned int val; 2762 2763 if (!snd_hdsp_use_is_exclusive(hdsp)) 2764 return -EBUSY; 2765 val = ucontrol->value.integer.value[0] & 1; 2766 spin_lock_irq(&hdsp->lock); 2767 change = (int)val != hdsp_line_out(hdsp); 2768 hdsp_set_line_output(hdsp, val); 2769 spin_unlock_irq(&hdsp->lock); 2770 return change; 2771 } 2772 2773 #define HDSP_PRECISE_POINTER(xname, xindex) \ 2774 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2775 .name = xname, \ 2776 .index = xindex, \ 2777 .info = snd_hdsp_info_precise_pointer, \ 2778 .get = snd_hdsp_get_precise_pointer, \ 2779 .put = snd_hdsp_put_precise_pointer \ 2780 } 2781 2782 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise) 2783 { 2784 if (precise) 2785 hdsp->precise_ptr = 1; 2786 else 2787 hdsp->precise_ptr = 0; 2788 return 0; 2789 } 2790 2791 #define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info 2792 2793 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2794 { 2795 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2796 2797 spin_lock_irq(&hdsp->lock); 2798 ucontrol->value.integer.value[0] = hdsp->precise_ptr; 2799 spin_unlock_irq(&hdsp->lock); 2800 return 0; 2801 } 2802 2803 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2804 { 2805 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2806 int change; 2807 unsigned int val; 2808 2809 if (!snd_hdsp_use_is_exclusive(hdsp)) 2810 return -EBUSY; 2811 val = ucontrol->value.integer.value[0] & 1; 2812 spin_lock_irq(&hdsp->lock); 2813 change = (int)val != hdsp->precise_ptr; 2814 hdsp_set_precise_pointer(hdsp, val); 2815 spin_unlock_irq(&hdsp->lock); 2816 return change; 2817 } 2818 2819 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \ 2820 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \ 2821 .name = xname, \ 2822 .index = xindex, \ 2823 .info = snd_hdsp_info_use_midi_tasklet, \ 2824 .get = snd_hdsp_get_use_midi_tasklet, \ 2825 .put = snd_hdsp_put_use_midi_tasklet \ 2826 } 2827 2828 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet) 2829 { 2830 if (use_tasklet) 2831 hdsp->use_midi_tasklet = 1; 2832 else 2833 hdsp->use_midi_tasklet = 0; 2834 return 0; 2835 } 2836 2837 #define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info 2838 2839 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2840 { 2841 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2842 2843 spin_lock_irq(&hdsp->lock); 2844 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet; 2845 spin_unlock_irq(&hdsp->lock); 2846 return 0; 2847 } 2848 2849 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2850 { 2851 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2852 int change; 2853 unsigned int val; 2854 2855 if (!snd_hdsp_use_is_exclusive(hdsp)) 2856 return -EBUSY; 2857 val = ucontrol->value.integer.value[0] & 1; 2858 spin_lock_irq(&hdsp->lock); 2859 change = (int)val != hdsp->use_midi_tasklet; 2860 hdsp_set_use_midi_tasklet(hdsp, val); 2861 spin_unlock_irq(&hdsp->lock); 2862 return change; 2863 } 2864 2865 #define HDSP_MIXER(xname, xindex) \ 2866 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \ 2867 .name = xname, \ 2868 .index = xindex, \ 2869 .device = 0, \ 2870 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \ 2871 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2872 .info = snd_hdsp_info_mixer, \ 2873 .get = snd_hdsp_get_mixer, \ 2874 .put = snd_hdsp_put_mixer \ 2875 } 2876 2877 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2878 { 2879 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2880 uinfo->count = 3; 2881 uinfo->value.integer.min = 0; 2882 uinfo->value.integer.max = 65536; 2883 uinfo->value.integer.step = 1; 2884 return 0; 2885 } 2886 2887 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2888 { 2889 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2890 int source; 2891 int destination; 2892 int addr; 2893 2894 source = ucontrol->value.integer.value[0]; 2895 destination = ucontrol->value.integer.value[1]; 2896 2897 if (source >= hdsp->max_channels) 2898 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination); 2899 else 2900 addr = hdsp_input_to_output_key(hdsp,source, destination); 2901 2902 spin_lock_irq(&hdsp->lock); 2903 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr); 2904 spin_unlock_irq(&hdsp->lock); 2905 return 0; 2906 } 2907 2908 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2909 { 2910 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2911 int change; 2912 int source; 2913 int destination; 2914 int gain; 2915 int addr; 2916 2917 if (!snd_hdsp_use_is_exclusive(hdsp)) 2918 return -EBUSY; 2919 2920 source = ucontrol->value.integer.value[0]; 2921 destination = ucontrol->value.integer.value[1]; 2922 2923 if (source >= hdsp->max_channels) 2924 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination); 2925 else 2926 addr = hdsp_input_to_output_key(hdsp,source, destination); 2927 2928 gain = ucontrol->value.integer.value[2]; 2929 2930 spin_lock_irq(&hdsp->lock); 2931 change = gain != hdsp_read_gain(hdsp, addr); 2932 if (change) 2933 hdsp_write_gain(hdsp, addr, gain); 2934 spin_unlock_irq(&hdsp->lock); 2935 return change; 2936 } 2937 2938 #define HDSP_WC_SYNC_CHECK(xname, xindex) \ 2939 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2940 .name = xname, \ 2941 .index = xindex, \ 2942 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2943 .info = snd_hdsp_info_sync_check, \ 2944 .get = snd_hdsp_get_wc_sync_check \ 2945 } 2946 2947 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2948 { 2949 static char *texts[] = {"No Lock", "Lock", "Sync" }; 2950 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2951 uinfo->count = 1; 2952 uinfo->value.enumerated.items = 3; 2953 if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items) 2954 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 2955 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2956 return 0; 2957 } 2958 2959 static int hdsp_wc_sync_check(struct hdsp *hdsp) 2960 { 2961 int status2 = hdsp_read(hdsp, HDSP_status2Register); 2962 if (status2 & HDSP_wc_lock) { 2963 if (status2 & HDSP_wc_sync) 2964 return 2; 2965 else 2966 return 1; 2967 } else 2968 return 0; 2969 return 0; 2970 } 2971 2972 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2973 { 2974 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 2975 2976 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp); 2977 return 0; 2978 } 2979 2980 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \ 2981 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 2982 .name = xname, \ 2983 .index = xindex, \ 2984 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 2985 .info = snd_hdsp_info_sync_check, \ 2986 .get = snd_hdsp_get_spdif_sync_check \ 2987 } 2988 2989 static int hdsp_spdif_sync_check(struct hdsp *hdsp) 2990 { 2991 int status = hdsp_read(hdsp, HDSP_statusRegister); 2992 if (status & HDSP_SPDIFErrorFlag) 2993 return 0; 2994 else { 2995 if (status & HDSP_SPDIFSync) 2996 return 2; 2997 else 2998 return 1; 2999 } 3000 return 0; 3001 } 3002 3003 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3004 { 3005 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3006 3007 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp); 3008 return 0; 3009 } 3010 3011 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \ 3012 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3013 .name = xname, \ 3014 .index = xindex, \ 3015 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3016 .info = snd_hdsp_info_sync_check, \ 3017 .get = snd_hdsp_get_adatsync_sync_check \ 3018 } 3019 3020 static int hdsp_adatsync_sync_check(struct hdsp *hdsp) 3021 { 3022 int status = hdsp_read(hdsp, HDSP_statusRegister); 3023 if (status & HDSP_TimecodeLock) { 3024 if (status & HDSP_TimecodeSync) 3025 return 2; 3026 else 3027 return 1; 3028 } else 3029 return 0; 3030 } 3031 3032 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3033 { 3034 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3035 3036 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp); 3037 return 0; 3038 } 3039 3040 #define HDSP_ADAT_SYNC_CHECK \ 3041 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3042 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ 3043 .info = snd_hdsp_info_sync_check, \ 3044 .get = snd_hdsp_get_adat_sync_check \ 3045 } 3046 3047 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx) 3048 { 3049 int status = hdsp_read(hdsp, HDSP_statusRegister); 3050 3051 if (status & (HDSP_Lock0>>idx)) { 3052 if (status & (HDSP_Sync0>>idx)) 3053 return 2; 3054 else 3055 return 1; 3056 } else 3057 return 0; 3058 } 3059 3060 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3061 { 3062 int offset; 3063 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3064 3065 offset = ucontrol->id.index - 1; 3066 snd_BUG_ON(offset < 0); 3067 3068 switch (hdsp->io_type) { 3069 case Digiface: 3070 case H9652: 3071 if (offset >= 3) 3072 return -EINVAL; 3073 break; 3074 case Multiface: 3075 case H9632: 3076 if (offset >= 1) 3077 return -EINVAL; 3078 break; 3079 default: 3080 return -EIO; 3081 } 3082 3083 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset); 3084 return 0; 3085 } 3086 3087 #define HDSP_DDS_OFFSET(xname, xindex) \ 3088 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ 3089 .name = xname, \ 3090 .index = xindex, \ 3091 .info = snd_hdsp_info_dds_offset, \ 3092 .get = snd_hdsp_get_dds_offset, \ 3093 .put = snd_hdsp_put_dds_offset \ 3094 } 3095 3096 static int hdsp_dds_offset(struct hdsp *hdsp) 3097 { 3098 u64 n; 3099 unsigned int dds_value = hdsp->dds_value; 3100 int system_sample_rate = hdsp->system_sample_rate; 3101 3102 if (!dds_value) 3103 return 0; 3104 3105 n = DDS_NUMERATOR; 3106 /* 3107 * dds_value = n / rate 3108 * rate = n / dds_value 3109 */ 3110 n = div_u64(n, dds_value); 3111 if (system_sample_rate >= 112000) 3112 n *= 4; 3113 else if (system_sample_rate >= 56000) 3114 n *= 2; 3115 return ((int)n) - system_sample_rate; 3116 } 3117 3118 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz) 3119 { 3120 int rate = hdsp->system_sample_rate + offset_hz; 3121 hdsp_set_dds_value(hdsp, rate); 3122 return 0; 3123 } 3124 3125 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 3126 { 3127 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 3128 uinfo->count = 1; 3129 uinfo->value.integer.min = -5000; 3130 uinfo->value.integer.max = 5000; 3131 return 0; 3132 } 3133 3134 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3135 { 3136 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3137 3138 ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp); 3139 return 0; 3140 } 3141 3142 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 3143 { 3144 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol); 3145 int change; 3146 int val; 3147 3148 if (!snd_hdsp_use_is_exclusive(hdsp)) 3149 return -EBUSY; 3150 val = ucontrol->value.enumerated.item[0]; 3151 spin_lock_irq(&hdsp->lock); 3152 if (val != hdsp_dds_offset(hdsp)) 3153 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0; 3154 else 3155 change = 0; 3156 spin_unlock_irq(&hdsp->lock); 3157 return change; 3158 } 3159 3160 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = { 3161 HDSP_DA_GAIN("DA Gain", 0), 3162 HDSP_AD_GAIN("AD Gain", 0), 3163 HDSP_PHONE_GAIN("Phones Gain", 0), 3164 HDSP_XLR_BREAKOUT_CABLE("XLR Breakout Cable", 0), 3165 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0) 3166 }; 3167 3168 static struct snd_kcontrol_new snd_hdsp_controls[] = { 3169 { 3170 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3171 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 3172 .info = snd_hdsp_control_spdif_info, 3173 .get = snd_hdsp_control_spdif_get, 3174 .put = snd_hdsp_control_spdif_put, 3175 }, 3176 { 3177 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 3178 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3179 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 3180 .info = snd_hdsp_control_spdif_stream_info, 3181 .get = snd_hdsp_control_spdif_stream_get, 3182 .put = snd_hdsp_control_spdif_stream_put, 3183 }, 3184 { 3185 .access = SNDRV_CTL_ELEM_ACCESS_READ, 3186 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3187 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 3188 .info = snd_hdsp_control_spdif_mask_info, 3189 .get = snd_hdsp_control_spdif_mask_get, 3190 .private_value = IEC958_AES0_NONAUDIO | 3191 IEC958_AES0_PROFESSIONAL | 3192 IEC958_AES0_CON_EMPHASIS, 3193 }, 3194 { 3195 .access = SNDRV_CTL_ELEM_ACCESS_READ, 3196 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 3197 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 3198 .info = snd_hdsp_control_spdif_mask_info, 3199 .get = snd_hdsp_control_spdif_mask_get, 3200 .private_value = IEC958_AES0_NONAUDIO | 3201 IEC958_AES0_PROFESSIONAL | 3202 IEC958_AES0_PRO_EMPHASIS, 3203 }, 3204 HDSP_MIXER("Mixer", 0), 3205 HDSP_SPDIF_IN("IEC958 Input Connector", 0), 3206 HDSP_SPDIF_OUT("IEC958 Output also on ADAT1", 0), 3207 HDSP_SPDIF_PROFESSIONAL("IEC958 Professional Bit", 0), 3208 HDSP_SPDIF_EMPHASIS("IEC958 Emphasis Bit", 0), 3209 HDSP_SPDIF_NON_AUDIO("IEC958 Non-audio Bit", 0), 3210 /* 'Sample Clock Source' complies with the alsa control naming scheme */ 3211 HDSP_CLOCK_SOURCE("Sample Clock Source", 0), 3212 { 3213 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 3214 .name = "Sample Clock Source Locking", 3215 .info = snd_hdsp_info_clock_source_lock, 3216 .get = snd_hdsp_get_clock_source_lock, 3217 .put = snd_hdsp_put_clock_source_lock, 3218 }, 3219 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0), 3220 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0), 3221 HDSP_AUTOSYNC_REF("AutoSync Reference", 0), 3222 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0), 3223 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0), 3224 /* 'External Rate' complies with the alsa control naming scheme */ 3225 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0), 3226 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0), 3227 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0), 3228 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0), 3229 HDSP_LINE_OUT("Line Out", 0), 3230 HDSP_PRECISE_POINTER("Precise Pointer", 0), 3231 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0), 3232 }; 3233 3234 static struct snd_kcontrol_new snd_hdsp_96xx_aeb = HDSP_AEB("Analog Extension Board", 0); 3235 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK; 3236 3237 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp) 3238 { 3239 unsigned int idx; 3240 int err; 3241 struct snd_kcontrol *kctl; 3242 3243 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) { 3244 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0) 3245 return err; 3246 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 3247 hdsp->spdif_ctl = kctl; 3248 } 3249 3250 /* ADAT SyncCheck status */ 3251 snd_hdsp_adat_sync_check.name = "ADAT Lock Status"; 3252 snd_hdsp_adat_sync_check.index = 1; 3253 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) 3254 return err; 3255 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 3256 for (idx = 1; idx < 3; ++idx) { 3257 snd_hdsp_adat_sync_check.index = idx+1; 3258 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp)))) 3259 return err; 3260 } 3261 } 3262 3263 /* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */ 3264 if (hdsp->io_type == H9632) { 3265 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) { 3266 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0) 3267 return err; 3268 } 3269 } 3270 3271 /* AEB control for H96xx card */ 3272 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) { 3273 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0) 3274 return err; 3275 } 3276 3277 return 0; 3278 } 3279 3280 /*------------------------------------------------------------ 3281 /proc interface 3282 ------------------------------------------------------------*/ 3283 3284 static void 3285 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 3286 { 3287 struct hdsp *hdsp = entry->private_data; 3288 unsigned int status; 3289 unsigned int status2; 3290 char *pref_sync_ref; 3291 char *autosync_ref; 3292 char *system_clock_mode; 3293 char *clock_source; 3294 int x; 3295 3296 status = hdsp_read(hdsp, HDSP_statusRegister); 3297 status2 = hdsp_read(hdsp, HDSP_status2Register); 3298 3299 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name, 3300 hdsp->card->number + 1); 3301 snd_iprintf(buffer, "Buffers: capture %p playback %p\n", 3302 hdsp->capture_buffer, hdsp->playback_buffer); 3303 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n", 3304 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase); 3305 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register); 3306 snd_iprintf(buffer, "Control2 register: 0x%x\n", 3307 hdsp->control2_register); 3308 snd_iprintf(buffer, "Status register: 0x%x\n", status); 3309 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2); 3310 3311 if (hdsp_check_for_iobox(hdsp)) { 3312 snd_iprintf(buffer, "No I/O box connected.\n" 3313 "Please connect one and upload firmware.\n"); 3314 return; 3315 } 3316 3317 if (hdsp_check_for_firmware(hdsp, 0)) { 3318 if (hdsp->state & HDSP_FirmwareCached) { 3319 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) { 3320 snd_iprintf(buffer, "Firmware loading from " 3321 "cache failed, " 3322 "please upload manually.\n"); 3323 return; 3324 } 3325 } else { 3326 int err = -EINVAL; 3327 #ifdef HDSP_FW_LOADER 3328 err = hdsp_request_fw_loader(hdsp); 3329 #endif 3330 if (err < 0) { 3331 snd_iprintf(buffer, 3332 "No firmware loaded nor cached, " 3333 "please upload firmware.\n"); 3334 return; 3335 } 3336 } 3337 } 3338 3339 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff); 3340 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0)); 3341 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0)); 3342 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1)); 3343 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1)); 3344 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off"); 3345 3346 snd_iprintf(buffer, "\n"); 3347 3348 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask)); 3349 3350 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes); 3351 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp)); 3352 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off"); 3353 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off"); 3354 3355 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2); 3356 3357 snd_iprintf(buffer, "\n"); 3358 3359 switch (hdsp_clock_source(hdsp)) { 3360 case HDSP_CLOCK_SOURCE_AUTOSYNC: 3361 clock_source = "AutoSync"; 3362 break; 3363 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ: 3364 clock_source = "Internal 32 kHz"; 3365 break; 3366 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ: 3367 clock_source = "Internal 44.1 kHz"; 3368 break; 3369 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ: 3370 clock_source = "Internal 48 kHz"; 3371 break; 3372 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ: 3373 clock_source = "Internal 64 kHz"; 3374 break; 3375 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ: 3376 clock_source = "Internal 88.2 kHz"; 3377 break; 3378 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ: 3379 clock_source = "Internal 96 kHz"; 3380 break; 3381 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ: 3382 clock_source = "Internal 128 kHz"; 3383 break; 3384 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ: 3385 clock_source = "Internal 176.4 kHz"; 3386 break; 3387 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: 3388 clock_source = "Internal 192 kHz"; 3389 break; 3390 default: 3391 clock_source = "Error"; 3392 } 3393 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source); 3394 3395 if (hdsp_system_clock_mode(hdsp)) 3396 system_clock_mode = "Slave"; 3397 else 3398 system_clock_mode = "Master"; 3399 3400 switch (hdsp_pref_sync_ref (hdsp)) { 3401 case HDSP_SYNC_FROM_WORD: 3402 pref_sync_ref = "Word Clock"; 3403 break; 3404 case HDSP_SYNC_FROM_ADAT_SYNC: 3405 pref_sync_ref = "ADAT Sync"; 3406 break; 3407 case HDSP_SYNC_FROM_SPDIF: 3408 pref_sync_ref = "SPDIF"; 3409 break; 3410 case HDSP_SYNC_FROM_ADAT1: 3411 pref_sync_ref = "ADAT1"; 3412 break; 3413 case HDSP_SYNC_FROM_ADAT2: 3414 pref_sync_ref = "ADAT2"; 3415 break; 3416 case HDSP_SYNC_FROM_ADAT3: 3417 pref_sync_ref = "ADAT3"; 3418 break; 3419 default: 3420 pref_sync_ref = "Word Clock"; 3421 break; 3422 } 3423 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref); 3424 3425 switch (hdsp_autosync_ref (hdsp)) { 3426 case HDSP_AUTOSYNC_FROM_WORD: 3427 autosync_ref = "Word Clock"; 3428 break; 3429 case HDSP_AUTOSYNC_FROM_ADAT_SYNC: 3430 autosync_ref = "ADAT Sync"; 3431 break; 3432 case HDSP_AUTOSYNC_FROM_SPDIF: 3433 autosync_ref = "SPDIF"; 3434 break; 3435 case HDSP_AUTOSYNC_FROM_NONE: 3436 autosync_ref = "None"; 3437 break; 3438 case HDSP_AUTOSYNC_FROM_ADAT1: 3439 autosync_ref = "ADAT1"; 3440 break; 3441 case HDSP_AUTOSYNC_FROM_ADAT2: 3442 autosync_ref = "ADAT2"; 3443 break; 3444 case HDSP_AUTOSYNC_FROM_ADAT3: 3445 autosync_ref = "ADAT3"; 3446 break; 3447 default: 3448 autosync_ref = "---"; 3449 break; 3450 } 3451 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref); 3452 3453 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp)); 3454 3455 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode); 3456 3457 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate); 3458 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No"); 3459 3460 snd_iprintf(buffer, "\n"); 3461 3462 switch (hdsp_spdif_in(hdsp)) { 3463 case HDSP_SPDIFIN_OPTICAL: 3464 snd_iprintf(buffer, "IEC958 input: Optical\n"); 3465 break; 3466 case HDSP_SPDIFIN_COAXIAL: 3467 snd_iprintf(buffer, "IEC958 input: Coaxial\n"); 3468 break; 3469 case HDSP_SPDIFIN_INTERNAL: 3470 snd_iprintf(buffer, "IEC958 input: Internal\n"); 3471 break; 3472 case HDSP_SPDIFIN_AES: 3473 snd_iprintf(buffer, "IEC958 input: AES\n"); 3474 break; 3475 default: 3476 snd_iprintf(buffer, "IEC958 input: ???\n"); 3477 break; 3478 } 3479 3480 if (hdsp->control_register & HDSP_SPDIFOpticalOut) 3481 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n"); 3482 else 3483 snd_iprintf(buffer, "IEC958 output: Coaxial only\n"); 3484 3485 if (hdsp->control_register & HDSP_SPDIFProfessional) 3486 snd_iprintf(buffer, "IEC958 quality: Professional\n"); 3487 else 3488 snd_iprintf(buffer, "IEC958 quality: Consumer\n"); 3489 3490 if (hdsp->control_register & HDSP_SPDIFEmphasis) 3491 snd_iprintf(buffer, "IEC958 emphasis: on\n"); 3492 else 3493 snd_iprintf(buffer, "IEC958 emphasis: off\n"); 3494 3495 if (hdsp->control_register & HDSP_SPDIFNonAudio) 3496 snd_iprintf(buffer, "IEC958 NonAudio: on\n"); 3497 else 3498 snd_iprintf(buffer, "IEC958 NonAudio: off\n"); 3499 if ((x = hdsp_spdif_sample_rate (hdsp)) != 0) 3500 snd_iprintf (buffer, "IEC958 sample rate: %d\n", x); 3501 else 3502 snd_iprintf (buffer, "IEC958 sample rate: Error flag set\n"); 3503 3504 snd_iprintf(buffer, "\n"); 3505 3506 /* Sync Check */ 3507 x = status & HDSP_Sync0; 3508 if (status & HDSP_Lock0) 3509 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock"); 3510 else 3511 snd_iprintf(buffer, "ADAT1: No Lock\n"); 3512 3513 switch (hdsp->io_type) { 3514 case Digiface: 3515 case H9652: 3516 x = status & HDSP_Sync1; 3517 if (status & HDSP_Lock1) 3518 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock"); 3519 else 3520 snd_iprintf(buffer, "ADAT2: No Lock\n"); 3521 x = status & HDSP_Sync2; 3522 if (status & HDSP_Lock2) 3523 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock"); 3524 else 3525 snd_iprintf(buffer, "ADAT3: No Lock\n"); 3526 break; 3527 default: 3528 /* relax */ 3529 break; 3530 } 3531 3532 x = status & HDSP_SPDIFSync; 3533 if (status & HDSP_SPDIFErrorFlag) 3534 snd_iprintf (buffer, "SPDIF: No Lock\n"); 3535 else 3536 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock"); 3537 3538 x = status2 & HDSP_wc_sync; 3539 if (status2 & HDSP_wc_lock) 3540 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock"); 3541 else 3542 snd_iprintf (buffer, "Word Clock: No Lock\n"); 3543 3544 x = status & HDSP_TimecodeSync; 3545 if (status & HDSP_TimecodeLock) 3546 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock"); 3547 else 3548 snd_iprintf(buffer, "ADAT Sync: No Lock\n"); 3549 3550 snd_iprintf(buffer, "\n"); 3551 3552 /* Informations about H9632 specific controls */ 3553 if (hdsp->io_type == H9632) { 3554 char *tmp; 3555 3556 switch (hdsp_ad_gain(hdsp)) { 3557 case 0: 3558 tmp = "-10 dBV"; 3559 break; 3560 case 1: 3561 tmp = "+4 dBu"; 3562 break; 3563 default: 3564 tmp = "Lo Gain"; 3565 break; 3566 } 3567 snd_iprintf(buffer, "AD Gain : %s\n", tmp); 3568 3569 switch (hdsp_da_gain(hdsp)) { 3570 case 0: 3571 tmp = "Hi Gain"; 3572 break; 3573 case 1: 3574 tmp = "+4 dBu"; 3575 break; 3576 default: 3577 tmp = "-10 dBV"; 3578 break; 3579 } 3580 snd_iprintf(buffer, "DA Gain : %s\n", tmp); 3581 3582 switch (hdsp_phone_gain(hdsp)) { 3583 case 0: 3584 tmp = "0 dB"; 3585 break; 3586 case 1: 3587 tmp = "-6 dB"; 3588 break; 3589 default: 3590 tmp = "-12 dB"; 3591 break; 3592 } 3593 snd_iprintf(buffer, "Phones Gain : %s\n", tmp); 3594 3595 snd_iprintf(buffer, "XLR Breakout Cable : %s\n", hdsp_xlr_breakout_cable(hdsp) ? "yes" : "no"); 3596 3597 if (hdsp->control_register & HDSP_AnalogExtensionBoard) 3598 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n"); 3599 else 3600 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n"); 3601 snd_iprintf(buffer, "\n"); 3602 } 3603 3604 } 3605 3606 static void snd_hdsp_proc_init(struct hdsp *hdsp) 3607 { 3608 struct snd_info_entry *entry; 3609 3610 if (! snd_card_proc_new(hdsp->card, "hdsp", &entry)) 3611 snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read); 3612 } 3613 3614 static void snd_hdsp_free_buffers(struct hdsp *hdsp) 3615 { 3616 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci); 3617 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci); 3618 } 3619 3620 static int __devinit snd_hdsp_initialize_memory(struct hdsp *hdsp) 3621 { 3622 unsigned long pb_bus, cb_bus; 3623 3624 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 || 3625 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) { 3626 if (hdsp->capture_dma_buf.area) 3627 snd_dma_free_pages(&hdsp->capture_dma_buf); 3628 printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name); 3629 return -ENOMEM; 3630 } 3631 3632 /* Align to bus-space 64K boundary */ 3633 3634 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul); 3635 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul); 3636 3637 /* Tell the card where it is */ 3638 3639 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus); 3640 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus); 3641 3642 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr); 3643 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr); 3644 3645 return 0; 3646 } 3647 3648 static int snd_hdsp_set_defaults(struct hdsp *hdsp) 3649 { 3650 unsigned int i; 3651 3652 /* ASSUMPTION: hdsp->lock is either held, or 3653 there is no need to hold it (e.g. during module 3654 initialization). 3655 */ 3656 3657 /* set defaults: 3658 3659 SPDIF Input via Coax 3660 Master clock mode 3661 maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer, 3662 which implies 2 4096 sample, 32Kbyte periods). 3663 Enable line out. 3664 */ 3665 3666 hdsp->control_register = HDSP_ClockModeMaster | 3667 HDSP_SPDIFInputCoaxial | 3668 hdsp_encode_latency(7) | 3669 HDSP_LineOut; 3670 3671 3672 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3673 3674 #ifdef SNDRV_BIG_ENDIAN 3675 hdsp->control2_register = HDSP_BIGENDIAN_MODE; 3676 #else 3677 hdsp->control2_register = 0; 3678 #endif 3679 if (hdsp->io_type == H9652) 3680 snd_hdsp_9652_enable_mixer (hdsp); 3681 else 3682 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 3683 3684 hdsp_reset_hw_pointer(hdsp); 3685 hdsp_compute_period_size(hdsp); 3686 3687 /* silence everything */ 3688 3689 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i) 3690 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN; 3691 3692 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) { 3693 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN)) 3694 return -EIO; 3695 } 3696 3697 /* H9632 specific defaults */ 3698 if (hdsp->io_type == H9632) { 3699 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB); 3700 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3701 } 3702 3703 /* set a default rate so that the channel map is set up. 3704 */ 3705 3706 hdsp_set_rate(hdsp, 48000, 1); 3707 3708 return 0; 3709 } 3710 3711 static void hdsp_midi_tasklet(unsigned long arg) 3712 { 3713 struct hdsp *hdsp = (struct hdsp *)arg; 3714 3715 if (hdsp->midi[0].pending) 3716 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3717 if (hdsp->midi[1].pending) 3718 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3719 } 3720 3721 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id) 3722 { 3723 struct hdsp *hdsp = (struct hdsp *) dev_id; 3724 unsigned int status; 3725 int audio; 3726 int midi0; 3727 int midi1; 3728 unsigned int midi0status; 3729 unsigned int midi1status; 3730 int schedule = 0; 3731 3732 status = hdsp_read(hdsp, HDSP_statusRegister); 3733 3734 audio = status & HDSP_audioIRQPending; 3735 midi0 = status & HDSP_midi0IRQPending; 3736 midi1 = status & HDSP_midi1IRQPending; 3737 3738 if (!audio && !midi0 && !midi1) 3739 return IRQ_NONE; 3740 3741 hdsp_write(hdsp, HDSP_interruptConfirmation, 0); 3742 3743 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff; 3744 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff; 3745 3746 if (!(hdsp->state & HDSP_InitializationComplete)) 3747 return IRQ_HANDLED; 3748 3749 if (audio) { 3750 if (hdsp->capture_substream) 3751 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream); 3752 3753 if (hdsp->playback_substream) 3754 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream); 3755 } 3756 3757 if (midi0 && midi0status) { 3758 if (hdsp->use_midi_tasklet) { 3759 /* we disable interrupts for this input until processing is done */ 3760 hdsp->control_register &= ~HDSP_Midi0InterruptEnable; 3761 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3762 hdsp->midi[0].pending = 1; 3763 schedule = 1; 3764 } else { 3765 snd_hdsp_midi_input_read (&hdsp->midi[0]); 3766 } 3767 } 3768 if (hdsp->io_type != Multiface && hdsp->io_type != H9632 && midi1 && midi1status) { 3769 if (hdsp->use_midi_tasklet) { 3770 /* we disable interrupts for this input until processing is done */ 3771 hdsp->control_register &= ~HDSP_Midi1InterruptEnable; 3772 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register); 3773 hdsp->midi[1].pending = 1; 3774 schedule = 1; 3775 } else { 3776 snd_hdsp_midi_input_read (&hdsp->midi[1]); 3777 } 3778 } 3779 if (hdsp->use_midi_tasklet && schedule) 3780 tasklet_schedule(&hdsp->midi_tasklet); 3781 return IRQ_HANDLED; 3782 } 3783 3784 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream) 3785 { 3786 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3787 return hdsp_hw_pointer(hdsp); 3788 } 3789 3790 static char *hdsp_channel_buffer_location(struct hdsp *hdsp, 3791 int stream, 3792 int channel) 3793 3794 { 3795 int mapped_channel; 3796 3797 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels)) 3798 return NULL; 3799 3800 if ((mapped_channel = hdsp->channel_map[channel]) < 0) 3801 return NULL; 3802 3803 if (stream == SNDRV_PCM_STREAM_CAPTURE) 3804 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3805 else 3806 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES); 3807 } 3808 3809 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel, 3810 snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count) 3811 { 3812 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3813 char *channel_buf; 3814 3815 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4)) 3816 return -EINVAL; 3817 3818 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3819 if (snd_BUG_ON(!channel_buf)) 3820 return -EIO; 3821 if (copy_from_user(channel_buf + pos * 4, src, count * 4)) 3822 return -EFAULT; 3823 return count; 3824 } 3825 3826 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel, 3827 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count) 3828 { 3829 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3830 char *channel_buf; 3831 3832 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4)) 3833 return -EINVAL; 3834 3835 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3836 if (snd_BUG_ON(!channel_buf)) 3837 return -EIO; 3838 if (copy_to_user(dst, channel_buf + pos * 4, count * 4)) 3839 return -EFAULT; 3840 return count; 3841 } 3842 3843 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel, 3844 snd_pcm_uframes_t pos, snd_pcm_uframes_t count) 3845 { 3846 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3847 char *channel_buf; 3848 3849 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel); 3850 if (snd_BUG_ON(!channel_buf)) 3851 return -EIO; 3852 memset(channel_buf + pos * 4, 0, count * 4); 3853 return count; 3854 } 3855 3856 static int snd_hdsp_reset(struct snd_pcm_substream *substream) 3857 { 3858 struct snd_pcm_runtime *runtime = substream->runtime; 3859 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3860 struct snd_pcm_substream *other; 3861 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 3862 other = hdsp->capture_substream; 3863 else 3864 other = hdsp->playback_substream; 3865 if (hdsp->running) 3866 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp); 3867 else 3868 runtime->status->hw_ptr = 0; 3869 if (other) { 3870 struct snd_pcm_substream *s; 3871 struct snd_pcm_runtime *oruntime = other->runtime; 3872 snd_pcm_group_for_each_entry(s, substream) { 3873 if (s == other) { 3874 oruntime->status->hw_ptr = runtime->status->hw_ptr; 3875 break; 3876 } 3877 } 3878 } 3879 return 0; 3880 } 3881 3882 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream, 3883 struct snd_pcm_hw_params *params) 3884 { 3885 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3886 int err; 3887 pid_t this_pid; 3888 pid_t other_pid; 3889 3890 if (hdsp_check_for_iobox (hdsp)) 3891 return -EIO; 3892 3893 if (hdsp_check_for_firmware(hdsp, 1)) 3894 return -EIO; 3895 3896 spin_lock_irq(&hdsp->lock); 3897 3898 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) { 3899 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis); 3900 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream); 3901 this_pid = hdsp->playback_pid; 3902 other_pid = hdsp->capture_pid; 3903 } else { 3904 this_pid = hdsp->capture_pid; 3905 other_pid = hdsp->playback_pid; 3906 } 3907 3908 if ((other_pid > 0) && (this_pid != other_pid)) { 3909 3910 /* The other stream is open, and not by the same 3911 task as this one. Make sure that the parameters 3912 that matter are the same. 3913 */ 3914 3915 if (params_rate(params) != hdsp->system_sample_rate) { 3916 spin_unlock_irq(&hdsp->lock); 3917 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3918 return -EBUSY; 3919 } 3920 3921 if (params_period_size(params) != hdsp->period_bytes / 4) { 3922 spin_unlock_irq(&hdsp->lock); 3923 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 3924 return -EBUSY; 3925 } 3926 3927 /* We're fine. */ 3928 3929 spin_unlock_irq(&hdsp->lock); 3930 return 0; 3931 3932 } else { 3933 spin_unlock_irq(&hdsp->lock); 3934 } 3935 3936 /* how to make sure that the rate matches an externally-set one ? 3937 */ 3938 3939 spin_lock_irq(&hdsp->lock); 3940 if (! hdsp->clock_source_locked) { 3941 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) { 3942 spin_unlock_irq(&hdsp->lock); 3943 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE); 3944 return err; 3945 } 3946 } 3947 spin_unlock_irq(&hdsp->lock); 3948 3949 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) { 3950 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE); 3951 return err; 3952 } 3953 3954 return 0; 3955 } 3956 3957 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream, 3958 struct snd_pcm_channel_info *info) 3959 { 3960 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3961 int mapped_channel; 3962 3963 if (snd_BUG_ON(info->channel >= hdsp->max_channels)) 3964 return -EINVAL; 3965 3966 if ((mapped_channel = hdsp->channel_map[info->channel]) < 0) 3967 return -EINVAL; 3968 3969 info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES; 3970 info->first = 0; 3971 info->step = 32; 3972 return 0; 3973 } 3974 3975 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream, 3976 unsigned int cmd, void *arg) 3977 { 3978 switch (cmd) { 3979 case SNDRV_PCM_IOCTL1_RESET: 3980 return snd_hdsp_reset(substream); 3981 case SNDRV_PCM_IOCTL1_CHANNEL_INFO: 3982 return snd_hdsp_channel_info(substream, arg); 3983 default: 3984 break; 3985 } 3986 3987 return snd_pcm_lib_ioctl(substream, cmd, arg); 3988 } 3989 3990 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd) 3991 { 3992 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 3993 struct snd_pcm_substream *other; 3994 int running; 3995 3996 if (hdsp_check_for_iobox (hdsp)) 3997 return -EIO; 3998 3999 if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */ 4000 return -EIO; 4001 4002 spin_lock(&hdsp->lock); 4003 running = hdsp->running; 4004 switch (cmd) { 4005 case SNDRV_PCM_TRIGGER_START: 4006 running |= 1 << substream->stream; 4007 break; 4008 case SNDRV_PCM_TRIGGER_STOP: 4009 running &= ~(1 << substream->stream); 4010 break; 4011 default: 4012 snd_BUG(); 4013 spin_unlock(&hdsp->lock); 4014 return -EINVAL; 4015 } 4016 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4017 other = hdsp->capture_substream; 4018 else 4019 other = hdsp->playback_substream; 4020 4021 if (other) { 4022 struct snd_pcm_substream *s; 4023 snd_pcm_group_for_each_entry(s, substream) { 4024 if (s == other) { 4025 snd_pcm_trigger_done(s, substream); 4026 if (cmd == SNDRV_PCM_TRIGGER_START) 4027 running |= 1 << s->stream; 4028 else 4029 running &= ~(1 << s->stream); 4030 goto _ok; 4031 } 4032 } 4033 if (cmd == SNDRV_PCM_TRIGGER_START) { 4034 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) && 4035 substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4036 hdsp_silence_playback(hdsp); 4037 } else { 4038 if (running && 4039 substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 4040 hdsp_silence_playback(hdsp); 4041 } 4042 } else { 4043 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 4044 hdsp_silence_playback(hdsp); 4045 } 4046 _ok: 4047 snd_pcm_trigger_done(substream, substream); 4048 if (!hdsp->running && running) 4049 hdsp_start_audio(hdsp); 4050 else if (hdsp->running && !running) 4051 hdsp_stop_audio(hdsp); 4052 hdsp->running = running; 4053 spin_unlock(&hdsp->lock); 4054 4055 return 0; 4056 } 4057 4058 static int snd_hdsp_prepare(struct snd_pcm_substream *substream) 4059 { 4060 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4061 int result = 0; 4062 4063 if (hdsp_check_for_iobox (hdsp)) 4064 return -EIO; 4065 4066 if (hdsp_check_for_firmware(hdsp, 1)) 4067 return -EIO; 4068 4069 spin_lock_irq(&hdsp->lock); 4070 if (!hdsp->running) 4071 hdsp_reset_hw_pointer(hdsp); 4072 spin_unlock_irq(&hdsp->lock); 4073 return result; 4074 } 4075 4076 static struct snd_pcm_hardware snd_hdsp_playback_subinfo = 4077 { 4078 .info = (SNDRV_PCM_INFO_MMAP | 4079 SNDRV_PCM_INFO_MMAP_VALID | 4080 SNDRV_PCM_INFO_NONINTERLEAVED | 4081 SNDRV_PCM_INFO_SYNC_START | 4082 SNDRV_PCM_INFO_DOUBLE), 4083 #ifdef SNDRV_BIG_ENDIAN 4084 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4085 #else 4086 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4087 #endif 4088 .rates = (SNDRV_PCM_RATE_32000 | 4089 SNDRV_PCM_RATE_44100 | 4090 SNDRV_PCM_RATE_48000 | 4091 SNDRV_PCM_RATE_64000 | 4092 SNDRV_PCM_RATE_88200 | 4093 SNDRV_PCM_RATE_96000), 4094 .rate_min = 32000, 4095 .rate_max = 96000, 4096 .channels_min = 14, 4097 .channels_max = HDSP_MAX_CHANNELS, 4098 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4099 .period_bytes_min = (64 * 4) * 10, 4100 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4101 .periods_min = 2, 4102 .periods_max = 2, 4103 .fifo_size = 0 4104 }; 4105 4106 static struct snd_pcm_hardware snd_hdsp_capture_subinfo = 4107 { 4108 .info = (SNDRV_PCM_INFO_MMAP | 4109 SNDRV_PCM_INFO_MMAP_VALID | 4110 SNDRV_PCM_INFO_NONINTERLEAVED | 4111 SNDRV_PCM_INFO_SYNC_START), 4112 #ifdef SNDRV_BIG_ENDIAN 4113 .formats = SNDRV_PCM_FMTBIT_S32_BE, 4114 #else 4115 .formats = SNDRV_PCM_FMTBIT_S32_LE, 4116 #endif 4117 .rates = (SNDRV_PCM_RATE_32000 | 4118 SNDRV_PCM_RATE_44100 | 4119 SNDRV_PCM_RATE_48000 | 4120 SNDRV_PCM_RATE_64000 | 4121 SNDRV_PCM_RATE_88200 | 4122 SNDRV_PCM_RATE_96000), 4123 .rate_min = 32000, 4124 .rate_max = 96000, 4125 .channels_min = 14, 4126 .channels_max = HDSP_MAX_CHANNELS, 4127 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS, 4128 .period_bytes_min = (64 * 4) * 10, 4129 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS, 4130 .periods_min = 2, 4131 .periods_max = 2, 4132 .fifo_size = 0 4133 }; 4134 4135 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 }; 4136 4137 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = { 4138 .count = ARRAY_SIZE(hdsp_period_sizes), 4139 .list = hdsp_period_sizes, 4140 .mask = 0 4141 }; 4142 4143 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 }; 4144 4145 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = { 4146 .count = ARRAY_SIZE(hdsp_9632_sample_rates), 4147 .list = hdsp_9632_sample_rates, 4148 .mask = 0 4149 }; 4150 4151 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params, 4152 struct snd_pcm_hw_rule *rule) 4153 { 4154 struct hdsp *hdsp = rule->private; 4155 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4156 if (hdsp->io_type == H9632) { 4157 unsigned int list[3]; 4158 list[0] = hdsp->qs_in_channels; 4159 list[1] = hdsp->ds_in_channels; 4160 list[2] = hdsp->ss_in_channels; 4161 return snd_interval_list(c, 3, list, 0); 4162 } else { 4163 unsigned int list[2]; 4164 list[0] = hdsp->ds_in_channels; 4165 list[1] = hdsp->ss_in_channels; 4166 return snd_interval_list(c, 2, list, 0); 4167 } 4168 } 4169 4170 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params, 4171 struct snd_pcm_hw_rule *rule) 4172 { 4173 unsigned int list[3]; 4174 struct hdsp *hdsp = rule->private; 4175 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4176 if (hdsp->io_type == H9632) { 4177 list[0] = hdsp->qs_out_channels; 4178 list[1] = hdsp->ds_out_channels; 4179 list[2] = hdsp->ss_out_channels; 4180 return snd_interval_list(c, 3, list, 0); 4181 } else { 4182 list[0] = hdsp->ds_out_channels; 4183 list[1] = hdsp->ss_out_channels; 4184 } 4185 return snd_interval_list(c, 2, list, 0); 4186 } 4187 4188 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params, 4189 struct snd_pcm_hw_rule *rule) 4190 { 4191 struct hdsp *hdsp = rule->private; 4192 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4193 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4194 if (r->min > 96000 && hdsp->io_type == H9632) { 4195 struct snd_interval t = { 4196 .min = hdsp->qs_in_channels, 4197 .max = hdsp->qs_in_channels, 4198 .integer = 1, 4199 }; 4200 return snd_interval_refine(c, &t); 4201 } else if (r->min > 48000 && r->max <= 96000) { 4202 struct snd_interval t = { 4203 .min = hdsp->ds_in_channels, 4204 .max = hdsp->ds_in_channels, 4205 .integer = 1, 4206 }; 4207 return snd_interval_refine(c, &t); 4208 } else if (r->max < 64000) { 4209 struct snd_interval t = { 4210 .min = hdsp->ss_in_channels, 4211 .max = hdsp->ss_in_channels, 4212 .integer = 1, 4213 }; 4214 return snd_interval_refine(c, &t); 4215 } 4216 return 0; 4217 } 4218 4219 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params, 4220 struct snd_pcm_hw_rule *rule) 4221 { 4222 struct hdsp *hdsp = rule->private; 4223 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4224 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4225 if (r->min > 96000 && hdsp->io_type == H9632) { 4226 struct snd_interval t = { 4227 .min = hdsp->qs_out_channels, 4228 .max = hdsp->qs_out_channels, 4229 .integer = 1, 4230 }; 4231 return snd_interval_refine(c, &t); 4232 } else if (r->min > 48000 && r->max <= 96000) { 4233 struct snd_interval t = { 4234 .min = hdsp->ds_out_channels, 4235 .max = hdsp->ds_out_channels, 4236 .integer = 1, 4237 }; 4238 return snd_interval_refine(c, &t); 4239 } else if (r->max < 64000) { 4240 struct snd_interval t = { 4241 .min = hdsp->ss_out_channels, 4242 .max = hdsp->ss_out_channels, 4243 .integer = 1, 4244 }; 4245 return snd_interval_refine(c, &t); 4246 } 4247 return 0; 4248 } 4249 4250 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params, 4251 struct snd_pcm_hw_rule *rule) 4252 { 4253 struct hdsp *hdsp = rule->private; 4254 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4255 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4256 if (c->min >= hdsp->ss_out_channels) { 4257 struct snd_interval t = { 4258 .min = 32000, 4259 .max = 48000, 4260 .integer = 1, 4261 }; 4262 return snd_interval_refine(r, &t); 4263 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) { 4264 struct snd_interval t = { 4265 .min = 128000, 4266 .max = 192000, 4267 .integer = 1, 4268 }; 4269 return snd_interval_refine(r, &t); 4270 } else if (c->max <= hdsp->ds_out_channels) { 4271 struct snd_interval t = { 4272 .min = 64000, 4273 .max = 96000, 4274 .integer = 1, 4275 }; 4276 return snd_interval_refine(r, &t); 4277 } 4278 return 0; 4279 } 4280 4281 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params, 4282 struct snd_pcm_hw_rule *rule) 4283 { 4284 struct hdsp *hdsp = rule->private; 4285 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS); 4286 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE); 4287 if (c->min >= hdsp->ss_in_channels) { 4288 struct snd_interval t = { 4289 .min = 32000, 4290 .max = 48000, 4291 .integer = 1, 4292 }; 4293 return snd_interval_refine(r, &t); 4294 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) { 4295 struct snd_interval t = { 4296 .min = 128000, 4297 .max = 192000, 4298 .integer = 1, 4299 }; 4300 return snd_interval_refine(r, &t); 4301 } else if (c->max <= hdsp->ds_in_channels) { 4302 struct snd_interval t = { 4303 .min = 64000, 4304 .max = 96000, 4305 .integer = 1, 4306 }; 4307 return snd_interval_refine(r, &t); 4308 } 4309 return 0; 4310 } 4311 4312 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream) 4313 { 4314 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4315 struct snd_pcm_runtime *runtime = substream->runtime; 4316 4317 if (hdsp_check_for_iobox (hdsp)) 4318 return -EIO; 4319 4320 if (hdsp_check_for_firmware(hdsp, 1)) 4321 return -EIO; 4322 4323 spin_lock_irq(&hdsp->lock); 4324 4325 snd_pcm_set_sync(substream); 4326 4327 runtime->hw = snd_hdsp_playback_subinfo; 4328 runtime->dma_area = hdsp->playback_buffer; 4329 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4330 4331 hdsp->playback_pid = current->pid; 4332 hdsp->playback_substream = substream; 4333 4334 spin_unlock_irq(&hdsp->lock); 4335 4336 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4337 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4338 if (hdsp->clock_source_locked) { 4339 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate; 4340 } else if (hdsp->io_type == H9632) { 4341 runtime->hw.rate_max = 192000; 4342 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4343 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4344 } 4345 if (hdsp->io_type == H9632) { 4346 runtime->hw.channels_min = hdsp->qs_out_channels; 4347 runtime->hw.channels_max = hdsp->ss_out_channels; 4348 } 4349 4350 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4351 snd_hdsp_hw_rule_out_channels, hdsp, 4352 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4353 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4354 snd_hdsp_hw_rule_out_channels_rate, hdsp, 4355 SNDRV_PCM_HW_PARAM_RATE, -1); 4356 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4357 snd_hdsp_hw_rule_rate_out_channels, hdsp, 4358 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4359 4360 hdsp->creg_spdif_stream = hdsp->creg_spdif; 4361 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4362 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4363 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4364 return 0; 4365 } 4366 4367 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream) 4368 { 4369 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4370 4371 spin_lock_irq(&hdsp->lock); 4372 4373 hdsp->playback_pid = -1; 4374 hdsp->playback_substream = NULL; 4375 4376 spin_unlock_irq(&hdsp->lock); 4377 4378 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 4379 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE | 4380 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id); 4381 return 0; 4382 } 4383 4384 4385 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream) 4386 { 4387 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4388 struct snd_pcm_runtime *runtime = substream->runtime; 4389 4390 if (hdsp_check_for_iobox (hdsp)) 4391 return -EIO; 4392 4393 if (hdsp_check_for_firmware(hdsp, 1)) 4394 return -EIO; 4395 4396 spin_lock_irq(&hdsp->lock); 4397 4398 snd_pcm_set_sync(substream); 4399 4400 runtime->hw = snd_hdsp_capture_subinfo; 4401 runtime->dma_area = hdsp->capture_buffer; 4402 runtime->dma_bytes = HDSP_DMA_AREA_BYTES; 4403 4404 hdsp->capture_pid = current->pid; 4405 hdsp->capture_substream = substream; 4406 4407 spin_unlock_irq(&hdsp->lock); 4408 4409 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24); 4410 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes); 4411 if (hdsp->io_type == H9632) { 4412 runtime->hw.channels_min = hdsp->qs_in_channels; 4413 runtime->hw.channels_max = hdsp->ss_in_channels; 4414 runtime->hw.rate_max = 192000; 4415 runtime->hw.rates = SNDRV_PCM_RATE_KNOT; 4416 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates); 4417 } 4418 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4419 snd_hdsp_hw_rule_in_channels, hdsp, 4420 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4421 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 4422 snd_hdsp_hw_rule_in_channels_rate, hdsp, 4423 SNDRV_PCM_HW_PARAM_RATE, -1); 4424 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 4425 snd_hdsp_hw_rule_rate_in_channels, hdsp, 4426 SNDRV_PCM_HW_PARAM_CHANNELS, -1); 4427 return 0; 4428 } 4429 4430 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream) 4431 { 4432 struct hdsp *hdsp = snd_pcm_substream_chip(substream); 4433 4434 spin_lock_irq(&hdsp->lock); 4435 4436 hdsp->capture_pid = -1; 4437 hdsp->capture_substream = NULL; 4438 4439 spin_unlock_irq(&hdsp->lock); 4440 return 0; 4441 } 4442 4443 /* helper functions for copying meter values */ 4444 static inline int copy_u32_le(void __user *dest, void __iomem *src) 4445 { 4446 u32 val = readl(src); 4447 return copy_to_user(dest, &val, 4); 4448 } 4449 4450 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4451 { 4452 u32 rms_low, rms_high; 4453 u64 rms; 4454 rms_low = readl(src_low); 4455 rms_high = readl(src_high); 4456 rms = ((u64)rms_high << 32) | rms_low; 4457 return copy_to_user(dest, &rms, 8); 4458 } 4459 4460 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high) 4461 { 4462 u32 rms_low, rms_high; 4463 u64 rms; 4464 rms_low = readl(src_low) & 0xffffff00; 4465 rms_high = readl(src_high) & 0xffffff00; 4466 rms = ((u64)rms_high << 32) | rms_low; 4467 return copy_to_user(dest, &rms, 8); 4468 } 4469 4470 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4471 { 4472 int doublespeed = 0; 4473 int i, j, channels, ofs; 4474 4475 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4476 doublespeed = 1; 4477 channels = doublespeed ? 14 : 26; 4478 for (i = 0, j = 0; i < 26; ++i) { 4479 if (doublespeed && (i & 4)) 4480 continue; 4481 ofs = HDSP_9652_peakBase - j * 4; 4482 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs)) 4483 return -EFAULT; 4484 ofs -= channels * 4; 4485 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs)) 4486 return -EFAULT; 4487 ofs -= channels * 4; 4488 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs)) 4489 return -EFAULT; 4490 ofs = HDSP_9652_rmsBase + j * 8; 4491 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs, 4492 hdsp->iobase + ofs + 4)) 4493 return -EFAULT; 4494 ofs += channels * 8; 4495 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs, 4496 hdsp->iobase + ofs + 4)) 4497 return -EFAULT; 4498 ofs += channels * 8; 4499 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs, 4500 hdsp->iobase + ofs + 4)) 4501 return -EFAULT; 4502 j++; 4503 } 4504 return 0; 4505 } 4506 4507 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4508 { 4509 int i, j; 4510 struct hdsp_9632_meters __iomem *m; 4511 int doublespeed = 0; 4512 4513 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus) 4514 doublespeed = 1; 4515 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase); 4516 for (i = 0, j = 0; i < 16; ++i, ++j) { 4517 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j])) 4518 return -EFAULT; 4519 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j])) 4520 return -EFAULT; 4521 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j])) 4522 return -EFAULT; 4523 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j], 4524 &m->input_rms_high[j])) 4525 return -EFAULT; 4526 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j], 4527 &m->playback_rms_high[j])) 4528 return -EFAULT; 4529 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j], 4530 &m->output_rms_high[j])) 4531 return -EFAULT; 4532 if (doublespeed && i == 3) i += 4; 4533 } 4534 return 0; 4535 } 4536 4537 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms) 4538 { 4539 int i; 4540 4541 for (i = 0; i < 26; i++) { 4542 if (copy_u32_le(&peak_rms->playback_peaks[i], 4543 hdsp->iobase + HDSP_playbackPeakLevel + i * 4)) 4544 return -EFAULT; 4545 if (copy_u32_le(&peak_rms->input_peaks[i], 4546 hdsp->iobase + HDSP_inputPeakLevel + i * 4)) 4547 return -EFAULT; 4548 } 4549 for (i = 0; i < 28; i++) { 4550 if (copy_u32_le(&peak_rms->output_peaks[i], 4551 hdsp->iobase + HDSP_outputPeakLevel + i * 4)) 4552 return -EFAULT; 4553 } 4554 for (i = 0; i < 26; ++i) { 4555 if (copy_u64_le(&peak_rms->playback_rms[i], 4556 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4, 4557 hdsp->iobase + HDSP_playbackRmsLevel + i * 8)) 4558 return -EFAULT; 4559 if (copy_u64_le(&peak_rms->input_rms[i], 4560 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4, 4561 hdsp->iobase + HDSP_inputRmsLevel + i * 8)) 4562 return -EFAULT; 4563 } 4564 return 0; 4565 } 4566 4567 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg) 4568 { 4569 struct hdsp *hdsp = hw->private_data; 4570 void __user *argp = (void __user *)arg; 4571 int err; 4572 4573 switch (cmd) { 4574 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: { 4575 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg; 4576 4577 err = hdsp_check_for_iobox(hdsp); 4578 if (err < 0) 4579 return err; 4580 4581 err = hdsp_check_for_firmware(hdsp, 1); 4582 if (err < 0) 4583 return err; 4584 4585 if (!(hdsp->state & HDSP_FirmwareLoaded)) { 4586 snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n"); 4587 return -EINVAL; 4588 } 4589 4590 switch (hdsp->io_type) { 4591 case H9652: 4592 return hdsp_9652_get_peak(hdsp, peak_rms); 4593 case H9632: 4594 return hdsp_9632_get_peak(hdsp, peak_rms); 4595 default: 4596 return hdsp_get_peak(hdsp, peak_rms); 4597 } 4598 } 4599 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: { 4600 struct hdsp_config_info info; 4601 unsigned long flags; 4602 int i; 4603 4604 err = hdsp_check_for_iobox(hdsp); 4605 if (err < 0) 4606 return err; 4607 4608 err = hdsp_check_for_firmware(hdsp, 1); 4609 if (err < 0) 4610 return err; 4611 4612 memset(&info, 0, sizeof(info)); 4613 spin_lock_irqsave(&hdsp->lock, flags); 4614 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp); 4615 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp); 4616 if (hdsp->io_type != H9632) 4617 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp); 4618 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp); 4619 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != H9632) ? 3 : 1); ++i) 4620 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i); 4621 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp); 4622 info.spdif_out = (unsigned char)hdsp_spdif_out(hdsp); 4623 info.spdif_professional = (unsigned char)hdsp_spdif_professional(hdsp); 4624 info.spdif_emphasis = (unsigned char)hdsp_spdif_emphasis(hdsp); 4625 info.spdif_nonaudio = (unsigned char)hdsp_spdif_nonaudio(hdsp); 4626 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp); 4627 info.system_sample_rate = hdsp->system_sample_rate; 4628 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp); 4629 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp); 4630 info.clock_source = (unsigned char)hdsp_clock_source(hdsp); 4631 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp); 4632 info.line_out = (unsigned char)hdsp_line_out(hdsp); 4633 if (hdsp->io_type == H9632) { 4634 info.da_gain = (unsigned char)hdsp_da_gain(hdsp); 4635 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp); 4636 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp); 4637 info.xlr_breakout_cable = (unsigned char)hdsp_xlr_breakout_cable(hdsp); 4638 4639 } 4640 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) 4641 info.analog_extension_board = (unsigned char)hdsp_aeb(hdsp); 4642 spin_unlock_irqrestore(&hdsp->lock, flags); 4643 if (copy_to_user(argp, &info, sizeof(info))) 4644 return -EFAULT; 4645 break; 4646 } 4647 case SNDRV_HDSP_IOCTL_GET_9632_AEB: { 4648 struct hdsp_9632_aeb h9632_aeb; 4649 4650 if (hdsp->io_type != H9632) return -EINVAL; 4651 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS; 4652 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS; 4653 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb))) 4654 return -EFAULT; 4655 break; 4656 } 4657 case SNDRV_HDSP_IOCTL_GET_VERSION: { 4658 struct hdsp_version hdsp_version; 4659 int err; 4660 4661 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4662 if (hdsp->io_type == Undefined) { 4663 if ((err = hdsp_get_iobox_version(hdsp)) < 0) 4664 return err; 4665 } 4666 hdsp_version.io_type = hdsp->io_type; 4667 hdsp_version.firmware_rev = hdsp->firmware_rev; 4668 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version)))) 4669 return -EFAULT; 4670 break; 4671 } 4672 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: { 4673 struct hdsp_firmware __user *firmware; 4674 u32 __user *firmware_data; 4675 int err; 4676 4677 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL; 4678 /* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */ 4679 if (hdsp->io_type == Undefined) return -EINVAL; 4680 4681 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded)) 4682 return -EBUSY; 4683 4684 snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n"); 4685 firmware = (struct hdsp_firmware __user *)argp; 4686 4687 if (get_user(firmware_data, &firmware->firmware_data)) 4688 return -EFAULT; 4689 4690 if (hdsp_check_for_iobox (hdsp)) 4691 return -EIO; 4692 4693 if (copy_from_user(hdsp->firmware_cache, firmware_data, sizeof(hdsp->firmware_cache)) != 0) 4694 return -EFAULT; 4695 4696 hdsp->state |= HDSP_FirmwareCached; 4697 4698 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) 4699 return err; 4700 4701 if (!(hdsp->state & HDSP_InitializationComplete)) { 4702 if ((err = snd_hdsp_enable_io(hdsp)) < 0) 4703 return err; 4704 4705 snd_hdsp_initialize_channels(hdsp); 4706 snd_hdsp_initialize_midi_flush(hdsp); 4707 4708 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { 4709 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); 4710 return err; 4711 } 4712 } 4713 break; 4714 } 4715 case SNDRV_HDSP_IOCTL_GET_MIXER: { 4716 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp; 4717 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE)) 4718 return -EFAULT; 4719 break; 4720 } 4721 default: 4722 return -EINVAL; 4723 } 4724 return 0; 4725 } 4726 4727 static struct snd_pcm_ops snd_hdsp_playback_ops = { 4728 .open = snd_hdsp_playback_open, 4729 .close = snd_hdsp_playback_release, 4730 .ioctl = snd_hdsp_ioctl, 4731 .hw_params = snd_hdsp_hw_params, 4732 .prepare = snd_hdsp_prepare, 4733 .trigger = snd_hdsp_trigger, 4734 .pointer = snd_hdsp_hw_pointer, 4735 .copy = snd_hdsp_playback_copy, 4736 .silence = snd_hdsp_hw_silence, 4737 }; 4738 4739 static struct snd_pcm_ops snd_hdsp_capture_ops = { 4740 .open = snd_hdsp_capture_open, 4741 .close = snd_hdsp_capture_release, 4742 .ioctl = snd_hdsp_ioctl, 4743 .hw_params = snd_hdsp_hw_params, 4744 .prepare = snd_hdsp_prepare, 4745 .trigger = snd_hdsp_trigger, 4746 .pointer = snd_hdsp_hw_pointer, 4747 .copy = snd_hdsp_capture_copy, 4748 }; 4749 4750 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp) 4751 { 4752 struct snd_hwdep *hw; 4753 int err; 4754 4755 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0) 4756 return err; 4757 4758 hdsp->hwdep = hw; 4759 hw->private_data = hdsp; 4760 strcpy(hw->name, "HDSP hwdep interface"); 4761 4762 hw->ops.ioctl = snd_hdsp_hwdep_ioctl; 4763 4764 return 0; 4765 } 4766 4767 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp) 4768 { 4769 struct snd_pcm *pcm; 4770 int err; 4771 4772 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0) 4773 return err; 4774 4775 hdsp->pcm = pcm; 4776 pcm->private_data = hdsp; 4777 strcpy(pcm->name, hdsp->card_name); 4778 4779 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops); 4780 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops); 4781 4782 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 4783 4784 return 0; 4785 } 4786 4787 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp) 4788 { 4789 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER; 4790 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register); 4791 } 4792 4793 static int snd_hdsp_enable_io (struct hdsp *hdsp) 4794 { 4795 int i; 4796 4797 if (hdsp_fifo_wait (hdsp, 0, 100)) { 4798 snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n"); 4799 return -EIO; 4800 } 4801 4802 for (i = 0; i < hdsp->max_channels; ++i) { 4803 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1); 4804 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1); 4805 } 4806 4807 return 0; 4808 } 4809 4810 static void snd_hdsp_initialize_channels(struct hdsp *hdsp) 4811 { 4812 int status, aebi_channels, aebo_channels; 4813 4814 switch (hdsp->io_type) { 4815 case Digiface: 4816 hdsp->card_name = "RME Hammerfall DSP + Digiface"; 4817 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS; 4818 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS; 4819 break; 4820 4821 case H9652: 4822 hdsp->card_name = "RME Hammerfall HDSP 9652"; 4823 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS; 4824 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS; 4825 break; 4826 4827 case H9632: 4828 status = hdsp_read(hdsp, HDSP_statusRegister); 4829 /* HDSP_AEBx bits are low when AEB are connected */ 4830 aebi_channels = (status & HDSP_AEBI) ? 0 : 4; 4831 aebo_channels = (status & HDSP_AEBO) ? 0 : 4; 4832 hdsp->card_name = "RME Hammerfall HDSP 9632"; 4833 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels; 4834 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels; 4835 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels; 4836 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels; 4837 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels; 4838 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels; 4839 break; 4840 4841 case Multiface: 4842 hdsp->card_name = "RME Hammerfall DSP + Multiface"; 4843 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS; 4844 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS; 4845 break; 4846 4847 default: 4848 /* should never get here */ 4849 break; 4850 } 4851 } 4852 4853 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp) 4854 { 4855 snd_hdsp_flush_midi_input (hdsp, 0); 4856 snd_hdsp_flush_midi_input (hdsp, 1); 4857 } 4858 4859 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp) 4860 { 4861 int err; 4862 4863 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) { 4864 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n"); 4865 return err; 4866 } 4867 4868 4869 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) { 4870 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n"); 4871 return err; 4872 } 4873 4874 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) { 4875 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) { 4876 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n"); 4877 return err; 4878 } 4879 } 4880 4881 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) { 4882 snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n"); 4883 return err; 4884 } 4885 4886 snd_hdsp_proc_init(hdsp); 4887 4888 hdsp->system_sample_rate = -1; 4889 hdsp->playback_pid = -1; 4890 hdsp->capture_pid = -1; 4891 hdsp->capture_substream = NULL; 4892 hdsp->playback_substream = NULL; 4893 4894 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) { 4895 snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n"); 4896 return err; 4897 } 4898 4899 if (!(hdsp->state & HDSP_InitializationComplete)) { 4900 strcpy(card->shortname, "Hammerfall DSP"); 4901 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 4902 hdsp->port, hdsp->irq); 4903 4904 if ((err = snd_card_register(card)) < 0) { 4905 snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n"); 4906 return err; 4907 } 4908 hdsp->state |= HDSP_InitializationComplete; 4909 } 4910 4911 return 0; 4912 } 4913 4914 #ifdef HDSP_FW_LOADER 4915 /* load firmware via hotplug fw loader */ 4916 static int hdsp_request_fw_loader(struct hdsp *hdsp) 4917 { 4918 const char *fwfile; 4919 const struct firmware *fw; 4920 int err; 4921 4922 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 4923 return 0; 4924 if (hdsp->io_type == Undefined) { 4925 if ((err = hdsp_get_iobox_version(hdsp)) < 0) 4926 return err; 4927 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) 4928 return 0; 4929 } 4930 4931 /* caution: max length of firmware filename is 30! */ 4932 switch (hdsp->io_type) { 4933 case Multiface: 4934 if (hdsp->firmware_rev == 0xa) 4935 fwfile = "multiface_firmware.bin"; 4936 else 4937 fwfile = "multiface_firmware_rev11.bin"; 4938 break; 4939 case Digiface: 4940 if (hdsp->firmware_rev == 0xa) 4941 fwfile = "digiface_firmware.bin"; 4942 else 4943 fwfile = "digiface_firmware_rev11.bin"; 4944 break; 4945 default: 4946 snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type); 4947 return -EINVAL; 4948 } 4949 4950 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) { 4951 snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile); 4952 return -ENOENT; 4953 } 4954 if (fw->size < sizeof(hdsp->firmware_cache)) { 4955 snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n", 4956 (int)fw->size, (int)sizeof(hdsp->firmware_cache)); 4957 release_firmware(fw); 4958 return -EINVAL; 4959 } 4960 4961 memcpy(hdsp->firmware_cache, fw->data, sizeof(hdsp->firmware_cache)); 4962 4963 release_firmware(fw); 4964 4965 hdsp->state |= HDSP_FirmwareCached; 4966 4967 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0) 4968 return err; 4969 4970 if (!(hdsp->state & HDSP_InitializationComplete)) { 4971 if ((err = snd_hdsp_enable_io(hdsp)) < 0) 4972 return err; 4973 4974 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) { 4975 snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n"); 4976 return err; 4977 } 4978 snd_hdsp_initialize_channels(hdsp); 4979 snd_hdsp_initialize_midi_flush(hdsp); 4980 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) { 4981 snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n"); 4982 return err; 4983 } 4984 } 4985 return 0; 4986 } 4987 #endif 4988 4989 static int __devinit snd_hdsp_create(struct snd_card *card, 4990 struct hdsp *hdsp) 4991 { 4992 struct pci_dev *pci = hdsp->pci; 4993 int err; 4994 int is_9652 = 0; 4995 int is_9632 = 0; 4996 4997 hdsp->irq = -1; 4998 hdsp->state = 0; 4999 hdsp->midi[0].rmidi = NULL; 5000 hdsp->midi[1].rmidi = NULL; 5001 hdsp->midi[0].input = NULL; 5002 hdsp->midi[1].input = NULL; 5003 hdsp->midi[0].output = NULL; 5004 hdsp->midi[1].output = NULL; 5005 hdsp->midi[0].pending = 0; 5006 hdsp->midi[1].pending = 0; 5007 spin_lock_init(&hdsp->midi[0].lock); 5008 spin_lock_init(&hdsp->midi[1].lock); 5009 hdsp->iobase = NULL; 5010 hdsp->control_register = 0; 5011 hdsp->control2_register = 0; 5012 hdsp->io_type = Undefined; 5013 hdsp->max_channels = 26; 5014 5015 hdsp->card = card; 5016 5017 spin_lock_init(&hdsp->lock); 5018 5019 tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp); 5020 5021 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev); 5022 hdsp->firmware_rev &= 0xff; 5023 5024 /* From Martin Bjoernsen : 5025 "It is important that the card's latency timer register in 5026 the PCI configuration space is set to a value much larger 5027 than 0 by the computer's BIOS or the driver. 5028 The windows driver always sets this 8 bit register [...] 5029 to its maximum 255 to avoid problems with some computers." 5030 */ 5031 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF); 5032 5033 strcpy(card->driver, "H-DSP"); 5034 strcpy(card->mixername, "Xilinx FPGA"); 5035 5036 if (hdsp->firmware_rev < 0xa) 5037 return -ENODEV; 5038 else if (hdsp->firmware_rev < 0x64) 5039 hdsp->card_name = "RME Hammerfall DSP"; 5040 else if (hdsp->firmware_rev < 0x96) { 5041 hdsp->card_name = "RME HDSP 9652"; 5042 is_9652 = 1; 5043 } else { 5044 hdsp->card_name = "RME HDSP 9632"; 5045 hdsp->max_channels = 16; 5046 is_9632 = 1; 5047 } 5048 5049 if ((err = pci_enable_device(pci)) < 0) 5050 return err; 5051 5052 pci_set_master(hdsp->pci); 5053 5054 if ((err = pci_request_regions(pci, "hdsp")) < 0) 5055 return err; 5056 hdsp->port = pci_resource_start(pci, 0); 5057 if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) { 5058 snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1); 5059 return -EBUSY; 5060 } 5061 5062 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED, 5063 "hdsp", hdsp)) { 5064 snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq); 5065 return -EBUSY; 5066 } 5067 5068 hdsp->irq = pci->irq; 5069 hdsp->precise_ptr = 0; 5070 hdsp->use_midi_tasklet = 1; 5071 hdsp->dds_value = 0; 5072 5073 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0) 5074 return err; 5075 5076 if (!is_9652 && !is_9632) { 5077 /* we wait a maximum of 10 seconds to let freshly 5078 * inserted cardbus cards do their hardware init */ 5079 err = hdsp_wait_for_iobox(hdsp, 1000, 10); 5080 5081 if (err < 0) 5082 return err; 5083 5084 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) { 5085 #ifdef HDSP_FW_LOADER 5086 if ((err = hdsp_request_fw_loader(hdsp)) < 0) 5087 /* we don't fail as this can happen 5088 if userspace is not ready for 5089 firmware upload 5090 */ 5091 snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n"); 5092 else 5093 /* init is complete, we return */ 5094 return 0; 5095 #endif 5096 /* we defer initialization */ 5097 snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n"); 5098 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) 5099 return err; 5100 return 0; 5101 } else { 5102 snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n"); 5103 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1) 5104 hdsp->io_type = Multiface; 5105 else 5106 hdsp->io_type = Digiface; 5107 } 5108 } 5109 5110 if ((err = snd_hdsp_enable_io(hdsp)) != 0) 5111 return err; 5112 5113 if (is_9652) 5114 hdsp->io_type = H9652; 5115 5116 if (is_9632) 5117 hdsp->io_type = H9632; 5118 5119 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0) 5120 return err; 5121 5122 snd_hdsp_initialize_channels(hdsp); 5123 snd_hdsp_initialize_midi_flush(hdsp); 5124 5125 hdsp->state |= HDSP_FirmwareLoaded; 5126 5127 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0) 5128 return err; 5129 5130 return 0; 5131 } 5132 5133 static int snd_hdsp_free(struct hdsp *hdsp) 5134 { 5135 if (hdsp->port) { 5136 /* stop the audio, and cancel all interrupts */ 5137 tasklet_kill(&hdsp->midi_tasklet); 5138 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable); 5139 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register); 5140 } 5141 5142 if (hdsp->irq >= 0) 5143 free_irq(hdsp->irq, (void *)hdsp); 5144 5145 snd_hdsp_free_buffers(hdsp); 5146 5147 if (hdsp->iobase) 5148 iounmap(hdsp->iobase); 5149 5150 if (hdsp->port) 5151 pci_release_regions(hdsp->pci); 5152 5153 pci_disable_device(hdsp->pci); 5154 return 0; 5155 } 5156 5157 static void snd_hdsp_card_free(struct snd_card *card) 5158 { 5159 struct hdsp *hdsp = card->private_data; 5160 5161 if (hdsp) 5162 snd_hdsp_free(hdsp); 5163 } 5164 5165 static int __devinit snd_hdsp_probe(struct pci_dev *pci, 5166 const struct pci_device_id *pci_id) 5167 { 5168 static int dev; 5169 struct hdsp *hdsp; 5170 struct snd_card *card; 5171 int err; 5172 5173 if (dev >= SNDRV_CARDS) 5174 return -ENODEV; 5175 if (!enable[dev]) { 5176 dev++; 5177 return -ENOENT; 5178 } 5179 5180 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 5181 sizeof(struct hdsp), &card); 5182 if (err < 0) 5183 return err; 5184 5185 hdsp = card->private_data; 5186 card->private_free = snd_hdsp_card_free; 5187 hdsp->dev = dev; 5188 hdsp->pci = pci; 5189 snd_card_set_dev(card, &pci->dev); 5190 5191 if ((err = snd_hdsp_create(card, hdsp)) < 0) { 5192 snd_card_free(card); 5193 return err; 5194 } 5195 5196 strcpy(card->shortname, "Hammerfall DSP"); 5197 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name, 5198 hdsp->port, hdsp->irq); 5199 5200 if ((err = snd_card_register(card)) < 0) { 5201 snd_card_free(card); 5202 return err; 5203 } 5204 pci_set_drvdata(pci, card); 5205 dev++; 5206 return 0; 5207 } 5208 5209 static void __devexit snd_hdsp_remove(struct pci_dev *pci) 5210 { 5211 snd_card_free(pci_get_drvdata(pci)); 5212 pci_set_drvdata(pci, NULL); 5213 } 5214 5215 static struct pci_driver driver = { 5216 .name = "RME Hammerfall DSP", 5217 .id_table = snd_hdsp_ids, 5218 .probe = snd_hdsp_probe, 5219 .remove = __devexit_p(snd_hdsp_remove), 5220 }; 5221 5222 static int __init alsa_card_hdsp_init(void) 5223 { 5224 return pci_register_driver(&driver); 5225 } 5226 5227 static void __exit alsa_card_hdsp_exit(void) 5228 { 5229 pci_unregister_driver(&driver); 5230 } 5231 5232 module_init(alsa_card_hdsp_init) 5233 module_exit(alsa_card_hdsp_exit) 5234