xref: /openbmc/linux/sound/pci/rme9652/hdsp.c (revision 8a10bc9d)
1 /*
2  *   ALSA driver for RME Hammerfall DSP audio interface(s)
3  *
4  *      Copyright (c) 2002  Paul Davis
5  *                          Marcus Andersson
6  *                          Thomas Charbonnel
7  *
8  *   This program is free software; you can redistribute it and/or modify
9  *   it under the terms of the GNU General Public License as published by
10  *   the Free Software Foundation; either version 2 of the License, or
11  *   (at your option) any later version.
12  *
13  *   This program is distributed in the hope that it will be useful,
14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *   GNU General Public License for more details.
17  *
18  *   You should have received a copy of the GNU General Public License
19  *   along with this program; if not, write to the Free Software
20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21  *
22  */
23 
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/pci.h>
28 #include <linux/firmware.h>
29 #include <linux/module.h>
30 #include <linux/math64.h>
31 #include <linux/vmalloc.h>
32 
33 #include <sound/core.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/info.h>
37 #include <sound/asoundef.h>
38 #include <sound/rawmidi.h>
39 #include <sound/hwdep.h>
40 #include <sound/initval.h>
41 #include <sound/hdsp.h>
42 
43 #include <asm/byteorder.h>
44 #include <asm/current.h>
45 #include <asm/io.h>
46 
47 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
48 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
49 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
50 
51 module_param_array(index, int, NULL, 0444);
52 MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
53 module_param_array(id, charp, NULL, 0444);
54 MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
55 module_param_array(enable, bool, NULL, 0444);
56 MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
57 MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
58 MODULE_DESCRIPTION("RME Hammerfall DSP");
59 MODULE_LICENSE("GPL");
60 MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
61 	        "{RME HDSP-9652},"
62 		"{RME HDSP-9632}}");
63 MODULE_FIRMWARE("rpm_firmware.bin");
64 MODULE_FIRMWARE("multiface_firmware.bin");
65 MODULE_FIRMWARE("multiface_firmware_rev11.bin");
66 MODULE_FIRMWARE("digiface_firmware.bin");
67 MODULE_FIRMWARE("digiface_firmware_rev11.bin");
68 
69 #define HDSP_MAX_CHANNELS        26
70 #define HDSP_MAX_DS_CHANNELS     14
71 #define HDSP_MAX_QS_CHANNELS     8
72 #define DIGIFACE_SS_CHANNELS     26
73 #define DIGIFACE_DS_CHANNELS     14
74 #define MULTIFACE_SS_CHANNELS    18
75 #define MULTIFACE_DS_CHANNELS    14
76 #define H9652_SS_CHANNELS        26
77 #define H9652_DS_CHANNELS        14
78 /* This does not include possible Analog Extension Boards
79    AEBs are detected at card initialization
80 */
81 #define H9632_SS_CHANNELS	 12
82 #define H9632_DS_CHANNELS	 8
83 #define H9632_QS_CHANNELS	 4
84 #define RPM_CHANNELS             6
85 
86 /* Write registers. These are defined as byte-offsets from the iobase value.
87  */
88 #define HDSP_resetPointer               0
89 #define HDSP_freqReg			0
90 #define HDSP_outputBufferAddress	32
91 #define HDSP_inputBufferAddress		36
92 #define HDSP_controlRegister		64
93 #define HDSP_interruptConfirmation	96
94 #define HDSP_outputEnable	  	128
95 #define HDSP_control2Reg		256
96 #define HDSP_midiDataOut0  		352
97 #define HDSP_midiDataOut1  		356
98 #define HDSP_fifoData  			368
99 #define HDSP_inputEnable	 	384
100 
101 /* Read registers. These are defined as byte-offsets from the iobase value
102  */
103 
104 #define HDSP_statusRegister    0
105 #define HDSP_timecode        128
106 #define HDSP_status2Register 192
107 #define HDSP_midiDataIn0     360
108 #define HDSP_midiDataIn1     364
109 #define HDSP_midiStatusOut0  384
110 #define HDSP_midiStatusOut1  388
111 #define HDSP_midiStatusIn0   392
112 #define HDSP_midiStatusIn1   396
113 #define HDSP_fifoStatus      400
114 
115 /* the meters are regular i/o-mapped registers, but offset
116    considerably from the rest. the peak registers are reset
117    when read; the least-significant 4 bits are full-scale counters;
118    the actual peak value is in the most-significant 24 bits.
119 */
120 
121 #define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
122 #define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
123 #define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
124 #define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
125 #define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */
126 
127 
128 /* This is for H9652 cards
129    Peak values are read downward from the base
130    Rms values are read upward
131    There are rms values for the outputs too
132    26*3 values are read in ss mode
133    14*3 in ds mode, with no gap between values
134 */
135 #define HDSP_9652_peakBase	7164
136 #define HDSP_9652_rmsBase	4096
137 
138 /* c.f. the hdsp_9632_meters_t struct */
139 #define HDSP_9632_metersBase	4096
140 
141 #define HDSP_IO_EXTENT     7168
142 
143 /* control2 register bits */
144 
145 #define HDSP_TMS                0x01
146 #define HDSP_TCK                0x02
147 #define HDSP_TDI                0x04
148 #define HDSP_JTAG               0x08
149 #define HDSP_PWDN               0x10
150 #define HDSP_PROGRAM	        0x020
151 #define HDSP_CONFIG_MODE_0	0x040
152 #define HDSP_CONFIG_MODE_1	0x080
153 #define HDSP_VERSION_BIT	(0x100 | HDSP_S_LOAD)
154 #define HDSP_BIGENDIAN_MODE     0x200
155 #define HDSP_RD_MULTIPLE        0x400
156 #define HDSP_9652_ENABLE_MIXER  0x800
157 #define HDSP_S200		0x800
158 #define HDSP_S300		(0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
159 #define HDSP_CYCLIC_MODE	0x1000
160 #define HDSP_TDO                0x10000000
161 
162 #define HDSP_S_PROGRAM	    (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
163 #define HDSP_S_LOAD	    (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
164 
165 /* Control Register bits */
166 
167 #define HDSP_Start                (1<<0)  /* start engine */
168 #define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
169 #define HDSP_Latency1             (1<<2)  /* [ see above ] */
170 #define HDSP_Latency2             (1<<3)  /* [ see above ] */
171 #define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
172 #define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
173 #define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
174 #define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
175 #define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
176 #define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
177 #define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
178 #define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
179 #define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
180 #define HDSP_SyncRef2             (1<<13)
181 #define HDSP_SPDIFInputSelect0    (1<<14)
182 #define HDSP_SPDIFInputSelect1    (1<<15)
183 #define HDSP_SyncRef0             (1<<16)
184 #define HDSP_SyncRef1             (1<<17)
185 #define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
186 #define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
187 #define HDSP_Midi0InterruptEnable (1<<22)
188 #define HDSP_Midi1InterruptEnable (1<<23)
189 #define HDSP_LineOut              (1<<24)
190 #define HDSP_ADGain0		  (1<<25) /* From here : H9632 specific */
191 #define HDSP_ADGain1		  (1<<26)
192 #define HDSP_DAGain0		  (1<<27)
193 #define HDSP_DAGain1		  (1<<28)
194 #define HDSP_PhoneGain0		  (1<<29)
195 #define HDSP_PhoneGain1		  (1<<30)
196 #define HDSP_QuadSpeed	  	  (1<<31)
197 
198 /* RPM uses some of the registers for special purposes */
199 #define HDSP_RPM_Inp12            0x04A00
200 #define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
201 #define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
202 #define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
203 #define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
204 #define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */
205 
206 #define HDSP_RPM_Inp34            0x32000
207 #define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
208 #define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
209 #define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
210 #define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
211 #define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */
212 
213 #define HDSP_RPM_Bypass           0x01000
214 
215 #define HDSP_RPM_Disconnect       0x00001
216 
217 #define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
218 #define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
219 #define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
220 #define HDSP_ADGainLowGain     0
221 
222 #define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
223 #define HDSP_DAGainHighGain      HDSP_DAGainMask
224 #define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
225 #define HDSP_DAGainMinus10dBV    0
226 
227 #define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
228 #define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
229 #define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
230 #define HDSP_PhoneGainMinus12dB  0
231 
232 #define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
233 #define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
234 
235 #define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
236 #define HDSP_SPDIFInputADAT1    0
237 #define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
238 #define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
239 #define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
240 
241 #define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
242 #define HDSP_SyncRef_ADAT1       0
243 #define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
244 #define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
245 #define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
246 #define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
247 #define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)
248 
249 /* Sample Clock Sources */
250 
251 #define HDSP_CLOCK_SOURCE_AUTOSYNC           0
252 #define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
253 #define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
254 #define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
255 #define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
256 #define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
257 #define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
258 #define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
259 #define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
260 #define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9
261 
262 /* Preferred sync reference choices - used by "pref_sync_ref" control switch */
263 
264 #define HDSP_SYNC_FROM_WORD      0
265 #define HDSP_SYNC_FROM_SPDIF     1
266 #define HDSP_SYNC_FROM_ADAT1     2
267 #define HDSP_SYNC_FROM_ADAT_SYNC 3
268 #define HDSP_SYNC_FROM_ADAT2     4
269 #define HDSP_SYNC_FROM_ADAT3     5
270 
271 /* SyncCheck status */
272 
273 #define HDSP_SYNC_CHECK_NO_LOCK 0
274 #define HDSP_SYNC_CHECK_LOCK    1
275 #define HDSP_SYNC_CHECK_SYNC	2
276 
277 /* AutoSync references - used by "autosync_ref" control switch */
278 
279 #define HDSP_AUTOSYNC_FROM_WORD      0
280 #define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
281 #define HDSP_AUTOSYNC_FROM_SPDIF     2
282 #define HDSP_AUTOSYNC_FROM_NONE	     3
283 #define HDSP_AUTOSYNC_FROM_ADAT1     4
284 #define HDSP_AUTOSYNC_FROM_ADAT2     5
285 #define HDSP_AUTOSYNC_FROM_ADAT3     6
286 
287 /* Possible sources of S/PDIF input */
288 
289 #define HDSP_SPDIFIN_OPTICAL  0	/* optical  (ADAT1) */
290 #define HDSP_SPDIFIN_COAXIAL  1	/* coaxial (RCA) */
291 #define HDSP_SPDIFIN_INTERNAL 2	/* internal (CDROM) */
292 #define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/
293 
294 #define HDSP_Frequency32KHz    HDSP_Frequency0
295 #define HDSP_Frequency44_1KHz  HDSP_Frequency1
296 #define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
297 #define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
298 #define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
299 #define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
300 /* For H9632 cards */
301 #define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
302 #define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
303 #define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
304 /* RME says n = 104857600000000, but in the windows MADI driver, I see:
305 	return 104857600000000 / rate; // 100 MHz
306 	return 110100480000000 / rate; // 105 MHz
307 */
308 #define DDS_NUMERATOR 104857600000000ULL;  /*  =  2^20 * 10^8 */
309 
310 #define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
311 #define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)
312 
313 #define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
314 #define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
315 
316 /* Status Register bits */
317 
318 #define HDSP_audioIRQPending    (1<<0)
319 #define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
320 #define HDSP_spdifFrequency3	HDSP_Lock2 /* this is for H9632 only */
321 #define HDSP_Lock1              (1<<2)
322 #define HDSP_Lock0              (1<<3)
323 #define HDSP_SPDIFSync          (1<<4)
324 #define HDSP_TimecodeLock       (1<<5)
325 #define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
326 #define HDSP_Sync2              (1<<16)
327 #define HDSP_Sync1              (1<<17)
328 #define HDSP_Sync0              (1<<18)
329 #define HDSP_DoubleSpeedStatus  (1<<19)
330 #define HDSP_ConfigError        (1<<20)
331 #define HDSP_DllError           (1<<21)
332 #define HDSP_spdifFrequency0    (1<<22)
333 #define HDSP_spdifFrequency1    (1<<23)
334 #define HDSP_spdifFrequency2    (1<<24)
335 #define HDSP_SPDIFErrorFlag     (1<<25)
336 #define HDSP_BufferID           (1<<26)
337 #define HDSP_TimecodeSync       (1<<27)
338 #define HDSP_AEBO          	(1<<28) /* H9632 specific Analog Extension Boards */
339 #define HDSP_AEBI		(1<<29) /* 0 = present, 1 = absent */
340 #define HDSP_midi0IRQPending    (1<<30)
341 #define HDSP_midi1IRQPending    (1<<31)
342 
343 #define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
344 #define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
345 				      HDSP_spdifFrequency1|\
346 				      HDSP_spdifFrequency2|\
347 				      HDSP_spdifFrequency3)
348 
349 #define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
350 #define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
351 #define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
352 
353 #define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
354 #define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
355 #define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
356 
357 /* This is for H9632 cards */
358 #define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
359 				     HDSP_spdifFrequency1|\
360 				     HDSP_spdifFrequency2)
361 #define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
362 #define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
363 
364 /* Status2 Register bits */
365 
366 #define HDSP_version0     (1<<0)
367 #define HDSP_version1     (1<<1)
368 #define HDSP_version2     (1<<2)
369 #define HDSP_wc_lock      (1<<3)
370 #define HDSP_wc_sync      (1<<4)
371 #define HDSP_inp_freq0    (1<<5)
372 #define HDSP_inp_freq1    (1<<6)
373 #define HDSP_inp_freq2    (1<<7)
374 #define HDSP_SelSyncRef0  (1<<8)
375 #define HDSP_SelSyncRef1  (1<<9)
376 #define HDSP_SelSyncRef2  (1<<10)
377 
378 #define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
379 
380 #define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
381 #define HDSP_systemFrequency32   (HDSP_inp_freq0)
382 #define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
383 #define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
384 #define HDSP_systemFrequency64   (HDSP_inp_freq2)
385 #define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
386 #define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
387 /* FIXME : more values for 9632 cards ? */
388 
389 #define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
390 #define HDSP_SelSyncRef_ADAT1      0
391 #define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
392 #define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
393 #define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
394 #define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
395 #define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
396 
397 /* Card state flags */
398 
399 #define HDSP_InitializationComplete  (1<<0)
400 #define HDSP_FirmwareLoaded	     (1<<1)
401 #define HDSP_FirmwareCached	     (1<<2)
402 
403 /* FIFO wait times, defined in terms of 1/10ths of msecs */
404 
405 #define HDSP_LONG_WAIT	 5000
406 #define HDSP_SHORT_WAIT  30
407 
408 #define UNITY_GAIN                       32768
409 #define MINUS_INFINITY_GAIN              0
410 
411 /* the size of a substream (1 mono data stream) */
412 
413 #define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
414 #define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)
415 
416 /* the size of the area we need to allocate for DMA transfers. the
417    size is the same regardless of the number of channels - the
418    Multiface still uses the same memory area.
419 
420    Note that we allocate 1 more channel than is apparently needed
421    because the h/w seems to write 1 byte beyond the end of the last
422    page. Sigh.
423 */
424 
425 #define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
426 #define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
427 
428 #define HDSP_FIRMWARE_SIZE	(24413 * 4)
429 
430 struct hdsp_9632_meters {
431     u32 input_peak[16];
432     u32 playback_peak[16];
433     u32 output_peak[16];
434     u32 xxx_peak[16];
435     u32 padding[64];
436     u32 input_rms_low[16];
437     u32 playback_rms_low[16];
438     u32 output_rms_low[16];
439     u32 xxx_rms_low[16];
440     u32 input_rms_high[16];
441     u32 playback_rms_high[16];
442     u32 output_rms_high[16];
443     u32 xxx_rms_high[16];
444 };
445 
446 struct hdsp_midi {
447     struct hdsp             *hdsp;
448     int                      id;
449     struct snd_rawmidi           *rmidi;
450     struct snd_rawmidi_substream *input;
451     struct snd_rawmidi_substream *output;
452     char                     istimer; /* timer in use */
453     struct timer_list	     timer;
454     spinlock_t               lock;
455     int			     pending;
456 };
457 
458 struct hdsp {
459 	spinlock_t            lock;
460 	struct snd_pcm_substream *capture_substream;
461 	struct snd_pcm_substream *playback_substream;
462         struct hdsp_midi      midi[2];
463 	struct tasklet_struct midi_tasklet;
464 	int		      use_midi_tasklet;
465 	int                   precise_ptr;
466 	u32                   control_register;	     /* cached value */
467 	u32                   control2_register;     /* cached value */
468 	u32                   creg_spdif;
469 	u32                   creg_spdif_stream;
470 	int                   clock_source_locked;
471 	char                 *card_name;	 /* digiface/multiface/rpm */
472 	enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
473         unsigned short        firmware_rev;
474 	unsigned short	      state;		     /* stores state bits */
475 	const struct firmware *firmware;
476 	u32                  *fw_uploaded;
477 	size_t                period_bytes; 	     /* guess what this is */
478 	unsigned char	      max_channels;
479 	unsigned char	      qs_in_channels;	     /* quad speed mode for H9632 */
480 	unsigned char         ds_in_channels;
481 	unsigned char         ss_in_channels;	    /* different for multiface/digiface */
482 	unsigned char	      qs_out_channels;
483 	unsigned char         ds_out_channels;
484 	unsigned char         ss_out_channels;
485 
486 	struct snd_dma_buffer capture_dma_buf;
487 	struct snd_dma_buffer playback_dma_buf;
488 	unsigned char        *capture_buffer;	    /* suitably aligned address */
489 	unsigned char        *playback_buffer;	    /* suitably aligned address */
490 
491 	pid_t                 capture_pid;
492 	pid_t                 playback_pid;
493 	int                   running;
494 	int                   system_sample_rate;
495 	char                 *channel_map;
496 	int                   dev;
497 	int                   irq;
498 	unsigned long         port;
499         void __iomem         *iobase;
500 	struct snd_card *card;
501 	struct snd_pcm *pcm;
502 	struct snd_hwdep          *hwdep;
503 	struct pci_dev       *pci;
504 	struct snd_kcontrol *spdif_ctl;
505         unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
506 	unsigned int          dds_value; /* last value written to freq register */
507 };
508 
509 /* These tables map the ALSA channels 1..N to the channels that we
510    need to use in order to find the relevant channel buffer. RME
511    refer to this kind of mapping as between "the ADAT channel and
512    the DMA channel." We index it using the logical audio channel,
513    and the value is the DMA channel (i.e. channel buffer number)
514    where the data for that channel can be read/written from/to.
515 */
516 
517 static char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
518 	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
519 	18, 19, 20, 21, 22, 23, 24, 25
520 };
521 
522 static char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
523 	/* Analog */
524 	0, 1, 2, 3, 4, 5, 6, 7,
525 	/* ADAT 2 */
526 	16, 17, 18, 19, 20, 21, 22, 23,
527 	/* SPDIF */
528 	24, 25,
529 	-1, -1, -1, -1, -1, -1, -1, -1
530 };
531 
532 static char channel_map_ds[HDSP_MAX_CHANNELS] = {
533 	/* ADAT channels are remapped */
534 	1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
535 	/* channels 12 and 13 are S/PDIF */
536 	24, 25,
537 	/* others don't exist */
538 	-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
539 };
540 
541 static char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
542 	/* ADAT channels */
543 	0, 1, 2, 3, 4, 5, 6, 7,
544 	/* SPDIF */
545 	8, 9,
546 	/* Analog */
547 	10, 11,
548 	/* AO4S-192 and AI4S-192 extension boards */
549 	12, 13, 14, 15,
550 	/* others don't exist */
551 	-1, -1, -1, -1, -1, -1, -1, -1,
552 	-1, -1
553 };
554 
555 static char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
556 	/* ADAT */
557 	1, 3, 5, 7,
558 	/* SPDIF */
559 	8, 9,
560 	/* Analog */
561 	10, 11,
562 	/* AO4S-192 and AI4S-192 extension boards */
563 	12, 13, 14, 15,
564 	/* others don't exist */
565 	-1, -1, -1, -1, -1, -1, -1, -1,
566 	-1, -1, -1, -1, -1, -1
567 };
568 
569 static char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
570 	/* ADAT is disabled in this mode */
571 	/* SPDIF */
572 	8, 9,
573 	/* Analog */
574 	10, 11,
575 	/* AO4S-192 and AI4S-192 extension boards */
576 	12, 13, 14, 15,
577 	/* others don't exist */
578 	-1, -1, -1, -1, -1, -1, -1, -1,
579 	-1, -1, -1, -1, -1, -1, -1, -1,
580 	-1, -1
581 };
582 
583 static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
584 {
585 	dmab->dev.type = SNDRV_DMA_TYPE_DEV;
586 	dmab->dev.dev = snd_dma_pci_data(pci);
587 	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
588 				size, dmab) < 0)
589 		return -ENOMEM;
590 	return 0;
591 }
592 
593 static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
594 {
595 	if (dmab->area)
596 		snd_dma_free_pages(dmab);
597 }
598 
599 
600 static DEFINE_PCI_DEVICE_TABLE(snd_hdsp_ids) = {
601 	{
602 		.vendor = PCI_VENDOR_ID_XILINX,
603 		.device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
604 		.subvendor = PCI_ANY_ID,
605 		.subdevice = PCI_ANY_ID,
606 	}, /* RME Hammerfall-DSP */
607 	{ 0, },
608 };
609 
610 MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
611 
612 /* prototypes */
613 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
614 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
615 static int snd_hdsp_enable_io (struct hdsp *hdsp);
616 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
617 static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
618 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
619 static int hdsp_autosync_ref(struct hdsp *hdsp);
620 static int snd_hdsp_set_defaults(struct hdsp *hdsp);
621 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
622 
623 static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
624 {
625 	switch (hdsp->io_type) {
626 	case Multiface:
627 	case Digiface:
628 	case RPM:
629 	default:
630 		if (hdsp->firmware_rev == 0xa)
631 			return (64 * out) + (32 + (in));
632 		else
633 			return (52 * out) + (26 + (in));
634 	case H9632:
635 		return (32 * out) + (16 + (in));
636 	case H9652:
637 		return (52 * out) + (26 + (in));
638 	}
639 }
640 
641 static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
642 {
643 	switch (hdsp->io_type) {
644 	case Multiface:
645 	case Digiface:
646 	case RPM:
647 	default:
648 		if (hdsp->firmware_rev == 0xa)
649 			return (64 * out) + in;
650 		else
651 			return (52 * out) + in;
652 	case H9632:
653 		return (32 * out) + in;
654 	case H9652:
655 		return (52 * out) + in;
656 	}
657 }
658 
659 static void hdsp_write(struct hdsp *hdsp, int reg, int val)
660 {
661 	writel(val, hdsp->iobase + reg);
662 }
663 
664 static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
665 {
666 	return readl (hdsp->iobase + reg);
667 }
668 
669 static int hdsp_check_for_iobox (struct hdsp *hdsp)
670 {
671 	int i;
672 
673 	if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
674 	for (i = 0; i < 500; i++) {
675 		if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
676 					HDSP_ConfigError)) {
677 			if (i) {
678 				snd_printd("Hammerfall-DSP: IO box found after %d ms\n",
679 						(20 * i));
680 			}
681 			return 0;
682 		}
683 		msleep(20);
684 	}
685 	snd_printk(KERN_ERR "Hammerfall-DSP: no IO box connected!\n");
686 	hdsp->state &= ~HDSP_FirmwareLoaded;
687 	return -EIO;
688 }
689 
690 static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
691 			       unsigned int delay)
692 {
693 	unsigned int i;
694 
695 	if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
696 		return 0;
697 
698 	for (i = 0; i != loops; ++i) {
699 		if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
700 			msleep(delay);
701 		else {
702 			snd_printd("Hammerfall-DSP: iobox found after %ums!\n",
703 				   i * delay);
704 			return 0;
705 		}
706 	}
707 
708 	snd_printk("Hammerfall-DSP: no IO box connected!\n");
709 	hdsp->state &= ~HDSP_FirmwareLoaded;
710 	return -EIO;
711 }
712 
713 static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
714 
715 	int i;
716 	unsigned long flags;
717 	const u32 *cache;
718 
719 	if (hdsp->fw_uploaded)
720 		cache = hdsp->fw_uploaded;
721 	else {
722 		if (!hdsp->firmware)
723 			return -ENODEV;
724 		cache = (u32 *)hdsp->firmware->data;
725 		if (!cache)
726 			return -ENODEV;
727 	}
728 
729 	if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
730 
731 		snd_printk ("Hammerfall-DSP: loading firmware\n");
732 
733 		hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
734 		hdsp_write (hdsp, HDSP_fifoData, 0);
735 
736 		if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
737 			snd_printk ("Hammerfall-DSP: timeout waiting for download preparation\n");
738 			hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
739 			return -EIO;
740 		}
741 
742 		hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
743 
744 		for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
745 			hdsp_write(hdsp, HDSP_fifoData, cache[i]);
746 			if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
747 				snd_printk ("Hammerfall-DSP: timeout during firmware loading\n");
748 				hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
749 				return -EIO;
750 			}
751 		}
752 
753 		hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
754 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
755 
756 		ssleep(3);
757 #ifdef SNDRV_BIG_ENDIAN
758 		hdsp->control2_register = HDSP_BIGENDIAN_MODE;
759 #else
760 		hdsp->control2_register = 0;
761 #endif
762 		hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
763 		snd_printk ("Hammerfall-DSP: finished firmware loading\n");
764 
765 	}
766 	if (hdsp->state & HDSP_InitializationComplete) {
767 		snd_printk(KERN_INFO "Hammerfall-DSP: firmware loaded from cache, restoring defaults\n");
768 		spin_lock_irqsave(&hdsp->lock, flags);
769 		snd_hdsp_set_defaults(hdsp);
770 		spin_unlock_irqrestore(&hdsp->lock, flags);
771 	}
772 
773 	hdsp->state |= HDSP_FirmwareLoaded;
774 
775 	return 0;
776 }
777 
778 static int hdsp_get_iobox_version (struct hdsp *hdsp)
779 {
780 	if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
781 
782 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
783 		hdsp_write(hdsp, HDSP_fifoData, 0);
784 
785 		if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
786 			hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
787 			hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
788 		}
789 
790 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
791 		hdsp_write (hdsp, HDSP_fifoData, 0);
792 		if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
793 			hdsp->io_type = Multiface;
794 			snd_printk("Hammerfall-DSP: Multiface found\n");
795 			return 0;
796 		}
797 
798 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
799 		hdsp_write(hdsp, HDSP_fifoData, 0);
800 		if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
801 			hdsp->io_type = Digiface;
802 			snd_printk("Hammerfall-DSP: Digiface found\n");
803 			return 0;
804 		}
805 
806 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
807 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
808 		hdsp_write(hdsp, HDSP_fifoData, 0);
809 		if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
810 			hdsp->io_type = Multiface;
811 			snd_printk("Hammerfall-DSP: Multiface found\n");
812 			return 0;
813 		}
814 
815 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
816 		hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
817 		hdsp_write(hdsp, HDSP_fifoData, 0);
818 		if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
819 			hdsp->io_type = Multiface;
820 			snd_printk("Hammerfall-DSP: Multiface found\n");
821 			return 0;
822 		}
823 
824 		hdsp->io_type = RPM;
825 		snd_printk("Hammerfall-DSP: RPM found\n");
826 		return 0;
827 	} else {
828 		/* firmware was already loaded, get iobox type */
829 		if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
830 			hdsp->io_type = RPM;
831 		else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
832 			hdsp->io_type = Multiface;
833 		else
834 			hdsp->io_type = Digiface;
835 	}
836 	return 0;
837 }
838 
839 
840 static int hdsp_request_fw_loader(struct hdsp *hdsp);
841 
842 static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
843 {
844 	if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
845 		return 0;
846 	if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
847 		hdsp->state &= ~HDSP_FirmwareLoaded;
848 		if (! load_on_demand)
849 			return -EIO;
850 		snd_printk(KERN_ERR "Hammerfall-DSP: firmware not present.\n");
851 		/* try to load firmware */
852 		if (! (hdsp->state & HDSP_FirmwareCached)) {
853 			if (! hdsp_request_fw_loader(hdsp))
854 				return 0;
855 			snd_printk(KERN_ERR
856 				   "Hammerfall-DSP: No firmware loaded nor "
857 				   "cached, please upload firmware.\n");
858 			return -EIO;
859 		}
860 		if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
861 			snd_printk(KERN_ERR
862 				   "Hammerfall-DSP: Firmware loading from "
863 				   "cache failed, please upload manually.\n");
864 			return -EIO;
865 		}
866 	}
867 	return 0;
868 }
869 
870 
871 static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
872 {
873 	int i;
874 
875 	/* the fifoStatus registers reports on how many words
876 	   are available in the command FIFO.
877 	*/
878 
879 	for (i = 0; i < timeout; i++) {
880 
881 		if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
882 			return 0;
883 
884 		/* not very friendly, but we only do this during a firmware
885 		   load and changing the mixer, so we just put up with it.
886 		*/
887 
888 		udelay (100);
889 	}
890 
891 	snd_printk ("Hammerfall-DSP: wait for FIFO status <= %d failed after %d iterations\n",
892 		    count, timeout);
893 	return -1;
894 }
895 
896 static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
897 {
898 	if (addr >= HDSP_MATRIX_MIXER_SIZE)
899 		return 0;
900 
901 	return hdsp->mixer_matrix[addr];
902 }
903 
904 static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
905 {
906 	unsigned int ad;
907 
908 	if (addr >= HDSP_MATRIX_MIXER_SIZE)
909 		return -1;
910 
911 	if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
912 
913 		/* from martin bjornsen:
914 
915 		   "You can only write dwords to the
916 		   mixer memory which contain two
917 		   mixer values in the low and high
918 		   word. So if you want to change
919 		   value 0 you have to read value 1
920 		   from the cache and write both to
921 		   the first dword in the mixer
922 		   memory."
923 		*/
924 
925 		if (hdsp->io_type == H9632 && addr >= 512)
926 			return 0;
927 
928 		if (hdsp->io_type == H9652 && addr >= 1352)
929 			return 0;
930 
931 		hdsp->mixer_matrix[addr] = data;
932 
933 
934 		/* `addr' addresses a 16-bit wide address, but
935 		   the address space accessed via hdsp_write
936 		   uses byte offsets. put another way, addr
937 		   varies from 0 to 1351, but to access the
938 		   corresponding memory location, we need
939 		   to access 0 to 2703 ...
940 		*/
941 		ad = addr/2;
942 
943 		hdsp_write (hdsp, 4096 + (ad*4),
944 			    (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
945 			    hdsp->mixer_matrix[addr&0x7fe]);
946 
947 		return 0;
948 
949 	} else {
950 
951 		ad = (addr << 16) + data;
952 
953 		if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
954 			return -1;
955 
956 		hdsp_write (hdsp, HDSP_fifoData, ad);
957 		hdsp->mixer_matrix[addr] = data;
958 
959 	}
960 
961 	return 0;
962 }
963 
964 static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
965 {
966 	unsigned long flags;
967 	int ret = 1;
968 
969 	spin_lock_irqsave(&hdsp->lock, flags);
970 	if ((hdsp->playback_pid != hdsp->capture_pid) &&
971 	    (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
972 		ret = 0;
973 	spin_unlock_irqrestore(&hdsp->lock, flags);
974 	return ret;
975 }
976 
977 static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
978 {
979 	unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
980 	unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
981 
982 	/* For the 9632, the mask is different */
983 	if (hdsp->io_type == H9632)
984 		 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
985 
986 	if (status & HDSP_SPDIFErrorFlag)
987 		return 0;
988 
989 	switch (rate_bits) {
990 	case HDSP_spdifFrequency32KHz: return 32000;
991 	case HDSP_spdifFrequency44_1KHz: return 44100;
992 	case HDSP_spdifFrequency48KHz: return 48000;
993 	case HDSP_spdifFrequency64KHz: return 64000;
994 	case HDSP_spdifFrequency88_2KHz: return 88200;
995 	case HDSP_spdifFrequency96KHz: return 96000;
996 	case HDSP_spdifFrequency128KHz:
997 		if (hdsp->io_type == H9632) return 128000;
998 		break;
999 	case HDSP_spdifFrequency176_4KHz:
1000 		if (hdsp->io_type == H9632) return 176400;
1001 		break;
1002 	case HDSP_spdifFrequency192KHz:
1003 		if (hdsp->io_type == H9632) return 192000;
1004 		break;
1005 	default:
1006 		break;
1007 	}
1008 	snd_printk ("Hammerfall-DSP: unknown spdif frequency status; bits = 0x%x, status = 0x%x\n", rate_bits, status);
1009 	return 0;
1010 }
1011 
1012 static int hdsp_external_sample_rate(struct hdsp *hdsp)
1013 {
1014 	unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
1015 	unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
1016 
1017 	/* For the 9632 card, there seems to be no bit for indicating external
1018 	 * sample rate greater than 96kHz. The card reports the corresponding
1019 	 * single speed. So the best means seems to get spdif rate when
1020 	 * autosync reference is spdif */
1021 	if (hdsp->io_type == H9632 &&
1022 	    hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1023 		 return hdsp_spdif_sample_rate(hdsp);
1024 
1025 	switch (rate_bits) {
1026 	case HDSP_systemFrequency32:   return 32000;
1027 	case HDSP_systemFrequency44_1: return 44100;
1028 	case HDSP_systemFrequency48:   return 48000;
1029 	case HDSP_systemFrequency64:   return 64000;
1030 	case HDSP_systemFrequency88_2: return 88200;
1031 	case HDSP_systemFrequency96:   return 96000;
1032 	default:
1033 		return 0;
1034 	}
1035 }
1036 
1037 static void hdsp_compute_period_size(struct hdsp *hdsp)
1038 {
1039 	hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1040 }
1041 
1042 static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1043 {
1044 	int position;
1045 
1046 	position = hdsp_read(hdsp, HDSP_statusRegister);
1047 
1048 	if (!hdsp->precise_ptr)
1049 		return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1050 
1051 	position &= HDSP_BufferPositionMask;
1052 	position /= 4;
1053 	position &= (hdsp->period_bytes/2) - 1;
1054 	return position;
1055 }
1056 
1057 static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1058 {
1059 	hdsp_write (hdsp, HDSP_resetPointer, 0);
1060 	if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1061 		/* HDSP_resetPointer = HDSP_freqReg, which is strange and
1062 		 * requires (?) to write again DDS value after a reset pointer
1063 		 * (at least, it works like this) */
1064 		hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1065 }
1066 
1067 static void hdsp_start_audio(struct hdsp *s)
1068 {
1069 	s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1070 	hdsp_write(s, HDSP_controlRegister, s->control_register);
1071 }
1072 
1073 static void hdsp_stop_audio(struct hdsp *s)
1074 {
1075 	s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1076 	hdsp_write(s, HDSP_controlRegister, s->control_register);
1077 }
1078 
1079 static void hdsp_silence_playback(struct hdsp *hdsp)
1080 {
1081 	memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1082 }
1083 
1084 static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1085 {
1086 	int n;
1087 
1088 	spin_lock_irq(&s->lock);
1089 
1090 	frames >>= 7;
1091 	n = 0;
1092 	while (frames) {
1093 		n++;
1094 		frames >>= 1;
1095 	}
1096 
1097 	s->control_register &= ~HDSP_LatencyMask;
1098 	s->control_register |= hdsp_encode_latency(n);
1099 
1100 	hdsp_write(s, HDSP_controlRegister, s->control_register);
1101 
1102 	hdsp_compute_period_size(s);
1103 
1104 	spin_unlock_irq(&s->lock);
1105 
1106 	return 0;
1107 }
1108 
1109 static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1110 {
1111 	u64 n;
1112 
1113 	if (rate >= 112000)
1114 		rate /= 4;
1115 	else if (rate >= 56000)
1116 		rate /= 2;
1117 
1118 	n = DDS_NUMERATOR;
1119 	n = div_u64(n, rate);
1120 	/* n should be less than 2^32 for being written to FREQ register */
1121 	snd_BUG_ON(n >> 32);
1122 	/* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
1123 	   value to write it after a reset */
1124 	hdsp->dds_value = n;
1125 	hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1126 }
1127 
1128 static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1129 {
1130 	int reject_if_open = 0;
1131 	int current_rate;
1132 	int rate_bits;
1133 
1134 	/* ASSUMPTION: hdsp->lock is either held, or
1135 	   there is no need for it (e.g. during module
1136 	   initialization).
1137 	*/
1138 
1139 	if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1140 		if (called_internally) {
1141 			/* request from ctl or card initialization */
1142 			snd_printk(KERN_ERR "Hammerfall-DSP: device is not running as a clock master: cannot set sample rate.\n");
1143 			return -1;
1144 		} else {
1145 			/* hw_param request while in AutoSync mode */
1146 			int external_freq = hdsp_external_sample_rate(hdsp);
1147 			int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1148 
1149 			if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1150 				snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in double speed mode\n");
1151 			else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1152 				snd_printk(KERN_INFO "Hammerfall-DSP: Detected ADAT in quad speed mode\n");
1153 			else if (rate != external_freq) {
1154 				snd_printk(KERN_INFO "Hammerfall-DSP: No AutoSync source for requested rate\n");
1155 				return -1;
1156 			}
1157 		}
1158 	}
1159 
1160 	current_rate = hdsp->system_sample_rate;
1161 
1162 	/* Changing from a "single speed" to a "double speed" rate is
1163 	   not allowed if any substreams are open. This is because
1164 	   such a change causes a shift in the location of
1165 	   the DMA buffers and a reduction in the number of available
1166 	   buffers.
1167 
1168 	   Note that a similar but essentially insoluble problem
1169 	   exists for externally-driven rate changes. All we can do
1170 	   is to flag rate changes in the read/write routines.  */
1171 
1172 	if (rate > 96000 && hdsp->io_type != H9632)
1173 		return -EINVAL;
1174 
1175 	switch (rate) {
1176 	case 32000:
1177 		if (current_rate > 48000)
1178 			reject_if_open = 1;
1179 		rate_bits = HDSP_Frequency32KHz;
1180 		break;
1181 	case 44100:
1182 		if (current_rate > 48000)
1183 			reject_if_open = 1;
1184 		rate_bits = HDSP_Frequency44_1KHz;
1185 		break;
1186 	case 48000:
1187 		if (current_rate > 48000)
1188 			reject_if_open = 1;
1189 		rate_bits = HDSP_Frequency48KHz;
1190 		break;
1191 	case 64000:
1192 		if (current_rate <= 48000 || current_rate > 96000)
1193 			reject_if_open = 1;
1194 		rate_bits = HDSP_Frequency64KHz;
1195 		break;
1196 	case 88200:
1197 		if (current_rate <= 48000 || current_rate > 96000)
1198 			reject_if_open = 1;
1199 		rate_bits = HDSP_Frequency88_2KHz;
1200 		break;
1201 	case 96000:
1202 		if (current_rate <= 48000 || current_rate > 96000)
1203 			reject_if_open = 1;
1204 		rate_bits = HDSP_Frequency96KHz;
1205 		break;
1206 	case 128000:
1207 		if (current_rate < 128000)
1208 			reject_if_open = 1;
1209 		rate_bits = HDSP_Frequency128KHz;
1210 		break;
1211 	case 176400:
1212 		if (current_rate < 128000)
1213 			reject_if_open = 1;
1214 		rate_bits = HDSP_Frequency176_4KHz;
1215 		break;
1216 	case 192000:
1217 		if (current_rate < 128000)
1218 			reject_if_open = 1;
1219 		rate_bits = HDSP_Frequency192KHz;
1220 		break;
1221 	default:
1222 		return -EINVAL;
1223 	}
1224 
1225 	if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1226 		snd_printk ("Hammerfall-DSP: cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1227 			    hdsp->capture_pid,
1228 			    hdsp->playback_pid);
1229 		return -EBUSY;
1230 	}
1231 
1232 	hdsp->control_register &= ~HDSP_FrequencyMask;
1233 	hdsp->control_register |= rate_bits;
1234 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1235 
1236 	/* For HDSP9632 rev 152, need to set DDS value in FREQ register */
1237 	if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1238 		hdsp_set_dds_value(hdsp, rate);
1239 
1240 	if (rate >= 128000) {
1241 		hdsp->channel_map = channel_map_H9632_qs;
1242 	} else if (rate > 48000) {
1243 		if (hdsp->io_type == H9632)
1244 			hdsp->channel_map = channel_map_H9632_ds;
1245 		else
1246 			hdsp->channel_map = channel_map_ds;
1247 	} else {
1248 		switch (hdsp->io_type) {
1249 		case RPM:
1250 		case Multiface:
1251 			hdsp->channel_map = channel_map_mf_ss;
1252 			break;
1253 		case Digiface:
1254 		case H9652:
1255 			hdsp->channel_map = channel_map_df_ss;
1256 			break;
1257 		case H9632:
1258 			hdsp->channel_map = channel_map_H9632_ss;
1259 			break;
1260 		default:
1261 			/* should never happen */
1262 			break;
1263 		}
1264 	}
1265 
1266 	hdsp->system_sample_rate = rate;
1267 
1268 	return 0;
1269 }
1270 
1271 /*----------------------------------------------------------------------------
1272    MIDI
1273   ----------------------------------------------------------------------------*/
1274 
1275 static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1276 {
1277 	/* the hardware already does the relevant bit-mask with 0xff */
1278 	if (id)
1279 		return hdsp_read(hdsp, HDSP_midiDataIn1);
1280 	else
1281 		return hdsp_read(hdsp, HDSP_midiDataIn0);
1282 }
1283 
1284 static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1285 {
1286 	/* the hardware already does the relevant bit-mask with 0xff */
1287 	if (id)
1288 		hdsp_write(hdsp, HDSP_midiDataOut1, val);
1289 	else
1290 		hdsp_write(hdsp, HDSP_midiDataOut0, val);
1291 }
1292 
1293 static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1294 {
1295 	if (id)
1296 		return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1297 	else
1298 		return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1299 }
1300 
1301 static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1302 {
1303 	int fifo_bytes_used;
1304 
1305 	if (id)
1306 		fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1307 	else
1308 		fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1309 
1310 	if (fifo_bytes_used < 128)
1311 		return  128 - fifo_bytes_used;
1312 	else
1313 		return 0;
1314 }
1315 
1316 static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1317 {
1318 	while (snd_hdsp_midi_input_available (hdsp, id))
1319 		snd_hdsp_midi_read_byte (hdsp, id);
1320 }
1321 
1322 static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1323 {
1324 	unsigned long flags;
1325 	int n_pending;
1326 	int to_write;
1327 	int i;
1328 	unsigned char buf[128];
1329 
1330 	/* Output is not interrupt driven */
1331 
1332 	spin_lock_irqsave (&hmidi->lock, flags);
1333 	if (hmidi->output) {
1334 		if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1335 			if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1336 				if (n_pending > (int)sizeof (buf))
1337 					n_pending = sizeof (buf);
1338 
1339 				if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1340 					for (i = 0; i < to_write; ++i)
1341 						snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1342 				}
1343 			}
1344 		}
1345 	}
1346 	spin_unlock_irqrestore (&hmidi->lock, flags);
1347 	return 0;
1348 }
1349 
1350 static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1351 {
1352 	unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
1353 	unsigned long flags;
1354 	int n_pending;
1355 	int i;
1356 
1357 	spin_lock_irqsave (&hmidi->lock, flags);
1358 	if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1359 		if (hmidi->input) {
1360 			if (n_pending > (int)sizeof (buf))
1361 				n_pending = sizeof (buf);
1362 			for (i = 0; i < n_pending; ++i)
1363 				buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1364 			if (n_pending)
1365 				snd_rawmidi_receive (hmidi->input, buf, n_pending);
1366 		} else {
1367 			/* flush the MIDI input FIFO */
1368 			while (--n_pending)
1369 				snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1370 		}
1371 	}
1372 	hmidi->pending = 0;
1373 	if (hmidi->id)
1374 		hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1375 	else
1376 		hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1377 	hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1378 	spin_unlock_irqrestore (&hmidi->lock, flags);
1379 	return snd_hdsp_midi_output_write (hmidi);
1380 }
1381 
1382 static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1383 {
1384 	struct hdsp *hdsp;
1385 	struct hdsp_midi *hmidi;
1386 	unsigned long flags;
1387 	u32 ie;
1388 
1389 	hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1390 	hdsp = hmidi->hdsp;
1391 	ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1392 	spin_lock_irqsave (&hdsp->lock, flags);
1393 	if (up) {
1394 		if (!(hdsp->control_register & ie)) {
1395 			snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1396 			hdsp->control_register |= ie;
1397 		}
1398 	} else {
1399 		hdsp->control_register &= ~ie;
1400 		tasklet_kill(&hdsp->midi_tasklet);
1401 	}
1402 
1403 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1404 	spin_unlock_irqrestore (&hdsp->lock, flags);
1405 }
1406 
1407 static void snd_hdsp_midi_output_timer(unsigned long data)
1408 {
1409 	struct hdsp_midi *hmidi = (struct hdsp_midi *) data;
1410 	unsigned long flags;
1411 
1412 	snd_hdsp_midi_output_write(hmidi);
1413 	spin_lock_irqsave (&hmidi->lock, flags);
1414 
1415 	/* this does not bump hmidi->istimer, because the
1416 	   kernel automatically removed the timer when it
1417 	   expired, and we are now adding it back, thus
1418 	   leaving istimer wherever it was set before.
1419 	*/
1420 
1421 	if (hmidi->istimer) {
1422 		hmidi->timer.expires = 1 + jiffies;
1423 		add_timer(&hmidi->timer);
1424 	}
1425 
1426 	spin_unlock_irqrestore (&hmidi->lock, flags);
1427 }
1428 
1429 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1430 {
1431 	struct hdsp_midi *hmidi;
1432 	unsigned long flags;
1433 
1434 	hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1435 	spin_lock_irqsave (&hmidi->lock, flags);
1436 	if (up) {
1437 		if (!hmidi->istimer) {
1438 			init_timer(&hmidi->timer);
1439 			hmidi->timer.function = snd_hdsp_midi_output_timer;
1440 			hmidi->timer.data = (unsigned long) hmidi;
1441 			hmidi->timer.expires = 1 + jiffies;
1442 			add_timer(&hmidi->timer);
1443 			hmidi->istimer++;
1444 		}
1445 	} else {
1446 		if (hmidi->istimer && --hmidi->istimer <= 0)
1447 			del_timer (&hmidi->timer);
1448 	}
1449 	spin_unlock_irqrestore (&hmidi->lock, flags);
1450 	if (up)
1451 		snd_hdsp_midi_output_write(hmidi);
1452 }
1453 
1454 static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1455 {
1456 	struct hdsp_midi *hmidi;
1457 
1458 	hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1459 	spin_lock_irq (&hmidi->lock);
1460 	snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1461 	hmidi->input = substream;
1462 	spin_unlock_irq (&hmidi->lock);
1463 
1464 	return 0;
1465 }
1466 
1467 static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1468 {
1469 	struct hdsp_midi *hmidi;
1470 
1471 	hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1472 	spin_lock_irq (&hmidi->lock);
1473 	hmidi->output = substream;
1474 	spin_unlock_irq (&hmidi->lock);
1475 
1476 	return 0;
1477 }
1478 
1479 static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1480 {
1481 	struct hdsp_midi *hmidi;
1482 
1483 	snd_hdsp_midi_input_trigger (substream, 0);
1484 
1485 	hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1486 	spin_lock_irq (&hmidi->lock);
1487 	hmidi->input = NULL;
1488 	spin_unlock_irq (&hmidi->lock);
1489 
1490 	return 0;
1491 }
1492 
1493 static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1494 {
1495 	struct hdsp_midi *hmidi;
1496 
1497 	snd_hdsp_midi_output_trigger (substream, 0);
1498 
1499 	hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1500 	spin_lock_irq (&hmidi->lock);
1501 	hmidi->output = NULL;
1502 	spin_unlock_irq (&hmidi->lock);
1503 
1504 	return 0;
1505 }
1506 
1507 static struct snd_rawmidi_ops snd_hdsp_midi_output =
1508 {
1509 	.open =		snd_hdsp_midi_output_open,
1510 	.close =	snd_hdsp_midi_output_close,
1511 	.trigger =	snd_hdsp_midi_output_trigger,
1512 };
1513 
1514 static struct snd_rawmidi_ops snd_hdsp_midi_input =
1515 {
1516 	.open =		snd_hdsp_midi_input_open,
1517 	.close =	snd_hdsp_midi_input_close,
1518 	.trigger =	snd_hdsp_midi_input_trigger,
1519 };
1520 
1521 static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1522 {
1523 	char buf[32];
1524 
1525 	hdsp->midi[id].id = id;
1526 	hdsp->midi[id].rmidi = NULL;
1527 	hdsp->midi[id].input = NULL;
1528 	hdsp->midi[id].output = NULL;
1529 	hdsp->midi[id].hdsp = hdsp;
1530 	hdsp->midi[id].istimer = 0;
1531 	hdsp->midi[id].pending = 0;
1532 	spin_lock_init (&hdsp->midi[id].lock);
1533 
1534 	sprintf (buf, "%s MIDI %d", card->shortname, id+1);
1535 	if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1536 		return -1;
1537 
1538 	sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1539 	hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1540 
1541 	snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1542 	snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1543 
1544 	hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1545 		SNDRV_RAWMIDI_INFO_INPUT |
1546 		SNDRV_RAWMIDI_INFO_DUPLEX;
1547 
1548 	return 0;
1549 }
1550 
1551 /*-----------------------------------------------------------------------------
1552   Control Interface
1553   ----------------------------------------------------------------------------*/
1554 
1555 static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1556 {
1557 	u32 val = 0;
1558 	val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1559 	val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1560 	if (val & HDSP_SPDIFProfessional)
1561 		val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1562 	else
1563 		val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1564 	return val;
1565 }
1566 
1567 static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1568 {
1569 	aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1570 			 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1571 	if (val & HDSP_SPDIFProfessional)
1572 		aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1573 	else
1574 		aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1575 }
1576 
1577 static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1578 {
1579 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1580 	uinfo->count = 1;
1581 	return 0;
1582 }
1583 
1584 static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1585 {
1586 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1587 
1588 	snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1589 	return 0;
1590 }
1591 
1592 static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1593 {
1594 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1595 	int change;
1596 	u32 val;
1597 
1598 	val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1599 	spin_lock_irq(&hdsp->lock);
1600 	change = val != hdsp->creg_spdif;
1601 	hdsp->creg_spdif = val;
1602 	spin_unlock_irq(&hdsp->lock);
1603 	return change;
1604 }
1605 
1606 static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1607 {
1608 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1609 	uinfo->count = 1;
1610 	return 0;
1611 }
1612 
1613 static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1614 {
1615 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1616 
1617 	snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1618 	return 0;
1619 }
1620 
1621 static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1622 {
1623 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1624 	int change;
1625 	u32 val;
1626 
1627 	val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1628 	spin_lock_irq(&hdsp->lock);
1629 	change = val != hdsp->creg_spdif_stream;
1630 	hdsp->creg_spdif_stream = val;
1631 	hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1632 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1633 	spin_unlock_irq(&hdsp->lock);
1634 	return change;
1635 }
1636 
1637 static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1638 {
1639 	uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1640 	uinfo->count = 1;
1641 	return 0;
1642 }
1643 
1644 static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1645 {
1646 	ucontrol->value.iec958.status[0] = kcontrol->private_value;
1647 	return 0;
1648 }
1649 
1650 #define HDSP_SPDIF_IN(xname, xindex) \
1651 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1652   .name = xname, \
1653   .index = xindex, \
1654   .info = snd_hdsp_info_spdif_in, \
1655   .get = snd_hdsp_get_spdif_in, \
1656   .put = snd_hdsp_put_spdif_in }
1657 
1658 static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1659 {
1660 	return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1661 }
1662 
1663 static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1664 {
1665 	hdsp->control_register &= ~HDSP_SPDIFInputMask;
1666 	hdsp->control_register |= hdsp_encode_spdif_in(in);
1667 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1668 	return 0;
1669 }
1670 
1671 static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1672 {
1673 	static char *texts[4] = {"Optical", "Coaxial", "Internal", "AES"};
1674 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1675 
1676 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1677 	uinfo->count = 1;
1678 	uinfo->value.enumerated.items = ((hdsp->io_type == H9632) ? 4 : 3);
1679 	if (uinfo->value.enumerated.item > ((hdsp->io_type == H9632) ? 3 : 2))
1680 		uinfo->value.enumerated.item = ((hdsp->io_type == H9632) ? 3 : 2);
1681 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1682 	return 0;
1683 }
1684 
1685 static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1686 {
1687 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1688 
1689 	ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1690 	return 0;
1691 }
1692 
1693 static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1694 {
1695 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1696 	int change;
1697 	unsigned int val;
1698 
1699 	if (!snd_hdsp_use_is_exclusive(hdsp))
1700 		return -EBUSY;
1701 	val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1702 	spin_lock_irq(&hdsp->lock);
1703 	change = val != hdsp_spdif_in(hdsp);
1704 	if (change)
1705 		hdsp_set_spdif_input(hdsp, val);
1706 	spin_unlock_irq(&hdsp->lock);
1707 	return change;
1708 }
1709 
1710 #define HDSP_TOGGLE_SETTING(xname, xindex) \
1711 {   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1712 	.name = xname, \
1713 	.private_value = xindex, \
1714 	.info = snd_hdsp_info_toggle_setting, \
1715 	.get = snd_hdsp_get_toggle_setting, \
1716 	.put = snd_hdsp_put_toggle_setting \
1717 }
1718 
1719 static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1720 {
1721 	return (hdsp->control_register & regmask) ? 1 : 0;
1722 }
1723 
1724 static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1725 {
1726 	if (out)
1727 		hdsp->control_register |= regmask;
1728 	else
1729 		hdsp->control_register &= ~regmask;
1730 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1731 
1732 	return 0;
1733 }
1734 
1735 #define snd_hdsp_info_toggle_setting		   snd_ctl_boolean_mono_info
1736 
1737 static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1738 		struct snd_ctl_elem_value *ucontrol)
1739 {
1740 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1741 	u32 regmask = kcontrol->private_value;
1742 
1743 	spin_lock_irq(&hdsp->lock);
1744 	ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1745 	spin_unlock_irq(&hdsp->lock);
1746 	return 0;
1747 }
1748 
1749 static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1750 		struct snd_ctl_elem_value *ucontrol)
1751 {
1752 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1753 	u32 regmask = kcontrol->private_value;
1754 	int change;
1755 	unsigned int val;
1756 
1757 	if (!snd_hdsp_use_is_exclusive(hdsp))
1758 		return -EBUSY;
1759 	val = ucontrol->value.integer.value[0] & 1;
1760 	spin_lock_irq(&hdsp->lock);
1761 	change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1762 	if (change)
1763 		hdsp_set_toggle_setting(hdsp, regmask, val);
1764 	spin_unlock_irq(&hdsp->lock);
1765 	return change;
1766 }
1767 
1768 #define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1769 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1770   .name = xname, \
1771   .index = xindex, \
1772   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1773   .info = snd_hdsp_info_spdif_sample_rate, \
1774   .get = snd_hdsp_get_spdif_sample_rate \
1775 }
1776 
1777 static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1778 {
1779 	static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1780 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1781 
1782 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1783 	uinfo->count = 1;
1784 	uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7;
1785 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1786 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1787 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1788 	return 0;
1789 }
1790 
1791 static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1792 {
1793 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1794 
1795 	switch (hdsp_spdif_sample_rate(hdsp)) {
1796 	case 32000:
1797 		ucontrol->value.enumerated.item[0] = 0;
1798 		break;
1799 	case 44100:
1800 		ucontrol->value.enumerated.item[0] = 1;
1801 		break;
1802 	case 48000:
1803 		ucontrol->value.enumerated.item[0] = 2;
1804 		break;
1805 	case 64000:
1806 		ucontrol->value.enumerated.item[0] = 3;
1807 		break;
1808 	case 88200:
1809 		ucontrol->value.enumerated.item[0] = 4;
1810 		break;
1811 	case 96000:
1812 		ucontrol->value.enumerated.item[0] = 5;
1813 		break;
1814 	case 128000:
1815 		ucontrol->value.enumerated.item[0] = 7;
1816 		break;
1817 	case 176400:
1818 		ucontrol->value.enumerated.item[0] = 8;
1819 		break;
1820 	case 192000:
1821 		ucontrol->value.enumerated.item[0] = 9;
1822 		break;
1823 	default:
1824 		ucontrol->value.enumerated.item[0] = 6;
1825 	}
1826 	return 0;
1827 }
1828 
1829 #define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1830 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1831   .name = xname, \
1832   .index = xindex, \
1833   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1834   .info = snd_hdsp_info_system_sample_rate, \
1835   .get = snd_hdsp_get_system_sample_rate \
1836 }
1837 
1838 static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1839 {
1840 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1841 	uinfo->count = 1;
1842 	return 0;
1843 }
1844 
1845 static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1846 {
1847 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1848 
1849 	ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1850 	return 0;
1851 }
1852 
1853 #define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1854 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1855   .name = xname, \
1856   .index = xindex, \
1857   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1858   .info = snd_hdsp_info_autosync_sample_rate, \
1859   .get = snd_hdsp_get_autosync_sample_rate \
1860 }
1861 
1862 static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1863 {
1864 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1865 	static char *texts[] = {"32000", "44100", "48000", "64000", "88200", "96000", "None", "128000", "176400", "192000"};
1866 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1867 	uinfo->count = 1;
1868 	uinfo->value.enumerated.items = (hdsp->io_type == H9632) ? 10 : 7 ;
1869 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1870 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1871 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1872 	return 0;
1873 }
1874 
1875 static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1876 {
1877 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1878 
1879 	switch (hdsp_external_sample_rate(hdsp)) {
1880 	case 32000:
1881 		ucontrol->value.enumerated.item[0] = 0;
1882 		break;
1883 	case 44100:
1884 		ucontrol->value.enumerated.item[0] = 1;
1885 		break;
1886 	case 48000:
1887 		ucontrol->value.enumerated.item[0] = 2;
1888 		break;
1889 	case 64000:
1890 		ucontrol->value.enumerated.item[0] = 3;
1891 		break;
1892 	case 88200:
1893 		ucontrol->value.enumerated.item[0] = 4;
1894 		break;
1895 	case 96000:
1896 		ucontrol->value.enumerated.item[0] = 5;
1897 		break;
1898 	case 128000:
1899 		ucontrol->value.enumerated.item[0] = 7;
1900 		break;
1901 	case 176400:
1902 		ucontrol->value.enumerated.item[0] = 8;
1903 		break;
1904 	case 192000:
1905 		ucontrol->value.enumerated.item[0] = 9;
1906 		break;
1907 	default:
1908 		ucontrol->value.enumerated.item[0] = 6;
1909 	}
1910 	return 0;
1911 }
1912 
1913 #define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1914 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1915   .name = xname, \
1916   .index = xindex, \
1917   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1918   .info = snd_hdsp_info_system_clock_mode, \
1919   .get = snd_hdsp_get_system_clock_mode \
1920 }
1921 
1922 static int hdsp_system_clock_mode(struct hdsp *hdsp)
1923 {
1924 	if (hdsp->control_register & HDSP_ClockModeMaster)
1925 		return 0;
1926 	else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1927 			return 0;
1928 	return 1;
1929 }
1930 
1931 static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1932 {
1933 	static char *texts[] = {"Master", "Slave" };
1934 
1935 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1936 	uinfo->count = 1;
1937 	uinfo->value.enumerated.items = 2;
1938 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
1939 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1940 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1941 	return 0;
1942 }
1943 
1944 static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1945 {
1946 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1947 
1948 	ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1949 	return 0;
1950 }
1951 
1952 #define HDSP_CLOCK_SOURCE(xname, xindex) \
1953 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1954   .name = xname, \
1955   .index = xindex, \
1956   .info = snd_hdsp_info_clock_source, \
1957   .get = snd_hdsp_get_clock_source, \
1958   .put = snd_hdsp_put_clock_source \
1959 }
1960 
1961 static int hdsp_clock_source(struct hdsp *hdsp)
1962 {
1963 	if (hdsp->control_register & HDSP_ClockModeMaster) {
1964 		switch (hdsp->system_sample_rate) {
1965 		case 32000:
1966 			return 1;
1967 		case 44100:
1968 			return 2;
1969 		case 48000:
1970 			return 3;
1971 		case 64000:
1972 			return 4;
1973 		case 88200:
1974 			return 5;
1975 		case 96000:
1976 			return 6;
1977 		case 128000:
1978 			return 7;
1979 		case 176400:
1980 			return 8;
1981 		case 192000:
1982 			return 9;
1983 		default:
1984 			return 3;
1985 		}
1986 	} else {
1987 		return 0;
1988 	}
1989 }
1990 
1991 static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1992 {
1993 	int rate;
1994 	switch (mode) {
1995 	case HDSP_CLOCK_SOURCE_AUTOSYNC:
1996 		if (hdsp_external_sample_rate(hdsp) != 0) {
1997 		    if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1998 			hdsp->control_register &= ~HDSP_ClockModeMaster;
1999 			hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2000 			return 0;
2001 		    }
2002 		}
2003 		return -1;
2004 	case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
2005 		rate = 32000;
2006 		break;
2007 	case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
2008 		rate = 44100;
2009 		break;
2010 	case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
2011 		rate = 48000;
2012 		break;
2013 	case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
2014 		rate = 64000;
2015 		break;
2016 	case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
2017 		rate = 88200;
2018 		break;
2019 	case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
2020 		rate = 96000;
2021 		break;
2022 	case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
2023 		rate = 128000;
2024 		break;
2025 	case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
2026 		rate = 176400;
2027 		break;
2028 	case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2029 		rate = 192000;
2030 		break;
2031 	default:
2032 		rate = 48000;
2033 	}
2034 	hdsp->control_register |= HDSP_ClockModeMaster;
2035 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2036 	hdsp_set_rate(hdsp, rate, 1);
2037 	return 0;
2038 }
2039 
2040 static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2041 {
2042 	static char *texts[] = {"AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz", "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz", "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz", "Internal 192.0 KHz" };
2043 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2044 
2045 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2046 	uinfo->count = 1;
2047 	if (hdsp->io_type == H9632)
2048 	    uinfo->value.enumerated.items = 10;
2049 	else
2050 	    uinfo->value.enumerated.items = 7;
2051 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2052 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2053 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2054 	return 0;
2055 }
2056 
2057 static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2058 {
2059 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2060 
2061 	ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2062 	return 0;
2063 }
2064 
2065 static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2066 {
2067 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2068 	int change;
2069 	int val;
2070 
2071 	if (!snd_hdsp_use_is_exclusive(hdsp))
2072 		return -EBUSY;
2073 	val = ucontrol->value.enumerated.item[0];
2074 	if (val < 0) val = 0;
2075 	if (hdsp->io_type == H9632) {
2076 		if (val > 9)
2077 			val = 9;
2078 	} else {
2079 		if (val > 6)
2080 			val = 6;
2081 	}
2082 	spin_lock_irq(&hdsp->lock);
2083 	if (val != hdsp_clock_source(hdsp))
2084 		change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2085 	else
2086 		change = 0;
2087 	spin_unlock_irq(&hdsp->lock);
2088 	return change;
2089 }
2090 
2091 #define snd_hdsp_info_clock_source_lock		snd_ctl_boolean_mono_info
2092 
2093 static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2094 {
2095 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2096 
2097 	ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2098 	return 0;
2099 }
2100 
2101 static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2102 {
2103 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2104 	int change;
2105 
2106 	change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2107 	if (change)
2108 		hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2109 	return change;
2110 }
2111 
2112 #define HDSP_DA_GAIN(xname, xindex) \
2113 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2114   .name = xname, \
2115   .index = xindex, \
2116   .info = snd_hdsp_info_da_gain, \
2117   .get = snd_hdsp_get_da_gain, \
2118   .put = snd_hdsp_put_da_gain \
2119 }
2120 
2121 static int hdsp_da_gain(struct hdsp *hdsp)
2122 {
2123 	switch (hdsp->control_register & HDSP_DAGainMask) {
2124 	case HDSP_DAGainHighGain:
2125 		return 0;
2126 	case HDSP_DAGainPlus4dBu:
2127 		return 1;
2128 	case HDSP_DAGainMinus10dBV:
2129 		return 2;
2130 	default:
2131 		return 1;
2132 	}
2133 }
2134 
2135 static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2136 {
2137 	hdsp->control_register &= ~HDSP_DAGainMask;
2138 	switch (mode) {
2139 	case 0:
2140 		hdsp->control_register |= HDSP_DAGainHighGain;
2141 		break;
2142 	case 1:
2143 		hdsp->control_register |= HDSP_DAGainPlus4dBu;
2144 		break;
2145 	case 2:
2146 		hdsp->control_register |= HDSP_DAGainMinus10dBV;
2147 		break;
2148 	default:
2149 		return -1;
2150 
2151 	}
2152 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2153 	return 0;
2154 }
2155 
2156 static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2157 {
2158 	static char *texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2159 
2160 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2161 	uinfo->count = 1;
2162 	uinfo->value.enumerated.items = 3;
2163 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2164 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2165 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2166 	return 0;
2167 }
2168 
2169 static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2170 {
2171 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2172 
2173 	ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2174 	return 0;
2175 }
2176 
2177 static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2178 {
2179 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2180 	int change;
2181 	int val;
2182 
2183 	if (!snd_hdsp_use_is_exclusive(hdsp))
2184 		return -EBUSY;
2185 	val = ucontrol->value.enumerated.item[0];
2186 	if (val < 0) val = 0;
2187 	if (val > 2) val = 2;
2188 	spin_lock_irq(&hdsp->lock);
2189 	if (val != hdsp_da_gain(hdsp))
2190 		change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2191 	else
2192 		change = 0;
2193 	spin_unlock_irq(&hdsp->lock);
2194 	return change;
2195 }
2196 
2197 #define HDSP_AD_GAIN(xname, xindex) \
2198 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2199   .name = xname, \
2200   .index = xindex, \
2201   .info = snd_hdsp_info_ad_gain, \
2202   .get = snd_hdsp_get_ad_gain, \
2203   .put = snd_hdsp_put_ad_gain \
2204 }
2205 
2206 static int hdsp_ad_gain(struct hdsp *hdsp)
2207 {
2208 	switch (hdsp->control_register & HDSP_ADGainMask) {
2209 	case HDSP_ADGainMinus10dBV:
2210 		return 0;
2211 	case HDSP_ADGainPlus4dBu:
2212 		return 1;
2213 	case HDSP_ADGainLowGain:
2214 		return 2;
2215 	default:
2216 		return 1;
2217 	}
2218 }
2219 
2220 static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2221 {
2222 	hdsp->control_register &= ~HDSP_ADGainMask;
2223 	switch (mode) {
2224 	case 0:
2225 		hdsp->control_register |= HDSP_ADGainMinus10dBV;
2226 		break;
2227 	case 1:
2228 		hdsp->control_register |= HDSP_ADGainPlus4dBu;
2229 		break;
2230 	case 2:
2231 		hdsp->control_register |= HDSP_ADGainLowGain;
2232 		break;
2233 	default:
2234 		return -1;
2235 
2236 	}
2237 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2238 	return 0;
2239 }
2240 
2241 static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2242 {
2243 	static char *texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2244 
2245 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2246 	uinfo->count = 1;
2247 	uinfo->value.enumerated.items = 3;
2248 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2249 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2250 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2251 	return 0;
2252 }
2253 
2254 static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2255 {
2256 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2257 
2258 	ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2259 	return 0;
2260 }
2261 
2262 static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2263 {
2264 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2265 	int change;
2266 	int val;
2267 
2268 	if (!snd_hdsp_use_is_exclusive(hdsp))
2269 		return -EBUSY;
2270 	val = ucontrol->value.enumerated.item[0];
2271 	if (val < 0) val = 0;
2272 	if (val > 2) val = 2;
2273 	spin_lock_irq(&hdsp->lock);
2274 	if (val != hdsp_ad_gain(hdsp))
2275 		change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2276 	else
2277 		change = 0;
2278 	spin_unlock_irq(&hdsp->lock);
2279 	return change;
2280 }
2281 
2282 #define HDSP_PHONE_GAIN(xname, xindex) \
2283 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2284   .name = xname, \
2285   .index = xindex, \
2286   .info = snd_hdsp_info_phone_gain, \
2287   .get = snd_hdsp_get_phone_gain, \
2288   .put = snd_hdsp_put_phone_gain \
2289 }
2290 
2291 static int hdsp_phone_gain(struct hdsp *hdsp)
2292 {
2293 	switch (hdsp->control_register & HDSP_PhoneGainMask) {
2294 	case HDSP_PhoneGain0dB:
2295 		return 0;
2296 	case HDSP_PhoneGainMinus6dB:
2297 		return 1;
2298 	case HDSP_PhoneGainMinus12dB:
2299 		return 2;
2300 	default:
2301 		return 0;
2302 	}
2303 }
2304 
2305 static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2306 {
2307 	hdsp->control_register &= ~HDSP_PhoneGainMask;
2308 	switch (mode) {
2309 	case 0:
2310 		hdsp->control_register |= HDSP_PhoneGain0dB;
2311 		break;
2312 	case 1:
2313 		hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2314 		break;
2315 	case 2:
2316 		hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2317 		break;
2318 	default:
2319 		return -1;
2320 
2321 	}
2322 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2323 	return 0;
2324 }
2325 
2326 static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2327 {
2328 	static char *texts[] = {"0 dB", "-6 dB", "-12 dB"};
2329 
2330 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2331 	uinfo->count = 1;
2332 	uinfo->value.enumerated.items = 3;
2333 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2334 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2335 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2336 	return 0;
2337 }
2338 
2339 static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2340 {
2341 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2342 
2343 	ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2344 	return 0;
2345 }
2346 
2347 static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2348 {
2349 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2350 	int change;
2351 	int val;
2352 
2353 	if (!snd_hdsp_use_is_exclusive(hdsp))
2354 		return -EBUSY;
2355 	val = ucontrol->value.enumerated.item[0];
2356 	if (val < 0) val = 0;
2357 	if (val > 2) val = 2;
2358 	spin_lock_irq(&hdsp->lock);
2359 	if (val != hdsp_phone_gain(hdsp))
2360 		change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2361 	else
2362 		change = 0;
2363 	spin_unlock_irq(&hdsp->lock);
2364 	return change;
2365 }
2366 
2367 #define HDSP_PREF_SYNC_REF(xname, xindex) \
2368 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2369   .name = xname, \
2370   .index = xindex, \
2371   .info = snd_hdsp_info_pref_sync_ref, \
2372   .get = snd_hdsp_get_pref_sync_ref, \
2373   .put = snd_hdsp_put_pref_sync_ref \
2374 }
2375 
2376 static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2377 {
2378 	/* Notice that this looks at the requested sync source,
2379 	   not the one actually in use.
2380 	*/
2381 
2382 	switch (hdsp->control_register & HDSP_SyncRefMask) {
2383 	case HDSP_SyncRef_ADAT1:
2384 		return HDSP_SYNC_FROM_ADAT1;
2385 	case HDSP_SyncRef_ADAT2:
2386 		return HDSP_SYNC_FROM_ADAT2;
2387 	case HDSP_SyncRef_ADAT3:
2388 		return HDSP_SYNC_FROM_ADAT3;
2389 	case HDSP_SyncRef_SPDIF:
2390 		return HDSP_SYNC_FROM_SPDIF;
2391 	case HDSP_SyncRef_WORD:
2392 		return HDSP_SYNC_FROM_WORD;
2393 	case HDSP_SyncRef_ADAT_SYNC:
2394 		return HDSP_SYNC_FROM_ADAT_SYNC;
2395 	default:
2396 		return HDSP_SYNC_FROM_WORD;
2397 	}
2398 	return 0;
2399 }
2400 
2401 static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2402 {
2403 	hdsp->control_register &= ~HDSP_SyncRefMask;
2404 	switch (pref) {
2405 	case HDSP_SYNC_FROM_ADAT1:
2406 		hdsp->control_register &= ~HDSP_SyncRefMask; /* clear SyncRef bits */
2407 		break;
2408 	case HDSP_SYNC_FROM_ADAT2:
2409 		hdsp->control_register |= HDSP_SyncRef_ADAT2;
2410 		break;
2411 	case HDSP_SYNC_FROM_ADAT3:
2412 		hdsp->control_register |= HDSP_SyncRef_ADAT3;
2413 		break;
2414 	case HDSP_SYNC_FROM_SPDIF:
2415 		hdsp->control_register |= HDSP_SyncRef_SPDIF;
2416 		break;
2417 	case HDSP_SYNC_FROM_WORD:
2418 		hdsp->control_register |= HDSP_SyncRef_WORD;
2419 		break;
2420 	case HDSP_SYNC_FROM_ADAT_SYNC:
2421 		hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2422 		break;
2423 	default:
2424 		return -1;
2425 	}
2426 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2427 	return 0;
2428 }
2429 
2430 static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2431 {
2432 	static char *texts[] = {"Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3" };
2433 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2434 
2435 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2436 	uinfo->count = 1;
2437 
2438 	switch (hdsp->io_type) {
2439 	case Digiface:
2440 	case H9652:
2441 		uinfo->value.enumerated.items = 6;
2442 		break;
2443 	case Multiface:
2444 		uinfo->value.enumerated.items = 4;
2445 		break;
2446 	case H9632:
2447 		uinfo->value.enumerated.items = 3;
2448 		break;
2449 	default:
2450 		return -EINVAL;
2451 	}
2452 
2453 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2454 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2455 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2456 	return 0;
2457 }
2458 
2459 static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2460 {
2461 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2462 
2463 	ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2464 	return 0;
2465 }
2466 
2467 static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2468 {
2469 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2470 	int change, max;
2471 	unsigned int val;
2472 
2473 	if (!snd_hdsp_use_is_exclusive(hdsp))
2474 		return -EBUSY;
2475 
2476 	switch (hdsp->io_type) {
2477 	case Digiface:
2478 	case H9652:
2479 		max = 6;
2480 		break;
2481 	case Multiface:
2482 		max = 4;
2483 		break;
2484 	case H9632:
2485 		max = 3;
2486 		break;
2487 	default:
2488 		return -EIO;
2489 	}
2490 
2491 	val = ucontrol->value.enumerated.item[0] % max;
2492 	spin_lock_irq(&hdsp->lock);
2493 	change = (int)val != hdsp_pref_sync_ref(hdsp);
2494 	hdsp_set_pref_sync_ref(hdsp, val);
2495 	spin_unlock_irq(&hdsp->lock);
2496 	return change;
2497 }
2498 
2499 #define HDSP_AUTOSYNC_REF(xname, xindex) \
2500 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2501   .name = xname, \
2502   .index = xindex, \
2503   .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2504   .info = snd_hdsp_info_autosync_ref, \
2505   .get = snd_hdsp_get_autosync_ref, \
2506 }
2507 
2508 static int hdsp_autosync_ref(struct hdsp *hdsp)
2509 {
2510 	/* This looks at the autosync selected sync reference */
2511 	unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2512 
2513 	switch (status2 & HDSP_SelSyncRefMask) {
2514 	case HDSP_SelSyncRef_WORD:
2515 		return HDSP_AUTOSYNC_FROM_WORD;
2516 	case HDSP_SelSyncRef_ADAT_SYNC:
2517 		return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2518 	case HDSP_SelSyncRef_SPDIF:
2519 		return HDSP_AUTOSYNC_FROM_SPDIF;
2520 	case HDSP_SelSyncRefMask:
2521 		return HDSP_AUTOSYNC_FROM_NONE;
2522 	case HDSP_SelSyncRef_ADAT1:
2523 		return HDSP_AUTOSYNC_FROM_ADAT1;
2524 	case HDSP_SelSyncRef_ADAT2:
2525 		return HDSP_AUTOSYNC_FROM_ADAT2;
2526 	case HDSP_SelSyncRef_ADAT3:
2527 		return HDSP_AUTOSYNC_FROM_ADAT3;
2528 	default:
2529 		return HDSP_AUTOSYNC_FROM_WORD;
2530 	}
2531 	return 0;
2532 }
2533 
2534 static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2535 {
2536 	static char *texts[] = {"Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3" };
2537 
2538 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2539 	uinfo->count = 1;
2540 	uinfo->value.enumerated.items = 7;
2541 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2542 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2543 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2544 	return 0;
2545 }
2546 
2547 static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2548 {
2549 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2550 
2551 	ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2552 	return 0;
2553 }
2554 
2555 #define HDSP_PRECISE_POINTER(xname, xindex) \
2556 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2557   .name = xname, \
2558   .index = xindex, \
2559   .info = snd_hdsp_info_precise_pointer, \
2560   .get = snd_hdsp_get_precise_pointer, \
2561   .put = snd_hdsp_put_precise_pointer \
2562 }
2563 
2564 static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2565 {
2566 	if (precise)
2567 		hdsp->precise_ptr = 1;
2568 	else
2569 		hdsp->precise_ptr = 0;
2570 	return 0;
2571 }
2572 
2573 #define snd_hdsp_info_precise_pointer		snd_ctl_boolean_mono_info
2574 
2575 static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2576 {
2577 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2578 
2579 	spin_lock_irq(&hdsp->lock);
2580 	ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2581 	spin_unlock_irq(&hdsp->lock);
2582 	return 0;
2583 }
2584 
2585 static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2586 {
2587 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2588 	int change;
2589 	unsigned int val;
2590 
2591 	if (!snd_hdsp_use_is_exclusive(hdsp))
2592 		return -EBUSY;
2593 	val = ucontrol->value.integer.value[0] & 1;
2594 	spin_lock_irq(&hdsp->lock);
2595 	change = (int)val != hdsp->precise_ptr;
2596 	hdsp_set_precise_pointer(hdsp, val);
2597 	spin_unlock_irq(&hdsp->lock);
2598 	return change;
2599 }
2600 
2601 #define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2602 { .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2603   .name = xname, \
2604   .index = xindex, \
2605   .info = snd_hdsp_info_use_midi_tasklet, \
2606   .get = snd_hdsp_get_use_midi_tasklet, \
2607   .put = snd_hdsp_put_use_midi_tasklet \
2608 }
2609 
2610 static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2611 {
2612 	if (use_tasklet)
2613 		hdsp->use_midi_tasklet = 1;
2614 	else
2615 		hdsp->use_midi_tasklet = 0;
2616 	return 0;
2617 }
2618 
2619 #define snd_hdsp_info_use_midi_tasklet		snd_ctl_boolean_mono_info
2620 
2621 static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2622 {
2623 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2624 
2625 	spin_lock_irq(&hdsp->lock);
2626 	ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2627 	spin_unlock_irq(&hdsp->lock);
2628 	return 0;
2629 }
2630 
2631 static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2632 {
2633 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2634 	int change;
2635 	unsigned int val;
2636 
2637 	if (!snd_hdsp_use_is_exclusive(hdsp))
2638 		return -EBUSY;
2639 	val = ucontrol->value.integer.value[0] & 1;
2640 	spin_lock_irq(&hdsp->lock);
2641 	change = (int)val != hdsp->use_midi_tasklet;
2642 	hdsp_set_use_midi_tasklet(hdsp, val);
2643 	spin_unlock_irq(&hdsp->lock);
2644 	return change;
2645 }
2646 
2647 #define HDSP_MIXER(xname, xindex) \
2648 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2649   .name = xname, \
2650   .index = xindex, \
2651   .device = 0, \
2652   .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2653 		 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2654   .info = snd_hdsp_info_mixer, \
2655   .get = snd_hdsp_get_mixer, \
2656   .put = snd_hdsp_put_mixer \
2657 }
2658 
2659 static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2660 {
2661 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2662 	uinfo->count = 3;
2663 	uinfo->value.integer.min = 0;
2664 	uinfo->value.integer.max = 65536;
2665 	uinfo->value.integer.step = 1;
2666 	return 0;
2667 }
2668 
2669 static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2670 {
2671 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2672 	int source;
2673 	int destination;
2674 	int addr;
2675 
2676 	source = ucontrol->value.integer.value[0];
2677 	destination = ucontrol->value.integer.value[1];
2678 
2679 	if (source >= hdsp->max_channels)
2680 		addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2681 	else
2682 		addr = hdsp_input_to_output_key(hdsp,source, destination);
2683 
2684 	spin_lock_irq(&hdsp->lock);
2685 	ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2686 	spin_unlock_irq(&hdsp->lock);
2687 	return 0;
2688 }
2689 
2690 static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2691 {
2692 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2693 	int change;
2694 	int source;
2695 	int destination;
2696 	int gain;
2697 	int addr;
2698 
2699 	if (!snd_hdsp_use_is_exclusive(hdsp))
2700 		return -EBUSY;
2701 
2702 	source = ucontrol->value.integer.value[0];
2703 	destination = ucontrol->value.integer.value[1];
2704 
2705 	if (source >= hdsp->max_channels)
2706 		addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2707 	else
2708 		addr = hdsp_input_to_output_key(hdsp,source, destination);
2709 
2710 	gain = ucontrol->value.integer.value[2];
2711 
2712 	spin_lock_irq(&hdsp->lock);
2713 	change = gain != hdsp_read_gain(hdsp, addr);
2714 	if (change)
2715 		hdsp_write_gain(hdsp, addr, gain);
2716 	spin_unlock_irq(&hdsp->lock);
2717 	return change;
2718 }
2719 
2720 #define HDSP_WC_SYNC_CHECK(xname, xindex) \
2721 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2722   .name = xname, \
2723   .index = xindex, \
2724   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2725   .info = snd_hdsp_info_sync_check, \
2726   .get = snd_hdsp_get_wc_sync_check \
2727 }
2728 
2729 static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2730 {
2731 	static char *texts[] = {"No Lock", "Lock", "Sync" };
2732 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2733 	uinfo->count = 1;
2734 	uinfo->value.enumerated.items = 3;
2735 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
2736 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
2737 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2738 	return 0;
2739 }
2740 
2741 static int hdsp_wc_sync_check(struct hdsp *hdsp)
2742 {
2743 	int status2 = hdsp_read(hdsp, HDSP_status2Register);
2744 	if (status2 & HDSP_wc_lock) {
2745 		if (status2 & HDSP_wc_sync)
2746 			return 2;
2747 		else
2748 			 return 1;
2749 	} else
2750 		return 0;
2751 	return 0;
2752 }
2753 
2754 static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2755 {
2756 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2757 
2758 	ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2759 	return 0;
2760 }
2761 
2762 #define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2763 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2764   .name = xname, \
2765   .index = xindex, \
2766   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2767   .info = snd_hdsp_info_sync_check, \
2768   .get = snd_hdsp_get_spdif_sync_check \
2769 }
2770 
2771 static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2772 {
2773 	int status = hdsp_read(hdsp, HDSP_statusRegister);
2774 	if (status & HDSP_SPDIFErrorFlag)
2775 		return 0;
2776 	else {
2777 		if (status & HDSP_SPDIFSync)
2778 			return 2;
2779 		else
2780 			return 1;
2781 	}
2782 	return 0;
2783 }
2784 
2785 static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2786 {
2787 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2788 
2789 	ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2790 	return 0;
2791 }
2792 
2793 #define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2794 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2795   .name = xname, \
2796   .index = xindex, \
2797   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2798   .info = snd_hdsp_info_sync_check, \
2799   .get = snd_hdsp_get_adatsync_sync_check \
2800 }
2801 
2802 static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2803 {
2804 	int status = hdsp_read(hdsp, HDSP_statusRegister);
2805 	if (status & HDSP_TimecodeLock) {
2806 		if (status & HDSP_TimecodeSync)
2807 			return 2;
2808 		else
2809 			return 1;
2810 	} else
2811 		return 0;
2812 }
2813 
2814 static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2815 {
2816 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2817 
2818 	ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2819 	return 0;
2820 }
2821 
2822 #define HDSP_ADAT_SYNC_CHECK \
2823 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2824   .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2825   .info = snd_hdsp_info_sync_check, \
2826   .get = snd_hdsp_get_adat_sync_check \
2827 }
2828 
2829 static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2830 {
2831 	int status = hdsp_read(hdsp, HDSP_statusRegister);
2832 
2833 	if (status & (HDSP_Lock0>>idx)) {
2834 		if (status & (HDSP_Sync0>>idx))
2835 			return 2;
2836 		else
2837 			return 1;
2838 	} else
2839 		return 0;
2840 }
2841 
2842 static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2843 {
2844 	int offset;
2845 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2846 
2847 	offset = ucontrol->id.index - 1;
2848 	snd_BUG_ON(offset < 0);
2849 
2850 	switch (hdsp->io_type) {
2851 	case Digiface:
2852 	case H9652:
2853 		if (offset >= 3)
2854 			return -EINVAL;
2855 		break;
2856 	case Multiface:
2857 	case H9632:
2858 		if (offset >= 1)
2859 			return -EINVAL;
2860 		break;
2861 	default:
2862 		return -EIO;
2863 	}
2864 
2865 	ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2866 	return 0;
2867 }
2868 
2869 #define HDSP_DDS_OFFSET(xname, xindex) \
2870 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2871   .name = xname, \
2872   .index = xindex, \
2873   .info = snd_hdsp_info_dds_offset, \
2874   .get = snd_hdsp_get_dds_offset, \
2875   .put = snd_hdsp_put_dds_offset \
2876 }
2877 
2878 static int hdsp_dds_offset(struct hdsp *hdsp)
2879 {
2880 	u64 n;
2881 	unsigned int dds_value = hdsp->dds_value;
2882 	int system_sample_rate = hdsp->system_sample_rate;
2883 
2884 	if (!dds_value)
2885 		return 0;
2886 
2887 	n = DDS_NUMERATOR;
2888 	/*
2889 	 * dds_value = n / rate
2890 	 * rate = n / dds_value
2891 	 */
2892 	n = div_u64(n, dds_value);
2893 	if (system_sample_rate >= 112000)
2894 		n *= 4;
2895 	else if (system_sample_rate >= 56000)
2896 		n *= 2;
2897 	return ((int)n) - system_sample_rate;
2898 }
2899 
2900 static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2901 {
2902 	int rate = hdsp->system_sample_rate + offset_hz;
2903 	hdsp_set_dds_value(hdsp, rate);
2904 	return 0;
2905 }
2906 
2907 static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2908 {
2909 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2910 	uinfo->count = 1;
2911 	uinfo->value.integer.min = -5000;
2912 	uinfo->value.integer.max = 5000;
2913 	return 0;
2914 }
2915 
2916 static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2917 {
2918 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2919 
2920 	ucontrol->value.enumerated.item[0] = hdsp_dds_offset(hdsp);
2921 	return 0;
2922 }
2923 
2924 static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2925 {
2926 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2927 	int change;
2928 	int val;
2929 
2930 	if (!snd_hdsp_use_is_exclusive(hdsp))
2931 		return -EBUSY;
2932 	val = ucontrol->value.enumerated.item[0];
2933 	spin_lock_irq(&hdsp->lock);
2934 	if (val != hdsp_dds_offset(hdsp))
2935 		change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2936 	else
2937 		change = 0;
2938 	spin_unlock_irq(&hdsp->lock);
2939 	return change;
2940 }
2941 
2942 static struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2943 HDSP_DA_GAIN("DA Gain", 0),
2944 HDSP_AD_GAIN("AD Gain", 0),
2945 HDSP_PHONE_GAIN("Phones Gain", 0),
2946 HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2947 HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2948 };
2949 
2950 static struct snd_kcontrol_new snd_hdsp_controls[] = {
2951 {
2952 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2953 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2954 	.info =		snd_hdsp_control_spdif_info,
2955 	.get =		snd_hdsp_control_spdif_get,
2956 	.put =		snd_hdsp_control_spdif_put,
2957 },
2958 {
2959 	.access =	SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2960 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2961 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2962 	.info =		snd_hdsp_control_spdif_stream_info,
2963 	.get =		snd_hdsp_control_spdif_stream_get,
2964 	.put =		snd_hdsp_control_spdif_stream_put,
2965 },
2966 {
2967 	.access =	SNDRV_CTL_ELEM_ACCESS_READ,
2968 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2969 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2970 	.info =		snd_hdsp_control_spdif_mask_info,
2971 	.get =		snd_hdsp_control_spdif_mask_get,
2972 	.private_value = IEC958_AES0_NONAUDIO |
2973   			 IEC958_AES0_PROFESSIONAL |
2974 			 IEC958_AES0_CON_EMPHASIS,
2975 },
2976 {
2977 	.access =	SNDRV_CTL_ELEM_ACCESS_READ,
2978 	.iface =	SNDRV_CTL_ELEM_IFACE_PCM,
2979 	.name =		SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2980 	.info =		snd_hdsp_control_spdif_mask_info,
2981 	.get =		snd_hdsp_control_spdif_mask_get,
2982 	.private_value = IEC958_AES0_NONAUDIO |
2983 			 IEC958_AES0_PROFESSIONAL |
2984 			 IEC958_AES0_PRO_EMPHASIS,
2985 },
2986 HDSP_MIXER("Mixer", 0),
2987 HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2988 HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2989 HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2990 HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2991 HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2992 /* 'Sample Clock Source' complies with the alsa control naming scheme */
2993 HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2994 {
2995 	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2996 	.name = "Sample Clock Source Locking",
2997 	.info = snd_hdsp_info_clock_source_lock,
2998 	.get = snd_hdsp_get_clock_source_lock,
2999 	.put = snd_hdsp_put_clock_source_lock,
3000 },
3001 HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
3002 HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
3003 HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
3004 HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
3005 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3006 /* 'External Rate' complies with the alsa control naming scheme */
3007 HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
3008 HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
3009 HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
3010 HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
3011 HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
3012 HDSP_PRECISE_POINTER("Precise Pointer", 0),
3013 HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
3014 };
3015 
3016 
3017 static int hdsp_rpm_input12(struct hdsp *hdsp)
3018 {
3019 	switch (hdsp->control_register & HDSP_RPM_Inp12) {
3020 	case HDSP_RPM_Inp12_Phon_6dB:
3021 		return 0;
3022 	case HDSP_RPM_Inp12_Phon_n6dB:
3023 		return 2;
3024 	case HDSP_RPM_Inp12_Line_0dB:
3025 		return 3;
3026 	case HDSP_RPM_Inp12_Line_n6dB:
3027 		return 4;
3028 	}
3029 	return 1;
3030 }
3031 
3032 
3033 static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3034 {
3035 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3036 
3037 	ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
3038 	return 0;
3039 }
3040 
3041 
3042 static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
3043 {
3044 	hdsp->control_register &= ~HDSP_RPM_Inp12;
3045 	switch (mode) {
3046 	case 0:
3047 		hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
3048 		break;
3049 	case 1:
3050 		break;
3051 	case 2:
3052 		hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
3053 		break;
3054 	case 3:
3055 		hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
3056 		break;
3057 	case 4:
3058 		hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
3059 		break;
3060 	default:
3061 		return -1;
3062 	}
3063 
3064 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3065 	return 0;
3066 }
3067 
3068 
3069 static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3070 {
3071 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3072 	int change;
3073 	int val;
3074 
3075 	if (!snd_hdsp_use_is_exclusive(hdsp))
3076 		return -EBUSY;
3077 	val = ucontrol->value.enumerated.item[0];
3078 	if (val < 0)
3079 		val = 0;
3080 	if (val > 4)
3081 		val = 4;
3082 	spin_lock_irq(&hdsp->lock);
3083 	if (val != hdsp_rpm_input12(hdsp))
3084 		change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3085 	else
3086 		change = 0;
3087 	spin_unlock_irq(&hdsp->lock);
3088 	return change;
3089 }
3090 
3091 
3092 static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3093 {
3094 	static char *texts[] = {"Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"};
3095 
3096 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3097 	uinfo->count = 1;
3098 	uinfo->value.enumerated.items = 5;
3099 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3100 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3101 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3102 	return 0;
3103 }
3104 
3105 
3106 static int hdsp_rpm_input34(struct hdsp *hdsp)
3107 {
3108 	switch (hdsp->control_register & HDSP_RPM_Inp34) {
3109 	case HDSP_RPM_Inp34_Phon_6dB:
3110 		return 0;
3111 	case HDSP_RPM_Inp34_Phon_n6dB:
3112 		return 2;
3113 	case HDSP_RPM_Inp34_Line_0dB:
3114 		return 3;
3115 	case HDSP_RPM_Inp34_Line_n6dB:
3116 		return 4;
3117 	}
3118 	return 1;
3119 }
3120 
3121 
3122 static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3123 {
3124 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3125 
3126 	ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3127 	return 0;
3128 }
3129 
3130 
3131 static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3132 {
3133 	hdsp->control_register &= ~HDSP_RPM_Inp34;
3134 	switch (mode) {
3135 	case 0:
3136 		hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3137 		break;
3138 	case 1:
3139 		break;
3140 	case 2:
3141 		hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3142 		break;
3143 	case 3:
3144 		hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3145 		break;
3146 	case 4:
3147 		hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3148 		break;
3149 	default:
3150 		return -1;
3151 	}
3152 
3153 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3154 	return 0;
3155 }
3156 
3157 
3158 static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3159 {
3160 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3161 	int change;
3162 	int val;
3163 
3164 	if (!snd_hdsp_use_is_exclusive(hdsp))
3165 		return -EBUSY;
3166 	val = ucontrol->value.enumerated.item[0];
3167 	if (val < 0)
3168 		val = 0;
3169 	if (val > 4)
3170 		val = 4;
3171 	spin_lock_irq(&hdsp->lock);
3172 	if (val != hdsp_rpm_input34(hdsp))
3173 		change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3174 	else
3175 		change = 0;
3176 	spin_unlock_irq(&hdsp->lock);
3177 	return change;
3178 }
3179 
3180 
3181 /* RPM Bypass switch */
3182 static int hdsp_rpm_bypass(struct hdsp *hdsp)
3183 {
3184 	return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3185 }
3186 
3187 
3188 static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3189 {
3190 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3191 
3192 	ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3193 	return 0;
3194 }
3195 
3196 
3197 static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3198 {
3199 	if (on)
3200 		hdsp->control_register |= HDSP_RPM_Bypass;
3201 	else
3202 		hdsp->control_register &= ~HDSP_RPM_Bypass;
3203 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3204 	return 0;
3205 }
3206 
3207 
3208 static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3209 {
3210 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3211 	int change;
3212 	unsigned int val;
3213 
3214 	if (!snd_hdsp_use_is_exclusive(hdsp))
3215 		return -EBUSY;
3216 	val = ucontrol->value.integer.value[0] & 1;
3217 	spin_lock_irq(&hdsp->lock);
3218 	change = (int)val != hdsp_rpm_bypass(hdsp);
3219 	hdsp_set_rpm_bypass(hdsp, val);
3220 	spin_unlock_irq(&hdsp->lock);
3221 	return change;
3222 }
3223 
3224 
3225 static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3226 {
3227 	static char *texts[] = {"On", "Off"};
3228 
3229 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3230 	uinfo->count = 1;
3231 	uinfo->value.enumerated.items = 2;
3232 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3233 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3234 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3235 	return 0;
3236 }
3237 
3238 
3239 /* RPM Disconnect switch */
3240 static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3241 {
3242 	return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3243 }
3244 
3245 
3246 static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3247 {
3248 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3249 
3250 	ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3251 	return 0;
3252 }
3253 
3254 
3255 static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3256 {
3257 	if (on)
3258 		hdsp->control_register |= HDSP_RPM_Disconnect;
3259 	else
3260 		hdsp->control_register &= ~HDSP_RPM_Disconnect;
3261 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3262 	return 0;
3263 }
3264 
3265 
3266 static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3267 {
3268 	struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3269 	int change;
3270 	unsigned int val;
3271 
3272 	if (!snd_hdsp_use_is_exclusive(hdsp))
3273 		return -EBUSY;
3274 	val = ucontrol->value.integer.value[0] & 1;
3275 	spin_lock_irq(&hdsp->lock);
3276 	change = (int)val != hdsp_rpm_disconnect(hdsp);
3277 	hdsp_set_rpm_disconnect(hdsp, val);
3278 	spin_unlock_irq(&hdsp->lock);
3279 	return change;
3280 }
3281 
3282 static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3283 {
3284 	static char *texts[] = {"On", "Off"};
3285 
3286 	uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
3287 	uinfo->count = 1;
3288 	uinfo->value.enumerated.items = 2;
3289 	if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
3290 		uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
3291 	strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
3292 	return 0;
3293 }
3294 
3295 static struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3296 	{
3297 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3298 		.name = "RPM Bypass",
3299 		.get = snd_hdsp_get_rpm_bypass,
3300 		.put = snd_hdsp_put_rpm_bypass,
3301 		.info = snd_hdsp_info_rpm_bypass
3302 	},
3303 	{
3304 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3305 		.name = "RPM Disconnect",
3306 		.get = snd_hdsp_get_rpm_disconnect,
3307 		.put = snd_hdsp_put_rpm_disconnect,
3308 		.info = snd_hdsp_info_rpm_disconnect
3309 	},
3310 	{
3311 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3312 		.name = "Input 1/2",
3313 		.get = snd_hdsp_get_rpm_input12,
3314 		.put = snd_hdsp_put_rpm_input12,
3315 		.info = snd_hdsp_info_rpm_input
3316 	},
3317 	{
3318 		.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3319 		.name = "Input 3/4",
3320 		.get = snd_hdsp_get_rpm_input34,
3321 		.put = snd_hdsp_put_rpm_input34,
3322 		.info = snd_hdsp_info_rpm_input
3323 	},
3324 	HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3325 	HDSP_MIXER("Mixer", 0)
3326 };
3327 
3328 static struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3329 	HDSP_TOGGLE_SETTING("Analog Extension Board",
3330 			HDSP_AnalogExtensionBoard);
3331 static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3332 
3333 static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3334 {
3335 	unsigned int idx;
3336 	int err;
3337 	struct snd_kcontrol *kctl;
3338 
3339 	if (hdsp->io_type == RPM) {
3340 		/* RPM Bypass, Disconnect and Input switches */
3341 		for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3342 			err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3343 			if (err < 0)
3344 				return err;
3345 		}
3346 		return 0;
3347 	}
3348 
3349 	for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3350 		if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3351 			return err;
3352 		if (idx == 1)	/* IEC958 (S/PDIF) Stream */
3353 			hdsp->spdif_ctl = kctl;
3354 	}
3355 
3356 	/* ADAT SyncCheck status */
3357 	snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3358 	snd_hdsp_adat_sync_check.index = 1;
3359 	if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3360 		return err;
3361 	if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3362 		for (idx = 1; idx < 3; ++idx) {
3363 			snd_hdsp_adat_sync_check.index = idx+1;
3364 			if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3365 				return err;
3366 		}
3367 	}
3368 
3369 	/* DA, AD and Phone gain and XLR breakout cable controls for H9632 cards */
3370 	if (hdsp->io_type == H9632) {
3371 		for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3372 			if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3373 				return err;
3374 		}
3375 	}
3376 
3377 	/* AEB control for H96xx card */
3378 	if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3379 		if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3380 				return err;
3381 	}
3382 
3383 	return 0;
3384 }
3385 
3386 /*------------------------------------------------------------
3387    /proc interface
3388  ------------------------------------------------------------*/
3389 
3390 static void
3391 snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3392 {
3393 	struct hdsp *hdsp = entry->private_data;
3394 	unsigned int status;
3395 	unsigned int status2;
3396 	char *pref_sync_ref;
3397 	char *autosync_ref;
3398 	char *system_clock_mode;
3399 	char *clock_source;
3400 	int x;
3401 
3402 	status = hdsp_read(hdsp, HDSP_statusRegister);
3403 	status2 = hdsp_read(hdsp, HDSP_status2Register);
3404 
3405 	snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3406 		    hdsp->card->number + 1);
3407 	snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3408 		    hdsp->capture_buffer, hdsp->playback_buffer);
3409 	snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3410 		    hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3411 	snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3412 	snd_iprintf(buffer, "Control2 register: 0x%x\n",
3413 		    hdsp->control2_register);
3414 	snd_iprintf(buffer, "Status register: 0x%x\n", status);
3415 	snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3416 
3417 	if (hdsp_check_for_iobox(hdsp)) {
3418 		snd_iprintf(buffer, "No I/O box connected.\n"
3419 			    "Please connect one and upload firmware.\n");
3420 		return;
3421 	}
3422 
3423 	if (hdsp_check_for_firmware(hdsp, 0)) {
3424 		if (hdsp->state & HDSP_FirmwareCached) {
3425 			if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3426 				snd_iprintf(buffer, "Firmware loading from "
3427 					    "cache failed, "
3428 					    "please upload manually.\n");
3429 				return;
3430 			}
3431 		} else {
3432 			int err = -EINVAL;
3433 			err = hdsp_request_fw_loader(hdsp);
3434 			if (err < 0) {
3435 				snd_iprintf(buffer,
3436 					    "No firmware loaded nor cached, "
3437 					    "please upload firmware.\n");
3438 				return;
3439 			}
3440 		}
3441 	}
3442 
3443 	snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3444 	snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3445 	snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3446 	snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3447 	snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3448 	snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3449 
3450 	snd_iprintf(buffer, "\n");
3451 
3452 	x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3453 
3454 	snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3455 	snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3456 	snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3457 	snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3458 
3459 	snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3460 
3461 	snd_iprintf(buffer, "\n");
3462 
3463 	switch (hdsp_clock_source(hdsp)) {
3464 	case HDSP_CLOCK_SOURCE_AUTOSYNC:
3465 		clock_source = "AutoSync";
3466 		break;
3467 	case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3468 		clock_source = "Internal 32 kHz";
3469 		break;
3470 	case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3471 		clock_source = "Internal 44.1 kHz";
3472 		break;
3473 	case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3474 		clock_source = "Internal 48 kHz";
3475 		break;
3476 	case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3477 		clock_source = "Internal 64 kHz";
3478 		break;
3479 	case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3480 		clock_source = "Internal 88.2 kHz";
3481 		break;
3482 	case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3483 		clock_source = "Internal 96 kHz";
3484 		break;
3485 	case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3486 		clock_source = "Internal 128 kHz";
3487 		break;
3488 	case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3489 		clock_source = "Internal 176.4 kHz";
3490 		break;
3491 		case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3492 		clock_source = "Internal 192 kHz";
3493 		break;
3494 	default:
3495 		clock_source = "Error";
3496 	}
3497 	snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3498 
3499 	if (hdsp_system_clock_mode(hdsp))
3500 		system_clock_mode = "Slave";
3501 	else
3502 		system_clock_mode = "Master";
3503 
3504 	switch (hdsp_pref_sync_ref (hdsp)) {
3505 	case HDSP_SYNC_FROM_WORD:
3506 		pref_sync_ref = "Word Clock";
3507 		break;
3508 	case HDSP_SYNC_FROM_ADAT_SYNC:
3509 		pref_sync_ref = "ADAT Sync";
3510 		break;
3511 	case HDSP_SYNC_FROM_SPDIF:
3512 		pref_sync_ref = "SPDIF";
3513 		break;
3514 	case HDSP_SYNC_FROM_ADAT1:
3515 		pref_sync_ref = "ADAT1";
3516 		break;
3517 	case HDSP_SYNC_FROM_ADAT2:
3518 		pref_sync_ref = "ADAT2";
3519 		break;
3520 	case HDSP_SYNC_FROM_ADAT3:
3521 		pref_sync_ref = "ADAT3";
3522 		break;
3523 	default:
3524 		pref_sync_ref = "Word Clock";
3525 		break;
3526 	}
3527 	snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3528 
3529 	switch (hdsp_autosync_ref (hdsp)) {
3530 	case HDSP_AUTOSYNC_FROM_WORD:
3531 		autosync_ref = "Word Clock";
3532 		break;
3533 	case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3534 		autosync_ref = "ADAT Sync";
3535 		break;
3536 	case HDSP_AUTOSYNC_FROM_SPDIF:
3537 		autosync_ref = "SPDIF";
3538 		break;
3539 	case HDSP_AUTOSYNC_FROM_NONE:
3540 		autosync_ref = "None";
3541 		break;
3542 	case HDSP_AUTOSYNC_FROM_ADAT1:
3543 		autosync_ref = "ADAT1";
3544 		break;
3545 	case HDSP_AUTOSYNC_FROM_ADAT2:
3546 		autosync_ref = "ADAT2";
3547 		break;
3548 	case HDSP_AUTOSYNC_FROM_ADAT3:
3549 		autosync_ref = "ADAT3";
3550 		break;
3551 	default:
3552 		autosync_ref = "---";
3553 		break;
3554 	}
3555 	snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3556 
3557 	snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3558 
3559 	snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3560 
3561 	snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3562 	snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3563 
3564 	snd_iprintf(buffer, "\n");
3565 
3566 	if (hdsp->io_type != RPM) {
3567 		switch (hdsp_spdif_in(hdsp)) {
3568 		case HDSP_SPDIFIN_OPTICAL:
3569 			snd_iprintf(buffer, "IEC958 input: Optical\n");
3570 			break;
3571 		case HDSP_SPDIFIN_COAXIAL:
3572 			snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3573 			break;
3574 		case HDSP_SPDIFIN_INTERNAL:
3575 			snd_iprintf(buffer, "IEC958 input: Internal\n");
3576 			break;
3577 		case HDSP_SPDIFIN_AES:
3578 			snd_iprintf(buffer, "IEC958 input: AES\n");
3579 			break;
3580 		default:
3581 			snd_iprintf(buffer, "IEC958 input: ???\n");
3582 			break;
3583 		}
3584 	}
3585 
3586 	if (RPM == hdsp->io_type) {
3587 		if (hdsp->control_register & HDSP_RPM_Bypass)
3588 			snd_iprintf(buffer, "RPM Bypass: disabled\n");
3589 		else
3590 			snd_iprintf(buffer, "RPM Bypass: enabled\n");
3591 		if (hdsp->control_register & HDSP_RPM_Disconnect)
3592 			snd_iprintf(buffer, "RPM disconnected\n");
3593 		else
3594 			snd_iprintf(buffer, "RPM connected\n");
3595 
3596 		switch (hdsp->control_register & HDSP_RPM_Inp12) {
3597 		case HDSP_RPM_Inp12_Phon_6dB:
3598 			snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3599 			break;
3600 		case HDSP_RPM_Inp12_Phon_0dB:
3601 			snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3602 			break;
3603 		case HDSP_RPM_Inp12_Phon_n6dB:
3604 			snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3605 			break;
3606 		case HDSP_RPM_Inp12_Line_0dB:
3607 			snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3608 			break;
3609 		case HDSP_RPM_Inp12_Line_n6dB:
3610 			snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3611 			break;
3612 		default:
3613 			snd_iprintf(buffer, "Input 1/2: ???\n");
3614 		}
3615 
3616 		switch (hdsp->control_register & HDSP_RPM_Inp34) {
3617 		case HDSP_RPM_Inp34_Phon_6dB:
3618 			snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3619 			break;
3620 		case HDSP_RPM_Inp34_Phon_0dB:
3621 			snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3622 			break;
3623 		case HDSP_RPM_Inp34_Phon_n6dB:
3624 			snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3625 			break;
3626 		case HDSP_RPM_Inp34_Line_0dB:
3627 			snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3628 			break;
3629 		case HDSP_RPM_Inp34_Line_n6dB:
3630 			snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3631 			break;
3632 		default:
3633 			snd_iprintf(buffer, "Input 3/4: ???\n");
3634 		}
3635 
3636 	} else {
3637 		if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3638 			snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3639 		else
3640 			snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3641 
3642 		if (hdsp->control_register & HDSP_SPDIFProfessional)
3643 			snd_iprintf(buffer, "IEC958 quality: Professional\n");
3644 		else
3645 			snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3646 
3647 		if (hdsp->control_register & HDSP_SPDIFEmphasis)
3648 			snd_iprintf(buffer, "IEC958 emphasis: on\n");
3649 		else
3650 			snd_iprintf(buffer, "IEC958 emphasis: off\n");
3651 
3652 		if (hdsp->control_register & HDSP_SPDIFNonAudio)
3653 			snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3654 		else
3655 			snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3656 		x = hdsp_spdif_sample_rate(hdsp);
3657 		if (x != 0)
3658 			snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3659 		else
3660 			snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3661 	}
3662 	snd_iprintf(buffer, "\n");
3663 
3664 	/* Sync Check */
3665 	x = status & HDSP_Sync0;
3666 	if (status & HDSP_Lock0)
3667 		snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3668 	else
3669 		snd_iprintf(buffer, "ADAT1: No Lock\n");
3670 
3671 	switch (hdsp->io_type) {
3672 	case Digiface:
3673 	case H9652:
3674 		x = status & HDSP_Sync1;
3675 		if (status & HDSP_Lock1)
3676 			snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3677 		else
3678 			snd_iprintf(buffer, "ADAT2: No Lock\n");
3679 		x = status & HDSP_Sync2;
3680 		if (status & HDSP_Lock2)
3681 			snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3682 		else
3683 			snd_iprintf(buffer, "ADAT3: No Lock\n");
3684 		break;
3685 	default:
3686 		/* relax */
3687 		break;
3688 	}
3689 
3690 	x = status & HDSP_SPDIFSync;
3691 	if (status & HDSP_SPDIFErrorFlag)
3692 		snd_iprintf (buffer, "SPDIF: No Lock\n");
3693 	else
3694 		snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3695 
3696 	x = status2 & HDSP_wc_sync;
3697 	if (status2 & HDSP_wc_lock)
3698 		snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3699 	else
3700 		snd_iprintf (buffer, "Word Clock: No Lock\n");
3701 
3702 	x = status & HDSP_TimecodeSync;
3703 	if (status & HDSP_TimecodeLock)
3704 		snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3705 	else
3706 		snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3707 
3708 	snd_iprintf(buffer, "\n");
3709 
3710 	/* Informations about H9632 specific controls */
3711 	if (hdsp->io_type == H9632) {
3712 		char *tmp;
3713 
3714 		switch (hdsp_ad_gain(hdsp)) {
3715 		case 0:
3716 			tmp = "-10 dBV";
3717 			break;
3718 		case 1:
3719 			tmp = "+4 dBu";
3720 			break;
3721 		default:
3722 			tmp = "Lo Gain";
3723 			break;
3724 		}
3725 		snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3726 
3727 		switch (hdsp_da_gain(hdsp)) {
3728 		case 0:
3729 			tmp = "Hi Gain";
3730 			break;
3731 		case 1:
3732 			tmp = "+4 dBu";
3733 			break;
3734 		default:
3735 			tmp = "-10 dBV";
3736 			break;
3737 		}
3738 		snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3739 
3740 		switch (hdsp_phone_gain(hdsp)) {
3741 		case 0:
3742 			tmp = "0 dB";
3743 			break;
3744 		case 1:
3745 			tmp = "-6 dB";
3746 			break;
3747 		default:
3748 			tmp = "-12 dB";
3749 			break;
3750 		}
3751 		snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3752 
3753 		snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3754 			hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3755 			"yes" : "no");
3756 
3757 		if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3758 			snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3759 		else
3760 			snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3761 		snd_iprintf(buffer, "\n");
3762 	}
3763 
3764 }
3765 
3766 static void snd_hdsp_proc_init(struct hdsp *hdsp)
3767 {
3768 	struct snd_info_entry *entry;
3769 
3770 	if (! snd_card_proc_new(hdsp->card, "hdsp", &entry))
3771 		snd_info_set_text_ops(entry, hdsp, snd_hdsp_proc_read);
3772 }
3773 
3774 static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3775 {
3776 	snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3777 	snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3778 }
3779 
3780 static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3781 {
3782 	unsigned long pb_bus, cb_bus;
3783 
3784 	if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3785 	    snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3786 		if (hdsp->capture_dma_buf.area)
3787 			snd_dma_free_pages(&hdsp->capture_dma_buf);
3788 		printk(KERN_ERR "%s: no buffers available\n", hdsp->card_name);
3789 		return -ENOMEM;
3790 	}
3791 
3792 	/* Align to bus-space 64K boundary */
3793 
3794 	cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3795 	pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3796 
3797 	/* Tell the card where it is */
3798 
3799 	hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3800 	hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3801 
3802 	hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3803 	hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3804 
3805 	return 0;
3806 }
3807 
3808 static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3809 {
3810 	unsigned int i;
3811 
3812 	/* ASSUMPTION: hdsp->lock is either held, or
3813 	   there is no need to hold it (e.g. during module
3814 	   initialization).
3815 	 */
3816 
3817 	/* set defaults:
3818 
3819 	   SPDIF Input via Coax
3820 	   Master clock mode
3821 	   maximum latency (7 => 2^7 = 8192 samples, 64Kbyte buffer,
3822 	                    which implies 2 4096 sample, 32Kbyte periods).
3823            Enable line out.
3824 	 */
3825 
3826 	hdsp->control_register = HDSP_ClockModeMaster |
3827 		                 HDSP_SPDIFInputCoaxial |
3828 		                 hdsp_encode_latency(7) |
3829 		                 HDSP_LineOut;
3830 
3831 
3832 	hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3833 
3834 #ifdef SNDRV_BIG_ENDIAN
3835 	hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3836 #else
3837 	hdsp->control2_register = 0;
3838 #endif
3839 	if (hdsp->io_type == H9652)
3840 	        snd_hdsp_9652_enable_mixer (hdsp);
3841 	else
3842 		hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3843 
3844 	hdsp_reset_hw_pointer(hdsp);
3845 	hdsp_compute_period_size(hdsp);
3846 
3847 	/* silence everything */
3848 
3849 	for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3850 		hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3851 
3852 	for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3853 		if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3854 			return -EIO;
3855 	}
3856 
3857 	/* H9632 specific defaults */
3858 	if (hdsp->io_type == H9632) {
3859 		hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3860 		hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3861 	}
3862 
3863 	/* set a default rate so that the channel map is set up.
3864 	 */
3865 
3866 	hdsp_set_rate(hdsp, 48000, 1);
3867 
3868 	return 0;
3869 }
3870 
3871 static void hdsp_midi_tasklet(unsigned long arg)
3872 {
3873 	struct hdsp *hdsp = (struct hdsp *)arg;
3874 
3875 	if (hdsp->midi[0].pending)
3876 		snd_hdsp_midi_input_read (&hdsp->midi[0]);
3877 	if (hdsp->midi[1].pending)
3878 		snd_hdsp_midi_input_read (&hdsp->midi[1]);
3879 }
3880 
3881 static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3882 {
3883 	struct hdsp *hdsp = (struct hdsp *) dev_id;
3884 	unsigned int status;
3885 	int audio;
3886 	int midi0;
3887 	int midi1;
3888 	unsigned int midi0status;
3889 	unsigned int midi1status;
3890 	int schedule = 0;
3891 
3892 	status = hdsp_read(hdsp, HDSP_statusRegister);
3893 
3894 	audio = status & HDSP_audioIRQPending;
3895 	midi0 = status & HDSP_midi0IRQPending;
3896 	midi1 = status & HDSP_midi1IRQPending;
3897 
3898 	if (!audio && !midi0 && !midi1)
3899 		return IRQ_NONE;
3900 
3901 	hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3902 
3903 	midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3904 	midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3905 
3906 	if (!(hdsp->state & HDSP_InitializationComplete))
3907 		return IRQ_HANDLED;
3908 
3909 	if (audio) {
3910 		if (hdsp->capture_substream)
3911 			snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3912 
3913 		if (hdsp->playback_substream)
3914 			snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3915 	}
3916 
3917 	if (midi0 && midi0status) {
3918 		if (hdsp->use_midi_tasklet) {
3919 			/* we disable interrupts for this input until processing is done */
3920 			hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3921 			hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3922 			hdsp->midi[0].pending = 1;
3923 			schedule = 1;
3924 		} else {
3925 			snd_hdsp_midi_input_read (&hdsp->midi[0]);
3926 		}
3927 	}
3928 	if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3929 		if (hdsp->use_midi_tasklet) {
3930 			/* we disable interrupts for this input until processing is done */
3931 			hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3932 			hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3933 			hdsp->midi[1].pending = 1;
3934 			schedule = 1;
3935 		} else {
3936 			snd_hdsp_midi_input_read (&hdsp->midi[1]);
3937 		}
3938 	}
3939 	if (hdsp->use_midi_tasklet && schedule)
3940 		tasklet_schedule(&hdsp->midi_tasklet);
3941 	return IRQ_HANDLED;
3942 }
3943 
3944 static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3945 {
3946 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3947 	return hdsp_hw_pointer(hdsp);
3948 }
3949 
3950 static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3951 					     int stream,
3952 					     int channel)
3953 
3954 {
3955 	int mapped_channel;
3956 
3957         if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3958 		return NULL;
3959 
3960 	if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3961 		return NULL;
3962 
3963 	if (stream == SNDRV_PCM_STREAM_CAPTURE)
3964 		return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3965 	else
3966 		return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3967 }
3968 
3969 static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream, int channel,
3970 				  snd_pcm_uframes_t pos, void __user *src, snd_pcm_uframes_t count)
3971 {
3972 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3973 	char *channel_buf;
3974 
3975 	if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3976 		return -EINVAL;
3977 
3978 	channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3979 	if (snd_BUG_ON(!channel_buf))
3980 		return -EIO;
3981 	if (copy_from_user(channel_buf + pos * 4, src, count * 4))
3982 		return -EFAULT;
3983 	return count;
3984 }
3985 
3986 static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream, int channel,
3987 				 snd_pcm_uframes_t pos, void __user *dst, snd_pcm_uframes_t count)
3988 {
3989 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3990 	char *channel_buf;
3991 
3992 	if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES / 4))
3993 		return -EINVAL;
3994 
3995 	channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3996 	if (snd_BUG_ON(!channel_buf))
3997 		return -EIO;
3998 	if (copy_to_user(dst, channel_buf + pos * 4, count * 4))
3999 		return -EFAULT;
4000 	return count;
4001 }
4002 
4003 static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream, int channel,
4004 				  snd_pcm_uframes_t pos, snd_pcm_uframes_t count)
4005 {
4006 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4007 	char *channel_buf;
4008 
4009 	channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
4010 	if (snd_BUG_ON(!channel_buf))
4011 		return -EIO;
4012 	memset(channel_buf + pos * 4, 0, count * 4);
4013 	return count;
4014 }
4015 
4016 static int snd_hdsp_reset(struct snd_pcm_substream *substream)
4017 {
4018 	struct snd_pcm_runtime *runtime = substream->runtime;
4019 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4020 	struct snd_pcm_substream *other;
4021 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4022 		other = hdsp->capture_substream;
4023 	else
4024 		other = hdsp->playback_substream;
4025 	if (hdsp->running)
4026 		runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
4027 	else
4028 		runtime->status->hw_ptr = 0;
4029 	if (other) {
4030 		struct snd_pcm_substream *s;
4031 		struct snd_pcm_runtime *oruntime = other->runtime;
4032 		snd_pcm_group_for_each_entry(s, substream) {
4033 			if (s == other) {
4034 				oruntime->status->hw_ptr = runtime->status->hw_ptr;
4035 				break;
4036 			}
4037 		}
4038 	}
4039 	return 0;
4040 }
4041 
4042 static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
4043 				 struct snd_pcm_hw_params *params)
4044 {
4045 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4046 	int err;
4047 	pid_t this_pid;
4048 	pid_t other_pid;
4049 
4050 	if (hdsp_check_for_iobox (hdsp))
4051 		return -EIO;
4052 
4053 	if (hdsp_check_for_firmware(hdsp, 1))
4054 		return -EIO;
4055 
4056 	spin_lock_irq(&hdsp->lock);
4057 
4058 	if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4059 		hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4060 		hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4061 		this_pid = hdsp->playback_pid;
4062 		other_pid = hdsp->capture_pid;
4063 	} else {
4064 		this_pid = hdsp->capture_pid;
4065 		other_pid = hdsp->playback_pid;
4066 	}
4067 
4068 	if ((other_pid > 0) && (this_pid != other_pid)) {
4069 
4070 		/* The other stream is open, and not by the same
4071 		   task as this one. Make sure that the parameters
4072 		   that matter are the same.
4073 		 */
4074 
4075 		if (params_rate(params) != hdsp->system_sample_rate) {
4076 			spin_unlock_irq(&hdsp->lock);
4077 			_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4078 			return -EBUSY;
4079 		}
4080 
4081 		if (params_period_size(params) != hdsp->period_bytes / 4) {
4082 			spin_unlock_irq(&hdsp->lock);
4083 			_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4084 			return -EBUSY;
4085 		}
4086 
4087 		/* We're fine. */
4088 
4089 		spin_unlock_irq(&hdsp->lock);
4090  		return 0;
4091 
4092 	} else {
4093 		spin_unlock_irq(&hdsp->lock);
4094 	}
4095 
4096 	/* how to make sure that the rate matches an externally-set one ?
4097 	 */
4098 
4099 	spin_lock_irq(&hdsp->lock);
4100 	if (! hdsp->clock_source_locked) {
4101 		if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4102 			spin_unlock_irq(&hdsp->lock);
4103 			_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4104 			return err;
4105 		}
4106 	}
4107 	spin_unlock_irq(&hdsp->lock);
4108 
4109 	if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4110 		_snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4111 		return err;
4112 	}
4113 
4114 	return 0;
4115 }
4116 
4117 static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4118 				    struct snd_pcm_channel_info *info)
4119 {
4120 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4121 	int mapped_channel;
4122 
4123 	if (snd_BUG_ON(info->channel >= hdsp->max_channels))
4124 		return -EINVAL;
4125 
4126 	if ((mapped_channel = hdsp->channel_map[info->channel]) < 0)
4127 		return -EINVAL;
4128 
4129 	info->offset = mapped_channel * HDSP_CHANNEL_BUFFER_BYTES;
4130 	info->first = 0;
4131 	info->step = 32;
4132 	return 0;
4133 }
4134 
4135 static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4136 			     unsigned int cmd, void *arg)
4137 {
4138 	switch (cmd) {
4139 	case SNDRV_PCM_IOCTL1_RESET:
4140 		return snd_hdsp_reset(substream);
4141 	case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4142 		return snd_hdsp_channel_info(substream, arg);
4143 	default:
4144 		break;
4145 	}
4146 
4147 	return snd_pcm_lib_ioctl(substream, cmd, arg);
4148 }
4149 
4150 static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4151 {
4152 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4153 	struct snd_pcm_substream *other;
4154 	int running;
4155 
4156 	if (hdsp_check_for_iobox (hdsp))
4157 		return -EIO;
4158 
4159 	if (hdsp_check_for_firmware(hdsp, 0)) /* no auto-loading in trigger */
4160 		return -EIO;
4161 
4162 	spin_lock(&hdsp->lock);
4163 	running = hdsp->running;
4164 	switch (cmd) {
4165 	case SNDRV_PCM_TRIGGER_START:
4166 		running |= 1 << substream->stream;
4167 		break;
4168 	case SNDRV_PCM_TRIGGER_STOP:
4169 		running &= ~(1 << substream->stream);
4170 		break;
4171 	default:
4172 		snd_BUG();
4173 		spin_unlock(&hdsp->lock);
4174 		return -EINVAL;
4175 	}
4176 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4177 		other = hdsp->capture_substream;
4178 	else
4179 		other = hdsp->playback_substream;
4180 
4181 	if (other) {
4182 		struct snd_pcm_substream *s;
4183 		snd_pcm_group_for_each_entry(s, substream) {
4184 			if (s == other) {
4185 				snd_pcm_trigger_done(s, substream);
4186 				if (cmd == SNDRV_PCM_TRIGGER_START)
4187 					running |= 1 << s->stream;
4188 				else
4189 					running &= ~(1 << s->stream);
4190 				goto _ok;
4191 			}
4192 		}
4193 		if (cmd == SNDRV_PCM_TRIGGER_START) {
4194 			if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4195 			    substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4196 				hdsp_silence_playback(hdsp);
4197 		} else {
4198 			if (running &&
4199 			    substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4200 				hdsp_silence_playback(hdsp);
4201 		}
4202 	} else {
4203 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4204 				hdsp_silence_playback(hdsp);
4205 	}
4206  _ok:
4207 	snd_pcm_trigger_done(substream, substream);
4208 	if (!hdsp->running && running)
4209 		hdsp_start_audio(hdsp);
4210 	else if (hdsp->running && !running)
4211 		hdsp_stop_audio(hdsp);
4212 	hdsp->running = running;
4213 	spin_unlock(&hdsp->lock);
4214 
4215 	return 0;
4216 }
4217 
4218 static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4219 {
4220 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4221 	int result = 0;
4222 
4223 	if (hdsp_check_for_iobox (hdsp))
4224 		return -EIO;
4225 
4226 	if (hdsp_check_for_firmware(hdsp, 1))
4227 		return -EIO;
4228 
4229 	spin_lock_irq(&hdsp->lock);
4230 	if (!hdsp->running)
4231 		hdsp_reset_hw_pointer(hdsp);
4232 	spin_unlock_irq(&hdsp->lock);
4233 	return result;
4234 }
4235 
4236 static struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4237 {
4238 	.info =			(SNDRV_PCM_INFO_MMAP |
4239 				 SNDRV_PCM_INFO_MMAP_VALID |
4240 				 SNDRV_PCM_INFO_NONINTERLEAVED |
4241 				 SNDRV_PCM_INFO_SYNC_START |
4242 				 SNDRV_PCM_INFO_DOUBLE),
4243 #ifdef SNDRV_BIG_ENDIAN
4244 	.formats =		SNDRV_PCM_FMTBIT_S32_BE,
4245 #else
4246 	.formats =		SNDRV_PCM_FMTBIT_S32_LE,
4247 #endif
4248 	.rates =		(SNDRV_PCM_RATE_32000 |
4249 				 SNDRV_PCM_RATE_44100 |
4250 				 SNDRV_PCM_RATE_48000 |
4251 				 SNDRV_PCM_RATE_64000 |
4252 				 SNDRV_PCM_RATE_88200 |
4253 				 SNDRV_PCM_RATE_96000),
4254 	.rate_min =		32000,
4255 	.rate_max =		96000,
4256 	.channels_min =		6,
4257 	.channels_max =		HDSP_MAX_CHANNELS,
4258 	.buffer_bytes_max =	HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4259 	.period_bytes_min =	(64 * 4) * 10,
4260 	.period_bytes_max =	(8192 * 4) * HDSP_MAX_CHANNELS,
4261 	.periods_min =		2,
4262 	.periods_max =		2,
4263 	.fifo_size =		0
4264 };
4265 
4266 static struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4267 {
4268 	.info =			(SNDRV_PCM_INFO_MMAP |
4269 				 SNDRV_PCM_INFO_MMAP_VALID |
4270 				 SNDRV_PCM_INFO_NONINTERLEAVED |
4271 				 SNDRV_PCM_INFO_SYNC_START),
4272 #ifdef SNDRV_BIG_ENDIAN
4273 	.formats =		SNDRV_PCM_FMTBIT_S32_BE,
4274 #else
4275 	.formats =		SNDRV_PCM_FMTBIT_S32_LE,
4276 #endif
4277 	.rates =		(SNDRV_PCM_RATE_32000 |
4278 				 SNDRV_PCM_RATE_44100 |
4279 				 SNDRV_PCM_RATE_48000 |
4280 				 SNDRV_PCM_RATE_64000 |
4281 				 SNDRV_PCM_RATE_88200 |
4282 				 SNDRV_PCM_RATE_96000),
4283 	.rate_min =		32000,
4284 	.rate_max =		96000,
4285 	.channels_min =		5,
4286 	.channels_max =		HDSP_MAX_CHANNELS,
4287 	.buffer_bytes_max =	HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4288 	.period_bytes_min =	(64 * 4) * 10,
4289 	.period_bytes_max =	(8192 * 4) * HDSP_MAX_CHANNELS,
4290 	.periods_min =		2,
4291 	.periods_max =		2,
4292 	.fifo_size =		0
4293 };
4294 
4295 static unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4296 
4297 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4298 	.count = ARRAY_SIZE(hdsp_period_sizes),
4299 	.list = hdsp_period_sizes,
4300 	.mask = 0
4301 };
4302 
4303 static unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4304 
4305 static struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4306 	.count = ARRAY_SIZE(hdsp_9632_sample_rates),
4307 	.list = hdsp_9632_sample_rates,
4308 	.mask = 0
4309 };
4310 
4311 static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4312 					struct snd_pcm_hw_rule *rule)
4313 {
4314 	struct hdsp *hdsp = rule->private;
4315 	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4316 	if (hdsp->io_type == H9632) {
4317 		unsigned int list[3];
4318 		list[0] = hdsp->qs_in_channels;
4319 		list[1] = hdsp->ds_in_channels;
4320 		list[2] = hdsp->ss_in_channels;
4321 		return snd_interval_list(c, 3, list, 0);
4322 	} else {
4323 		unsigned int list[2];
4324 		list[0] = hdsp->ds_in_channels;
4325 		list[1] = hdsp->ss_in_channels;
4326 		return snd_interval_list(c, 2, list, 0);
4327 	}
4328 }
4329 
4330 static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4331 					struct snd_pcm_hw_rule *rule)
4332 {
4333 	unsigned int list[3];
4334 	struct hdsp *hdsp = rule->private;
4335 	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4336 	if (hdsp->io_type == H9632) {
4337 		list[0] = hdsp->qs_out_channels;
4338 		list[1] = hdsp->ds_out_channels;
4339 		list[2] = hdsp->ss_out_channels;
4340 		return snd_interval_list(c, 3, list, 0);
4341 	} else {
4342 		list[0] = hdsp->ds_out_channels;
4343 		list[1] = hdsp->ss_out_channels;
4344 	}
4345 	return snd_interval_list(c, 2, list, 0);
4346 }
4347 
4348 static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4349 					     struct snd_pcm_hw_rule *rule)
4350 {
4351 	struct hdsp *hdsp = rule->private;
4352 	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4353 	struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4354 	if (r->min > 96000 && hdsp->io_type == H9632) {
4355 		struct snd_interval t = {
4356 			.min = hdsp->qs_in_channels,
4357 			.max = hdsp->qs_in_channels,
4358 			.integer = 1,
4359 		};
4360 		return snd_interval_refine(c, &t);
4361 	} else if (r->min > 48000 && r->max <= 96000) {
4362 		struct snd_interval t = {
4363 			.min = hdsp->ds_in_channels,
4364 			.max = hdsp->ds_in_channels,
4365 			.integer = 1,
4366 		};
4367 		return snd_interval_refine(c, &t);
4368 	} else if (r->max < 64000) {
4369 		struct snd_interval t = {
4370 			.min = hdsp->ss_in_channels,
4371 			.max = hdsp->ss_in_channels,
4372 			.integer = 1,
4373 		};
4374 		return snd_interval_refine(c, &t);
4375 	}
4376 	return 0;
4377 }
4378 
4379 static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4380 					     struct snd_pcm_hw_rule *rule)
4381 {
4382 	struct hdsp *hdsp = rule->private;
4383 	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4384 	struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4385 	if (r->min > 96000 && hdsp->io_type == H9632) {
4386 		struct snd_interval t = {
4387 			.min = hdsp->qs_out_channels,
4388 			.max = hdsp->qs_out_channels,
4389 			.integer = 1,
4390 		};
4391 		return snd_interval_refine(c, &t);
4392 	} else if (r->min > 48000 && r->max <= 96000) {
4393 		struct snd_interval t = {
4394 			.min = hdsp->ds_out_channels,
4395 			.max = hdsp->ds_out_channels,
4396 			.integer = 1,
4397 		};
4398 		return snd_interval_refine(c, &t);
4399 	} else if (r->max < 64000) {
4400 		struct snd_interval t = {
4401 			.min = hdsp->ss_out_channels,
4402 			.max = hdsp->ss_out_channels,
4403 			.integer = 1,
4404 		};
4405 		return snd_interval_refine(c, &t);
4406 	}
4407 	return 0;
4408 }
4409 
4410 static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4411 					     struct snd_pcm_hw_rule *rule)
4412 {
4413 	struct hdsp *hdsp = rule->private;
4414 	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4415 	struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4416 	if (c->min >= hdsp->ss_out_channels) {
4417 		struct snd_interval t = {
4418 			.min = 32000,
4419 			.max = 48000,
4420 			.integer = 1,
4421 		};
4422 		return snd_interval_refine(r, &t);
4423 	} else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4424 		struct snd_interval t = {
4425 			.min = 128000,
4426 			.max = 192000,
4427 			.integer = 1,
4428 		};
4429 		return snd_interval_refine(r, &t);
4430 	} else if (c->max <= hdsp->ds_out_channels) {
4431 		struct snd_interval t = {
4432 			.min = 64000,
4433 			.max = 96000,
4434 			.integer = 1,
4435 		};
4436 		return snd_interval_refine(r, &t);
4437 	}
4438 	return 0;
4439 }
4440 
4441 static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4442 					     struct snd_pcm_hw_rule *rule)
4443 {
4444 	struct hdsp *hdsp = rule->private;
4445 	struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4446 	struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4447 	if (c->min >= hdsp->ss_in_channels) {
4448 		struct snd_interval t = {
4449 			.min = 32000,
4450 			.max = 48000,
4451 			.integer = 1,
4452 		};
4453 		return snd_interval_refine(r, &t);
4454 	} else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4455 		struct snd_interval t = {
4456 			.min = 128000,
4457 			.max = 192000,
4458 			.integer = 1,
4459 		};
4460 		return snd_interval_refine(r, &t);
4461 	} else if (c->max <= hdsp->ds_in_channels) {
4462 		struct snd_interval t = {
4463 			.min = 64000,
4464 			.max = 96000,
4465 			.integer = 1,
4466 		};
4467 		return snd_interval_refine(r, &t);
4468 	}
4469 	return 0;
4470 }
4471 
4472 static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4473 {
4474 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4475 	struct snd_pcm_runtime *runtime = substream->runtime;
4476 
4477 	if (hdsp_check_for_iobox (hdsp))
4478 		return -EIO;
4479 
4480 	if (hdsp_check_for_firmware(hdsp, 1))
4481 		return -EIO;
4482 
4483 	spin_lock_irq(&hdsp->lock);
4484 
4485 	snd_pcm_set_sync(substream);
4486 
4487         runtime->hw = snd_hdsp_playback_subinfo;
4488 	runtime->dma_area = hdsp->playback_buffer;
4489 	runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4490 
4491 	hdsp->playback_pid = current->pid;
4492 	hdsp->playback_substream = substream;
4493 
4494 	spin_unlock_irq(&hdsp->lock);
4495 
4496 	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4497 	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4498 	if (hdsp->clock_source_locked) {
4499 		runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4500 	} else if (hdsp->io_type == H9632) {
4501 		runtime->hw.rate_max = 192000;
4502 		runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4503 		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4504 	}
4505 	if (hdsp->io_type == H9632) {
4506 		runtime->hw.channels_min = hdsp->qs_out_channels;
4507 		runtime->hw.channels_max = hdsp->ss_out_channels;
4508 	}
4509 
4510 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4511 			     snd_hdsp_hw_rule_out_channels, hdsp,
4512 			     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4513 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4514 			     snd_hdsp_hw_rule_out_channels_rate, hdsp,
4515 			     SNDRV_PCM_HW_PARAM_RATE, -1);
4516 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4517 			     snd_hdsp_hw_rule_rate_out_channels, hdsp,
4518 			     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4519 
4520 	if (RPM != hdsp->io_type) {
4521 		hdsp->creg_spdif_stream = hdsp->creg_spdif;
4522 		hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4523 		snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4524 			SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4525 	}
4526 	return 0;
4527 }
4528 
4529 static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4530 {
4531 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4532 
4533 	spin_lock_irq(&hdsp->lock);
4534 
4535 	hdsp->playback_pid = -1;
4536 	hdsp->playback_substream = NULL;
4537 
4538 	spin_unlock_irq(&hdsp->lock);
4539 
4540 	if (RPM != hdsp->io_type) {
4541 		hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4542 		snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4543 			SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4544 	}
4545 	return 0;
4546 }
4547 
4548 
4549 static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4550 {
4551 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4552 	struct snd_pcm_runtime *runtime = substream->runtime;
4553 
4554 	if (hdsp_check_for_iobox (hdsp))
4555 		return -EIO;
4556 
4557 	if (hdsp_check_for_firmware(hdsp, 1))
4558 		return -EIO;
4559 
4560 	spin_lock_irq(&hdsp->lock);
4561 
4562 	snd_pcm_set_sync(substream);
4563 
4564 	runtime->hw = snd_hdsp_capture_subinfo;
4565 	runtime->dma_area = hdsp->capture_buffer;
4566 	runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4567 
4568 	hdsp->capture_pid = current->pid;
4569 	hdsp->capture_substream = substream;
4570 
4571 	spin_unlock_irq(&hdsp->lock);
4572 
4573 	snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4574 	snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4575 	if (hdsp->io_type == H9632) {
4576 		runtime->hw.channels_min = hdsp->qs_in_channels;
4577 		runtime->hw.channels_max = hdsp->ss_in_channels;
4578 		runtime->hw.rate_max = 192000;
4579 		runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4580 		snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4581 	}
4582 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4583 			     snd_hdsp_hw_rule_in_channels, hdsp,
4584 			     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4585 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4586 			     snd_hdsp_hw_rule_in_channels_rate, hdsp,
4587 			     SNDRV_PCM_HW_PARAM_RATE, -1);
4588 	snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4589 			     snd_hdsp_hw_rule_rate_in_channels, hdsp,
4590 			     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4591 	return 0;
4592 }
4593 
4594 static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4595 {
4596 	struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4597 
4598 	spin_lock_irq(&hdsp->lock);
4599 
4600 	hdsp->capture_pid = -1;
4601 	hdsp->capture_substream = NULL;
4602 
4603 	spin_unlock_irq(&hdsp->lock);
4604 	return 0;
4605 }
4606 
4607 /* helper functions for copying meter values */
4608 static inline int copy_u32_le(void __user *dest, void __iomem *src)
4609 {
4610 	u32 val = readl(src);
4611 	return copy_to_user(dest, &val, 4);
4612 }
4613 
4614 static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4615 {
4616 	u32 rms_low, rms_high;
4617 	u64 rms;
4618 	rms_low = readl(src_low);
4619 	rms_high = readl(src_high);
4620 	rms = ((u64)rms_high << 32) | rms_low;
4621 	return copy_to_user(dest, &rms, 8);
4622 }
4623 
4624 static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4625 {
4626 	u32 rms_low, rms_high;
4627 	u64 rms;
4628 	rms_low = readl(src_low) & 0xffffff00;
4629 	rms_high = readl(src_high) & 0xffffff00;
4630 	rms = ((u64)rms_high << 32) | rms_low;
4631 	return copy_to_user(dest, &rms, 8);
4632 }
4633 
4634 static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4635 {
4636 	int doublespeed = 0;
4637 	int i, j, channels, ofs;
4638 
4639 	if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4640 		doublespeed = 1;
4641 	channels = doublespeed ? 14 : 26;
4642 	for (i = 0, j = 0; i < 26; ++i) {
4643 		if (doublespeed && (i & 4))
4644 			continue;
4645 		ofs = HDSP_9652_peakBase - j * 4;
4646 		if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4647 			return -EFAULT;
4648 		ofs -= channels * 4;
4649 		if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4650 			return -EFAULT;
4651 		ofs -= channels * 4;
4652 		if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4653 			return -EFAULT;
4654 		ofs = HDSP_9652_rmsBase + j * 8;
4655 		if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4656 				hdsp->iobase + ofs + 4))
4657 			return -EFAULT;
4658 		ofs += channels * 8;
4659 		if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4660 				hdsp->iobase + ofs + 4))
4661 			return -EFAULT;
4662 		ofs += channels * 8;
4663 		if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4664 				hdsp->iobase + ofs + 4))
4665 			return -EFAULT;
4666 		j++;
4667 	}
4668 	return 0;
4669 }
4670 
4671 static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4672 {
4673 	int i, j;
4674 	struct hdsp_9632_meters __iomem *m;
4675 	int doublespeed = 0;
4676 
4677 	if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4678 		doublespeed = 1;
4679 	m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4680 	for (i = 0, j = 0; i < 16; ++i, ++j) {
4681 		if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4682 			return -EFAULT;
4683 		if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4684 			return -EFAULT;
4685 		if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4686 			return -EFAULT;
4687 		if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4688 				&m->input_rms_high[j]))
4689 			return -EFAULT;
4690 		if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4691 				&m->playback_rms_high[j]))
4692 			return -EFAULT;
4693 		if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4694 				&m->output_rms_high[j]))
4695 			return -EFAULT;
4696 		if (doublespeed && i == 3) i += 4;
4697 	}
4698 	return 0;
4699 }
4700 
4701 static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4702 {
4703 	int i;
4704 
4705 	for (i = 0; i < 26; i++) {
4706 		if (copy_u32_le(&peak_rms->playback_peaks[i],
4707 				hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4708 			return -EFAULT;
4709 		if (copy_u32_le(&peak_rms->input_peaks[i],
4710 				hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4711 			return -EFAULT;
4712 	}
4713 	for (i = 0; i < 28; i++) {
4714 		if (copy_u32_le(&peak_rms->output_peaks[i],
4715 				hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4716 			return -EFAULT;
4717 	}
4718 	for (i = 0; i < 26; ++i) {
4719 		if (copy_u64_le(&peak_rms->playback_rms[i],
4720 				hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4721 				hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4722 			return -EFAULT;
4723 		if (copy_u64_le(&peak_rms->input_rms[i],
4724 				hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4725 				hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4726 			return -EFAULT;
4727 	}
4728 	return 0;
4729 }
4730 
4731 static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4732 {
4733 	struct hdsp *hdsp = hw->private_data;
4734 	void __user *argp = (void __user *)arg;
4735 	int err;
4736 
4737 	switch (cmd) {
4738 	case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4739 		struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4740 
4741 		err = hdsp_check_for_iobox(hdsp);
4742 		if (err < 0)
4743 			return err;
4744 
4745 		err = hdsp_check_for_firmware(hdsp, 1);
4746 		if (err < 0)
4747 			return err;
4748 
4749 		if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4750 			snd_printk(KERN_ERR "Hammerfall-DSP: firmware needs to be uploaded to the card.\n");
4751 			return -EINVAL;
4752 		}
4753 
4754 		switch (hdsp->io_type) {
4755 		case H9652:
4756 			return hdsp_9652_get_peak(hdsp, peak_rms);
4757 		case H9632:
4758 			return hdsp_9632_get_peak(hdsp, peak_rms);
4759 		default:
4760 			return hdsp_get_peak(hdsp, peak_rms);
4761 		}
4762 	}
4763 	case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4764 		struct hdsp_config_info info;
4765 		unsigned long flags;
4766 		int i;
4767 
4768 		err = hdsp_check_for_iobox(hdsp);
4769 		if (err < 0)
4770 			return err;
4771 
4772 		err = hdsp_check_for_firmware(hdsp, 1);
4773 		if (err < 0)
4774 			return err;
4775 
4776 		memset(&info, 0, sizeof(info));
4777 		spin_lock_irqsave(&hdsp->lock, flags);
4778 		info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4779 		info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4780 		if (hdsp->io_type != H9632)
4781 		    info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4782 		info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4783 		for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4784 			info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4785 		info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4786 		info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4787 				HDSP_SPDIFOpticalOut);
4788 		info.spdif_professional = (unsigned char)
4789 			hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4790 		info.spdif_emphasis = (unsigned char)
4791 			hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4792 		info.spdif_nonaudio = (unsigned char)
4793 			hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4794 		info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4795 		info.system_sample_rate = hdsp->system_sample_rate;
4796 		info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4797 		info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4798 		info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4799 		info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4800 		info.line_out = (unsigned char)
4801 			hdsp_toggle_setting(hdsp, HDSP_LineOut);
4802 		if (hdsp->io_type == H9632) {
4803 			info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4804 			info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4805 			info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4806 			info.xlr_breakout_cable =
4807 				(unsigned char)hdsp_toggle_setting(hdsp,
4808 					HDSP_XLRBreakoutCable);
4809 
4810 		} else if (hdsp->io_type == RPM) {
4811 			info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4812 			info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4813 		}
4814 		if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4815 			info.analog_extension_board =
4816 				(unsigned char)hdsp_toggle_setting(hdsp,
4817 					    HDSP_AnalogExtensionBoard);
4818 		spin_unlock_irqrestore(&hdsp->lock, flags);
4819 		if (copy_to_user(argp, &info, sizeof(info)))
4820 			return -EFAULT;
4821 		break;
4822 	}
4823 	case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4824 		struct hdsp_9632_aeb h9632_aeb;
4825 
4826 		if (hdsp->io_type != H9632) return -EINVAL;
4827 		h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4828 		h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4829 		if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4830 			return -EFAULT;
4831 		break;
4832 	}
4833 	case SNDRV_HDSP_IOCTL_GET_VERSION: {
4834 		struct hdsp_version hdsp_version;
4835 		int err;
4836 
4837 		if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4838 		if (hdsp->io_type == Undefined) {
4839 			if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4840 				return err;
4841 		}
4842 		memset(&hdsp_version, 0, sizeof(hdsp_version));
4843 		hdsp_version.io_type = hdsp->io_type;
4844 		hdsp_version.firmware_rev = hdsp->firmware_rev;
4845 		if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4846 		    	return -EFAULT;
4847 		break;
4848 	}
4849 	case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4850 		struct hdsp_firmware __user *firmware;
4851 		u32 __user *firmware_data;
4852 		int err;
4853 
4854 		if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4855 		/* SNDRV_HDSP_IOCTL_GET_VERSION must have been called */
4856 		if (hdsp->io_type == Undefined) return -EINVAL;
4857 
4858 		if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4859 			return -EBUSY;
4860 
4861 		snd_printk(KERN_INFO "Hammerfall-DSP: initializing firmware upload\n");
4862 		firmware = (struct hdsp_firmware __user *)argp;
4863 
4864 		if (get_user(firmware_data, &firmware->firmware_data))
4865 			return -EFAULT;
4866 
4867 		if (hdsp_check_for_iobox (hdsp))
4868 			return -EIO;
4869 
4870 		if (!hdsp->fw_uploaded) {
4871 			hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4872 			if (!hdsp->fw_uploaded)
4873 				return -ENOMEM;
4874 		}
4875 
4876 		if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4877 				   HDSP_FIRMWARE_SIZE)) {
4878 			vfree(hdsp->fw_uploaded);
4879 			hdsp->fw_uploaded = NULL;
4880 			return -EFAULT;
4881 		}
4882 
4883 		hdsp->state |= HDSP_FirmwareCached;
4884 
4885 		if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4886 			return err;
4887 
4888 		if (!(hdsp->state & HDSP_InitializationComplete)) {
4889 			if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4890 				return err;
4891 
4892 			snd_hdsp_initialize_channels(hdsp);
4893 			snd_hdsp_initialize_midi_flush(hdsp);
4894 
4895 			if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4896 				snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
4897 				return err;
4898 			}
4899 		}
4900 		break;
4901 	}
4902 	case SNDRV_HDSP_IOCTL_GET_MIXER: {
4903 		struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4904 		if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4905 			return -EFAULT;
4906 		break;
4907 	}
4908 	default:
4909 		return -EINVAL;
4910 	}
4911 	return 0;
4912 }
4913 
4914 static struct snd_pcm_ops snd_hdsp_playback_ops = {
4915 	.open =		snd_hdsp_playback_open,
4916 	.close =	snd_hdsp_playback_release,
4917 	.ioctl =	snd_hdsp_ioctl,
4918 	.hw_params =	snd_hdsp_hw_params,
4919 	.prepare =	snd_hdsp_prepare,
4920 	.trigger =	snd_hdsp_trigger,
4921 	.pointer =	snd_hdsp_hw_pointer,
4922 	.copy =		snd_hdsp_playback_copy,
4923 	.silence =	snd_hdsp_hw_silence,
4924 };
4925 
4926 static struct snd_pcm_ops snd_hdsp_capture_ops = {
4927 	.open =		snd_hdsp_capture_open,
4928 	.close =	snd_hdsp_capture_release,
4929 	.ioctl =	snd_hdsp_ioctl,
4930 	.hw_params =	snd_hdsp_hw_params,
4931 	.prepare =	snd_hdsp_prepare,
4932 	.trigger =	snd_hdsp_trigger,
4933 	.pointer =	snd_hdsp_hw_pointer,
4934 	.copy =		snd_hdsp_capture_copy,
4935 };
4936 
4937 static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4938 {
4939 	struct snd_hwdep *hw;
4940 	int err;
4941 
4942 	if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4943 		return err;
4944 
4945 	hdsp->hwdep = hw;
4946 	hw->private_data = hdsp;
4947 	strcpy(hw->name, "HDSP hwdep interface");
4948 
4949 	hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4950 	hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4951 
4952 	return 0;
4953 }
4954 
4955 static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4956 {
4957 	struct snd_pcm *pcm;
4958 	int err;
4959 
4960 	if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4961 		return err;
4962 
4963 	hdsp->pcm = pcm;
4964 	pcm->private_data = hdsp;
4965 	strcpy(pcm->name, hdsp->card_name);
4966 
4967 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4968 	snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4969 
4970 	pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4971 
4972 	return 0;
4973 }
4974 
4975 static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4976 {
4977         hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4978 	hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4979 }
4980 
4981 static int snd_hdsp_enable_io (struct hdsp *hdsp)
4982 {
4983 	int i;
4984 
4985 	if (hdsp_fifo_wait (hdsp, 0, 100)) {
4986 		snd_printk(KERN_ERR "Hammerfall-DSP: enable_io fifo_wait failed\n");
4987 		return -EIO;
4988 	}
4989 
4990 	for (i = 0; i < hdsp->max_channels; ++i) {
4991 		hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4992 		hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4993 	}
4994 
4995 	return 0;
4996 }
4997 
4998 static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4999 {
5000 	int status, aebi_channels, aebo_channels;
5001 
5002 	switch (hdsp->io_type) {
5003 	case Digiface:
5004 		hdsp->card_name = "RME Hammerfall DSP + Digiface";
5005 		hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
5006 		hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
5007 		break;
5008 
5009 	case H9652:
5010 		hdsp->card_name = "RME Hammerfall HDSP 9652";
5011 		hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
5012 		hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
5013 		break;
5014 
5015 	case H9632:
5016 		status = hdsp_read(hdsp, HDSP_statusRegister);
5017 		/* HDSP_AEBx bits are low when AEB are connected */
5018 		aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
5019 		aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
5020 		hdsp->card_name = "RME Hammerfall HDSP 9632";
5021 		hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
5022 		hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
5023 		hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
5024 		hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
5025 		hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
5026 		hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
5027 		break;
5028 
5029 	case Multiface:
5030 		hdsp->card_name = "RME Hammerfall DSP + Multiface";
5031 		hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
5032 		hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
5033 		break;
5034 
5035 	case RPM:
5036 		hdsp->card_name = "RME Hammerfall DSP + RPM";
5037 		hdsp->ss_in_channels = RPM_CHANNELS-1;
5038 		hdsp->ss_out_channels = RPM_CHANNELS;
5039 		hdsp->ds_in_channels = RPM_CHANNELS-1;
5040 		hdsp->ds_out_channels = RPM_CHANNELS;
5041 		break;
5042 
5043 	default:
5044  		/* should never get here */
5045 		break;
5046 	}
5047 }
5048 
5049 static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5050 {
5051 	snd_hdsp_flush_midi_input (hdsp, 0);
5052 	snd_hdsp_flush_midi_input (hdsp, 1);
5053 }
5054 
5055 static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5056 {
5057 	int err;
5058 
5059 	if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5060 		snd_printk(KERN_ERR "Hammerfall-DSP: Error creating pcm interface\n");
5061 		return err;
5062 	}
5063 
5064 
5065 	if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5066 		snd_printk(KERN_ERR "Hammerfall-DSP: Error creating first midi interface\n");
5067 		return err;
5068 	}
5069 
5070 	if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5071 		if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5072 			snd_printk(KERN_ERR "Hammerfall-DSP: Error creating second midi interface\n");
5073 			return err;
5074 		}
5075 	}
5076 
5077 	if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5078 		snd_printk(KERN_ERR "Hammerfall-DSP: Error creating ctl interface\n");
5079 		return err;
5080 	}
5081 
5082 	snd_hdsp_proc_init(hdsp);
5083 
5084 	hdsp->system_sample_rate = -1;
5085 	hdsp->playback_pid = -1;
5086 	hdsp->capture_pid = -1;
5087 	hdsp->capture_substream = NULL;
5088 	hdsp->playback_substream = NULL;
5089 
5090 	if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5091 		snd_printk(KERN_ERR "Hammerfall-DSP: Error setting default values\n");
5092 		return err;
5093 	}
5094 
5095 	if (!(hdsp->state & HDSP_InitializationComplete)) {
5096 		strcpy(card->shortname, "Hammerfall DSP");
5097 		sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5098 			hdsp->port, hdsp->irq);
5099 
5100 		if ((err = snd_card_register(card)) < 0) {
5101 			snd_printk(KERN_ERR "Hammerfall-DSP: error registering card\n");
5102 			return err;
5103 		}
5104 		hdsp->state |= HDSP_InitializationComplete;
5105 	}
5106 
5107 	return 0;
5108 }
5109 
5110 /* load firmware via hotplug fw loader */
5111 static int hdsp_request_fw_loader(struct hdsp *hdsp)
5112 {
5113 	const char *fwfile;
5114 	const struct firmware *fw;
5115 	int err;
5116 
5117 	if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5118 		return 0;
5119 	if (hdsp->io_type == Undefined) {
5120 		if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5121 			return err;
5122 		if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5123 			return 0;
5124 	}
5125 
5126 	/* caution: max length of firmware filename is 30! */
5127 	switch (hdsp->io_type) {
5128 	case RPM:
5129 		fwfile = "rpm_firmware.bin";
5130 		break;
5131 	case Multiface:
5132 		if (hdsp->firmware_rev == 0xa)
5133 			fwfile = "multiface_firmware.bin";
5134 		else
5135 			fwfile = "multiface_firmware_rev11.bin";
5136 		break;
5137 	case Digiface:
5138 		if (hdsp->firmware_rev == 0xa)
5139 			fwfile = "digiface_firmware.bin";
5140 		else
5141 			fwfile = "digiface_firmware_rev11.bin";
5142 		break;
5143 	default:
5144 		snd_printk(KERN_ERR "Hammerfall-DSP: invalid io_type %d\n", hdsp->io_type);
5145 		return -EINVAL;
5146 	}
5147 
5148 	if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5149 		snd_printk(KERN_ERR "Hammerfall-DSP: cannot load firmware %s\n", fwfile);
5150 		return -ENOENT;
5151 	}
5152 	if (fw->size < HDSP_FIRMWARE_SIZE) {
5153 		snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n",
5154 			   (int)fw->size, HDSP_FIRMWARE_SIZE);
5155 		return -EINVAL;
5156 	}
5157 
5158 	hdsp->firmware = fw;
5159 
5160 	hdsp->state |= HDSP_FirmwareCached;
5161 
5162 	if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5163 		return err;
5164 
5165 	if (!(hdsp->state & HDSP_InitializationComplete)) {
5166 		if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5167 			return err;
5168 
5169 		if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5170 			snd_printk(KERN_ERR "Hammerfall-DSP: error creating hwdep device\n");
5171 			return err;
5172 		}
5173 		snd_hdsp_initialize_channels(hdsp);
5174 		snd_hdsp_initialize_midi_flush(hdsp);
5175 		if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5176 			snd_printk(KERN_ERR "Hammerfall-DSP: error creating alsa devices\n");
5177 			return err;
5178 		}
5179 	}
5180 	return 0;
5181 }
5182 
5183 static int snd_hdsp_create(struct snd_card *card,
5184 			   struct hdsp *hdsp)
5185 {
5186 	struct pci_dev *pci = hdsp->pci;
5187 	int err;
5188 	int is_9652 = 0;
5189 	int is_9632 = 0;
5190 
5191 	hdsp->irq = -1;
5192 	hdsp->state = 0;
5193 	hdsp->midi[0].rmidi = NULL;
5194 	hdsp->midi[1].rmidi = NULL;
5195 	hdsp->midi[0].input = NULL;
5196 	hdsp->midi[1].input = NULL;
5197 	hdsp->midi[0].output = NULL;
5198 	hdsp->midi[1].output = NULL;
5199 	hdsp->midi[0].pending = 0;
5200 	hdsp->midi[1].pending = 0;
5201 	spin_lock_init(&hdsp->midi[0].lock);
5202 	spin_lock_init(&hdsp->midi[1].lock);
5203 	hdsp->iobase = NULL;
5204 	hdsp->control_register = 0;
5205 	hdsp->control2_register = 0;
5206 	hdsp->io_type = Undefined;
5207 	hdsp->max_channels = 26;
5208 
5209 	hdsp->card = card;
5210 
5211 	spin_lock_init(&hdsp->lock);
5212 
5213 	tasklet_init(&hdsp->midi_tasklet, hdsp_midi_tasklet, (unsigned long)hdsp);
5214 
5215 	pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5216 	hdsp->firmware_rev &= 0xff;
5217 
5218 	/* From Martin Bjoernsen :
5219 	    "It is important that the card's latency timer register in
5220 	    the PCI configuration space is set to a value much larger
5221 	    than 0 by the computer's BIOS or the driver.
5222 	    The windows driver always sets this 8 bit register [...]
5223 	    to its maximum 255 to avoid problems with some computers."
5224 	*/
5225 	pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5226 
5227 	strcpy(card->driver, "H-DSP");
5228 	strcpy(card->mixername, "Xilinx FPGA");
5229 
5230 	if (hdsp->firmware_rev < 0xa)
5231 		return -ENODEV;
5232 	else if (hdsp->firmware_rev < 0x64)
5233 		hdsp->card_name = "RME Hammerfall DSP";
5234 	else if (hdsp->firmware_rev < 0x96) {
5235 		hdsp->card_name = "RME HDSP 9652";
5236 		is_9652 = 1;
5237 	} else {
5238 		hdsp->card_name = "RME HDSP 9632";
5239 		hdsp->max_channels = 16;
5240 		is_9632 = 1;
5241 	}
5242 
5243 	if ((err = pci_enable_device(pci)) < 0)
5244 		return err;
5245 
5246 	pci_set_master(hdsp->pci);
5247 
5248 	if ((err = pci_request_regions(pci, "hdsp")) < 0)
5249 		return err;
5250 	hdsp->port = pci_resource_start(pci, 0);
5251 	if ((hdsp->iobase = ioremap_nocache(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5252 		snd_printk(KERN_ERR "Hammerfall-DSP: unable to remap region 0x%lx-0x%lx\n", hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5253 		return -EBUSY;
5254 	}
5255 
5256 	if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5257 			KBUILD_MODNAME, hdsp)) {
5258 		snd_printk(KERN_ERR "Hammerfall-DSP: unable to use IRQ %d\n", pci->irq);
5259 		return -EBUSY;
5260 	}
5261 
5262 	hdsp->irq = pci->irq;
5263 	hdsp->precise_ptr = 0;
5264 	hdsp->use_midi_tasklet = 1;
5265 	hdsp->dds_value = 0;
5266 
5267 	if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5268 		return err;
5269 
5270 	if (!is_9652 && !is_9632) {
5271 		/* we wait a maximum of 10 seconds to let freshly
5272 		 * inserted cardbus cards do their hardware init */
5273 		err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5274 
5275 		if (err < 0)
5276 			return err;
5277 
5278 		if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5279 			if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5280 				/* we don't fail as this can happen
5281 				   if userspace is not ready for
5282 				   firmware upload
5283 				*/
5284 				snd_printk(KERN_ERR "Hammerfall-DSP: couldn't get firmware from userspace. try using hdsploader\n");
5285 			else
5286 				/* init is complete, we return */
5287 				return 0;
5288 			/* we defer initialization */
5289 			snd_printk(KERN_INFO "Hammerfall-DSP: card initialization pending : waiting for firmware\n");
5290 			if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5291 				return err;
5292 			return 0;
5293 		} else {
5294 			snd_printk(KERN_INFO "Hammerfall-DSP: Firmware already present, initializing card.\n");
5295 			if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5296 				hdsp->io_type = RPM;
5297 			else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5298 				hdsp->io_type = Multiface;
5299 			else
5300 				hdsp->io_type = Digiface;
5301 		}
5302 	}
5303 
5304 	if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5305 		return err;
5306 
5307 	if (is_9652)
5308 	        hdsp->io_type = H9652;
5309 
5310 	if (is_9632)
5311 		hdsp->io_type = H9632;
5312 
5313 	if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5314 		return err;
5315 
5316 	snd_hdsp_initialize_channels(hdsp);
5317 	snd_hdsp_initialize_midi_flush(hdsp);
5318 
5319 	hdsp->state |= HDSP_FirmwareLoaded;
5320 
5321 	if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5322 		return err;
5323 
5324 	return 0;
5325 }
5326 
5327 static int snd_hdsp_free(struct hdsp *hdsp)
5328 {
5329 	if (hdsp->port) {
5330 		/* stop the audio, and cancel all interrupts */
5331 		tasklet_kill(&hdsp->midi_tasklet);
5332 		hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5333 		hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5334 	}
5335 
5336 	if (hdsp->irq >= 0)
5337 		free_irq(hdsp->irq, (void *)hdsp);
5338 
5339 	snd_hdsp_free_buffers(hdsp);
5340 
5341 	if (hdsp->firmware)
5342 		release_firmware(hdsp->firmware);
5343 	vfree(hdsp->fw_uploaded);
5344 
5345 	if (hdsp->iobase)
5346 		iounmap(hdsp->iobase);
5347 
5348 	if (hdsp->port)
5349 		pci_release_regions(hdsp->pci);
5350 
5351 	pci_disable_device(hdsp->pci);
5352 	return 0;
5353 }
5354 
5355 static void snd_hdsp_card_free(struct snd_card *card)
5356 {
5357 	struct hdsp *hdsp = card->private_data;
5358 
5359 	if (hdsp)
5360 		snd_hdsp_free(hdsp);
5361 }
5362 
5363 static int snd_hdsp_probe(struct pci_dev *pci,
5364 			  const struct pci_device_id *pci_id)
5365 {
5366 	static int dev;
5367 	struct hdsp *hdsp;
5368 	struct snd_card *card;
5369 	int err;
5370 
5371 	if (dev >= SNDRV_CARDS)
5372 		return -ENODEV;
5373 	if (!enable[dev]) {
5374 		dev++;
5375 		return -ENOENT;
5376 	}
5377 
5378 	err = snd_card_create(index[dev], id[dev], THIS_MODULE,
5379 			      sizeof(struct hdsp), &card);
5380 	if (err < 0)
5381 		return err;
5382 
5383 	hdsp = card->private_data;
5384 	card->private_free = snd_hdsp_card_free;
5385 	hdsp->dev = dev;
5386 	hdsp->pci = pci;
5387 	snd_card_set_dev(card, &pci->dev);
5388 
5389 	if ((err = snd_hdsp_create(card, hdsp)) < 0) {
5390 		snd_card_free(card);
5391 		return err;
5392 	}
5393 
5394 	strcpy(card->shortname, "Hammerfall DSP");
5395 	sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5396 		hdsp->port, hdsp->irq);
5397 
5398 	if ((err = snd_card_register(card)) < 0) {
5399 		snd_card_free(card);
5400 		return err;
5401 	}
5402 	pci_set_drvdata(pci, card);
5403 	dev++;
5404 	return 0;
5405 }
5406 
5407 static void snd_hdsp_remove(struct pci_dev *pci)
5408 {
5409 	snd_card_free(pci_get_drvdata(pci));
5410 }
5411 
5412 static struct pci_driver hdsp_driver = {
5413 	.name =     KBUILD_MODNAME,
5414 	.id_table = snd_hdsp_ids,
5415 	.probe =    snd_hdsp_probe,
5416 	.remove = snd_hdsp_remove,
5417 };
5418 
5419 module_pci_driver(hdsp_driver);
5420