1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio 4 * interfaces 5 * 6 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> 7 * 8 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control 9 * code. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/vmalloc.h> 18 #include <linux/io.h> 19 20 #include <sound/core.h> 21 #include <sound/info.h> 22 #include <sound/control.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/asoundef.h> 26 #include <sound/initval.h> 27 28 /* note, two last pcis should be equal, it is not a bug */ 29 30 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); 31 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " 32 "Digi96/8 PAD"); 33 MODULE_LICENSE("GPL"); 34 35 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 36 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 37 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 38 39 module_param_array(index, int, NULL, 0444); 40 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); 41 module_param_array(id, charp, NULL, 0444); 42 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); 43 module_param_array(enable, bool, NULL, 0444); 44 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); 45 46 /* 47 * Defines for RME Digi96 series, from internal RME reference documents 48 * dated 12.01.00 49 */ 50 51 #define RME96_SPDIF_NCHANNELS 2 52 53 /* Playback and capture buffer size */ 54 #define RME96_BUFFER_SIZE 0x10000 55 56 /* IO area size */ 57 #define RME96_IO_SIZE 0x60000 58 59 /* IO area offsets */ 60 #define RME96_IO_PLAY_BUFFER 0x0 61 #define RME96_IO_REC_BUFFER 0x10000 62 #define RME96_IO_CONTROL_REGISTER 0x20000 63 #define RME96_IO_ADDITIONAL_REG 0x20004 64 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 65 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 66 #define RME96_IO_SET_PLAY_POS 0x40000 67 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 68 #define RME96_IO_SET_REC_POS 0x50000 69 #define RME96_IO_RESET_REC_POS 0x5FFFC 70 #define RME96_IO_GET_PLAY_POS 0x20000 71 #define RME96_IO_GET_REC_POS 0x30000 72 73 /* Write control register bits */ 74 #define RME96_WCR_START (1 << 0) 75 #define RME96_WCR_START_2 (1 << 1) 76 #define RME96_WCR_GAIN_0 (1 << 2) 77 #define RME96_WCR_GAIN_1 (1 << 3) 78 #define RME96_WCR_MODE24 (1 << 4) 79 #define RME96_WCR_MODE24_2 (1 << 5) 80 #define RME96_WCR_BM (1 << 6) 81 #define RME96_WCR_BM_2 (1 << 7) 82 #define RME96_WCR_ADAT (1 << 8) 83 #define RME96_WCR_FREQ_0 (1 << 9) 84 #define RME96_WCR_FREQ_1 (1 << 10) 85 #define RME96_WCR_DS (1 << 11) 86 #define RME96_WCR_PRO (1 << 12) 87 #define RME96_WCR_EMP (1 << 13) 88 #define RME96_WCR_SEL (1 << 14) 89 #define RME96_WCR_MASTER (1 << 15) 90 #define RME96_WCR_PD (1 << 16) 91 #define RME96_WCR_INP_0 (1 << 17) 92 #define RME96_WCR_INP_1 (1 << 18) 93 #define RME96_WCR_THRU_0 (1 << 19) 94 #define RME96_WCR_THRU_1 (1 << 20) 95 #define RME96_WCR_THRU_2 (1 << 21) 96 #define RME96_WCR_THRU_3 (1 << 22) 97 #define RME96_WCR_THRU_4 (1 << 23) 98 #define RME96_WCR_THRU_5 (1 << 24) 99 #define RME96_WCR_THRU_6 (1 << 25) 100 #define RME96_WCR_THRU_7 (1 << 26) 101 #define RME96_WCR_DOLBY (1 << 27) 102 #define RME96_WCR_MONITOR_0 (1 << 28) 103 #define RME96_WCR_MONITOR_1 (1 << 29) 104 #define RME96_WCR_ISEL (1 << 30) 105 #define RME96_WCR_IDIS (1 << 31) 106 107 #define RME96_WCR_BITPOS_GAIN_0 2 108 #define RME96_WCR_BITPOS_GAIN_1 3 109 #define RME96_WCR_BITPOS_FREQ_0 9 110 #define RME96_WCR_BITPOS_FREQ_1 10 111 #define RME96_WCR_BITPOS_INP_0 17 112 #define RME96_WCR_BITPOS_INP_1 18 113 #define RME96_WCR_BITPOS_MONITOR_0 28 114 #define RME96_WCR_BITPOS_MONITOR_1 29 115 116 /* Read control register bits */ 117 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 118 #define RME96_RCR_IRQ_2 (1 << 16) 119 #define RME96_RCR_T_OUT (1 << 17) 120 #define RME96_RCR_DEV_ID_0 (1 << 21) 121 #define RME96_RCR_DEV_ID_1 (1 << 22) 122 #define RME96_RCR_LOCK (1 << 23) 123 #define RME96_RCR_VERF (1 << 26) 124 #define RME96_RCR_F0 (1 << 27) 125 #define RME96_RCR_F1 (1 << 28) 126 #define RME96_RCR_F2 (1 << 29) 127 #define RME96_RCR_AUTOSYNC (1 << 30) 128 #define RME96_RCR_IRQ (1 << 31) 129 130 #define RME96_RCR_BITPOS_F0 27 131 #define RME96_RCR_BITPOS_F1 28 132 #define RME96_RCR_BITPOS_F2 29 133 134 /* Additional register bits */ 135 #define RME96_AR_WSEL (1 << 0) 136 #define RME96_AR_ANALOG (1 << 1) 137 #define RME96_AR_FREQPAD_0 (1 << 2) 138 #define RME96_AR_FREQPAD_1 (1 << 3) 139 #define RME96_AR_FREQPAD_2 (1 << 4) 140 #define RME96_AR_PD2 (1 << 5) 141 #define RME96_AR_DAC_EN (1 << 6) 142 #define RME96_AR_CLATCH (1 << 7) 143 #define RME96_AR_CCLK (1 << 8) 144 #define RME96_AR_CDATA (1 << 9) 145 146 #define RME96_AR_BITPOS_F0 2 147 #define RME96_AR_BITPOS_F1 3 148 #define RME96_AR_BITPOS_F2 4 149 150 /* Monitor tracks */ 151 #define RME96_MONITOR_TRACKS_1_2 0 152 #define RME96_MONITOR_TRACKS_3_4 1 153 #define RME96_MONITOR_TRACKS_5_6 2 154 #define RME96_MONITOR_TRACKS_7_8 3 155 156 /* Attenuation */ 157 #define RME96_ATTENUATION_0 0 158 #define RME96_ATTENUATION_6 1 159 #define RME96_ATTENUATION_12 2 160 #define RME96_ATTENUATION_18 3 161 162 /* Input types */ 163 #define RME96_INPUT_OPTICAL 0 164 #define RME96_INPUT_COAXIAL 1 165 #define RME96_INPUT_INTERNAL 2 166 #define RME96_INPUT_XLR 3 167 #define RME96_INPUT_ANALOG 4 168 169 /* Clock modes */ 170 #define RME96_CLOCKMODE_SLAVE 0 171 #define RME96_CLOCKMODE_MASTER 1 172 #define RME96_CLOCKMODE_WORDCLOCK 2 173 174 /* Block sizes in bytes */ 175 #define RME96_SMALL_BLOCK_SIZE 2048 176 #define RME96_LARGE_BLOCK_SIZE 8192 177 178 /* Volume control */ 179 #define RME96_AD1852_VOL_BITS 14 180 #define RME96_AD1855_VOL_BITS 10 181 182 /* Defines for snd_rme96_trigger */ 183 #define RME96_TB_START_PLAYBACK 1 184 #define RME96_TB_START_CAPTURE 2 185 #define RME96_TB_STOP_PLAYBACK 4 186 #define RME96_TB_STOP_CAPTURE 8 187 #define RME96_TB_RESET_PLAYPOS 16 188 #define RME96_TB_RESET_CAPTUREPOS 32 189 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 190 #define RME96_TB_CLEAR_CAPTURE_IRQ 128 191 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) 192 #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) 193 #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ 194 | RME96_RESUME_CAPTURE) 195 #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ 196 | RME96_TB_RESET_PLAYPOS) 197 #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ 198 | RME96_TB_RESET_CAPTUREPOS) 199 #define RME96_START_BOTH (RME96_START_PLAYBACK \ 200 | RME96_START_CAPTURE) 201 #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ 202 | RME96_TB_CLEAR_PLAYBACK_IRQ) 203 #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ 204 | RME96_TB_CLEAR_CAPTURE_IRQ) 205 #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ 206 | RME96_STOP_CAPTURE) 207 208 struct rme96 { 209 spinlock_t lock; 210 int irq; 211 unsigned long port; 212 void __iomem *iobase; 213 214 u32 wcreg; /* cached write control register value */ 215 u32 wcreg_spdif; /* S/PDIF setup */ 216 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 217 u32 rcreg; /* cached read control register value */ 218 u32 areg; /* cached additional register value */ 219 u16 vol[2]; /* cached volume of analog output */ 220 221 u8 rev; /* card revision number */ 222 223 #ifdef CONFIG_PM_SLEEP 224 u32 playback_pointer; 225 u32 capture_pointer; 226 void *playback_suspend_buffer; 227 void *capture_suspend_buffer; 228 #endif 229 230 struct snd_pcm_substream *playback_substream; 231 struct snd_pcm_substream *capture_substream; 232 233 int playback_frlog; /* log2 of framesize */ 234 int capture_frlog; 235 236 size_t playback_periodsize; /* in bytes, zero if not used */ 237 size_t capture_periodsize; /* in bytes, zero if not used */ 238 239 struct snd_card *card; 240 struct snd_pcm *spdif_pcm; 241 struct snd_pcm *adat_pcm; 242 struct pci_dev *pci; 243 struct snd_kcontrol *spdif_ctl; 244 }; 245 246 static const struct pci_device_id snd_rme96_ids[] = { 247 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, 248 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, 249 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, 250 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, 251 { 0, } 252 }; 253 254 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 255 256 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) 257 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) 258 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 259 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ 260 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 261 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) 262 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ 263 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) 264 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) 265 266 static int 267 snd_rme96_playback_prepare(struct snd_pcm_substream *substream); 268 269 static int 270 snd_rme96_capture_prepare(struct snd_pcm_substream *substream); 271 272 static int 273 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 274 int cmd); 275 276 static int 277 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 278 int cmd); 279 280 static snd_pcm_uframes_t 281 snd_rme96_playback_pointer(struct snd_pcm_substream *substream); 282 283 static snd_pcm_uframes_t 284 snd_rme96_capture_pointer(struct snd_pcm_substream *substream); 285 286 static void snd_rme96_proc_init(struct rme96 *rme96); 287 288 static int 289 snd_rme96_create_switches(struct snd_card *card, 290 struct rme96 *rme96); 291 292 static int 293 snd_rme96_getinputtype(struct rme96 *rme96); 294 295 static inline unsigned int 296 snd_rme96_playback_ptr(struct rme96 *rme96) 297 { 298 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 299 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; 300 } 301 302 static inline unsigned int 303 snd_rme96_capture_ptr(struct rme96 *rme96) 304 { 305 return (readl(rme96->iobase + RME96_IO_GET_REC_POS) 306 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; 307 } 308 309 static int 310 snd_rme96_playback_silence(struct snd_pcm_substream *substream, 311 int channel, unsigned long pos, unsigned long count) 312 { 313 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 314 315 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 316 0, count); 317 return 0; 318 } 319 320 static int 321 snd_rme96_playback_copy(struct snd_pcm_substream *substream, 322 int channel, unsigned long pos, 323 void __user *src, unsigned long count) 324 { 325 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 326 327 return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 328 src, count); 329 } 330 331 static int 332 snd_rme96_playback_copy_kernel(struct snd_pcm_substream *substream, 333 int channel, unsigned long pos, 334 void *src, unsigned long count) 335 { 336 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 337 338 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count); 339 return 0; 340 } 341 342 static int 343 snd_rme96_capture_copy(struct snd_pcm_substream *substream, 344 int channel, unsigned long pos, 345 void __user *dst, unsigned long count) 346 { 347 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 348 349 return copy_to_user_fromio(dst, 350 rme96->iobase + RME96_IO_REC_BUFFER + pos, 351 count); 352 } 353 354 static int 355 snd_rme96_capture_copy_kernel(struct snd_pcm_substream *substream, 356 int channel, unsigned long pos, 357 void *dst, unsigned long count) 358 { 359 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 360 361 memcpy_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count); 362 return 0; 363 } 364 365 /* 366 * Digital output capabilities (S/PDIF) 367 */ 368 static const struct snd_pcm_hardware snd_rme96_playback_spdif_info = 369 { 370 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 371 SNDRV_PCM_INFO_MMAP_VALID | 372 SNDRV_PCM_INFO_SYNC_START | 373 SNDRV_PCM_INFO_RESUME | 374 SNDRV_PCM_INFO_INTERLEAVED | 375 SNDRV_PCM_INFO_PAUSE), 376 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 377 SNDRV_PCM_FMTBIT_S32_LE), 378 .rates = (SNDRV_PCM_RATE_32000 | 379 SNDRV_PCM_RATE_44100 | 380 SNDRV_PCM_RATE_48000 | 381 SNDRV_PCM_RATE_64000 | 382 SNDRV_PCM_RATE_88200 | 383 SNDRV_PCM_RATE_96000), 384 .rate_min = 32000, 385 .rate_max = 96000, 386 .channels_min = 2, 387 .channels_max = 2, 388 .buffer_bytes_max = RME96_BUFFER_SIZE, 389 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 390 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 391 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 392 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 393 .fifo_size = 0, 394 }; 395 396 /* 397 * Digital input capabilities (S/PDIF) 398 */ 399 static const struct snd_pcm_hardware snd_rme96_capture_spdif_info = 400 { 401 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 402 SNDRV_PCM_INFO_MMAP_VALID | 403 SNDRV_PCM_INFO_SYNC_START | 404 SNDRV_PCM_INFO_RESUME | 405 SNDRV_PCM_INFO_INTERLEAVED | 406 SNDRV_PCM_INFO_PAUSE), 407 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 408 SNDRV_PCM_FMTBIT_S32_LE), 409 .rates = (SNDRV_PCM_RATE_32000 | 410 SNDRV_PCM_RATE_44100 | 411 SNDRV_PCM_RATE_48000 | 412 SNDRV_PCM_RATE_64000 | 413 SNDRV_PCM_RATE_88200 | 414 SNDRV_PCM_RATE_96000), 415 .rate_min = 32000, 416 .rate_max = 96000, 417 .channels_min = 2, 418 .channels_max = 2, 419 .buffer_bytes_max = RME96_BUFFER_SIZE, 420 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 421 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 422 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 423 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 424 .fifo_size = 0, 425 }; 426 427 /* 428 * Digital output capabilities (ADAT) 429 */ 430 static const struct snd_pcm_hardware snd_rme96_playback_adat_info = 431 { 432 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 433 SNDRV_PCM_INFO_MMAP_VALID | 434 SNDRV_PCM_INFO_SYNC_START | 435 SNDRV_PCM_INFO_RESUME | 436 SNDRV_PCM_INFO_INTERLEAVED | 437 SNDRV_PCM_INFO_PAUSE), 438 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 439 SNDRV_PCM_FMTBIT_S32_LE), 440 .rates = (SNDRV_PCM_RATE_44100 | 441 SNDRV_PCM_RATE_48000), 442 .rate_min = 44100, 443 .rate_max = 48000, 444 .channels_min = 8, 445 .channels_max = 8, 446 .buffer_bytes_max = RME96_BUFFER_SIZE, 447 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 448 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 449 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 450 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 451 .fifo_size = 0, 452 }; 453 454 /* 455 * Digital input capabilities (ADAT) 456 */ 457 static const struct snd_pcm_hardware snd_rme96_capture_adat_info = 458 { 459 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 460 SNDRV_PCM_INFO_MMAP_VALID | 461 SNDRV_PCM_INFO_SYNC_START | 462 SNDRV_PCM_INFO_RESUME | 463 SNDRV_PCM_INFO_INTERLEAVED | 464 SNDRV_PCM_INFO_PAUSE), 465 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 466 SNDRV_PCM_FMTBIT_S32_LE), 467 .rates = (SNDRV_PCM_RATE_44100 | 468 SNDRV_PCM_RATE_48000), 469 .rate_min = 44100, 470 .rate_max = 48000, 471 .channels_min = 8, 472 .channels_max = 8, 473 .buffer_bytes_max = RME96_BUFFER_SIZE, 474 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 475 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 476 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 477 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 478 .fifo_size = 0, 479 }; 480 481 /* 482 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface 483 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up 484 * on the falling edge of CCLK and be stable on the rising edge. The rising 485 * edge of CLATCH after the last data bit clocks in the whole data word. 486 * A fast processor could probably drive the SPI interface faster than the 487 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) 488 * limits the data rate to 500KHz and only causes a delay of 33 microsecs. 489 * 490 * NOTE: increased delay from 1 to 10, since there where problems setting 491 * the volume. 492 */ 493 static void 494 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) 495 { 496 int i; 497 498 for (i = 0; i < 16; i++) { 499 if (val & 0x8000) { 500 rme96->areg |= RME96_AR_CDATA; 501 } else { 502 rme96->areg &= ~RME96_AR_CDATA; 503 } 504 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); 505 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 506 udelay(10); 507 rme96->areg |= RME96_AR_CCLK; 508 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 509 udelay(10); 510 val <<= 1; 511 } 512 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); 513 rme96->areg |= RME96_AR_CLATCH; 514 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 515 udelay(10); 516 rme96->areg &= ~RME96_AR_CLATCH; 517 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 518 } 519 520 static void 521 snd_rme96_apply_dac_volume(struct rme96 *rme96) 522 { 523 if (RME96_DAC_IS_1852(rme96)) { 524 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); 525 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); 526 } else if (RME96_DAC_IS_1855(rme96)) { 527 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); 528 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); 529 } 530 } 531 532 static void 533 snd_rme96_reset_dac(struct rme96 *rme96) 534 { 535 writel(rme96->wcreg | RME96_WCR_PD, 536 rme96->iobase + RME96_IO_CONTROL_REGISTER); 537 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 538 } 539 540 static int 541 snd_rme96_getmontracks(struct rme96 *rme96) 542 { 543 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + 544 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); 545 } 546 547 static int 548 snd_rme96_setmontracks(struct rme96 *rme96, 549 int montracks) 550 { 551 if (montracks & 1) { 552 rme96->wcreg |= RME96_WCR_MONITOR_0; 553 } else { 554 rme96->wcreg &= ~RME96_WCR_MONITOR_0; 555 } 556 if (montracks & 2) { 557 rme96->wcreg |= RME96_WCR_MONITOR_1; 558 } else { 559 rme96->wcreg &= ~RME96_WCR_MONITOR_1; 560 } 561 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 562 return 0; 563 } 564 565 static int 566 snd_rme96_getattenuation(struct rme96 *rme96) 567 { 568 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + 569 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); 570 } 571 572 static int 573 snd_rme96_setattenuation(struct rme96 *rme96, 574 int attenuation) 575 { 576 switch (attenuation) { 577 case 0: 578 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & 579 ~RME96_WCR_GAIN_1; 580 break; 581 case 1: 582 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & 583 ~RME96_WCR_GAIN_1; 584 break; 585 case 2: 586 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | 587 RME96_WCR_GAIN_1; 588 break; 589 case 3: 590 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | 591 RME96_WCR_GAIN_1; 592 break; 593 default: 594 return -EINVAL; 595 } 596 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 597 return 0; 598 } 599 600 static int 601 snd_rme96_capture_getrate(struct rme96 *rme96, 602 int *is_adat) 603 { 604 int n, rate; 605 606 *is_adat = 0; 607 if (rme96->areg & RME96_AR_ANALOG) { 608 /* Analog input, overrides S/PDIF setting */ 609 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + 610 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); 611 switch (n) { 612 case 1: 613 rate = 32000; 614 break; 615 case 2: 616 rate = 44100; 617 break; 618 case 3: 619 rate = 48000; 620 break; 621 default: 622 return -1; 623 } 624 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; 625 } 626 627 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 628 if (rme96->rcreg & RME96_RCR_LOCK) { 629 /* ADAT rate */ 630 *is_adat = 1; 631 if (rme96->rcreg & RME96_RCR_T_OUT) { 632 return 48000; 633 } 634 return 44100; 635 } 636 637 if (rme96->rcreg & RME96_RCR_VERF) { 638 return -1; 639 } 640 641 /* S/PDIF rate */ 642 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + 643 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + 644 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); 645 646 switch (n) { 647 case 0: 648 if (rme96->rcreg & RME96_RCR_T_OUT) { 649 return 64000; 650 } 651 return -1; 652 case 3: return 96000; 653 case 4: return 88200; 654 case 5: return 48000; 655 case 6: return 44100; 656 case 7: return 32000; 657 default: 658 break; 659 } 660 return -1; 661 } 662 663 static int 664 snd_rme96_playback_getrate(struct rme96 *rme96) 665 { 666 int rate, dummy; 667 668 if (!(rme96->wcreg & RME96_WCR_MASTER) && 669 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 670 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 671 { 672 /* slave clock */ 673 return rate; 674 } 675 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + 676 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); 677 switch (rate) { 678 case 1: 679 rate = 32000; 680 break; 681 case 2: 682 rate = 44100; 683 break; 684 case 3: 685 rate = 48000; 686 break; 687 default: 688 return -1; 689 } 690 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; 691 } 692 693 static int 694 snd_rme96_playback_setrate(struct rme96 *rme96, 695 int rate) 696 { 697 int ds; 698 699 ds = rme96->wcreg & RME96_WCR_DS; 700 switch (rate) { 701 case 32000: 702 rme96->wcreg &= ~RME96_WCR_DS; 703 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 704 ~RME96_WCR_FREQ_1; 705 break; 706 case 44100: 707 rme96->wcreg &= ~RME96_WCR_DS; 708 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 709 ~RME96_WCR_FREQ_0; 710 break; 711 case 48000: 712 rme96->wcreg &= ~RME96_WCR_DS; 713 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 714 RME96_WCR_FREQ_1; 715 break; 716 case 64000: 717 rme96->wcreg |= RME96_WCR_DS; 718 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 719 ~RME96_WCR_FREQ_1; 720 break; 721 case 88200: 722 rme96->wcreg |= RME96_WCR_DS; 723 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 724 ~RME96_WCR_FREQ_0; 725 break; 726 case 96000: 727 rme96->wcreg |= RME96_WCR_DS; 728 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 729 RME96_WCR_FREQ_1; 730 break; 731 default: 732 return -EINVAL; 733 } 734 if ((!ds && rme96->wcreg & RME96_WCR_DS) || 735 (ds && !(rme96->wcreg & RME96_WCR_DS))) 736 { 737 /* change to/from double-speed: reset the DAC (if available) */ 738 snd_rme96_reset_dac(rme96); 739 return 1; /* need to restore volume */ 740 } else { 741 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 742 return 0; 743 } 744 } 745 746 static int 747 snd_rme96_capture_analog_setrate(struct rme96 *rme96, 748 int rate) 749 { 750 switch (rate) { 751 case 32000: 752 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 753 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 754 break; 755 case 44100: 756 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 757 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 758 break; 759 case 48000: 760 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 761 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 762 break; 763 case 64000: 764 if (rme96->rev < 4) { 765 return -EINVAL; 766 } 767 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 768 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 769 break; 770 case 88200: 771 if (rme96->rev < 4) { 772 return -EINVAL; 773 } 774 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 775 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 776 break; 777 case 96000: 778 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 779 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 780 break; 781 default: 782 return -EINVAL; 783 } 784 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 785 return 0; 786 } 787 788 static int 789 snd_rme96_setclockmode(struct rme96 *rme96, 790 int mode) 791 { 792 switch (mode) { 793 case RME96_CLOCKMODE_SLAVE: 794 /* AutoSync */ 795 rme96->wcreg &= ~RME96_WCR_MASTER; 796 rme96->areg &= ~RME96_AR_WSEL; 797 break; 798 case RME96_CLOCKMODE_MASTER: 799 /* Internal */ 800 rme96->wcreg |= RME96_WCR_MASTER; 801 rme96->areg &= ~RME96_AR_WSEL; 802 break; 803 case RME96_CLOCKMODE_WORDCLOCK: 804 /* Word clock is a master mode */ 805 rme96->wcreg |= RME96_WCR_MASTER; 806 rme96->areg |= RME96_AR_WSEL; 807 break; 808 default: 809 return -EINVAL; 810 } 811 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 812 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 813 return 0; 814 } 815 816 static int 817 snd_rme96_getclockmode(struct rme96 *rme96) 818 { 819 if (rme96->areg & RME96_AR_WSEL) { 820 return RME96_CLOCKMODE_WORDCLOCK; 821 } 822 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : 823 RME96_CLOCKMODE_SLAVE; 824 } 825 826 static int 827 snd_rme96_setinputtype(struct rme96 *rme96, 828 int type) 829 { 830 int n; 831 832 switch (type) { 833 case RME96_INPUT_OPTICAL: 834 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & 835 ~RME96_WCR_INP_1; 836 break; 837 case RME96_INPUT_COAXIAL: 838 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & 839 ~RME96_WCR_INP_1; 840 break; 841 case RME96_INPUT_INTERNAL: 842 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | 843 RME96_WCR_INP_1; 844 break; 845 case RME96_INPUT_XLR: 846 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 847 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || 848 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 849 rme96->rev > 4)) 850 { 851 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ 852 return -EINVAL; 853 } 854 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | 855 RME96_WCR_INP_1; 856 break; 857 case RME96_INPUT_ANALOG: 858 if (!RME96_HAS_ANALOG_IN(rme96)) { 859 return -EINVAL; 860 } 861 rme96->areg |= RME96_AR_ANALOG; 862 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 863 if (rme96->rev < 4) { 864 /* 865 * Revision less than 004 does not support 64 and 866 * 88.2 kHz 867 */ 868 if (snd_rme96_capture_getrate(rme96, &n) == 88200) { 869 snd_rme96_capture_analog_setrate(rme96, 44100); 870 } 871 if (snd_rme96_capture_getrate(rme96, &n) == 64000) { 872 snd_rme96_capture_analog_setrate(rme96, 32000); 873 } 874 } 875 return 0; 876 default: 877 return -EINVAL; 878 } 879 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { 880 rme96->areg &= ~RME96_AR_ANALOG; 881 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 882 } 883 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 884 return 0; 885 } 886 887 static int 888 snd_rme96_getinputtype(struct rme96 *rme96) 889 { 890 if (rme96->areg & RME96_AR_ANALOG) { 891 return RME96_INPUT_ANALOG; 892 } 893 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + 894 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); 895 } 896 897 static void 898 snd_rme96_setframelog(struct rme96 *rme96, 899 int n_channels, 900 int is_playback) 901 { 902 int frlog; 903 904 if (n_channels == 2) { 905 frlog = 1; 906 } else { 907 /* assume 8 channels */ 908 frlog = 3; 909 } 910 if (is_playback) { 911 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; 912 rme96->playback_frlog = frlog; 913 } else { 914 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; 915 rme96->capture_frlog = frlog; 916 } 917 } 918 919 static int 920 snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format) 921 { 922 switch (format) { 923 case SNDRV_PCM_FORMAT_S16_LE: 924 rme96->wcreg &= ~RME96_WCR_MODE24; 925 break; 926 case SNDRV_PCM_FORMAT_S32_LE: 927 rme96->wcreg |= RME96_WCR_MODE24; 928 break; 929 default: 930 return -EINVAL; 931 } 932 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 933 return 0; 934 } 935 936 static int 937 snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format) 938 { 939 switch (format) { 940 case SNDRV_PCM_FORMAT_S16_LE: 941 rme96->wcreg &= ~RME96_WCR_MODE24_2; 942 break; 943 case SNDRV_PCM_FORMAT_S32_LE: 944 rme96->wcreg |= RME96_WCR_MODE24_2; 945 break; 946 default: 947 return -EINVAL; 948 } 949 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 950 return 0; 951 } 952 953 static void 954 snd_rme96_set_period_properties(struct rme96 *rme96, 955 size_t period_bytes) 956 { 957 switch (period_bytes) { 958 case RME96_LARGE_BLOCK_SIZE: 959 rme96->wcreg &= ~RME96_WCR_ISEL; 960 break; 961 case RME96_SMALL_BLOCK_SIZE: 962 rme96->wcreg |= RME96_WCR_ISEL; 963 break; 964 default: 965 snd_BUG(); 966 break; 967 } 968 rme96->wcreg &= ~RME96_WCR_IDIS; 969 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 970 } 971 972 static int 973 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, 974 struct snd_pcm_hw_params *params) 975 { 976 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 977 struct snd_pcm_runtime *runtime = substream->runtime; 978 int err, rate, dummy; 979 bool apply_dac_volume = false; 980 981 runtime->dma_area = (void __force *)(rme96->iobase + 982 RME96_IO_PLAY_BUFFER); 983 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; 984 runtime->dma_bytes = RME96_BUFFER_SIZE; 985 986 spin_lock_irq(&rme96->lock); 987 if (!(rme96->wcreg & RME96_WCR_MASTER) && 988 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 989 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 990 { 991 /* slave clock */ 992 if ((int)params_rate(params) != rate) { 993 err = -EIO; 994 goto error; 995 } 996 } else { 997 err = snd_rme96_playback_setrate(rme96, params_rate(params)); 998 if (err < 0) 999 goto error; 1000 apply_dac_volume = err > 0; /* need to restore volume later? */ 1001 } 1002 1003 err = snd_rme96_playback_setformat(rme96, params_format(params)); 1004 if (err < 0) 1005 goto error; 1006 snd_rme96_setframelog(rme96, params_channels(params), 1); 1007 if (rme96->capture_periodsize != 0) { 1008 if (params_period_size(params) << rme96->playback_frlog != 1009 rme96->capture_periodsize) 1010 { 1011 err = -EBUSY; 1012 goto error; 1013 } 1014 } 1015 rme96->playback_periodsize = 1016 params_period_size(params) << rme96->playback_frlog; 1017 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); 1018 /* S/PDIF setup */ 1019 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { 1020 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 1021 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1022 } 1023 1024 err = 0; 1025 error: 1026 spin_unlock_irq(&rme96->lock); 1027 if (apply_dac_volume) { 1028 usleep_range(3000, 10000); 1029 snd_rme96_apply_dac_volume(rme96); 1030 } 1031 1032 return err; 1033 } 1034 1035 static int 1036 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, 1037 struct snd_pcm_hw_params *params) 1038 { 1039 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1040 struct snd_pcm_runtime *runtime = substream->runtime; 1041 int err, isadat, rate; 1042 1043 runtime->dma_area = (void __force *)(rme96->iobase + 1044 RME96_IO_REC_BUFFER); 1045 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; 1046 runtime->dma_bytes = RME96_BUFFER_SIZE; 1047 1048 spin_lock_irq(&rme96->lock); 1049 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) { 1050 spin_unlock_irq(&rme96->lock); 1051 return err; 1052 } 1053 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1054 if ((err = snd_rme96_capture_analog_setrate(rme96, 1055 params_rate(params))) < 0) 1056 { 1057 spin_unlock_irq(&rme96->lock); 1058 return err; 1059 } 1060 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1061 if ((int)params_rate(params) != rate) { 1062 spin_unlock_irq(&rme96->lock); 1063 return -EIO; 1064 } 1065 if ((isadat && runtime->hw.channels_min == 2) || 1066 (!isadat && runtime->hw.channels_min == 8)) 1067 { 1068 spin_unlock_irq(&rme96->lock); 1069 return -EIO; 1070 } 1071 } 1072 snd_rme96_setframelog(rme96, params_channels(params), 0); 1073 if (rme96->playback_periodsize != 0) { 1074 if (params_period_size(params) << rme96->capture_frlog != 1075 rme96->playback_periodsize) 1076 { 1077 spin_unlock_irq(&rme96->lock); 1078 return -EBUSY; 1079 } 1080 } 1081 rme96->capture_periodsize = 1082 params_period_size(params) << rme96->capture_frlog; 1083 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); 1084 spin_unlock_irq(&rme96->lock); 1085 1086 return 0; 1087 } 1088 1089 static void 1090 snd_rme96_trigger(struct rme96 *rme96, 1091 int op) 1092 { 1093 if (op & RME96_TB_RESET_PLAYPOS) 1094 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1095 if (op & RME96_TB_RESET_CAPTUREPOS) 1096 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1097 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { 1098 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1099 if (rme96->rcreg & RME96_RCR_IRQ) 1100 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1101 } 1102 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { 1103 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1104 if (rme96->rcreg & RME96_RCR_IRQ_2) 1105 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1106 } 1107 if (op & RME96_TB_START_PLAYBACK) 1108 rme96->wcreg |= RME96_WCR_START; 1109 if (op & RME96_TB_STOP_PLAYBACK) 1110 rme96->wcreg &= ~RME96_WCR_START; 1111 if (op & RME96_TB_START_CAPTURE) 1112 rme96->wcreg |= RME96_WCR_START_2; 1113 if (op & RME96_TB_STOP_CAPTURE) 1114 rme96->wcreg &= ~RME96_WCR_START_2; 1115 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1116 } 1117 1118 1119 1120 static irqreturn_t 1121 snd_rme96_interrupt(int irq, 1122 void *dev_id) 1123 { 1124 struct rme96 *rme96 = (struct rme96 *)dev_id; 1125 1126 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1127 /* fastpath out, to ease interrupt sharing */ 1128 if (!((rme96->rcreg & RME96_RCR_IRQ) || 1129 (rme96->rcreg & RME96_RCR_IRQ_2))) 1130 { 1131 return IRQ_NONE; 1132 } 1133 1134 if (rme96->rcreg & RME96_RCR_IRQ) { 1135 /* playback */ 1136 snd_pcm_period_elapsed(rme96->playback_substream); 1137 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1138 } 1139 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1140 /* capture */ 1141 snd_pcm_period_elapsed(rme96->capture_substream); 1142 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1143 } 1144 return IRQ_HANDLED; 1145 } 1146 1147 static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; 1148 1149 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 1150 .count = ARRAY_SIZE(period_bytes), 1151 .list = period_bytes, 1152 .mask = 0 1153 }; 1154 1155 static void 1156 rme96_set_buffer_size_constraint(struct rme96 *rme96, 1157 struct snd_pcm_runtime *runtime) 1158 { 1159 unsigned int size; 1160 1161 snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1162 RME96_BUFFER_SIZE); 1163 if ((size = rme96->playback_periodsize) != 0 || 1164 (size = rme96->capture_periodsize) != 0) 1165 snd_pcm_hw_constraint_single(runtime, 1166 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1167 size); 1168 else 1169 snd_pcm_hw_constraint_list(runtime, 0, 1170 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1171 &hw_constraints_period_bytes); 1172 } 1173 1174 static int 1175 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) 1176 { 1177 int rate, dummy; 1178 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1179 struct snd_pcm_runtime *runtime = substream->runtime; 1180 1181 snd_pcm_set_sync(substream); 1182 spin_lock_irq(&rme96->lock); 1183 if (rme96->playback_substream) { 1184 spin_unlock_irq(&rme96->lock); 1185 return -EBUSY; 1186 } 1187 rme96->wcreg &= ~RME96_WCR_ADAT; 1188 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1189 rme96->playback_substream = substream; 1190 spin_unlock_irq(&rme96->lock); 1191 1192 runtime->hw = snd_rme96_playback_spdif_info; 1193 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1194 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1195 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1196 { 1197 /* slave clock */ 1198 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1199 runtime->hw.rate_min = rate; 1200 runtime->hw.rate_max = rate; 1201 } 1202 rme96_set_buffer_size_constraint(rme96, runtime); 1203 1204 rme96->wcreg_spdif_stream = rme96->wcreg_spdif; 1205 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1206 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1207 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1208 return 0; 1209 } 1210 1211 static int 1212 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) 1213 { 1214 int isadat, rate; 1215 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1216 struct snd_pcm_runtime *runtime = substream->runtime; 1217 1218 snd_pcm_set_sync(substream); 1219 runtime->hw = snd_rme96_capture_spdif_info; 1220 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1221 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) 1222 { 1223 if (isadat) { 1224 return -EIO; 1225 } 1226 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1227 runtime->hw.rate_min = rate; 1228 runtime->hw.rate_max = rate; 1229 } 1230 1231 spin_lock_irq(&rme96->lock); 1232 if (rme96->capture_substream) { 1233 spin_unlock_irq(&rme96->lock); 1234 return -EBUSY; 1235 } 1236 rme96->capture_substream = substream; 1237 spin_unlock_irq(&rme96->lock); 1238 1239 rme96_set_buffer_size_constraint(rme96, runtime); 1240 return 0; 1241 } 1242 1243 static int 1244 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) 1245 { 1246 int rate, dummy; 1247 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1248 struct snd_pcm_runtime *runtime = substream->runtime; 1249 1250 snd_pcm_set_sync(substream); 1251 spin_lock_irq(&rme96->lock); 1252 if (rme96->playback_substream) { 1253 spin_unlock_irq(&rme96->lock); 1254 return -EBUSY; 1255 } 1256 rme96->wcreg |= RME96_WCR_ADAT; 1257 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1258 rme96->playback_substream = substream; 1259 spin_unlock_irq(&rme96->lock); 1260 1261 runtime->hw = snd_rme96_playback_adat_info; 1262 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1263 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1264 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1265 { 1266 /* slave clock */ 1267 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1268 runtime->hw.rate_min = rate; 1269 runtime->hw.rate_max = rate; 1270 } 1271 rme96_set_buffer_size_constraint(rme96, runtime); 1272 return 0; 1273 } 1274 1275 static int 1276 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) 1277 { 1278 int isadat, rate; 1279 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1280 struct snd_pcm_runtime *runtime = substream->runtime; 1281 1282 snd_pcm_set_sync(substream); 1283 runtime->hw = snd_rme96_capture_adat_info; 1284 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1285 /* makes no sense to use analog input. Note that analog 1286 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ 1287 return -EIO; 1288 } 1289 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1290 if (!isadat) { 1291 return -EIO; 1292 } 1293 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1294 runtime->hw.rate_min = rate; 1295 runtime->hw.rate_max = rate; 1296 } 1297 1298 spin_lock_irq(&rme96->lock); 1299 if (rme96->capture_substream) { 1300 spin_unlock_irq(&rme96->lock); 1301 return -EBUSY; 1302 } 1303 rme96->capture_substream = substream; 1304 spin_unlock_irq(&rme96->lock); 1305 1306 rme96_set_buffer_size_constraint(rme96, runtime); 1307 return 0; 1308 } 1309 1310 static int 1311 snd_rme96_playback_close(struct snd_pcm_substream *substream) 1312 { 1313 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1314 int spdif = 0; 1315 1316 spin_lock_irq(&rme96->lock); 1317 if (RME96_ISPLAYING(rme96)) { 1318 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1319 } 1320 rme96->playback_substream = NULL; 1321 rme96->playback_periodsize = 0; 1322 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; 1323 spin_unlock_irq(&rme96->lock); 1324 if (spdif) { 1325 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1326 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1327 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1328 } 1329 return 0; 1330 } 1331 1332 static int 1333 snd_rme96_capture_close(struct snd_pcm_substream *substream) 1334 { 1335 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1336 1337 spin_lock_irq(&rme96->lock); 1338 if (RME96_ISRECORDING(rme96)) { 1339 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1340 } 1341 rme96->capture_substream = NULL; 1342 rme96->capture_periodsize = 0; 1343 spin_unlock_irq(&rme96->lock); 1344 return 0; 1345 } 1346 1347 static int 1348 snd_rme96_playback_prepare(struct snd_pcm_substream *substream) 1349 { 1350 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1351 1352 spin_lock_irq(&rme96->lock); 1353 if (RME96_ISPLAYING(rme96)) { 1354 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1355 } 1356 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1357 spin_unlock_irq(&rme96->lock); 1358 return 0; 1359 } 1360 1361 static int 1362 snd_rme96_capture_prepare(struct snd_pcm_substream *substream) 1363 { 1364 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1365 1366 spin_lock_irq(&rme96->lock); 1367 if (RME96_ISRECORDING(rme96)) { 1368 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1369 } 1370 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1371 spin_unlock_irq(&rme96->lock); 1372 return 0; 1373 } 1374 1375 static int 1376 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 1377 int cmd) 1378 { 1379 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1380 struct snd_pcm_substream *s; 1381 bool sync; 1382 1383 snd_pcm_group_for_each_entry(s, substream) { 1384 if (snd_pcm_substream_chip(s) == rme96) 1385 snd_pcm_trigger_done(s, substream); 1386 } 1387 1388 sync = (rme96->playback_substream && rme96->capture_substream) && 1389 (rme96->playback_substream->group == 1390 rme96->capture_substream->group); 1391 1392 switch (cmd) { 1393 case SNDRV_PCM_TRIGGER_START: 1394 if (!RME96_ISPLAYING(rme96)) { 1395 if (substream != rme96->playback_substream) 1396 return -EBUSY; 1397 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1398 : RME96_START_PLAYBACK); 1399 } 1400 break; 1401 1402 case SNDRV_PCM_TRIGGER_SUSPEND: 1403 case SNDRV_PCM_TRIGGER_STOP: 1404 if (RME96_ISPLAYING(rme96)) { 1405 if (substream != rme96->playback_substream) 1406 return -EBUSY; 1407 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1408 : RME96_STOP_PLAYBACK); 1409 } 1410 break; 1411 1412 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1413 if (RME96_ISPLAYING(rme96)) 1414 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1415 : RME96_STOP_PLAYBACK); 1416 break; 1417 1418 case SNDRV_PCM_TRIGGER_RESUME: 1419 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1420 if (!RME96_ISPLAYING(rme96)) 1421 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1422 : RME96_RESUME_PLAYBACK); 1423 break; 1424 1425 default: 1426 return -EINVAL; 1427 } 1428 1429 return 0; 1430 } 1431 1432 static int 1433 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 1434 int cmd) 1435 { 1436 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1437 struct snd_pcm_substream *s; 1438 bool sync; 1439 1440 snd_pcm_group_for_each_entry(s, substream) { 1441 if (snd_pcm_substream_chip(s) == rme96) 1442 snd_pcm_trigger_done(s, substream); 1443 } 1444 1445 sync = (rme96->playback_substream && rme96->capture_substream) && 1446 (rme96->playback_substream->group == 1447 rme96->capture_substream->group); 1448 1449 switch (cmd) { 1450 case SNDRV_PCM_TRIGGER_START: 1451 if (!RME96_ISRECORDING(rme96)) { 1452 if (substream != rme96->capture_substream) 1453 return -EBUSY; 1454 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1455 : RME96_START_CAPTURE); 1456 } 1457 break; 1458 1459 case SNDRV_PCM_TRIGGER_SUSPEND: 1460 case SNDRV_PCM_TRIGGER_STOP: 1461 if (RME96_ISRECORDING(rme96)) { 1462 if (substream != rme96->capture_substream) 1463 return -EBUSY; 1464 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1465 : RME96_STOP_CAPTURE); 1466 } 1467 break; 1468 1469 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1470 if (RME96_ISRECORDING(rme96)) 1471 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1472 : RME96_STOP_CAPTURE); 1473 break; 1474 1475 case SNDRV_PCM_TRIGGER_RESUME: 1476 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1477 if (!RME96_ISRECORDING(rme96)) 1478 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1479 : RME96_RESUME_CAPTURE); 1480 break; 1481 1482 default: 1483 return -EINVAL; 1484 } 1485 1486 return 0; 1487 } 1488 1489 static snd_pcm_uframes_t 1490 snd_rme96_playback_pointer(struct snd_pcm_substream *substream) 1491 { 1492 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1493 return snd_rme96_playback_ptr(rme96); 1494 } 1495 1496 static snd_pcm_uframes_t 1497 snd_rme96_capture_pointer(struct snd_pcm_substream *substream) 1498 { 1499 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1500 return snd_rme96_capture_ptr(rme96); 1501 } 1502 1503 static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = { 1504 .open = snd_rme96_playback_spdif_open, 1505 .close = snd_rme96_playback_close, 1506 .hw_params = snd_rme96_playback_hw_params, 1507 .prepare = snd_rme96_playback_prepare, 1508 .trigger = snd_rme96_playback_trigger, 1509 .pointer = snd_rme96_playback_pointer, 1510 .copy_user = snd_rme96_playback_copy, 1511 .copy_kernel = snd_rme96_playback_copy_kernel, 1512 .fill_silence = snd_rme96_playback_silence, 1513 .mmap = snd_pcm_lib_mmap_iomem, 1514 }; 1515 1516 static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = { 1517 .open = snd_rme96_capture_spdif_open, 1518 .close = snd_rme96_capture_close, 1519 .hw_params = snd_rme96_capture_hw_params, 1520 .prepare = snd_rme96_capture_prepare, 1521 .trigger = snd_rme96_capture_trigger, 1522 .pointer = snd_rme96_capture_pointer, 1523 .copy_user = snd_rme96_capture_copy, 1524 .copy_kernel = snd_rme96_capture_copy_kernel, 1525 .mmap = snd_pcm_lib_mmap_iomem, 1526 }; 1527 1528 static const struct snd_pcm_ops snd_rme96_playback_adat_ops = { 1529 .open = snd_rme96_playback_adat_open, 1530 .close = snd_rme96_playback_close, 1531 .hw_params = snd_rme96_playback_hw_params, 1532 .prepare = snd_rme96_playback_prepare, 1533 .trigger = snd_rme96_playback_trigger, 1534 .pointer = snd_rme96_playback_pointer, 1535 .copy_user = snd_rme96_playback_copy, 1536 .copy_kernel = snd_rme96_playback_copy_kernel, 1537 .fill_silence = snd_rme96_playback_silence, 1538 .mmap = snd_pcm_lib_mmap_iomem, 1539 }; 1540 1541 static const struct snd_pcm_ops snd_rme96_capture_adat_ops = { 1542 .open = snd_rme96_capture_adat_open, 1543 .close = snd_rme96_capture_close, 1544 .hw_params = snd_rme96_capture_hw_params, 1545 .prepare = snd_rme96_capture_prepare, 1546 .trigger = snd_rme96_capture_trigger, 1547 .pointer = snd_rme96_capture_pointer, 1548 .copy_user = snd_rme96_capture_copy, 1549 .copy_kernel = snd_rme96_capture_copy_kernel, 1550 .mmap = snd_pcm_lib_mmap_iomem, 1551 }; 1552 1553 static void 1554 snd_rme96_free(void *private_data) 1555 { 1556 struct rme96 *rme96 = (struct rme96 *)private_data; 1557 1558 if (!rme96) 1559 return; 1560 1561 if (rme96->irq >= 0) { 1562 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1563 rme96->areg &= ~RME96_AR_DAC_EN; 1564 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1565 free_irq(rme96->irq, (void *)rme96); 1566 rme96->irq = -1; 1567 } 1568 if (rme96->iobase) { 1569 iounmap(rme96->iobase); 1570 rme96->iobase = NULL; 1571 } 1572 if (rme96->port) { 1573 pci_release_regions(rme96->pci); 1574 rme96->port = 0; 1575 } 1576 #ifdef CONFIG_PM_SLEEP 1577 vfree(rme96->playback_suspend_buffer); 1578 vfree(rme96->capture_suspend_buffer); 1579 #endif 1580 pci_disable_device(rme96->pci); 1581 } 1582 1583 static void 1584 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) 1585 { 1586 struct rme96 *rme96 = pcm->private_data; 1587 rme96->spdif_pcm = NULL; 1588 } 1589 1590 static void 1591 snd_rme96_free_adat_pcm(struct snd_pcm *pcm) 1592 { 1593 struct rme96 *rme96 = pcm->private_data; 1594 rme96->adat_pcm = NULL; 1595 } 1596 1597 static int 1598 snd_rme96_create(struct rme96 *rme96) 1599 { 1600 struct pci_dev *pci = rme96->pci; 1601 int err; 1602 1603 rme96->irq = -1; 1604 spin_lock_init(&rme96->lock); 1605 1606 if ((err = pci_enable_device(pci)) < 0) 1607 return err; 1608 1609 if ((err = pci_request_regions(pci, "RME96")) < 0) 1610 return err; 1611 rme96->port = pci_resource_start(rme96->pci, 0); 1612 1613 rme96->iobase = ioremap(rme96->port, RME96_IO_SIZE); 1614 if (!rme96->iobase) { 1615 dev_err(rme96->card->dev, 1616 "unable to remap memory region 0x%lx-0x%lx\n", 1617 rme96->port, rme96->port + RME96_IO_SIZE - 1); 1618 return -ENOMEM; 1619 } 1620 1621 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED, 1622 KBUILD_MODNAME, rme96)) { 1623 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq); 1624 return -EBUSY; 1625 } 1626 rme96->irq = pci->irq; 1627 rme96->card->sync_irq = rme96->irq; 1628 1629 /* read the card's revision number */ 1630 pci_read_config_byte(pci, 8, &rme96->rev); 1631 1632 /* set up ALSA pcm device for S/PDIF */ 1633 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1634 1, 1, &rme96->spdif_pcm)) < 0) 1635 { 1636 return err; 1637 } 1638 rme96->spdif_pcm->private_data = rme96; 1639 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; 1640 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); 1641 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); 1642 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); 1643 1644 rme96->spdif_pcm->info_flags = 0; 1645 1646 /* set up ALSA pcm device for ADAT */ 1647 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { 1648 /* ADAT is not available on the base model */ 1649 rme96->adat_pcm = NULL; 1650 } else { 1651 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1652 1, 1, &rme96->adat_pcm)) < 0) 1653 { 1654 return err; 1655 } 1656 rme96->adat_pcm->private_data = rme96; 1657 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; 1658 strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); 1659 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); 1660 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); 1661 1662 rme96->adat_pcm->info_flags = 0; 1663 } 1664 1665 rme96->playback_periodsize = 0; 1666 rme96->capture_periodsize = 0; 1667 1668 /* make sure playback/capture is stopped, if by some reason active */ 1669 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1670 1671 /* set default values in registers */ 1672 rme96->wcreg = 1673 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ 1674 RME96_WCR_SEL | /* normal playback */ 1675 RME96_WCR_MASTER | /* set to master clock mode */ 1676 RME96_WCR_INP_0; /* set coaxial input */ 1677 1678 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ 1679 1680 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1681 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1682 1683 /* reset the ADC */ 1684 writel(rme96->areg | RME96_AR_PD2, 1685 rme96->iobase + RME96_IO_ADDITIONAL_REG); 1686 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1687 1688 /* reset and enable the DAC (order is important). */ 1689 snd_rme96_reset_dac(rme96); 1690 rme96->areg |= RME96_AR_DAC_EN; 1691 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1692 1693 /* reset playback and record buffer pointers */ 1694 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1695 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1696 1697 /* reset volume */ 1698 rme96->vol[0] = rme96->vol[1] = 0; 1699 if (RME96_HAS_ANALOG_OUT(rme96)) { 1700 snd_rme96_apply_dac_volume(rme96); 1701 } 1702 1703 /* init switch interface */ 1704 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) { 1705 return err; 1706 } 1707 1708 /* init proc interface */ 1709 snd_rme96_proc_init(rme96); 1710 1711 return 0; 1712 } 1713 1714 /* 1715 * proc interface 1716 */ 1717 1718 static void 1719 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1720 { 1721 int n; 1722 struct rme96 *rme96 = entry->private_data; 1723 1724 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1725 1726 snd_iprintf(buffer, rme96->card->longname); 1727 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); 1728 1729 snd_iprintf(buffer, "\nGeneral settings\n"); 1730 if (rme96->wcreg & RME96_WCR_IDIS) { 1731 snd_iprintf(buffer, " period size: N/A (interrupts " 1732 "disabled)\n"); 1733 } else if (rme96->wcreg & RME96_WCR_ISEL) { 1734 snd_iprintf(buffer, " period size: 2048 bytes\n"); 1735 } else { 1736 snd_iprintf(buffer, " period size: 8192 bytes\n"); 1737 } 1738 snd_iprintf(buffer, "\nInput settings\n"); 1739 switch (snd_rme96_getinputtype(rme96)) { 1740 case RME96_INPUT_OPTICAL: 1741 snd_iprintf(buffer, " input: optical"); 1742 break; 1743 case RME96_INPUT_COAXIAL: 1744 snd_iprintf(buffer, " input: coaxial"); 1745 break; 1746 case RME96_INPUT_INTERNAL: 1747 snd_iprintf(buffer, " input: internal"); 1748 break; 1749 case RME96_INPUT_XLR: 1750 snd_iprintf(buffer, " input: XLR"); 1751 break; 1752 case RME96_INPUT_ANALOG: 1753 snd_iprintf(buffer, " input: analog"); 1754 break; 1755 } 1756 if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1757 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1758 } else { 1759 if (n) { 1760 snd_iprintf(buffer, " (8 channels)\n"); 1761 } else { 1762 snd_iprintf(buffer, " (2 channels)\n"); 1763 } 1764 snd_iprintf(buffer, " sample rate: %d Hz\n", 1765 snd_rme96_capture_getrate(rme96, &n)); 1766 } 1767 if (rme96->wcreg & RME96_WCR_MODE24_2) { 1768 snd_iprintf(buffer, " sample format: 24 bit\n"); 1769 } else { 1770 snd_iprintf(buffer, " sample format: 16 bit\n"); 1771 } 1772 1773 snd_iprintf(buffer, "\nOutput settings\n"); 1774 if (rme96->wcreg & RME96_WCR_SEL) { 1775 snd_iprintf(buffer, " output signal: normal playback\n"); 1776 } else { 1777 snd_iprintf(buffer, " output signal: same as input\n"); 1778 } 1779 snd_iprintf(buffer, " sample rate: %d Hz\n", 1780 snd_rme96_playback_getrate(rme96)); 1781 if (rme96->wcreg & RME96_WCR_MODE24) { 1782 snd_iprintf(buffer, " sample format: 24 bit\n"); 1783 } else { 1784 snd_iprintf(buffer, " sample format: 16 bit\n"); 1785 } 1786 if (rme96->areg & RME96_AR_WSEL) { 1787 snd_iprintf(buffer, " sample clock source: word clock\n"); 1788 } else if (rme96->wcreg & RME96_WCR_MASTER) { 1789 snd_iprintf(buffer, " sample clock source: internal\n"); 1790 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1791 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); 1792 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1793 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); 1794 } else { 1795 snd_iprintf(buffer, " sample clock source: autosync\n"); 1796 } 1797 if (rme96->wcreg & RME96_WCR_PRO) { 1798 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1799 } else { 1800 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1801 } 1802 if (rme96->wcreg & RME96_WCR_EMP) { 1803 snd_iprintf(buffer, " emphasis: on\n"); 1804 } else { 1805 snd_iprintf(buffer, " emphasis: off\n"); 1806 } 1807 if (rme96->wcreg & RME96_WCR_DOLBY) { 1808 snd_iprintf(buffer, " non-audio (dolby): on\n"); 1809 } else { 1810 snd_iprintf(buffer, " non-audio (dolby): off\n"); 1811 } 1812 if (RME96_HAS_ANALOG_IN(rme96)) { 1813 snd_iprintf(buffer, "\nAnalog output settings\n"); 1814 switch (snd_rme96_getmontracks(rme96)) { 1815 case RME96_MONITOR_TRACKS_1_2: 1816 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); 1817 break; 1818 case RME96_MONITOR_TRACKS_3_4: 1819 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); 1820 break; 1821 case RME96_MONITOR_TRACKS_5_6: 1822 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); 1823 break; 1824 case RME96_MONITOR_TRACKS_7_8: 1825 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); 1826 break; 1827 } 1828 switch (snd_rme96_getattenuation(rme96)) { 1829 case RME96_ATTENUATION_0: 1830 snd_iprintf(buffer, " attenuation: 0 dB\n"); 1831 break; 1832 case RME96_ATTENUATION_6: 1833 snd_iprintf(buffer, " attenuation: -6 dB\n"); 1834 break; 1835 case RME96_ATTENUATION_12: 1836 snd_iprintf(buffer, " attenuation: -12 dB\n"); 1837 break; 1838 case RME96_ATTENUATION_18: 1839 snd_iprintf(buffer, " attenuation: -18 dB\n"); 1840 break; 1841 } 1842 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); 1843 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); 1844 } 1845 } 1846 1847 static void snd_rme96_proc_init(struct rme96 *rme96) 1848 { 1849 snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read); 1850 } 1851 1852 /* 1853 * control interface 1854 */ 1855 1856 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info 1857 1858 static int 1859 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1860 { 1861 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1862 1863 spin_lock_irq(&rme96->lock); 1864 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; 1865 spin_unlock_irq(&rme96->lock); 1866 return 0; 1867 } 1868 static int 1869 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1870 { 1871 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1872 unsigned int val; 1873 int change; 1874 1875 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; 1876 spin_lock_irq(&rme96->lock); 1877 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; 1878 change = val != rme96->wcreg; 1879 rme96->wcreg = val; 1880 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1881 spin_unlock_irq(&rme96->lock); 1882 return change; 1883 } 1884 1885 static int 1886 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1887 { 1888 static const char * const _texts[5] = { 1889 "Optical", "Coaxial", "Internal", "XLR", "Analog" 1890 }; 1891 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1892 const char *texts[5] = { 1893 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] 1894 }; 1895 int num_items; 1896 1897 switch (rme96->pci->device) { 1898 case PCI_DEVICE_ID_RME_DIGI96: 1899 case PCI_DEVICE_ID_RME_DIGI96_8: 1900 num_items = 3; 1901 break; 1902 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1903 num_items = 4; 1904 break; 1905 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1906 if (rme96->rev > 4) { 1907 /* PST */ 1908 num_items = 4; 1909 texts[3] = _texts[4]; /* Analog instead of XLR */ 1910 } else { 1911 /* PAD */ 1912 num_items = 5; 1913 } 1914 break; 1915 default: 1916 snd_BUG(); 1917 return -EINVAL; 1918 } 1919 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1920 } 1921 static int 1922 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1923 { 1924 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1925 unsigned int items = 3; 1926 1927 spin_lock_irq(&rme96->lock); 1928 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); 1929 1930 switch (rme96->pci->device) { 1931 case PCI_DEVICE_ID_RME_DIGI96: 1932 case PCI_DEVICE_ID_RME_DIGI96_8: 1933 items = 3; 1934 break; 1935 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1936 items = 4; 1937 break; 1938 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1939 if (rme96->rev > 4) { 1940 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ 1941 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { 1942 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; 1943 } 1944 items = 4; 1945 } else { 1946 items = 5; 1947 } 1948 break; 1949 default: 1950 snd_BUG(); 1951 break; 1952 } 1953 if (ucontrol->value.enumerated.item[0] >= items) { 1954 ucontrol->value.enumerated.item[0] = items - 1; 1955 } 1956 1957 spin_unlock_irq(&rme96->lock); 1958 return 0; 1959 } 1960 static int 1961 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1962 { 1963 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1964 unsigned int val; 1965 int change, items = 3; 1966 1967 switch (rme96->pci->device) { 1968 case PCI_DEVICE_ID_RME_DIGI96: 1969 case PCI_DEVICE_ID_RME_DIGI96_8: 1970 items = 3; 1971 break; 1972 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1973 items = 4; 1974 break; 1975 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1976 if (rme96->rev > 4) { 1977 items = 4; 1978 } else { 1979 items = 5; 1980 } 1981 break; 1982 default: 1983 snd_BUG(); 1984 break; 1985 } 1986 val = ucontrol->value.enumerated.item[0] % items; 1987 1988 /* special case for PST */ 1989 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { 1990 if (val == RME96_INPUT_XLR) { 1991 val = RME96_INPUT_ANALOG; 1992 } 1993 } 1994 1995 spin_lock_irq(&rme96->lock); 1996 change = (int)val != snd_rme96_getinputtype(rme96); 1997 snd_rme96_setinputtype(rme96, val); 1998 spin_unlock_irq(&rme96->lock); 1999 return change; 2000 } 2001 2002 static int 2003 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2004 { 2005 static const char * const texts[3] = { "AutoSync", "Internal", "Word" }; 2006 2007 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2008 } 2009 static int 2010 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2011 { 2012 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2013 2014 spin_lock_irq(&rme96->lock); 2015 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); 2016 spin_unlock_irq(&rme96->lock); 2017 return 0; 2018 } 2019 static int 2020 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2021 { 2022 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2023 unsigned int val; 2024 int change; 2025 2026 val = ucontrol->value.enumerated.item[0] % 3; 2027 spin_lock_irq(&rme96->lock); 2028 change = (int)val != snd_rme96_getclockmode(rme96); 2029 snd_rme96_setclockmode(rme96, val); 2030 spin_unlock_irq(&rme96->lock); 2031 return change; 2032 } 2033 2034 static int 2035 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2036 { 2037 static const char * const texts[4] = { 2038 "0 dB", "-6 dB", "-12 dB", "-18 dB" 2039 }; 2040 2041 return snd_ctl_enum_info(uinfo, 1, 4, texts); 2042 } 2043 static int 2044 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2045 { 2046 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2047 2048 spin_lock_irq(&rme96->lock); 2049 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); 2050 spin_unlock_irq(&rme96->lock); 2051 return 0; 2052 } 2053 static int 2054 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2055 { 2056 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2057 unsigned int val; 2058 int change; 2059 2060 val = ucontrol->value.enumerated.item[0] % 4; 2061 spin_lock_irq(&rme96->lock); 2062 2063 change = (int)val != snd_rme96_getattenuation(rme96); 2064 snd_rme96_setattenuation(rme96, val); 2065 spin_unlock_irq(&rme96->lock); 2066 return change; 2067 } 2068 2069 static int 2070 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2071 { 2072 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" }; 2073 2074 return snd_ctl_enum_info(uinfo, 1, 4, texts); 2075 } 2076 static int 2077 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2078 { 2079 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2080 2081 spin_lock_irq(&rme96->lock); 2082 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); 2083 spin_unlock_irq(&rme96->lock); 2084 return 0; 2085 } 2086 static int 2087 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2088 { 2089 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2090 unsigned int val; 2091 int change; 2092 2093 val = ucontrol->value.enumerated.item[0] % 4; 2094 spin_lock_irq(&rme96->lock); 2095 change = (int)val != snd_rme96_getmontracks(rme96); 2096 snd_rme96_setmontracks(rme96, val); 2097 spin_unlock_irq(&rme96->lock); 2098 return change; 2099 } 2100 2101 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) 2102 { 2103 u32 val = 0; 2104 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; 2105 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; 2106 if (val & RME96_WCR_PRO) 2107 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2108 else 2109 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2110 return val; 2111 } 2112 2113 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 2114 { 2115 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | 2116 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); 2117 if (val & RME96_WCR_PRO) 2118 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 2119 else 2120 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 2121 } 2122 2123 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2124 { 2125 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2126 uinfo->count = 1; 2127 return 0; 2128 } 2129 2130 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2131 { 2132 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2133 2134 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); 2135 return 0; 2136 } 2137 2138 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2139 { 2140 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2141 int change; 2142 u32 val; 2143 2144 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2145 spin_lock_irq(&rme96->lock); 2146 change = val != rme96->wcreg_spdif; 2147 rme96->wcreg_spdif = val; 2148 spin_unlock_irq(&rme96->lock); 2149 return change; 2150 } 2151 2152 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2153 { 2154 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2155 uinfo->count = 1; 2156 return 0; 2157 } 2158 2159 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2160 { 2161 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2162 2163 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); 2164 return 0; 2165 } 2166 2167 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2168 { 2169 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2170 int change; 2171 u32 val; 2172 2173 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2174 spin_lock_irq(&rme96->lock); 2175 change = val != rme96->wcreg_spdif_stream; 2176 rme96->wcreg_spdif_stream = val; 2177 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 2178 rme96->wcreg |= val; 2179 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 2180 spin_unlock_irq(&rme96->lock); 2181 return change; 2182 } 2183 2184 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2185 { 2186 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2187 uinfo->count = 1; 2188 return 0; 2189 } 2190 2191 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2192 { 2193 ucontrol->value.iec958.status[0] = kcontrol->private_value; 2194 return 0; 2195 } 2196 2197 static int 2198 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2199 { 2200 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2201 2202 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2203 uinfo->count = 2; 2204 uinfo->value.integer.min = 0; 2205 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); 2206 return 0; 2207 } 2208 2209 static int 2210 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2211 { 2212 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2213 2214 spin_lock_irq(&rme96->lock); 2215 u->value.integer.value[0] = rme96->vol[0]; 2216 u->value.integer.value[1] = rme96->vol[1]; 2217 spin_unlock_irq(&rme96->lock); 2218 2219 return 0; 2220 } 2221 2222 static int 2223 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2224 { 2225 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2226 int change = 0; 2227 unsigned int vol, maxvol; 2228 2229 2230 if (!RME96_HAS_ANALOG_OUT(rme96)) 2231 return -EINVAL; 2232 maxvol = RME96_185X_MAX_OUT(rme96); 2233 spin_lock_irq(&rme96->lock); 2234 vol = u->value.integer.value[0]; 2235 if (vol != rme96->vol[0] && vol <= maxvol) { 2236 rme96->vol[0] = vol; 2237 change = 1; 2238 } 2239 vol = u->value.integer.value[1]; 2240 if (vol != rme96->vol[1] && vol <= maxvol) { 2241 rme96->vol[1] = vol; 2242 change = 1; 2243 } 2244 if (change) 2245 snd_rme96_apply_dac_volume(rme96); 2246 spin_unlock_irq(&rme96->lock); 2247 2248 return change; 2249 } 2250 2251 static const struct snd_kcontrol_new snd_rme96_controls[] = { 2252 { 2253 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2254 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2255 .info = snd_rme96_control_spdif_info, 2256 .get = snd_rme96_control_spdif_get, 2257 .put = snd_rme96_control_spdif_put 2258 }, 2259 { 2260 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2261 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2262 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2263 .info = snd_rme96_control_spdif_stream_info, 2264 .get = snd_rme96_control_spdif_stream_get, 2265 .put = snd_rme96_control_spdif_stream_put 2266 }, 2267 { 2268 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2269 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2270 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2271 .info = snd_rme96_control_spdif_mask_info, 2272 .get = snd_rme96_control_spdif_mask_get, 2273 .private_value = IEC958_AES0_NONAUDIO | 2274 IEC958_AES0_PROFESSIONAL | 2275 IEC958_AES0_CON_EMPHASIS 2276 }, 2277 { 2278 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2279 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2280 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2281 .info = snd_rme96_control_spdif_mask_info, 2282 .get = snd_rme96_control_spdif_mask_get, 2283 .private_value = IEC958_AES0_NONAUDIO | 2284 IEC958_AES0_PROFESSIONAL | 2285 IEC958_AES0_PRO_EMPHASIS 2286 }, 2287 { 2288 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2289 .name = "Input Connector", 2290 .info = snd_rme96_info_inputtype_control, 2291 .get = snd_rme96_get_inputtype_control, 2292 .put = snd_rme96_put_inputtype_control 2293 }, 2294 { 2295 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2296 .name = "Loopback Input", 2297 .info = snd_rme96_info_loopback_control, 2298 .get = snd_rme96_get_loopback_control, 2299 .put = snd_rme96_put_loopback_control 2300 }, 2301 { 2302 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2303 .name = "Sample Clock Source", 2304 .info = snd_rme96_info_clockmode_control, 2305 .get = snd_rme96_get_clockmode_control, 2306 .put = snd_rme96_put_clockmode_control 2307 }, 2308 { 2309 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2310 .name = "Monitor Tracks", 2311 .info = snd_rme96_info_montracks_control, 2312 .get = snd_rme96_get_montracks_control, 2313 .put = snd_rme96_put_montracks_control 2314 }, 2315 { 2316 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2317 .name = "Attenuation", 2318 .info = snd_rme96_info_attenuation_control, 2319 .get = snd_rme96_get_attenuation_control, 2320 .put = snd_rme96_put_attenuation_control 2321 }, 2322 { 2323 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2324 .name = "DAC Playback Volume", 2325 .info = snd_rme96_dac_volume_info, 2326 .get = snd_rme96_dac_volume_get, 2327 .put = snd_rme96_dac_volume_put 2328 } 2329 }; 2330 2331 static int 2332 snd_rme96_create_switches(struct snd_card *card, 2333 struct rme96 *rme96) 2334 { 2335 int idx, err; 2336 struct snd_kcontrol *kctl; 2337 2338 for (idx = 0; idx < 7; idx++) { 2339 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2340 return err; 2341 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 2342 rme96->spdif_ctl = kctl; 2343 } 2344 2345 if (RME96_HAS_ANALOG_OUT(rme96)) { 2346 for (idx = 7; idx < 10; idx++) 2347 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2348 return err; 2349 } 2350 2351 return 0; 2352 } 2353 2354 /* 2355 * Card initialisation 2356 */ 2357 2358 #ifdef CONFIG_PM_SLEEP 2359 2360 static int rme96_suspend(struct device *dev) 2361 { 2362 struct snd_card *card = dev_get_drvdata(dev); 2363 struct rme96 *rme96 = card->private_data; 2364 2365 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2366 2367 /* save capture & playback pointers */ 2368 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 2369 & RME96_RCR_AUDIO_ADDR_MASK; 2370 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS) 2371 & RME96_RCR_AUDIO_ADDR_MASK; 2372 2373 /* save playback and capture buffers */ 2374 memcpy_fromio(rme96->playback_suspend_buffer, 2375 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); 2376 memcpy_fromio(rme96->capture_suspend_buffer, 2377 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); 2378 2379 /* disable the DAC */ 2380 rme96->areg &= ~RME96_AR_DAC_EN; 2381 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2382 return 0; 2383 } 2384 2385 static int rme96_resume(struct device *dev) 2386 { 2387 struct snd_card *card = dev_get_drvdata(dev); 2388 struct rme96 *rme96 = card->private_data; 2389 2390 /* reset playback and record buffer pointers */ 2391 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS 2392 + rme96->playback_pointer); 2393 writel(0, rme96->iobase + RME96_IO_SET_REC_POS 2394 + rme96->capture_pointer); 2395 2396 /* restore playback and capture buffers */ 2397 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, 2398 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); 2399 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, 2400 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); 2401 2402 /* reset the ADC */ 2403 writel(rme96->areg | RME96_AR_PD2, 2404 rme96->iobase + RME96_IO_ADDITIONAL_REG); 2405 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2406 2407 /* reset and enable DAC, restore analog volume */ 2408 snd_rme96_reset_dac(rme96); 2409 rme96->areg |= RME96_AR_DAC_EN; 2410 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2411 if (RME96_HAS_ANALOG_OUT(rme96)) { 2412 usleep_range(3000, 10000); 2413 snd_rme96_apply_dac_volume(rme96); 2414 } 2415 2416 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2417 2418 return 0; 2419 } 2420 2421 static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume); 2422 #define RME96_PM_OPS &rme96_pm 2423 #else 2424 #define RME96_PM_OPS NULL 2425 #endif /* CONFIG_PM_SLEEP */ 2426 2427 static void snd_rme96_card_free(struct snd_card *card) 2428 { 2429 snd_rme96_free(card->private_data); 2430 } 2431 2432 static int 2433 snd_rme96_probe(struct pci_dev *pci, 2434 const struct pci_device_id *pci_id) 2435 { 2436 static int dev; 2437 struct rme96 *rme96; 2438 struct snd_card *card; 2439 int err; 2440 u8 val; 2441 2442 if (dev >= SNDRV_CARDS) { 2443 return -ENODEV; 2444 } 2445 if (!enable[dev]) { 2446 dev++; 2447 return -ENOENT; 2448 } 2449 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2450 sizeof(struct rme96), &card); 2451 if (err < 0) 2452 return err; 2453 card->private_free = snd_rme96_card_free; 2454 rme96 = card->private_data; 2455 rme96->card = card; 2456 rme96->pci = pci; 2457 err = snd_rme96_create(rme96); 2458 if (err) 2459 goto free_card; 2460 2461 #ifdef CONFIG_PM_SLEEP 2462 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2463 if (!rme96->playback_suspend_buffer) { 2464 err = -ENOMEM; 2465 goto free_card; 2466 } 2467 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2468 if (!rme96->capture_suspend_buffer) { 2469 err = -ENOMEM; 2470 goto free_card; 2471 } 2472 #endif 2473 2474 strcpy(card->driver, "Digi96"); 2475 switch (rme96->pci->device) { 2476 case PCI_DEVICE_ID_RME_DIGI96: 2477 strcpy(card->shortname, "RME Digi96"); 2478 break; 2479 case PCI_DEVICE_ID_RME_DIGI96_8: 2480 strcpy(card->shortname, "RME Digi96/8"); 2481 break; 2482 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 2483 strcpy(card->shortname, "RME Digi96/8 PRO"); 2484 break; 2485 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 2486 pci_read_config_byte(rme96->pci, 8, &val); 2487 if (val < 5) { 2488 strcpy(card->shortname, "RME Digi96/8 PAD"); 2489 } else { 2490 strcpy(card->shortname, "RME Digi96/8 PST"); 2491 } 2492 break; 2493 } 2494 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, 2495 rme96->port, rme96->irq); 2496 err = snd_card_register(card); 2497 if (err) 2498 goto free_card; 2499 2500 pci_set_drvdata(pci, card); 2501 dev++; 2502 return 0; 2503 free_card: 2504 snd_card_free(card); 2505 return err; 2506 } 2507 2508 static void snd_rme96_remove(struct pci_dev *pci) 2509 { 2510 snd_card_free(pci_get_drvdata(pci)); 2511 } 2512 2513 static struct pci_driver rme96_driver = { 2514 .name = KBUILD_MODNAME, 2515 .id_table = snd_rme96_ids, 2516 .probe = snd_rme96_probe, 2517 .remove = snd_rme96_remove, 2518 .driver = { 2519 .pm = RME96_PM_OPS, 2520 }, 2521 }; 2522 2523 module_pci_driver(rme96_driver); 2524