1 /* 2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio 3 * interfaces 4 * 5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> 6 * 7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control 8 * code. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/init.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/module.h> 31 #include <linux/vmalloc.h> 32 33 #include <sound/core.h> 34 #include <sound/info.h> 35 #include <sound/control.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/asoundef.h> 39 #include <sound/initval.h> 40 41 #include <asm/io.h> 42 43 /* note, two last pcis should be equal, it is not a bug */ 44 45 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); 46 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " 47 "Digi96/8 PAD"); 48 MODULE_LICENSE("GPL"); 49 MODULE_SUPPORTED_DEVICE("{{RME,Digi96}," 50 "{RME,Digi96/8}," 51 "{RME,Digi96/8 PRO}," 52 "{RME,Digi96/8 PST}," 53 "{RME,Digi96/8 PAD}}"); 54 55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 57 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 58 59 module_param_array(index, int, NULL, 0444); 60 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); 61 module_param_array(id, charp, NULL, 0444); 62 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); 63 module_param_array(enable, bool, NULL, 0444); 64 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); 65 66 /* 67 * Defines for RME Digi96 series, from internal RME reference documents 68 * dated 12.01.00 69 */ 70 71 #define RME96_SPDIF_NCHANNELS 2 72 73 /* Playback and capture buffer size */ 74 #define RME96_BUFFER_SIZE 0x10000 75 76 /* IO area size */ 77 #define RME96_IO_SIZE 0x60000 78 79 /* IO area offsets */ 80 #define RME96_IO_PLAY_BUFFER 0x0 81 #define RME96_IO_REC_BUFFER 0x10000 82 #define RME96_IO_CONTROL_REGISTER 0x20000 83 #define RME96_IO_ADDITIONAL_REG 0x20004 84 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 85 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 86 #define RME96_IO_SET_PLAY_POS 0x40000 87 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 88 #define RME96_IO_SET_REC_POS 0x50000 89 #define RME96_IO_RESET_REC_POS 0x5FFFC 90 #define RME96_IO_GET_PLAY_POS 0x20000 91 #define RME96_IO_GET_REC_POS 0x30000 92 93 /* Write control register bits */ 94 #define RME96_WCR_START (1 << 0) 95 #define RME96_WCR_START_2 (1 << 1) 96 #define RME96_WCR_GAIN_0 (1 << 2) 97 #define RME96_WCR_GAIN_1 (1 << 3) 98 #define RME96_WCR_MODE24 (1 << 4) 99 #define RME96_WCR_MODE24_2 (1 << 5) 100 #define RME96_WCR_BM (1 << 6) 101 #define RME96_WCR_BM_2 (1 << 7) 102 #define RME96_WCR_ADAT (1 << 8) 103 #define RME96_WCR_FREQ_0 (1 << 9) 104 #define RME96_WCR_FREQ_1 (1 << 10) 105 #define RME96_WCR_DS (1 << 11) 106 #define RME96_WCR_PRO (1 << 12) 107 #define RME96_WCR_EMP (1 << 13) 108 #define RME96_WCR_SEL (1 << 14) 109 #define RME96_WCR_MASTER (1 << 15) 110 #define RME96_WCR_PD (1 << 16) 111 #define RME96_WCR_INP_0 (1 << 17) 112 #define RME96_WCR_INP_1 (1 << 18) 113 #define RME96_WCR_THRU_0 (1 << 19) 114 #define RME96_WCR_THRU_1 (1 << 20) 115 #define RME96_WCR_THRU_2 (1 << 21) 116 #define RME96_WCR_THRU_3 (1 << 22) 117 #define RME96_WCR_THRU_4 (1 << 23) 118 #define RME96_WCR_THRU_5 (1 << 24) 119 #define RME96_WCR_THRU_6 (1 << 25) 120 #define RME96_WCR_THRU_7 (1 << 26) 121 #define RME96_WCR_DOLBY (1 << 27) 122 #define RME96_WCR_MONITOR_0 (1 << 28) 123 #define RME96_WCR_MONITOR_1 (1 << 29) 124 #define RME96_WCR_ISEL (1 << 30) 125 #define RME96_WCR_IDIS (1 << 31) 126 127 #define RME96_WCR_BITPOS_GAIN_0 2 128 #define RME96_WCR_BITPOS_GAIN_1 3 129 #define RME96_WCR_BITPOS_FREQ_0 9 130 #define RME96_WCR_BITPOS_FREQ_1 10 131 #define RME96_WCR_BITPOS_INP_0 17 132 #define RME96_WCR_BITPOS_INP_1 18 133 #define RME96_WCR_BITPOS_MONITOR_0 28 134 #define RME96_WCR_BITPOS_MONITOR_1 29 135 136 /* Read control register bits */ 137 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 138 #define RME96_RCR_IRQ_2 (1 << 16) 139 #define RME96_RCR_T_OUT (1 << 17) 140 #define RME96_RCR_DEV_ID_0 (1 << 21) 141 #define RME96_RCR_DEV_ID_1 (1 << 22) 142 #define RME96_RCR_LOCK (1 << 23) 143 #define RME96_RCR_VERF (1 << 26) 144 #define RME96_RCR_F0 (1 << 27) 145 #define RME96_RCR_F1 (1 << 28) 146 #define RME96_RCR_F2 (1 << 29) 147 #define RME96_RCR_AUTOSYNC (1 << 30) 148 #define RME96_RCR_IRQ (1 << 31) 149 150 #define RME96_RCR_BITPOS_F0 27 151 #define RME96_RCR_BITPOS_F1 28 152 #define RME96_RCR_BITPOS_F2 29 153 154 /* Additional register bits */ 155 #define RME96_AR_WSEL (1 << 0) 156 #define RME96_AR_ANALOG (1 << 1) 157 #define RME96_AR_FREQPAD_0 (1 << 2) 158 #define RME96_AR_FREQPAD_1 (1 << 3) 159 #define RME96_AR_FREQPAD_2 (1 << 4) 160 #define RME96_AR_PD2 (1 << 5) 161 #define RME96_AR_DAC_EN (1 << 6) 162 #define RME96_AR_CLATCH (1 << 7) 163 #define RME96_AR_CCLK (1 << 8) 164 #define RME96_AR_CDATA (1 << 9) 165 166 #define RME96_AR_BITPOS_F0 2 167 #define RME96_AR_BITPOS_F1 3 168 #define RME96_AR_BITPOS_F2 4 169 170 /* Monitor tracks */ 171 #define RME96_MONITOR_TRACKS_1_2 0 172 #define RME96_MONITOR_TRACKS_3_4 1 173 #define RME96_MONITOR_TRACKS_5_6 2 174 #define RME96_MONITOR_TRACKS_7_8 3 175 176 /* Attenuation */ 177 #define RME96_ATTENUATION_0 0 178 #define RME96_ATTENUATION_6 1 179 #define RME96_ATTENUATION_12 2 180 #define RME96_ATTENUATION_18 3 181 182 /* Input types */ 183 #define RME96_INPUT_OPTICAL 0 184 #define RME96_INPUT_COAXIAL 1 185 #define RME96_INPUT_INTERNAL 2 186 #define RME96_INPUT_XLR 3 187 #define RME96_INPUT_ANALOG 4 188 189 /* Clock modes */ 190 #define RME96_CLOCKMODE_SLAVE 0 191 #define RME96_CLOCKMODE_MASTER 1 192 #define RME96_CLOCKMODE_WORDCLOCK 2 193 194 /* Block sizes in bytes */ 195 #define RME96_SMALL_BLOCK_SIZE 2048 196 #define RME96_LARGE_BLOCK_SIZE 8192 197 198 /* Volume control */ 199 #define RME96_AD1852_VOL_BITS 14 200 #define RME96_AD1855_VOL_BITS 10 201 202 /* Defines for snd_rme96_trigger */ 203 #define RME96_TB_START_PLAYBACK 1 204 #define RME96_TB_START_CAPTURE 2 205 #define RME96_TB_STOP_PLAYBACK 4 206 #define RME96_TB_STOP_CAPTURE 8 207 #define RME96_TB_RESET_PLAYPOS 16 208 #define RME96_TB_RESET_CAPTUREPOS 32 209 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 210 #define RME96_TB_CLEAR_CAPTURE_IRQ 128 211 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) 212 #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) 213 #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ 214 | RME96_RESUME_CAPTURE) 215 #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ 216 | RME96_TB_RESET_PLAYPOS) 217 #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ 218 | RME96_TB_RESET_CAPTUREPOS) 219 #define RME96_START_BOTH (RME96_START_PLAYBACK \ 220 | RME96_START_CAPTURE) 221 #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ 222 | RME96_TB_CLEAR_PLAYBACK_IRQ) 223 #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ 224 | RME96_TB_CLEAR_CAPTURE_IRQ) 225 #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ 226 | RME96_STOP_CAPTURE) 227 228 struct rme96 { 229 spinlock_t lock; 230 int irq; 231 unsigned long port; 232 void __iomem *iobase; 233 234 u32 wcreg; /* cached write control register value */ 235 u32 wcreg_spdif; /* S/PDIF setup */ 236 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 237 u32 rcreg; /* cached read control register value */ 238 u32 areg; /* cached additional register value */ 239 u16 vol[2]; /* cached volume of analog output */ 240 241 u8 rev; /* card revision number */ 242 243 #ifdef CONFIG_PM 244 u32 playback_pointer; 245 u32 capture_pointer; 246 void *playback_suspend_buffer; 247 void *capture_suspend_buffer; 248 #endif 249 250 struct snd_pcm_substream *playback_substream; 251 struct snd_pcm_substream *capture_substream; 252 253 int playback_frlog; /* log2 of framesize */ 254 int capture_frlog; 255 256 size_t playback_periodsize; /* in bytes, zero if not used */ 257 size_t capture_periodsize; /* in bytes, zero if not used */ 258 259 struct snd_card *card; 260 struct snd_pcm *spdif_pcm; 261 struct snd_pcm *adat_pcm; 262 struct pci_dev *pci; 263 struct snd_kcontrol *spdif_ctl; 264 }; 265 266 static DEFINE_PCI_DEVICE_TABLE(snd_rme96_ids) = { 267 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, 268 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, 269 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, 270 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, 271 { 0, } 272 }; 273 274 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 275 276 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) 277 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) 278 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 279 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ 280 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 281 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) 282 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ 283 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) 284 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) 285 286 static int 287 snd_rme96_playback_prepare(struct snd_pcm_substream *substream); 288 289 static int 290 snd_rme96_capture_prepare(struct snd_pcm_substream *substream); 291 292 static int 293 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 294 int cmd); 295 296 static int 297 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 298 int cmd); 299 300 static snd_pcm_uframes_t 301 snd_rme96_playback_pointer(struct snd_pcm_substream *substream); 302 303 static snd_pcm_uframes_t 304 snd_rme96_capture_pointer(struct snd_pcm_substream *substream); 305 306 static void snd_rme96_proc_init(struct rme96 *rme96); 307 308 static int 309 snd_rme96_create_switches(struct snd_card *card, 310 struct rme96 *rme96); 311 312 static int 313 snd_rme96_getinputtype(struct rme96 *rme96); 314 315 static inline unsigned int 316 snd_rme96_playback_ptr(struct rme96 *rme96) 317 { 318 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 319 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; 320 } 321 322 static inline unsigned int 323 snd_rme96_capture_ptr(struct rme96 *rme96) 324 { 325 return (readl(rme96->iobase + RME96_IO_GET_REC_POS) 326 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; 327 } 328 329 static int 330 snd_rme96_playback_silence(struct snd_pcm_substream *substream, 331 int channel, /* not used (interleaved data) */ 332 snd_pcm_uframes_t pos, 333 snd_pcm_uframes_t count) 334 { 335 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 336 count <<= rme96->playback_frlog; 337 pos <<= rme96->playback_frlog; 338 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 339 0, count); 340 return 0; 341 } 342 343 static int 344 snd_rme96_playback_copy(struct snd_pcm_substream *substream, 345 int channel, /* not used (interleaved data) */ 346 snd_pcm_uframes_t pos, 347 void __user *src, 348 snd_pcm_uframes_t count) 349 { 350 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 351 count <<= rme96->playback_frlog; 352 pos <<= rme96->playback_frlog; 353 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, 354 count); 355 return 0; 356 } 357 358 static int 359 snd_rme96_capture_copy(struct snd_pcm_substream *substream, 360 int channel, /* not used (interleaved data) */ 361 snd_pcm_uframes_t pos, 362 void __user *dst, 363 snd_pcm_uframes_t count) 364 { 365 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 366 count <<= rme96->capture_frlog; 367 pos <<= rme96->capture_frlog; 368 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, 369 count); 370 return 0; 371 } 372 373 /* 374 * Digital output capabilities (S/PDIF) 375 */ 376 static struct snd_pcm_hardware snd_rme96_playback_spdif_info = 377 { 378 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 379 SNDRV_PCM_INFO_MMAP_VALID | 380 SNDRV_PCM_INFO_SYNC_START | 381 SNDRV_PCM_INFO_RESUME | 382 SNDRV_PCM_INFO_INTERLEAVED | 383 SNDRV_PCM_INFO_PAUSE), 384 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 385 SNDRV_PCM_FMTBIT_S32_LE), 386 .rates = (SNDRV_PCM_RATE_32000 | 387 SNDRV_PCM_RATE_44100 | 388 SNDRV_PCM_RATE_48000 | 389 SNDRV_PCM_RATE_64000 | 390 SNDRV_PCM_RATE_88200 | 391 SNDRV_PCM_RATE_96000), 392 .rate_min = 32000, 393 .rate_max = 96000, 394 .channels_min = 2, 395 .channels_max = 2, 396 .buffer_bytes_max = RME96_BUFFER_SIZE, 397 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 398 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 399 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 400 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 401 .fifo_size = 0, 402 }; 403 404 /* 405 * Digital input capabilities (S/PDIF) 406 */ 407 static struct snd_pcm_hardware snd_rme96_capture_spdif_info = 408 { 409 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 410 SNDRV_PCM_INFO_MMAP_VALID | 411 SNDRV_PCM_INFO_SYNC_START | 412 SNDRV_PCM_INFO_RESUME | 413 SNDRV_PCM_INFO_INTERLEAVED | 414 SNDRV_PCM_INFO_PAUSE), 415 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 416 SNDRV_PCM_FMTBIT_S32_LE), 417 .rates = (SNDRV_PCM_RATE_32000 | 418 SNDRV_PCM_RATE_44100 | 419 SNDRV_PCM_RATE_48000 | 420 SNDRV_PCM_RATE_64000 | 421 SNDRV_PCM_RATE_88200 | 422 SNDRV_PCM_RATE_96000), 423 .rate_min = 32000, 424 .rate_max = 96000, 425 .channels_min = 2, 426 .channels_max = 2, 427 .buffer_bytes_max = RME96_BUFFER_SIZE, 428 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 429 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 430 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 431 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 432 .fifo_size = 0, 433 }; 434 435 /* 436 * Digital output capabilities (ADAT) 437 */ 438 static struct snd_pcm_hardware snd_rme96_playback_adat_info = 439 { 440 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 441 SNDRV_PCM_INFO_MMAP_VALID | 442 SNDRV_PCM_INFO_SYNC_START | 443 SNDRV_PCM_INFO_RESUME | 444 SNDRV_PCM_INFO_INTERLEAVED | 445 SNDRV_PCM_INFO_PAUSE), 446 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 447 SNDRV_PCM_FMTBIT_S32_LE), 448 .rates = (SNDRV_PCM_RATE_44100 | 449 SNDRV_PCM_RATE_48000), 450 .rate_min = 44100, 451 .rate_max = 48000, 452 .channels_min = 8, 453 .channels_max = 8, 454 .buffer_bytes_max = RME96_BUFFER_SIZE, 455 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 456 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 457 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 458 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 459 .fifo_size = 0, 460 }; 461 462 /* 463 * Digital input capabilities (ADAT) 464 */ 465 static struct snd_pcm_hardware snd_rme96_capture_adat_info = 466 { 467 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 468 SNDRV_PCM_INFO_MMAP_VALID | 469 SNDRV_PCM_INFO_SYNC_START | 470 SNDRV_PCM_INFO_RESUME | 471 SNDRV_PCM_INFO_INTERLEAVED | 472 SNDRV_PCM_INFO_PAUSE), 473 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 474 SNDRV_PCM_FMTBIT_S32_LE), 475 .rates = (SNDRV_PCM_RATE_44100 | 476 SNDRV_PCM_RATE_48000), 477 .rate_min = 44100, 478 .rate_max = 48000, 479 .channels_min = 8, 480 .channels_max = 8, 481 .buffer_bytes_max = RME96_BUFFER_SIZE, 482 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 483 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 484 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 485 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 486 .fifo_size = 0, 487 }; 488 489 /* 490 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface 491 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up 492 * on the falling edge of CCLK and be stable on the rising edge. The rising 493 * edge of CLATCH after the last data bit clocks in the whole data word. 494 * A fast processor could probably drive the SPI interface faster than the 495 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) 496 * limits the data rate to 500KHz and only causes a delay of 33 microsecs. 497 * 498 * NOTE: increased delay from 1 to 10, since there where problems setting 499 * the volume. 500 */ 501 static void 502 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) 503 { 504 int i; 505 506 for (i = 0; i < 16; i++) { 507 if (val & 0x8000) { 508 rme96->areg |= RME96_AR_CDATA; 509 } else { 510 rme96->areg &= ~RME96_AR_CDATA; 511 } 512 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); 513 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 514 udelay(10); 515 rme96->areg |= RME96_AR_CCLK; 516 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 517 udelay(10); 518 val <<= 1; 519 } 520 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); 521 rme96->areg |= RME96_AR_CLATCH; 522 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 523 udelay(10); 524 rme96->areg &= ~RME96_AR_CLATCH; 525 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 526 } 527 528 static void 529 snd_rme96_apply_dac_volume(struct rme96 *rme96) 530 { 531 if (RME96_DAC_IS_1852(rme96)) { 532 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); 533 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); 534 } else if (RME96_DAC_IS_1855(rme96)) { 535 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); 536 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); 537 } 538 } 539 540 static void 541 snd_rme96_reset_dac(struct rme96 *rme96) 542 { 543 writel(rme96->wcreg | RME96_WCR_PD, 544 rme96->iobase + RME96_IO_CONTROL_REGISTER); 545 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 546 } 547 548 static int 549 snd_rme96_getmontracks(struct rme96 *rme96) 550 { 551 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + 552 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); 553 } 554 555 static int 556 snd_rme96_setmontracks(struct rme96 *rme96, 557 int montracks) 558 { 559 if (montracks & 1) { 560 rme96->wcreg |= RME96_WCR_MONITOR_0; 561 } else { 562 rme96->wcreg &= ~RME96_WCR_MONITOR_0; 563 } 564 if (montracks & 2) { 565 rme96->wcreg |= RME96_WCR_MONITOR_1; 566 } else { 567 rme96->wcreg &= ~RME96_WCR_MONITOR_1; 568 } 569 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 570 return 0; 571 } 572 573 static int 574 snd_rme96_getattenuation(struct rme96 *rme96) 575 { 576 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + 577 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); 578 } 579 580 static int 581 snd_rme96_setattenuation(struct rme96 *rme96, 582 int attenuation) 583 { 584 switch (attenuation) { 585 case 0: 586 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & 587 ~RME96_WCR_GAIN_1; 588 break; 589 case 1: 590 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & 591 ~RME96_WCR_GAIN_1; 592 break; 593 case 2: 594 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | 595 RME96_WCR_GAIN_1; 596 break; 597 case 3: 598 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | 599 RME96_WCR_GAIN_1; 600 break; 601 default: 602 return -EINVAL; 603 } 604 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 605 return 0; 606 } 607 608 static int 609 snd_rme96_capture_getrate(struct rme96 *rme96, 610 int *is_adat) 611 { 612 int n, rate; 613 614 *is_adat = 0; 615 if (rme96->areg & RME96_AR_ANALOG) { 616 /* Analog input, overrides S/PDIF setting */ 617 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + 618 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); 619 switch (n) { 620 case 1: 621 rate = 32000; 622 break; 623 case 2: 624 rate = 44100; 625 break; 626 case 3: 627 rate = 48000; 628 break; 629 default: 630 return -1; 631 } 632 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; 633 } 634 635 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 636 if (rme96->rcreg & RME96_RCR_LOCK) { 637 /* ADAT rate */ 638 *is_adat = 1; 639 if (rme96->rcreg & RME96_RCR_T_OUT) { 640 return 48000; 641 } 642 return 44100; 643 } 644 645 if (rme96->rcreg & RME96_RCR_VERF) { 646 return -1; 647 } 648 649 /* S/PDIF rate */ 650 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + 651 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + 652 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); 653 654 switch (n) { 655 case 0: 656 if (rme96->rcreg & RME96_RCR_T_OUT) { 657 return 64000; 658 } 659 return -1; 660 case 3: return 96000; 661 case 4: return 88200; 662 case 5: return 48000; 663 case 6: return 44100; 664 case 7: return 32000; 665 default: 666 break; 667 } 668 return -1; 669 } 670 671 static int 672 snd_rme96_playback_getrate(struct rme96 *rme96) 673 { 674 int rate, dummy; 675 676 if (!(rme96->wcreg & RME96_WCR_MASTER) && 677 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 678 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 679 { 680 /* slave clock */ 681 return rate; 682 } 683 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + 684 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); 685 switch (rate) { 686 case 1: 687 rate = 32000; 688 break; 689 case 2: 690 rate = 44100; 691 break; 692 case 3: 693 rate = 48000; 694 break; 695 default: 696 return -1; 697 } 698 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; 699 } 700 701 static int 702 snd_rme96_playback_setrate(struct rme96 *rme96, 703 int rate) 704 { 705 int ds; 706 707 ds = rme96->wcreg & RME96_WCR_DS; 708 switch (rate) { 709 case 32000: 710 rme96->wcreg &= ~RME96_WCR_DS; 711 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 712 ~RME96_WCR_FREQ_1; 713 break; 714 case 44100: 715 rme96->wcreg &= ~RME96_WCR_DS; 716 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 717 ~RME96_WCR_FREQ_0; 718 break; 719 case 48000: 720 rme96->wcreg &= ~RME96_WCR_DS; 721 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 722 RME96_WCR_FREQ_1; 723 break; 724 case 64000: 725 rme96->wcreg |= RME96_WCR_DS; 726 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 727 ~RME96_WCR_FREQ_1; 728 break; 729 case 88200: 730 rme96->wcreg |= RME96_WCR_DS; 731 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 732 ~RME96_WCR_FREQ_0; 733 break; 734 case 96000: 735 rme96->wcreg |= RME96_WCR_DS; 736 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 737 RME96_WCR_FREQ_1; 738 break; 739 default: 740 return -EINVAL; 741 } 742 if ((!ds && rme96->wcreg & RME96_WCR_DS) || 743 (ds && !(rme96->wcreg & RME96_WCR_DS))) 744 { 745 /* change to/from double-speed: reset the DAC (if available) */ 746 snd_rme96_reset_dac(rme96); 747 } else { 748 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 749 } 750 return 0; 751 } 752 753 static int 754 snd_rme96_capture_analog_setrate(struct rme96 *rme96, 755 int rate) 756 { 757 switch (rate) { 758 case 32000: 759 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 760 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 761 break; 762 case 44100: 763 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 764 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 765 break; 766 case 48000: 767 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 768 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 769 break; 770 case 64000: 771 if (rme96->rev < 4) { 772 return -EINVAL; 773 } 774 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 775 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 776 break; 777 case 88200: 778 if (rme96->rev < 4) { 779 return -EINVAL; 780 } 781 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 782 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 783 break; 784 case 96000: 785 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 786 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 787 break; 788 default: 789 return -EINVAL; 790 } 791 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 792 return 0; 793 } 794 795 static int 796 snd_rme96_setclockmode(struct rme96 *rme96, 797 int mode) 798 { 799 switch (mode) { 800 case RME96_CLOCKMODE_SLAVE: 801 /* AutoSync */ 802 rme96->wcreg &= ~RME96_WCR_MASTER; 803 rme96->areg &= ~RME96_AR_WSEL; 804 break; 805 case RME96_CLOCKMODE_MASTER: 806 /* Internal */ 807 rme96->wcreg |= RME96_WCR_MASTER; 808 rme96->areg &= ~RME96_AR_WSEL; 809 break; 810 case RME96_CLOCKMODE_WORDCLOCK: 811 /* Word clock is a master mode */ 812 rme96->wcreg |= RME96_WCR_MASTER; 813 rme96->areg |= RME96_AR_WSEL; 814 break; 815 default: 816 return -EINVAL; 817 } 818 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 819 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 820 return 0; 821 } 822 823 static int 824 snd_rme96_getclockmode(struct rme96 *rme96) 825 { 826 if (rme96->areg & RME96_AR_WSEL) { 827 return RME96_CLOCKMODE_WORDCLOCK; 828 } 829 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : 830 RME96_CLOCKMODE_SLAVE; 831 } 832 833 static int 834 snd_rme96_setinputtype(struct rme96 *rme96, 835 int type) 836 { 837 int n; 838 839 switch (type) { 840 case RME96_INPUT_OPTICAL: 841 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & 842 ~RME96_WCR_INP_1; 843 break; 844 case RME96_INPUT_COAXIAL: 845 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & 846 ~RME96_WCR_INP_1; 847 break; 848 case RME96_INPUT_INTERNAL: 849 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | 850 RME96_WCR_INP_1; 851 break; 852 case RME96_INPUT_XLR: 853 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 854 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || 855 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 856 rme96->rev > 4)) 857 { 858 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ 859 return -EINVAL; 860 } 861 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | 862 RME96_WCR_INP_1; 863 break; 864 case RME96_INPUT_ANALOG: 865 if (!RME96_HAS_ANALOG_IN(rme96)) { 866 return -EINVAL; 867 } 868 rme96->areg |= RME96_AR_ANALOG; 869 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 870 if (rme96->rev < 4) { 871 /* 872 * Revision less than 004 does not support 64 and 873 * 88.2 kHz 874 */ 875 if (snd_rme96_capture_getrate(rme96, &n) == 88200) { 876 snd_rme96_capture_analog_setrate(rme96, 44100); 877 } 878 if (snd_rme96_capture_getrate(rme96, &n) == 64000) { 879 snd_rme96_capture_analog_setrate(rme96, 32000); 880 } 881 } 882 return 0; 883 default: 884 return -EINVAL; 885 } 886 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { 887 rme96->areg &= ~RME96_AR_ANALOG; 888 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 889 } 890 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 891 return 0; 892 } 893 894 static int 895 snd_rme96_getinputtype(struct rme96 *rme96) 896 { 897 if (rme96->areg & RME96_AR_ANALOG) { 898 return RME96_INPUT_ANALOG; 899 } 900 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + 901 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); 902 } 903 904 static void 905 snd_rme96_setframelog(struct rme96 *rme96, 906 int n_channels, 907 int is_playback) 908 { 909 int frlog; 910 911 if (n_channels == 2) { 912 frlog = 1; 913 } else { 914 /* assume 8 channels */ 915 frlog = 3; 916 } 917 if (is_playback) { 918 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; 919 rme96->playback_frlog = frlog; 920 } else { 921 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; 922 rme96->capture_frlog = frlog; 923 } 924 } 925 926 static int 927 snd_rme96_playback_setformat(struct rme96 *rme96, 928 int format) 929 { 930 switch (format) { 931 case SNDRV_PCM_FORMAT_S16_LE: 932 rme96->wcreg &= ~RME96_WCR_MODE24; 933 break; 934 case SNDRV_PCM_FORMAT_S32_LE: 935 rme96->wcreg |= RME96_WCR_MODE24; 936 break; 937 default: 938 return -EINVAL; 939 } 940 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 941 return 0; 942 } 943 944 static int 945 snd_rme96_capture_setformat(struct rme96 *rme96, 946 int format) 947 { 948 switch (format) { 949 case SNDRV_PCM_FORMAT_S16_LE: 950 rme96->wcreg &= ~RME96_WCR_MODE24_2; 951 break; 952 case SNDRV_PCM_FORMAT_S32_LE: 953 rme96->wcreg |= RME96_WCR_MODE24_2; 954 break; 955 default: 956 return -EINVAL; 957 } 958 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 959 return 0; 960 } 961 962 static void 963 snd_rme96_set_period_properties(struct rme96 *rme96, 964 size_t period_bytes) 965 { 966 switch (period_bytes) { 967 case RME96_LARGE_BLOCK_SIZE: 968 rme96->wcreg &= ~RME96_WCR_ISEL; 969 break; 970 case RME96_SMALL_BLOCK_SIZE: 971 rme96->wcreg |= RME96_WCR_ISEL; 972 break; 973 default: 974 snd_BUG(); 975 break; 976 } 977 rme96->wcreg &= ~RME96_WCR_IDIS; 978 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 979 } 980 981 static int 982 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, 983 struct snd_pcm_hw_params *params) 984 { 985 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 986 struct snd_pcm_runtime *runtime = substream->runtime; 987 int err, rate, dummy; 988 989 runtime->dma_area = (void __force *)(rme96->iobase + 990 RME96_IO_PLAY_BUFFER); 991 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; 992 runtime->dma_bytes = RME96_BUFFER_SIZE; 993 994 spin_lock_irq(&rme96->lock); 995 if (!(rme96->wcreg & RME96_WCR_MASTER) && 996 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 997 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 998 { 999 /* slave clock */ 1000 if ((int)params_rate(params) != rate) { 1001 spin_unlock_irq(&rme96->lock); 1002 return -EIO; 1003 } 1004 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) { 1005 spin_unlock_irq(&rme96->lock); 1006 return err; 1007 } 1008 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) { 1009 spin_unlock_irq(&rme96->lock); 1010 return err; 1011 } 1012 snd_rme96_setframelog(rme96, params_channels(params), 1); 1013 if (rme96->capture_periodsize != 0) { 1014 if (params_period_size(params) << rme96->playback_frlog != 1015 rme96->capture_periodsize) 1016 { 1017 spin_unlock_irq(&rme96->lock); 1018 return -EBUSY; 1019 } 1020 } 1021 rme96->playback_periodsize = 1022 params_period_size(params) << rme96->playback_frlog; 1023 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); 1024 /* S/PDIF setup */ 1025 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { 1026 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 1027 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1028 } 1029 spin_unlock_irq(&rme96->lock); 1030 1031 return 0; 1032 } 1033 1034 static int 1035 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, 1036 struct snd_pcm_hw_params *params) 1037 { 1038 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1039 struct snd_pcm_runtime *runtime = substream->runtime; 1040 int err, isadat, rate; 1041 1042 runtime->dma_area = (void __force *)(rme96->iobase + 1043 RME96_IO_REC_BUFFER); 1044 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; 1045 runtime->dma_bytes = RME96_BUFFER_SIZE; 1046 1047 spin_lock_irq(&rme96->lock); 1048 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) { 1049 spin_unlock_irq(&rme96->lock); 1050 return err; 1051 } 1052 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1053 if ((err = snd_rme96_capture_analog_setrate(rme96, 1054 params_rate(params))) < 0) 1055 { 1056 spin_unlock_irq(&rme96->lock); 1057 return err; 1058 } 1059 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1060 if ((int)params_rate(params) != rate) { 1061 spin_unlock_irq(&rme96->lock); 1062 return -EIO; 1063 } 1064 if ((isadat && runtime->hw.channels_min == 2) || 1065 (!isadat && runtime->hw.channels_min == 8)) 1066 { 1067 spin_unlock_irq(&rme96->lock); 1068 return -EIO; 1069 } 1070 } 1071 snd_rme96_setframelog(rme96, params_channels(params), 0); 1072 if (rme96->playback_periodsize != 0) { 1073 if (params_period_size(params) << rme96->capture_frlog != 1074 rme96->playback_periodsize) 1075 { 1076 spin_unlock_irq(&rme96->lock); 1077 return -EBUSY; 1078 } 1079 } 1080 rme96->capture_periodsize = 1081 params_period_size(params) << rme96->capture_frlog; 1082 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); 1083 spin_unlock_irq(&rme96->lock); 1084 1085 return 0; 1086 } 1087 1088 static void 1089 snd_rme96_trigger(struct rme96 *rme96, 1090 int op) 1091 { 1092 if (op & RME96_TB_RESET_PLAYPOS) 1093 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1094 if (op & RME96_TB_RESET_CAPTUREPOS) 1095 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1096 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { 1097 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1098 if (rme96->rcreg & RME96_RCR_IRQ) 1099 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1100 } 1101 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { 1102 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1103 if (rme96->rcreg & RME96_RCR_IRQ_2) 1104 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1105 } 1106 if (op & RME96_TB_START_PLAYBACK) 1107 rme96->wcreg |= RME96_WCR_START; 1108 if (op & RME96_TB_STOP_PLAYBACK) 1109 rme96->wcreg &= ~RME96_WCR_START; 1110 if (op & RME96_TB_START_CAPTURE) 1111 rme96->wcreg |= RME96_WCR_START_2; 1112 if (op & RME96_TB_STOP_CAPTURE) 1113 rme96->wcreg &= ~RME96_WCR_START_2; 1114 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1115 } 1116 1117 1118 1119 static irqreturn_t 1120 snd_rme96_interrupt(int irq, 1121 void *dev_id) 1122 { 1123 struct rme96 *rme96 = (struct rme96 *)dev_id; 1124 1125 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1126 /* fastpath out, to ease interrupt sharing */ 1127 if (!((rme96->rcreg & RME96_RCR_IRQ) || 1128 (rme96->rcreg & RME96_RCR_IRQ_2))) 1129 { 1130 return IRQ_NONE; 1131 } 1132 1133 if (rme96->rcreg & RME96_RCR_IRQ) { 1134 /* playback */ 1135 snd_pcm_period_elapsed(rme96->playback_substream); 1136 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1137 } 1138 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1139 /* capture */ 1140 snd_pcm_period_elapsed(rme96->capture_substream); 1141 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1142 } 1143 return IRQ_HANDLED; 1144 } 1145 1146 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; 1147 1148 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 1149 .count = ARRAY_SIZE(period_bytes), 1150 .list = period_bytes, 1151 .mask = 0 1152 }; 1153 1154 static void 1155 rme96_set_buffer_size_constraint(struct rme96 *rme96, 1156 struct snd_pcm_runtime *runtime) 1157 { 1158 unsigned int size; 1159 1160 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1161 RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); 1162 if ((size = rme96->playback_periodsize) != 0 || 1163 (size = rme96->capture_periodsize) != 0) 1164 snd_pcm_hw_constraint_minmax(runtime, 1165 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1166 size, size); 1167 else 1168 snd_pcm_hw_constraint_list(runtime, 0, 1169 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1170 &hw_constraints_period_bytes); 1171 } 1172 1173 static int 1174 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) 1175 { 1176 int rate, dummy; 1177 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1178 struct snd_pcm_runtime *runtime = substream->runtime; 1179 1180 snd_pcm_set_sync(substream); 1181 spin_lock_irq(&rme96->lock); 1182 if (rme96->playback_substream != NULL) { 1183 spin_unlock_irq(&rme96->lock); 1184 return -EBUSY; 1185 } 1186 rme96->wcreg &= ~RME96_WCR_ADAT; 1187 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1188 rme96->playback_substream = substream; 1189 spin_unlock_irq(&rme96->lock); 1190 1191 runtime->hw = snd_rme96_playback_spdif_info; 1192 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1193 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1194 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1195 { 1196 /* slave clock */ 1197 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1198 runtime->hw.rate_min = rate; 1199 runtime->hw.rate_max = rate; 1200 } 1201 rme96_set_buffer_size_constraint(rme96, runtime); 1202 1203 rme96->wcreg_spdif_stream = rme96->wcreg_spdif; 1204 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1205 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1206 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1207 return 0; 1208 } 1209 1210 static int 1211 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) 1212 { 1213 int isadat, rate; 1214 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1215 struct snd_pcm_runtime *runtime = substream->runtime; 1216 1217 snd_pcm_set_sync(substream); 1218 runtime->hw = snd_rme96_capture_spdif_info; 1219 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1220 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) 1221 { 1222 if (isadat) { 1223 return -EIO; 1224 } 1225 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1226 runtime->hw.rate_min = rate; 1227 runtime->hw.rate_max = rate; 1228 } 1229 1230 spin_lock_irq(&rme96->lock); 1231 if (rme96->capture_substream != NULL) { 1232 spin_unlock_irq(&rme96->lock); 1233 return -EBUSY; 1234 } 1235 rme96->capture_substream = substream; 1236 spin_unlock_irq(&rme96->lock); 1237 1238 rme96_set_buffer_size_constraint(rme96, runtime); 1239 return 0; 1240 } 1241 1242 static int 1243 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) 1244 { 1245 int rate, dummy; 1246 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1247 struct snd_pcm_runtime *runtime = substream->runtime; 1248 1249 snd_pcm_set_sync(substream); 1250 spin_lock_irq(&rme96->lock); 1251 if (rme96->playback_substream != NULL) { 1252 spin_unlock_irq(&rme96->lock); 1253 return -EBUSY; 1254 } 1255 rme96->wcreg |= RME96_WCR_ADAT; 1256 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1257 rme96->playback_substream = substream; 1258 spin_unlock_irq(&rme96->lock); 1259 1260 runtime->hw = snd_rme96_playback_adat_info; 1261 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1262 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1263 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1264 { 1265 /* slave clock */ 1266 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1267 runtime->hw.rate_min = rate; 1268 runtime->hw.rate_max = rate; 1269 } 1270 rme96_set_buffer_size_constraint(rme96, runtime); 1271 return 0; 1272 } 1273 1274 static int 1275 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) 1276 { 1277 int isadat, rate; 1278 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1279 struct snd_pcm_runtime *runtime = substream->runtime; 1280 1281 snd_pcm_set_sync(substream); 1282 runtime->hw = snd_rme96_capture_adat_info; 1283 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1284 /* makes no sense to use analog input. Note that analog 1285 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ 1286 return -EIO; 1287 } 1288 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1289 if (!isadat) { 1290 return -EIO; 1291 } 1292 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1293 runtime->hw.rate_min = rate; 1294 runtime->hw.rate_max = rate; 1295 } 1296 1297 spin_lock_irq(&rme96->lock); 1298 if (rme96->capture_substream != NULL) { 1299 spin_unlock_irq(&rme96->lock); 1300 return -EBUSY; 1301 } 1302 rme96->capture_substream = substream; 1303 spin_unlock_irq(&rme96->lock); 1304 1305 rme96_set_buffer_size_constraint(rme96, runtime); 1306 return 0; 1307 } 1308 1309 static int 1310 snd_rme96_playback_close(struct snd_pcm_substream *substream) 1311 { 1312 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1313 int spdif = 0; 1314 1315 spin_lock_irq(&rme96->lock); 1316 if (RME96_ISPLAYING(rme96)) { 1317 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1318 } 1319 rme96->playback_substream = NULL; 1320 rme96->playback_periodsize = 0; 1321 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; 1322 spin_unlock_irq(&rme96->lock); 1323 if (spdif) { 1324 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1325 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1326 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1327 } 1328 return 0; 1329 } 1330 1331 static int 1332 snd_rme96_capture_close(struct snd_pcm_substream *substream) 1333 { 1334 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1335 1336 spin_lock_irq(&rme96->lock); 1337 if (RME96_ISRECORDING(rme96)) { 1338 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1339 } 1340 rme96->capture_substream = NULL; 1341 rme96->capture_periodsize = 0; 1342 spin_unlock_irq(&rme96->lock); 1343 return 0; 1344 } 1345 1346 static int 1347 snd_rme96_playback_prepare(struct snd_pcm_substream *substream) 1348 { 1349 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1350 1351 spin_lock_irq(&rme96->lock); 1352 if (RME96_ISPLAYING(rme96)) { 1353 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1354 } 1355 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1356 spin_unlock_irq(&rme96->lock); 1357 return 0; 1358 } 1359 1360 static int 1361 snd_rme96_capture_prepare(struct snd_pcm_substream *substream) 1362 { 1363 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1364 1365 spin_lock_irq(&rme96->lock); 1366 if (RME96_ISRECORDING(rme96)) { 1367 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1368 } 1369 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1370 spin_unlock_irq(&rme96->lock); 1371 return 0; 1372 } 1373 1374 static int 1375 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 1376 int cmd) 1377 { 1378 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1379 struct snd_pcm_substream *s; 1380 bool sync; 1381 1382 snd_pcm_group_for_each_entry(s, substream) { 1383 if (snd_pcm_substream_chip(s) == rme96) 1384 snd_pcm_trigger_done(s, substream); 1385 } 1386 1387 sync = (rme96->playback_substream && rme96->capture_substream) && 1388 (rme96->playback_substream->group == 1389 rme96->capture_substream->group); 1390 1391 switch (cmd) { 1392 case SNDRV_PCM_TRIGGER_START: 1393 if (!RME96_ISPLAYING(rme96)) { 1394 if (substream != rme96->playback_substream) 1395 return -EBUSY; 1396 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1397 : RME96_START_PLAYBACK); 1398 } 1399 break; 1400 1401 case SNDRV_PCM_TRIGGER_SUSPEND: 1402 case SNDRV_PCM_TRIGGER_STOP: 1403 if (RME96_ISPLAYING(rme96)) { 1404 if (substream != rme96->playback_substream) 1405 return -EBUSY; 1406 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1407 : RME96_STOP_PLAYBACK); 1408 } 1409 break; 1410 1411 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1412 if (RME96_ISPLAYING(rme96)) 1413 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1414 : RME96_STOP_PLAYBACK); 1415 break; 1416 1417 case SNDRV_PCM_TRIGGER_RESUME: 1418 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1419 if (!RME96_ISPLAYING(rme96)) 1420 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1421 : RME96_RESUME_PLAYBACK); 1422 break; 1423 1424 default: 1425 return -EINVAL; 1426 } 1427 1428 return 0; 1429 } 1430 1431 static int 1432 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 1433 int cmd) 1434 { 1435 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1436 struct snd_pcm_substream *s; 1437 bool sync; 1438 1439 snd_pcm_group_for_each_entry(s, substream) { 1440 if (snd_pcm_substream_chip(s) == rme96) 1441 snd_pcm_trigger_done(s, substream); 1442 } 1443 1444 sync = (rme96->playback_substream && rme96->capture_substream) && 1445 (rme96->playback_substream->group == 1446 rme96->capture_substream->group); 1447 1448 switch (cmd) { 1449 case SNDRV_PCM_TRIGGER_START: 1450 if (!RME96_ISRECORDING(rme96)) { 1451 if (substream != rme96->capture_substream) 1452 return -EBUSY; 1453 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1454 : RME96_START_CAPTURE); 1455 } 1456 break; 1457 1458 case SNDRV_PCM_TRIGGER_SUSPEND: 1459 case SNDRV_PCM_TRIGGER_STOP: 1460 if (RME96_ISRECORDING(rme96)) { 1461 if (substream != rme96->capture_substream) 1462 return -EBUSY; 1463 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1464 : RME96_STOP_CAPTURE); 1465 } 1466 break; 1467 1468 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1469 if (RME96_ISRECORDING(rme96)) 1470 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1471 : RME96_STOP_CAPTURE); 1472 break; 1473 1474 case SNDRV_PCM_TRIGGER_RESUME: 1475 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1476 if (!RME96_ISRECORDING(rme96)) 1477 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1478 : RME96_RESUME_CAPTURE); 1479 break; 1480 1481 default: 1482 return -EINVAL; 1483 } 1484 1485 return 0; 1486 } 1487 1488 static snd_pcm_uframes_t 1489 snd_rme96_playback_pointer(struct snd_pcm_substream *substream) 1490 { 1491 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1492 return snd_rme96_playback_ptr(rme96); 1493 } 1494 1495 static snd_pcm_uframes_t 1496 snd_rme96_capture_pointer(struct snd_pcm_substream *substream) 1497 { 1498 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1499 return snd_rme96_capture_ptr(rme96); 1500 } 1501 1502 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = { 1503 .open = snd_rme96_playback_spdif_open, 1504 .close = snd_rme96_playback_close, 1505 .ioctl = snd_pcm_lib_ioctl, 1506 .hw_params = snd_rme96_playback_hw_params, 1507 .prepare = snd_rme96_playback_prepare, 1508 .trigger = snd_rme96_playback_trigger, 1509 .pointer = snd_rme96_playback_pointer, 1510 .copy = snd_rme96_playback_copy, 1511 .silence = snd_rme96_playback_silence, 1512 .mmap = snd_pcm_lib_mmap_iomem, 1513 }; 1514 1515 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = { 1516 .open = snd_rme96_capture_spdif_open, 1517 .close = snd_rme96_capture_close, 1518 .ioctl = snd_pcm_lib_ioctl, 1519 .hw_params = snd_rme96_capture_hw_params, 1520 .prepare = snd_rme96_capture_prepare, 1521 .trigger = snd_rme96_capture_trigger, 1522 .pointer = snd_rme96_capture_pointer, 1523 .copy = snd_rme96_capture_copy, 1524 .mmap = snd_pcm_lib_mmap_iomem, 1525 }; 1526 1527 static struct snd_pcm_ops snd_rme96_playback_adat_ops = { 1528 .open = snd_rme96_playback_adat_open, 1529 .close = snd_rme96_playback_close, 1530 .ioctl = snd_pcm_lib_ioctl, 1531 .hw_params = snd_rme96_playback_hw_params, 1532 .prepare = snd_rme96_playback_prepare, 1533 .trigger = snd_rme96_playback_trigger, 1534 .pointer = snd_rme96_playback_pointer, 1535 .copy = snd_rme96_playback_copy, 1536 .silence = snd_rme96_playback_silence, 1537 .mmap = snd_pcm_lib_mmap_iomem, 1538 }; 1539 1540 static struct snd_pcm_ops snd_rme96_capture_adat_ops = { 1541 .open = snd_rme96_capture_adat_open, 1542 .close = snd_rme96_capture_close, 1543 .ioctl = snd_pcm_lib_ioctl, 1544 .hw_params = snd_rme96_capture_hw_params, 1545 .prepare = snd_rme96_capture_prepare, 1546 .trigger = snd_rme96_capture_trigger, 1547 .pointer = snd_rme96_capture_pointer, 1548 .copy = snd_rme96_capture_copy, 1549 .mmap = snd_pcm_lib_mmap_iomem, 1550 }; 1551 1552 static void 1553 snd_rme96_free(void *private_data) 1554 { 1555 struct rme96 *rme96 = (struct rme96 *)private_data; 1556 1557 if (rme96 == NULL) { 1558 return; 1559 } 1560 if (rme96->irq >= 0) { 1561 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1562 rme96->areg &= ~RME96_AR_DAC_EN; 1563 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1564 free_irq(rme96->irq, (void *)rme96); 1565 rme96->irq = -1; 1566 } 1567 if (rme96->iobase) { 1568 iounmap(rme96->iobase); 1569 rme96->iobase = NULL; 1570 } 1571 if (rme96->port) { 1572 pci_release_regions(rme96->pci); 1573 rme96->port = 0; 1574 } 1575 #ifdef CONFIG_PM 1576 vfree(rme96->playback_suspend_buffer); 1577 vfree(rme96->capture_suspend_buffer); 1578 #endif 1579 pci_disable_device(rme96->pci); 1580 } 1581 1582 static void 1583 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) 1584 { 1585 struct rme96 *rme96 = pcm->private_data; 1586 rme96->spdif_pcm = NULL; 1587 } 1588 1589 static void 1590 snd_rme96_free_adat_pcm(struct snd_pcm *pcm) 1591 { 1592 struct rme96 *rme96 = pcm->private_data; 1593 rme96->adat_pcm = NULL; 1594 } 1595 1596 static int 1597 snd_rme96_create(struct rme96 *rme96) 1598 { 1599 struct pci_dev *pci = rme96->pci; 1600 int err; 1601 1602 rme96->irq = -1; 1603 spin_lock_init(&rme96->lock); 1604 1605 if ((err = pci_enable_device(pci)) < 0) 1606 return err; 1607 1608 if ((err = pci_request_regions(pci, "RME96")) < 0) 1609 return err; 1610 rme96->port = pci_resource_start(rme96->pci, 0); 1611 1612 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE); 1613 if (!rme96->iobase) { 1614 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1); 1615 return -ENOMEM; 1616 } 1617 1618 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED, 1619 KBUILD_MODNAME, rme96)) { 1620 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1621 return -EBUSY; 1622 } 1623 rme96->irq = pci->irq; 1624 1625 /* read the card's revision number */ 1626 pci_read_config_byte(pci, 8, &rme96->rev); 1627 1628 /* set up ALSA pcm device for S/PDIF */ 1629 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1630 1, 1, &rme96->spdif_pcm)) < 0) 1631 { 1632 return err; 1633 } 1634 rme96->spdif_pcm->private_data = rme96; 1635 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; 1636 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); 1637 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); 1638 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); 1639 1640 rme96->spdif_pcm->info_flags = 0; 1641 1642 /* set up ALSA pcm device for ADAT */ 1643 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { 1644 /* ADAT is not available on the base model */ 1645 rme96->adat_pcm = NULL; 1646 } else { 1647 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1648 1, 1, &rme96->adat_pcm)) < 0) 1649 { 1650 return err; 1651 } 1652 rme96->adat_pcm->private_data = rme96; 1653 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; 1654 strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); 1655 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); 1656 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); 1657 1658 rme96->adat_pcm->info_flags = 0; 1659 } 1660 1661 rme96->playback_periodsize = 0; 1662 rme96->capture_periodsize = 0; 1663 1664 /* make sure playback/capture is stopped, if by some reason active */ 1665 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1666 1667 /* set default values in registers */ 1668 rme96->wcreg = 1669 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ 1670 RME96_WCR_SEL | /* normal playback */ 1671 RME96_WCR_MASTER | /* set to master clock mode */ 1672 RME96_WCR_INP_0; /* set coaxial input */ 1673 1674 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ 1675 1676 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1677 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1678 1679 /* reset the ADC */ 1680 writel(rme96->areg | RME96_AR_PD2, 1681 rme96->iobase + RME96_IO_ADDITIONAL_REG); 1682 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1683 1684 /* reset and enable the DAC (order is important). */ 1685 snd_rme96_reset_dac(rme96); 1686 rme96->areg |= RME96_AR_DAC_EN; 1687 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1688 1689 /* reset playback and record buffer pointers */ 1690 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1691 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1692 1693 /* reset volume */ 1694 rme96->vol[0] = rme96->vol[1] = 0; 1695 if (RME96_HAS_ANALOG_OUT(rme96)) { 1696 snd_rme96_apply_dac_volume(rme96); 1697 } 1698 1699 /* init switch interface */ 1700 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) { 1701 return err; 1702 } 1703 1704 /* init proc interface */ 1705 snd_rme96_proc_init(rme96); 1706 1707 return 0; 1708 } 1709 1710 /* 1711 * proc interface 1712 */ 1713 1714 static void 1715 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1716 { 1717 int n; 1718 struct rme96 *rme96 = entry->private_data; 1719 1720 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1721 1722 snd_iprintf(buffer, rme96->card->longname); 1723 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); 1724 1725 snd_iprintf(buffer, "\nGeneral settings\n"); 1726 if (rme96->wcreg & RME96_WCR_IDIS) { 1727 snd_iprintf(buffer, " period size: N/A (interrupts " 1728 "disabled)\n"); 1729 } else if (rme96->wcreg & RME96_WCR_ISEL) { 1730 snd_iprintf(buffer, " period size: 2048 bytes\n"); 1731 } else { 1732 snd_iprintf(buffer, " period size: 8192 bytes\n"); 1733 } 1734 snd_iprintf(buffer, "\nInput settings\n"); 1735 switch (snd_rme96_getinputtype(rme96)) { 1736 case RME96_INPUT_OPTICAL: 1737 snd_iprintf(buffer, " input: optical"); 1738 break; 1739 case RME96_INPUT_COAXIAL: 1740 snd_iprintf(buffer, " input: coaxial"); 1741 break; 1742 case RME96_INPUT_INTERNAL: 1743 snd_iprintf(buffer, " input: internal"); 1744 break; 1745 case RME96_INPUT_XLR: 1746 snd_iprintf(buffer, " input: XLR"); 1747 break; 1748 case RME96_INPUT_ANALOG: 1749 snd_iprintf(buffer, " input: analog"); 1750 break; 1751 } 1752 if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1753 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1754 } else { 1755 if (n) { 1756 snd_iprintf(buffer, " (8 channels)\n"); 1757 } else { 1758 snd_iprintf(buffer, " (2 channels)\n"); 1759 } 1760 snd_iprintf(buffer, " sample rate: %d Hz\n", 1761 snd_rme96_capture_getrate(rme96, &n)); 1762 } 1763 if (rme96->wcreg & RME96_WCR_MODE24_2) { 1764 snd_iprintf(buffer, " sample format: 24 bit\n"); 1765 } else { 1766 snd_iprintf(buffer, " sample format: 16 bit\n"); 1767 } 1768 1769 snd_iprintf(buffer, "\nOutput settings\n"); 1770 if (rme96->wcreg & RME96_WCR_SEL) { 1771 snd_iprintf(buffer, " output signal: normal playback\n"); 1772 } else { 1773 snd_iprintf(buffer, " output signal: same as input\n"); 1774 } 1775 snd_iprintf(buffer, " sample rate: %d Hz\n", 1776 snd_rme96_playback_getrate(rme96)); 1777 if (rme96->wcreg & RME96_WCR_MODE24) { 1778 snd_iprintf(buffer, " sample format: 24 bit\n"); 1779 } else { 1780 snd_iprintf(buffer, " sample format: 16 bit\n"); 1781 } 1782 if (rme96->areg & RME96_AR_WSEL) { 1783 snd_iprintf(buffer, " sample clock source: word clock\n"); 1784 } else if (rme96->wcreg & RME96_WCR_MASTER) { 1785 snd_iprintf(buffer, " sample clock source: internal\n"); 1786 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1787 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); 1788 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1789 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); 1790 } else { 1791 snd_iprintf(buffer, " sample clock source: autosync\n"); 1792 } 1793 if (rme96->wcreg & RME96_WCR_PRO) { 1794 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1795 } else { 1796 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1797 } 1798 if (rme96->wcreg & RME96_WCR_EMP) { 1799 snd_iprintf(buffer, " emphasis: on\n"); 1800 } else { 1801 snd_iprintf(buffer, " emphasis: off\n"); 1802 } 1803 if (rme96->wcreg & RME96_WCR_DOLBY) { 1804 snd_iprintf(buffer, " non-audio (dolby): on\n"); 1805 } else { 1806 snd_iprintf(buffer, " non-audio (dolby): off\n"); 1807 } 1808 if (RME96_HAS_ANALOG_IN(rme96)) { 1809 snd_iprintf(buffer, "\nAnalog output settings\n"); 1810 switch (snd_rme96_getmontracks(rme96)) { 1811 case RME96_MONITOR_TRACKS_1_2: 1812 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); 1813 break; 1814 case RME96_MONITOR_TRACKS_3_4: 1815 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); 1816 break; 1817 case RME96_MONITOR_TRACKS_5_6: 1818 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); 1819 break; 1820 case RME96_MONITOR_TRACKS_7_8: 1821 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); 1822 break; 1823 } 1824 switch (snd_rme96_getattenuation(rme96)) { 1825 case RME96_ATTENUATION_0: 1826 snd_iprintf(buffer, " attenuation: 0 dB\n"); 1827 break; 1828 case RME96_ATTENUATION_6: 1829 snd_iprintf(buffer, " attenuation: -6 dB\n"); 1830 break; 1831 case RME96_ATTENUATION_12: 1832 snd_iprintf(buffer, " attenuation: -12 dB\n"); 1833 break; 1834 case RME96_ATTENUATION_18: 1835 snd_iprintf(buffer, " attenuation: -18 dB\n"); 1836 break; 1837 } 1838 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); 1839 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); 1840 } 1841 } 1842 1843 static void snd_rme96_proc_init(struct rme96 *rme96) 1844 { 1845 struct snd_info_entry *entry; 1846 1847 if (! snd_card_proc_new(rme96->card, "rme96", &entry)) 1848 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read); 1849 } 1850 1851 /* 1852 * control interface 1853 */ 1854 1855 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info 1856 1857 static int 1858 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1859 { 1860 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1861 1862 spin_lock_irq(&rme96->lock); 1863 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; 1864 spin_unlock_irq(&rme96->lock); 1865 return 0; 1866 } 1867 static int 1868 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1869 { 1870 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1871 unsigned int val; 1872 int change; 1873 1874 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; 1875 spin_lock_irq(&rme96->lock); 1876 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; 1877 change = val != rme96->wcreg; 1878 rme96->wcreg = val; 1879 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1880 spin_unlock_irq(&rme96->lock); 1881 return change; 1882 } 1883 1884 static int 1885 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1886 { 1887 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" }; 1888 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1889 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] }; 1890 1891 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 1892 uinfo->count = 1; 1893 switch (rme96->pci->device) { 1894 case PCI_DEVICE_ID_RME_DIGI96: 1895 case PCI_DEVICE_ID_RME_DIGI96_8: 1896 uinfo->value.enumerated.items = 3; 1897 break; 1898 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1899 uinfo->value.enumerated.items = 4; 1900 break; 1901 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1902 if (rme96->rev > 4) { 1903 /* PST */ 1904 uinfo->value.enumerated.items = 4; 1905 texts[3] = _texts[4]; /* Analog instead of XLR */ 1906 } else { 1907 /* PAD */ 1908 uinfo->value.enumerated.items = 5; 1909 } 1910 break; 1911 default: 1912 snd_BUG(); 1913 break; 1914 } 1915 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) { 1916 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1; 1917 } 1918 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 1919 return 0; 1920 } 1921 static int 1922 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1923 { 1924 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1925 unsigned int items = 3; 1926 1927 spin_lock_irq(&rme96->lock); 1928 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); 1929 1930 switch (rme96->pci->device) { 1931 case PCI_DEVICE_ID_RME_DIGI96: 1932 case PCI_DEVICE_ID_RME_DIGI96_8: 1933 items = 3; 1934 break; 1935 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1936 items = 4; 1937 break; 1938 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1939 if (rme96->rev > 4) { 1940 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ 1941 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { 1942 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; 1943 } 1944 items = 4; 1945 } else { 1946 items = 5; 1947 } 1948 break; 1949 default: 1950 snd_BUG(); 1951 break; 1952 } 1953 if (ucontrol->value.enumerated.item[0] >= items) { 1954 ucontrol->value.enumerated.item[0] = items - 1; 1955 } 1956 1957 spin_unlock_irq(&rme96->lock); 1958 return 0; 1959 } 1960 static int 1961 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1962 { 1963 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1964 unsigned int val; 1965 int change, items = 3; 1966 1967 switch (rme96->pci->device) { 1968 case PCI_DEVICE_ID_RME_DIGI96: 1969 case PCI_DEVICE_ID_RME_DIGI96_8: 1970 items = 3; 1971 break; 1972 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1973 items = 4; 1974 break; 1975 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1976 if (rme96->rev > 4) { 1977 items = 4; 1978 } else { 1979 items = 5; 1980 } 1981 break; 1982 default: 1983 snd_BUG(); 1984 break; 1985 } 1986 val = ucontrol->value.enumerated.item[0] % items; 1987 1988 /* special case for PST */ 1989 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { 1990 if (val == RME96_INPUT_XLR) { 1991 val = RME96_INPUT_ANALOG; 1992 } 1993 } 1994 1995 spin_lock_irq(&rme96->lock); 1996 change = (int)val != snd_rme96_getinputtype(rme96); 1997 snd_rme96_setinputtype(rme96, val); 1998 spin_unlock_irq(&rme96->lock); 1999 return change; 2000 } 2001 2002 static int 2003 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2004 { 2005 static char *texts[3] = { "AutoSync", "Internal", "Word" }; 2006 2007 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2008 uinfo->count = 1; 2009 uinfo->value.enumerated.items = 3; 2010 if (uinfo->value.enumerated.item > 2) { 2011 uinfo->value.enumerated.item = 2; 2012 } 2013 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2014 return 0; 2015 } 2016 static int 2017 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2018 { 2019 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2020 2021 spin_lock_irq(&rme96->lock); 2022 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); 2023 spin_unlock_irq(&rme96->lock); 2024 return 0; 2025 } 2026 static int 2027 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2028 { 2029 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2030 unsigned int val; 2031 int change; 2032 2033 val = ucontrol->value.enumerated.item[0] % 3; 2034 spin_lock_irq(&rme96->lock); 2035 change = (int)val != snd_rme96_getclockmode(rme96); 2036 snd_rme96_setclockmode(rme96, val); 2037 spin_unlock_irq(&rme96->lock); 2038 return change; 2039 } 2040 2041 static int 2042 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2043 { 2044 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" }; 2045 2046 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2047 uinfo->count = 1; 2048 uinfo->value.enumerated.items = 4; 2049 if (uinfo->value.enumerated.item > 3) { 2050 uinfo->value.enumerated.item = 3; 2051 } 2052 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2053 return 0; 2054 } 2055 static int 2056 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2057 { 2058 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2059 2060 spin_lock_irq(&rme96->lock); 2061 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); 2062 spin_unlock_irq(&rme96->lock); 2063 return 0; 2064 } 2065 static int 2066 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2067 { 2068 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2069 unsigned int val; 2070 int change; 2071 2072 val = ucontrol->value.enumerated.item[0] % 4; 2073 spin_lock_irq(&rme96->lock); 2074 2075 change = (int)val != snd_rme96_getattenuation(rme96); 2076 snd_rme96_setattenuation(rme96, val); 2077 spin_unlock_irq(&rme96->lock); 2078 return change; 2079 } 2080 2081 static int 2082 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2083 { 2084 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" }; 2085 2086 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; 2087 uinfo->count = 1; 2088 uinfo->value.enumerated.items = 4; 2089 if (uinfo->value.enumerated.item > 3) { 2090 uinfo->value.enumerated.item = 3; 2091 } 2092 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]); 2093 return 0; 2094 } 2095 static int 2096 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2097 { 2098 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2099 2100 spin_lock_irq(&rme96->lock); 2101 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); 2102 spin_unlock_irq(&rme96->lock); 2103 return 0; 2104 } 2105 static int 2106 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2107 { 2108 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2109 unsigned int val; 2110 int change; 2111 2112 val = ucontrol->value.enumerated.item[0] % 4; 2113 spin_lock_irq(&rme96->lock); 2114 change = (int)val != snd_rme96_getmontracks(rme96); 2115 snd_rme96_setmontracks(rme96, val); 2116 spin_unlock_irq(&rme96->lock); 2117 return change; 2118 } 2119 2120 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) 2121 { 2122 u32 val = 0; 2123 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; 2124 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; 2125 if (val & RME96_WCR_PRO) 2126 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2127 else 2128 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2129 return val; 2130 } 2131 2132 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 2133 { 2134 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | 2135 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); 2136 if (val & RME96_WCR_PRO) 2137 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 2138 else 2139 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 2140 } 2141 2142 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2143 { 2144 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2145 uinfo->count = 1; 2146 return 0; 2147 } 2148 2149 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2150 { 2151 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2152 2153 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); 2154 return 0; 2155 } 2156 2157 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2158 { 2159 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2160 int change; 2161 u32 val; 2162 2163 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2164 spin_lock_irq(&rme96->lock); 2165 change = val != rme96->wcreg_spdif; 2166 rme96->wcreg_spdif = val; 2167 spin_unlock_irq(&rme96->lock); 2168 return change; 2169 } 2170 2171 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2172 { 2173 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2174 uinfo->count = 1; 2175 return 0; 2176 } 2177 2178 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2179 { 2180 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2181 2182 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); 2183 return 0; 2184 } 2185 2186 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2187 { 2188 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2189 int change; 2190 u32 val; 2191 2192 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2193 spin_lock_irq(&rme96->lock); 2194 change = val != rme96->wcreg_spdif_stream; 2195 rme96->wcreg_spdif_stream = val; 2196 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 2197 rme96->wcreg |= val; 2198 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 2199 spin_unlock_irq(&rme96->lock); 2200 return change; 2201 } 2202 2203 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2204 { 2205 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2206 uinfo->count = 1; 2207 return 0; 2208 } 2209 2210 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2211 { 2212 ucontrol->value.iec958.status[0] = kcontrol->private_value; 2213 return 0; 2214 } 2215 2216 static int 2217 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2218 { 2219 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2220 2221 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2222 uinfo->count = 2; 2223 uinfo->value.integer.min = 0; 2224 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); 2225 return 0; 2226 } 2227 2228 static int 2229 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2230 { 2231 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2232 2233 spin_lock_irq(&rme96->lock); 2234 u->value.integer.value[0] = rme96->vol[0]; 2235 u->value.integer.value[1] = rme96->vol[1]; 2236 spin_unlock_irq(&rme96->lock); 2237 2238 return 0; 2239 } 2240 2241 static int 2242 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2243 { 2244 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2245 int change = 0; 2246 unsigned int vol, maxvol; 2247 2248 2249 if (!RME96_HAS_ANALOG_OUT(rme96)) 2250 return -EINVAL; 2251 maxvol = RME96_185X_MAX_OUT(rme96); 2252 spin_lock_irq(&rme96->lock); 2253 vol = u->value.integer.value[0]; 2254 if (vol != rme96->vol[0] && vol <= maxvol) { 2255 rme96->vol[0] = vol; 2256 change = 1; 2257 } 2258 vol = u->value.integer.value[1]; 2259 if (vol != rme96->vol[1] && vol <= maxvol) { 2260 rme96->vol[1] = vol; 2261 change = 1; 2262 } 2263 if (change) 2264 snd_rme96_apply_dac_volume(rme96); 2265 spin_unlock_irq(&rme96->lock); 2266 2267 return change; 2268 } 2269 2270 static struct snd_kcontrol_new snd_rme96_controls[] = { 2271 { 2272 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2273 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2274 .info = snd_rme96_control_spdif_info, 2275 .get = snd_rme96_control_spdif_get, 2276 .put = snd_rme96_control_spdif_put 2277 }, 2278 { 2279 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2280 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2281 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2282 .info = snd_rme96_control_spdif_stream_info, 2283 .get = snd_rme96_control_spdif_stream_get, 2284 .put = snd_rme96_control_spdif_stream_put 2285 }, 2286 { 2287 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2288 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2289 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2290 .info = snd_rme96_control_spdif_mask_info, 2291 .get = snd_rme96_control_spdif_mask_get, 2292 .private_value = IEC958_AES0_NONAUDIO | 2293 IEC958_AES0_PROFESSIONAL | 2294 IEC958_AES0_CON_EMPHASIS 2295 }, 2296 { 2297 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2298 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2299 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2300 .info = snd_rme96_control_spdif_mask_info, 2301 .get = snd_rme96_control_spdif_mask_get, 2302 .private_value = IEC958_AES0_NONAUDIO | 2303 IEC958_AES0_PROFESSIONAL | 2304 IEC958_AES0_PRO_EMPHASIS 2305 }, 2306 { 2307 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2308 .name = "Input Connector", 2309 .info = snd_rme96_info_inputtype_control, 2310 .get = snd_rme96_get_inputtype_control, 2311 .put = snd_rme96_put_inputtype_control 2312 }, 2313 { 2314 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2315 .name = "Loopback Input", 2316 .info = snd_rme96_info_loopback_control, 2317 .get = snd_rme96_get_loopback_control, 2318 .put = snd_rme96_put_loopback_control 2319 }, 2320 { 2321 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2322 .name = "Sample Clock Source", 2323 .info = snd_rme96_info_clockmode_control, 2324 .get = snd_rme96_get_clockmode_control, 2325 .put = snd_rme96_put_clockmode_control 2326 }, 2327 { 2328 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2329 .name = "Monitor Tracks", 2330 .info = snd_rme96_info_montracks_control, 2331 .get = snd_rme96_get_montracks_control, 2332 .put = snd_rme96_put_montracks_control 2333 }, 2334 { 2335 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2336 .name = "Attenuation", 2337 .info = snd_rme96_info_attenuation_control, 2338 .get = snd_rme96_get_attenuation_control, 2339 .put = snd_rme96_put_attenuation_control 2340 }, 2341 { 2342 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2343 .name = "DAC Playback Volume", 2344 .info = snd_rme96_dac_volume_info, 2345 .get = snd_rme96_dac_volume_get, 2346 .put = snd_rme96_dac_volume_put 2347 } 2348 }; 2349 2350 static int 2351 snd_rme96_create_switches(struct snd_card *card, 2352 struct rme96 *rme96) 2353 { 2354 int idx, err; 2355 struct snd_kcontrol *kctl; 2356 2357 for (idx = 0; idx < 7; idx++) { 2358 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2359 return err; 2360 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 2361 rme96->spdif_ctl = kctl; 2362 } 2363 2364 if (RME96_HAS_ANALOG_OUT(rme96)) { 2365 for (idx = 7; idx < 10; idx++) 2366 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2367 return err; 2368 } 2369 2370 return 0; 2371 } 2372 2373 /* 2374 * Card initialisation 2375 */ 2376 2377 #ifdef CONFIG_PM 2378 2379 static int 2380 snd_rme96_suspend(struct pci_dev *pci, 2381 pm_message_t state) 2382 { 2383 struct snd_card *card = pci_get_drvdata(pci); 2384 struct rme96 *rme96 = card->private_data; 2385 2386 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2387 snd_pcm_suspend(rme96->playback_substream); 2388 snd_pcm_suspend(rme96->capture_substream); 2389 2390 /* save capture & playback pointers */ 2391 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 2392 & RME96_RCR_AUDIO_ADDR_MASK; 2393 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS) 2394 & RME96_RCR_AUDIO_ADDR_MASK; 2395 2396 /* save playback and capture buffers */ 2397 memcpy_fromio(rme96->playback_suspend_buffer, 2398 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); 2399 memcpy_fromio(rme96->capture_suspend_buffer, 2400 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); 2401 2402 /* disable the DAC */ 2403 rme96->areg &= ~RME96_AR_DAC_EN; 2404 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2405 2406 pci_disable_device(pci); 2407 pci_save_state(pci); 2408 2409 return 0; 2410 } 2411 2412 static int 2413 snd_rme96_resume(struct pci_dev *pci) 2414 { 2415 struct snd_card *card = pci_get_drvdata(pci); 2416 struct rme96 *rme96 = card->private_data; 2417 2418 pci_restore_state(pci); 2419 if (pci_enable_device(pci) < 0) { 2420 printk(KERN_ERR "rme96: pci_enable_device failed, disabling device\n"); 2421 snd_card_disconnect(card); 2422 return -EIO; 2423 } 2424 2425 /* reset playback and record buffer pointers */ 2426 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS 2427 + rme96->playback_pointer); 2428 writel(0, rme96->iobase + RME96_IO_SET_REC_POS 2429 + rme96->capture_pointer); 2430 2431 /* restore playback and capture buffers */ 2432 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, 2433 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); 2434 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, 2435 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); 2436 2437 /* reset the ADC */ 2438 writel(rme96->areg | RME96_AR_PD2, 2439 rme96->iobase + RME96_IO_ADDITIONAL_REG); 2440 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2441 2442 /* reset and enable DAC, restore analog volume */ 2443 snd_rme96_reset_dac(rme96); 2444 rme96->areg |= RME96_AR_DAC_EN; 2445 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2446 if (RME96_HAS_ANALOG_OUT(rme96)) { 2447 usleep_range(3000, 10000); 2448 snd_rme96_apply_dac_volume(rme96); 2449 } 2450 2451 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2452 2453 return 0; 2454 } 2455 2456 #endif 2457 2458 static void snd_rme96_card_free(struct snd_card *card) 2459 { 2460 snd_rme96_free(card->private_data); 2461 } 2462 2463 static int 2464 snd_rme96_probe(struct pci_dev *pci, 2465 const struct pci_device_id *pci_id) 2466 { 2467 static int dev; 2468 struct rme96 *rme96; 2469 struct snd_card *card; 2470 int err; 2471 u8 val; 2472 2473 if (dev >= SNDRV_CARDS) { 2474 return -ENODEV; 2475 } 2476 if (!enable[dev]) { 2477 dev++; 2478 return -ENOENT; 2479 } 2480 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 2481 sizeof(struct rme96), &card); 2482 if (err < 0) 2483 return err; 2484 card->private_free = snd_rme96_card_free; 2485 rme96 = card->private_data; 2486 rme96->card = card; 2487 rme96->pci = pci; 2488 snd_card_set_dev(card, &pci->dev); 2489 if ((err = snd_rme96_create(rme96)) < 0) { 2490 snd_card_free(card); 2491 return err; 2492 } 2493 2494 #ifdef CONFIG_PM 2495 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2496 if (!rme96->playback_suspend_buffer) { 2497 snd_printk(KERN_ERR 2498 "Failed to allocate playback suspend buffer!\n"); 2499 snd_card_free(card); 2500 return -ENOMEM; 2501 } 2502 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2503 if (!rme96->capture_suspend_buffer) { 2504 snd_printk(KERN_ERR 2505 "Failed to allocate capture suspend buffer!\n"); 2506 snd_card_free(card); 2507 return -ENOMEM; 2508 } 2509 #endif 2510 2511 strcpy(card->driver, "Digi96"); 2512 switch (rme96->pci->device) { 2513 case PCI_DEVICE_ID_RME_DIGI96: 2514 strcpy(card->shortname, "RME Digi96"); 2515 break; 2516 case PCI_DEVICE_ID_RME_DIGI96_8: 2517 strcpy(card->shortname, "RME Digi96/8"); 2518 break; 2519 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 2520 strcpy(card->shortname, "RME Digi96/8 PRO"); 2521 break; 2522 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 2523 pci_read_config_byte(rme96->pci, 8, &val); 2524 if (val < 5) { 2525 strcpy(card->shortname, "RME Digi96/8 PAD"); 2526 } else { 2527 strcpy(card->shortname, "RME Digi96/8 PST"); 2528 } 2529 break; 2530 } 2531 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, 2532 rme96->port, rme96->irq); 2533 2534 if ((err = snd_card_register(card)) < 0) { 2535 snd_card_free(card); 2536 return err; 2537 } 2538 pci_set_drvdata(pci, card); 2539 dev++; 2540 return 0; 2541 } 2542 2543 static void snd_rme96_remove(struct pci_dev *pci) 2544 { 2545 snd_card_free(pci_get_drvdata(pci)); 2546 } 2547 2548 static struct pci_driver rme96_driver = { 2549 .name = KBUILD_MODNAME, 2550 .id_table = snd_rme96_ids, 2551 .probe = snd_rme96_probe, 2552 .remove = snd_rme96_remove, 2553 #ifdef CONFIG_PM 2554 .suspend = snd_rme96_suspend, 2555 .resume = snd_rme96_resume, 2556 #endif 2557 }; 2558 2559 module_pci_driver(rme96_driver); 2560