1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio 4 * interfaces 5 * 6 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> 7 * 8 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control 9 * code. 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/pci.h> 16 #include <linux/module.h> 17 #include <linux/vmalloc.h> 18 #include <linux/io.h> 19 20 #include <sound/core.h> 21 #include <sound/info.h> 22 #include <sound/control.h> 23 #include <sound/pcm.h> 24 #include <sound/pcm_params.h> 25 #include <sound/asoundef.h> 26 #include <sound/initval.h> 27 28 /* note, two last pcis should be equal, it is not a bug */ 29 30 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); 31 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " 32 "Digi96/8 PAD"); 33 MODULE_LICENSE("GPL"); 34 35 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 36 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 37 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 38 39 module_param_array(index, int, NULL, 0444); 40 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); 41 module_param_array(id, charp, NULL, 0444); 42 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); 43 module_param_array(enable, bool, NULL, 0444); 44 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); 45 46 /* 47 * Defines for RME Digi96 series, from internal RME reference documents 48 * dated 12.01.00 49 */ 50 51 #define RME96_SPDIF_NCHANNELS 2 52 53 /* Playback and capture buffer size */ 54 #define RME96_BUFFER_SIZE 0x10000 55 56 /* IO area size */ 57 #define RME96_IO_SIZE 0x60000 58 59 /* IO area offsets */ 60 #define RME96_IO_PLAY_BUFFER 0x0 61 #define RME96_IO_REC_BUFFER 0x10000 62 #define RME96_IO_CONTROL_REGISTER 0x20000 63 #define RME96_IO_ADDITIONAL_REG 0x20004 64 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 65 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 66 #define RME96_IO_SET_PLAY_POS 0x40000 67 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 68 #define RME96_IO_SET_REC_POS 0x50000 69 #define RME96_IO_RESET_REC_POS 0x5FFFC 70 #define RME96_IO_GET_PLAY_POS 0x20000 71 #define RME96_IO_GET_REC_POS 0x30000 72 73 /* Write control register bits */ 74 #define RME96_WCR_START (1 << 0) 75 #define RME96_WCR_START_2 (1 << 1) 76 #define RME96_WCR_GAIN_0 (1 << 2) 77 #define RME96_WCR_GAIN_1 (1 << 3) 78 #define RME96_WCR_MODE24 (1 << 4) 79 #define RME96_WCR_MODE24_2 (1 << 5) 80 #define RME96_WCR_BM (1 << 6) 81 #define RME96_WCR_BM_2 (1 << 7) 82 #define RME96_WCR_ADAT (1 << 8) 83 #define RME96_WCR_FREQ_0 (1 << 9) 84 #define RME96_WCR_FREQ_1 (1 << 10) 85 #define RME96_WCR_DS (1 << 11) 86 #define RME96_WCR_PRO (1 << 12) 87 #define RME96_WCR_EMP (1 << 13) 88 #define RME96_WCR_SEL (1 << 14) 89 #define RME96_WCR_MASTER (1 << 15) 90 #define RME96_WCR_PD (1 << 16) 91 #define RME96_WCR_INP_0 (1 << 17) 92 #define RME96_WCR_INP_1 (1 << 18) 93 #define RME96_WCR_THRU_0 (1 << 19) 94 #define RME96_WCR_THRU_1 (1 << 20) 95 #define RME96_WCR_THRU_2 (1 << 21) 96 #define RME96_WCR_THRU_3 (1 << 22) 97 #define RME96_WCR_THRU_4 (1 << 23) 98 #define RME96_WCR_THRU_5 (1 << 24) 99 #define RME96_WCR_THRU_6 (1 << 25) 100 #define RME96_WCR_THRU_7 (1 << 26) 101 #define RME96_WCR_DOLBY (1 << 27) 102 #define RME96_WCR_MONITOR_0 (1 << 28) 103 #define RME96_WCR_MONITOR_1 (1 << 29) 104 #define RME96_WCR_ISEL (1 << 30) 105 #define RME96_WCR_IDIS (1 << 31) 106 107 #define RME96_WCR_BITPOS_GAIN_0 2 108 #define RME96_WCR_BITPOS_GAIN_1 3 109 #define RME96_WCR_BITPOS_FREQ_0 9 110 #define RME96_WCR_BITPOS_FREQ_1 10 111 #define RME96_WCR_BITPOS_INP_0 17 112 #define RME96_WCR_BITPOS_INP_1 18 113 #define RME96_WCR_BITPOS_MONITOR_0 28 114 #define RME96_WCR_BITPOS_MONITOR_1 29 115 116 /* Read control register bits */ 117 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 118 #define RME96_RCR_IRQ_2 (1 << 16) 119 #define RME96_RCR_T_OUT (1 << 17) 120 #define RME96_RCR_DEV_ID_0 (1 << 21) 121 #define RME96_RCR_DEV_ID_1 (1 << 22) 122 #define RME96_RCR_LOCK (1 << 23) 123 #define RME96_RCR_VERF (1 << 26) 124 #define RME96_RCR_F0 (1 << 27) 125 #define RME96_RCR_F1 (1 << 28) 126 #define RME96_RCR_F2 (1 << 29) 127 #define RME96_RCR_AUTOSYNC (1 << 30) 128 #define RME96_RCR_IRQ (1 << 31) 129 130 #define RME96_RCR_BITPOS_F0 27 131 #define RME96_RCR_BITPOS_F1 28 132 #define RME96_RCR_BITPOS_F2 29 133 134 /* Additional register bits */ 135 #define RME96_AR_WSEL (1 << 0) 136 #define RME96_AR_ANALOG (1 << 1) 137 #define RME96_AR_FREQPAD_0 (1 << 2) 138 #define RME96_AR_FREQPAD_1 (1 << 3) 139 #define RME96_AR_FREQPAD_2 (1 << 4) 140 #define RME96_AR_PD2 (1 << 5) 141 #define RME96_AR_DAC_EN (1 << 6) 142 #define RME96_AR_CLATCH (1 << 7) 143 #define RME96_AR_CCLK (1 << 8) 144 #define RME96_AR_CDATA (1 << 9) 145 146 #define RME96_AR_BITPOS_F0 2 147 #define RME96_AR_BITPOS_F1 3 148 #define RME96_AR_BITPOS_F2 4 149 150 /* Monitor tracks */ 151 #define RME96_MONITOR_TRACKS_1_2 0 152 #define RME96_MONITOR_TRACKS_3_4 1 153 #define RME96_MONITOR_TRACKS_5_6 2 154 #define RME96_MONITOR_TRACKS_7_8 3 155 156 /* Attenuation */ 157 #define RME96_ATTENUATION_0 0 158 #define RME96_ATTENUATION_6 1 159 #define RME96_ATTENUATION_12 2 160 #define RME96_ATTENUATION_18 3 161 162 /* Input types */ 163 #define RME96_INPUT_OPTICAL 0 164 #define RME96_INPUT_COAXIAL 1 165 #define RME96_INPUT_INTERNAL 2 166 #define RME96_INPUT_XLR 3 167 #define RME96_INPUT_ANALOG 4 168 169 /* Clock modes */ 170 #define RME96_CLOCKMODE_SLAVE 0 171 #define RME96_CLOCKMODE_MASTER 1 172 #define RME96_CLOCKMODE_WORDCLOCK 2 173 174 /* Block sizes in bytes */ 175 #define RME96_SMALL_BLOCK_SIZE 2048 176 #define RME96_LARGE_BLOCK_SIZE 8192 177 178 /* Volume control */ 179 #define RME96_AD1852_VOL_BITS 14 180 #define RME96_AD1855_VOL_BITS 10 181 182 /* Defines for snd_rme96_trigger */ 183 #define RME96_TB_START_PLAYBACK 1 184 #define RME96_TB_START_CAPTURE 2 185 #define RME96_TB_STOP_PLAYBACK 4 186 #define RME96_TB_STOP_CAPTURE 8 187 #define RME96_TB_RESET_PLAYPOS 16 188 #define RME96_TB_RESET_CAPTUREPOS 32 189 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 190 #define RME96_TB_CLEAR_CAPTURE_IRQ 128 191 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) 192 #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) 193 #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ 194 | RME96_RESUME_CAPTURE) 195 #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ 196 | RME96_TB_RESET_PLAYPOS) 197 #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ 198 | RME96_TB_RESET_CAPTUREPOS) 199 #define RME96_START_BOTH (RME96_START_PLAYBACK \ 200 | RME96_START_CAPTURE) 201 #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ 202 | RME96_TB_CLEAR_PLAYBACK_IRQ) 203 #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ 204 | RME96_TB_CLEAR_CAPTURE_IRQ) 205 #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ 206 | RME96_STOP_CAPTURE) 207 208 struct rme96 { 209 spinlock_t lock; 210 int irq; 211 unsigned long port; 212 void __iomem *iobase; 213 214 u32 wcreg; /* cached write control register value */ 215 u32 wcreg_spdif; /* S/PDIF setup */ 216 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 217 u32 rcreg; /* cached read control register value */ 218 u32 areg; /* cached additional register value */ 219 u16 vol[2]; /* cached volume of analog output */ 220 221 u8 rev; /* card revision number */ 222 223 #ifdef CONFIG_PM_SLEEP 224 u32 playback_pointer; 225 u32 capture_pointer; 226 void *playback_suspend_buffer; 227 void *capture_suspend_buffer; 228 #endif 229 230 struct snd_pcm_substream *playback_substream; 231 struct snd_pcm_substream *capture_substream; 232 233 int playback_frlog; /* log2 of framesize */ 234 int capture_frlog; 235 236 size_t playback_periodsize; /* in bytes, zero if not used */ 237 size_t capture_periodsize; /* in bytes, zero if not used */ 238 239 struct snd_card *card; 240 struct snd_pcm *spdif_pcm; 241 struct snd_pcm *adat_pcm; 242 struct pci_dev *pci; 243 struct snd_kcontrol *spdif_ctl; 244 }; 245 246 static const struct pci_device_id snd_rme96_ids[] = { 247 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, 248 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, 249 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, 250 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, 251 { 0, } 252 }; 253 254 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 255 256 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) 257 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) 258 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 259 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ 260 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 261 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) 262 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ 263 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) 264 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) 265 266 static int 267 snd_rme96_playback_prepare(struct snd_pcm_substream *substream); 268 269 static int 270 snd_rme96_capture_prepare(struct snd_pcm_substream *substream); 271 272 static int 273 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 274 int cmd); 275 276 static int 277 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 278 int cmd); 279 280 static snd_pcm_uframes_t 281 snd_rme96_playback_pointer(struct snd_pcm_substream *substream); 282 283 static snd_pcm_uframes_t 284 snd_rme96_capture_pointer(struct snd_pcm_substream *substream); 285 286 static void snd_rme96_proc_init(struct rme96 *rme96); 287 288 static int 289 snd_rme96_create_switches(struct snd_card *card, 290 struct rme96 *rme96); 291 292 static int 293 snd_rme96_getinputtype(struct rme96 *rme96); 294 295 static inline unsigned int 296 snd_rme96_playback_ptr(struct rme96 *rme96) 297 { 298 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 299 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; 300 } 301 302 static inline unsigned int 303 snd_rme96_capture_ptr(struct rme96 *rme96) 304 { 305 return (readl(rme96->iobase + RME96_IO_GET_REC_POS) 306 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; 307 } 308 309 static int 310 snd_rme96_playback_silence(struct snd_pcm_substream *substream, 311 int channel, unsigned long pos, unsigned long count) 312 { 313 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 314 315 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 316 0, count); 317 return 0; 318 } 319 320 static int 321 snd_rme96_playback_copy(struct snd_pcm_substream *substream, 322 int channel, unsigned long pos, 323 void __user *src, unsigned long count) 324 { 325 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 326 327 return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 328 src, count); 329 } 330 331 static int 332 snd_rme96_playback_copy_kernel(struct snd_pcm_substream *substream, 333 int channel, unsigned long pos, 334 void *src, unsigned long count) 335 { 336 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 337 338 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, count); 339 return 0; 340 } 341 342 static int 343 snd_rme96_capture_copy(struct snd_pcm_substream *substream, 344 int channel, unsigned long pos, 345 void __user *dst, unsigned long count) 346 { 347 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 348 349 return copy_to_user_fromio(dst, 350 rme96->iobase + RME96_IO_REC_BUFFER + pos, 351 count); 352 } 353 354 static int 355 snd_rme96_capture_copy_kernel(struct snd_pcm_substream *substream, 356 int channel, unsigned long pos, 357 void *dst, unsigned long count) 358 { 359 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 360 361 memcpy_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, count); 362 return 0; 363 } 364 365 /* 366 * Digital output capabilities (S/PDIF) 367 */ 368 static const struct snd_pcm_hardware snd_rme96_playback_spdif_info = 369 { 370 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 371 SNDRV_PCM_INFO_MMAP_VALID | 372 SNDRV_PCM_INFO_SYNC_START | 373 SNDRV_PCM_INFO_RESUME | 374 SNDRV_PCM_INFO_INTERLEAVED | 375 SNDRV_PCM_INFO_PAUSE), 376 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 377 SNDRV_PCM_FMTBIT_S32_LE), 378 .rates = (SNDRV_PCM_RATE_32000 | 379 SNDRV_PCM_RATE_44100 | 380 SNDRV_PCM_RATE_48000 | 381 SNDRV_PCM_RATE_64000 | 382 SNDRV_PCM_RATE_88200 | 383 SNDRV_PCM_RATE_96000), 384 .rate_min = 32000, 385 .rate_max = 96000, 386 .channels_min = 2, 387 .channels_max = 2, 388 .buffer_bytes_max = RME96_BUFFER_SIZE, 389 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 390 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 391 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 392 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 393 .fifo_size = 0, 394 }; 395 396 /* 397 * Digital input capabilities (S/PDIF) 398 */ 399 static const struct snd_pcm_hardware snd_rme96_capture_spdif_info = 400 { 401 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 402 SNDRV_PCM_INFO_MMAP_VALID | 403 SNDRV_PCM_INFO_SYNC_START | 404 SNDRV_PCM_INFO_RESUME | 405 SNDRV_PCM_INFO_INTERLEAVED | 406 SNDRV_PCM_INFO_PAUSE), 407 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 408 SNDRV_PCM_FMTBIT_S32_LE), 409 .rates = (SNDRV_PCM_RATE_32000 | 410 SNDRV_PCM_RATE_44100 | 411 SNDRV_PCM_RATE_48000 | 412 SNDRV_PCM_RATE_64000 | 413 SNDRV_PCM_RATE_88200 | 414 SNDRV_PCM_RATE_96000), 415 .rate_min = 32000, 416 .rate_max = 96000, 417 .channels_min = 2, 418 .channels_max = 2, 419 .buffer_bytes_max = RME96_BUFFER_SIZE, 420 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 421 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 422 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 423 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 424 .fifo_size = 0, 425 }; 426 427 /* 428 * Digital output capabilities (ADAT) 429 */ 430 static const struct snd_pcm_hardware snd_rme96_playback_adat_info = 431 { 432 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 433 SNDRV_PCM_INFO_MMAP_VALID | 434 SNDRV_PCM_INFO_SYNC_START | 435 SNDRV_PCM_INFO_RESUME | 436 SNDRV_PCM_INFO_INTERLEAVED | 437 SNDRV_PCM_INFO_PAUSE), 438 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 439 SNDRV_PCM_FMTBIT_S32_LE), 440 .rates = (SNDRV_PCM_RATE_44100 | 441 SNDRV_PCM_RATE_48000), 442 .rate_min = 44100, 443 .rate_max = 48000, 444 .channels_min = 8, 445 .channels_max = 8, 446 .buffer_bytes_max = RME96_BUFFER_SIZE, 447 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 448 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 449 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 450 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 451 .fifo_size = 0, 452 }; 453 454 /* 455 * Digital input capabilities (ADAT) 456 */ 457 static const struct snd_pcm_hardware snd_rme96_capture_adat_info = 458 { 459 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 460 SNDRV_PCM_INFO_MMAP_VALID | 461 SNDRV_PCM_INFO_SYNC_START | 462 SNDRV_PCM_INFO_RESUME | 463 SNDRV_PCM_INFO_INTERLEAVED | 464 SNDRV_PCM_INFO_PAUSE), 465 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 466 SNDRV_PCM_FMTBIT_S32_LE), 467 .rates = (SNDRV_PCM_RATE_44100 | 468 SNDRV_PCM_RATE_48000), 469 .rate_min = 44100, 470 .rate_max = 48000, 471 .channels_min = 8, 472 .channels_max = 8, 473 .buffer_bytes_max = RME96_BUFFER_SIZE, 474 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 475 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 476 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 477 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 478 .fifo_size = 0, 479 }; 480 481 /* 482 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface 483 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up 484 * on the falling edge of CCLK and be stable on the rising edge. The rising 485 * edge of CLATCH after the last data bit clocks in the whole data word. 486 * A fast processor could probably drive the SPI interface faster than the 487 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) 488 * limits the data rate to 500KHz and only causes a delay of 33 microsecs. 489 * 490 * NOTE: increased delay from 1 to 10, since there where problems setting 491 * the volume. 492 */ 493 static void 494 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) 495 { 496 int i; 497 498 for (i = 0; i < 16; i++) { 499 if (val & 0x8000) { 500 rme96->areg |= RME96_AR_CDATA; 501 } else { 502 rme96->areg &= ~RME96_AR_CDATA; 503 } 504 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); 505 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 506 udelay(10); 507 rme96->areg |= RME96_AR_CCLK; 508 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 509 udelay(10); 510 val <<= 1; 511 } 512 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); 513 rme96->areg |= RME96_AR_CLATCH; 514 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 515 udelay(10); 516 rme96->areg &= ~RME96_AR_CLATCH; 517 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 518 } 519 520 static void 521 snd_rme96_apply_dac_volume(struct rme96 *rme96) 522 { 523 if (RME96_DAC_IS_1852(rme96)) { 524 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); 525 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); 526 } else if (RME96_DAC_IS_1855(rme96)) { 527 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); 528 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); 529 } 530 } 531 532 static void 533 snd_rme96_reset_dac(struct rme96 *rme96) 534 { 535 writel(rme96->wcreg | RME96_WCR_PD, 536 rme96->iobase + RME96_IO_CONTROL_REGISTER); 537 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 538 } 539 540 static int 541 snd_rme96_getmontracks(struct rme96 *rme96) 542 { 543 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + 544 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); 545 } 546 547 static int 548 snd_rme96_setmontracks(struct rme96 *rme96, 549 int montracks) 550 { 551 if (montracks & 1) { 552 rme96->wcreg |= RME96_WCR_MONITOR_0; 553 } else { 554 rme96->wcreg &= ~RME96_WCR_MONITOR_0; 555 } 556 if (montracks & 2) { 557 rme96->wcreg |= RME96_WCR_MONITOR_1; 558 } else { 559 rme96->wcreg &= ~RME96_WCR_MONITOR_1; 560 } 561 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 562 return 0; 563 } 564 565 static int 566 snd_rme96_getattenuation(struct rme96 *rme96) 567 { 568 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + 569 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); 570 } 571 572 static int 573 snd_rme96_setattenuation(struct rme96 *rme96, 574 int attenuation) 575 { 576 switch (attenuation) { 577 case 0: 578 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & 579 ~RME96_WCR_GAIN_1; 580 break; 581 case 1: 582 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & 583 ~RME96_WCR_GAIN_1; 584 break; 585 case 2: 586 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | 587 RME96_WCR_GAIN_1; 588 break; 589 case 3: 590 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | 591 RME96_WCR_GAIN_1; 592 break; 593 default: 594 return -EINVAL; 595 } 596 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 597 return 0; 598 } 599 600 static int 601 snd_rme96_capture_getrate(struct rme96 *rme96, 602 int *is_adat) 603 { 604 int n, rate; 605 606 *is_adat = 0; 607 if (rme96->areg & RME96_AR_ANALOG) { 608 /* Analog input, overrides S/PDIF setting */ 609 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + 610 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); 611 switch (n) { 612 case 1: 613 rate = 32000; 614 break; 615 case 2: 616 rate = 44100; 617 break; 618 case 3: 619 rate = 48000; 620 break; 621 default: 622 return -1; 623 } 624 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; 625 } 626 627 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 628 if (rme96->rcreg & RME96_RCR_LOCK) { 629 /* ADAT rate */ 630 *is_adat = 1; 631 if (rme96->rcreg & RME96_RCR_T_OUT) { 632 return 48000; 633 } 634 return 44100; 635 } 636 637 if (rme96->rcreg & RME96_RCR_VERF) { 638 return -1; 639 } 640 641 /* S/PDIF rate */ 642 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + 643 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + 644 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); 645 646 switch (n) { 647 case 0: 648 if (rme96->rcreg & RME96_RCR_T_OUT) { 649 return 64000; 650 } 651 return -1; 652 case 3: return 96000; 653 case 4: return 88200; 654 case 5: return 48000; 655 case 6: return 44100; 656 case 7: return 32000; 657 default: 658 break; 659 } 660 return -1; 661 } 662 663 static int 664 snd_rme96_playback_getrate(struct rme96 *rme96) 665 { 666 int rate, dummy; 667 668 if (!(rme96->wcreg & RME96_WCR_MASTER) && 669 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 670 rate = snd_rme96_capture_getrate(rme96, &dummy); 671 if (rate > 0) { 672 /* slave clock */ 673 return rate; 674 } 675 } 676 677 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + 678 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); 679 switch (rate) { 680 case 1: 681 rate = 32000; 682 break; 683 case 2: 684 rate = 44100; 685 break; 686 case 3: 687 rate = 48000; 688 break; 689 default: 690 return -1; 691 } 692 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; 693 } 694 695 static int 696 snd_rme96_playback_setrate(struct rme96 *rme96, 697 int rate) 698 { 699 int ds; 700 701 ds = rme96->wcreg & RME96_WCR_DS; 702 switch (rate) { 703 case 32000: 704 rme96->wcreg &= ~RME96_WCR_DS; 705 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 706 ~RME96_WCR_FREQ_1; 707 break; 708 case 44100: 709 rme96->wcreg &= ~RME96_WCR_DS; 710 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 711 ~RME96_WCR_FREQ_0; 712 break; 713 case 48000: 714 rme96->wcreg &= ~RME96_WCR_DS; 715 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 716 RME96_WCR_FREQ_1; 717 break; 718 case 64000: 719 rme96->wcreg |= RME96_WCR_DS; 720 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 721 ~RME96_WCR_FREQ_1; 722 break; 723 case 88200: 724 rme96->wcreg |= RME96_WCR_DS; 725 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 726 ~RME96_WCR_FREQ_0; 727 break; 728 case 96000: 729 rme96->wcreg |= RME96_WCR_DS; 730 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 731 RME96_WCR_FREQ_1; 732 break; 733 default: 734 return -EINVAL; 735 } 736 if ((!ds && rme96->wcreg & RME96_WCR_DS) || 737 (ds && !(rme96->wcreg & RME96_WCR_DS))) 738 { 739 /* change to/from double-speed: reset the DAC (if available) */ 740 snd_rme96_reset_dac(rme96); 741 return 1; /* need to restore volume */ 742 } else { 743 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 744 return 0; 745 } 746 } 747 748 static int 749 snd_rme96_capture_analog_setrate(struct rme96 *rme96, 750 int rate) 751 { 752 switch (rate) { 753 case 32000: 754 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 755 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 756 break; 757 case 44100: 758 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 759 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 760 break; 761 case 48000: 762 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 763 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 764 break; 765 case 64000: 766 if (rme96->rev < 4) { 767 return -EINVAL; 768 } 769 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 770 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 771 break; 772 case 88200: 773 if (rme96->rev < 4) { 774 return -EINVAL; 775 } 776 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 777 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 778 break; 779 case 96000: 780 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 781 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 782 break; 783 default: 784 return -EINVAL; 785 } 786 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 787 return 0; 788 } 789 790 static int 791 snd_rme96_setclockmode(struct rme96 *rme96, 792 int mode) 793 { 794 switch (mode) { 795 case RME96_CLOCKMODE_SLAVE: 796 /* AutoSync */ 797 rme96->wcreg &= ~RME96_WCR_MASTER; 798 rme96->areg &= ~RME96_AR_WSEL; 799 break; 800 case RME96_CLOCKMODE_MASTER: 801 /* Internal */ 802 rme96->wcreg |= RME96_WCR_MASTER; 803 rme96->areg &= ~RME96_AR_WSEL; 804 break; 805 case RME96_CLOCKMODE_WORDCLOCK: 806 /* Word clock is a master mode */ 807 rme96->wcreg |= RME96_WCR_MASTER; 808 rme96->areg |= RME96_AR_WSEL; 809 break; 810 default: 811 return -EINVAL; 812 } 813 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 814 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 815 return 0; 816 } 817 818 static int 819 snd_rme96_getclockmode(struct rme96 *rme96) 820 { 821 if (rme96->areg & RME96_AR_WSEL) { 822 return RME96_CLOCKMODE_WORDCLOCK; 823 } 824 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : 825 RME96_CLOCKMODE_SLAVE; 826 } 827 828 static int 829 snd_rme96_setinputtype(struct rme96 *rme96, 830 int type) 831 { 832 int n; 833 834 switch (type) { 835 case RME96_INPUT_OPTICAL: 836 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & 837 ~RME96_WCR_INP_1; 838 break; 839 case RME96_INPUT_COAXIAL: 840 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & 841 ~RME96_WCR_INP_1; 842 break; 843 case RME96_INPUT_INTERNAL: 844 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | 845 RME96_WCR_INP_1; 846 break; 847 case RME96_INPUT_XLR: 848 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 849 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || 850 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 851 rme96->rev > 4)) 852 { 853 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ 854 return -EINVAL; 855 } 856 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | 857 RME96_WCR_INP_1; 858 break; 859 case RME96_INPUT_ANALOG: 860 if (!RME96_HAS_ANALOG_IN(rme96)) { 861 return -EINVAL; 862 } 863 rme96->areg |= RME96_AR_ANALOG; 864 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 865 if (rme96->rev < 4) { 866 /* 867 * Revision less than 004 does not support 64 and 868 * 88.2 kHz 869 */ 870 if (snd_rme96_capture_getrate(rme96, &n) == 88200) { 871 snd_rme96_capture_analog_setrate(rme96, 44100); 872 } 873 if (snd_rme96_capture_getrate(rme96, &n) == 64000) { 874 snd_rme96_capture_analog_setrate(rme96, 32000); 875 } 876 } 877 return 0; 878 default: 879 return -EINVAL; 880 } 881 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { 882 rme96->areg &= ~RME96_AR_ANALOG; 883 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 884 } 885 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 886 return 0; 887 } 888 889 static int 890 snd_rme96_getinputtype(struct rme96 *rme96) 891 { 892 if (rme96->areg & RME96_AR_ANALOG) { 893 return RME96_INPUT_ANALOG; 894 } 895 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + 896 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); 897 } 898 899 static void 900 snd_rme96_setframelog(struct rme96 *rme96, 901 int n_channels, 902 int is_playback) 903 { 904 int frlog; 905 906 if (n_channels == 2) { 907 frlog = 1; 908 } else { 909 /* assume 8 channels */ 910 frlog = 3; 911 } 912 if (is_playback) { 913 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; 914 rme96->playback_frlog = frlog; 915 } else { 916 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; 917 rme96->capture_frlog = frlog; 918 } 919 } 920 921 static int 922 snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format) 923 { 924 switch (format) { 925 case SNDRV_PCM_FORMAT_S16_LE: 926 rme96->wcreg &= ~RME96_WCR_MODE24; 927 break; 928 case SNDRV_PCM_FORMAT_S32_LE: 929 rme96->wcreg |= RME96_WCR_MODE24; 930 break; 931 default: 932 return -EINVAL; 933 } 934 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 935 return 0; 936 } 937 938 static int 939 snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format) 940 { 941 switch (format) { 942 case SNDRV_PCM_FORMAT_S16_LE: 943 rme96->wcreg &= ~RME96_WCR_MODE24_2; 944 break; 945 case SNDRV_PCM_FORMAT_S32_LE: 946 rme96->wcreg |= RME96_WCR_MODE24_2; 947 break; 948 default: 949 return -EINVAL; 950 } 951 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 952 return 0; 953 } 954 955 static void 956 snd_rme96_set_period_properties(struct rme96 *rme96, 957 size_t period_bytes) 958 { 959 switch (period_bytes) { 960 case RME96_LARGE_BLOCK_SIZE: 961 rme96->wcreg &= ~RME96_WCR_ISEL; 962 break; 963 case RME96_SMALL_BLOCK_SIZE: 964 rme96->wcreg |= RME96_WCR_ISEL; 965 break; 966 default: 967 snd_BUG(); 968 break; 969 } 970 rme96->wcreg &= ~RME96_WCR_IDIS; 971 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 972 } 973 974 static int 975 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, 976 struct snd_pcm_hw_params *params) 977 { 978 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 979 struct snd_pcm_runtime *runtime = substream->runtime; 980 int err, rate, dummy; 981 bool apply_dac_volume = false; 982 983 runtime->dma_area = (void __force *)(rme96->iobase + 984 RME96_IO_PLAY_BUFFER); 985 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; 986 runtime->dma_bytes = RME96_BUFFER_SIZE; 987 988 spin_lock_irq(&rme96->lock); 989 rate = 0; 990 if (!(rme96->wcreg & RME96_WCR_MASTER) && 991 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) 992 rate = snd_rme96_capture_getrate(rme96, &dummy); 993 if (rate > 0) { 994 /* slave clock */ 995 if ((int)params_rate(params) != rate) { 996 err = -EIO; 997 goto error; 998 } 999 } else { 1000 err = snd_rme96_playback_setrate(rme96, params_rate(params)); 1001 if (err < 0) 1002 goto error; 1003 apply_dac_volume = err > 0; /* need to restore volume later? */ 1004 } 1005 1006 err = snd_rme96_playback_setformat(rme96, params_format(params)); 1007 if (err < 0) 1008 goto error; 1009 snd_rme96_setframelog(rme96, params_channels(params), 1); 1010 if (rme96->capture_periodsize != 0) { 1011 if (params_period_size(params) << rme96->playback_frlog != 1012 rme96->capture_periodsize) 1013 { 1014 err = -EBUSY; 1015 goto error; 1016 } 1017 } 1018 rme96->playback_periodsize = 1019 params_period_size(params) << rme96->playback_frlog; 1020 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); 1021 /* S/PDIF setup */ 1022 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { 1023 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 1024 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1025 } 1026 1027 err = 0; 1028 error: 1029 spin_unlock_irq(&rme96->lock); 1030 if (apply_dac_volume) { 1031 usleep_range(3000, 10000); 1032 snd_rme96_apply_dac_volume(rme96); 1033 } 1034 1035 return err; 1036 } 1037 1038 static int 1039 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, 1040 struct snd_pcm_hw_params *params) 1041 { 1042 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1043 struct snd_pcm_runtime *runtime = substream->runtime; 1044 int err, isadat, rate; 1045 1046 runtime->dma_area = (void __force *)(rme96->iobase + 1047 RME96_IO_REC_BUFFER); 1048 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; 1049 runtime->dma_bytes = RME96_BUFFER_SIZE; 1050 1051 spin_lock_irq(&rme96->lock); 1052 err = snd_rme96_capture_setformat(rme96, params_format(params)); 1053 if (err < 0) { 1054 spin_unlock_irq(&rme96->lock); 1055 return err; 1056 } 1057 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1058 err = snd_rme96_capture_analog_setrate(rme96, params_rate(params)); 1059 if (err < 0) { 1060 spin_unlock_irq(&rme96->lock); 1061 return err; 1062 } 1063 } else { 1064 rate = snd_rme96_capture_getrate(rme96, &isadat); 1065 if (rate > 0) { 1066 if ((int)params_rate(params) != rate) { 1067 spin_unlock_irq(&rme96->lock); 1068 return -EIO; 1069 } 1070 if ((isadat && runtime->hw.channels_min == 2) || 1071 (!isadat && runtime->hw.channels_min == 8)) { 1072 spin_unlock_irq(&rme96->lock); 1073 return -EIO; 1074 } 1075 } 1076 } 1077 snd_rme96_setframelog(rme96, params_channels(params), 0); 1078 if (rme96->playback_periodsize != 0) { 1079 if (params_period_size(params) << rme96->capture_frlog != 1080 rme96->playback_periodsize) 1081 { 1082 spin_unlock_irq(&rme96->lock); 1083 return -EBUSY; 1084 } 1085 } 1086 rme96->capture_periodsize = 1087 params_period_size(params) << rme96->capture_frlog; 1088 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); 1089 spin_unlock_irq(&rme96->lock); 1090 1091 return 0; 1092 } 1093 1094 static void 1095 snd_rme96_trigger(struct rme96 *rme96, 1096 int op) 1097 { 1098 if (op & RME96_TB_RESET_PLAYPOS) 1099 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1100 if (op & RME96_TB_RESET_CAPTUREPOS) 1101 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1102 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { 1103 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1104 if (rme96->rcreg & RME96_RCR_IRQ) 1105 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1106 } 1107 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { 1108 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1109 if (rme96->rcreg & RME96_RCR_IRQ_2) 1110 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1111 } 1112 if (op & RME96_TB_START_PLAYBACK) 1113 rme96->wcreg |= RME96_WCR_START; 1114 if (op & RME96_TB_STOP_PLAYBACK) 1115 rme96->wcreg &= ~RME96_WCR_START; 1116 if (op & RME96_TB_START_CAPTURE) 1117 rme96->wcreg |= RME96_WCR_START_2; 1118 if (op & RME96_TB_STOP_CAPTURE) 1119 rme96->wcreg &= ~RME96_WCR_START_2; 1120 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1121 } 1122 1123 1124 1125 static irqreturn_t 1126 snd_rme96_interrupt(int irq, 1127 void *dev_id) 1128 { 1129 struct rme96 *rme96 = (struct rme96 *)dev_id; 1130 1131 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1132 /* fastpath out, to ease interrupt sharing */ 1133 if (!((rme96->rcreg & RME96_RCR_IRQ) || 1134 (rme96->rcreg & RME96_RCR_IRQ_2))) 1135 { 1136 return IRQ_NONE; 1137 } 1138 1139 if (rme96->rcreg & RME96_RCR_IRQ) { 1140 /* playback */ 1141 snd_pcm_period_elapsed(rme96->playback_substream); 1142 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1143 } 1144 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1145 /* capture */ 1146 snd_pcm_period_elapsed(rme96->capture_substream); 1147 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1148 } 1149 return IRQ_HANDLED; 1150 } 1151 1152 static const unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; 1153 1154 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 1155 .count = ARRAY_SIZE(period_bytes), 1156 .list = period_bytes, 1157 .mask = 0 1158 }; 1159 1160 static void 1161 rme96_set_buffer_size_constraint(struct rme96 *rme96, 1162 struct snd_pcm_runtime *runtime) 1163 { 1164 unsigned int size; 1165 1166 snd_pcm_hw_constraint_single(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1167 RME96_BUFFER_SIZE); 1168 size = rme96->playback_periodsize; 1169 if (!size) 1170 size = rme96->capture_periodsize; 1171 if (size) 1172 snd_pcm_hw_constraint_single(runtime, 1173 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1174 size); 1175 else 1176 snd_pcm_hw_constraint_list(runtime, 0, 1177 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1178 &hw_constraints_period_bytes); 1179 } 1180 1181 static int 1182 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) 1183 { 1184 int rate, dummy; 1185 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1186 struct snd_pcm_runtime *runtime = substream->runtime; 1187 1188 snd_pcm_set_sync(substream); 1189 spin_lock_irq(&rme96->lock); 1190 if (rme96->playback_substream) { 1191 spin_unlock_irq(&rme96->lock); 1192 return -EBUSY; 1193 } 1194 rme96->wcreg &= ~RME96_WCR_ADAT; 1195 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1196 rme96->playback_substream = substream; 1197 spin_unlock_irq(&rme96->lock); 1198 1199 runtime->hw = snd_rme96_playback_spdif_info; 1200 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1201 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 1202 rate = snd_rme96_capture_getrate(rme96, &dummy); 1203 if (rate > 0) { 1204 /* slave clock */ 1205 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1206 runtime->hw.rate_min = rate; 1207 runtime->hw.rate_max = rate; 1208 } 1209 } 1210 rme96_set_buffer_size_constraint(rme96, runtime); 1211 1212 rme96->wcreg_spdif_stream = rme96->wcreg_spdif; 1213 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1214 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1215 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1216 return 0; 1217 } 1218 1219 static int 1220 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) 1221 { 1222 int isadat, rate; 1223 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1224 struct snd_pcm_runtime *runtime = substream->runtime; 1225 1226 snd_pcm_set_sync(substream); 1227 runtime->hw = snd_rme96_capture_spdif_info; 1228 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 1229 rate = snd_rme96_capture_getrate(rme96, &isadat); 1230 if (rate > 0) { 1231 if (isadat) 1232 return -EIO; 1233 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1234 runtime->hw.rate_min = rate; 1235 runtime->hw.rate_max = rate; 1236 } 1237 } 1238 1239 spin_lock_irq(&rme96->lock); 1240 if (rme96->capture_substream) { 1241 spin_unlock_irq(&rme96->lock); 1242 return -EBUSY; 1243 } 1244 rme96->capture_substream = substream; 1245 spin_unlock_irq(&rme96->lock); 1246 1247 rme96_set_buffer_size_constraint(rme96, runtime); 1248 return 0; 1249 } 1250 1251 static int 1252 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) 1253 { 1254 int rate, dummy; 1255 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1256 struct snd_pcm_runtime *runtime = substream->runtime; 1257 1258 snd_pcm_set_sync(substream); 1259 spin_lock_irq(&rme96->lock); 1260 if (rme96->playback_substream) { 1261 spin_unlock_irq(&rme96->lock); 1262 return -EBUSY; 1263 } 1264 rme96->wcreg |= RME96_WCR_ADAT; 1265 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1266 rme96->playback_substream = substream; 1267 spin_unlock_irq(&rme96->lock); 1268 1269 runtime->hw = snd_rme96_playback_adat_info; 1270 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1271 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG) { 1272 rate = snd_rme96_capture_getrate(rme96, &dummy); 1273 if (rate > 0) { 1274 /* slave clock */ 1275 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1276 runtime->hw.rate_min = rate; 1277 runtime->hw.rate_max = rate; 1278 } 1279 } 1280 1281 rme96_set_buffer_size_constraint(rme96, runtime); 1282 return 0; 1283 } 1284 1285 static int 1286 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) 1287 { 1288 int isadat, rate; 1289 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1290 struct snd_pcm_runtime *runtime = substream->runtime; 1291 1292 snd_pcm_set_sync(substream); 1293 runtime->hw = snd_rme96_capture_adat_info; 1294 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1295 /* makes no sense to use analog input. Note that analog 1296 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ 1297 return -EIO; 1298 } 1299 rate = snd_rme96_capture_getrate(rme96, &isadat); 1300 if (rate > 0) { 1301 if (!isadat) { 1302 return -EIO; 1303 } 1304 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1305 runtime->hw.rate_min = rate; 1306 runtime->hw.rate_max = rate; 1307 } 1308 1309 spin_lock_irq(&rme96->lock); 1310 if (rme96->capture_substream) { 1311 spin_unlock_irq(&rme96->lock); 1312 return -EBUSY; 1313 } 1314 rme96->capture_substream = substream; 1315 spin_unlock_irq(&rme96->lock); 1316 1317 rme96_set_buffer_size_constraint(rme96, runtime); 1318 return 0; 1319 } 1320 1321 static int 1322 snd_rme96_playback_close(struct snd_pcm_substream *substream) 1323 { 1324 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1325 int spdif = 0; 1326 1327 spin_lock_irq(&rme96->lock); 1328 if (RME96_ISPLAYING(rme96)) { 1329 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1330 } 1331 rme96->playback_substream = NULL; 1332 rme96->playback_periodsize = 0; 1333 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; 1334 spin_unlock_irq(&rme96->lock); 1335 if (spdif) { 1336 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1337 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1338 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1339 } 1340 return 0; 1341 } 1342 1343 static int 1344 snd_rme96_capture_close(struct snd_pcm_substream *substream) 1345 { 1346 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1347 1348 spin_lock_irq(&rme96->lock); 1349 if (RME96_ISRECORDING(rme96)) { 1350 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1351 } 1352 rme96->capture_substream = NULL; 1353 rme96->capture_periodsize = 0; 1354 spin_unlock_irq(&rme96->lock); 1355 return 0; 1356 } 1357 1358 static int 1359 snd_rme96_playback_prepare(struct snd_pcm_substream *substream) 1360 { 1361 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1362 1363 spin_lock_irq(&rme96->lock); 1364 if (RME96_ISPLAYING(rme96)) { 1365 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1366 } 1367 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1368 spin_unlock_irq(&rme96->lock); 1369 return 0; 1370 } 1371 1372 static int 1373 snd_rme96_capture_prepare(struct snd_pcm_substream *substream) 1374 { 1375 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1376 1377 spin_lock_irq(&rme96->lock); 1378 if (RME96_ISRECORDING(rme96)) { 1379 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1380 } 1381 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1382 spin_unlock_irq(&rme96->lock); 1383 return 0; 1384 } 1385 1386 static int 1387 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 1388 int cmd) 1389 { 1390 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1391 struct snd_pcm_substream *s; 1392 bool sync; 1393 1394 snd_pcm_group_for_each_entry(s, substream) { 1395 if (snd_pcm_substream_chip(s) == rme96) 1396 snd_pcm_trigger_done(s, substream); 1397 } 1398 1399 sync = (rme96->playback_substream && rme96->capture_substream) && 1400 (rme96->playback_substream->group == 1401 rme96->capture_substream->group); 1402 1403 switch (cmd) { 1404 case SNDRV_PCM_TRIGGER_START: 1405 if (!RME96_ISPLAYING(rme96)) { 1406 if (substream != rme96->playback_substream) 1407 return -EBUSY; 1408 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1409 : RME96_START_PLAYBACK); 1410 } 1411 break; 1412 1413 case SNDRV_PCM_TRIGGER_SUSPEND: 1414 case SNDRV_PCM_TRIGGER_STOP: 1415 if (RME96_ISPLAYING(rme96)) { 1416 if (substream != rme96->playback_substream) 1417 return -EBUSY; 1418 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1419 : RME96_STOP_PLAYBACK); 1420 } 1421 break; 1422 1423 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1424 if (RME96_ISPLAYING(rme96)) 1425 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1426 : RME96_STOP_PLAYBACK); 1427 break; 1428 1429 case SNDRV_PCM_TRIGGER_RESUME: 1430 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1431 if (!RME96_ISPLAYING(rme96)) 1432 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1433 : RME96_RESUME_PLAYBACK); 1434 break; 1435 1436 default: 1437 return -EINVAL; 1438 } 1439 1440 return 0; 1441 } 1442 1443 static int 1444 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 1445 int cmd) 1446 { 1447 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1448 struct snd_pcm_substream *s; 1449 bool sync; 1450 1451 snd_pcm_group_for_each_entry(s, substream) { 1452 if (snd_pcm_substream_chip(s) == rme96) 1453 snd_pcm_trigger_done(s, substream); 1454 } 1455 1456 sync = (rme96->playback_substream && rme96->capture_substream) && 1457 (rme96->playback_substream->group == 1458 rme96->capture_substream->group); 1459 1460 switch (cmd) { 1461 case SNDRV_PCM_TRIGGER_START: 1462 if (!RME96_ISRECORDING(rme96)) { 1463 if (substream != rme96->capture_substream) 1464 return -EBUSY; 1465 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1466 : RME96_START_CAPTURE); 1467 } 1468 break; 1469 1470 case SNDRV_PCM_TRIGGER_SUSPEND: 1471 case SNDRV_PCM_TRIGGER_STOP: 1472 if (RME96_ISRECORDING(rme96)) { 1473 if (substream != rme96->capture_substream) 1474 return -EBUSY; 1475 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1476 : RME96_STOP_CAPTURE); 1477 } 1478 break; 1479 1480 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1481 if (RME96_ISRECORDING(rme96)) 1482 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1483 : RME96_STOP_CAPTURE); 1484 break; 1485 1486 case SNDRV_PCM_TRIGGER_RESUME: 1487 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1488 if (!RME96_ISRECORDING(rme96)) 1489 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1490 : RME96_RESUME_CAPTURE); 1491 break; 1492 1493 default: 1494 return -EINVAL; 1495 } 1496 1497 return 0; 1498 } 1499 1500 static snd_pcm_uframes_t 1501 snd_rme96_playback_pointer(struct snd_pcm_substream *substream) 1502 { 1503 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1504 return snd_rme96_playback_ptr(rme96); 1505 } 1506 1507 static snd_pcm_uframes_t 1508 snd_rme96_capture_pointer(struct snd_pcm_substream *substream) 1509 { 1510 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1511 return snd_rme96_capture_ptr(rme96); 1512 } 1513 1514 static const struct snd_pcm_ops snd_rme96_playback_spdif_ops = { 1515 .open = snd_rme96_playback_spdif_open, 1516 .close = snd_rme96_playback_close, 1517 .hw_params = snd_rme96_playback_hw_params, 1518 .prepare = snd_rme96_playback_prepare, 1519 .trigger = snd_rme96_playback_trigger, 1520 .pointer = snd_rme96_playback_pointer, 1521 .copy_user = snd_rme96_playback_copy, 1522 .copy_kernel = snd_rme96_playback_copy_kernel, 1523 .fill_silence = snd_rme96_playback_silence, 1524 .mmap = snd_pcm_lib_mmap_iomem, 1525 }; 1526 1527 static const struct snd_pcm_ops snd_rme96_capture_spdif_ops = { 1528 .open = snd_rme96_capture_spdif_open, 1529 .close = snd_rme96_capture_close, 1530 .hw_params = snd_rme96_capture_hw_params, 1531 .prepare = snd_rme96_capture_prepare, 1532 .trigger = snd_rme96_capture_trigger, 1533 .pointer = snd_rme96_capture_pointer, 1534 .copy_user = snd_rme96_capture_copy, 1535 .copy_kernel = snd_rme96_capture_copy_kernel, 1536 .mmap = snd_pcm_lib_mmap_iomem, 1537 }; 1538 1539 static const struct snd_pcm_ops snd_rme96_playback_adat_ops = { 1540 .open = snd_rme96_playback_adat_open, 1541 .close = snd_rme96_playback_close, 1542 .hw_params = snd_rme96_playback_hw_params, 1543 .prepare = snd_rme96_playback_prepare, 1544 .trigger = snd_rme96_playback_trigger, 1545 .pointer = snd_rme96_playback_pointer, 1546 .copy_user = snd_rme96_playback_copy, 1547 .copy_kernel = snd_rme96_playback_copy_kernel, 1548 .fill_silence = snd_rme96_playback_silence, 1549 .mmap = snd_pcm_lib_mmap_iomem, 1550 }; 1551 1552 static const struct snd_pcm_ops snd_rme96_capture_adat_ops = { 1553 .open = snd_rme96_capture_adat_open, 1554 .close = snd_rme96_capture_close, 1555 .hw_params = snd_rme96_capture_hw_params, 1556 .prepare = snd_rme96_capture_prepare, 1557 .trigger = snd_rme96_capture_trigger, 1558 .pointer = snd_rme96_capture_pointer, 1559 .copy_user = snd_rme96_capture_copy, 1560 .copy_kernel = snd_rme96_capture_copy_kernel, 1561 .mmap = snd_pcm_lib_mmap_iomem, 1562 }; 1563 1564 static void 1565 snd_rme96_free(void *private_data) 1566 { 1567 struct rme96 *rme96 = (struct rme96 *)private_data; 1568 1569 if (!rme96) 1570 return; 1571 1572 if (rme96->irq >= 0) { 1573 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1574 rme96->areg &= ~RME96_AR_DAC_EN; 1575 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1576 free_irq(rme96->irq, (void *)rme96); 1577 rme96->irq = -1; 1578 } 1579 if (rme96->iobase) { 1580 iounmap(rme96->iobase); 1581 rme96->iobase = NULL; 1582 } 1583 if (rme96->port) { 1584 pci_release_regions(rme96->pci); 1585 rme96->port = 0; 1586 } 1587 #ifdef CONFIG_PM_SLEEP 1588 vfree(rme96->playback_suspend_buffer); 1589 vfree(rme96->capture_suspend_buffer); 1590 #endif 1591 pci_disable_device(rme96->pci); 1592 } 1593 1594 static void 1595 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) 1596 { 1597 struct rme96 *rme96 = pcm->private_data; 1598 rme96->spdif_pcm = NULL; 1599 } 1600 1601 static void 1602 snd_rme96_free_adat_pcm(struct snd_pcm *pcm) 1603 { 1604 struct rme96 *rme96 = pcm->private_data; 1605 rme96->adat_pcm = NULL; 1606 } 1607 1608 static int 1609 snd_rme96_create(struct rme96 *rme96) 1610 { 1611 struct pci_dev *pci = rme96->pci; 1612 int err; 1613 1614 rme96->irq = -1; 1615 spin_lock_init(&rme96->lock); 1616 1617 err = pci_enable_device(pci); 1618 if (err < 0) 1619 return err; 1620 1621 err = pci_request_regions(pci, "RME96"); 1622 if (err < 0) 1623 return err; 1624 rme96->port = pci_resource_start(rme96->pci, 0); 1625 1626 rme96->iobase = ioremap(rme96->port, RME96_IO_SIZE); 1627 if (!rme96->iobase) { 1628 dev_err(rme96->card->dev, 1629 "unable to remap memory region 0x%lx-0x%lx\n", 1630 rme96->port, rme96->port + RME96_IO_SIZE - 1); 1631 return -ENOMEM; 1632 } 1633 1634 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED, 1635 KBUILD_MODNAME, rme96)) { 1636 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq); 1637 return -EBUSY; 1638 } 1639 rme96->irq = pci->irq; 1640 rme96->card->sync_irq = rme96->irq; 1641 1642 /* read the card's revision number */ 1643 pci_read_config_byte(pci, 8, &rme96->rev); 1644 1645 /* set up ALSA pcm device for S/PDIF */ 1646 err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1647 1, 1, &rme96->spdif_pcm); 1648 if (err < 0) 1649 return err; 1650 1651 rme96->spdif_pcm->private_data = rme96; 1652 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; 1653 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); 1654 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); 1655 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); 1656 1657 rme96->spdif_pcm->info_flags = 0; 1658 1659 /* set up ALSA pcm device for ADAT */ 1660 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { 1661 /* ADAT is not available on the base model */ 1662 rme96->adat_pcm = NULL; 1663 } else { 1664 err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1665 1, 1, &rme96->adat_pcm); 1666 if (err < 0) 1667 return err; 1668 rme96->adat_pcm->private_data = rme96; 1669 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; 1670 strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); 1671 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); 1672 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); 1673 1674 rme96->adat_pcm->info_flags = 0; 1675 } 1676 1677 rme96->playback_periodsize = 0; 1678 rme96->capture_periodsize = 0; 1679 1680 /* make sure playback/capture is stopped, if by some reason active */ 1681 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1682 1683 /* set default values in registers */ 1684 rme96->wcreg = 1685 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ 1686 RME96_WCR_SEL | /* normal playback */ 1687 RME96_WCR_MASTER | /* set to master clock mode */ 1688 RME96_WCR_INP_0; /* set coaxial input */ 1689 1690 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ 1691 1692 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1693 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1694 1695 /* reset the ADC */ 1696 writel(rme96->areg | RME96_AR_PD2, 1697 rme96->iobase + RME96_IO_ADDITIONAL_REG); 1698 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1699 1700 /* reset and enable the DAC (order is important). */ 1701 snd_rme96_reset_dac(rme96); 1702 rme96->areg |= RME96_AR_DAC_EN; 1703 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1704 1705 /* reset playback and record buffer pointers */ 1706 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1707 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1708 1709 /* reset volume */ 1710 rme96->vol[0] = rme96->vol[1] = 0; 1711 if (RME96_HAS_ANALOG_OUT(rme96)) { 1712 snd_rme96_apply_dac_volume(rme96); 1713 } 1714 1715 /* init switch interface */ 1716 err = snd_rme96_create_switches(rme96->card, rme96); 1717 if (err < 0) 1718 return err; 1719 1720 /* init proc interface */ 1721 snd_rme96_proc_init(rme96); 1722 1723 return 0; 1724 } 1725 1726 /* 1727 * proc interface 1728 */ 1729 1730 static void 1731 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1732 { 1733 int n; 1734 struct rme96 *rme96 = entry->private_data; 1735 1736 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1737 1738 snd_iprintf(buffer, rme96->card->longname); 1739 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); 1740 1741 snd_iprintf(buffer, "\nGeneral settings\n"); 1742 if (rme96->wcreg & RME96_WCR_IDIS) { 1743 snd_iprintf(buffer, " period size: N/A (interrupts " 1744 "disabled)\n"); 1745 } else if (rme96->wcreg & RME96_WCR_ISEL) { 1746 snd_iprintf(buffer, " period size: 2048 bytes\n"); 1747 } else { 1748 snd_iprintf(buffer, " period size: 8192 bytes\n"); 1749 } 1750 snd_iprintf(buffer, "\nInput settings\n"); 1751 switch (snd_rme96_getinputtype(rme96)) { 1752 case RME96_INPUT_OPTICAL: 1753 snd_iprintf(buffer, " input: optical"); 1754 break; 1755 case RME96_INPUT_COAXIAL: 1756 snd_iprintf(buffer, " input: coaxial"); 1757 break; 1758 case RME96_INPUT_INTERNAL: 1759 snd_iprintf(buffer, " input: internal"); 1760 break; 1761 case RME96_INPUT_XLR: 1762 snd_iprintf(buffer, " input: XLR"); 1763 break; 1764 case RME96_INPUT_ANALOG: 1765 snd_iprintf(buffer, " input: analog"); 1766 break; 1767 } 1768 if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1769 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1770 } else { 1771 if (n) { 1772 snd_iprintf(buffer, " (8 channels)\n"); 1773 } else { 1774 snd_iprintf(buffer, " (2 channels)\n"); 1775 } 1776 snd_iprintf(buffer, " sample rate: %d Hz\n", 1777 snd_rme96_capture_getrate(rme96, &n)); 1778 } 1779 if (rme96->wcreg & RME96_WCR_MODE24_2) { 1780 snd_iprintf(buffer, " sample format: 24 bit\n"); 1781 } else { 1782 snd_iprintf(buffer, " sample format: 16 bit\n"); 1783 } 1784 1785 snd_iprintf(buffer, "\nOutput settings\n"); 1786 if (rme96->wcreg & RME96_WCR_SEL) { 1787 snd_iprintf(buffer, " output signal: normal playback\n"); 1788 } else { 1789 snd_iprintf(buffer, " output signal: same as input\n"); 1790 } 1791 snd_iprintf(buffer, " sample rate: %d Hz\n", 1792 snd_rme96_playback_getrate(rme96)); 1793 if (rme96->wcreg & RME96_WCR_MODE24) { 1794 snd_iprintf(buffer, " sample format: 24 bit\n"); 1795 } else { 1796 snd_iprintf(buffer, " sample format: 16 bit\n"); 1797 } 1798 if (rme96->areg & RME96_AR_WSEL) { 1799 snd_iprintf(buffer, " sample clock source: word clock\n"); 1800 } else if (rme96->wcreg & RME96_WCR_MASTER) { 1801 snd_iprintf(buffer, " sample clock source: internal\n"); 1802 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1803 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); 1804 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1805 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); 1806 } else { 1807 snd_iprintf(buffer, " sample clock source: autosync\n"); 1808 } 1809 if (rme96->wcreg & RME96_WCR_PRO) { 1810 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1811 } else { 1812 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1813 } 1814 if (rme96->wcreg & RME96_WCR_EMP) { 1815 snd_iprintf(buffer, " emphasis: on\n"); 1816 } else { 1817 snd_iprintf(buffer, " emphasis: off\n"); 1818 } 1819 if (rme96->wcreg & RME96_WCR_DOLBY) { 1820 snd_iprintf(buffer, " non-audio (dolby): on\n"); 1821 } else { 1822 snd_iprintf(buffer, " non-audio (dolby): off\n"); 1823 } 1824 if (RME96_HAS_ANALOG_IN(rme96)) { 1825 snd_iprintf(buffer, "\nAnalog output settings\n"); 1826 switch (snd_rme96_getmontracks(rme96)) { 1827 case RME96_MONITOR_TRACKS_1_2: 1828 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); 1829 break; 1830 case RME96_MONITOR_TRACKS_3_4: 1831 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); 1832 break; 1833 case RME96_MONITOR_TRACKS_5_6: 1834 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); 1835 break; 1836 case RME96_MONITOR_TRACKS_7_8: 1837 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); 1838 break; 1839 } 1840 switch (snd_rme96_getattenuation(rme96)) { 1841 case RME96_ATTENUATION_0: 1842 snd_iprintf(buffer, " attenuation: 0 dB\n"); 1843 break; 1844 case RME96_ATTENUATION_6: 1845 snd_iprintf(buffer, " attenuation: -6 dB\n"); 1846 break; 1847 case RME96_ATTENUATION_12: 1848 snd_iprintf(buffer, " attenuation: -12 dB\n"); 1849 break; 1850 case RME96_ATTENUATION_18: 1851 snd_iprintf(buffer, " attenuation: -18 dB\n"); 1852 break; 1853 } 1854 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); 1855 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); 1856 } 1857 } 1858 1859 static void snd_rme96_proc_init(struct rme96 *rme96) 1860 { 1861 snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read); 1862 } 1863 1864 /* 1865 * control interface 1866 */ 1867 1868 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info 1869 1870 static int 1871 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1872 { 1873 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1874 1875 spin_lock_irq(&rme96->lock); 1876 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; 1877 spin_unlock_irq(&rme96->lock); 1878 return 0; 1879 } 1880 static int 1881 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1882 { 1883 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1884 unsigned int val; 1885 int change; 1886 1887 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; 1888 spin_lock_irq(&rme96->lock); 1889 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; 1890 change = val != rme96->wcreg; 1891 rme96->wcreg = val; 1892 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1893 spin_unlock_irq(&rme96->lock); 1894 return change; 1895 } 1896 1897 static int 1898 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1899 { 1900 static const char * const _texts[5] = { 1901 "Optical", "Coaxial", "Internal", "XLR", "Analog" 1902 }; 1903 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1904 const char *texts[5] = { 1905 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] 1906 }; 1907 int num_items; 1908 1909 switch (rme96->pci->device) { 1910 case PCI_DEVICE_ID_RME_DIGI96: 1911 case PCI_DEVICE_ID_RME_DIGI96_8: 1912 num_items = 3; 1913 break; 1914 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1915 num_items = 4; 1916 break; 1917 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1918 if (rme96->rev > 4) { 1919 /* PST */ 1920 num_items = 4; 1921 texts[3] = _texts[4]; /* Analog instead of XLR */ 1922 } else { 1923 /* PAD */ 1924 num_items = 5; 1925 } 1926 break; 1927 default: 1928 snd_BUG(); 1929 return -EINVAL; 1930 } 1931 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1932 } 1933 static int 1934 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1935 { 1936 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1937 unsigned int items = 3; 1938 1939 spin_lock_irq(&rme96->lock); 1940 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); 1941 1942 switch (rme96->pci->device) { 1943 case PCI_DEVICE_ID_RME_DIGI96: 1944 case PCI_DEVICE_ID_RME_DIGI96_8: 1945 items = 3; 1946 break; 1947 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1948 items = 4; 1949 break; 1950 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1951 if (rme96->rev > 4) { 1952 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ 1953 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { 1954 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; 1955 } 1956 items = 4; 1957 } else { 1958 items = 5; 1959 } 1960 break; 1961 default: 1962 snd_BUG(); 1963 break; 1964 } 1965 if (ucontrol->value.enumerated.item[0] >= items) { 1966 ucontrol->value.enumerated.item[0] = items - 1; 1967 } 1968 1969 spin_unlock_irq(&rme96->lock); 1970 return 0; 1971 } 1972 static int 1973 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1974 { 1975 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1976 unsigned int val; 1977 int change, items = 3; 1978 1979 switch (rme96->pci->device) { 1980 case PCI_DEVICE_ID_RME_DIGI96: 1981 case PCI_DEVICE_ID_RME_DIGI96_8: 1982 items = 3; 1983 break; 1984 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1985 items = 4; 1986 break; 1987 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1988 if (rme96->rev > 4) { 1989 items = 4; 1990 } else { 1991 items = 5; 1992 } 1993 break; 1994 default: 1995 snd_BUG(); 1996 break; 1997 } 1998 val = ucontrol->value.enumerated.item[0] % items; 1999 2000 /* special case for PST */ 2001 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { 2002 if (val == RME96_INPUT_XLR) { 2003 val = RME96_INPUT_ANALOG; 2004 } 2005 } 2006 2007 spin_lock_irq(&rme96->lock); 2008 change = (int)val != snd_rme96_getinputtype(rme96); 2009 snd_rme96_setinputtype(rme96, val); 2010 spin_unlock_irq(&rme96->lock); 2011 return change; 2012 } 2013 2014 static int 2015 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2016 { 2017 static const char * const texts[3] = { "AutoSync", "Internal", "Word" }; 2018 2019 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2020 } 2021 static int 2022 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2023 { 2024 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2025 2026 spin_lock_irq(&rme96->lock); 2027 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); 2028 spin_unlock_irq(&rme96->lock); 2029 return 0; 2030 } 2031 static int 2032 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2033 { 2034 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2035 unsigned int val; 2036 int change; 2037 2038 val = ucontrol->value.enumerated.item[0] % 3; 2039 spin_lock_irq(&rme96->lock); 2040 change = (int)val != snd_rme96_getclockmode(rme96); 2041 snd_rme96_setclockmode(rme96, val); 2042 spin_unlock_irq(&rme96->lock); 2043 return change; 2044 } 2045 2046 static int 2047 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2048 { 2049 static const char * const texts[4] = { 2050 "0 dB", "-6 dB", "-12 dB", "-18 dB" 2051 }; 2052 2053 return snd_ctl_enum_info(uinfo, 1, 4, texts); 2054 } 2055 static int 2056 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2057 { 2058 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2059 2060 spin_lock_irq(&rme96->lock); 2061 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); 2062 spin_unlock_irq(&rme96->lock); 2063 return 0; 2064 } 2065 static int 2066 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2067 { 2068 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2069 unsigned int val; 2070 int change; 2071 2072 val = ucontrol->value.enumerated.item[0] % 4; 2073 spin_lock_irq(&rme96->lock); 2074 2075 change = (int)val != snd_rme96_getattenuation(rme96); 2076 snd_rme96_setattenuation(rme96, val); 2077 spin_unlock_irq(&rme96->lock); 2078 return change; 2079 } 2080 2081 static int 2082 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2083 { 2084 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" }; 2085 2086 return snd_ctl_enum_info(uinfo, 1, 4, texts); 2087 } 2088 static int 2089 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2090 { 2091 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2092 2093 spin_lock_irq(&rme96->lock); 2094 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); 2095 spin_unlock_irq(&rme96->lock); 2096 return 0; 2097 } 2098 static int 2099 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2100 { 2101 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2102 unsigned int val; 2103 int change; 2104 2105 val = ucontrol->value.enumerated.item[0] % 4; 2106 spin_lock_irq(&rme96->lock); 2107 change = (int)val != snd_rme96_getmontracks(rme96); 2108 snd_rme96_setmontracks(rme96, val); 2109 spin_unlock_irq(&rme96->lock); 2110 return change; 2111 } 2112 2113 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) 2114 { 2115 u32 val = 0; 2116 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; 2117 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; 2118 if (val & RME96_WCR_PRO) 2119 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2120 else 2121 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2122 return val; 2123 } 2124 2125 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 2126 { 2127 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | 2128 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); 2129 if (val & RME96_WCR_PRO) 2130 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 2131 else 2132 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 2133 } 2134 2135 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2136 { 2137 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2138 uinfo->count = 1; 2139 return 0; 2140 } 2141 2142 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2143 { 2144 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2145 2146 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); 2147 return 0; 2148 } 2149 2150 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2151 { 2152 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2153 int change; 2154 u32 val; 2155 2156 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2157 spin_lock_irq(&rme96->lock); 2158 change = val != rme96->wcreg_spdif; 2159 rme96->wcreg_spdif = val; 2160 spin_unlock_irq(&rme96->lock); 2161 return change; 2162 } 2163 2164 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2165 { 2166 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2167 uinfo->count = 1; 2168 return 0; 2169 } 2170 2171 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2172 { 2173 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2174 2175 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); 2176 return 0; 2177 } 2178 2179 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2180 { 2181 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2182 int change; 2183 u32 val; 2184 2185 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2186 spin_lock_irq(&rme96->lock); 2187 change = val != rme96->wcreg_spdif_stream; 2188 rme96->wcreg_spdif_stream = val; 2189 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 2190 rme96->wcreg |= val; 2191 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 2192 spin_unlock_irq(&rme96->lock); 2193 return change; 2194 } 2195 2196 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2197 { 2198 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2199 uinfo->count = 1; 2200 return 0; 2201 } 2202 2203 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2204 { 2205 ucontrol->value.iec958.status[0] = kcontrol->private_value; 2206 return 0; 2207 } 2208 2209 static int 2210 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2211 { 2212 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2213 2214 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2215 uinfo->count = 2; 2216 uinfo->value.integer.min = 0; 2217 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); 2218 return 0; 2219 } 2220 2221 static int 2222 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2223 { 2224 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2225 2226 spin_lock_irq(&rme96->lock); 2227 u->value.integer.value[0] = rme96->vol[0]; 2228 u->value.integer.value[1] = rme96->vol[1]; 2229 spin_unlock_irq(&rme96->lock); 2230 2231 return 0; 2232 } 2233 2234 static int 2235 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2236 { 2237 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2238 int change = 0; 2239 unsigned int vol, maxvol; 2240 2241 2242 if (!RME96_HAS_ANALOG_OUT(rme96)) 2243 return -EINVAL; 2244 maxvol = RME96_185X_MAX_OUT(rme96); 2245 spin_lock_irq(&rme96->lock); 2246 vol = u->value.integer.value[0]; 2247 if (vol != rme96->vol[0] && vol <= maxvol) { 2248 rme96->vol[0] = vol; 2249 change = 1; 2250 } 2251 vol = u->value.integer.value[1]; 2252 if (vol != rme96->vol[1] && vol <= maxvol) { 2253 rme96->vol[1] = vol; 2254 change = 1; 2255 } 2256 if (change) 2257 snd_rme96_apply_dac_volume(rme96); 2258 spin_unlock_irq(&rme96->lock); 2259 2260 return change; 2261 } 2262 2263 static const struct snd_kcontrol_new snd_rme96_controls[] = { 2264 { 2265 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2266 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2267 .info = snd_rme96_control_spdif_info, 2268 .get = snd_rme96_control_spdif_get, 2269 .put = snd_rme96_control_spdif_put 2270 }, 2271 { 2272 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2273 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2274 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2275 .info = snd_rme96_control_spdif_stream_info, 2276 .get = snd_rme96_control_spdif_stream_get, 2277 .put = snd_rme96_control_spdif_stream_put 2278 }, 2279 { 2280 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2281 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2282 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2283 .info = snd_rme96_control_spdif_mask_info, 2284 .get = snd_rme96_control_spdif_mask_get, 2285 .private_value = IEC958_AES0_NONAUDIO | 2286 IEC958_AES0_PROFESSIONAL | 2287 IEC958_AES0_CON_EMPHASIS 2288 }, 2289 { 2290 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2291 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2292 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2293 .info = snd_rme96_control_spdif_mask_info, 2294 .get = snd_rme96_control_spdif_mask_get, 2295 .private_value = IEC958_AES0_NONAUDIO | 2296 IEC958_AES0_PROFESSIONAL | 2297 IEC958_AES0_PRO_EMPHASIS 2298 }, 2299 { 2300 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2301 .name = "Input Connector", 2302 .info = snd_rme96_info_inputtype_control, 2303 .get = snd_rme96_get_inputtype_control, 2304 .put = snd_rme96_put_inputtype_control 2305 }, 2306 { 2307 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2308 .name = "Loopback Input", 2309 .info = snd_rme96_info_loopback_control, 2310 .get = snd_rme96_get_loopback_control, 2311 .put = snd_rme96_put_loopback_control 2312 }, 2313 { 2314 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2315 .name = "Sample Clock Source", 2316 .info = snd_rme96_info_clockmode_control, 2317 .get = snd_rme96_get_clockmode_control, 2318 .put = snd_rme96_put_clockmode_control 2319 }, 2320 { 2321 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2322 .name = "Monitor Tracks", 2323 .info = snd_rme96_info_montracks_control, 2324 .get = snd_rme96_get_montracks_control, 2325 .put = snd_rme96_put_montracks_control 2326 }, 2327 { 2328 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2329 .name = "Attenuation", 2330 .info = snd_rme96_info_attenuation_control, 2331 .get = snd_rme96_get_attenuation_control, 2332 .put = snd_rme96_put_attenuation_control 2333 }, 2334 { 2335 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2336 .name = "DAC Playback Volume", 2337 .info = snd_rme96_dac_volume_info, 2338 .get = snd_rme96_dac_volume_get, 2339 .put = snd_rme96_dac_volume_put 2340 } 2341 }; 2342 2343 static int 2344 snd_rme96_create_switches(struct snd_card *card, 2345 struct rme96 *rme96) 2346 { 2347 int idx, err; 2348 struct snd_kcontrol *kctl; 2349 2350 for (idx = 0; idx < 7; idx++) { 2351 kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96); 2352 err = snd_ctl_add(card, kctl); 2353 if (err < 0) 2354 return err; 2355 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 2356 rme96->spdif_ctl = kctl; 2357 } 2358 2359 if (RME96_HAS_ANALOG_OUT(rme96)) { 2360 for (idx = 7; idx < 10; idx++) { 2361 err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96)); 2362 if (err < 0) 2363 return err; 2364 } 2365 } 2366 2367 return 0; 2368 } 2369 2370 /* 2371 * Card initialisation 2372 */ 2373 2374 #ifdef CONFIG_PM_SLEEP 2375 2376 static int rme96_suspend(struct device *dev) 2377 { 2378 struct snd_card *card = dev_get_drvdata(dev); 2379 struct rme96 *rme96 = card->private_data; 2380 2381 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2382 2383 /* save capture & playback pointers */ 2384 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 2385 & RME96_RCR_AUDIO_ADDR_MASK; 2386 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS) 2387 & RME96_RCR_AUDIO_ADDR_MASK; 2388 2389 /* save playback and capture buffers */ 2390 memcpy_fromio(rme96->playback_suspend_buffer, 2391 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); 2392 memcpy_fromio(rme96->capture_suspend_buffer, 2393 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); 2394 2395 /* disable the DAC */ 2396 rme96->areg &= ~RME96_AR_DAC_EN; 2397 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2398 return 0; 2399 } 2400 2401 static int rme96_resume(struct device *dev) 2402 { 2403 struct snd_card *card = dev_get_drvdata(dev); 2404 struct rme96 *rme96 = card->private_data; 2405 2406 /* reset playback and record buffer pointers */ 2407 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS 2408 + rme96->playback_pointer); 2409 writel(0, rme96->iobase + RME96_IO_SET_REC_POS 2410 + rme96->capture_pointer); 2411 2412 /* restore playback and capture buffers */ 2413 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, 2414 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); 2415 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, 2416 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); 2417 2418 /* reset the ADC */ 2419 writel(rme96->areg | RME96_AR_PD2, 2420 rme96->iobase + RME96_IO_ADDITIONAL_REG); 2421 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2422 2423 /* reset and enable DAC, restore analog volume */ 2424 snd_rme96_reset_dac(rme96); 2425 rme96->areg |= RME96_AR_DAC_EN; 2426 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2427 if (RME96_HAS_ANALOG_OUT(rme96)) { 2428 usleep_range(3000, 10000); 2429 snd_rme96_apply_dac_volume(rme96); 2430 } 2431 2432 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2433 2434 return 0; 2435 } 2436 2437 static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume); 2438 #define RME96_PM_OPS &rme96_pm 2439 #else 2440 #define RME96_PM_OPS NULL 2441 #endif /* CONFIG_PM_SLEEP */ 2442 2443 static void snd_rme96_card_free(struct snd_card *card) 2444 { 2445 snd_rme96_free(card->private_data); 2446 } 2447 2448 static int 2449 snd_rme96_probe(struct pci_dev *pci, 2450 const struct pci_device_id *pci_id) 2451 { 2452 static int dev; 2453 struct rme96 *rme96; 2454 struct snd_card *card; 2455 int err; 2456 u8 val; 2457 2458 if (dev >= SNDRV_CARDS) { 2459 return -ENODEV; 2460 } 2461 if (!enable[dev]) { 2462 dev++; 2463 return -ENOENT; 2464 } 2465 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2466 sizeof(struct rme96), &card); 2467 if (err < 0) 2468 return err; 2469 card->private_free = snd_rme96_card_free; 2470 rme96 = card->private_data; 2471 rme96->card = card; 2472 rme96->pci = pci; 2473 err = snd_rme96_create(rme96); 2474 if (err) 2475 goto free_card; 2476 2477 #ifdef CONFIG_PM_SLEEP 2478 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2479 if (!rme96->playback_suspend_buffer) { 2480 err = -ENOMEM; 2481 goto free_card; 2482 } 2483 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2484 if (!rme96->capture_suspend_buffer) { 2485 err = -ENOMEM; 2486 goto free_card; 2487 } 2488 #endif 2489 2490 strcpy(card->driver, "Digi96"); 2491 switch (rme96->pci->device) { 2492 case PCI_DEVICE_ID_RME_DIGI96: 2493 strcpy(card->shortname, "RME Digi96"); 2494 break; 2495 case PCI_DEVICE_ID_RME_DIGI96_8: 2496 strcpy(card->shortname, "RME Digi96/8"); 2497 break; 2498 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 2499 strcpy(card->shortname, "RME Digi96/8 PRO"); 2500 break; 2501 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 2502 pci_read_config_byte(rme96->pci, 8, &val); 2503 if (val < 5) { 2504 strcpy(card->shortname, "RME Digi96/8 PAD"); 2505 } else { 2506 strcpy(card->shortname, "RME Digi96/8 PST"); 2507 } 2508 break; 2509 } 2510 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, 2511 rme96->port, rme96->irq); 2512 err = snd_card_register(card); 2513 if (err) 2514 goto free_card; 2515 2516 pci_set_drvdata(pci, card); 2517 dev++; 2518 return 0; 2519 free_card: 2520 snd_card_free(card); 2521 return err; 2522 } 2523 2524 static void snd_rme96_remove(struct pci_dev *pci) 2525 { 2526 snd_card_free(pci_get_drvdata(pci)); 2527 } 2528 2529 static struct pci_driver rme96_driver = { 2530 .name = KBUILD_MODNAME, 2531 .id_table = snd_rme96_ids, 2532 .probe = snd_rme96_probe, 2533 .remove = snd_rme96_remove, 2534 .driver = { 2535 .pm = RME96_PM_OPS, 2536 }, 2537 }; 2538 2539 module_pci_driver(rme96_driver); 2540