1 /* 2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio 3 * interfaces 4 * 5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se> 6 * 7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control 8 * code. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <linux/delay.h> 27 #include <linux/init.h> 28 #include <linux/interrupt.h> 29 #include <linux/pci.h> 30 #include <linux/module.h> 31 #include <linux/vmalloc.h> 32 33 #include <sound/core.h> 34 #include <sound/info.h> 35 #include <sound/control.h> 36 #include <sound/pcm.h> 37 #include <sound/pcm_params.h> 38 #include <sound/asoundef.h> 39 #include <sound/initval.h> 40 41 #include <asm/io.h> 42 43 /* note, two last pcis should be equal, it is not a bug */ 44 45 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>"); 46 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, " 47 "Digi96/8 PAD"); 48 MODULE_LICENSE("GPL"); 49 MODULE_SUPPORTED_DEVICE("{{RME,Digi96}," 50 "{RME,Digi96/8}," 51 "{RME,Digi96/8 PRO}," 52 "{RME,Digi96/8 PST}," 53 "{RME,Digi96/8 PAD}}"); 54 55 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 56 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 57 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 58 59 module_param_array(index, int, NULL, 0444); 60 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard."); 61 module_param_array(id, charp, NULL, 0444); 62 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard."); 63 module_param_array(enable, bool, NULL, 0444); 64 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard."); 65 66 /* 67 * Defines for RME Digi96 series, from internal RME reference documents 68 * dated 12.01.00 69 */ 70 71 #define RME96_SPDIF_NCHANNELS 2 72 73 /* Playback and capture buffer size */ 74 #define RME96_BUFFER_SIZE 0x10000 75 76 /* IO area size */ 77 #define RME96_IO_SIZE 0x60000 78 79 /* IO area offsets */ 80 #define RME96_IO_PLAY_BUFFER 0x0 81 #define RME96_IO_REC_BUFFER 0x10000 82 #define RME96_IO_CONTROL_REGISTER 0x20000 83 #define RME96_IO_ADDITIONAL_REG 0x20004 84 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008 85 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C 86 #define RME96_IO_SET_PLAY_POS 0x40000 87 #define RME96_IO_RESET_PLAY_POS 0x4FFFC 88 #define RME96_IO_SET_REC_POS 0x50000 89 #define RME96_IO_RESET_REC_POS 0x5FFFC 90 #define RME96_IO_GET_PLAY_POS 0x20000 91 #define RME96_IO_GET_REC_POS 0x30000 92 93 /* Write control register bits */ 94 #define RME96_WCR_START (1 << 0) 95 #define RME96_WCR_START_2 (1 << 1) 96 #define RME96_WCR_GAIN_0 (1 << 2) 97 #define RME96_WCR_GAIN_1 (1 << 3) 98 #define RME96_WCR_MODE24 (1 << 4) 99 #define RME96_WCR_MODE24_2 (1 << 5) 100 #define RME96_WCR_BM (1 << 6) 101 #define RME96_WCR_BM_2 (1 << 7) 102 #define RME96_WCR_ADAT (1 << 8) 103 #define RME96_WCR_FREQ_0 (1 << 9) 104 #define RME96_WCR_FREQ_1 (1 << 10) 105 #define RME96_WCR_DS (1 << 11) 106 #define RME96_WCR_PRO (1 << 12) 107 #define RME96_WCR_EMP (1 << 13) 108 #define RME96_WCR_SEL (1 << 14) 109 #define RME96_WCR_MASTER (1 << 15) 110 #define RME96_WCR_PD (1 << 16) 111 #define RME96_WCR_INP_0 (1 << 17) 112 #define RME96_WCR_INP_1 (1 << 18) 113 #define RME96_WCR_THRU_0 (1 << 19) 114 #define RME96_WCR_THRU_1 (1 << 20) 115 #define RME96_WCR_THRU_2 (1 << 21) 116 #define RME96_WCR_THRU_3 (1 << 22) 117 #define RME96_WCR_THRU_4 (1 << 23) 118 #define RME96_WCR_THRU_5 (1 << 24) 119 #define RME96_WCR_THRU_6 (1 << 25) 120 #define RME96_WCR_THRU_7 (1 << 26) 121 #define RME96_WCR_DOLBY (1 << 27) 122 #define RME96_WCR_MONITOR_0 (1 << 28) 123 #define RME96_WCR_MONITOR_1 (1 << 29) 124 #define RME96_WCR_ISEL (1 << 30) 125 #define RME96_WCR_IDIS (1 << 31) 126 127 #define RME96_WCR_BITPOS_GAIN_0 2 128 #define RME96_WCR_BITPOS_GAIN_1 3 129 #define RME96_WCR_BITPOS_FREQ_0 9 130 #define RME96_WCR_BITPOS_FREQ_1 10 131 #define RME96_WCR_BITPOS_INP_0 17 132 #define RME96_WCR_BITPOS_INP_1 18 133 #define RME96_WCR_BITPOS_MONITOR_0 28 134 #define RME96_WCR_BITPOS_MONITOR_1 29 135 136 /* Read control register bits */ 137 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF 138 #define RME96_RCR_IRQ_2 (1 << 16) 139 #define RME96_RCR_T_OUT (1 << 17) 140 #define RME96_RCR_DEV_ID_0 (1 << 21) 141 #define RME96_RCR_DEV_ID_1 (1 << 22) 142 #define RME96_RCR_LOCK (1 << 23) 143 #define RME96_RCR_VERF (1 << 26) 144 #define RME96_RCR_F0 (1 << 27) 145 #define RME96_RCR_F1 (1 << 28) 146 #define RME96_RCR_F2 (1 << 29) 147 #define RME96_RCR_AUTOSYNC (1 << 30) 148 #define RME96_RCR_IRQ (1 << 31) 149 150 #define RME96_RCR_BITPOS_F0 27 151 #define RME96_RCR_BITPOS_F1 28 152 #define RME96_RCR_BITPOS_F2 29 153 154 /* Additional register bits */ 155 #define RME96_AR_WSEL (1 << 0) 156 #define RME96_AR_ANALOG (1 << 1) 157 #define RME96_AR_FREQPAD_0 (1 << 2) 158 #define RME96_AR_FREQPAD_1 (1 << 3) 159 #define RME96_AR_FREQPAD_2 (1 << 4) 160 #define RME96_AR_PD2 (1 << 5) 161 #define RME96_AR_DAC_EN (1 << 6) 162 #define RME96_AR_CLATCH (1 << 7) 163 #define RME96_AR_CCLK (1 << 8) 164 #define RME96_AR_CDATA (1 << 9) 165 166 #define RME96_AR_BITPOS_F0 2 167 #define RME96_AR_BITPOS_F1 3 168 #define RME96_AR_BITPOS_F2 4 169 170 /* Monitor tracks */ 171 #define RME96_MONITOR_TRACKS_1_2 0 172 #define RME96_MONITOR_TRACKS_3_4 1 173 #define RME96_MONITOR_TRACKS_5_6 2 174 #define RME96_MONITOR_TRACKS_7_8 3 175 176 /* Attenuation */ 177 #define RME96_ATTENUATION_0 0 178 #define RME96_ATTENUATION_6 1 179 #define RME96_ATTENUATION_12 2 180 #define RME96_ATTENUATION_18 3 181 182 /* Input types */ 183 #define RME96_INPUT_OPTICAL 0 184 #define RME96_INPUT_COAXIAL 1 185 #define RME96_INPUT_INTERNAL 2 186 #define RME96_INPUT_XLR 3 187 #define RME96_INPUT_ANALOG 4 188 189 /* Clock modes */ 190 #define RME96_CLOCKMODE_SLAVE 0 191 #define RME96_CLOCKMODE_MASTER 1 192 #define RME96_CLOCKMODE_WORDCLOCK 2 193 194 /* Block sizes in bytes */ 195 #define RME96_SMALL_BLOCK_SIZE 2048 196 #define RME96_LARGE_BLOCK_SIZE 8192 197 198 /* Volume control */ 199 #define RME96_AD1852_VOL_BITS 14 200 #define RME96_AD1855_VOL_BITS 10 201 202 /* Defines for snd_rme96_trigger */ 203 #define RME96_TB_START_PLAYBACK 1 204 #define RME96_TB_START_CAPTURE 2 205 #define RME96_TB_STOP_PLAYBACK 4 206 #define RME96_TB_STOP_CAPTURE 8 207 #define RME96_TB_RESET_PLAYPOS 16 208 #define RME96_TB_RESET_CAPTUREPOS 32 209 #define RME96_TB_CLEAR_PLAYBACK_IRQ 64 210 #define RME96_TB_CLEAR_CAPTURE_IRQ 128 211 #define RME96_RESUME_PLAYBACK (RME96_TB_START_PLAYBACK) 212 #define RME96_RESUME_CAPTURE (RME96_TB_START_CAPTURE) 213 #define RME96_RESUME_BOTH (RME96_RESUME_PLAYBACK \ 214 | RME96_RESUME_CAPTURE) 215 #define RME96_START_PLAYBACK (RME96_TB_START_PLAYBACK \ 216 | RME96_TB_RESET_PLAYPOS) 217 #define RME96_START_CAPTURE (RME96_TB_START_CAPTURE \ 218 | RME96_TB_RESET_CAPTUREPOS) 219 #define RME96_START_BOTH (RME96_START_PLAYBACK \ 220 | RME96_START_CAPTURE) 221 #define RME96_STOP_PLAYBACK (RME96_TB_STOP_PLAYBACK \ 222 | RME96_TB_CLEAR_PLAYBACK_IRQ) 223 #define RME96_STOP_CAPTURE (RME96_TB_STOP_CAPTURE \ 224 | RME96_TB_CLEAR_CAPTURE_IRQ) 225 #define RME96_STOP_BOTH (RME96_STOP_PLAYBACK \ 226 | RME96_STOP_CAPTURE) 227 228 struct rme96 { 229 spinlock_t lock; 230 int irq; 231 unsigned long port; 232 void __iomem *iobase; 233 234 u32 wcreg; /* cached write control register value */ 235 u32 wcreg_spdif; /* S/PDIF setup */ 236 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 237 u32 rcreg; /* cached read control register value */ 238 u32 areg; /* cached additional register value */ 239 u16 vol[2]; /* cached volume of analog output */ 240 241 u8 rev; /* card revision number */ 242 243 #ifdef CONFIG_PM_SLEEP 244 u32 playback_pointer; 245 u32 capture_pointer; 246 void *playback_suspend_buffer; 247 void *capture_suspend_buffer; 248 #endif 249 250 struct snd_pcm_substream *playback_substream; 251 struct snd_pcm_substream *capture_substream; 252 253 int playback_frlog; /* log2 of framesize */ 254 int capture_frlog; 255 256 size_t playback_periodsize; /* in bytes, zero if not used */ 257 size_t capture_periodsize; /* in bytes, zero if not used */ 258 259 struct snd_card *card; 260 struct snd_pcm *spdif_pcm; 261 struct snd_pcm *adat_pcm; 262 struct pci_dev *pci; 263 struct snd_kcontrol *spdif_ctl; 264 }; 265 266 static const struct pci_device_id snd_rme96_ids[] = { 267 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96), 0, }, 268 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8), 0, }, 269 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO), 0, }, 270 { PCI_VDEVICE(XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST), 0, }, 271 { 0, } 272 }; 273 274 MODULE_DEVICE_TABLE(pci, snd_rme96_ids); 275 276 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START) 277 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2) 278 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 279 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \ 280 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST) 281 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4) 282 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \ 283 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2)) 284 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1) 285 286 static int 287 snd_rme96_playback_prepare(struct snd_pcm_substream *substream); 288 289 static int 290 snd_rme96_capture_prepare(struct snd_pcm_substream *substream); 291 292 static int 293 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 294 int cmd); 295 296 static int 297 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 298 int cmd); 299 300 static snd_pcm_uframes_t 301 snd_rme96_playback_pointer(struct snd_pcm_substream *substream); 302 303 static snd_pcm_uframes_t 304 snd_rme96_capture_pointer(struct snd_pcm_substream *substream); 305 306 static void snd_rme96_proc_init(struct rme96 *rme96); 307 308 static int 309 snd_rme96_create_switches(struct snd_card *card, 310 struct rme96 *rme96); 311 312 static int 313 snd_rme96_getinputtype(struct rme96 *rme96); 314 315 static inline unsigned int 316 snd_rme96_playback_ptr(struct rme96 *rme96) 317 { 318 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 319 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog; 320 } 321 322 static inline unsigned int 323 snd_rme96_capture_ptr(struct rme96 *rme96) 324 { 325 return (readl(rme96->iobase + RME96_IO_GET_REC_POS) 326 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog; 327 } 328 329 static int 330 snd_rme96_playback_silence(struct snd_pcm_substream *substream, 331 int channel, /* not used (interleaved data) */ 332 snd_pcm_uframes_t pos, 333 snd_pcm_uframes_t count) 334 { 335 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 336 count <<= rme96->playback_frlog; 337 pos <<= rme96->playback_frlog; 338 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, 339 0, count); 340 return 0; 341 } 342 343 static int 344 snd_rme96_playback_copy(struct snd_pcm_substream *substream, 345 int channel, /* not used (interleaved data) */ 346 snd_pcm_uframes_t pos, 347 void __user *src, 348 snd_pcm_uframes_t count) 349 { 350 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 351 count <<= rme96->playback_frlog; 352 pos <<= rme96->playback_frlog; 353 return copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src, 354 count); 355 } 356 357 static int 358 snd_rme96_capture_copy(struct snd_pcm_substream *substream, 359 int channel, /* not used (interleaved data) */ 360 snd_pcm_uframes_t pos, 361 void __user *dst, 362 snd_pcm_uframes_t count) 363 { 364 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 365 count <<= rme96->capture_frlog; 366 pos <<= rme96->capture_frlog; 367 return copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos, 368 count); 369 } 370 371 /* 372 * Digital output capabilities (S/PDIF) 373 */ 374 static struct snd_pcm_hardware snd_rme96_playback_spdif_info = 375 { 376 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 377 SNDRV_PCM_INFO_MMAP_VALID | 378 SNDRV_PCM_INFO_SYNC_START | 379 SNDRV_PCM_INFO_RESUME | 380 SNDRV_PCM_INFO_INTERLEAVED | 381 SNDRV_PCM_INFO_PAUSE), 382 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 383 SNDRV_PCM_FMTBIT_S32_LE), 384 .rates = (SNDRV_PCM_RATE_32000 | 385 SNDRV_PCM_RATE_44100 | 386 SNDRV_PCM_RATE_48000 | 387 SNDRV_PCM_RATE_64000 | 388 SNDRV_PCM_RATE_88200 | 389 SNDRV_PCM_RATE_96000), 390 .rate_min = 32000, 391 .rate_max = 96000, 392 .channels_min = 2, 393 .channels_max = 2, 394 .buffer_bytes_max = RME96_BUFFER_SIZE, 395 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 396 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 397 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 398 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 399 .fifo_size = 0, 400 }; 401 402 /* 403 * Digital input capabilities (S/PDIF) 404 */ 405 static struct snd_pcm_hardware snd_rme96_capture_spdif_info = 406 { 407 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 408 SNDRV_PCM_INFO_MMAP_VALID | 409 SNDRV_PCM_INFO_SYNC_START | 410 SNDRV_PCM_INFO_RESUME | 411 SNDRV_PCM_INFO_INTERLEAVED | 412 SNDRV_PCM_INFO_PAUSE), 413 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 414 SNDRV_PCM_FMTBIT_S32_LE), 415 .rates = (SNDRV_PCM_RATE_32000 | 416 SNDRV_PCM_RATE_44100 | 417 SNDRV_PCM_RATE_48000 | 418 SNDRV_PCM_RATE_64000 | 419 SNDRV_PCM_RATE_88200 | 420 SNDRV_PCM_RATE_96000), 421 .rate_min = 32000, 422 .rate_max = 96000, 423 .channels_min = 2, 424 .channels_max = 2, 425 .buffer_bytes_max = RME96_BUFFER_SIZE, 426 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 427 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 428 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 429 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 430 .fifo_size = 0, 431 }; 432 433 /* 434 * Digital output capabilities (ADAT) 435 */ 436 static struct snd_pcm_hardware snd_rme96_playback_adat_info = 437 { 438 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 439 SNDRV_PCM_INFO_MMAP_VALID | 440 SNDRV_PCM_INFO_SYNC_START | 441 SNDRV_PCM_INFO_RESUME | 442 SNDRV_PCM_INFO_INTERLEAVED | 443 SNDRV_PCM_INFO_PAUSE), 444 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 445 SNDRV_PCM_FMTBIT_S32_LE), 446 .rates = (SNDRV_PCM_RATE_44100 | 447 SNDRV_PCM_RATE_48000), 448 .rate_min = 44100, 449 .rate_max = 48000, 450 .channels_min = 8, 451 .channels_max = 8, 452 .buffer_bytes_max = RME96_BUFFER_SIZE, 453 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 454 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 455 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 456 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 457 .fifo_size = 0, 458 }; 459 460 /* 461 * Digital input capabilities (ADAT) 462 */ 463 static struct snd_pcm_hardware snd_rme96_capture_adat_info = 464 { 465 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 466 SNDRV_PCM_INFO_MMAP_VALID | 467 SNDRV_PCM_INFO_SYNC_START | 468 SNDRV_PCM_INFO_RESUME | 469 SNDRV_PCM_INFO_INTERLEAVED | 470 SNDRV_PCM_INFO_PAUSE), 471 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 472 SNDRV_PCM_FMTBIT_S32_LE), 473 .rates = (SNDRV_PCM_RATE_44100 | 474 SNDRV_PCM_RATE_48000), 475 .rate_min = 44100, 476 .rate_max = 48000, 477 .channels_min = 8, 478 .channels_max = 8, 479 .buffer_bytes_max = RME96_BUFFER_SIZE, 480 .period_bytes_min = RME96_SMALL_BLOCK_SIZE, 481 .period_bytes_max = RME96_LARGE_BLOCK_SIZE, 482 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE, 483 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE, 484 .fifo_size = 0, 485 }; 486 487 /* 488 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface 489 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up 490 * on the falling edge of CCLK and be stable on the rising edge. The rising 491 * edge of CLATCH after the last data bit clocks in the whole data word. 492 * A fast processor could probably drive the SPI interface faster than the 493 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1) 494 * limits the data rate to 500KHz and only causes a delay of 33 microsecs. 495 * 496 * NOTE: increased delay from 1 to 10, since there where problems setting 497 * the volume. 498 */ 499 static void 500 snd_rme96_write_SPI(struct rme96 *rme96, u16 val) 501 { 502 int i; 503 504 for (i = 0; i < 16; i++) { 505 if (val & 0x8000) { 506 rme96->areg |= RME96_AR_CDATA; 507 } else { 508 rme96->areg &= ~RME96_AR_CDATA; 509 } 510 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH); 511 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 512 udelay(10); 513 rme96->areg |= RME96_AR_CCLK; 514 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 515 udelay(10); 516 val <<= 1; 517 } 518 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA); 519 rme96->areg |= RME96_AR_CLATCH; 520 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 521 udelay(10); 522 rme96->areg &= ~RME96_AR_CLATCH; 523 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 524 } 525 526 static void 527 snd_rme96_apply_dac_volume(struct rme96 *rme96) 528 { 529 if (RME96_DAC_IS_1852(rme96)) { 530 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0); 531 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2); 532 } else if (RME96_DAC_IS_1855(rme96)) { 533 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000); 534 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400); 535 } 536 } 537 538 static void 539 snd_rme96_reset_dac(struct rme96 *rme96) 540 { 541 writel(rme96->wcreg | RME96_WCR_PD, 542 rme96->iobase + RME96_IO_CONTROL_REGISTER); 543 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 544 } 545 546 static int 547 snd_rme96_getmontracks(struct rme96 *rme96) 548 { 549 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) + 550 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1); 551 } 552 553 static int 554 snd_rme96_setmontracks(struct rme96 *rme96, 555 int montracks) 556 { 557 if (montracks & 1) { 558 rme96->wcreg |= RME96_WCR_MONITOR_0; 559 } else { 560 rme96->wcreg &= ~RME96_WCR_MONITOR_0; 561 } 562 if (montracks & 2) { 563 rme96->wcreg |= RME96_WCR_MONITOR_1; 564 } else { 565 rme96->wcreg &= ~RME96_WCR_MONITOR_1; 566 } 567 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 568 return 0; 569 } 570 571 static int 572 snd_rme96_getattenuation(struct rme96 *rme96) 573 { 574 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) + 575 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1); 576 } 577 578 static int 579 snd_rme96_setattenuation(struct rme96 *rme96, 580 int attenuation) 581 { 582 switch (attenuation) { 583 case 0: 584 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) & 585 ~RME96_WCR_GAIN_1; 586 break; 587 case 1: 588 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) & 589 ~RME96_WCR_GAIN_1; 590 break; 591 case 2: 592 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) | 593 RME96_WCR_GAIN_1; 594 break; 595 case 3: 596 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) | 597 RME96_WCR_GAIN_1; 598 break; 599 default: 600 return -EINVAL; 601 } 602 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 603 return 0; 604 } 605 606 static int 607 snd_rme96_capture_getrate(struct rme96 *rme96, 608 int *is_adat) 609 { 610 int n, rate; 611 612 *is_adat = 0; 613 if (rme96->areg & RME96_AR_ANALOG) { 614 /* Analog input, overrides S/PDIF setting */ 615 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) + 616 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1); 617 switch (n) { 618 case 1: 619 rate = 32000; 620 break; 621 case 2: 622 rate = 44100; 623 break; 624 case 3: 625 rate = 48000; 626 break; 627 default: 628 return -1; 629 } 630 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate; 631 } 632 633 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 634 if (rme96->rcreg & RME96_RCR_LOCK) { 635 /* ADAT rate */ 636 *is_adat = 1; 637 if (rme96->rcreg & RME96_RCR_T_OUT) { 638 return 48000; 639 } 640 return 44100; 641 } 642 643 if (rme96->rcreg & RME96_RCR_VERF) { 644 return -1; 645 } 646 647 /* S/PDIF rate */ 648 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) + 649 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) + 650 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2); 651 652 switch (n) { 653 case 0: 654 if (rme96->rcreg & RME96_RCR_T_OUT) { 655 return 64000; 656 } 657 return -1; 658 case 3: return 96000; 659 case 4: return 88200; 660 case 5: return 48000; 661 case 6: return 44100; 662 case 7: return 32000; 663 default: 664 break; 665 } 666 return -1; 667 } 668 669 static int 670 snd_rme96_playback_getrate(struct rme96 *rme96) 671 { 672 int rate, dummy; 673 674 if (!(rme96->wcreg & RME96_WCR_MASTER) && 675 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 676 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 677 { 678 /* slave clock */ 679 return rate; 680 } 681 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) + 682 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1); 683 switch (rate) { 684 case 1: 685 rate = 32000; 686 break; 687 case 2: 688 rate = 44100; 689 break; 690 case 3: 691 rate = 48000; 692 break; 693 default: 694 return -1; 695 } 696 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate; 697 } 698 699 static int 700 snd_rme96_playback_setrate(struct rme96 *rme96, 701 int rate) 702 { 703 int ds; 704 705 ds = rme96->wcreg & RME96_WCR_DS; 706 switch (rate) { 707 case 32000: 708 rme96->wcreg &= ~RME96_WCR_DS; 709 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 710 ~RME96_WCR_FREQ_1; 711 break; 712 case 44100: 713 rme96->wcreg &= ~RME96_WCR_DS; 714 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 715 ~RME96_WCR_FREQ_0; 716 break; 717 case 48000: 718 rme96->wcreg &= ~RME96_WCR_DS; 719 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 720 RME96_WCR_FREQ_1; 721 break; 722 case 64000: 723 rme96->wcreg |= RME96_WCR_DS; 724 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) & 725 ~RME96_WCR_FREQ_1; 726 break; 727 case 88200: 728 rme96->wcreg |= RME96_WCR_DS; 729 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) & 730 ~RME96_WCR_FREQ_0; 731 break; 732 case 96000: 733 rme96->wcreg |= RME96_WCR_DS; 734 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) | 735 RME96_WCR_FREQ_1; 736 break; 737 default: 738 return -EINVAL; 739 } 740 if ((!ds && rme96->wcreg & RME96_WCR_DS) || 741 (ds && !(rme96->wcreg & RME96_WCR_DS))) 742 { 743 /* change to/from double-speed: reset the DAC (if available) */ 744 snd_rme96_reset_dac(rme96); 745 } else { 746 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 747 } 748 return 0; 749 } 750 751 static int 752 snd_rme96_capture_analog_setrate(struct rme96 *rme96, 753 int rate) 754 { 755 switch (rate) { 756 case 32000: 757 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 758 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 759 break; 760 case 44100: 761 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 762 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 763 break; 764 case 48000: 765 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 766 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2; 767 break; 768 case 64000: 769 if (rme96->rev < 4) { 770 return -EINVAL; 771 } 772 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) & 773 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 774 break; 775 case 88200: 776 if (rme96->rev < 4) { 777 return -EINVAL; 778 } 779 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) | 780 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 781 break; 782 case 96000: 783 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) | 784 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2; 785 break; 786 default: 787 return -EINVAL; 788 } 789 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 790 return 0; 791 } 792 793 static int 794 snd_rme96_setclockmode(struct rme96 *rme96, 795 int mode) 796 { 797 switch (mode) { 798 case RME96_CLOCKMODE_SLAVE: 799 /* AutoSync */ 800 rme96->wcreg &= ~RME96_WCR_MASTER; 801 rme96->areg &= ~RME96_AR_WSEL; 802 break; 803 case RME96_CLOCKMODE_MASTER: 804 /* Internal */ 805 rme96->wcreg |= RME96_WCR_MASTER; 806 rme96->areg &= ~RME96_AR_WSEL; 807 break; 808 case RME96_CLOCKMODE_WORDCLOCK: 809 /* Word clock is a master mode */ 810 rme96->wcreg |= RME96_WCR_MASTER; 811 rme96->areg |= RME96_AR_WSEL; 812 break; 813 default: 814 return -EINVAL; 815 } 816 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 817 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 818 return 0; 819 } 820 821 static int 822 snd_rme96_getclockmode(struct rme96 *rme96) 823 { 824 if (rme96->areg & RME96_AR_WSEL) { 825 return RME96_CLOCKMODE_WORDCLOCK; 826 } 827 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER : 828 RME96_CLOCKMODE_SLAVE; 829 } 830 831 static int 832 snd_rme96_setinputtype(struct rme96 *rme96, 833 int type) 834 { 835 int n; 836 837 switch (type) { 838 case RME96_INPUT_OPTICAL: 839 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) & 840 ~RME96_WCR_INP_1; 841 break; 842 case RME96_INPUT_COAXIAL: 843 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) & 844 ~RME96_WCR_INP_1; 845 break; 846 case RME96_INPUT_INTERNAL: 847 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) | 848 RME96_WCR_INP_1; 849 break; 850 case RME96_INPUT_XLR: 851 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 852 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) || 853 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && 854 rme96->rev > 4)) 855 { 856 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */ 857 return -EINVAL; 858 } 859 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) | 860 RME96_WCR_INP_1; 861 break; 862 case RME96_INPUT_ANALOG: 863 if (!RME96_HAS_ANALOG_IN(rme96)) { 864 return -EINVAL; 865 } 866 rme96->areg |= RME96_AR_ANALOG; 867 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 868 if (rme96->rev < 4) { 869 /* 870 * Revision less than 004 does not support 64 and 871 * 88.2 kHz 872 */ 873 if (snd_rme96_capture_getrate(rme96, &n) == 88200) { 874 snd_rme96_capture_analog_setrate(rme96, 44100); 875 } 876 if (snd_rme96_capture_getrate(rme96, &n) == 64000) { 877 snd_rme96_capture_analog_setrate(rme96, 32000); 878 } 879 } 880 return 0; 881 default: 882 return -EINVAL; 883 } 884 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) { 885 rme96->areg &= ~RME96_AR_ANALOG; 886 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 887 } 888 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 889 return 0; 890 } 891 892 static int 893 snd_rme96_getinputtype(struct rme96 *rme96) 894 { 895 if (rme96->areg & RME96_AR_ANALOG) { 896 return RME96_INPUT_ANALOG; 897 } 898 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) + 899 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1); 900 } 901 902 static void 903 snd_rme96_setframelog(struct rme96 *rme96, 904 int n_channels, 905 int is_playback) 906 { 907 int frlog; 908 909 if (n_channels == 2) { 910 frlog = 1; 911 } else { 912 /* assume 8 channels */ 913 frlog = 3; 914 } 915 if (is_playback) { 916 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1; 917 rme96->playback_frlog = frlog; 918 } else { 919 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1; 920 rme96->capture_frlog = frlog; 921 } 922 } 923 924 static int 925 snd_rme96_playback_setformat(struct rme96 *rme96, snd_pcm_format_t format) 926 { 927 switch (format) { 928 case SNDRV_PCM_FORMAT_S16_LE: 929 rme96->wcreg &= ~RME96_WCR_MODE24; 930 break; 931 case SNDRV_PCM_FORMAT_S32_LE: 932 rme96->wcreg |= RME96_WCR_MODE24; 933 break; 934 default: 935 return -EINVAL; 936 } 937 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 938 return 0; 939 } 940 941 static int 942 snd_rme96_capture_setformat(struct rme96 *rme96, snd_pcm_format_t format) 943 { 944 switch (format) { 945 case SNDRV_PCM_FORMAT_S16_LE: 946 rme96->wcreg &= ~RME96_WCR_MODE24_2; 947 break; 948 case SNDRV_PCM_FORMAT_S32_LE: 949 rme96->wcreg |= RME96_WCR_MODE24_2; 950 break; 951 default: 952 return -EINVAL; 953 } 954 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 955 return 0; 956 } 957 958 static void 959 snd_rme96_set_period_properties(struct rme96 *rme96, 960 size_t period_bytes) 961 { 962 switch (period_bytes) { 963 case RME96_LARGE_BLOCK_SIZE: 964 rme96->wcreg &= ~RME96_WCR_ISEL; 965 break; 966 case RME96_SMALL_BLOCK_SIZE: 967 rme96->wcreg |= RME96_WCR_ISEL; 968 break; 969 default: 970 snd_BUG(); 971 break; 972 } 973 rme96->wcreg &= ~RME96_WCR_IDIS; 974 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 975 } 976 977 static int 978 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream, 979 struct snd_pcm_hw_params *params) 980 { 981 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 982 struct snd_pcm_runtime *runtime = substream->runtime; 983 int err, rate, dummy; 984 985 runtime->dma_area = (void __force *)(rme96->iobase + 986 RME96_IO_PLAY_BUFFER); 987 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER; 988 runtime->dma_bytes = RME96_BUFFER_SIZE; 989 990 spin_lock_irq(&rme96->lock); 991 if (!(rme96->wcreg & RME96_WCR_MASTER) && 992 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 993 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 994 { 995 /* slave clock */ 996 if ((int)params_rate(params) != rate) { 997 spin_unlock_irq(&rme96->lock); 998 return -EIO; 999 } 1000 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) { 1001 spin_unlock_irq(&rme96->lock); 1002 return err; 1003 } 1004 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) { 1005 spin_unlock_irq(&rme96->lock); 1006 return err; 1007 } 1008 snd_rme96_setframelog(rme96, params_channels(params), 1); 1009 if (rme96->capture_periodsize != 0) { 1010 if (params_period_size(params) << rme96->playback_frlog != 1011 rme96->capture_periodsize) 1012 { 1013 spin_unlock_irq(&rme96->lock); 1014 return -EBUSY; 1015 } 1016 } 1017 rme96->playback_periodsize = 1018 params_period_size(params) << rme96->playback_frlog; 1019 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize); 1020 /* S/PDIF setup */ 1021 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) { 1022 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 1023 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1024 } 1025 spin_unlock_irq(&rme96->lock); 1026 1027 return 0; 1028 } 1029 1030 static int 1031 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream, 1032 struct snd_pcm_hw_params *params) 1033 { 1034 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1035 struct snd_pcm_runtime *runtime = substream->runtime; 1036 int err, isadat, rate; 1037 1038 runtime->dma_area = (void __force *)(rme96->iobase + 1039 RME96_IO_REC_BUFFER); 1040 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER; 1041 runtime->dma_bytes = RME96_BUFFER_SIZE; 1042 1043 spin_lock_irq(&rme96->lock); 1044 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) { 1045 spin_unlock_irq(&rme96->lock); 1046 return err; 1047 } 1048 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1049 if ((err = snd_rme96_capture_analog_setrate(rme96, 1050 params_rate(params))) < 0) 1051 { 1052 spin_unlock_irq(&rme96->lock); 1053 return err; 1054 } 1055 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1056 if ((int)params_rate(params) != rate) { 1057 spin_unlock_irq(&rme96->lock); 1058 return -EIO; 1059 } 1060 if ((isadat && runtime->hw.channels_min == 2) || 1061 (!isadat && runtime->hw.channels_min == 8)) 1062 { 1063 spin_unlock_irq(&rme96->lock); 1064 return -EIO; 1065 } 1066 } 1067 snd_rme96_setframelog(rme96, params_channels(params), 0); 1068 if (rme96->playback_periodsize != 0) { 1069 if (params_period_size(params) << rme96->capture_frlog != 1070 rme96->playback_periodsize) 1071 { 1072 spin_unlock_irq(&rme96->lock); 1073 return -EBUSY; 1074 } 1075 } 1076 rme96->capture_periodsize = 1077 params_period_size(params) << rme96->capture_frlog; 1078 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize); 1079 spin_unlock_irq(&rme96->lock); 1080 1081 return 0; 1082 } 1083 1084 static void 1085 snd_rme96_trigger(struct rme96 *rme96, 1086 int op) 1087 { 1088 if (op & RME96_TB_RESET_PLAYPOS) 1089 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1090 if (op & RME96_TB_RESET_CAPTUREPOS) 1091 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1092 if (op & RME96_TB_CLEAR_PLAYBACK_IRQ) { 1093 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1094 if (rme96->rcreg & RME96_RCR_IRQ) 1095 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1096 } 1097 if (op & RME96_TB_CLEAR_CAPTURE_IRQ) { 1098 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1099 if (rme96->rcreg & RME96_RCR_IRQ_2) 1100 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1101 } 1102 if (op & RME96_TB_START_PLAYBACK) 1103 rme96->wcreg |= RME96_WCR_START; 1104 if (op & RME96_TB_STOP_PLAYBACK) 1105 rme96->wcreg &= ~RME96_WCR_START; 1106 if (op & RME96_TB_START_CAPTURE) 1107 rme96->wcreg |= RME96_WCR_START_2; 1108 if (op & RME96_TB_STOP_CAPTURE) 1109 rme96->wcreg &= ~RME96_WCR_START_2; 1110 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1111 } 1112 1113 1114 1115 static irqreturn_t 1116 snd_rme96_interrupt(int irq, 1117 void *dev_id) 1118 { 1119 struct rme96 *rme96 = (struct rme96 *)dev_id; 1120 1121 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1122 /* fastpath out, to ease interrupt sharing */ 1123 if (!((rme96->rcreg & RME96_RCR_IRQ) || 1124 (rme96->rcreg & RME96_RCR_IRQ_2))) 1125 { 1126 return IRQ_NONE; 1127 } 1128 1129 if (rme96->rcreg & RME96_RCR_IRQ) { 1130 /* playback */ 1131 snd_pcm_period_elapsed(rme96->playback_substream); 1132 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ); 1133 } 1134 if (rme96->rcreg & RME96_RCR_IRQ_2) { 1135 /* capture */ 1136 snd_pcm_period_elapsed(rme96->capture_substream); 1137 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ); 1138 } 1139 return IRQ_HANDLED; 1140 } 1141 1142 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE }; 1143 1144 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 1145 .count = ARRAY_SIZE(period_bytes), 1146 .list = period_bytes, 1147 .mask = 0 1148 }; 1149 1150 static void 1151 rme96_set_buffer_size_constraint(struct rme96 *rme96, 1152 struct snd_pcm_runtime *runtime) 1153 { 1154 unsigned int size; 1155 1156 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 1157 RME96_BUFFER_SIZE, RME96_BUFFER_SIZE); 1158 if ((size = rme96->playback_periodsize) != 0 || 1159 (size = rme96->capture_periodsize) != 0) 1160 snd_pcm_hw_constraint_minmax(runtime, 1161 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1162 size, size); 1163 else 1164 snd_pcm_hw_constraint_list(runtime, 0, 1165 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 1166 &hw_constraints_period_bytes); 1167 } 1168 1169 static int 1170 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream) 1171 { 1172 int rate, dummy; 1173 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1174 struct snd_pcm_runtime *runtime = substream->runtime; 1175 1176 snd_pcm_set_sync(substream); 1177 spin_lock_irq(&rme96->lock); 1178 if (rme96->playback_substream != NULL) { 1179 spin_unlock_irq(&rme96->lock); 1180 return -EBUSY; 1181 } 1182 rme96->wcreg &= ~RME96_WCR_ADAT; 1183 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1184 rme96->playback_substream = substream; 1185 spin_unlock_irq(&rme96->lock); 1186 1187 runtime->hw = snd_rme96_playback_spdif_info; 1188 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1189 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1190 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1191 { 1192 /* slave clock */ 1193 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1194 runtime->hw.rate_min = rate; 1195 runtime->hw.rate_max = rate; 1196 } 1197 rme96_set_buffer_size_constraint(rme96, runtime); 1198 1199 rme96->wcreg_spdif_stream = rme96->wcreg_spdif; 1200 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1201 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1202 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1203 return 0; 1204 } 1205 1206 static int 1207 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream) 1208 { 1209 int isadat, rate; 1210 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1211 struct snd_pcm_runtime *runtime = substream->runtime; 1212 1213 snd_pcm_set_sync(substream); 1214 runtime->hw = snd_rme96_capture_spdif_info; 1215 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1216 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) 1217 { 1218 if (isadat) { 1219 return -EIO; 1220 } 1221 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1222 runtime->hw.rate_min = rate; 1223 runtime->hw.rate_max = rate; 1224 } 1225 1226 spin_lock_irq(&rme96->lock); 1227 if (rme96->capture_substream != NULL) { 1228 spin_unlock_irq(&rme96->lock); 1229 return -EBUSY; 1230 } 1231 rme96->capture_substream = substream; 1232 spin_unlock_irq(&rme96->lock); 1233 1234 rme96_set_buffer_size_constraint(rme96, runtime); 1235 return 0; 1236 } 1237 1238 static int 1239 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream) 1240 { 1241 int rate, dummy; 1242 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1243 struct snd_pcm_runtime *runtime = substream->runtime; 1244 1245 snd_pcm_set_sync(substream); 1246 spin_lock_irq(&rme96->lock); 1247 if (rme96->playback_substream != NULL) { 1248 spin_unlock_irq(&rme96->lock); 1249 return -EBUSY; 1250 } 1251 rme96->wcreg |= RME96_WCR_ADAT; 1252 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1253 rme96->playback_substream = substream; 1254 spin_unlock_irq(&rme96->lock); 1255 1256 runtime->hw = snd_rme96_playback_adat_info; 1257 if (!(rme96->wcreg & RME96_WCR_MASTER) && 1258 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG && 1259 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0) 1260 { 1261 /* slave clock */ 1262 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1263 runtime->hw.rate_min = rate; 1264 runtime->hw.rate_max = rate; 1265 } 1266 rme96_set_buffer_size_constraint(rme96, runtime); 1267 return 0; 1268 } 1269 1270 static int 1271 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream) 1272 { 1273 int isadat, rate; 1274 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1275 struct snd_pcm_runtime *runtime = substream->runtime; 1276 1277 snd_pcm_set_sync(substream); 1278 runtime->hw = snd_rme96_capture_adat_info; 1279 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1280 /* makes no sense to use analog input. Note that analog 1281 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */ 1282 return -EIO; 1283 } 1284 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) { 1285 if (!isadat) { 1286 return -EIO; 1287 } 1288 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 1289 runtime->hw.rate_min = rate; 1290 runtime->hw.rate_max = rate; 1291 } 1292 1293 spin_lock_irq(&rme96->lock); 1294 if (rme96->capture_substream != NULL) { 1295 spin_unlock_irq(&rme96->lock); 1296 return -EBUSY; 1297 } 1298 rme96->capture_substream = substream; 1299 spin_unlock_irq(&rme96->lock); 1300 1301 rme96_set_buffer_size_constraint(rme96, runtime); 1302 return 0; 1303 } 1304 1305 static int 1306 snd_rme96_playback_close(struct snd_pcm_substream *substream) 1307 { 1308 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1309 int spdif = 0; 1310 1311 spin_lock_irq(&rme96->lock); 1312 if (RME96_ISPLAYING(rme96)) { 1313 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1314 } 1315 rme96->playback_substream = NULL; 1316 rme96->playback_periodsize = 0; 1317 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0; 1318 spin_unlock_irq(&rme96->lock); 1319 if (spdif) { 1320 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 1321 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE | 1322 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id); 1323 } 1324 return 0; 1325 } 1326 1327 static int 1328 snd_rme96_capture_close(struct snd_pcm_substream *substream) 1329 { 1330 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1331 1332 spin_lock_irq(&rme96->lock); 1333 if (RME96_ISRECORDING(rme96)) { 1334 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1335 } 1336 rme96->capture_substream = NULL; 1337 rme96->capture_periodsize = 0; 1338 spin_unlock_irq(&rme96->lock); 1339 return 0; 1340 } 1341 1342 static int 1343 snd_rme96_playback_prepare(struct snd_pcm_substream *substream) 1344 { 1345 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1346 1347 spin_lock_irq(&rme96->lock); 1348 if (RME96_ISPLAYING(rme96)) { 1349 snd_rme96_trigger(rme96, RME96_STOP_PLAYBACK); 1350 } 1351 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1352 spin_unlock_irq(&rme96->lock); 1353 return 0; 1354 } 1355 1356 static int 1357 snd_rme96_capture_prepare(struct snd_pcm_substream *substream) 1358 { 1359 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1360 1361 spin_lock_irq(&rme96->lock); 1362 if (RME96_ISRECORDING(rme96)) { 1363 snd_rme96_trigger(rme96, RME96_STOP_CAPTURE); 1364 } 1365 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1366 spin_unlock_irq(&rme96->lock); 1367 return 0; 1368 } 1369 1370 static int 1371 snd_rme96_playback_trigger(struct snd_pcm_substream *substream, 1372 int cmd) 1373 { 1374 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1375 struct snd_pcm_substream *s; 1376 bool sync; 1377 1378 snd_pcm_group_for_each_entry(s, substream) { 1379 if (snd_pcm_substream_chip(s) == rme96) 1380 snd_pcm_trigger_done(s, substream); 1381 } 1382 1383 sync = (rme96->playback_substream && rme96->capture_substream) && 1384 (rme96->playback_substream->group == 1385 rme96->capture_substream->group); 1386 1387 switch (cmd) { 1388 case SNDRV_PCM_TRIGGER_START: 1389 if (!RME96_ISPLAYING(rme96)) { 1390 if (substream != rme96->playback_substream) 1391 return -EBUSY; 1392 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1393 : RME96_START_PLAYBACK); 1394 } 1395 break; 1396 1397 case SNDRV_PCM_TRIGGER_SUSPEND: 1398 case SNDRV_PCM_TRIGGER_STOP: 1399 if (RME96_ISPLAYING(rme96)) { 1400 if (substream != rme96->playback_substream) 1401 return -EBUSY; 1402 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1403 : RME96_STOP_PLAYBACK); 1404 } 1405 break; 1406 1407 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1408 if (RME96_ISPLAYING(rme96)) 1409 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1410 : RME96_STOP_PLAYBACK); 1411 break; 1412 1413 case SNDRV_PCM_TRIGGER_RESUME: 1414 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1415 if (!RME96_ISPLAYING(rme96)) 1416 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1417 : RME96_RESUME_PLAYBACK); 1418 break; 1419 1420 default: 1421 return -EINVAL; 1422 } 1423 1424 return 0; 1425 } 1426 1427 static int 1428 snd_rme96_capture_trigger(struct snd_pcm_substream *substream, 1429 int cmd) 1430 { 1431 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1432 struct snd_pcm_substream *s; 1433 bool sync; 1434 1435 snd_pcm_group_for_each_entry(s, substream) { 1436 if (snd_pcm_substream_chip(s) == rme96) 1437 snd_pcm_trigger_done(s, substream); 1438 } 1439 1440 sync = (rme96->playback_substream && rme96->capture_substream) && 1441 (rme96->playback_substream->group == 1442 rme96->capture_substream->group); 1443 1444 switch (cmd) { 1445 case SNDRV_PCM_TRIGGER_START: 1446 if (!RME96_ISRECORDING(rme96)) { 1447 if (substream != rme96->capture_substream) 1448 return -EBUSY; 1449 snd_rme96_trigger(rme96, sync ? RME96_START_BOTH 1450 : RME96_START_CAPTURE); 1451 } 1452 break; 1453 1454 case SNDRV_PCM_TRIGGER_SUSPEND: 1455 case SNDRV_PCM_TRIGGER_STOP: 1456 if (RME96_ISRECORDING(rme96)) { 1457 if (substream != rme96->capture_substream) 1458 return -EBUSY; 1459 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1460 : RME96_STOP_CAPTURE); 1461 } 1462 break; 1463 1464 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1465 if (RME96_ISRECORDING(rme96)) 1466 snd_rme96_trigger(rme96, sync ? RME96_STOP_BOTH 1467 : RME96_STOP_CAPTURE); 1468 break; 1469 1470 case SNDRV_PCM_TRIGGER_RESUME: 1471 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1472 if (!RME96_ISRECORDING(rme96)) 1473 snd_rme96_trigger(rme96, sync ? RME96_RESUME_BOTH 1474 : RME96_RESUME_CAPTURE); 1475 break; 1476 1477 default: 1478 return -EINVAL; 1479 } 1480 1481 return 0; 1482 } 1483 1484 static snd_pcm_uframes_t 1485 snd_rme96_playback_pointer(struct snd_pcm_substream *substream) 1486 { 1487 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1488 return snd_rme96_playback_ptr(rme96); 1489 } 1490 1491 static snd_pcm_uframes_t 1492 snd_rme96_capture_pointer(struct snd_pcm_substream *substream) 1493 { 1494 struct rme96 *rme96 = snd_pcm_substream_chip(substream); 1495 return snd_rme96_capture_ptr(rme96); 1496 } 1497 1498 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = { 1499 .open = snd_rme96_playback_spdif_open, 1500 .close = snd_rme96_playback_close, 1501 .ioctl = snd_pcm_lib_ioctl, 1502 .hw_params = snd_rme96_playback_hw_params, 1503 .prepare = snd_rme96_playback_prepare, 1504 .trigger = snd_rme96_playback_trigger, 1505 .pointer = snd_rme96_playback_pointer, 1506 .copy = snd_rme96_playback_copy, 1507 .silence = snd_rme96_playback_silence, 1508 .mmap = snd_pcm_lib_mmap_iomem, 1509 }; 1510 1511 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = { 1512 .open = snd_rme96_capture_spdif_open, 1513 .close = snd_rme96_capture_close, 1514 .ioctl = snd_pcm_lib_ioctl, 1515 .hw_params = snd_rme96_capture_hw_params, 1516 .prepare = snd_rme96_capture_prepare, 1517 .trigger = snd_rme96_capture_trigger, 1518 .pointer = snd_rme96_capture_pointer, 1519 .copy = snd_rme96_capture_copy, 1520 .mmap = snd_pcm_lib_mmap_iomem, 1521 }; 1522 1523 static struct snd_pcm_ops snd_rme96_playback_adat_ops = { 1524 .open = snd_rme96_playback_adat_open, 1525 .close = snd_rme96_playback_close, 1526 .ioctl = snd_pcm_lib_ioctl, 1527 .hw_params = snd_rme96_playback_hw_params, 1528 .prepare = snd_rme96_playback_prepare, 1529 .trigger = snd_rme96_playback_trigger, 1530 .pointer = snd_rme96_playback_pointer, 1531 .copy = snd_rme96_playback_copy, 1532 .silence = snd_rme96_playback_silence, 1533 .mmap = snd_pcm_lib_mmap_iomem, 1534 }; 1535 1536 static struct snd_pcm_ops snd_rme96_capture_adat_ops = { 1537 .open = snd_rme96_capture_adat_open, 1538 .close = snd_rme96_capture_close, 1539 .ioctl = snd_pcm_lib_ioctl, 1540 .hw_params = snd_rme96_capture_hw_params, 1541 .prepare = snd_rme96_capture_prepare, 1542 .trigger = snd_rme96_capture_trigger, 1543 .pointer = snd_rme96_capture_pointer, 1544 .copy = snd_rme96_capture_copy, 1545 .mmap = snd_pcm_lib_mmap_iomem, 1546 }; 1547 1548 static void 1549 snd_rme96_free(void *private_data) 1550 { 1551 struct rme96 *rme96 = (struct rme96 *)private_data; 1552 1553 if (rme96 == NULL) { 1554 return; 1555 } 1556 if (rme96->irq >= 0) { 1557 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1558 rme96->areg &= ~RME96_AR_DAC_EN; 1559 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1560 free_irq(rme96->irq, (void *)rme96); 1561 rme96->irq = -1; 1562 } 1563 if (rme96->iobase) { 1564 iounmap(rme96->iobase); 1565 rme96->iobase = NULL; 1566 } 1567 if (rme96->port) { 1568 pci_release_regions(rme96->pci); 1569 rme96->port = 0; 1570 } 1571 #ifdef CONFIG_PM_SLEEP 1572 vfree(rme96->playback_suspend_buffer); 1573 vfree(rme96->capture_suspend_buffer); 1574 #endif 1575 pci_disable_device(rme96->pci); 1576 } 1577 1578 static void 1579 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm) 1580 { 1581 struct rme96 *rme96 = pcm->private_data; 1582 rme96->spdif_pcm = NULL; 1583 } 1584 1585 static void 1586 snd_rme96_free_adat_pcm(struct snd_pcm *pcm) 1587 { 1588 struct rme96 *rme96 = pcm->private_data; 1589 rme96->adat_pcm = NULL; 1590 } 1591 1592 static int 1593 snd_rme96_create(struct rme96 *rme96) 1594 { 1595 struct pci_dev *pci = rme96->pci; 1596 int err; 1597 1598 rme96->irq = -1; 1599 spin_lock_init(&rme96->lock); 1600 1601 if ((err = pci_enable_device(pci)) < 0) 1602 return err; 1603 1604 if ((err = pci_request_regions(pci, "RME96")) < 0) 1605 return err; 1606 rme96->port = pci_resource_start(rme96->pci, 0); 1607 1608 rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE); 1609 if (!rme96->iobase) { 1610 dev_err(rme96->card->dev, 1611 "unable to remap memory region 0x%lx-0x%lx\n", 1612 rme96->port, rme96->port + RME96_IO_SIZE - 1); 1613 return -ENOMEM; 1614 } 1615 1616 if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED, 1617 KBUILD_MODNAME, rme96)) { 1618 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq); 1619 return -EBUSY; 1620 } 1621 rme96->irq = pci->irq; 1622 1623 /* read the card's revision number */ 1624 pci_read_config_byte(pci, 8, &rme96->rev); 1625 1626 /* set up ALSA pcm device for S/PDIF */ 1627 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0, 1628 1, 1, &rme96->spdif_pcm)) < 0) 1629 { 1630 return err; 1631 } 1632 rme96->spdif_pcm->private_data = rme96; 1633 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm; 1634 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958"); 1635 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops); 1636 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops); 1637 1638 rme96->spdif_pcm->info_flags = 0; 1639 1640 /* set up ALSA pcm device for ADAT */ 1641 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) { 1642 /* ADAT is not available on the base model */ 1643 rme96->adat_pcm = NULL; 1644 } else { 1645 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1, 1646 1, 1, &rme96->adat_pcm)) < 0) 1647 { 1648 return err; 1649 } 1650 rme96->adat_pcm->private_data = rme96; 1651 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm; 1652 strcpy(rme96->adat_pcm->name, "Digi96 ADAT"); 1653 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops); 1654 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops); 1655 1656 rme96->adat_pcm->info_flags = 0; 1657 } 1658 1659 rme96->playback_periodsize = 0; 1660 rme96->capture_periodsize = 0; 1661 1662 /* make sure playback/capture is stopped, if by some reason active */ 1663 snd_rme96_trigger(rme96, RME96_STOP_BOTH); 1664 1665 /* set default values in registers */ 1666 rme96->wcreg = 1667 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */ 1668 RME96_WCR_SEL | /* normal playback */ 1669 RME96_WCR_MASTER | /* set to master clock mode */ 1670 RME96_WCR_INP_0; /* set coaxial input */ 1671 1672 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */ 1673 1674 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1675 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1676 1677 /* reset the ADC */ 1678 writel(rme96->areg | RME96_AR_PD2, 1679 rme96->iobase + RME96_IO_ADDITIONAL_REG); 1680 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1681 1682 /* reset and enable the DAC (order is important). */ 1683 snd_rme96_reset_dac(rme96); 1684 rme96->areg |= RME96_AR_DAC_EN; 1685 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 1686 1687 /* reset playback and record buffer pointers */ 1688 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS); 1689 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS); 1690 1691 /* reset volume */ 1692 rme96->vol[0] = rme96->vol[1] = 0; 1693 if (RME96_HAS_ANALOG_OUT(rme96)) { 1694 snd_rme96_apply_dac_volume(rme96); 1695 } 1696 1697 /* init switch interface */ 1698 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) { 1699 return err; 1700 } 1701 1702 /* init proc interface */ 1703 snd_rme96_proc_init(rme96); 1704 1705 return 0; 1706 } 1707 1708 /* 1709 * proc interface 1710 */ 1711 1712 static void 1713 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1714 { 1715 int n; 1716 struct rme96 *rme96 = entry->private_data; 1717 1718 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER); 1719 1720 snd_iprintf(buffer, rme96->card->longname); 1721 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1); 1722 1723 snd_iprintf(buffer, "\nGeneral settings\n"); 1724 if (rme96->wcreg & RME96_WCR_IDIS) { 1725 snd_iprintf(buffer, " period size: N/A (interrupts " 1726 "disabled)\n"); 1727 } else if (rme96->wcreg & RME96_WCR_ISEL) { 1728 snd_iprintf(buffer, " period size: 2048 bytes\n"); 1729 } else { 1730 snd_iprintf(buffer, " period size: 8192 bytes\n"); 1731 } 1732 snd_iprintf(buffer, "\nInput settings\n"); 1733 switch (snd_rme96_getinputtype(rme96)) { 1734 case RME96_INPUT_OPTICAL: 1735 snd_iprintf(buffer, " input: optical"); 1736 break; 1737 case RME96_INPUT_COAXIAL: 1738 snd_iprintf(buffer, " input: coaxial"); 1739 break; 1740 case RME96_INPUT_INTERNAL: 1741 snd_iprintf(buffer, " input: internal"); 1742 break; 1743 case RME96_INPUT_XLR: 1744 snd_iprintf(buffer, " input: XLR"); 1745 break; 1746 case RME96_INPUT_ANALOG: 1747 snd_iprintf(buffer, " input: analog"); 1748 break; 1749 } 1750 if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1751 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1752 } else { 1753 if (n) { 1754 snd_iprintf(buffer, " (8 channels)\n"); 1755 } else { 1756 snd_iprintf(buffer, " (2 channels)\n"); 1757 } 1758 snd_iprintf(buffer, " sample rate: %d Hz\n", 1759 snd_rme96_capture_getrate(rme96, &n)); 1760 } 1761 if (rme96->wcreg & RME96_WCR_MODE24_2) { 1762 snd_iprintf(buffer, " sample format: 24 bit\n"); 1763 } else { 1764 snd_iprintf(buffer, " sample format: 16 bit\n"); 1765 } 1766 1767 snd_iprintf(buffer, "\nOutput settings\n"); 1768 if (rme96->wcreg & RME96_WCR_SEL) { 1769 snd_iprintf(buffer, " output signal: normal playback\n"); 1770 } else { 1771 snd_iprintf(buffer, " output signal: same as input\n"); 1772 } 1773 snd_iprintf(buffer, " sample rate: %d Hz\n", 1774 snd_rme96_playback_getrate(rme96)); 1775 if (rme96->wcreg & RME96_WCR_MODE24) { 1776 snd_iprintf(buffer, " sample format: 24 bit\n"); 1777 } else { 1778 snd_iprintf(buffer, " sample format: 16 bit\n"); 1779 } 1780 if (rme96->areg & RME96_AR_WSEL) { 1781 snd_iprintf(buffer, " sample clock source: word clock\n"); 1782 } else if (rme96->wcreg & RME96_WCR_MASTER) { 1783 snd_iprintf(buffer, " sample clock source: internal\n"); 1784 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) { 1785 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n"); 1786 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) { 1787 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n"); 1788 } else { 1789 snd_iprintf(buffer, " sample clock source: autosync\n"); 1790 } 1791 if (rme96->wcreg & RME96_WCR_PRO) { 1792 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1793 } else { 1794 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1795 } 1796 if (rme96->wcreg & RME96_WCR_EMP) { 1797 snd_iprintf(buffer, " emphasis: on\n"); 1798 } else { 1799 snd_iprintf(buffer, " emphasis: off\n"); 1800 } 1801 if (rme96->wcreg & RME96_WCR_DOLBY) { 1802 snd_iprintf(buffer, " non-audio (dolby): on\n"); 1803 } else { 1804 snd_iprintf(buffer, " non-audio (dolby): off\n"); 1805 } 1806 if (RME96_HAS_ANALOG_IN(rme96)) { 1807 snd_iprintf(buffer, "\nAnalog output settings\n"); 1808 switch (snd_rme96_getmontracks(rme96)) { 1809 case RME96_MONITOR_TRACKS_1_2: 1810 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n"); 1811 break; 1812 case RME96_MONITOR_TRACKS_3_4: 1813 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n"); 1814 break; 1815 case RME96_MONITOR_TRACKS_5_6: 1816 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n"); 1817 break; 1818 case RME96_MONITOR_TRACKS_7_8: 1819 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n"); 1820 break; 1821 } 1822 switch (snd_rme96_getattenuation(rme96)) { 1823 case RME96_ATTENUATION_0: 1824 snd_iprintf(buffer, " attenuation: 0 dB\n"); 1825 break; 1826 case RME96_ATTENUATION_6: 1827 snd_iprintf(buffer, " attenuation: -6 dB\n"); 1828 break; 1829 case RME96_ATTENUATION_12: 1830 snd_iprintf(buffer, " attenuation: -12 dB\n"); 1831 break; 1832 case RME96_ATTENUATION_18: 1833 snd_iprintf(buffer, " attenuation: -18 dB\n"); 1834 break; 1835 } 1836 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]); 1837 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]); 1838 } 1839 } 1840 1841 static void snd_rme96_proc_init(struct rme96 *rme96) 1842 { 1843 struct snd_info_entry *entry; 1844 1845 if (! snd_card_proc_new(rme96->card, "rme96", &entry)) 1846 snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read); 1847 } 1848 1849 /* 1850 * control interface 1851 */ 1852 1853 #define snd_rme96_info_loopback_control snd_ctl_boolean_mono_info 1854 1855 static int 1856 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1857 { 1858 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1859 1860 spin_lock_irq(&rme96->lock); 1861 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1; 1862 spin_unlock_irq(&rme96->lock); 1863 return 0; 1864 } 1865 static int 1866 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1867 { 1868 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1869 unsigned int val; 1870 int change; 1871 1872 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL; 1873 spin_lock_irq(&rme96->lock); 1874 val = (rme96->wcreg & ~RME96_WCR_SEL) | val; 1875 change = val != rme96->wcreg; 1876 rme96->wcreg = val; 1877 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER); 1878 spin_unlock_irq(&rme96->lock); 1879 return change; 1880 } 1881 1882 static int 1883 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 1884 { 1885 static const char * const _texts[5] = { 1886 "Optical", "Coaxial", "Internal", "XLR", "Analog" 1887 }; 1888 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1889 const char *texts[5] = { 1890 _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] 1891 }; 1892 int num_items; 1893 1894 switch (rme96->pci->device) { 1895 case PCI_DEVICE_ID_RME_DIGI96: 1896 case PCI_DEVICE_ID_RME_DIGI96_8: 1897 num_items = 3; 1898 break; 1899 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1900 num_items = 4; 1901 break; 1902 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1903 if (rme96->rev > 4) { 1904 /* PST */ 1905 num_items = 4; 1906 texts[3] = _texts[4]; /* Analog instead of XLR */ 1907 } else { 1908 /* PAD */ 1909 num_items = 5; 1910 } 1911 break; 1912 default: 1913 snd_BUG(); 1914 return -EINVAL; 1915 } 1916 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1917 } 1918 static int 1919 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1920 { 1921 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1922 unsigned int items = 3; 1923 1924 spin_lock_irq(&rme96->lock); 1925 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96); 1926 1927 switch (rme96->pci->device) { 1928 case PCI_DEVICE_ID_RME_DIGI96: 1929 case PCI_DEVICE_ID_RME_DIGI96_8: 1930 items = 3; 1931 break; 1932 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1933 items = 4; 1934 break; 1935 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1936 if (rme96->rev > 4) { 1937 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */ 1938 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) { 1939 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR; 1940 } 1941 items = 4; 1942 } else { 1943 items = 5; 1944 } 1945 break; 1946 default: 1947 snd_BUG(); 1948 break; 1949 } 1950 if (ucontrol->value.enumerated.item[0] >= items) { 1951 ucontrol->value.enumerated.item[0] = items - 1; 1952 } 1953 1954 spin_unlock_irq(&rme96->lock); 1955 return 0; 1956 } 1957 static int 1958 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 1959 { 1960 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 1961 unsigned int val; 1962 int change, items = 3; 1963 1964 switch (rme96->pci->device) { 1965 case PCI_DEVICE_ID_RME_DIGI96: 1966 case PCI_DEVICE_ID_RME_DIGI96_8: 1967 items = 3; 1968 break; 1969 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 1970 items = 4; 1971 break; 1972 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 1973 if (rme96->rev > 4) { 1974 items = 4; 1975 } else { 1976 items = 5; 1977 } 1978 break; 1979 default: 1980 snd_BUG(); 1981 break; 1982 } 1983 val = ucontrol->value.enumerated.item[0] % items; 1984 1985 /* special case for PST */ 1986 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) { 1987 if (val == RME96_INPUT_XLR) { 1988 val = RME96_INPUT_ANALOG; 1989 } 1990 } 1991 1992 spin_lock_irq(&rme96->lock); 1993 change = (int)val != snd_rme96_getinputtype(rme96); 1994 snd_rme96_setinputtype(rme96, val); 1995 spin_unlock_irq(&rme96->lock); 1996 return change; 1997 } 1998 1999 static int 2000 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2001 { 2002 static const char * const texts[3] = { "AutoSync", "Internal", "Word" }; 2003 2004 return snd_ctl_enum_info(uinfo, 1, 3, texts); 2005 } 2006 static int 2007 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2008 { 2009 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2010 2011 spin_lock_irq(&rme96->lock); 2012 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96); 2013 spin_unlock_irq(&rme96->lock); 2014 return 0; 2015 } 2016 static int 2017 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2018 { 2019 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2020 unsigned int val; 2021 int change; 2022 2023 val = ucontrol->value.enumerated.item[0] % 3; 2024 spin_lock_irq(&rme96->lock); 2025 change = (int)val != snd_rme96_getclockmode(rme96); 2026 snd_rme96_setclockmode(rme96, val); 2027 spin_unlock_irq(&rme96->lock); 2028 return change; 2029 } 2030 2031 static int 2032 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2033 { 2034 static const char * const texts[4] = { 2035 "0 dB", "-6 dB", "-12 dB", "-18 dB" 2036 }; 2037 2038 return snd_ctl_enum_info(uinfo, 1, 4, texts); 2039 } 2040 static int 2041 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2042 { 2043 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2044 2045 spin_lock_irq(&rme96->lock); 2046 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96); 2047 spin_unlock_irq(&rme96->lock); 2048 return 0; 2049 } 2050 static int 2051 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2052 { 2053 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2054 unsigned int val; 2055 int change; 2056 2057 val = ucontrol->value.enumerated.item[0] % 4; 2058 spin_lock_irq(&rme96->lock); 2059 2060 change = (int)val != snd_rme96_getattenuation(rme96); 2061 snd_rme96_setattenuation(rme96, val); 2062 spin_unlock_irq(&rme96->lock); 2063 return change; 2064 } 2065 2066 static int 2067 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2068 { 2069 static const char * const texts[4] = { "1+2", "3+4", "5+6", "7+8" }; 2070 2071 return snd_ctl_enum_info(uinfo, 1, 4, texts); 2072 } 2073 static int 2074 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2075 { 2076 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2077 2078 spin_lock_irq(&rme96->lock); 2079 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96); 2080 spin_unlock_irq(&rme96->lock); 2081 return 0; 2082 } 2083 static int 2084 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2085 { 2086 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2087 unsigned int val; 2088 int change; 2089 2090 val = ucontrol->value.enumerated.item[0] % 4; 2091 spin_lock_irq(&rme96->lock); 2092 change = (int)val != snd_rme96_getmontracks(rme96); 2093 snd_rme96_setmontracks(rme96, val); 2094 spin_unlock_irq(&rme96->lock); 2095 return change; 2096 } 2097 2098 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes) 2099 { 2100 u32 val = 0; 2101 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0; 2102 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0; 2103 if (val & RME96_WCR_PRO) 2104 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2105 else 2106 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0; 2107 return val; 2108 } 2109 2110 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val) 2111 { 2112 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) | 2113 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0); 2114 if (val & RME96_WCR_PRO) 2115 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 2116 else 2117 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 2118 } 2119 2120 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2121 { 2122 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2123 uinfo->count = 1; 2124 return 0; 2125 } 2126 2127 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2128 { 2129 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2130 2131 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif); 2132 return 0; 2133 } 2134 2135 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2136 { 2137 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2138 int change; 2139 u32 val; 2140 2141 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2142 spin_lock_irq(&rme96->lock); 2143 change = val != rme96->wcreg_spdif; 2144 rme96->wcreg_spdif = val; 2145 spin_unlock_irq(&rme96->lock); 2146 return change; 2147 } 2148 2149 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2150 { 2151 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2152 uinfo->count = 1; 2153 return 0; 2154 } 2155 2156 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2157 { 2158 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2159 2160 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream); 2161 return 0; 2162 } 2163 2164 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2165 { 2166 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2167 int change; 2168 u32 val; 2169 2170 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958); 2171 spin_lock_irq(&rme96->lock); 2172 change = val != rme96->wcreg_spdif_stream; 2173 rme96->wcreg_spdif_stream = val; 2174 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP); 2175 rme96->wcreg |= val; 2176 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER); 2177 spin_unlock_irq(&rme96->lock); 2178 return change; 2179 } 2180 2181 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2182 { 2183 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 2184 uinfo->count = 1; 2185 return 0; 2186 } 2187 2188 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) 2189 { 2190 ucontrol->value.iec958.status[0] = kcontrol->private_value; 2191 return 0; 2192 } 2193 2194 static int 2195 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) 2196 { 2197 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2198 2199 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 2200 uinfo->count = 2; 2201 uinfo->value.integer.min = 0; 2202 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96); 2203 return 0; 2204 } 2205 2206 static int 2207 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2208 { 2209 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2210 2211 spin_lock_irq(&rme96->lock); 2212 u->value.integer.value[0] = rme96->vol[0]; 2213 u->value.integer.value[1] = rme96->vol[1]; 2214 spin_unlock_irq(&rme96->lock); 2215 2216 return 0; 2217 } 2218 2219 static int 2220 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u) 2221 { 2222 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol); 2223 int change = 0; 2224 unsigned int vol, maxvol; 2225 2226 2227 if (!RME96_HAS_ANALOG_OUT(rme96)) 2228 return -EINVAL; 2229 maxvol = RME96_185X_MAX_OUT(rme96); 2230 spin_lock_irq(&rme96->lock); 2231 vol = u->value.integer.value[0]; 2232 if (vol != rme96->vol[0] && vol <= maxvol) { 2233 rme96->vol[0] = vol; 2234 change = 1; 2235 } 2236 vol = u->value.integer.value[1]; 2237 if (vol != rme96->vol[1] && vol <= maxvol) { 2238 rme96->vol[1] = vol; 2239 change = 1; 2240 } 2241 if (change) 2242 snd_rme96_apply_dac_volume(rme96); 2243 spin_unlock_irq(&rme96->lock); 2244 2245 return change; 2246 } 2247 2248 static struct snd_kcontrol_new snd_rme96_controls[] = { 2249 { 2250 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2251 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT), 2252 .info = snd_rme96_control_spdif_info, 2253 .get = snd_rme96_control_spdif_get, 2254 .put = snd_rme96_control_spdif_put 2255 }, 2256 { 2257 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 2258 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2259 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM), 2260 .info = snd_rme96_control_spdif_stream_info, 2261 .get = snd_rme96_control_spdif_stream_get, 2262 .put = snd_rme96_control_spdif_stream_put 2263 }, 2264 { 2265 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2266 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2267 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK), 2268 .info = snd_rme96_control_spdif_mask_info, 2269 .get = snd_rme96_control_spdif_mask_get, 2270 .private_value = IEC958_AES0_NONAUDIO | 2271 IEC958_AES0_PROFESSIONAL | 2272 IEC958_AES0_CON_EMPHASIS 2273 }, 2274 { 2275 .access = SNDRV_CTL_ELEM_ACCESS_READ, 2276 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 2277 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK), 2278 .info = snd_rme96_control_spdif_mask_info, 2279 .get = snd_rme96_control_spdif_mask_get, 2280 .private_value = IEC958_AES0_NONAUDIO | 2281 IEC958_AES0_PROFESSIONAL | 2282 IEC958_AES0_PRO_EMPHASIS 2283 }, 2284 { 2285 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2286 .name = "Input Connector", 2287 .info = snd_rme96_info_inputtype_control, 2288 .get = snd_rme96_get_inputtype_control, 2289 .put = snd_rme96_put_inputtype_control 2290 }, 2291 { 2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2293 .name = "Loopback Input", 2294 .info = snd_rme96_info_loopback_control, 2295 .get = snd_rme96_get_loopback_control, 2296 .put = snd_rme96_put_loopback_control 2297 }, 2298 { 2299 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2300 .name = "Sample Clock Source", 2301 .info = snd_rme96_info_clockmode_control, 2302 .get = snd_rme96_get_clockmode_control, 2303 .put = snd_rme96_put_clockmode_control 2304 }, 2305 { 2306 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2307 .name = "Monitor Tracks", 2308 .info = snd_rme96_info_montracks_control, 2309 .get = snd_rme96_get_montracks_control, 2310 .put = snd_rme96_put_montracks_control 2311 }, 2312 { 2313 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2314 .name = "Attenuation", 2315 .info = snd_rme96_info_attenuation_control, 2316 .get = snd_rme96_get_attenuation_control, 2317 .put = snd_rme96_put_attenuation_control 2318 }, 2319 { 2320 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 2321 .name = "DAC Playback Volume", 2322 .info = snd_rme96_dac_volume_info, 2323 .get = snd_rme96_dac_volume_get, 2324 .put = snd_rme96_dac_volume_put 2325 } 2326 }; 2327 2328 static int 2329 snd_rme96_create_switches(struct snd_card *card, 2330 struct rme96 *rme96) 2331 { 2332 int idx, err; 2333 struct snd_kcontrol *kctl; 2334 2335 for (idx = 0; idx < 7; idx++) { 2336 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2337 return err; 2338 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 2339 rme96->spdif_ctl = kctl; 2340 } 2341 2342 if (RME96_HAS_ANALOG_OUT(rme96)) { 2343 for (idx = 7; idx < 10; idx++) 2344 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0) 2345 return err; 2346 } 2347 2348 return 0; 2349 } 2350 2351 /* 2352 * Card initialisation 2353 */ 2354 2355 #ifdef CONFIG_PM_SLEEP 2356 2357 static int rme96_suspend(struct device *dev) 2358 { 2359 struct snd_card *card = dev_get_drvdata(dev); 2360 struct rme96 *rme96 = card->private_data; 2361 2362 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2363 snd_pcm_suspend(rme96->playback_substream); 2364 snd_pcm_suspend(rme96->capture_substream); 2365 2366 /* save capture & playback pointers */ 2367 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS) 2368 & RME96_RCR_AUDIO_ADDR_MASK; 2369 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS) 2370 & RME96_RCR_AUDIO_ADDR_MASK; 2371 2372 /* save playback and capture buffers */ 2373 memcpy_fromio(rme96->playback_suspend_buffer, 2374 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE); 2375 memcpy_fromio(rme96->capture_suspend_buffer, 2376 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE); 2377 2378 /* disable the DAC */ 2379 rme96->areg &= ~RME96_AR_DAC_EN; 2380 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2381 return 0; 2382 } 2383 2384 static int rme96_resume(struct device *dev) 2385 { 2386 struct snd_card *card = dev_get_drvdata(dev); 2387 struct rme96 *rme96 = card->private_data; 2388 2389 /* reset playback and record buffer pointers */ 2390 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS 2391 + rme96->playback_pointer); 2392 writel(0, rme96->iobase + RME96_IO_SET_REC_POS 2393 + rme96->capture_pointer); 2394 2395 /* restore playback and capture buffers */ 2396 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER, 2397 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE); 2398 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER, 2399 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE); 2400 2401 /* reset the ADC */ 2402 writel(rme96->areg | RME96_AR_PD2, 2403 rme96->iobase + RME96_IO_ADDITIONAL_REG); 2404 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2405 2406 /* reset and enable DAC, restore analog volume */ 2407 snd_rme96_reset_dac(rme96); 2408 rme96->areg |= RME96_AR_DAC_EN; 2409 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG); 2410 if (RME96_HAS_ANALOG_OUT(rme96)) { 2411 usleep_range(3000, 10000); 2412 snd_rme96_apply_dac_volume(rme96); 2413 } 2414 2415 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2416 2417 return 0; 2418 } 2419 2420 static SIMPLE_DEV_PM_OPS(rme96_pm, rme96_suspend, rme96_resume); 2421 #define RME96_PM_OPS &rme96_pm 2422 #else 2423 #define RME96_PM_OPS NULL 2424 #endif /* CONFIG_PM_SLEEP */ 2425 2426 static void snd_rme96_card_free(struct snd_card *card) 2427 { 2428 snd_rme96_free(card->private_data); 2429 } 2430 2431 static int 2432 snd_rme96_probe(struct pci_dev *pci, 2433 const struct pci_device_id *pci_id) 2434 { 2435 static int dev; 2436 struct rme96 *rme96; 2437 struct snd_card *card; 2438 int err; 2439 u8 val; 2440 2441 if (dev >= SNDRV_CARDS) { 2442 return -ENODEV; 2443 } 2444 if (!enable[dev]) { 2445 dev++; 2446 return -ENOENT; 2447 } 2448 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2449 sizeof(struct rme96), &card); 2450 if (err < 0) 2451 return err; 2452 card->private_free = snd_rme96_card_free; 2453 rme96 = card->private_data; 2454 rme96->card = card; 2455 rme96->pci = pci; 2456 if ((err = snd_rme96_create(rme96)) < 0) { 2457 snd_card_free(card); 2458 return err; 2459 } 2460 2461 #ifdef CONFIG_PM_SLEEP 2462 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2463 if (!rme96->playback_suspend_buffer) { 2464 dev_err(card->dev, 2465 "Failed to allocate playback suspend buffer!\n"); 2466 snd_card_free(card); 2467 return -ENOMEM; 2468 } 2469 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE); 2470 if (!rme96->capture_suspend_buffer) { 2471 dev_err(card->dev, 2472 "Failed to allocate capture suspend buffer!\n"); 2473 snd_card_free(card); 2474 return -ENOMEM; 2475 } 2476 #endif 2477 2478 strcpy(card->driver, "Digi96"); 2479 switch (rme96->pci->device) { 2480 case PCI_DEVICE_ID_RME_DIGI96: 2481 strcpy(card->shortname, "RME Digi96"); 2482 break; 2483 case PCI_DEVICE_ID_RME_DIGI96_8: 2484 strcpy(card->shortname, "RME Digi96/8"); 2485 break; 2486 case PCI_DEVICE_ID_RME_DIGI96_8_PRO: 2487 strcpy(card->shortname, "RME Digi96/8 PRO"); 2488 break; 2489 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST: 2490 pci_read_config_byte(rme96->pci, 8, &val); 2491 if (val < 5) { 2492 strcpy(card->shortname, "RME Digi96/8 PAD"); 2493 } else { 2494 strcpy(card->shortname, "RME Digi96/8 PST"); 2495 } 2496 break; 2497 } 2498 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname, 2499 rme96->port, rme96->irq); 2500 2501 if ((err = snd_card_register(card)) < 0) { 2502 snd_card_free(card); 2503 return err; 2504 } 2505 pci_set_drvdata(pci, card); 2506 dev++; 2507 return 0; 2508 } 2509 2510 static void snd_rme96_remove(struct pci_dev *pci) 2511 { 2512 snd_card_free(pci_get_drvdata(pci)); 2513 } 2514 2515 static struct pci_driver rme96_driver = { 2516 .name = KBUILD_MODNAME, 2517 .id_table = snd_rme96_ids, 2518 .probe = snd_rme96_probe, 2519 .remove = snd_rme96_remove, 2520 .driver = { 2521 .pm = RME96_PM_OPS, 2522 }, 2523 }; 2524 2525 module_pci_driver(rme96_driver); 2526