1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces 4 * 5 * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>, 6 * Pilo Chambert <pilo.c@wanadoo.fr> 7 * 8 * Thanks to : Anders Torger <torger@ludd.luth.se>, 9 * Henk Hesselink <henk@anda.nl> 10 * for writing the digi96-driver 11 * and RME for all informations. 12 * 13 * **************************************************************************** 14 * 15 * Note #1 "Sek'd models" ................................... martin 2002-12-07 16 * 17 * Identical soundcards by Sek'd were labeled: 18 * RME Digi 32 = Sek'd Prodif 32 19 * RME Digi 32 Pro = Sek'd Prodif 96 20 * RME Digi 32/8 = Sek'd Prodif Gold 21 * 22 * **************************************************************************** 23 * 24 * Note #2 "full duplex mode" ............................... martin 2002-12-07 25 * 26 * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical 27 * in this mode. Rec data and play data are using the same buffer therefore. At 28 * first you have got the playing bits in the buffer and then (after playing 29 * them) they were overwitten by the captured sound of the CS8412/14. Both 30 * modes (play/record) are running harmonically hand in hand in the same buffer 31 * and you have only one start bit plus one interrupt bit to control this 32 * paired action. 33 * This is opposite to the latter rme96 where playing and capturing is totally 34 * separated and so their full duplex mode is supported by alsa (using two 35 * start bits and two interrupts for two different buffers). 36 * But due to the wrong sequence of playing and capturing ALSA shows no solved 37 * full duplex support for the rme32 at the moment. That's bad, but I'm not 38 * able to solve it. Are you motivated enough to solve this problem now? Your 39 * patch would be welcome! 40 * 41 * **************************************************************************** 42 * 43 * "The story after the long seeking" -- tiwai 44 * 45 * Ok, the situation regarding the full duplex is now improved a bit. 46 * In the fullduplex mode (given by the module parameter), the hardware buffer 47 * is split to halves for read and write directions at the DMA pointer. 48 * That is, the half above the current DMA pointer is used for write, and 49 * the half below is used for read. To mangle this strange behavior, an 50 * software intermediate buffer is introduced. This is, of course, not good 51 * from the viewpoint of the data transfer efficiency. However, this allows 52 * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size. 53 * 54 * **************************************************************************** 55 */ 56 57 58 #include <linux/delay.h> 59 #include <linux/gfp.h> 60 #include <linux/init.h> 61 #include <linux/interrupt.h> 62 #include <linux/pci.h> 63 #include <linux/module.h> 64 #include <linux/io.h> 65 66 #include <sound/core.h> 67 #include <sound/info.h> 68 #include <sound/control.h> 69 #include <sound/pcm.h> 70 #include <sound/pcm_params.h> 71 #include <sound/pcm-indirect.h> 72 #include <sound/asoundef.h> 73 #include <sound/initval.h> 74 75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 77 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 78 static bool fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1}; 79 80 module_param_array(index, int, NULL, 0444); 81 MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard."); 82 module_param_array(id, charp, NULL, 0444); 83 MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard."); 84 module_param_array(enable, bool, NULL, 0444); 85 MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard."); 86 module_param_array(fullduplex, bool, NULL, 0444); 87 MODULE_PARM_DESC(fullduplex, "Support full-duplex mode."); 88 MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>"); 89 MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO"); 90 MODULE_LICENSE("GPL"); 91 MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}"); 92 93 /* Defines for RME Digi32 series */ 94 #define RME32_SPDIF_NCHANNELS 2 95 96 /* Playback and capture buffer size */ 97 #define RME32_BUFFER_SIZE 0x20000 98 99 /* IO area size */ 100 #define RME32_IO_SIZE 0x30000 101 102 /* IO area offsets */ 103 #define RME32_IO_DATA_BUFFER 0x0 104 #define RME32_IO_CONTROL_REGISTER 0x20000 105 #define RME32_IO_GET_POS 0x20000 106 #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004 107 #define RME32_IO_RESET_POS 0x20100 108 109 /* Write control register bits */ 110 #define RME32_WCR_START (1 << 0) /* startbit */ 111 #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono 112 Setting the whole card to mono 113 doesn't seem to be very useful. 114 A software-solution can handle 115 full-duplex with one direction in 116 stereo and the other way in mono. 117 So, the hardware should work all 118 the time in stereo! */ 119 #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */ 120 #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */ 121 #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */ 122 #define RME32_WCR_FREQ_1 (1 << 5) 123 #define RME32_WCR_INP_0 (1 << 6) /* input switch */ 124 #define RME32_WCR_INP_1 (1 << 7) 125 #define RME32_WCR_RESET (1 << 8) /* Reset address */ 126 #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */ 127 #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */ 128 #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */ 129 #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */ 130 #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */ 131 #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */ 132 #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */ 133 134 #define RME32_WCR_BITPOS_FREQ_0 4 135 #define RME32_WCR_BITPOS_FREQ_1 5 136 #define RME32_WCR_BITPOS_INP_0 6 137 #define RME32_WCR_BITPOS_INP_1 7 138 139 /* Read control register bits */ 140 #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff 141 #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */ 142 #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */ 143 #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */ 144 #define RME32_RCR_FREQ_1 (1 << 28) 145 #define RME32_RCR_FREQ_2 (1 << 29) 146 #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */ 147 #define RME32_RCR_IRQ (1 << 31) /* interrupt */ 148 149 #define RME32_RCR_BITPOS_F0 27 150 #define RME32_RCR_BITPOS_F1 28 151 #define RME32_RCR_BITPOS_F2 29 152 153 /* Input types */ 154 #define RME32_INPUT_OPTICAL 0 155 #define RME32_INPUT_COAXIAL 1 156 #define RME32_INPUT_INTERNAL 2 157 #define RME32_INPUT_XLR 3 158 159 /* Clock modes */ 160 #define RME32_CLOCKMODE_SLAVE 0 161 #define RME32_CLOCKMODE_MASTER_32 1 162 #define RME32_CLOCKMODE_MASTER_44 2 163 #define RME32_CLOCKMODE_MASTER_48 3 164 165 /* Block sizes in bytes */ 166 #define RME32_BLOCK_SIZE 8192 167 168 /* Software intermediate buffer (max) size */ 169 #define RME32_MID_BUFFER_SIZE (1024*1024) 170 171 /* Hardware revisions */ 172 #define RME32_32_REVISION 192 173 #define RME32_328_REVISION_OLD 100 174 #define RME32_328_REVISION_NEW 101 175 #define RME32_PRO_REVISION_WITH_8412 192 176 #define RME32_PRO_REVISION_WITH_8414 150 177 178 179 struct rme32 { 180 spinlock_t lock; 181 int irq; 182 unsigned long port; 183 void __iomem *iobase; 184 185 u32 wcreg; /* cached write control register value */ 186 u32 wcreg_spdif; /* S/PDIF setup */ 187 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */ 188 u32 rcreg; /* cached read control register value */ 189 190 u8 rev; /* card revision number */ 191 192 struct snd_pcm_substream *playback_substream; 193 struct snd_pcm_substream *capture_substream; 194 195 int playback_frlog; /* log2 of framesize */ 196 int capture_frlog; 197 198 size_t playback_periodsize; /* in bytes, zero if not used */ 199 size_t capture_periodsize; /* in bytes, zero if not used */ 200 201 unsigned int fullduplex_mode; 202 int running; 203 204 struct snd_pcm_indirect playback_pcm; 205 struct snd_pcm_indirect capture_pcm; 206 207 struct snd_card *card; 208 struct snd_pcm *spdif_pcm; 209 struct snd_pcm *adat_pcm; 210 struct pci_dev *pci; 211 struct snd_kcontrol *spdif_ctl; 212 }; 213 214 static const struct pci_device_id snd_rme32_ids[] = { 215 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32), 0,}, 216 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8), 0,}, 217 {PCI_VDEVICE(XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO), 0,}, 218 {0,} 219 }; 220 221 MODULE_DEVICE_TABLE(pci, snd_rme32_ids); 222 223 #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START) 224 #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414) 225 226 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream); 227 228 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream); 229 230 static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd); 231 232 static void snd_rme32_proc_init(struct rme32 * rme32); 233 234 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32); 235 236 static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32) 237 { 238 return (readl(rme32->iobase + RME32_IO_GET_POS) 239 & RME32_RCR_AUDIO_ADDR_MASK); 240 } 241 242 /* silence callback for halfduplex mode */ 243 static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, 244 int channel, unsigned long pos, 245 unsigned long count) 246 { 247 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 248 249 memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count); 250 return 0; 251 } 252 253 /* copy callback for halfduplex mode */ 254 static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, 255 int channel, unsigned long pos, 256 void __user *src, unsigned long count) 257 { 258 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 259 260 if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 261 src, count)) 262 return -EFAULT; 263 return 0; 264 } 265 266 static int snd_rme32_playback_copy_kernel(struct snd_pcm_substream *substream, 267 int channel, unsigned long pos, 268 void *src, unsigned long count) 269 { 270 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 271 272 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos, src, count); 273 return 0; 274 } 275 276 /* copy callback for halfduplex mode */ 277 static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, 278 int channel, unsigned long pos, 279 void __user *dst, unsigned long count) 280 { 281 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 282 283 if (copy_to_user_fromio(dst, 284 rme32->iobase + RME32_IO_DATA_BUFFER + pos, 285 count)) 286 return -EFAULT; 287 return 0; 288 } 289 290 static int snd_rme32_capture_copy_kernel(struct snd_pcm_substream *substream, 291 int channel, unsigned long pos, 292 void *dst, unsigned long count) 293 { 294 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 295 296 memcpy_fromio(dst, rme32->iobase + RME32_IO_DATA_BUFFER + pos, count); 297 return 0; 298 } 299 300 /* 301 * SPDIF I/O capabilities (half-duplex mode) 302 */ 303 static const struct snd_pcm_hardware snd_rme32_spdif_info = { 304 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 305 SNDRV_PCM_INFO_MMAP_VALID | 306 SNDRV_PCM_INFO_INTERLEAVED | 307 SNDRV_PCM_INFO_PAUSE | 308 SNDRV_PCM_INFO_SYNC_START | 309 SNDRV_PCM_INFO_SYNC_APPLPTR), 310 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 311 SNDRV_PCM_FMTBIT_S32_LE), 312 .rates = (SNDRV_PCM_RATE_32000 | 313 SNDRV_PCM_RATE_44100 | 314 SNDRV_PCM_RATE_48000), 315 .rate_min = 32000, 316 .rate_max = 48000, 317 .channels_min = 2, 318 .channels_max = 2, 319 .buffer_bytes_max = RME32_BUFFER_SIZE, 320 .period_bytes_min = RME32_BLOCK_SIZE, 321 .period_bytes_max = RME32_BLOCK_SIZE, 322 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 323 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 324 .fifo_size = 0, 325 }; 326 327 /* 328 * ADAT I/O capabilities (half-duplex mode) 329 */ 330 static const struct snd_pcm_hardware snd_rme32_adat_info = 331 { 332 .info = (SNDRV_PCM_INFO_MMAP_IOMEM | 333 SNDRV_PCM_INFO_MMAP_VALID | 334 SNDRV_PCM_INFO_INTERLEAVED | 335 SNDRV_PCM_INFO_PAUSE | 336 SNDRV_PCM_INFO_SYNC_START | 337 SNDRV_PCM_INFO_SYNC_APPLPTR), 338 .formats= SNDRV_PCM_FMTBIT_S16_LE, 339 .rates = (SNDRV_PCM_RATE_44100 | 340 SNDRV_PCM_RATE_48000), 341 .rate_min = 44100, 342 .rate_max = 48000, 343 .channels_min = 8, 344 .channels_max = 8, 345 .buffer_bytes_max = RME32_BUFFER_SIZE, 346 .period_bytes_min = RME32_BLOCK_SIZE, 347 .period_bytes_max = RME32_BLOCK_SIZE, 348 .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 349 .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE, 350 .fifo_size = 0, 351 }; 352 353 /* 354 * SPDIF I/O capabilities (full-duplex mode) 355 */ 356 static const struct snd_pcm_hardware snd_rme32_spdif_fd_info = { 357 .info = (SNDRV_PCM_INFO_MMAP | 358 SNDRV_PCM_INFO_MMAP_VALID | 359 SNDRV_PCM_INFO_INTERLEAVED | 360 SNDRV_PCM_INFO_PAUSE | 361 SNDRV_PCM_INFO_SYNC_START | 362 SNDRV_PCM_INFO_SYNC_APPLPTR), 363 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 364 SNDRV_PCM_FMTBIT_S32_LE), 365 .rates = (SNDRV_PCM_RATE_32000 | 366 SNDRV_PCM_RATE_44100 | 367 SNDRV_PCM_RATE_48000), 368 .rate_min = 32000, 369 .rate_max = 48000, 370 .channels_min = 2, 371 .channels_max = 2, 372 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 373 .period_bytes_min = RME32_BLOCK_SIZE, 374 .period_bytes_max = RME32_BLOCK_SIZE, 375 .periods_min = 2, 376 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 377 .fifo_size = 0, 378 }; 379 380 /* 381 * ADAT I/O capabilities (full-duplex mode) 382 */ 383 static const struct snd_pcm_hardware snd_rme32_adat_fd_info = 384 { 385 .info = (SNDRV_PCM_INFO_MMAP | 386 SNDRV_PCM_INFO_MMAP_VALID | 387 SNDRV_PCM_INFO_INTERLEAVED | 388 SNDRV_PCM_INFO_PAUSE | 389 SNDRV_PCM_INFO_SYNC_START | 390 SNDRV_PCM_INFO_SYNC_APPLPTR), 391 .formats= SNDRV_PCM_FMTBIT_S16_LE, 392 .rates = (SNDRV_PCM_RATE_44100 | 393 SNDRV_PCM_RATE_48000), 394 .rate_min = 44100, 395 .rate_max = 48000, 396 .channels_min = 8, 397 .channels_max = 8, 398 .buffer_bytes_max = RME32_MID_BUFFER_SIZE, 399 .period_bytes_min = RME32_BLOCK_SIZE, 400 .period_bytes_max = RME32_BLOCK_SIZE, 401 .periods_min = 2, 402 .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE, 403 .fifo_size = 0, 404 }; 405 406 static void snd_rme32_reset_dac(struct rme32 *rme32) 407 { 408 writel(rme32->wcreg | RME32_WCR_PD, 409 rme32->iobase + RME32_IO_CONTROL_REGISTER); 410 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 411 } 412 413 static int snd_rme32_playback_getrate(struct rme32 * rme32) 414 { 415 int rate; 416 417 rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 418 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 419 switch (rate) { 420 case 1: 421 rate = 32000; 422 break; 423 case 2: 424 rate = 44100; 425 break; 426 case 3: 427 rate = 48000; 428 break; 429 default: 430 return -1; 431 } 432 return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate; 433 } 434 435 static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat) 436 { 437 int n; 438 439 *is_adat = 0; 440 if (rme32->rcreg & RME32_RCR_LOCK) { 441 /* ADAT rate */ 442 *is_adat = 1; 443 } 444 if (rme32->rcreg & RME32_RCR_ERF) { 445 return -1; 446 } 447 448 /* S/PDIF rate */ 449 n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) + 450 (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) + 451 (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2); 452 453 if (RME32_PRO_WITH_8414(rme32)) 454 switch (n) { /* supporting the CS8414 */ 455 case 0: 456 case 1: 457 case 2: 458 return -1; 459 case 3: 460 return 96000; 461 case 4: 462 return 88200; 463 case 5: 464 return 48000; 465 case 6: 466 return 44100; 467 case 7: 468 return 32000; 469 default: 470 return -1; 471 } 472 else 473 switch (n) { /* supporting the CS8412 */ 474 case 0: 475 return -1; 476 case 1: 477 return 48000; 478 case 2: 479 return 44100; 480 case 3: 481 return 32000; 482 case 4: 483 return 48000; 484 case 5: 485 return 44100; 486 case 6: 487 return 44056; 488 case 7: 489 return 32000; 490 default: 491 break; 492 } 493 return -1; 494 } 495 496 static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate) 497 { 498 int ds; 499 500 ds = rme32->wcreg & RME32_WCR_DS_BM; 501 switch (rate) { 502 case 32000: 503 rme32->wcreg &= ~RME32_WCR_DS_BM; 504 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 505 ~RME32_WCR_FREQ_1; 506 break; 507 case 44100: 508 rme32->wcreg &= ~RME32_WCR_DS_BM; 509 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 510 ~RME32_WCR_FREQ_0; 511 break; 512 case 48000: 513 rme32->wcreg &= ~RME32_WCR_DS_BM; 514 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 515 RME32_WCR_FREQ_1; 516 break; 517 case 64000: 518 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 519 return -EINVAL; 520 rme32->wcreg |= RME32_WCR_DS_BM; 521 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 522 ~RME32_WCR_FREQ_1; 523 break; 524 case 88200: 525 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 526 return -EINVAL; 527 rme32->wcreg |= RME32_WCR_DS_BM; 528 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) & 529 ~RME32_WCR_FREQ_0; 530 break; 531 case 96000: 532 if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO) 533 return -EINVAL; 534 rme32->wcreg |= RME32_WCR_DS_BM; 535 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 536 RME32_WCR_FREQ_1; 537 break; 538 default: 539 return -EINVAL; 540 } 541 if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) || 542 (ds && !(rme32->wcreg & RME32_WCR_DS_BM))) 543 { 544 /* change to/from double-speed: reset the DAC (if available) */ 545 snd_rme32_reset_dac(rme32); 546 } else { 547 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 548 } 549 return 0; 550 } 551 552 static int snd_rme32_setclockmode(struct rme32 * rme32, int mode) 553 { 554 switch (mode) { 555 case RME32_CLOCKMODE_SLAVE: 556 /* AutoSync */ 557 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) & 558 ~RME32_WCR_FREQ_1; 559 break; 560 case RME32_CLOCKMODE_MASTER_32: 561 /* Internal 32.0kHz */ 562 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) & 563 ~RME32_WCR_FREQ_1; 564 break; 565 case RME32_CLOCKMODE_MASTER_44: 566 /* Internal 44.1kHz */ 567 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) | 568 RME32_WCR_FREQ_1; 569 break; 570 case RME32_CLOCKMODE_MASTER_48: 571 /* Internal 48.0kHz */ 572 rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) | 573 RME32_WCR_FREQ_1; 574 break; 575 default: 576 return -EINVAL; 577 } 578 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 579 return 0; 580 } 581 582 static int snd_rme32_getclockmode(struct rme32 * rme32) 583 { 584 return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) + 585 (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1); 586 } 587 588 static int snd_rme32_setinputtype(struct rme32 * rme32, int type) 589 { 590 switch (type) { 591 case RME32_INPUT_OPTICAL: 592 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) & 593 ~RME32_WCR_INP_1; 594 break; 595 case RME32_INPUT_COAXIAL: 596 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) & 597 ~RME32_WCR_INP_1; 598 break; 599 case RME32_INPUT_INTERNAL: 600 rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) | 601 RME32_WCR_INP_1; 602 break; 603 case RME32_INPUT_XLR: 604 rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) | 605 RME32_WCR_INP_1; 606 break; 607 default: 608 return -EINVAL; 609 } 610 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 611 return 0; 612 } 613 614 static int snd_rme32_getinputtype(struct rme32 * rme32) 615 { 616 return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) + 617 (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1); 618 } 619 620 static void 621 snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback) 622 { 623 int frlog; 624 625 if (n_channels == 2) { 626 frlog = 1; 627 } else { 628 /* assume 8 channels */ 629 frlog = 3; 630 } 631 if (is_playback) { 632 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 633 rme32->playback_frlog = frlog; 634 } else { 635 frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1; 636 rme32->capture_frlog = frlog; 637 } 638 } 639 640 static int snd_rme32_setformat(struct rme32 *rme32, snd_pcm_format_t format) 641 { 642 switch (format) { 643 case SNDRV_PCM_FORMAT_S16_LE: 644 rme32->wcreg &= ~RME32_WCR_MODE24; 645 break; 646 case SNDRV_PCM_FORMAT_S32_LE: 647 rme32->wcreg |= RME32_WCR_MODE24; 648 break; 649 default: 650 return -EINVAL; 651 } 652 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 653 return 0; 654 } 655 656 static int 657 snd_rme32_playback_hw_params(struct snd_pcm_substream *substream, 658 struct snd_pcm_hw_params *params) 659 { 660 int err, rate, dummy; 661 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 662 struct snd_pcm_runtime *runtime = substream->runtime; 663 664 if (!rme32->fullduplex_mode) { 665 runtime->dma_area = (void __force *)(rme32->iobase + 666 RME32_IO_DATA_BUFFER); 667 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 668 runtime->dma_bytes = RME32_BUFFER_SIZE; 669 } 670 671 spin_lock_irq(&rme32->lock); 672 if ((rme32->rcreg & RME32_RCR_KMODE) && 673 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { 674 /* AutoSync */ 675 if ((int)params_rate(params) != rate) { 676 spin_unlock_irq(&rme32->lock); 677 return -EIO; 678 } 679 } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) { 680 spin_unlock_irq(&rme32->lock); 681 return err; 682 } 683 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) { 684 spin_unlock_irq(&rme32->lock); 685 return err; 686 } 687 688 snd_rme32_setframelog(rme32, params_channels(params), 1); 689 if (rme32->capture_periodsize != 0) { 690 if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) { 691 spin_unlock_irq(&rme32->lock); 692 return -EBUSY; 693 } 694 } 695 rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog; 696 /* S/PDIF setup */ 697 if ((rme32->wcreg & RME32_WCR_ADAT) == 0) { 698 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 699 rme32->wcreg |= rme32->wcreg_spdif_stream; 700 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 701 } 702 spin_unlock_irq(&rme32->lock); 703 704 return 0; 705 } 706 707 static int 708 snd_rme32_capture_hw_params(struct snd_pcm_substream *substream, 709 struct snd_pcm_hw_params *params) 710 { 711 int err, isadat, rate; 712 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 713 struct snd_pcm_runtime *runtime = substream->runtime; 714 715 if (!rme32->fullduplex_mode) { 716 runtime->dma_area = (void __force *)rme32->iobase + 717 RME32_IO_DATA_BUFFER; 718 runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER; 719 runtime->dma_bytes = RME32_BUFFER_SIZE; 720 } 721 722 spin_lock_irq(&rme32->lock); 723 /* enable AutoSync for record-preparing */ 724 rme32->wcreg |= RME32_WCR_AUTOSYNC; 725 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 726 727 if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) { 728 spin_unlock_irq(&rme32->lock); 729 return err; 730 } 731 if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) { 732 spin_unlock_irq(&rme32->lock); 733 return err; 734 } 735 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { 736 if ((int)params_rate(params) != rate) { 737 spin_unlock_irq(&rme32->lock); 738 return -EIO; 739 } 740 if ((isadat && runtime->hw.channels_min == 2) || 741 (!isadat && runtime->hw.channels_min == 8)) { 742 spin_unlock_irq(&rme32->lock); 743 return -EIO; 744 } 745 } 746 /* AutoSync off for recording */ 747 rme32->wcreg &= ~RME32_WCR_AUTOSYNC; 748 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 749 750 snd_rme32_setframelog(rme32, params_channels(params), 0); 751 if (rme32->playback_periodsize != 0) { 752 if (params_period_size(params) << rme32->capture_frlog != 753 rme32->playback_periodsize) { 754 spin_unlock_irq(&rme32->lock); 755 return -EBUSY; 756 } 757 } 758 rme32->capture_periodsize = 759 params_period_size(params) << rme32->capture_frlog; 760 spin_unlock_irq(&rme32->lock); 761 762 return 0; 763 } 764 765 static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause) 766 { 767 if (!from_pause) { 768 writel(0, rme32->iobase + RME32_IO_RESET_POS); 769 } 770 771 rme32->wcreg |= RME32_WCR_START; 772 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 773 } 774 775 static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause) 776 { 777 /* 778 * Check if there is an unconfirmed IRQ, if so confirm it, or else 779 * the hardware will not stop generating interrupts 780 */ 781 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 782 if (rme32->rcreg & RME32_RCR_IRQ) { 783 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 784 } 785 rme32->wcreg &= ~RME32_WCR_START; 786 if (rme32->wcreg & RME32_WCR_SEL) 787 rme32->wcreg |= RME32_WCR_MUTE; 788 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 789 if (! to_pause) 790 writel(0, rme32->iobase + RME32_IO_RESET_POS); 791 } 792 793 static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id) 794 { 795 struct rme32 *rme32 = (struct rme32 *) dev_id; 796 797 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 798 if (!(rme32->rcreg & RME32_RCR_IRQ)) { 799 return IRQ_NONE; 800 } else { 801 if (rme32->capture_substream) { 802 snd_pcm_period_elapsed(rme32->capture_substream); 803 } 804 if (rme32->playback_substream) { 805 snd_pcm_period_elapsed(rme32->playback_substream); 806 } 807 writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ); 808 } 809 return IRQ_HANDLED; 810 } 811 812 static const unsigned int period_bytes[] = { RME32_BLOCK_SIZE }; 813 814 static const struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = { 815 .count = ARRAY_SIZE(period_bytes), 816 .list = period_bytes, 817 .mask = 0 818 }; 819 820 static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime) 821 { 822 if (! rme32->fullduplex_mode) { 823 snd_pcm_hw_constraint_single(runtime, 824 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 825 RME32_BUFFER_SIZE); 826 snd_pcm_hw_constraint_list(runtime, 0, 827 SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 828 &hw_constraints_period_bytes); 829 } 830 } 831 832 static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream) 833 { 834 int rate, dummy; 835 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 836 struct snd_pcm_runtime *runtime = substream->runtime; 837 838 snd_pcm_set_sync(substream); 839 840 spin_lock_irq(&rme32->lock); 841 if (rme32->playback_substream != NULL) { 842 spin_unlock_irq(&rme32->lock); 843 return -EBUSY; 844 } 845 rme32->wcreg &= ~RME32_WCR_ADAT; 846 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 847 rme32->playback_substream = substream; 848 spin_unlock_irq(&rme32->lock); 849 850 if (rme32->fullduplex_mode) 851 runtime->hw = snd_rme32_spdif_fd_info; 852 else 853 runtime->hw = snd_rme32_spdif_info; 854 if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) { 855 runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 856 runtime->hw.rate_max = 96000; 857 } 858 if ((rme32->rcreg & RME32_RCR_KMODE) && 859 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { 860 /* AutoSync */ 861 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 862 runtime->hw.rate_min = rate; 863 runtime->hw.rate_max = rate; 864 } 865 866 snd_rme32_set_buffer_constraint(rme32, runtime); 867 868 rme32->wcreg_spdif_stream = rme32->wcreg_spdif; 869 rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE; 870 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 871 SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id); 872 return 0; 873 } 874 875 static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream) 876 { 877 int isadat, rate; 878 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 879 struct snd_pcm_runtime *runtime = substream->runtime; 880 881 snd_pcm_set_sync(substream); 882 883 spin_lock_irq(&rme32->lock); 884 if (rme32->capture_substream != NULL) { 885 spin_unlock_irq(&rme32->lock); 886 return -EBUSY; 887 } 888 rme32->capture_substream = substream; 889 spin_unlock_irq(&rme32->lock); 890 891 if (rme32->fullduplex_mode) 892 runtime->hw = snd_rme32_spdif_fd_info; 893 else 894 runtime->hw = snd_rme32_spdif_info; 895 if (RME32_PRO_WITH_8414(rme32)) { 896 runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000; 897 runtime->hw.rate_max = 96000; 898 } 899 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { 900 if (isadat) { 901 return -EIO; 902 } 903 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 904 runtime->hw.rate_min = rate; 905 runtime->hw.rate_max = rate; 906 } 907 908 snd_rme32_set_buffer_constraint(rme32, runtime); 909 910 return 0; 911 } 912 913 static int 914 snd_rme32_playback_adat_open(struct snd_pcm_substream *substream) 915 { 916 int rate, dummy; 917 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 918 struct snd_pcm_runtime *runtime = substream->runtime; 919 920 snd_pcm_set_sync(substream); 921 922 spin_lock_irq(&rme32->lock); 923 if (rme32->playback_substream != NULL) { 924 spin_unlock_irq(&rme32->lock); 925 return -EBUSY; 926 } 927 rme32->wcreg |= RME32_WCR_ADAT; 928 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 929 rme32->playback_substream = substream; 930 spin_unlock_irq(&rme32->lock); 931 932 if (rme32->fullduplex_mode) 933 runtime->hw = snd_rme32_adat_fd_info; 934 else 935 runtime->hw = snd_rme32_adat_info; 936 if ((rme32->rcreg & RME32_RCR_KMODE) && 937 (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) { 938 /* AutoSync */ 939 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 940 runtime->hw.rate_min = rate; 941 runtime->hw.rate_max = rate; 942 } 943 944 snd_rme32_set_buffer_constraint(rme32, runtime); 945 return 0; 946 } 947 948 static int 949 snd_rme32_capture_adat_open(struct snd_pcm_substream *substream) 950 { 951 int isadat, rate; 952 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 953 struct snd_pcm_runtime *runtime = substream->runtime; 954 955 if (rme32->fullduplex_mode) 956 runtime->hw = snd_rme32_adat_fd_info; 957 else 958 runtime->hw = snd_rme32_adat_info; 959 if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) { 960 if (!isadat) { 961 return -EIO; 962 } 963 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate); 964 runtime->hw.rate_min = rate; 965 runtime->hw.rate_max = rate; 966 } 967 968 snd_pcm_set_sync(substream); 969 970 spin_lock_irq(&rme32->lock); 971 if (rme32->capture_substream != NULL) { 972 spin_unlock_irq(&rme32->lock); 973 return -EBUSY; 974 } 975 rme32->capture_substream = substream; 976 spin_unlock_irq(&rme32->lock); 977 978 snd_rme32_set_buffer_constraint(rme32, runtime); 979 return 0; 980 } 981 982 static int snd_rme32_playback_close(struct snd_pcm_substream *substream) 983 { 984 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 985 int spdif = 0; 986 987 spin_lock_irq(&rme32->lock); 988 rme32->playback_substream = NULL; 989 rme32->playback_periodsize = 0; 990 spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0; 991 spin_unlock_irq(&rme32->lock); 992 if (spdif) { 993 rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE; 994 snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE | 995 SNDRV_CTL_EVENT_MASK_INFO, 996 &rme32->spdif_ctl->id); 997 } 998 return 0; 999 } 1000 1001 static int snd_rme32_capture_close(struct snd_pcm_substream *substream) 1002 { 1003 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1004 1005 spin_lock_irq(&rme32->lock); 1006 rme32->capture_substream = NULL; 1007 rme32->capture_periodsize = 0; 1008 spin_unlock_irq(&rme32->lock); 1009 return 0; 1010 } 1011 1012 static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream) 1013 { 1014 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1015 1016 spin_lock_irq(&rme32->lock); 1017 if (rme32->fullduplex_mode) { 1018 memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm)); 1019 rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 1020 rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1021 } else { 1022 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1023 } 1024 if (rme32->wcreg & RME32_WCR_SEL) 1025 rme32->wcreg &= ~RME32_WCR_MUTE; 1026 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1027 spin_unlock_irq(&rme32->lock); 1028 return 0; 1029 } 1030 1031 static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream) 1032 { 1033 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1034 1035 spin_lock_irq(&rme32->lock); 1036 if (rme32->fullduplex_mode) { 1037 memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm)); 1038 rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE; 1039 rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2; 1040 rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream); 1041 } else { 1042 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1043 } 1044 spin_unlock_irq(&rme32->lock); 1045 return 0; 1046 } 1047 1048 static int 1049 snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 1050 { 1051 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1052 struct snd_pcm_substream *s; 1053 1054 spin_lock(&rme32->lock); 1055 snd_pcm_group_for_each_entry(s, substream) { 1056 if (s != rme32->playback_substream && 1057 s != rme32->capture_substream) 1058 continue; 1059 switch (cmd) { 1060 case SNDRV_PCM_TRIGGER_START: 1061 rme32->running |= (1 << s->stream); 1062 if (rme32->fullduplex_mode) { 1063 /* remember the current DMA position */ 1064 if (s == rme32->playback_substream) { 1065 rme32->playback_pcm.hw_io = 1066 rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1067 } else { 1068 rme32->capture_pcm.hw_io = 1069 rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32); 1070 } 1071 } 1072 break; 1073 case SNDRV_PCM_TRIGGER_STOP: 1074 rme32->running &= ~(1 << s->stream); 1075 break; 1076 } 1077 snd_pcm_trigger_done(s, substream); 1078 } 1079 1080 switch (cmd) { 1081 case SNDRV_PCM_TRIGGER_START: 1082 if (rme32->running && ! RME32_ISWORKING(rme32)) 1083 snd_rme32_pcm_start(rme32, 0); 1084 break; 1085 case SNDRV_PCM_TRIGGER_STOP: 1086 if (! rme32->running && RME32_ISWORKING(rme32)) 1087 snd_rme32_pcm_stop(rme32, 0); 1088 break; 1089 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 1090 if (rme32->running && RME32_ISWORKING(rme32)) 1091 snd_rme32_pcm_stop(rme32, 1); 1092 break; 1093 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 1094 if (rme32->running && ! RME32_ISWORKING(rme32)) 1095 snd_rme32_pcm_start(rme32, 1); 1096 break; 1097 } 1098 spin_unlock(&rme32->lock); 1099 return 0; 1100 } 1101 1102 /* pointer callback for halfduplex mode */ 1103 static snd_pcm_uframes_t 1104 snd_rme32_playback_pointer(struct snd_pcm_substream *substream) 1105 { 1106 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1107 return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog; 1108 } 1109 1110 static snd_pcm_uframes_t 1111 snd_rme32_capture_pointer(struct snd_pcm_substream *substream) 1112 { 1113 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1114 return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog; 1115 } 1116 1117 1118 /* ack and pointer callbacks for fullduplex mode */ 1119 static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream, 1120 struct snd_pcm_indirect *rec, size_t bytes) 1121 { 1122 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1123 memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1124 substream->runtime->dma_area + rec->sw_data, bytes); 1125 } 1126 1127 static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream) 1128 { 1129 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1130 struct snd_pcm_indirect *rec, *cprec; 1131 1132 rec = &rme32->playback_pcm; 1133 cprec = &rme32->capture_pcm; 1134 spin_lock(&rme32->lock); 1135 rec->hw_queue_size = RME32_BUFFER_SIZE; 1136 if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE)) 1137 rec->hw_queue_size -= cprec->hw_ready; 1138 spin_unlock(&rme32->lock); 1139 return snd_pcm_indirect_playback_transfer(substream, rec, 1140 snd_rme32_pb_trans_copy); 1141 } 1142 1143 static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream, 1144 struct snd_pcm_indirect *rec, size_t bytes) 1145 { 1146 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1147 memcpy_fromio(substream->runtime->dma_area + rec->sw_data, 1148 rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data, 1149 bytes); 1150 } 1151 1152 static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream) 1153 { 1154 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1155 return snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm, 1156 snd_rme32_cp_trans_copy); 1157 } 1158 1159 static snd_pcm_uframes_t 1160 snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream) 1161 { 1162 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1163 return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm, 1164 snd_rme32_pcm_byteptr(rme32)); 1165 } 1166 1167 static snd_pcm_uframes_t 1168 snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream) 1169 { 1170 struct rme32 *rme32 = snd_pcm_substream_chip(substream); 1171 return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm, 1172 snd_rme32_pcm_byteptr(rme32)); 1173 } 1174 1175 /* for halfduplex mode */ 1176 static const struct snd_pcm_ops snd_rme32_playback_spdif_ops = { 1177 .open = snd_rme32_playback_spdif_open, 1178 .close = snd_rme32_playback_close, 1179 .hw_params = snd_rme32_playback_hw_params, 1180 .prepare = snd_rme32_playback_prepare, 1181 .trigger = snd_rme32_pcm_trigger, 1182 .pointer = snd_rme32_playback_pointer, 1183 .copy_user = snd_rme32_playback_copy, 1184 .copy_kernel = snd_rme32_playback_copy_kernel, 1185 .fill_silence = snd_rme32_playback_silence, 1186 .mmap = snd_pcm_lib_mmap_iomem, 1187 }; 1188 1189 static const struct snd_pcm_ops snd_rme32_capture_spdif_ops = { 1190 .open = snd_rme32_capture_spdif_open, 1191 .close = snd_rme32_capture_close, 1192 .hw_params = snd_rme32_capture_hw_params, 1193 .prepare = snd_rme32_capture_prepare, 1194 .trigger = snd_rme32_pcm_trigger, 1195 .pointer = snd_rme32_capture_pointer, 1196 .copy_user = snd_rme32_capture_copy, 1197 .copy_kernel = snd_rme32_capture_copy_kernel, 1198 .mmap = snd_pcm_lib_mmap_iomem, 1199 }; 1200 1201 static const struct snd_pcm_ops snd_rme32_playback_adat_ops = { 1202 .open = snd_rme32_playback_adat_open, 1203 .close = snd_rme32_playback_close, 1204 .hw_params = snd_rme32_playback_hw_params, 1205 .prepare = snd_rme32_playback_prepare, 1206 .trigger = snd_rme32_pcm_trigger, 1207 .pointer = snd_rme32_playback_pointer, 1208 .copy_user = snd_rme32_playback_copy, 1209 .copy_kernel = snd_rme32_playback_copy_kernel, 1210 .fill_silence = snd_rme32_playback_silence, 1211 .mmap = snd_pcm_lib_mmap_iomem, 1212 }; 1213 1214 static const struct snd_pcm_ops snd_rme32_capture_adat_ops = { 1215 .open = snd_rme32_capture_adat_open, 1216 .close = snd_rme32_capture_close, 1217 .hw_params = snd_rme32_capture_hw_params, 1218 .prepare = snd_rme32_capture_prepare, 1219 .trigger = snd_rme32_pcm_trigger, 1220 .pointer = snd_rme32_capture_pointer, 1221 .copy_user = snd_rme32_capture_copy, 1222 .copy_kernel = snd_rme32_capture_copy_kernel, 1223 .mmap = snd_pcm_lib_mmap_iomem, 1224 }; 1225 1226 /* for fullduplex mode */ 1227 static const struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = { 1228 .open = snd_rme32_playback_spdif_open, 1229 .close = snd_rme32_playback_close, 1230 .hw_params = snd_rme32_playback_hw_params, 1231 .prepare = snd_rme32_playback_prepare, 1232 .trigger = snd_rme32_pcm_trigger, 1233 .pointer = snd_rme32_playback_fd_pointer, 1234 .ack = snd_rme32_playback_fd_ack, 1235 }; 1236 1237 static const struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = { 1238 .open = snd_rme32_capture_spdif_open, 1239 .close = snd_rme32_capture_close, 1240 .hw_params = snd_rme32_capture_hw_params, 1241 .prepare = snd_rme32_capture_prepare, 1242 .trigger = snd_rme32_pcm_trigger, 1243 .pointer = snd_rme32_capture_fd_pointer, 1244 .ack = snd_rme32_capture_fd_ack, 1245 }; 1246 1247 static const struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = { 1248 .open = snd_rme32_playback_adat_open, 1249 .close = snd_rme32_playback_close, 1250 .hw_params = snd_rme32_playback_hw_params, 1251 .prepare = snd_rme32_playback_prepare, 1252 .trigger = snd_rme32_pcm_trigger, 1253 .pointer = snd_rme32_playback_fd_pointer, 1254 .ack = snd_rme32_playback_fd_ack, 1255 }; 1256 1257 static const struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = { 1258 .open = snd_rme32_capture_adat_open, 1259 .close = snd_rme32_capture_close, 1260 .hw_params = snd_rme32_capture_hw_params, 1261 .prepare = snd_rme32_capture_prepare, 1262 .trigger = snd_rme32_pcm_trigger, 1263 .pointer = snd_rme32_capture_fd_pointer, 1264 .ack = snd_rme32_capture_fd_ack, 1265 }; 1266 1267 static void snd_rme32_free(void *private_data) 1268 { 1269 struct rme32 *rme32 = (struct rme32 *) private_data; 1270 1271 if (rme32 == NULL) { 1272 return; 1273 } 1274 if (rme32->irq >= 0) { 1275 snd_rme32_pcm_stop(rme32, 0); 1276 free_irq(rme32->irq, (void *) rme32); 1277 rme32->irq = -1; 1278 } 1279 if (rme32->iobase) { 1280 iounmap(rme32->iobase); 1281 rme32->iobase = NULL; 1282 } 1283 if (rme32->port) { 1284 pci_release_regions(rme32->pci); 1285 rme32->port = 0; 1286 } 1287 pci_disable_device(rme32->pci); 1288 } 1289 1290 static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm) 1291 { 1292 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1293 rme32->spdif_pcm = NULL; 1294 } 1295 1296 static void 1297 snd_rme32_free_adat_pcm(struct snd_pcm *pcm) 1298 { 1299 struct rme32 *rme32 = (struct rme32 *) pcm->private_data; 1300 rme32->adat_pcm = NULL; 1301 } 1302 1303 static int snd_rme32_create(struct rme32 *rme32) 1304 { 1305 struct pci_dev *pci = rme32->pci; 1306 int err; 1307 1308 rme32->irq = -1; 1309 spin_lock_init(&rme32->lock); 1310 1311 if ((err = pci_enable_device(pci)) < 0) 1312 return err; 1313 1314 if ((err = pci_request_regions(pci, "RME32")) < 0) 1315 return err; 1316 rme32->port = pci_resource_start(rme32->pci, 0); 1317 1318 rme32->iobase = ioremap(rme32->port, RME32_IO_SIZE); 1319 if (!rme32->iobase) { 1320 dev_err(rme32->card->dev, 1321 "unable to remap memory region 0x%lx-0x%lx\n", 1322 rme32->port, rme32->port + RME32_IO_SIZE - 1); 1323 return -ENOMEM; 1324 } 1325 1326 if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED, 1327 KBUILD_MODNAME, rme32)) { 1328 dev_err(rme32->card->dev, "unable to grab IRQ %d\n", pci->irq); 1329 return -EBUSY; 1330 } 1331 rme32->irq = pci->irq; 1332 rme32->card->sync_irq = rme32->irq; 1333 1334 /* read the card's revision number */ 1335 pci_read_config_byte(pci, 8, &rme32->rev); 1336 1337 /* set up ALSA pcm device for S/PDIF */ 1338 if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) { 1339 return err; 1340 } 1341 rme32->spdif_pcm->private_data = rme32; 1342 rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm; 1343 strcpy(rme32->spdif_pcm->name, "Digi32 IEC958"); 1344 if (rme32->fullduplex_mode) { 1345 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1346 &snd_rme32_playback_spdif_fd_ops); 1347 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1348 &snd_rme32_capture_spdif_fd_ops); 1349 snd_pcm_set_managed_buffer_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1350 NULL, 0, RME32_MID_BUFFER_SIZE); 1351 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1352 } else { 1353 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1354 &snd_rme32_playback_spdif_ops); 1355 snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, 1356 &snd_rme32_capture_spdif_ops); 1357 rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1358 } 1359 1360 /* set up ALSA pcm device for ADAT */ 1361 if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) || 1362 (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) { 1363 /* ADAT is not available on DIGI32 and DIGI32 Pro */ 1364 rme32->adat_pcm = NULL; 1365 } 1366 else { 1367 if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1, 1368 1, 1, &rme32->adat_pcm)) < 0) 1369 { 1370 return err; 1371 } 1372 rme32->adat_pcm->private_data = rme32; 1373 rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm; 1374 strcpy(rme32->adat_pcm->name, "Digi32 ADAT"); 1375 if (rme32->fullduplex_mode) { 1376 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1377 &snd_rme32_playback_adat_fd_ops); 1378 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1379 &snd_rme32_capture_adat_fd_ops); 1380 snd_pcm_set_managed_buffer_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS, 1381 NULL, 1382 0, RME32_MID_BUFFER_SIZE); 1383 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX; 1384 } else { 1385 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, 1386 &snd_rme32_playback_adat_ops); 1387 snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, 1388 &snd_rme32_capture_adat_ops); 1389 rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX; 1390 } 1391 } 1392 1393 1394 rme32->playback_periodsize = 0; 1395 rme32->capture_periodsize = 0; 1396 1397 /* make sure playback/capture is stopped, if by some reason active */ 1398 snd_rme32_pcm_stop(rme32, 0); 1399 1400 /* reset DAC */ 1401 snd_rme32_reset_dac(rme32); 1402 1403 /* reset buffer pointer */ 1404 writel(0, rme32->iobase + RME32_IO_RESET_POS); 1405 1406 /* set default values in registers */ 1407 rme32->wcreg = RME32_WCR_SEL | /* normal playback */ 1408 RME32_WCR_INP_0 | /* input select */ 1409 RME32_WCR_MUTE; /* muting on */ 1410 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1411 1412 1413 /* init switch interface */ 1414 if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) { 1415 return err; 1416 } 1417 1418 /* init proc interface */ 1419 snd_rme32_proc_init(rme32); 1420 1421 rme32->capture_substream = NULL; 1422 rme32->playback_substream = NULL; 1423 1424 return 0; 1425 } 1426 1427 /* 1428 * proc interface 1429 */ 1430 1431 static void 1432 snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer) 1433 { 1434 int n; 1435 struct rme32 *rme32 = (struct rme32 *) entry->private_data; 1436 1437 rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER); 1438 1439 snd_iprintf(buffer, rme32->card->longname); 1440 snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1); 1441 1442 snd_iprintf(buffer, "\nGeneral settings\n"); 1443 if (rme32->fullduplex_mode) 1444 snd_iprintf(buffer, " Full-duplex mode\n"); 1445 else 1446 snd_iprintf(buffer, " Half-duplex mode\n"); 1447 if (RME32_PRO_WITH_8414(rme32)) { 1448 snd_iprintf(buffer, " receiver: CS8414\n"); 1449 } else { 1450 snd_iprintf(buffer, " receiver: CS8412\n"); 1451 } 1452 if (rme32->wcreg & RME32_WCR_MODE24) { 1453 snd_iprintf(buffer, " format: 24 bit"); 1454 } else { 1455 snd_iprintf(buffer, " format: 16 bit"); 1456 } 1457 if (rme32->wcreg & RME32_WCR_MONO) { 1458 snd_iprintf(buffer, ", Mono\n"); 1459 } else { 1460 snd_iprintf(buffer, ", Stereo\n"); 1461 } 1462 1463 snd_iprintf(buffer, "\nInput settings\n"); 1464 switch (snd_rme32_getinputtype(rme32)) { 1465 case RME32_INPUT_OPTICAL: 1466 snd_iprintf(buffer, " input: optical"); 1467 break; 1468 case RME32_INPUT_COAXIAL: 1469 snd_iprintf(buffer, " input: coaxial"); 1470 break; 1471 case RME32_INPUT_INTERNAL: 1472 snd_iprintf(buffer, " input: internal"); 1473 break; 1474 case RME32_INPUT_XLR: 1475 snd_iprintf(buffer, " input: XLR"); 1476 break; 1477 } 1478 if (snd_rme32_capture_getrate(rme32, &n) < 0) { 1479 snd_iprintf(buffer, "\n sample rate: no valid signal\n"); 1480 } else { 1481 if (n) { 1482 snd_iprintf(buffer, " (8 channels)\n"); 1483 } else { 1484 snd_iprintf(buffer, " (2 channels)\n"); 1485 } 1486 snd_iprintf(buffer, " sample rate: %d Hz\n", 1487 snd_rme32_capture_getrate(rme32, &n)); 1488 } 1489 1490 snd_iprintf(buffer, "\nOutput settings\n"); 1491 if (rme32->wcreg & RME32_WCR_SEL) { 1492 snd_iprintf(buffer, " output signal: normal playback"); 1493 } else { 1494 snd_iprintf(buffer, " output signal: same as input"); 1495 } 1496 if (rme32->wcreg & RME32_WCR_MUTE) { 1497 snd_iprintf(buffer, " (muted)\n"); 1498 } else { 1499 snd_iprintf(buffer, "\n"); 1500 } 1501 1502 /* master output frequency */ 1503 if (! 1504 ((!(rme32->wcreg & RME32_WCR_FREQ_0)) 1505 && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) { 1506 snd_iprintf(buffer, " sample rate: %d Hz\n", 1507 snd_rme32_playback_getrate(rme32)); 1508 } 1509 if (rme32->rcreg & RME32_RCR_KMODE) { 1510 snd_iprintf(buffer, " sample clock source: AutoSync\n"); 1511 } else { 1512 snd_iprintf(buffer, " sample clock source: Internal\n"); 1513 } 1514 if (rme32->wcreg & RME32_WCR_PRO) { 1515 snd_iprintf(buffer, " format: AES/EBU (professional)\n"); 1516 } else { 1517 snd_iprintf(buffer, " format: IEC958 (consumer)\n"); 1518 } 1519 if (rme32->wcreg & RME32_WCR_EMP) { 1520 snd_iprintf(buffer, " emphasis: on\n"); 1521 } else { 1522 snd_iprintf(buffer, " emphasis: off\n"); 1523 } 1524 } 1525 1526 static void snd_rme32_proc_init(struct rme32 *rme32) 1527 { 1528 snd_card_ro_proc_new(rme32->card, "rme32", rme32, snd_rme32_proc_read); 1529 } 1530 1531 /* 1532 * control interface 1533 */ 1534 1535 #define snd_rme32_info_loopback_control snd_ctl_boolean_mono_info 1536 1537 static int 1538 snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol, 1539 struct snd_ctl_elem_value *ucontrol) 1540 { 1541 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1542 1543 spin_lock_irq(&rme32->lock); 1544 ucontrol->value.integer.value[0] = 1545 rme32->wcreg & RME32_WCR_SEL ? 0 : 1; 1546 spin_unlock_irq(&rme32->lock); 1547 return 0; 1548 } 1549 static int 1550 snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol, 1551 struct snd_ctl_elem_value *ucontrol) 1552 { 1553 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1554 unsigned int val; 1555 int change; 1556 1557 val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL; 1558 spin_lock_irq(&rme32->lock); 1559 val = (rme32->wcreg & ~RME32_WCR_SEL) | val; 1560 change = val != rme32->wcreg; 1561 if (ucontrol->value.integer.value[0]) 1562 val &= ~RME32_WCR_MUTE; 1563 else 1564 val |= RME32_WCR_MUTE; 1565 rme32->wcreg = val; 1566 writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1567 spin_unlock_irq(&rme32->lock); 1568 return change; 1569 } 1570 1571 static int 1572 snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol, 1573 struct snd_ctl_elem_info *uinfo) 1574 { 1575 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1576 static const char * const texts[4] = { 1577 "Optical", "Coaxial", "Internal", "XLR" 1578 }; 1579 int num_items; 1580 1581 switch (rme32->pci->device) { 1582 case PCI_DEVICE_ID_RME_DIGI32: 1583 case PCI_DEVICE_ID_RME_DIGI32_8: 1584 num_items = 3; 1585 break; 1586 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1587 num_items = 4; 1588 break; 1589 default: 1590 snd_BUG(); 1591 return -EINVAL; 1592 } 1593 return snd_ctl_enum_info(uinfo, 1, num_items, texts); 1594 } 1595 static int 1596 snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol, 1597 struct snd_ctl_elem_value *ucontrol) 1598 { 1599 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1600 unsigned int items = 3; 1601 1602 spin_lock_irq(&rme32->lock); 1603 ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32); 1604 1605 switch (rme32->pci->device) { 1606 case PCI_DEVICE_ID_RME_DIGI32: 1607 case PCI_DEVICE_ID_RME_DIGI32_8: 1608 items = 3; 1609 break; 1610 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1611 items = 4; 1612 break; 1613 default: 1614 snd_BUG(); 1615 break; 1616 } 1617 if (ucontrol->value.enumerated.item[0] >= items) { 1618 ucontrol->value.enumerated.item[0] = items - 1; 1619 } 1620 1621 spin_unlock_irq(&rme32->lock); 1622 return 0; 1623 } 1624 static int 1625 snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol, 1626 struct snd_ctl_elem_value *ucontrol) 1627 { 1628 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1629 unsigned int val; 1630 int change, items = 3; 1631 1632 switch (rme32->pci->device) { 1633 case PCI_DEVICE_ID_RME_DIGI32: 1634 case PCI_DEVICE_ID_RME_DIGI32_8: 1635 items = 3; 1636 break; 1637 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1638 items = 4; 1639 break; 1640 default: 1641 snd_BUG(); 1642 break; 1643 } 1644 val = ucontrol->value.enumerated.item[0] % items; 1645 1646 spin_lock_irq(&rme32->lock); 1647 change = val != (unsigned int)snd_rme32_getinputtype(rme32); 1648 snd_rme32_setinputtype(rme32, val); 1649 spin_unlock_irq(&rme32->lock); 1650 return change; 1651 } 1652 1653 static int 1654 snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol, 1655 struct snd_ctl_elem_info *uinfo) 1656 { 1657 static const char * const texts[4] = { "AutoSync", 1658 "Internal 32.0kHz", 1659 "Internal 44.1kHz", 1660 "Internal 48.0kHz" }; 1661 1662 return snd_ctl_enum_info(uinfo, 1, 4, texts); 1663 } 1664 static int 1665 snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol, 1666 struct snd_ctl_elem_value *ucontrol) 1667 { 1668 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1669 1670 spin_lock_irq(&rme32->lock); 1671 ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32); 1672 spin_unlock_irq(&rme32->lock); 1673 return 0; 1674 } 1675 static int 1676 snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol, 1677 struct snd_ctl_elem_value *ucontrol) 1678 { 1679 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1680 unsigned int val; 1681 int change; 1682 1683 val = ucontrol->value.enumerated.item[0] % 3; 1684 spin_lock_irq(&rme32->lock); 1685 change = val != (unsigned int)snd_rme32_getclockmode(rme32); 1686 snd_rme32_setclockmode(rme32, val); 1687 spin_unlock_irq(&rme32->lock); 1688 return change; 1689 } 1690 1691 static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes) 1692 { 1693 u32 val = 0; 1694 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0; 1695 if (val & RME32_WCR_PRO) 1696 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1697 else 1698 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0; 1699 return val; 1700 } 1701 1702 static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val) 1703 { 1704 aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0); 1705 if (val & RME32_WCR_PRO) 1706 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0; 1707 else 1708 aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0; 1709 } 1710 1711 static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol, 1712 struct snd_ctl_elem_info *uinfo) 1713 { 1714 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1715 uinfo->count = 1; 1716 return 0; 1717 } 1718 1719 static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol, 1720 struct snd_ctl_elem_value *ucontrol) 1721 { 1722 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1723 1724 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1725 rme32->wcreg_spdif); 1726 return 0; 1727 } 1728 1729 static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol, 1730 struct snd_ctl_elem_value *ucontrol) 1731 { 1732 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1733 int change; 1734 u32 val; 1735 1736 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1737 spin_lock_irq(&rme32->lock); 1738 change = val != rme32->wcreg_spdif; 1739 rme32->wcreg_spdif = val; 1740 spin_unlock_irq(&rme32->lock); 1741 return change; 1742 } 1743 1744 static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol, 1745 struct snd_ctl_elem_info *uinfo) 1746 { 1747 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1748 uinfo->count = 1; 1749 return 0; 1750 } 1751 1752 static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol, 1753 struct snd_ctl_elem_value * 1754 ucontrol) 1755 { 1756 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1757 1758 snd_rme32_convert_to_aes(&ucontrol->value.iec958, 1759 rme32->wcreg_spdif_stream); 1760 return 0; 1761 } 1762 1763 static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol, 1764 struct snd_ctl_elem_value * 1765 ucontrol) 1766 { 1767 struct rme32 *rme32 = snd_kcontrol_chip(kcontrol); 1768 int change; 1769 u32 val; 1770 1771 val = snd_rme32_convert_from_aes(&ucontrol->value.iec958); 1772 spin_lock_irq(&rme32->lock); 1773 change = val != rme32->wcreg_spdif_stream; 1774 rme32->wcreg_spdif_stream = val; 1775 rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP); 1776 rme32->wcreg |= val; 1777 writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER); 1778 spin_unlock_irq(&rme32->lock); 1779 return change; 1780 } 1781 1782 static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol, 1783 struct snd_ctl_elem_info *uinfo) 1784 { 1785 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958; 1786 uinfo->count = 1; 1787 return 0; 1788 } 1789 1790 static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol, 1791 struct snd_ctl_elem_value * 1792 ucontrol) 1793 { 1794 ucontrol->value.iec958.status[0] = kcontrol->private_value; 1795 return 0; 1796 } 1797 1798 static const struct snd_kcontrol_new snd_rme32_controls[] = { 1799 { 1800 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1801 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT), 1802 .info = snd_rme32_control_spdif_info, 1803 .get = snd_rme32_control_spdif_get, 1804 .put = snd_rme32_control_spdif_put 1805 }, 1806 { 1807 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE, 1808 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1809 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM), 1810 .info = snd_rme32_control_spdif_stream_info, 1811 .get = snd_rme32_control_spdif_stream_get, 1812 .put = snd_rme32_control_spdif_stream_put 1813 }, 1814 { 1815 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1816 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1817 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK), 1818 .info = snd_rme32_control_spdif_mask_info, 1819 .get = snd_rme32_control_spdif_mask_get, 1820 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS 1821 }, 1822 { 1823 .access = SNDRV_CTL_ELEM_ACCESS_READ, 1824 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1825 .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK), 1826 .info = snd_rme32_control_spdif_mask_info, 1827 .get = snd_rme32_control_spdif_mask_get, 1828 .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS 1829 }, 1830 { 1831 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1832 .name = "Input Connector", 1833 .info = snd_rme32_info_inputtype_control, 1834 .get = snd_rme32_get_inputtype_control, 1835 .put = snd_rme32_put_inputtype_control 1836 }, 1837 { 1838 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1839 .name = "Loopback Input", 1840 .info = snd_rme32_info_loopback_control, 1841 .get = snd_rme32_get_loopback_control, 1842 .put = snd_rme32_put_loopback_control 1843 }, 1844 { 1845 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, 1846 .name = "Sample Clock Source", 1847 .info = snd_rme32_info_clockmode_control, 1848 .get = snd_rme32_get_clockmode_control, 1849 .put = snd_rme32_put_clockmode_control 1850 } 1851 }; 1852 1853 static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32) 1854 { 1855 int idx, err; 1856 struct snd_kcontrol *kctl; 1857 1858 for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) { 1859 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0) 1860 return err; 1861 if (idx == 1) /* IEC958 (S/PDIF) Stream */ 1862 rme32->spdif_ctl = kctl; 1863 } 1864 1865 return 0; 1866 } 1867 1868 /* 1869 * Card initialisation 1870 */ 1871 1872 static void snd_rme32_card_free(struct snd_card *card) 1873 { 1874 snd_rme32_free(card->private_data); 1875 } 1876 1877 static int 1878 snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1879 { 1880 static int dev; 1881 struct rme32 *rme32; 1882 struct snd_card *card; 1883 int err; 1884 1885 if (dev >= SNDRV_CARDS) { 1886 return -ENODEV; 1887 } 1888 if (!enable[dev]) { 1889 dev++; 1890 return -ENOENT; 1891 } 1892 1893 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 1894 sizeof(struct rme32), &card); 1895 if (err < 0) 1896 return err; 1897 card->private_free = snd_rme32_card_free; 1898 rme32 = (struct rme32 *) card->private_data; 1899 rme32->card = card; 1900 rme32->pci = pci; 1901 if (fullduplex[dev]) 1902 rme32->fullduplex_mode = 1; 1903 if ((err = snd_rme32_create(rme32)) < 0) { 1904 snd_card_free(card); 1905 return err; 1906 } 1907 1908 strcpy(card->driver, "Digi32"); 1909 switch (rme32->pci->device) { 1910 case PCI_DEVICE_ID_RME_DIGI32: 1911 strcpy(card->shortname, "RME Digi32"); 1912 break; 1913 case PCI_DEVICE_ID_RME_DIGI32_8: 1914 strcpy(card->shortname, "RME Digi32/8"); 1915 break; 1916 case PCI_DEVICE_ID_RME_DIGI32_PRO: 1917 strcpy(card->shortname, "RME Digi32 PRO"); 1918 break; 1919 } 1920 sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d", 1921 card->shortname, rme32->rev, rme32->port, rme32->irq); 1922 1923 if ((err = snd_card_register(card)) < 0) { 1924 snd_card_free(card); 1925 return err; 1926 } 1927 pci_set_drvdata(pci, card); 1928 dev++; 1929 return 0; 1930 } 1931 1932 static void snd_rme32_remove(struct pci_dev *pci) 1933 { 1934 snd_card_free(pci_get_drvdata(pci)); 1935 } 1936 1937 static struct pci_driver rme32_driver = { 1938 .name = KBUILD_MODNAME, 1939 .id_table = snd_rme32_ids, 1940 .probe = snd_rme32_probe, 1941 .remove = snd_rme32_remove, 1942 }; 1943 1944 module_pci_driver(rme32_driver); 1945