1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Driver for Digigram pcxhr compatible soundcards 4 * 5 * low level interface with interrupt and message handling 6 * 7 * Copyright (c) 2004 by Digigram <alsa@digigram.com> 8 */ 9 10 #ifndef __SOUND_PCXHR_CORE_H 11 #define __SOUND_PCXHR_CORE_H 12 13 struct firmware; 14 struct pcxhr_mgr; 15 16 /* init and firmware download commands */ 17 void pcxhr_reset_xilinx_com(struct pcxhr_mgr *mgr); 18 void pcxhr_reset_dsp(struct pcxhr_mgr *mgr); 19 void pcxhr_enable_dsp(struct pcxhr_mgr *mgr); 20 int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second); 21 int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom); 22 int pcxhr_load_boot_binary(struct pcxhr_mgr *mgr, const struct firmware *boot); 23 int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp); 24 25 /* DSP time available on MailBox4 register : 24 bit time samples() */ 26 #define PCXHR_DSP_TIME_MASK 0x00ffffff 27 #define PCXHR_DSP_TIME_INVALID 0x10000000 28 29 30 #define PCXHR_SIZE_MAX_CMD 8 31 #define PCXHR_SIZE_MAX_STATUS 16 32 #define PCXHR_SIZE_MAX_LONG_STATUS 256 33 34 struct pcxhr_rmh { 35 u16 cmd_len; /* length of the command to send (WORDs) */ 36 u16 stat_len; /* length of the status received (WORDs) */ 37 u16 dsp_stat; /* status type, RMP_SSIZE_XXX */ 38 u16 cmd_idx; /* index of the command */ 39 u32 cmd[PCXHR_SIZE_MAX_CMD]; 40 u32 stat[PCXHR_SIZE_MAX_STATUS]; 41 }; 42 43 enum { 44 CMD_VERSION, /* cmd_len = 2 stat_len = 1 */ 45 CMD_SUPPORTED, /* cmd_len = 1 stat_len = 4 */ 46 CMD_TEST_IT, /* cmd_len = 1 stat_len = 1 */ 47 CMD_SEND_IRQA, /* cmd_len = 1 stat_len = 0 */ 48 CMD_ACCESS_IO_WRITE, /* cmd_len >= 1 stat_len >= 1 */ 49 CMD_ACCESS_IO_READ, /* cmd_len >= 1 stat_len >= 1 */ 50 CMD_ASYNC, /* cmd_len = 1 stat_len = 1 */ 51 CMD_MODIFY_CLOCK, /* cmd_len = 3 stat_len = 0 */ 52 CMD_RESYNC_AUDIO_INPUTS, /* cmd_len = 1 stat_len = 0 */ 53 CMD_GET_DSP_RESOURCES, /* cmd_len = 1 stat_len = 4 */ 54 CMD_SET_TIMER_INTERRUPT, /* cmd_len = 1 stat_len = 0 */ 55 CMD_RES_PIPE, /* cmd_len >=2 stat_len = 0 */ 56 CMD_FREE_PIPE, /* cmd_len = 1 stat_len = 0 */ 57 CMD_CONF_PIPE, /* cmd_len = 2 stat_len = 0 */ 58 CMD_STOP_PIPE, /* cmd_len = 1 stat_len = 0 */ 59 CMD_PIPE_SAMPLE_COUNT, /* cmd_len = 2 stat_len = 2 */ 60 CMD_CAN_START_PIPE, /* cmd_len >= 1 stat_len = 1 */ 61 CMD_START_STREAM, /* cmd_len = 2 stat_len = 0 */ 62 CMD_STREAM_OUT_LEVEL_ADJUST, /* cmd_len >= 1 stat_len = 0 */ 63 CMD_STOP_STREAM, /* cmd_len = 2 stat_len = 0 */ 64 CMD_UPDATE_R_BUFFERS, /* cmd_len = 4 stat_len = 0 */ 65 CMD_FORMAT_STREAM_OUT, /* cmd_len >= 2 stat_len = 0 */ 66 CMD_FORMAT_STREAM_IN, /* cmd_len >= 4 stat_len = 0 */ 67 CMD_STREAM_SAMPLE_COUNT, /* cmd_len = 2 stat_len = (2 * nb_stream) */ 68 CMD_AUDIO_LEVEL_ADJUST, /* cmd_len = 3 stat_len = 0 */ 69 CMD_GET_TIME_CODE, /* cmd_len = 1 stat_len = 5 */ 70 CMD_MANAGE_SIGNAL, /* cmd_len = 1 stat_len = 0 */ 71 CMD_LAST_INDEX 72 }; 73 74 #define MASK_DSP_WORD 0x00ffffff 75 #define MASK_ALL_STREAM 0x00ffffff 76 #define MASK_DSP_WORD_LEVEL 0x000001ff 77 #define MASK_FIRST_FIELD 0x0000001f 78 #define FIELD_SIZE 5 79 80 /* 81 init the rmh struct; by default cmd_len is set to 1 82 */ 83 void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd); 84 85 void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh* rmh, int capture, unsigned int param1, 86 unsigned int param2, unsigned int param3); 87 88 #define DSP_EXT_CMD_SET(x) (x->dsp_version > 0x012800) 89 90 /* 91 send the rmh 92 */ 93 int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh); 94 95 96 /* values used for CMD_ACCESS_IO_WRITE and CMD_ACCESS_IO_READ */ 97 #define IO_NUM_REG_CONT 0 98 #define IO_NUM_REG_GENCLK 1 99 #define IO_NUM_REG_MUTE_OUT 2 100 #define IO_NUM_SPEED_RATIO 4 101 #define IO_NUM_REG_STATUS 5 102 #define IO_NUM_REG_CUER 10 103 #define IO_NUM_UER_CHIP_REG 11 104 #define IO_NUM_REG_CONFIG_SRC 12 105 #define IO_NUM_REG_OUT_ANA_LEVEL 20 106 #define IO_NUM_REG_IN_ANA_LEVEL 21 107 108 #define REG_CONT_VALSMPTE 0x000800 109 #define REG_CONT_UNMUTE_INPUTS 0x020000 110 111 /* parameters used with register IO_NUM_REG_STATUS */ 112 #define REG_STATUS_OPTIONS 0 113 #define REG_STATUS_AES_SYNC 8 114 #define REG_STATUS_AES_1 9 115 #define REG_STATUS_AES_2 10 116 #define REG_STATUS_AES_3 11 117 #define REG_STATUS_AES_4 12 118 #define REG_STATUS_WORD_CLOCK 13 119 #define REG_STATUS_INTER_SYNC 14 120 #define REG_STATUS_CURRENT 0x80 121 /* results */ 122 #define REG_STATUS_OPT_NO_VIDEO_SIGNAL 0x01 123 #define REG_STATUS_OPT_DAUGHTER_MASK 0x1c 124 #define REG_STATUS_OPT_ANALOG_BOARD 0x00 125 #define REG_STATUS_OPT_NO_DAUGHTER 0x1c 126 #define REG_STATUS_OPT_COMPANION_MASK 0xe0 127 #define REG_STATUS_OPT_NO_COMPANION 0xe0 128 #define REG_STATUS_SYNC_32000 0x00 129 #define REG_STATUS_SYNC_44100 0x01 130 #define REG_STATUS_SYNC_48000 0x02 131 #define REG_STATUS_SYNC_64000 0x03 132 #define REG_STATUS_SYNC_88200 0x04 133 #define REG_STATUS_SYNC_96000 0x05 134 #define REG_STATUS_SYNC_128000 0x06 135 #define REG_STATUS_SYNC_176400 0x07 136 #define REG_STATUS_SYNC_192000 0x08 137 138 int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start); 139 140 int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask, 141 unsigned int value, int *changed); 142 143 /* codec parameters */ 144 #define CS8416_RUN 0x200401 145 #define CS8416_FORMAT_DETECT 0x200b00 146 #define CS8416_CSB0 0x201900 147 #define CS8416_CSB1 0x201a00 148 #define CS8416_CSB2 0x201b00 149 #define CS8416_CSB3 0x201c00 150 #define CS8416_CSB4 0x201d00 151 #define CS8416_VERSION 0x207f00 152 153 #define CS8420_DATA_FLOW_CTL 0x200301 154 #define CS8420_CLOCK_SRC_CTL 0x200401 155 #define CS8420_RECEIVER_ERRORS 0x201000 156 #define CS8420_SRC_RATIO 0x201e00 157 #define CS8420_CSB0 0x202000 158 #define CS8420_CSB1 0x202100 159 #define CS8420_CSB2 0x202200 160 #define CS8420_CSB3 0x202300 161 #define CS8420_CSB4 0x202400 162 #define CS8420_VERSION 0x207f00 163 164 #define CS4271_MODE_CTL_1 0x200101 165 #define CS4271_DAC_CTL 0x200201 166 #define CS4271_VOLMIX 0x200301 167 #define CS4271_VOLMUTE_LEFT 0x200401 168 #define CS4271_VOLMUTE_RIGHT 0x200501 169 #define CS4271_ADC_CTL 0x200601 170 #define CS4271_MODE_CTL_2 0x200701 171 172 #define CHIP_SIG_AND_MAP_SPI 0xff7f00 173 174 /* codec selection */ 175 #define CS4271_01_CS 0x160018 176 #define CS4271_23_CS 0x160019 177 #define CS4271_45_CS 0x16001a 178 #define CS4271_67_CS 0x16001b 179 #define CS4271_89_CS 0x16001c 180 #define CS4271_AB_CS 0x16001d 181 #define CS8420_01_CS 0x080090 182 #define CS8420_23_CS 0x080092 183 #define CS8420_45_CS 0x080094 184 #define CS8420_67_CS 0x080096 185 #define CS8416_01_CS 0x080098 186 187 188 /* interrupt handling */ 189 irqreturn_t pcxhr_interrupt(int irq, void *dev_id); 190 irqreturn_t pcxhr_threaded_irq(int irq, void *dev_id); 191 192 #endif /* __SOUND_PCXHR_CORE_H */ 193