1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for Digigram pcxhr compatible soundcards 4 * 5 * main file with alsa callbacks 6 * 7 * Copyright (c) 2004 by Digigram <alsa@digigram.com> 8 */ 9 10 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/slab.h> 14 #include <linux/pci.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/delay.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 20 #include <sound/core.h> 21 #include <sound/initval.h> 22 #include <sound/info.h> 23 #include <sound/control.h> 24 #include <sound/pcm.h> 25 #include <sound/pcm_params.h> 26 #include "pcxhr.h" 27 #include "pcxhr_mixer.h" 28 #include "pcxhr_hwdep.h" 29 #include "pcxhr_core.h" 30 #include "pcxhr_mix22.h" 31 32 #define DRIVER_NAME "pcxhr" 33 34 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, " 35 "Marc Titinger <titinger@digigram.com>"); 36 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING); 37 MODULE_LICENSE("GPL"); 38 MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}"); 39 40 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 41 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 42 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */ 43 static bool mono[SNDRV_CARDS]; /* capture mono only */ 44 45 module_param_array(index, int, NULL, 0444); 46 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard"); 47 module_param_array(id, charp, NULL, 0444); 48 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard"); 49 module_param_array(enable, bool, NULL, 0444); 50 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard"); 51 module_param_array(mono, bool, NULL, 0444); 52 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)"); 53 54 enum { 55 PCI_ID_VX882HR, 56 PCI_ID_PCX882HR, 57 PCI_ID_VX881HR, 58 PCI_ID_PCX881HR, 59 PCI_ID_VX882E, 60 PCI_ID_PCX882E, 61 PCI_ID_VX881E, 62 PCI_ID_PCX881E, 63 PCI_ID_VX1222HR, 64 PCI_ID_PCX1222HR, 65 PCI_ID_VX1221HR, 66 PCI_ID_PCX1221HR, 67 PCI_ID_VX1222E, 68 PCI_ID_PCX1222E, 69 PCI_ID_VX1221E, 70 PCI_ID_PCX1221E, 71 PCI_ID_VX222HR, 72 PCI_ID_VX222E, 73 PCI_ID_PCX22HR, 74 PCI_ID_PCX22E, 75 PCI_ID_VX222HRMIC, 76 PCI_ID_VX222E_MIC, 77 PCI_ID_PCX924HR, 78 PCI_ID_PCX924E, 79 PCI_ID_PCX924HRMIC, 80 PCI_ID_PCX924E_MIC, 81 PCI_ID_VX442HR, 82 PCI_ID_PCX442HR, 83 PCI_ID_VX442E, 84 PCI_ID_PCX442E, 85 PCI_ID_VX822HR, 86 PCI_ID_PCX822HR, 87 PCI_ID_VX822E, 88 PCI_ID_PCX822E, 89 PCI_ID_LAST 90 }; 91 92 static const struct pci_device_id pcxhr_ids[] = { 93 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, 94 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, 95 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, 96 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, 97 { 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, }, 98 { 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, }, 99 { 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, }, 100 { 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, }, 101 { 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, }, 102 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, 103 { 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, }, 104 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, 105 { 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, }, 106 { 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, }, 107 { 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, }, 108 { 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, }, 109 { 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, }, 110 { 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, }, 111 { 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, }, 112 { 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, }, 113 { 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, }, 114 { 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, }, 115 { 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, }, 116 { 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, }, 117 { 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, }, 118 { 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, }, 119 { 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, }, 120 { 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, }, 121 { 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, }, 122 { 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, }, 123 { 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, }, 124 { 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, }, 125 { 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, }, 126 { 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, }, 127 { 0, } 128 }; 129 130 MODULE_DEVICE_TABLE(pci, pcxhr_ids); 131 132 struct board_parameters { 133 char* board_name; 134 short playback_chips; 135 short capture_chips; 136 short fw_file_set; 137 short firmware_num; 138 }; 139 static const struct board_parameters pcxhr_board_params[] = { 140 [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 0, 41 }, 141 [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 0, 41 }, 142 [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 0, 41 }, 143 [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 0, 41 }, 144 [PCI_ID_VX882E] = { "VX882e", 4, 4, 1, 41 }, 145 [PCI_ID_PCX882E] = { "PCX882e", 4, 4, 1, 41 }, 146 [PCI_ID_VX881E] = { "VX881e", 4, 4, 1, 41 }, 147 [PCI_ID_PCX881E] = { "PCX881e", 4, 4, 1, 41 }, 148 [PCI_ID_VX1222HR] = { "VX1222HR", 6, 1, 2, 42 }, 149 [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 2, 42 }, 150 [PCI_ID_VX1221HR] = { "VX1221HR", 6, 1, 2, 42 }, 151 [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 2, 42 }, 152 [PCI_ID_VX1222E] = { "VX1222e", 6, 1, 3, 42 }, 153 [PCI_ID_PCX1222E] = { "PCX1222e", 6, 1, 3, 42 }, 154 [PCI_ID_VX1221E] = { "VX1221e", 6, 1, 3, 42 }, 155 [PCI_ID_PCX1221E] = { "PCX1221e", 6, 1, 3, 42 }, 156 [PCI_ID_VX222HR] = { "VX222HR", 1, 1, 4, 44 }, 157 [PCI_ID_VX222E] = { "VX222e", 1, 1, 4, 44 }, 158 [PCI_ID_PCX22HR] = { "PCX22HR", 1, 0, 4, 44 }, 159 [PCI_ID_PCX22E] = { "PCX22e", 1, 0, 4, 44 }, 160 [PCI_ID_VX222HRMIC] = { "VX222HR-Mic", 1, 1, 5, 44 }, 161 [PCI_ID_VX222E_MIC] = { "VX222e-Mic", 1, 1, 5, 44 }, 162 [PCI_ID_PCX924HR] = { "PCX924HR", 1, 1, 5, 44 }, 163 [PCI_ID_PCX924E] = { "PCX924e", 1, 1, 5, 44 }, 164 [PCI_ID_PCX924HRMIC] = { "PCX924HR-Mic", 1, 1, 5, 44 }, 165 [PCI_ID_PCX924E_MIC] = { "PCX924e-Mic", 1, 1, 5, 44 }, 166 [PCI_ID_VX442HR] = { "VX442HR", 2, 2, 0, 41 }, 167 [PCI_ID_PCX442HR] = { "PCX442HR", 2, 2, 0, 41 }, 168 [PCI_ID_VX442E] = { "VX442e", 2, 2, 1, 41 }, 169 [PCI_ID_PCX442E] = { "PCX442e", 2, 2, 1, 41 }, 170 [PCI_ID_VX822HR] = { "VX822HR", 4, 1, 2, 42 }, 171 [PCI_ID_PCX822HR] = { "PCX822HR", 4, 1, 2, 42 }, 172 [PCI_ID_VX822E] = { "VX822e", 4, 1, 3, 42 }, 173 [PCI_ID_PCX822E] = { "PCX822e", 4, 1, 3, 42 }, 174 }; 175 176 /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */ 177 /* VX222HR, VX222e, PCX22HR and PCX22e */ 178 #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4) 179 /* some boards do not support 192kHz on digital AES input plugs */ 180 #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \ 181 (x->fw_file_set == 0) || \ 182 (x->fw_file_set == 2)) 183 184 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, 185 unsigned int* realfreq) 186 { 187 unsigned int reg; 188 189 if (freq < 6900 || freq > 110000) 190 return -EINVAL; 191 reg = (28224000 * 2) / freq; 192 reg = (reg - 1) / 2; 193 if (reg < 0x200) 194 *pllreg = reg + 0x800; 195 else if (reg < 0x400) 196 *pllreg = reg & 0x1ff; 197 else if (reg < 0x800) { 198 *pllreg = ((reg >> 1) & 0x1ff) + 0x200; 199 reg &= ~1; 200 } else { 201 *pllreg = ((reg >> 2) & 0x1ff) + 0x400; 202 reg &= ~3; 203 } 204 if (realfreq) 205 *realfreq = (28224000 / (reg + 1)); 206 return 0; 207 } 208 209 210 #define PCXHR_FREQ_REG_MASK 0x1f 211 #define PCXHR_FREQ_QUARTZ_48000 0x00 212 #define PCXHR_FREQ_QUARTZ_24000 0x01 213 #define PCXHR_FREQ_QUARTZ_12000 0x09 214 #define PCXHR_FREQ_QUARTZ_32000 0x08 215 #define PCXHR_FREQ_QUARTZ_16000 0x04 216 #define PCXHR_FREQ_QUARTZ_8000 0x0c 217 #define PCXHR_FREQ_QUARTZ_44100 0x02 218 #define PCXHR_FREQ_QUARTZ_22050 0x0a 219 #define PCXHR_FREQ_QUARTZ_11025 0x06 220 #define PCXHR_FREQ_PLL 0x05 221 #define PCXHR_FREQ_QUARTZ_192000 0x10 222 #define PCXHR_FREQ_QUARTZ_96000 0x18 223 #define PCXHR_FREQ_QUARTZ_176400 0x14 224 #define PCXHR_FREQ_QUARTZ_88200 0x1c 225 #define PCXHR_FREQ_QUARTZ_128000 0x12 226 #define PCXHR_FREQ_QUARTZ_64000 0x1a 227 228 #define PCXHR_FREQ_WORD_CLOCK 0x0f 229 #define PCXHR_FREQ_SYNC_AES 0x0e 230 #define PCXHR_FREQ_AES_1 0x07 231 #define PCXHR_FREQ_AES_2 0x0b 232 #define PCXHR_FREQ_AES_3 0x03 233 #define PCXHR_FREQ_AES_4 0x0d 234 235 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate, 236 unsigned int *reg, unsigned int *freq) 237 { 238 unsigned int val, realfreq, pllreg; 239 struct pcxhr_rmh rmh; 240 int err; 241 242 realfreq = rate; 243 switch (mgr->use_clock_type) { 244 case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */ 245 switch (rate) { 246 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break; 247 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break; 248 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break; 249 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break; 250 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break; 251 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break; 252 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break; 253 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break; 254 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break; 255 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break; 256 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break; 257 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break; 258 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break; 259 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break; 260 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break; 261 default : 262 val = PCXHR_FREQ_PLL; 263 /* get the value for the pll register */ 264 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq); 265 if (err) 266 return err; 267 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); 268 rmh.cmd[0] |= IO_NUM_REG_GENCLK; 269 rmh.cmd[1] = pllreg & MASK_DSP_WORD; 270 rmh.cmd[2] = pllreg >> 24; 271 rmh.cmd_len = 3; 272 err = pcxhr_send_msg(mgr, &rmh); 273 if (err < 0) { 274 dev_err(&mgr->pci->dev, 275 "error CMD_ACCESS_IO_WRITE " 276 "for PLL register : %x!\n", err); 277 return err; 278 } 279 } 280 break; 281 case PCXHR_CLOCK_TYPE_WORD_CLOCK: 282 val = PCXHR_FREQ_WORD_CLOCK; 283 break; 284 case PCXHR_CLOCK_TYPE_AES_SYNC: 285 val = PCXHR_FREQ_SYNC_AES; 286 break; 287 case PCXHR_CLOCK_TYPE_AES_1: 288 val = PCXHR_FREQ_AES_1; 289 break; 290 case PCXHR_CLOCK_TYPE_AES_2: 291 val = PCXHR_FREQ_AES_2; 292 break; 293 case PCXHR_CLOCK_TYPE_AES_3: 294 val = PCXHR_FREQ_AES_3; 295 break; 296 case PCXHR_CLOCK_TYPE_AES_4: 297 val = PCXHR_FREQ_AES_4; 298 break; 299 default: 300 return -EINVAL; 301 } 302 *reg = val; 303 *freq = realfreq; 304 return 0; 305 } 306 307 308 static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr, 309 unsigned int rate, 310 int *changed) 311 { 312 unsigned int val, realfreq, speed; 313 struct pcxhr_rmh rmh; 314 int err; 315 316 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq); 317 if (err) 318 return err; 319 320 /* codec speed modes */ 321 if (rate < 55000) 322 speed = 0; /* single speed */ 323 else if (rate < 100000) 324 speed = 1; /* dual speed */ 325 else 326 speed = 2; /* quad speed */ 327 if (mgr->codec_speed != speed) { 328 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */ 329 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 330 if (DSP_EXT_CMD_SET(mgr)) { 331 rmh.cmd[1] = 1; 332 rmh.cmd_len = 2; 333 } 334 err = pcxhr_send_msg(mgr, &rmh); 335 if (err) 336 return err; 337 338 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */ 339 rmh.cmd[0] |= IO_NUM_SPEED_RATIO; 340 rmh.cmd[1] = speed; 341 rmh.cmd_len = 2; 342 err = pcxhr_send_msg(mgr, &rmh); 343 if (err) 344 return err; 345 } 346 /* set the new frequency */ 347 dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val); 348 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, 349 val, changed); 350 if (err) 351 return err; 352 353 mgr->sample_rate_real = realfreq; 354 mgr->cur_clock_type = mgr->use_clock_type; 355 356 /* unmute after codec speed modes */ 357 if (mgr->codec_speed != speed) { 358 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */ 359 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 360 if (DSP_EXT_CMD_SET(mgr)) { 361 rmh.cmd[1] = 1; 362 rmh.cmd_len = 2; 363 } 364 err = pcxhr_send_msg(mgr, &rmh); 365 if (err) 366 return err; 367 mgr->codec_speed = speed; /* save new codec speed */ 368 } 369 370 dev_dbg(&mgr->pci->dev, "pcxhr_sub_set_clock to %dHz (realfreq=%d)\n", 371 rate, realfreq); 372 return 0; 373 } 374 375 #define PCXHR_MODIFY_CLOCK_S_BIT 0x04 376 377 #define PCXHR_IRQ_TIMER_FREQ 92000 378 #define PCXHR_IRQ_TIMER_PERIOD 48 379 380 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate) 381 { 382 struct pcxhr_rmh rmh; 383 int err, changed; 384 385 if (rate == 0) 386 return 0; /* nothing to do */ 387 388 if (mgr->is_hr_stereo) 389 err = hr222_sub_set_clock(mgr, rate, &changed); 390 else 391 err = pcxhr_sub_set_clock(mgr, rate, &changed); 392 393 if (err) 394 return err; 395 396 if (changed) { 397 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK); 398 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */ 399 if (rate < PCXHR_IRQ_TIMER_FREQ) 400 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD; 401 else 402 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2; 403 rmh.cmd[2] = rate; 404 rmh.cmd_len = 3; 405 err = pcxhr_send_msg(mgr, &rmh); 406 if (err) 407 return err; 408 } 409 return 0; 410 } 411 412 413 static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr, 414 enum pcxhr_clock_type clock_type, 415 int *sample_rate) 416 { 417 struct pcxhr_rmh rmh; 418 unsigned char reg; 419 int err, rate; 420 421 switch (clock_type) { 422 case PCXHR_CLOCK_TYPE_WORD_CLOCK: 423 reg = REG_STATUS_WORD_CLOCK; 424 break; 425 case PCXHR_CLOCK_TYPE_AES_SYNC: 426 reg = REG_STATUS_AES_SYNC; 427 break; 428 case PCXHR_CLOCK_TYPE_AES_1: 429 reg = REG_STATUS_AES_1; 430 break; 431 case PCXHR_CLOCK_TYPE_AES_2: 432 reg = REG_STATUS_AES_2; 433 break; 434 case PCXHR_CLOCK_TYPE_AES_3: 435 reg = REG_STATUS_AES_3; 436 break; 437 case PCXHR_CLOCK_TYPE_AES_4: 438 reg = REG_STATUS_AES_4; 439 break; 440 default: 441 return -EINVAL; 442 } 443 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); 444 rmh.cmd_len = 2; 445 rmh.cmd[0] |= IO_NUM_REG_STATUS; 446 if (mgr->last_reg_stat != reg) { 447 rmh.cmd[1] = reg; 448 err = pcxhr_send_msg(mgr, &rmh); 449 if (err) 450 return err; 451 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */ 452 mgr->last_reg_stat = reg; 453 } 454 rmh.cmd[1] = REG_STATUS_CURRENT; 455 err = pcxhr_send_msg(mgr, &rmh); 456 if (err) 457 return err; 458 switch (rmh.stat[1] & 0x0f) { 459 case REG_STATUS_SYNC_32000 : rate = 32000; break; 460 case REG_STATUS_SYNC_44100 : rate = 44100; break; 461 case REG_STATUS_SYNC_48000 : rate = 48000; break; 462 case REG_STATUS_SYNC_64000 : rate = 64000; break; 463 case REG_STATUS_SYNC_88200 : rate = 88200; break; 464 case REG_STATUS_SYNC_96000 : rate = 96000; break; 465 case REG_STATUS_SYNC_128000 : rate = 128000; break; 466 case REG_STATUS_SYNC_176400 : rate = 176400; break; 467 case REG_STATUS_SYNC_192000 : rate = 192000; break; 468 default: rate = 0; 469 } 470 dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate); 471 *sample_rate = rate; 472 return 0; 473 } 474 475 476 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, 477 enum pcxhr_clock_type clock_type, 478 int *sample_rate) 479 { 480 if (mgr->is_hr_stereo) 481 return hr222_get_external_clock(mgr, clock_type, 482 sample_rate); 483 else 484 return pcxhr_sub_get_external_clock(mgr, clock_type, 485 sample_rate); 486 } 487 488 /* 489 * start or stop playback/capture substream 490 */ 491 static int pcxhr_set_stream_state(struct snd_pcxhr *chip, 492 struct pcxhr_stream *stream) 493 { 494 int err; 495 struct pcxhr_rmh rmh; 496 int stream_mask, start; 497 498 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) 499 start = 1; 500 else { 501 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) { 502 dev_err(chip->card->dev, 503 "pcxhr_set_stream_state CANNOT be stopped\n"); 504 return -EINVAL; 505 } 506 start = 0; 507 } 508 if (!stream->substream) 509 return -EINVAL; 510 511 stream->timer_abs_periods = 0; 512 stream->timer_period_frag = 0; /* reset theoretical stream pos */ 513 stream->timer_buf_periods = 0; 514 stream->timer_is_synced = 0; 515 516 stream_mask = 517 stream->pipe->is_capture ? 1 : 1<<stream->substream->number; 518 519 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM); 520 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 521 stream->pipe->first_audio, 0, stream_mask); 522 523 chip = snd_pcm_substream_chip(stream->substream); 524 525 err = pcxhr_send_msg(chip->mgr, &rmh); 526 if (err) 527 dev_err(chip->card->dev, 528 "ERROR pcxhr_set_stream_state err=%x;\n", err); 529 stream->status = 530 start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED; 531 return err; 532 } 533 534 #define HEADER_FMT_BASE_LIN 0xfed00000 535 #define HEADER_FMT_BASE_FLOAT 0xfad00000 536 #define HEADER_FMT_INTEL 0x00008000 537 #define HEADER_FMT_24BITS 0x00004000 538 #define HEADER_FMT_16BITS 0x00002000 539 #define HEADER_FMT_UPTO11 0x00000200 540 #define HEADER_FMT_UPTO32 0x00000100 541 #define HEADER_FMT_MONO 0x00000080 542 543 static int pcxhr_set_format(struct pcxhr_stream *stream) 544 { 545 int err, is_capture, sample_rate, stream_num; 546 struct snd_pcxhr *chip; 547 struct pcxhr_rmh rmh; 548 unsigned int header; 549 550 chip = snd_pcm_substream_chip(stream->substream); 551 switch (stream->format) { 552 case SNDRV_PCM_FORMAT_U8: 553 header = HEADER_FMT_BASE_LIN; 554 break; 555 case SNDRV_PCM_FORMAT_S16_LE: 556 header = HEADER_FMT_BASE_LIN | 557 HEADER_FMT_16BITS | HEADER_FMT_INTEL; 558 break; 559 case SNDRV_PCM_FORMAT_S16_BE: 560 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS; 561 break; 562 case SNDRV_PCM_FORMAT_S24_3LE: 563 header = HEADER_FMT_BASE_LIN | 564 HEADER_FMT_24BITS | HEADER_FMT_INTEL; 565 break; 566 case SNDRV_PCM_FORMAT_S24_3BE: 567 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS; 568 break; 569 case SNDRV_PCM_FORMAT_FLOAT_LE: 570 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL; 571 break; 572 default: 573 dev_err(chip->card->dev, 574 "error pcxhr_set_format() : unknown format\n"); 575 return -EINVAL; 576 } 577 578 sample_rate = chip->mgr->sample_rate; 579 if (sample_rate <= 32000 && sample_rate !=0) { 580 if (sample_rate <= 11025) 581 header |= HEADER_FMT_UPTO11; 582 else 583 header |= HEADER_FMT_UPTO32; 584 } 585 if (stream->channels == 1) 586 header |= HEADER_FMT_MONO; 587 588 is_capture = stream->pipe->is_capture; 589 stream_num = is_capture ? 0 : stream->substream->number; 590 591 pcxhr_init_rmh(&rmh, is_capture ? 592 CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT); 593 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, 594 stream_num, 0); 595 if (is_capture) { 596 /* bug with old dsp versions: */ 597 /* bit 12 also sets the format of the playback stream */ 598 if (DSP_EXT_CMD_SET(chip->mgr)) 599 rmh.cmd[0] |= 1<<10; 600 else 601 rmh.cmd[0] |= 1<<12; 602 } 603 rmh.cmd[1] = 0; 604 rmh.cmd_len = 2; 605 if (DSP_EXT_CMD_SET(chip->mgr)) { 606 /* add channels and set bit 19 if channels>2 */ 607 rmh.cmd[1] = stream->channels; 608 if (!is_capture) { 609 /* playback : add channel mask to command */ 610 rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03; 611 rmh.cmd_len = 3; 612 } 613 } 614 rmh.cmd[rmh.cmd_len++] = header >> 8; 615 rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16; 616 err = pcxhr_send_msg(chip->mgr, &rmh); 617 if (err) 618 dev_err(chip->card->dev, 619 "ERROR pcxhr_set_format err=%x;\n", err); 620 return err; 621 } 622 623 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream) 624 { 625 int err, is_capture, stream_num; 626 struct pcxhr_rmh rmh; 627 struct snd_pcm_substream *subs = stream->substream; 628 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 629 630 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE); 631 stream_num = is_capture ? 0 : subs->number; 632 633 dev_dbg(chip->card->dev, 634 "pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", 635 is_capture ? 'c' : 'p', 636 chip->chip_idx, (void *)(long)subs->runtime->dma_addr, 637 subs->runtime->dma_bytes, subs->number); 638 639 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS); 640 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, 641 stream_num, 0); 642 643 /* max buffer size is 2 MByte */ 644 snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000); 645 /* size in bits */ 646 rmh.cmd[1] = subs->runtime->dma_bytes * 8; 647 /* most significant byte */ 648 rmh.cmd[2] = subs->runtime->dma_addr >> 24; 649 /* this is a circular buffer */ 650 rmh.cmd[2] |= 1<<19; 651 /* least 3 significant bytes */ 652 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; 653 rmh.cmd_len = 4; 654 err = pcxhr_send_msg(chip->mgr, &rmh); 655 if (err) 656 dev_err(chip->card->dev, 657 "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err); 658 return err; 659 } 660 661 662 #if 0 663 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, 664 snd_pcm_uframes_t *sample_count) 665 { 666 struct pcxhr_rmh rmh; 667 int err; 668 pcxhr_t *chip = snd_pcm_substream_chip(stream->substream); 669 pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT); 670 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0, 671 1<<stream->pipe->first_audio); 672 err = pcxhr_send_msg(chip->mgr, &rmh); 673 if (err == 0) { 674 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24; 675 *sample_count += (snd_pcm_uframes_t)rmh.stat[1]; 676 } 677 dev_dbg(chip->card->dev, "PIPE_SAMPLE_COUNT = %lx\n", *sample_count); 678 return err; 679 } 680 #endif 681 682 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream, 683 struct pcxhr_pipe **pipe) 684 { 685 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) { 686 *pipe = stream->pipe; 687 return 1; 688 } 689 return 0; 690 } 691 692 static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr) 693 { 694 int i, j, err; 695 struct pcxhr_pipe *pipe; 696 struct snd_pcxhr *chip; 697 int capture_mask = 0; 698 int playback_mask = 0; 699 700 #ifdef CONFIG_SND_DEBUG_VERBOSE 701 ktime_t start_time, stop_time, diff_time; 702 703 start_time = ktime_get(); 704 #endif 705 mutex_lock(&mgr->setup_mutex); 706 707 /* check the pipes concerned and build pipe_array */ 708 for (i = 0; i < mgr->num_cards; i++) { 709 chip = mgr->chip[i]; 710 for (j = 0; j < chip->nb_streams_capt; j++) { 711 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe)) 712 capture_mask |= (1 << pipe->first_audio); 713 } 714 for (j = 0; j < chip->nb_streams_play; j++) { 715 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) { 716 playback_mask |= (1 << pipe->first_audio); 717 break; /* add only once, as all playback 718 * streams of one chip use the same pipe 719 */ 720 } 721 } 722 } 723 if (capture_mask == 0 && playback_mask == 0) { 724 mutex_unlock(&mgr->setup_mutex); 725 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : no pipes\n"); 726 return; 727 } 728 729 dev_dbg(&mgr->pci->dev, "pcxhr_start_linked_stream : " 730 "playback_mask=%x capture_mask=%x\n", 731 playback_mask, capture_mask); 732 733 /* synchronous stop of all the pipes concerned */ 734 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0); 735 if (err) { 736 mutex_unlock(&mgr->setup_mutex); 737 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : " 738 "error stop pipes (P%x C%x)\n", 739 playback_mask, capture_mask); 740 return; 741 } 742 743 /* the dsp lost format and buffer info with the stop pipe */ 744 for (i = 0; i < mgr->num_cards; i++) { 745 struct pcxhr_stream *stream; 746 chip = mgr->chip[i]; 747 for (j = 0; j < chip->nb_streams_capt; j++) { 748 stream = &chip->capture_stream[j]; 749 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { 750 err = pcxhr_set_format(stream); 751 err = pcxhr_update_r_buffer(stream); 752 } 753 } 754 for (j = 0; j < chip->nb_streams_play; j++) { 755 stream = &chip->playback_stream[j]; 756 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { 757 err = pcxhr_set_format(stream); 758 err = pcxhr_update_r_buffer(stream); 759 } 760 } 761 } 762 /* start all the streams */ 763 for (i = 0; i < mgr->num_cards; i++) { 764 struct pcxhr_stream *stream; 765 chip = mgr->chip[i]; 766 for (j = 0; j < chip->nb_streams_capt; j++) { 767 stream = &chip->capture_stream[j]; 768 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) 769 err = pcxhr_set_stream_state(chip, stream); 770 } 771 for (j = 0; j < chip->nb_streams_play; j++) { 772 stream = &chip->playback_stream[j]; 773 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) 774 err = pcxhr_set_stream_state(chip, stream); 775 } 776 } 777 778 /* synchronous start of all the pipes concerned */ 779 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); 780 if (err) { 781 mutex_unlock(&mgr->setup_mutex); 782 dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : " 783 "error start pipes (P%x C%x)\n", 784 playback_mask, capture_mask); 785 return; 786 } 787 788 /* put the streams into the running state now 789 * (increment pointer by interrupt) 790 */ 791 mutex_lock(&mgr->lock); 792 for ( i =0; i < mgr->num_cards; i++) { 793 struct pcxhr_stream *stream; 794 chip = mgr->chip[i]; 795 for(j = 0; j < chip->nb_streams_capt; j++) { 796 stream = &chip->capture_stream[j]; 797 if(stream->status == PCXHR_STREAM_STATUS_STARTED) 798 stream->status = PCXHR_STREAM_STATUS_RUNNING; 799 } 800 for (j = 0; j < chip->nb_streams_play; j++) { 801 stream = &chip->playback_stream[j]; 802 if (stream->status == PCXHR_STREAM_STATUS_STARTED) { 803 /* playback will already have advanced ! */ 804 stream->timer_period_frag += mgr->granularity; 805 stream->status = PCXHR_STREAM_STATUS_RUNNING; 806 } 807 } 808 } 809 mutex_unlock(&mgr->lock); 810 811 mutex_unlock(&mgr->setup_mutex); 812 813 #ifdef CONFIG_SND_DEBUG_VERBOSE 814 stop_time = ktime_get(); 815 diff_time = ktime_sub(stop_time, start_time); 816 dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n", 817 (long)(ktime_to_ns(diff_time)), err); 818 #endif 819 } 820 821 822 /* 823 * trigger callback 824 */ 825 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd) 826 { 827 struct pcxhr_stream *stream; 828 struct snd_pcm_substream *s; 829 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 830 831 switch (cmd) { 832 case SNDRV_PCM_TRIGGER_START: 833 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_START\n"); 834 if (snd_pcm_stream_linked(subs)) { 835 snd_pcm_group_for_each_entry(s, subs) { 836 if (snd_pcm_substream_chip(s) != chip) 837 continue; 838 stream = s->runtime->private_data; 839 stream->status = 840 PCXHR_STREAM_STATUS_SCHEDULE_RUN; 841 snd_pcm_trigger_done(s, subs); 842 } 843 pcxhr_start_linked_stream(chip->mgr); 844 } else { 845 stream = subs->runtime->private_data; 846 dev_dbg(chip->card->dev, "Only one Substream %c %d\n", 847 stream->pipe->is_capture ? 'C' : 'P', 848 stream->pipe->first_audio); 849 if (pcxhr_set_format(stream)) 850 return -EINVAL; 851 if (pcxhr_update_r_buffer(stream)) 852 return -EINVAL; 853 854 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN; 855 if (pcxhr_set_stream_state(chip, stream)) 856 return -EINVAL; 857 stream->status = PCXHR_STREAM_STATUS_RUNNING; 858 } 859 break; 860 case SNDRV_PCM_TRIGGER_STOP: 861 dev_dbg(chip->card->dev, "SNDRV_PCM_TRIGGER_STOP\n"); 862 snd_pcm_group_for_each_entry(s, subs) { 863 stream = s->runtime->private_data; 864 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP; 865 if (pcxhr_set_stream_state(chip, stream)) 866 return -EINVAL; 867 snd_pcm_trigger_done(s, subs); 868 } 869 break; 870 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 871 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 872 /* TODO */ 873 default: 874 return -EINVAL; 875 } 876 return 0; 877 } 878 879 880 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start) 881 { 882 struct pcxhr_rmh rmh; 883 int err; 884 885 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT); 886 if (start) { 887 /* last dsp time invalid */ 888 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; 889 rmh.cmd[0] |= mgr->granularity; 890 } 891 err = pcxhr_send_msg(mgr, &rmh); 892 if (err < 0) 893 dev_err(&mgr->pci->dev, "error pcxhr_hardware_timer err(%x)\n", 894 err); 895 return err; 896 } 897 898 /* 899 * prepare callback for all pcms 900 */ 901 static int pcxhr_prepare(struct snd_pcm_substream *subs) 902 { 903 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 904 struct pcxhr_mgr *mgr = chip->mgr; 905 int err = 0; 906 907 dev_dbg(chip->card->dev, 908 "pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n", 909 subs->runtime->period_size, subs->runtime->periods, 910 subs->runtime->buffer_size); 911 912 mutex_lock(&mgr->setup_mutex); 913 914 do { 915 /* only the first stream can choose the sample rate */ 916 /* set the clock only once (first stream) */ 917 if (mgr->sample_rate != subs->runtime->rate) { 918 err = pcxhr_set_clock(mgr, subs->runtime->rate); 919 if (err) 920 break; 921 if (mgr->sample_rate == 0) 922 /* start the DSP-timer */ 923 err = pcxhr_hardware_timer(mgr, 1); 924 mgr->sample_rate = subs->runtime->rate; 925 } 926 } while(0); /* do only once (so we can use break instead of goto) */ 927 928 mutex_unlock(&mgr->setup_mutex); 929 930 return err; 931 } 932 933 934 /* 935 * HW_PARAMS callback for all pcms 936 */ 937 static int pcxhr_hw_params(struct snd_pcm_substream *subs, 938 struct snd_pcm_hw_params *hw) 939 { 940 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 941 struct pcxhr_mgr *mgr = chip->mgr; 942 struct pcxhr_stream *stream = subs->runtime->private_data; 943 944 mutex_lock(&mgr->setup_mutex); 945 946 /* set up channels */ 947 stream->channels = params_channels(hw); 948 /* set up format for the stream */ 949 stream->format = params_format(hw); 950 951 mutex_unlock(&mgr->setup_mutex); 952 953 return 0; 954 } 955 956 957 /* 958 * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max 959 */ 960 static const struct snd_pcm_hardware pcxhr_caps = 961 { 962 .info = (SNDRV_PCM_INFO_MMAP | 963 SNDRV_PCM_INFO_INTERLEAVED | 964 SNDRV_PCM_INFO_MMAP_VALID | 965 SNDRV_PCM_INFO_SYNC_START), 966 .formats = (SNDRV_PCM_FMTBIT_U8 | 967 SNDRV_PCM_FMTBIT_S16_LE | 968 SNDRV_PCM_FMTBIT_S16_BE | 969 SNDRV_PCM_FMTBIT_S24_3LE | 970 SNDRV_PCM_FMTBIT_S24_3BE | 971 SNDRV_PCM_FMTBIT_FLOAT_LE), 972 .rates = (SNDRV_PCM_RATE_CONTINUOUS | 973 SNDRV_PCM_RATE_8000_192000), 974 .rate_min = 8000, 975 .rate_max = 192000, 976 .channels_min = 1, 977 .channels_max = 2, 978 .buffer_bytes_max = (32*1024), 979 /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */ 980 .period_bytes_min = (2*PCXHR_GRANULARITY), 981 .period_bytes_max = (16*1024), 982 .periods_min = 2, 983 .periods_max = (32*1024/PCXHR_GRANULARITY), 984 }; 985 986 987 static int pcxhr_open(struct snd_pcm_substream *subs) 988 { 989 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 990 struct pcxhr_mgr *mgr = chip->mgr; 991 struct snd_pcm_runtime *runtime = subs->runtime; 992 struct pcxhr_stream *stream; 993 int err; 994 995 mutex_lock(&mgr->setup_mutex); 996 997 /* copy the struct snd_pcm_hardware struct */ 998 runtime->hw = pcxhr_caps; 999 1000 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) { 1001 dev_dbg(chip->card->dev, "pcxhr_open playback chip%d subs%d\n", 1002 chip->chip_idx, subs->number); 1003 stream = &chip->playback_stream[subs->number]; 1004 } else { 1005 dev_dbg(chip->card->dev, "pcxhr_open capture chip%d subs%d\n", 1006 chip->chip_idx, subs->number); 1007 if (mgr->mono_capture) 1008 runtime->hw.channels_max = 1; 1009 else 1010 runtime->hw.channels_min = 2; 1011 stream = &chip->capture_stream[subs->number]; 1012 } 1013 if (stream->status != PCXHR_STREAM_STATUS_FREE){ 1014 /* streams in use */ 1015 dev_err(chip->card->dev, "pcxhr_open chip%d subs%d in use\n", 1016 chip->chip_idx, subs->number); 1017 mutex_unlock(&mgr->setup_mutex); 1018 return -EBUSY; 1019 } 1020 1021 /* float format support is in some cases buggy on stereo cards */ 1022 if (mgr->is_hr_stereo) 1023 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE; 1024 1025 /* buffer-size should better be multiple of period-size */ 1026 err = snd_pcm_hw_constraint_integer(runtime, 1027 SNDRV_PCM_HW_PARAM_PERIODS); 1028 if (err < 0) { 1029 mutex_unlock(&mgr->setup_mutex); 1030 return err; 1031 } 1032 1033 /* if a sample rate is already used or fixed by external clock, 1034 * the stream cannot change 1035 */ 1036 if (mgr->sample_rate) 1037 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate; 1038 else { 1039 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) { 1040 int external_rate; 1041 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type, 1042 &external_rate) || 1043 external_rate == 0) { 1044 /* cannot detect the external clock rate */ 1045 mutex_unlock(&mgr->setup_mutex); 1046 return -EBUSY; 1047 } 1048 runtime->hw.rate_min = external_rate; 1049 runtime->hw.rate_max = external_rate; 1050 } 1051 } 1052 1053 stream->status = PCXHR_STREAM_STATUS_OPEN; 1054 stream->substream = subs; 1055 stream->channels = 0; /* not configured yet */ 1056 1057 runtime->private_data = stream; 1058 1059 /* better get a divisor of granularity values (96 or 192) */ 1060 snd_pcm_hw_constraint_step(runtime, 0, 1061 SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32); 1062 snd_pcm_hw_constraint_step(runtime, 0, 1063 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32); 1064 snd_pcm_set_sync(subs); 1065 1066 mgr->ref_count_rate++; 1067 1068 mutex_unlock(&mgr->setup_mutex); 1069 return 0; 1070 } 1071 1072 1073 static int pcxhr_close(struct snd_pcm_substream *subs) 1074 { 1075 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 1076 struct pcxhr_mgr *mgr = chip->mgr; 1077 struct pcxhr_stream *stream = subs->runtime->private_data; 1078 1079 mutex_lock(&mgr->setup_mutex); 1080 1081 dev_dbg(chip->card->dev, "pcxhr_close chip%d subs%d\n", 1082 chip->chip_idx, subs->number); 1083 1084 /* sample rate released */ 1085 if (--mgr->ref_count_rate == 0) { 1086 mgr->sample_rate = 0; /* the sample rate is no more locked */ 1087 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */ 1088 } 1089 1090 stream->status = PCXHR_STREAM_STATUS_FREE; 1091 stream->substream = NULL; 1092 1093 mutex_unlock(&mgr->setup_mutex); 1094 1095 return 0; 1096 } 1097 1098 1099 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs) 1100 { 1101 u_int32_t timer_period_frag; 1102 int timer_buf_periods; 1103 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 1104 struct snd_pcm_runtime *runtime = subs->runtime; 1105 struct pcxhr_stream *stream = runtime->private_data; 1106 1107 mutex_lock(&chip->mgr->lock); 1108 1109 /* get the period fragment and the nb of periods in the buffer */ 1110 timer_period_frag = stream->timer_period_frag; 1111 timer_buf_periods = stream->timer_buf_periods; 1112 1113 mutex_unlock(&chip->mgr->lock); 1114 1115 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) + 1116 timer_period_frag); 1117 } 1118 1119 1120 static const struct snd_pcm_ops pcxhr_ops = { 1121 .open = pcxhr_open, 1122 .close = pcxhr_close, 1123 .prepare = pcxhr_prepare, 1124 .hw_params = pcxhr_hw_params, 1125 .trigger = pcxhr_trigger, 1126 .pointer = pcxhr_stream_pointer, 1127 }; 1128 1129 /* 1130 */ 1131 int pcxhr_create_pcm(struct snd_pcxhr *chip) 1132 { 1133 int err; 1134 struct snd_pcm *pcm; 1135 char name[32]; 1136 1137 snprintf(name, sizeof(name), "pcxhr %d", chip->chip_idx); 1138 if ((err = snd_pcm_new(chip->card, name, 0, 1139 chip->nb_streams_play, 1140 chip->nb_streams_capt, &pcm)) < 0) { 1141 dev_err(chip->card->dev, "cannot create pcm %s\n", name); 1142 return err; 1143 } 1144 pcm->private_data = chip; 1145 1146 if (chip->nb_streams_play) 1147 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops); 1148 if (chip->nb_streams_capt) 1149 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops); 1150 1151 pcm->info_flags = 0; 1152 pcm->nonatomic = true; 1153 strcpy(pcm->name, name); 1154 1155 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 1156 &chip->mgr->pci->dev, 1157 32*1024, 32*1024); 1158 chip->pcm = pcm; 1159 return 0; 1160 } 1161 1162 static int pcxhr_chip_free(struct snd_pcxhr *chip) 1163 { 1164 kfree(chip); 1165 return 0; 1166 } 1167 1168 static int pcxhr_chip_dev_free(struct snd_device *device) 1169 { 1170 struct snd_pcxhr *chip = device->device_data; 1171 return pcxhr_chip_free(chip); 1172 } 1173 1174 1175 /* 1176 */ 1177 static int pcxhr_create(struct pcxhr_mgr *mgr, 1178 struct snd_card *card, int idx) 1179 { 1180 int err; 1181 struct snd_pcxhr *chip; 1182 static const struct snd_device_ops ops = { 1183 .dev_free = pcxhr_chip_dev_free, 1184 }; 1185 1186 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1187 if (!chip) 1188 return -ENOMEM; 1189 1190 chip->card = card; 1191 chip->chip_idx = idx; 1192 chip->mgr = mgr; 1193 card->sync_irq = mgr->irq; 1194 1195 if (idx < mgr->playback_chips) 1196 /* stereo or mono streams */ 1197 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS; 1198 1199 if (idx < mgr->capture_chips) { 1200 if (mgr->mono_capture) 1201 chip->nb_streams_capt = 2; /* 2 mono streams */ 1202 else 1203 chip->nb_streams_capt = 1; /* or 1 stereo stream */ 1204 } 1205 1206 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1207 pcxhr_chip_free(chip); 1208 return err; 1209 } 1210 1211 mgr->chip[idx] = chip; 1212 1213 return 0; 1214 } 1215 1216 /* proc interface */ 1217 static void pcxhr_proc_info(struct snd_info_entry *entry, 1218 struct snd_info_buffer *buffer) 1219 { 1220 struct snd_pcxhr *chip = entry->private_data; 1221 struct pcxhr_mgr *mgr = chip->mgr; 1222 1223 snd_iprintf(buffer, "\n%s\n", mgr->name); 1224 1225 /* stats available when embedded DSP is running */ 1226 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1227 struct pcxhr_rmh rmh; 1228 short ver_maj = (mgr->dsp_version >> 16) & 0xff; 1229 short ver_min = (mgr->dsp_version >> 8) & 0xff; 1230 short ver_build = mgr->dsp_version & 0xff; 1231 snd_iprintf(buffer, "module version %s\n", 1232 PCXHR_DRIVER_VERSION_STRING); 1233 snd_iprintf(buffer, "dsp version %d.%d.%d\n", 1234 ver_maj, ver_min, ver_build); 1235 if (mgr->board_has_analog) 1236 snd_iprintf(buffer, "analog io available\n"); 1237 else 1238 snd_iprintf(buffer, "digital only board\n"); 1239 1240 /* calc cpu load of the dsp */ 1241 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES); 1242 if( ! pcxhr_send_msg(mgr, &rmh) ) { 1243 int cur = rmh.stat[0]; 1244 int ref = rmh.stat[1]; 1245 if (ref > 0) { 1246 if (mgr->sample_rate_real != 0 && 1247 mgr->sample_rate_real != 48000) { 1248 ref = (ref * 48000) / 1249 mgr->sample_rate_real; 1250 if (mgr->sample_rate_real >= 1251 PCXHR_IRQ_TIMER_FREQ) 1252 ref *= 2; 1253 } 1254 cur = 100 - (100 * cur) / ref; 1255 snd_iprintf(buffer, "cpu load %d%%\n", cur); 1256 snd_iprintf(buffer, "buffer pool %d/%d\n", 1257 rmh.stat[2], rmh.stat[3]); 1258 } 1259 } 1260 snd_iprintf(buffer, "dma granularity : %d\n", 1261 mgr->granularity); 1262 snd_iprintf(buffer, "dsp time errors : %d\n", 1263 mgr->dsp_time_err); 1264 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n", 1265 mgr->async_err_pipe_xrun); 1266 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n", 1267 mgr->async_err_stream_xrun); 1268 snd_iprintf(buffer, "dsp async last other error : %x\n", 1269 mgr->async_err_other_last); 1270 /* debug zone dsp */ 1271 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS; 1272 rmh.cmd_len = 1; 1273 rmh.stat_len = PCXHR_SIZE_MAX_STATUS; 1274 rmh.dsp_stat = 0; 1275 rmh.cmd_idx = CMD_LAST_INDEX; 1276 if( ! pcxhr_send_msg(mgr, &rmh) ) { 1277 int i; 1278 if (rmh.stat_len > 8) 1279 rmh.stat_len = 8; 1280 for (i = 0; i < rmh.stat_len; i++) 1281 snd_iprintf(buffer, "debug[%02d] = %06x\n", 1282 i, rmh.stat[i]); 1283 } 1284 } else 1285 snd_iprintf(buffer, "no firmware loaded\n"); 1286 snd_iprintf(buffer, "\n"); 1287 } 1288 static void pcxhr_proc_sync(struct snd_info_entry *entry, 1289 struct snd_info_buffer *buffer) 1290 { 1291 struct snd_pcxhr *chip = entry->private_data; 1292 struct pcxhr_mgr *mgr = chip->mgr; 1293 static const char *textsHR22[3] = { 1294 "Internal", "AES Sync", "AES 1" 1295 }; 1296 static const char *textsPCXHR[7] = { 1297 "Internal", "Word", "AES Sync", 1298 "AES 1", "AES 2", "AES 3", "AES 4" 1299 }; 1300 const char **texts; 1301 int max_clock; 1302 if (mgr->is_hr_stereo) { 1303 texts = textsHR22; 1304 max_clock = HR22_CLOCK_TYPE_MAX; 1305 } else { 1306 texts = textsPCXHR; 1307 max_clock = PCXHR_CLOCK_TYPE_MAX; 1308 } 1309 1310 snd_iprintf(buffer, "\n%s\n", mgr->name); 1311 snd_iprintf(buffer, "Current Sample Clock\t: %s\n", 1312 texts[mgr->cur_clock_type]); 1313 snd_iprintf(buffer, "Current Sample Rate\t= %d\n", 1314 mgr->sample_rate_real); 1315 /* commands available when embedded DSP is running */ 1316 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1317 int i, err, sample_rate; 1318 for (i = 1; i <= max_clock; i++) { 1319 err = pcxhr_get_external_clock(mgr, i, &sample_rate); 1320 if (err) 1321 break; 1322 snd_iprintf(buffer, "%s Clock\t\t= %d\n", 1323 texts[i], sample_rate); 1324 } 1325 } else 1326 snd_iprintf(buffer, "no firmware loaded\n"); 1327 snd_iprintf(buffer, "\n"); 1328 } 1329 1330 static void pcxhr_proc_gpio_read(struct snd_info_entry *entry, 1331 struct snd_info_buffer *buffer) 1332 { 1333 struct snd_pcxhr *chip = entry->private_data; 1334 struct pcxhr_mgr *mgr = chip->mgr; 1335 /* commands available when embedded DSP is running */ 1336 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1337 /* gpio ports on stereo boards only available */ 1338 int value = 0; 1339 hr222_read_gpio(mgr, 1, &value); /* GPI */ 1340 snd_iprintf(buffer, "GPI: 0x%x\n", value); 1341 hr222_read_gpio(mgr, 0, &value); /* GP0 */ 1342 snd_iprintf(buffer, "GPO: 0x%x\n", value); 1343 } else 1344 snd_iprintf(buffer, "no firmware loaded\n"); 1345 snd_iprintf(buffer, "\n"); 1346 } 1347 static void pcxhr_proc_gpo_write(struct snd_info_entry *entry, 1348 struct snd_info_buffer *buffer) 1349 { 1350 struct snd_pcxhr *chip = entry->private_data; 1351 struct pcxhr_mgr *mgr = chip->mgr; 1352 char line[64]; 1353 int value; 1354 /* commands available when embedded DSP is running */ 1355 if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) 1356 return; 1357 while (!snd_info_get_line(buffer, line, sizeof(line))) { 1358 if (sscanf(line, "GPO: 0x%x", &value) != 1) 1359 continue; 1360 hr222_write_gpo(mgr, value); /* GP0 */ 1361 } 1362 } 1363 1364 /* Access to the results of the CMD_GET_TIME_CODE RMH */ 1365 #define TIME_CODE_VALID_MASK 0x00800000 1366 #define TIME_CODE_NEW_MASK 0x00400000 1367 #define TIME_CODE_BACK_MASK 0x00200000 1368 #define TIME_CODE_WAIT_MASK 0x00100000 1369 1370 /* Values for the CMD_MANAGE_SIGNAL RMH */ 1371 #define MANAGE_SIGNAL_TIME_CODE 0x01 1372 #define MANAGE_SIGNAL_MIDI 0x02 1373 1374 /* linear time code read proc*/ 1375 static void pcxhr_proc_ltc(struct snd_info_entry *entry, 1376 struct snd_info_buffer *buffer) 1377 { 1378 struct snd_pcxhr *chip = entry->private_data; 1379 struct pcxhr_mgr *mgr = chip->mgr; 1380 struct pcxhr_rmh rmh; 1381 unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm; 1382 int err; 1383 /* commands available when embedded DSP is running */ 1384 if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) { 1385 snd_iprintf(buffer, "no firmware loaded\n"); 1386 return; 1387 } 1388 if (!mgr->capture_ltc) { 1389 pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL); 1390 rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE; 1391 err = pcxhr_send_msg(mgr, &rmh); 1392 if (err) { 1393 snd_iprintf(buffer, "ltc not activated (%d)\n", err); 1394 return; 1395 } 1396 if (mgr->is_hr_stereo) 1397 hr222_manage_timecode(mgr, 1); 1398 else 1399 pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE, 1400 REG_CONT_VALSMPTE, NULL); 1401 mgr->capture_ltc = 1; 1402 } 1403 pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE); 1404 err = pcxhr_send_msg(mgr, &rmh); 1405 if (err) { 1406 snd_iprintf(buffer, "ltc read error (err=%d)\n", err); 1407 return ; 1408 } 1409 ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf); 1410 ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf); 1411 ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf); 1412 ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf); 1413 1414 snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n", 1415 ltcHrs, ltcMin, ltcSec, ltcFrm); 1416 snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff, 1417 rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff); 1418 /*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n", 1419 rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/ 1420 if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) { 1421 snd_iprintf(buffer, "warning: linear timecode not valid\n"); 1422 } 1423 } 1424 1425 static void pcxhr_proc_init(struct snd_pcxhr *chip) 1426 { 1427 snd_card_ro_proc_new(chip->card, "info", chip, pcxhr_proc_info); 1428 snd_card_ro_proc_new(chip->card, "sync", chip, pcxhr_proc_sync); 1429 /* gpio available on stereo sound cards only */ 1430 if (chip->mgr->is_hr_stereo) 1431 snd_card_rw_proc_new(chip->card, "gpio", chip, 1432 pcxhr_proc_gpio_read, 1433 pcxhr_proc_gpo_write); 1434 snd_card_ro_proc_new(chip->card, "ltc", chip, pcxhr_proc_ltc); 1435 } 1436 /* end of proc interface */ 1437 1438 /* 1439 * release all the cards assigned to a manager instance 1440 */ 1441 static int pcxhr_free(struct pcxhr_mgr *mgr) 1442 { 1443 unsigned int i; 1444 1445 for (i = 0; i < mgr->num_cards; i++) { 1446 if (mgr->chip[i]) 1447 snd_card_free(mgr->chip[i]->card); 1448 } 1449 1450 /* reset board if some firmware was loaded */ 1451 if(mgr->dsp_loaded) { 1452 pcxhr_reset_board(mgr); 1453 dev_dbg(&mgr->pci->dev, "reset pcxhr !\n"); 1454 } 1455 1456 /* release irq */ 1457 if (mgr->irq >= 0) 1458 free_irq(mgr->irq, mgr); 1459 1460 pci_release_regions(mgr->pci); 1461 1462 /* free hostport purgebuffer */ 1463 if (mgr->hostport.area) { 1464 snd_dma_free_pages(&mgr->hostport); 1465 mgr->hostport.area = NULL; 1466 } 1467 1468 kfree(mgr->prmh); 1469 1470 pci_disable_device(mgr->pci); 1471 kfree(mgr); 1472 return 0; 1473 } 1474 1475 /* 1476 * probe function - creates the card manager 1477 */ 1478 static int pcxhr_probe(struct pci_dev *pci, 1479 const struct pci_device_id *pci_id) 1480 { 1481 static int dev; 1482 struct pcxhr_mgr *mgr; 1483 unsigned int i; 1484 int err; 1485 size_t size; 1486 char *card_name; 1487 1488 if (dev >= SNDRV_CARDS) 1489 return -ENODEV; 1490 if (! enable[dev]) { 1491 dev++; 1492 return -ENOENT; 1493 } 1494 1495 /* enable PCI device */ 1496 if ((err = pci_enable_device(pci)) < 0) 1497 return err; 1498 pci_set_master(pci); 1499 1500 /* check if we can restrict PCI DMA transfers to 32 bits */ 1501 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(32)) < 0) { 1502 dev_err(&pci->dev, 1503 "architecture does not support 32bit PCI busmaster DMA\n"); 1504 pci_disable_device(pci); 1505 return -ENXIO; 1506 } 1507 1508 /* alloc card manager */ 1509 mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); 1510 if (! mgr) { 1511 pci_disable_device(pci); 1512 return -ENOMEM; 1513 } 1514 1515 if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) { 1516 kfree(mgr); 1517 pci_disable_device(pci); 1518 return -ENODEV; 1519 } 1520 card_name = 1521 pcxhr_board_params[pci_id->driver_data].board_name; 1522 mgr->playback_chips = 1523 pcxhr_board_params[pci_id->driver_data].playback_chips; 1524 mgr->capture_chips = 1525 pcxhr_board_params[pci_id->driver_data].capture_chips; 1526 mgr->fw_file_set = 1527 pcxhr_board_params[pci_id->driver_data].fw_file_set; 1528 mgr->firmware_num = 1529 pcxhr_board_params[pci_id->driver_data].firmware_num; 1530 mgr->mono_capture = mono[dev]; 1531 mgr->is_hr_stereo = (mgr->playback_chips == 1); 1532 mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr); 1533 mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr); 1534 1535 if (mgr->is_hr_stereo) 1536 mgr->granularity = PCXHR_GRANULARITY_HR22; 1537 else 1538 mgr->granularity = PCXHR_GRANULARITY; 1539 1540 /* resource assignment */ 1541 if ((err = pci_request_regions(pci, card_name)) < 0) { 1542 kfree(mgr); 1543 pci_disable_device(pci); 1544 return err; 1545 } 1546 for (i = 0; i < 3; i++) 1547 mgr->port[i] = pci_resource_start(pci, i); 1548 1549 mgr->pci = pci; 1550 mgr->irq = -1; 1551 1552 if (request_threaded_irq(pci->irq, pcxhr_interrupt, 1553 pcxhr_threaded_irq, IRQF_SHARED, 1554 KBUILD_MODNAME, mgr)) { 1555 dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq); 1556 pcxhr_free(mgr); 1557 return -EBUSY; 1558 } 1559 mgr->irq = pci->irq; 1560 1561 snprintf(mgr->name, sizeof(mgr->name), 1562 "Digigram at 0x%lx & 0x%lx, 0x%lx irq %i", 1563 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq); 1564 1565 /* ISR lock */ 1566 mutex_init(&mgr->lock); 1567 mutex_init(&mgr->msg_lock); 1568 1569 /* init setup mutex*/ 1570 mutex_init(&mgr->setup_mutex); 1571 1572 mgr->prmh = kmalloc(sizeof(*mgr->prmh) + 1573 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - 1574 PCXHR_SIZE_MAX_STATUS), 1575 GFP_KERNEL); 1576 if (! mgr->prmh) { 1577 pcxhr_free(mgr); 1578 return -ENOMEM; 1579 } 1580 1581 for (i=0; i < PCXHR_MAX_CARDS; i++) { 1582 struct snd_card *card; 1583 char tmpid[16]; 1584 int idx; 1585 1586 if (i >= max(mgr->playback_chips, mgr->capture_chips)) 1587 break; 1588 mgr->num_cards++; 1589 1590 if (index[dev] < 0) 1591 idx = index[dev]; 1592 else 1593 idx = index[dev] + i; 1594 1595 snprintf(tmpid, sizeof(tmpid), "%s-%d", 1596 id[dev] ? id[dev] : card_name, i); 1597 err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE, 1598 0, &card); 1599 1600 if (err < 0) { 1601 dev_err(&pci->dev, "cannot allocate the card %d\n", i); 1602 pcxhr_free(mgr); 1603 return err; 1604 } 1605 1606 strcpy(card->driver, DRIVER_NAME); 1607 snprintf(card->shortname, sizeof(card->shortname), 1608 "Digigram [PCM #%d]", i); 1609 snprintf(card->longname, sizeof(card->longname), 1610 "%s [PCM #%d]", mgr->name, i); 1611 1612 if ((err = pcxhr_create(mgr, card, i)) < 0) { 1613 snd_card_free(card); 1614 pcxhr_free(mgr); 1615 return err; 1616 } 1617 1618 if (i == 0) 1619 /* init proc interface only for chip0 */ 1620 pcxhr_proc_init(mgr->chip[i]); 1621 1622 if ((err = snd_card_register(card)) < 0) { 1623 pcxhr_free(mgr); 1624 return err; 1625 } 1626 } 1627 1628 /* create hostport purgebuffer */ 1629 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport)); 1630 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 1631 size, &mgr->hostport) < 0) { 1632 pcxhr_free(mgr); 1633 return -ENOMEM; 1634 } 1635 /* init purgebuffer */ 1636 memset(mgr->hostport.area, 0, size); 1637 1638 /* create a DSP loader */ 1639 err = pcxhr_setup_firmware(mgr); 1640 if (err < 0) { 1641 pcxhr_free(mgr); 1642 return err; 1643 } 1644 1645 pci_set_drvdata(pci, mgr); 1646 dev++; 1647 return 0; 1648 } 1649 1650 static void pcxhr_remove(struct pci_dev *pci) 1651 { 1652 pcxhr_free(pci_get_drvdata(pci)); 1653 } 1654 1655 static struct pci_driver pcxhr_driver = { 1656 .name = KBUILD_MODNAME, 1657 .id_table = pcxhr_ids, 1658 .probe = pcxhr_probe, 1659 .remove = pcxhr_remove, 1660 }; 1661 1662 module_pci_driver(pcxhr_driver); 1663