xref: /openbmc/linux/sound/pci/pcxhr/pcxhr.c (revision 6774def6)
1 /*
2  * Driver for Digigram pcxhr compatible soundcards
3  *
4  * main file with alsa callbacks
5  *
6  * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7  *
8  *   This program is free software; you can redistribute it and/or modify
9  *   it under the terms of the GNU General Public License as published by
10  *   the Free Software Foundation; either version 2 of the License, or
11  *   (at your option) any later version.
12  *
13  *   This program is distributed in the hope that it will be useful,
14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *   GNU General Public License for more details.
17  *
18  *   You should have received a copy of the GNU General Public License
19  *   along with this program; if not, write to the Free Software
20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21  */
22 
23 
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/slab.h>
27 #include <linux/pci.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/delay.h>
30 #include <linux/module.h>
31 #include <linux/mutex.h>
32 
33 #include <sound/core.h>
34 #include <sound/initval.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include "pcxhr.h"
40 #include "pcxhr_mixer.h"
41 #include "pcxhr_hwdep.h"
42 #include "pcxhr_core.h"
43 #include "pcxhr_mix22.h"
44 
45 #define DRIVER_NAME "pcxhr"
46 
47 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>, "
48 	      "Marc Titinger <titinger@digigram.com>");
49 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
50 MODULE_LICENSE("GPL");
51 MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
52 
53 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;	/* Index 0-MAX */
54 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;	/* ID for this card */
55 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
56 static bool mono[SNDRV_CARDS];				/* capture  mono only */
57 
58 module_param_array(index, int, NULL, 0444);
59 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
60 module_param_array(id, charp, NULL, 0444);
61 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
62 module_param_array(enable, bool, NULL, 0444);
63 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
64 module_param_array(mono, bool, NULL, 0444);
65 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
66 
67 enum {
68 	PCI_ID_VX882HR,
69 	PCI_ID_PCX882HR,
70 	PCI_ID_VX881HR,
71 	PCI_ID_PCX881HR,
72 	PCI_ID_VX882E,
73 	PCI_ID_PCX882E,
74 	PCI_ID_VX881E,
75 	PCI_ID_PCX881E,
76 	PCI_ID_VX1222HR,
77 	PCI_ID_PCX1222HR,
78 	PCI_ID_VX1221HR,
79 	PCI_ID_PCX1221HR,
80 	PCI_ID_VX1222E,
81 	PCI_ID_PCX1222E,
82 	PCI_ID_VX1221E,
83 	PCI_ID_PCX1221E,
84 	PCI_ID_VX222HR,
85 	PCI_ID_VX222E,
86 	PCI_ID_PCX22HR,
87 	PCI_ID_PCX22E,
88 	PCI_ID_VX222HRMIC,
89 	PCI_ID_VX222E_MIC,
90 	PCI_ID_PCX924HR,
91 	PCI_ID_PCX924E,
92 	PCI_ID_PCX924HRMIC,
93 	PCI_ID_PCX924E_MIC,
94 	PCI_ID_VX442HR,
95 	PCI_ID_PCX442HR,
96 	PCI_ID_VX442E,
97 	PCI_ID_PCX442E,
98 	PCI_ID_VX822HR,
99 	PCI_ID_PCX822HR,
100 	PCI_ID_VX822E,
101 	PCI_ID_PCX822E,
102 	PCI_ID_LAST
103 };
104 
105 static const struct pci_device_id pcxhr_ids[] = {
106 	{ 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },
107 	{ 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },
108 	{ 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },
109 	{ 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },
110 	{ 0x10b5, 0x9056, 0x1369, 0xb021, 0, 0, PCI_ID_VX882E, },
111 	{ 0x10b5, 0x9056, 0x1369, 0xb121, 0, 0, PCI_ID_PCX882E, },
112 	{ 0x10b5, 0x9056, 0x1369, 0xb221, 0, 0, PCI_ID_VX881E, },
113 	{ 0x10b5, 0x9056, 0x1369, 0xb321, 0, 0, PCI_ID_PCX881E, },
114 	{ 0x10b5, 0x9656, 0x1369, 0xb401, 0, 0, PCI_ID_VX1222HR, },
115 	{ 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, },
116 	{ 0x10b5, 0x9656, 0x1369, 0xb601, 0, 0, PCI_ID_VX1221HR, },
117 	{ 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, },
118 	{ 0x10b5, 0x9056, 0x1369, 0xb421, 0, 0, PCI_ID_VX1222E, },
119 	{ 0x10b5, 0x9056, 0x1369, 0xb521, 0, 0, PCI_ID_PCX1222E, },
120 	{ 0x10b5, 0x9056, 0x1369, 0xb621, 0, 0, PCI_ID_VX1221E, },
121 	{ 0x10b5, 0x9056, 0x1369, 0xb721, 0, 0, PCI_ID_PCX1221E, },
122 	{ 0x10b5, 0x9056, 0x1369, 0xba01, 0, 0, PCI_ID_VX222HR, },
123 	{ 0x10b5, 0x9056, 0x1369, 0xba21, 0, 0, PCI_ID_VX222E, },
124 	{ 0x10b5, 0x9056, 0x1369, 0xbd01, 0, 0, PCI_ID_PCX22HR, },
125 	{ 0x10b5, 0x9056, 0x1369, 0xbd21, 0, 0, PCI_ID_PCX22E, },
126 	{ 0x10b5, 0x9056, 0x1369, 0xbc01, 0, 0, PCI_ID_VX222HRMIC, },
127 	{ 0x10b5, 0x9056, 0x1369, 0xbc21, 0, 0, PCI_ID_VX222E_MIC, },
128 	{ 0x10b5, 0x9056, 0x1369, 0xbb01, 0, 0, PCI_ID_PCX924HR, },
129 	{ 0x10b5, 0x9056, 0x1369, 0xbb21, 0, 0, PCI_ID_PCX924E, },
130 	{ 0x10b5, 0x9056, 0x1369, 0xbf01, 0, 0, PCI_ID_PCX924HRMIC, },
131 	{ 0x10b5, 0x9056, 0x1369, 0xbf21, 0, 0, PCI_ID_PCX924E_MIC, },
132 	{ 0x10b5, 0x9656, 0x1369, 0xd001, 0, 0, PCI_ID_VX442HR, },
133 	{ 0x10b5, 0x9656, 0x1369, 0xd101, 0, 0, PCI_ID_PCX442HR, },
134 	{ 0x10b5, 0x9056, 0x1369, 0xd021, 0, 0, PCI_ID_VX442E, },
135 	{ 0x10b5, 0x9056, 0x1369, 0xd121, 0, 0, PCI_ID_PCX442E, },
136 	{ 0x10b5, 0x9656, 0x1369, 0xd201, 0, 0, PCI_ID_VX822HR, },
137 	{ 0x10b5, 0x9656, 0x1369, 0xd301, 0, 0, PCI_ID_PCX822HR, },
138 	{ 0x10b5, 0x9056, 0x1369, 0xd221, 0, 0, PCI_ID_VX822E, },
139 	{ 0x10b5, 0x9056, 0x1369, 0xd321, 0, 0, PCI_ID_PCX822E, },
140 	{ 0, }
141 };
142 
143 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
144 
145 struct board_parameters {
146 	char* board_name;
147 	short playback_chips;
148 	short capture_chips;
149 	short fw_file_set;
150 	short firmware_num;
151 };
152 static struct board_parameters pcxhr_board_params[] = {
153 [PCI_ID_VX882HR] =      { "VX882HR",      4, 4, 0, 41 },
154 [PCI_ID_PCX882HR] =     { "PCX882HR",     4, 4, 0, 41 },
155 [PCI_ID_VX881HR] =      { "VX881HR",      4, 4, 0, 41 },
156 [PCI_ID_PCX881HR] =     { "PCX881HR",     4, 4, 0, 41 },
157 [PCI_ID_VX882E] =       { "VX882e",       4, 4, 1, 41 },
158 [PCI_ID_PCX882E] =      { "PCX882e",      4, 4, 1, 41 },
159 [PCI_ID_VX881E] =       { "VX881e",       4, 4, 1, 41 },
160 [PCI_ID_PCX881E] =      { "PCX881e",      4, 4, 1, 41 },
161 [PCI_ID_VX1222HR] =     { "VX1222HR",     6, 1, 2, 42 },
162 [PCI_ID_PCX1222HR] =    { "PCX1222HR",    6, 1, 2, 42 },
163 [PCI_ID_VX1221HR] =     { "VX1221HR",     6, 1, 2, 42 },
164 [PCI_ID_PCX1221HR] =    { "PCX1221HR",    6, 1, 2, 42 },
165 [PCI_ID_VX1222E] =      { "VX1222e",      6, 1, 3, 42 },
166 [PCI_ID_PCX1222E] =     { "PCX1222e",     6, 1, 3, 42 },
167 [PCI_ID_VX1221E] =      { "VX1221e",      6, 1, 3, 42 },
168 [PCI_ID_PCX1221E] =     { "PCX1221e",     6, 1, 3, 42 },
169 [PCI_ID_VX222HR] =      { "VX222HR",      1, 1, 4, 44 },
170 [PCI_ID_VX222E] =       { "VX222e",       1, 1, 4, 44 },
171 [PCI_ID_PCX22HR] =      { "PCX22HR",      1, 0, 4, 44 },
172 [PCI_ID_PCX22E] =       { "PCX22e",       1, 0, 4, 44 },
173 [PCI_ID_VX222HRMIC] =   { "VX222HR-Mic",  1, 1, 5, 44 },
174 [PCI_ID_VX222E_MIC] =   { "VX222e-Mic",   1, 1, 5, 44 },
175 [PCI_ID_PCX924HR] =     { "PCX924HR",     1, 1, 5, 44 },
176 [PCI_ID_PCX924E] =      { "PCX924e",      1, 1, 5, 44 },
177 [PCI_ID_PCX924HRMIC] =  { "PCX924HR-Mic", 1, 1, 5, 44 },
178 [PCI_ID_PCX924E_MIC] =  { "PCX924e-Mic",  1, 1, 5, 44 },
179 [PCI_ID_VX442HR] =      { "VX442HR",      2, 2, 0, 41 },
180 [PCI_ID_PCX442HR] =     { "PCX442HR",     2, 2, 0, 41 },
181 [PCI_ID_VX442E] =       { "VX442e",       2, 2, 1, 41 },
182 [PCI_ID_PCX442E] =      { "PCX442e",      2, 2, 1, 41 },
183 [PCI_ID_VX822HR] =      { "VX822HR",      4, 1, 2, 42 },
184 [PCI_ID_PCX822HR] =     { "PCX822HR",     4, 1, 2, 42 },
185 [PCI_ID_VX822E] =       { "VX822e",       4, 1, 3, 42 },
186 [PCI_ID_PCX822E] =      { "PCX822e",      4, 1, 3, 42 },
187 };
188 
189 /* boards without hw AES1 and SRC onboard are all using fw_file_set==4 */
190 /* VX222HR, VX222e, PCX22HR and PCX22e */
191 #define PCXHR_BOARD_HAS_AES1(x) (x->fw_file_set != 4)
192 /* some boards do not support 192kHz on digital AES input plugs */
193 #define PCXHR_BOARD_AESIN_NO_192K(x) ((x->capture_chips == 0) || \
194 				      (x->fw_file_set == 0)   || \
195 				      (x->fw_file_set == 2))
196 
197 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
198 				   unsigned int* realfreq)
199 {
200 	unsigned int reg;
201 
202 	if (freq < 6900 || freq > 110000)
203 		return -EINVAL;
204 	reg = (28224000 * 2) / freq;
205 	reg = (reg - 1) / 2;
206 	if (reg < 0x200)
207 		*pllreg = reg + 0x800;
208 	else if (reg < 0x400)
209 		*pllreg = reg & 0x1ff;
210 	else if (reg < 0x800) {
211 		*pllreg = ((reg >> 1) & 0x1ff) + 0x200;
212 		reg &= ~1;
213 	} else {
214 		*pllreg = ((reg >> 2) & 0x1ff) + 0x400;
215 		reg &= ~3;
216 	}
217 	if (realfreq)
218 		*realfreq = (28224000 / (reg + 1));
219 	return 0;
220 }
221 
222 
223 #define PCXHR_FREQ_REG_MASK		0x1f
224 #define PCXHR_FREQ_QUARTZ_48000		0x00
225 #define PCXHR_FREQ_QUARTZ_24000		0x01
226 #define PCXHR_FREQ_QUARTZ_12000		0x09
227 #define PCXHR_FREQ_QUARTZ_32000		0x08
228 #define PCXHR_FREQ_QUARTZ_16000		0x04
229 #define PCXHR_FREQ_QUARTZ_8000		0x0c
230 #define PCXHR_FREQ_QUARTZ_44100		0x02
231 #define PCXHR_FREQ_QUARTZ_22050		0x0a
232 #define PCXHR_FREQ_QUARTZ_11025		0x06
233 #define PCXHR_FREQ_PLL			0x05
234 #define PCXHR_FREQ_QUARTZ_192000	0x10
235 #define PCXHR_FREQ_QUARTZ_96000		0x18
236 #define PCXHR_FREQ_QUARTZ_176400	0x14
237 #define PCXHR_FREQ_QUARTZ_88200		0x1c
238 #define PCXHR_FREQ_QUARTZ_128000	0x12
239 #define PCXHR_FREQ_QUARTZ_64000		0x1a
240 
241 #define PCXHR_FREQ_WORD_CLOCK		0x0f
242 #define PCXHR_FREQ_SYNC_AES		0x0e
243 #define PCXHR_FREQ_AES_1		0x07
244 #define PCXHR_FREQ_AES_2		0x0b
245 #define PCXHR_FREQ_AES_3		0x03
246 #define PCXHR_FREQ_AES_4		0x0d
247 
248 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
249 			       unsigned int *reg, unsigned int *freq)
250 {
251 	unsigned int val, realfreq, pllreg;
252 	struct pcxhr_rmh rmh;
253 	int err;
254 
255 	realfreq = rate;
256 	switch (mgr->use_clock_type) {
257 	case PCXHR_CLOCK_TYPE_INTERNAL :	/* clock by quartz or pll */
258 		switch (rate) {
259 		case 48000 :	val = PCXHR_FREQ_QUARTZ_48000;	break;
260 		case 24000 :	val = PCXHR_FREQ_QUARTZ_24000;	break;
261 		case 12000 :	val = PCXHR_FREQ_QUARTZ_12000;	break;
262 		case 32000 :	val = PCXHR_FREQ_QUARTZ_32000;	break;
263 		case 16000 :	val = PCXHR_FREQ_QUARTZ_16000;	break;
264 		case 8000 :	val = PCXHR_FREQ_QUARTZ_8000;	break;
265 		case 44100 :	val = PCXHR_FREQ_QUARTZ_44100;	break;
266 		case 22050 :	val = PCXHR_FREQ_QUARTZ_22050;	break;
267 		case 11025 :	val = PCXHR_FREQ_QUARTZ_11025;	break;
268 		case 192000 :	val = PCXHR_FREQ_QUARTZ_192000;	break;
269 		case 96000 :	val = PCXHR_FREQ_QUARTZ_96000;	break;
270 		case 176400 :	val = PCXHR_FREQ_QUARTZ_176400;	break;
271 		case 88200 :	val = PCXHR_FREQ_QUARTZ_88200;	break;
272 		case 128000 :	val = PCXHR_FREQ_QUARTZ_128000;	break;
273 		case 64000 :	val = PCXHR_FREQ_QUARTZ_64000;	break;
274 		default :
275 			val = PCXHR_FREQ_PLL;
276 			/* get the value for the pll register */
277 			err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
278 			if (err)
279 				return err;
280 			pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
281 			rmh.cmd[0] |= IO_NUM_REG_GENCLK;
282 			rmh.cmd[1]  = pllreg & MASK_DSP_WORD;
283 			rmh.cmd[2]  = pllreg >> 24;
284 			rmh.cmd_len = 3;
285 			err = pcxhr_send_msg(mgr, &rmh);
286 			if (err < 0) {
287 				dev_err(&mgr->pci->dev,
288 					   "error CMD_ACCESS_IO_WRITE "
289 					   "for PLL register : %x!\n", err);
290 				return err;
291 			}
292 		}
293 		break;
294 	case PCXHR_CLOCK_TYPE_WORD_CLOCK:
295 		val = PCXHR_FREQ_WORD_CLOCK;
296 		break;
297 	case PCXHR_CLOCK_TYPE_AES_SYNC:
298 		val = PCXHR_FREQ_SYNC_AES;
299 		break;
300 	case PCXHR_CLOCK_TYPE_AES_1:
301 		val = PCXHR_FREQ_AES_1;
302 		break;
303 	case PCXHR_CLOCK_TYPE_AES_2:
304 		val = PCXHR_FREQ_AES_2;
305 		break;
306 	case PCXHR_CLOCK_TYPE_AES_3:
307 		val = PCXHR_FREQ_AES_3;
308 		break;
309 	case PCXHR_CLOCK_TYPE_AES_4:
310 		val = PCXHR_FREQ_AES_4;
311 		break;
312 	default:
313 		return -EINVAL;
314 	}
315 	*reg = val;
316 	*freq = realfreq;
317 	return 0;
318 }
319 
320 
321 static int pcxhr_sub_set_clock(struct pcxhr_mgr *mgr,
322 			       unsigned int rate,
323 			       int *changed)
324 {
325 	unsigned int val, realfreq, speed;
326 	struct pcxhr_rmh rmh;
327 	int err;
328 
329 	err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
330 	if (err)
331 		return err;
332 
333 	/* codec speed modes */
334 	if (rate < 55000)
335 		speed = 0;	/* single speed */
336 	else if (rate < 100000)
337 		speed = 1;	/* dual speed */
338 	else
339 		speed = 2;	/* quad speed */
340 	if (mgr->codec_speed != speed) {
341 		pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */
342 		rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
343 		if (DSP_EXT_CMD_SET(mgr)) {
344 			rmh.cmd[1]  = 1;
345 			rmh.cmd_len = 2;
346 		}
347 		err = pcxhr_send_msg(mgr, &rmh);
348 		if (err)
349 			return err;
350 
351 		pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */
352 		rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
353 		rmh.cmd[1] = speed;
354 		rmh.cmd_len = 2;
355 		err = pcxhr_send_msg(mgr, &rmh);
356 		if (err)
357 			return err;
358 	}
359 	/* set the new frequency */
360 	dev_dbg(&mgr->pci->dev, "clock register : set %x\n", val);
361 	err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK,
362 					  val, changed);
363 	if (err)
364 		return err;
365 
366 	mgr->sample_rate_real = realfreq;
367 	mgr->cur_clock_type = mgr->use_clock_type;
368 
369 	/* unmute after codec speed modes */
370 	if (mgr->codec_speed != speed) {
371 		pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */
372 		rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
373 		if (DSP_EXT_CMD_SET(mgr)) {
374 			rmh.cmd[1]  = 1;
375 			rmh.cmd_len = 2;
376 		}
377 		err = pcxhr_send_msg(mgr, &rmh);
378 		if (err)
379 			return err;
380 		mgr->codec_speed = speed;	/* save new codec speed */
381 	}
382 
383 	dev_dbg(&mgr->pci->dev, "pcxhr_sub_set_clock to %dHz (realfreq=%d)\n",
384 		    rate, realfreq);
385 	return 0;
386 }
387 
388 #define PCXHR_MODIFY_CLOCK_S_BIT	0x04
389 
390 #define PCXHR_IRQ_TIMER_FREQ		92000
391 #define PCXHR_IRQ_TIMER_PERIOD		48
392 
393 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
394 {
395 	struct pcxhr_rmh rmh;
396 	int err, changed;
397 
398 	if (rate == 0)
399 		return 0; /* nothing to do */
400 
401 	if (mgr->is_hr_stereo)
402 		err = hr222_sub_set_clock(mgr, rate, &changed);
403 	else
404 		err = pcxhr_sub_set_clock(mgr, rate, &changed);
405 
406 	if (err)
407 		return err;
408 
409 	if (changed) {
410 		pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
411 		rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos  */
412 		if (rate < PCXHR_IRQ_TIMER_FREQ)
413 			rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
414 		else
415 			rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
416 		rmh.cmd[2] = rate;
417 		rmh.cmd_len = 3;
418 		err = pcxhr_send_msg(mgr, &rmh);
419 		if (err)
420 			return err;
421 	}
422 	return 0;
423 }
424 
425 
426 static int pcxhr_sub_get_external_clock(struct pcxhr_mgr *mgr,
427 					enum pcxhr_clock_type clock_type,
428 					int *sample_rate)
429 {
430 	struct pcxhr_rmh rmh;
431 	unsigned char reg;
432 	int err, rate;
433 
434 	switch (clock_type) {
435 	case PCXHR_CLOCK_TYPE_WORD_CLOCK:
436 		reg = REG_STATUS_WORD_CLOCK;
437 		break;
438 	case PCXHR_CLOCK_TYPE_AES_SYNC:
439 		reg = REG_STATUS_AES_SYNC;
440 		break;
441 	case PCXHR_CLOCK_TYPE_AES_1:
442 		reg = REG_STATUS_AES_1;
443 		break;
444 	case PCXHR_CLOCK_TYPE_AES_2:
445 		reg = REG_STATUS_AES_2;
446 		break;
447 	case PCXHR_CLOCK_TYPE_AES_3:
448 		reg = REG_STATUS_AES_3;
449 		break;
450 	case PCXHR_CLOCK_TYPE_AES_4:
451 		reg = REG_STATUS_AES_4;
452 		break;
453 	default:
454 		return -EINVAL;
455 	}
456 	pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
457 	rmh.cmd_len = 2;
458 	rmh.cmd[0] |= IO_NUM_REG_STATUS;
459 	if (mgr->last_reg_stat != reg) {
460 		rmh.cmd[1]  = reg;
461 		err = pcxhr_send_msg(mgr, &rmh);
462 		if (err)
463 			return err;
464 		udelay(100);	/* wait minimum 2 sample_frames at 32kHz ! */
465 		mgr->last_reg_stat = reg;
466 	}
467 	rmh.cmd[1]  = REG_STATUS_CURRENT;
468 	err = pcxhr_send_msg(mgr, &rmh);
469 	if (err)
470 		return err;
471 	switch (rmh.stat[1] & 0x0f) {
472 	case REG_STATUS_SYNC_32000 :	rate = 32000; break;
473 	case REG_STATUS_SYNC_44100 :	rate = 44100; break;
474 	case REG_STATUS_SYNC_48000 :	rate = 48000; break;
475 	case REG_STATUS_SYNC_64000 :	rate = 64000; break;
476 	case REG_STATUS_SYNC_88200 :	rate = 88200; break;
477 	case REG_STATUS_SYNC_96000 :	rate = 96000; break;
478 	case REG_STATUS_SYNC_128000 :	rate = 128000; break;
479 	case REG_STATUS_SYNC_176400 :	rate = 176400; break;
480 	case REG_STATUS_SYNC_192000 :	rate = 192000; break;
481 	default: rate = 0;
482 	}
483 	dev_dbg(&mgr->pci->dev, "External clock is at %d Hz\n", rate);
484 	*sample_rate = rate;
485 	return 0;
486 }
487 
488 
489 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr,
490 			     enum pcxhr_clock_type clock_type,
491 			     int *sample_rate)
492 {
493 	if (mgr->is_hr_stereo)
494 		return hr222_get_external_clock(mgr, clock_type,
495 						sample_rate);
496 	else
497 		return pcxhr_sub_get_external_clock(mgr, clock_type,
498 						    sample_rate);
499 }
500 
501 /*
502  *  start or stop playback/capture substream
503  */
504 static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
505 {
506 	int err;
507 	struct snd_pcxhr *chip;
508 	struct pcxhr_rmh rmh;
509 	int stream_mask, start;
510 
511 	if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
512 		start = 1;
513 	else {
514 		if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
515 			snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state "
516 				   "CANNOT be stopped\n");
517 			return -EINVAL;
518 		}
519 		start = 0;
520 	}
521 	if (!stream->substream)
522 		return -EINVAL;
523 
524 	stream->timer_abs_periods = 0;
525 	stream->timer_period_frag = 0;	/* reset theoretical stream pos */
526 	stream->timer_buf_periods = 0;
527 	stream->timer_is_synced = 0;
528 
529 	stream_mask =
530 	  stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
531 
532 	pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
533 	pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
534 				  stream->pipe->first_audio, 0, stream_mask);
535 
536 	chip = snd_pcm_substream_chip(stream->substream);
537 
538 	err = pcxhr_send_msg(chip->mgr, &rmh);
539 	if (err)
540 		dev_err(chip->card->dev,
541 			"ERROR pcxhr_set_stream_state err=%x;\n", err);
542 	stream->status =
543 	  start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
544 	return err;
545 }
546 
547 #define HEADER_FMT_BASE_LIN		0xfed00000
548 #define HEADER_FMT_BASE_FLOAT		0xfad00000
549 #define HEADER_FMT_INTEL		0x00008000
550 #define HEADER_FMT_24BITS		0x00004000
551 #define HEADER_FMT_16BITS		0x00002000
552 #define HEADER_FMT_UPTO11		0x00000200
553 #define HEADER_FMT_UPTO32		0x00000100
554 #define HEADER_FMT_MONO			0x00000080
555 
556 static int pcxhr_set_format(struct pcxhr_stream *stream)
557 {
558 	int err, is_capture, sample_rate, stream_num;
559 	struct snd_pcxhr *chip;
560 	struct pcxhr_rmh rmh;
561 	unsigned int header;
562 
563 	switch (stream->format) {
564 	case SNDRV_PCM_FORMAT_U8:
565 		header = HEADER_FMT_BASE_LIN;
566 		break;
567 	case SNDRV_PCM_FORMAT_S16_LE:
568 		header = HEADER_FMT_BASE_LIN |
569 			 HEADER_FMT_16BITS | HEADER_FMT_INTEL;
570 		break;
571 	case SNDRV_PCM_FORMAT_S16_BE:
572 		header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
573 		break;
574 	case SNDRV_PCM_FORMAT_S24_3LE:
575 		header = HEADER_FMT_BASE_LIN |
576 			 HEADER_FMT_24BITS | HEADER_FMT_INTEL;
577 		break;
578 	case SNDRV_PCM_FORMAT_S24_3BE:
579 		header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
580 		break;
581 	case SNDRV_PCM_FORMAT_FLOAT_LE:
582 		header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
583 		break;
584 	default:
585 		snd_printk(KERN_ERR
586 			   "error pcxhr_set_format() : unknown format\n");
587 		return -EINVAL;
588 	}
589 	chip = snd_pcm_substream_chip(stream->substream);
590 
591 	sample_rate = chip->mgr->sample_rate;
592 	if (sample_rate <= 32000 && sample_rate !=0) {
593 		if (sample_rate <= 11025)
594 			header |= HEADER_FMT_UPTO11;
595 		else
596 			header |= HEADER_FMT_UPTO32;
597 	}
598 	if (stream->channels == 1)
599 		header |= HEADER_FMT_MONO;
600 
601 	is_capture = stream->pipe->is_capture;
602 	stream_num = is_capture ? 0 : stream->substream->number;
603 
604 	pcxhr_init_rmh(&rmh, is_capture ?
605 		       CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
606 	pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
607 				  stream_num, 0);
608 	if (is_capture) {
609 		/* bug with old dsp versions: */
610 		/* bit 12 also sets the format of the playback stream */
611 		if (DSP_EXT_CMD_SET(chip->mgr))
612 			rmh.cmd[0] |= 1<<10;
613 		else
614 			rmh.cmd[0] |= 1<<12;
615 	}
616 	rmh.cmd[1] = 0;
617 	rmh.cmd_len = 2;
618 	if (DSP_EXT_CMD_SET(chip->mgr)) {
619 		/* add channels and set bit 19 if channels>2 */
620 		rmh.cmd[1] = stream->channels;
621 		if (!is_capture) {
622 			/* playback : add channel mask to command */
623 			rmh.cmd[2] = (stream->channels == 1) ? 0x01 : 0x03;
624 			rmh.cmd_len = 3;
625 		}
626 	}
627 	rmh.cmd[rmh.cmd_len++] = header >> 8;
628 	rmh.cmd[rmh.cmd_len++] = (header & 0xff) << 16;
629 	err = pcxhr_send_msg(chip->mgr, &rmh);
630 	if (err)
631 		dev_err(chip->card->dev,
632 			"ERROR pcxhr_set_format err=%x;\n", err);
633 	return err;
634 }
635 
636 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
637 {
638 	int err, is_capture, stream_num;
639 	struct pcxhr_rmh rmh;
640 	struct snd_pcm_substream *subs = stream->substream;
641 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
642 
643 	is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
644 	stream_num = is_capture ? 0 : subs->number;
645 
646 	snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : "
647 		    "addr(%p) bytes(%zx) subs(%d)\n",
648 		    is_capture ? 'c' : 'p',
649 		    chip->chip_idx, (void *)(long)subs->runtime->dma_addr,
650 		    subs->runtime->dma_bytes, subs->number);
651 
652 	pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
653 	pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio,
654 				  stream_num, 0);
655 
656 	/* max buffer size is 2 MByte */
657 	snd_BUG_ON(subs->runtime->dma_bytes >= 0x200000);
658 	/* size in bits */
659 	rmh.cmd[1] = subs->runtime->dma_bytes * 8;
660 	/* most significant byte */
661 	rmh.cmd[2] = subs->runtime->dma_addr >> 24;
662 	/* this is a circular buffer */
663 	rmh.cmd[2] |= 1<<19;
664 	/* least 3 significant bytes */
665 	rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;
666 	rmh.cmd_len = 4;
667 	err = pcxhr_send_msg(chip->mgr, &rmh);
668 	if (err)
669 		dev_err(chip->card->dev,
670 			   "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
671 	return err;
672 }
673 
674 
675 #if 0
676 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream,
677 				   snd_pcm_uframes_t *sample_count)
678 {
679 	struct pcxhr_rmh rmh;
680 	int err;
681 	pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
682 	pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
683 	pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
684 				  1<<stream->pipe->first_audio);
685 	err = pcxhr_send_msg(chip->mgr, &rmh);
686 	if (err == 0) {
687 		*sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
688 		*sample_count += (snd_pcm_uframes_t)rmh.stat[1];
689 	}
690 	snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
691 	return err;
692 }
693 #endif
694 
695 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
696 						  struct pcxhr_pipe **pipe)
697 {
698 	if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
699 		*pipe = stream->pipe;
700 		return 1;
701 	}
702 	return 0;
703 }
704 
705 static void pcxhr_start_linked_stream(struct pcxhr_mgr *mgr)
706 {
707 	int i, j, err;
708 	struct pcxhr_pipe *pipe;
709 	struct snd_pcxhr *chip;
710 	int capture_mask = 0;
711 	int playback_mask = 0;
712 
713 #ifdef CONFIG_SND_DEBUG_VERBOSE
714 	struct timeval my_tv1, my_tv2;
715 	do_gettimeofday(&my_tv1);
716 #endif
717 	mutex_lock(&mgr->setup_mutex);
718 
719 	/* check the pipes concerned and build pipe_array */
720 	for (i = 0; i < mgr->num_cards; i++) {
721 		chip = mgr->chip[i];
722 		for (j = 0; j < chip->nb_streams_capt; j++) {
723 			if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
724 				capture_mask |= (1 << pipe->first_audio);
725 		}
726 		for (j = 0; j < chip->nb_streams_play; j++) {
727 			if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
728 				playback_mask |= (1 << pipe->first_audio);
729 				break;	/* add only once, as all playback
730 					 * streams of one chip use the same pipe
731 					 */
732 			}
733 		}
734 	}
735 	if (capture_mask == 0 && playback_mask == 0) {
736 		mutex_unlock(&mgr->setup_mutex);
737 		dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : no pipes\n");
738 		return;
739 	}
740 
741 	dev_dbg(&mgr->pci->dev, "pcxhr_start_linked_stream : "
742 		    "playback_mask=%x capture_mask=%x\n",
743 		    playback_mask, capture_mask);
744 
745 	/* synchronous stop of all the pipes concerned */
746 	err = pcxhr_set_pipe_state(mgr,  playback_mask, capture_mask, 0);
747 	if (err) {
748 		mutex_unlock(&mgr->setup_mutex);
749 		dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : "
750 			   "error stop pipes (P%x C%x)\n",
751 			   playback_mask, capture_mask);
752 		return;
753 	}
754 
755 	/* the dsp lost format and buffer info with the stop pipe */
756 	for (i = 0; i < mgr->num_cards; i++) {
757 		struct pcxhr_stream *stream;
758 		chip = mgr->chip[i];
759 		for (j = 0; j < chip->nb_streams_capt; j++) {
760 			stream = &chip->capture_stream[j];
761 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
762 				err = pcxhr_set_format(stream);
763 				err = pcxhr_update_r_buffer(stream);
764 			}
765 		}
766 		for (j = 0; j < chip->nb_streams_play; j++) {
767 			stream = &chip->playback_stream[j];
768 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
769 				err = pcxhr_set_format(stream);
770 				err = pcxhr_update_r_buffer(stream);
771 			}
772 		}
773 	}
774 	/* start all the streams */
775 	for (i = 0; i < mgr->num_cards; i++) {
776 		struct pcxhr_stream *stream;
777 		chip = mgr->chip[i];
778 		for (j = 0; j < chip->nb_streams_capt; j++) {
779 			stream = &chip->capture_stream[j];
780 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
781 				err = pcxhr_set_stream_state(stream);
782 		}
783 		for (j = 0; j < chip->nb_streams_play; j++) {
784 			stream = &chip->playback_stream[j];
785 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
786 				err = pcxhr_set_stream_state(stream);
787 		}
788 	}
789 
790 	/* synchronous start of all the pipes concerned */
791 	err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
792 	if (err) {
793 		mutex_unlock(&mgr->setup_mutex);
794 		dev_err(&mgr->pci->dev, "pcxhr_start_linked_stream : "
795 			   "error start pipes (P%x C%x)\n",
796 			   playback_mask, capture_mask);
797 		return;
798 	}
799 
800 	/* put the streams into the running state now
801 	 * (increment pointer by interrupt)
802 	 */
803 	mutex_lock(&mgr->lock);
804 	for ( i =0; i < mgr->num_cards; i++) {
805 		struct pcxhr_stream *stream;
806 		chip = mgr->chip[i];
807 		for(j = 0; j < chip->nb_streams_capt; j++) {
808 			stream = &chip->capture_stream[j];
809 			if(stream->status == PCXHR_STREAM_STATUS_STARTED)
810 				stream->status = PCXHR_STREAM_STATUS_RUNNING;
811 		}
812 		for (j = 0; j < chip->nb_streams_play; j++) {
813 			stream = &chip->playback_stream[j];
814 			if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
815 				/* playback will already have advanced ! */
816 				stream->timer_period_frag += mgr->granularity;
817 				stream->status = PCXHR_STREAM_STATUS_RUNNING;
818 			}
819 		}
820 	}
821 	mutex_unlock(&mgr->lock);
822 
823 	mutex_unlock(&mgr->setup_mutex);
824 
825 #ifdef CONFIG_SND_DEBUG_VERBOSE
826 	do_gettimeofday(&my_tv2);
827 	dev_dbg(&mgr->pci->dev, "***TRIGGER START*** TIME = %ld (err = %x)\n",
828 		    (long)(my_tv2.tv_usec - my_tv1.tv_usec), err);
829 #endif
830 }
831 
832 
833 /*
834  *  trigger callback
835  */
836 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
837 {
838 	struct pcxhr_stream *stream;
839 	struct snd_pcm_substream *s;
840 
841 	switch (cmd) {
842 	case SNDRV_PCM_TRIGGER_START:
843 		snd_printdd("SNDRV_PCM_TRIGGER_START\n");
844 		if (snd_pcm_stream_linked(subs)) {
845 			struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
846 			snd_pcm_group_for_each_entry(s, subs) {
847 				if (snd_pcm_substream_chip(s) != chip)
848 					continue;
849 				stream = s->runtime->private_data;
850 				stream->status =
851 					PCXHR_STREAM_STATUS_SCHEDULE_RUN;
852 				snd_pcm_trigger_done(s, subs);
853 			}
854 			pcxhr_start_linked_stream(chip->mgr);
855 		} else {
856 			stream = subs->runtime->private_data;
857 			snd_printdd("Only one Substream %c %d\n",
858 				    stream->pipe->is_capture ? 'C' : 'P',
859 				    stream->pipe->first_audio);
860 			if (pcxhr_set_format(stream))
861 				return -EINVAL;
862 			if (pcxhr_update_r_buffer(stream))
863 				return -EINVAL;
864 
865 			stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
866 			if (pcxhr_set_stream_state(stream))
867 				return -EINVAL;
868 			stream->status = PCXHR_STREAM_STATUS_RUNNING;
869 		}
870 		break;
871 	case SNDRV_PCM_TRIGGER_STOP:
872 		snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
873 		snd_pcm_group_for_each_entry(s, subs) {
874 			stream = s->runtime->private_data;
875 			stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
876 			if (pcxhr_set_stream_state(stream))
877 				return -EINVAL;
878 			snd_pcm_trigger_done(s, subs);
879 		}
880 		break;
881 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
882 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
883 		/* TODO */
884 	default:
885 		return -EINVAL;
886 	}
887 	return 0;
888 }
889 
890 
891 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
892 {
893 	struct pcxhr_rmh rmh;
894 	int err;
895 
896 	pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
897 	if (start) {
898 		/* last dsp time invalid */
899 		mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
900 		rmh.cmd[0] |= mgr->granularity;
901 	}
902 	err = pcxhr_send_msg(mgr, &rmh);
903 	if (err < 0)
904 		dev_err(&mgr->pci->dev, "error pcxhr_hardware_timer err(%x)\n",
905 			   err);
906 	return err;
907 }
908 
909 /*
910  *  prepare callback for all pcms
911  */
912 static int pcxhr_prepare(struct snd_pcm_substream *subs)
913 {
914 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
915 	struct pcxhr_mgr *mgr = chip->mgr;
916 	int err = 0;
917 
918 	dev_dbg(chip->card->dev,
919 		"pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
920 		    subs->runtime->period_size, subs->runtime->periods,
921 		    subs->runtime->buffer_size);
922 
923 	mutex_lock(&mgr->setup_mutex);
924 
925 	do {
926 		/* only the first stream can choose the sample rate */
927 		/* set the clock only once (first stream) */
928 		if (mgr->sample_rate != subs->runtime->rate) {
929 			err = pcxhr_set_clock(mgr, subs->runtime->rate);
930 			if (err)
931 				break;
932 			if (mgr->sample_rate == 0)
933 				/* start the DSP-timer */
934 				err = pcxhr_hardware_timer(mgr, 1);
935 			mgr->sample_rate = subs->runtime->rate;
936 		}
937 	} while(0);	/* do only once (so we can use break instead of goto) */
938 
939 	mutex_unlock(&mgr->setup_mutex);
940 
941 	return err;
942 }
943 
944 
945 /*
946  *  HW_PARAMS callback for all pcms
947  */
948 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
949 			   struct snd_pcm_hw_params *hw)
950 {
951 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
952 	struct pcxhr_mgr *mgr = chip->mgr;
953 	struct pcxhr_stream *stream = subs->runtime->private_data;
954 	snd_pcm_format_t format;
955 	int err;
956 	int channels;
957 
958 	/* set up channels */
959 	channels = params_channels(hw);
960 
961 	/*  set up format for the stream */
962 	format = params_format(hw);
963 
964 	mutex_lock(&mgr->setup_mutex);
965 
966 	stream->channels = channels;
967 	stream->format = format;
968 
969 	/* allocate buffer */
970 	err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
971 
972 	mutex_unlock(&mgr->setup_mutex);
973 
974 	return err;
975 }
976 
977 static int pcxhr_hw_free(struct snd_pcm_substream *subs)
978 {
979 	snd_pcm_lib_free_pages(subs);
980 	return 0;
981 }
982 
983 
984 /*
985  *  CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
986  */
987 static struct snd_pcm_hardware pcxhr_caps =
988 {
989 	.info             = (SNDRV_PCM_INFO_MMAP |
990 			     SNDRV_PCM_INFO_INTERLEAVED |
991 			     SNDRV_PCM_INFO_MMAP_VALID |
992 			     SNDRV_PCM_INFO_SYNC_START),
993 	.formats	  = (SNDRV_PCM_FMTBIT_U8 |
994 			     SNDRV_PCM_FMTBIT_S16_LE |
995 			     SNDRV_PCM_FMTBIT_S16_BE |
996 			     SNDRV_PCM_FMTBIT_S24_3LE |
997 			     SNDRV_PCM_FMTBIT_S24_3BE |
998 			     SNDRV_PCM_FMTBIT_FLOAT_LE),
999 	.rates            = (SNDRV_PCM_RATE_CONTINUOUS |
1000 			     SNDRV_PCM_RATE_8000_192000),
1001 	.rate_min         = 8000,
1002 	.rate_max         = 192000,
1003 	.channels_min     = 1,
1004 	.channels_max     = 2,
1005 	.buffer_bytes_max = (32*1024),
1006 	/* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
1007 	.period_bytes_min = (2*PCXHR_GRANULARITY),
1008 	.period_bytes_max = (16*1024),
1009 	.periods_min      = 2,
1010 	.periods_max      = (32*1024/PCXHR_GRANULARITY),
1011 };
1012 
1013 
1014 static int pcxhr_open(struct snd_pcm_substream *subs)
1015 {
1016 	struct snd_pcxhr       *chip = snd_pcm_substream_chip(subs);
1017 	struct pcxhr_mgr       *mgr = chip->mgr;
1018 	struct snd_pcm_runtime *runtime = subs->runtime;
1019 	struct pcxhr_stream    *stream;
1020 	int err;
1021 
1022 	mutex_lock(&mgr->setup_mutex);
1023 
1024 	/* copy the struct snd_pcm_hardware struct */
1025 	runtime->hw = pcxhr_caps;
1026 
1027 	if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
1028 		dev_dbg(chip->card->dev, "pcxhr_open playback chip%d subs%d\n",
1029 			    chip->chip_idx, subs->number);
1030 		stream = &chip->playback_stream[subs->number];
1031 	} else {
1032 		dev_dbg(chip->card->dev, "pcxhr_open capture chip%d subs%d\n",
1033 			    chip->chip_idx, subs->number);
1034 		if (mgr->mono_capture)
1035 			runtime->hw.channels_max = 1;
1036 		else
1037 			runtime->hw.channels_min = 2;
1038 		stream = &chip->capture_stream[subs->number];
1039 	}
1040 	if (stream->status != PCXHR_STREAM_STATUS_FREE){
1041 		/* streams in use */
1042 		dev_err(chip->card->dev, "pcxhr_open chip%d subs%d in use\n",
1043 			   chip->chip_idx, subs->number);
1044 		mutex_unlock(&mgr->setup_mutex);
1045 		return -EBUSY;
1046 	}
1047 
1048 	/* float format support is in some cases buggy on stereo cards */
1049 	if (mgr->is_hr_stereo)
1050 		runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_FLOAT_LE;
1051 
1052 	/* buffer-size should better be multiple of period-size */
1053 	err = snd_pcm_hw_constraint_integer(runtime,
1054 					    SNDRV_PCM_HW_PARAM_PERIODS);
1055 	if (err < 0) {
1056 		mutex_unlock(&mgr->setup_mutex);
1057 		return err;
1058 	}
1059 
1060 	/* if a sample rate is already used or fixed by external clock,
1061 	 * the stream cannot change
1062 	 */
1063 	if (mgr->sample_rate)
1064 		runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
1065 	else {
1066 		if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
1067 			int external_rate;
1068 			if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
1069 						     &external_rate) ||
1070 			    external_rate == 0) {
1071 				/* cannot detect the external clock rate */
1072 				mutex_unlock(&mgr->setup_mutex);
1073 				return -EBUSY;
1074 			}
1075 			runtime->hw.rate_min = external_rate;
1076 			runtime->hw.rate_max = external_rate;
1077 		}
1078 	}
1079 
1080 	stream->status      = PCXHR_STREAM_STATUS_OPEN;
1081 	stream->substream   = subs;
1082 	stream->channels    = 0; /* not configured yet */
1083 
1084 	runtime->private_data = stream;
1085 
1086 	/* better get a divisor of granularity values (96 or 192) */
1087 	snd_pcm_hw_constraint_step(runtime, 0,
1088 				   SNDRV_PCM_HW_PARAM_BUFFER_SIZE, 32);
1089 	snd_pcm_hw_constraint_step(runtime, 0,
1090 				   SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 32);
1091 	snd_pcm_set_sync(subs);
1092 
1093 	mgr->ref_count_rate++;
1094 
1095 	mutex_unlock(&mgr->setup_mutex);
1096 	return 0;
1097 }
1098 
1099 
1100 static int pcxhr_close(struct snd_pcm_substream *subs)
1101 {
1102 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1103 	struct pcxhr_mgr *mgr = chip->mgr;
1104 	struct pcxhr_stream *stream = subs->runtime->private_data;
1105 
1106 	mutex_lock(&mgr->setup_mutex);
1107 
1108 	dev_dbg(chip->card->dev, "pcxhr_close chip%d subs%d\n",
1109 		    chip->chip_idx, subs->number);
1110 
1111 	/* sample rate released */
1112 	if (--mgr->ref_count_rate == 0) {
1113 		mgr->sample_rate = 0;	/* the sample rate is no more locked */
1114 		pcxhr_hardware_timer(mgr, 0);	/* stop the DSP-timer */
1115 	}
1116 
1117 	stream->status    = PCXHR_STREAM_STATUS_FREE;
1118 	stream->substream = NULL;
1119 
1120 	mutex_unlock(&mgr->setup_mutex);
1121 
1122 	return 0;
1123 }
1124 
1125 
1126 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
1127 {
1128 	u_int32_t timer_period_frag;
1129 	int timer_buf_periods;
1130 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
1131 	struct snd_pcm_runtime *runtime = subs->runtime;
1132 	struct pcxhr_stream *stream  = runtime->private_data;
1133 
1134 	mutex_lock(&chip->mgr->lock);
1135 
1136 	/* get the period fragment and the nb of periods in the buffer */
1137 	timer_period_frag = stream->timer_period_frag;
1138 	timer_buf_periods = stream->timer_buf_periods;
1139 
1140 	mutex_unlock(&chip->mgr->lock);
1141 
1142 	return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
1143 				   timer_period_frag);
1144 }
1145 
1146 
1147 static struct snd_pcm_ops pcxhr_ops = {
1148 	.open      = pcxhr_open,
1149 	.close     = pcxhr_close,
1150 	.ioctl     = snd_pcm_lib_ioctl,
1151 	.prepare   = pcxhr_prepare,
1152 	.hw_params = pcxhr_hw_params,
1153 	.hw_free   = pcxhr_hw_free,
1154 	.trigger   = pcxhr_trigger,
1155 	.pointer   = pcxhr_stream_pointer,
1156 };
1157 
1158 /*
1159  */
1160 int pcxhr_create_pcm(struct snd_pcxhr *chip)
1161 {
1162 	int err;
1163 	struct snd_pcm *pcm;
1164 	char name[32];
1165 
1166 	sprintf(name, "pcxhr %d", chip->chip_idx);
1167 	if ((err = snd_pcm_new(chip->card, name, 0,
1168 			       chip->nb_streams_play,
1169 			       chip->nb_streams_capt, &pcm)) < 0) {
1170 		dev_err(chip->card->dev, "cannot create pcm %s\n", name);
1171 		return err;
1172 	}
1173 	pcm->private_data = chip;
1174 
1175 	if (chip->nb_streams_play)
1176 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
1177 	if (chip->nb_streams_capt)
1178 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
1179 
1180 	pcm->info_flags = 0;
1181 	pcm->nonatomic = true;
1182 	strcpy(pcm->name, name);
1183 
1184 	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1185 					      snd_dma_pci_data(chip->mgr->pci),
1186 					      32*1024, 32*1024);
1187 	chip->pcm = pcm;
1188 	return 0;
1189 }
1190 
1191 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1192 {
1193 	kfree(chip);
1194 	return 0;
1195 }
1196 
1197 static int pcxhr_chip_dev_free(struct snd_device *device)
1198 {
1199 	struct snd_pcxhr *chip = device->device_data;
1200 	return pcxhr_chip_free(chip);
1201 }
1202 
1203 
1204 /*
1205  */
1206 static int pcxhr_create(struct pcxhr_mgr *mgr,
1207 			struct snd_card *card, int idx)
1208 {
1209 	int err;
1210 	struct snd_pcxhr *chip;
1211 	static struct snd_device_ops ops = {
1212 		.dev_free = pcxhr_chip_dev_free,
1213 	};
1214 
1215 	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1216 	if (! chip) {
1217 		dev_err(card->dev, "cannot allocate chip\n");
1218 		return -ENOMEM;
1219 	}
1220 
1221 	chip->card = card;
1222 	chip->chip_idx = idx;
1223 	chip->mgr = mgr;
1224 
1225 	if (idx < mgr->playback_chips)
1226 		/* stereo or mono streams */
1227 		chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1228 
1229 	if (idx < mgr->capture_chips) {
1230 		if (mgr->mono_capture)
1231 			chip->nb_streams_capt = 2;	/* 2 mono streams */
1232 		else
1233 			chip->nb_streams_capt = 1;	/* or 1 stereo stream */
1234 	}
1235 
1236 	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1237 		pcxhr_chip_free(chip);
1238 		return err;
1239 	}
1240 
1241 	mgr->chip[idx] = chip;
1242 
1243 	return 0;
1244 }
1245 
1246 /* proc interface */
1247 static void pcxhr_proc_info(struct snd_info_entry *entry,
1248 			    struct snd_info_buffer *buffer)
1249 {
1250 	struct snd_pcxhr *chip = entry->private_data;
1251 	struct pcxhr_mgr *mgr = chip->mgr;
1252 
1253 	snd_iprintf(buffer, "\n%s\n", mgr->longname);
1254 
1255 	/* stats available when embedded DSP is running */
1256 	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1257 		struct pcxhr_rmh rmh;
1258 		short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1259 		short ver_min = (mgr->dsp_version >> 8) & 0xff;
1260 		short ver_build = mgr->dsp_version & 0xff;
1261 		snd_iprintf(buffer, "module version %s\n",
1262 			    PCXHR_DRIVER_VERSION_STRING);
1263 		snd_iprintf(buffer, "dsp version %d.%d.%d\n",
1264 			    ver_maj, ver_min, ver_build);
1265 		if (mgr->board_has_analog)
1266 			snd_iprintf(buffer, "analog io available\n");
1267 		else
1268 			snd_iprintf(buffer, "digital only board\n");
1269 
1270 		/* calc cpu load of the dsp */
1271 		pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1272 		if( ! pcxhr_send_msg(mgr, &rmh) ) {
1273 			int cur = rmh.stat[0];
1274 			int ref = rmh.stat[1];
1275 			if (ref > 0) {
1276 				if (mgr->sample_rate_real != 0 &&
1277 				    mgr->sample_rate_real != 48000) {
1278 					ref = (ref * 48000) /
1279 					  mgr->sample_rate_real;
1280 					if (mgr->sample_rate_real >=
1281 					    PCXHR_IRQ_TIMER_FREQ)
1282 						ref *= 2;
1283 				}
1284 				cur = 100 - (100 * cur) / ref;
1285 				snd_iprintf(buffer, "cpu load    %d%%\n", cur);
1286 				snd_iprintf(buffer, "buffer pool %d/%d\n",
1287 					    rmh.stat[2], rmh.stat[3]);
1288 			}
1289 		}
1290 		snd_iprintf(buffer, "dma granularity : %d\n",
1291 			    mgr->granularity);
1292 		snd_iprintf(buffer, "dsp time errors : %d\n",
1293 			    mgr->dsp_time_err);
1294 		snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1295 			    mgr->async_err_pipe_xrun);
1296 		snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1297 			    mgr->async_err_stream_xrun);
1298 		snd_iprintf(buffer, "dsp async last other error : %x\n",
1299 			    mgr->async_err_other_last);
1300 		/* debug zone dsp */
1301 		rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1302 		rmh.cmd_len = 1;
1303 		rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1304 		rmh.dsp_stat = 0;
1305 		rmh.cmd_idx = CMD_LAST_INDEX;
1306 		if( ! pcxhr_send_msg(mgr, &rmh) ) {
1307 			int i;
1308 			if (rmh.stat_len > 8)
1309 				rmh.stat_len = 8;
1310 			for (i = 0; i < rmh.stat_len; i++)
1311 				snd_iprintf(buffer, "debug[%02d] = %06x\n",
1312 					    i,  rmh.stat[i]);
1313 		}
1314 	} else
1315 		snd_iprintf(buffer, "no firmware loaded\n");
1316 	snd_iprintf(buffer, "\n");
1317 }
1318 static void pcxhr_proc_sync(struct snd_info_entry *entry,
1319 			    struct snd_info_buffer *buffer)
1320 {
1321 	struct snd_pcxhr *chip = entry->private_data;
1322 	struct pcxhr_mgr *mgr = chip->mgr;
1323 	static const char *textsHR22[3] = {
1324 		"Internal", "AES Sync", "AES 1"
1325 	};
1326 	static const char *textsPCXHR[7] = {
1327 		"Internal", "Word", "AES Sync",
1328 		"AES 1", "AES 2", "AES 3", "AES 4"
1329 	};
1330 	const char **texts;
1331 	int max_clock;
1332 	if (mgr->is_hr_stereo) {
1333 		texts = textsHR22;
1334 		max_clock = HR22_CLOCK_TYPE_MAX;
1335 	} else {
1336 		texts = textsPCXHR;
1337 		max_clock = PCXHR_CLOCK_TYPE_MAX;
1338 	}
1339 
1340 	snd_iprintf(buffer, "\n%s\n", mgr->longname);
1341 	snd_iprintf(buffer, "Current Sample Clock\t: %s\n",
1342 		    texts[mgr->cur_clock_type]);
1343 	snd_iprintf(buffer, "Current Sample Rate\t= %d\n",
1344 		    mgr->sample_rate_real);
1345 	/* commands available when embedded DSP is running */
1346 	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1347 		int i, err, sample_rate;
1348 		for (i = 1; i <= max_clock; i++) {
1349 			err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1350 			if (err)
1351 				break;
1352 			snd_iprintf(buffer, "%s Clock\t\t= %d\n",
1353 				    texts[i], sample_rate);
1354 		}
1355 	} else
1356 		snd_iprintf(buffer, "no firmware loaded\n");
1357 	snd_iprintf(buffer, "\n");
1358 }
1359 
1360 static void pcxhr_proc_gpio_read(struct snd_info_entry *entry,
1361 				 struct snd_info_buffer *buffer)
1362 {
1363 	struct snd_pcxhr *chip = entry->private_data;
1364 	struct pcxhr_mgr *mgr = chip->mgr;
1365 	/* commands available when embedded DSP is running */
1366 	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1367 		/* gpio ports on stereo boards only available */
1368 		int value = 0;
1369 		hr222_read_gpio(mgr, 1, &value);	/* GPI */
1370 		snd_iprintf(buffer, "GPI: 0x%x\n", value);
1371 		hr222_read_gpio(mgr, 0, &value);	/* GP0 */
1372 		snd_iprintf(buffer, "GPO: 0x%x\n", value);
1373 	} else
1374 		snd_iprintf(buffer, "no firmware loaded\n");
1375 	snd_iprintf(buffer, "\n");
1376 }
1377 static void pcxhr_proc_gpo_write(struct snd_info_entry *entry,
1378 				 struct snd_info_buffer *buffer)
1379 {
1380 	struct snd_pcxhr *chip = entry->private_data;
1381 	struct pcxhr_mgr *mgr = chip->mgr;
1382 	char line[64];
1383 	int value;
1384 	/* commands available when embedded DSP is running */
1385 	if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)))
1386 		return;
1387 	while (!snd_info_get_line(buffer, line, sizeof(line))) {
1388 		if (sscanf(line, "GPO: 0x%x", &value) != 1)
1389 			continue;
1390 		hr222_write_gpo(mgr, value);	/* GP0 */
1391 	}
1392 }
1393 
1394 /* Access to the results of the CMD_GET_TIME_CODE RMH */
1395 #define TIME_CODE_VALID_MASK	0x00800000
1396 #define TIME_CODE_NEW_MASK	0x00400000
1397 #define TIME_CODE_BACK_MASK	0x00200000
1398 #define TIME_CODE_WAIT_MASK	0x00100000
1399 
1400 /* Values for the CMD_MANAGE_SIGNAL RMH */
1401 #define MANAGE_SIGNAL_TIME_CODE	0x01
1402 #define MANAGE_SIGNAL_MIDI	0x02
1403 
1404 /* linear time code read proc*/
1405 static void pcxhr_proc_ltc(struct snd_info_entry *entry,
1406 			   struct snd_info_buffer *buffer)
1407 {
1408 	struct snd_pcxhr *chip = entry->private_data;
1409 	struct pcxhr_mgr *mgr = chip->mgr;
1410 	struct pcxhr_rmh rmh;
1411 	unsigned int ltcHrs, ltcMin, ltcSec, ltcFrm;
1412 	int err;
1413 	/* commands available when embedded DSP is running */
1414 	if (!(mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX))) {
1415 		snd_iprintf(buffer, "no firmware loaded\n");
1416 		return;
1417 	}
1418 	if (!mgr->capture_ltc) {
1419 		pcxhr_init_rmh(&rmh, CMD_MANAGE_SIGNAL);
1420 		rmh.cmd[0] |= MANAGE_SIGNAL_TIME_CODE;
1421 		err = pcxhr_send_msg(mgr, &rmh);
1422 		if (err) {
1423 			snd_iprintf(buffer, "ltc not activated (%d)\n", err);
1424 			return;
1425 		}
1426 		if (mgr->is_hr_stereo)
1427 			hr222_manage_timecode(mgr, 1);
1428 		else
1429 			pcxhr_write_io_num_reg_cont(mgr, REG_CONT_VALSMPTE,
1430 						    REG_CONT_VALSMPTE, NULL);
1431 		mgr->capture_ltc = 1;
1432 	}
1433 	pcxhr_init_rmh(&rmh, CMD_GET_TIME_CODE);
1434 	err = pcxhr_send_msg(mgr, &rmh);
1435 	if (err) {
1436 		snd_iprintf(buffer, "ltc read error (err=%d)\n", err);
1437 		return ;
1438 	}
1439 	ltcHrs = 10*((rmh.stat[0] >> 8) & 0x3) + (rmh.stat[0] & 0xf);
1440 	ltcMin = 10*((rmh.stat[1] >> 16) & 0x7) + ((rmh.stat[1] >> 8) & 0xf);
1441 	ltcSec = 10*(rmh.stat[1] & 0x7) + ((rmh.stat[2] >> 16) & 0xf);
1442 	ltcFrm = 10*((rmh.stat[2] >> 8) & 0x3) + (rmh.stat[2] & 0xf);
1443 
1444 	snd_iprintf(buffer, "timecode: %02u:%02u:%02u-%02u\n",
1445 			    ltcHrs, ltcMin, ltcSec, ltcFrm);
1446 	snd_iprintf(buffer, "raw: 0x%04x%06x%06x\n", rmh.stat[0] & 0x00ffff,
1447 			    rmh.stat[1] & 0xffffff, rmh.stat[2] & 0xffffff);
1448 	/*snd_iprintf(buffer, "dsp ref time: 0x%06x%06x\n",
1449 			    rmh.stat[3] & 0xffffff, rmh.stat[4] & 0xffffff);*/
1450 	if (!(rmh.stat[0] & TIME_CODE_VALID_MASK)) {
1451 		snd_iprintf(buffer, "warning: linear timecode not valid\n");
1452 	}
1453 }
1454 
1455 static void pcxhr_proc_init(struct snd_pcxhr *chip)
1456 {
1457 	struct snd_info_entry *entry;
1458 
1459 	if (! snd_card_proc_new(chip->card, "info", &entry))
1460 		snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
1461 	if (! snd_card_proc_new(chip->card, "sync", &entry))
1462 		snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
1463 	/* gpio available on stereo sound cards only */
1464 	if (chip->mgr->is_hr_stereo &&
1465 	    !snd_card_proc_new(chip->card, "gpio", &entry)) {
1466 		snd_info_set_text_ops(entry, chip, pcxhr_proc_gpio_read);
1467 		entry->c.text.write = pcxhr_proc_gpo_write;
1468 		entry->mode |= S_IWUSR;
1469 	}
1470 	if (!snd_card_proc_new(chip->card, "ltc", &entry))
1471 		snd_info_set_text_ops(entry, chip, pcxhr_proc_ltc);
1472 }
1473 /* end of proc interface */
1474 
1475 /*
1476  * release all the cards assigned to a manager instance
1477  */
1478 static int pcxhr_free(struct pcxhr_mgr *mgr)
1479 {
1480 	unsigned int i;
1481 
1482 	for (i = 0; i < mgr->num_cards; i++) {
1483 		if (mgr->chip[i])
1484 			snd_card_free(mgr->chip[i]->card);
1485 	}
1486 
1487 	/* reset board if some firmware was loaded */
1488 	if(mgr->dsp_loaded) {
1489 		pcxhr_reset_board(mgr);
1490 		dev_dbg(&mgr->pci->dev, "reset pcxhr !\n");
1491 	}
1492 
1493 	/* release irq  */
1494 	if (mgr->irq >= 0)
1495 		free_irq(mgr->irq, mgr);
1496 
1497 	pci_release_regions(mgr->pci);
1498 
1499 	/* free hostport purgebuffer */
1500 	if (mgr->hostport.area) {
1501 		snd_dma_free_pages(&mgr->hostport);
1502 		mgr->hostport.area = NULL;
1503 	}
1504 
1505 	kfree(mgr->prmh);
1506 
1507 	pci_disable_device(mgr->pci);
1508 	kfree(mgr);
1509 	return 0;
1510 }
1511 
1512 /*
1513  *    probe function - creates the card manager
1514  */
1515 static int pcxhr_probe(struct pci_dev *pci,
1516 		       const struct pci_device_id *pci_id)
1517 {
1518 	static int dev;
1519 	struct pcxhr_mgr *mgr;
1520 	unsigned int i;
1521 	int err;
1522 	size_t size;
1523 	char *card_name;
1524 
1525 	if (dev >= SNDRV_CARDS)
1526 		return -ENODEV;
1527 	if (! enable[dev]) {
1528 		dev++;
1529 		return -ENOENT;
1530 	}
1531 
1532 	/* enable PCI device */
1533 	if ((err = pci_enable_device(pci)) < 0)
1534 		return err;
1535 	pci_set_master(pci);
1536 
1537 	/* check if we can restrict PCI DMA transfers to 32 bits */
1538 	if (pci_set_dma_mask(pci, DMA_BIT_MASK(32)) < 0) {
1539 		dev_err(&pci->dev,
1540 			"architecture does not support 32bit PCI busmaster DMA\n");
1541 		pci_disable_device(pci);
1542 		return -ENXIO;
1543 	}
1544 
1545 	/* alloc card manager */
1546 	mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1547 	if (! mgr) {
1548 		pci_disable_device(pci);
1549 		return -ENOMEM;
1550 	}
1551 
1552 	if (snd_BUG_ON(pci_id->driver_data >= PCI_ID_LAST)) {
1553 		kfree(mgr);
1554 		pci_disable_device(pci);
1555 		return -ENODEV;
1556 	}
1557 	card_name =
1558 		pcxhr_board_params[pci_id->driver_data].board_name;
1559 	mgr->playback_chips =
1560 		pcxhr_board_params[pci_id->driver_data].playback_chips;
1561 	mgr->capture_chips  =
1562 		pcxhr_board_params[pci_id->driver_data].capture_chips;
1563 	mgr->fw_file_set =
1564 		pcxhr_board_params[pci_id->driver_data].fw_file_set;
1565 	mgr->firmware_num  =
1566 		pcxhr_board_params[pci_id->driver_data].firmware_num;
1567 	mgr->mono_capture = mono[dev];
1568 	mgr->is_hr_stereo = (mgr->playback_chips == 1);
1569 	mgr->board_has_aes1 = PCXHR_BOARD_HAS_AES1(mgr);
1570 	mgr->board_aes_in_192k = !PCXHR_BOARD_AESIN_NO_192K(mgr);
1571 
1572 	if (mgr->is_hr_stereo)
1573 		mgr->granularity = PCXHR_GRANULARITY_HR22;
1574 	else
1575 		mgr->granularity = PCXHR_GRANULARITY;
1576 
1577 	/* resource assignment */
1578 	if ((err = pci_request_regions(pci, card_name)) < 0) {
1579 		kfree(mgr);
1580 		pci_disable_device(pci);
1581 		return err;
1582 	}
1583 	for (i = 0; i < 3; i++)
1584 		mgr->port[i] = pci_resource_start(pci, i);
1585 
1586 	mgr->pci = pci;
1587 	mgr->irq = -1;
1588 
1589 	if (request_threaded_irq(pci->irq, pcxhr_interrupt,
1590 				 pcxhr_threaded_irq, IRQF_SHARED,
1591 				 KBUILD_MODNAME, mgr)) {
1592 		dev_err(&pci->dev, "unable to grab IRQ %d\n", pci->irq);
1593 		pcxhr_free(mgr);
1594 		return -EBUSY;
1595 	}
1596 	mgr->irq = pci->irq;
1597 
1598 	sprintf(mgr->shortname, "Digigram %s", card_name);
1599 	sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i",
1600 		mgr->shortname,
1601 		mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1602 
1603 	/* ISR lock  */
1604 	mutex_init(&mgr->lock);
1605 	mutex_init(&mgr->msg_lock);
1606 
1607 	/* init setup mutex*/
1608 	mutex_init(&mgr->setup_mutex);
1609 
1610 	mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1611 			    sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS -
1612 					   PCXHR_SIZE_MAX_STATUS),
1613 			    GFP_KERNEL);
1614 	if (! mgr->prmh) {
1615 		pcxhr_free(mgr);
1616 		return -ENOMEM;
1617 	}
1618 
1619 	for (i=0; i < PCXHR_MAX_CARDS; i++) {
1620 		struct snd_card *card;
1621 		char tmpid[16];
1622 		int idx;
1623 
1624 		if (i >= max(mgr->playback_chips, mgr->capture_chips))
1625 			break;
1626 		mgr->num_cards++;
1627 
1628 		if (index[dev] < 0)
1629 			idx = index[dev];
1630 		else
1631 			idx = index[dev] + i;
1632 
1633 		snprintf(tmpid, sizeof(tmpid), "%s-%d",
1634 			 id[dev] ? id[dev] : card_name, i);
1635 		err = snd_card_new(&pci->dev, idx, tmpid, THIS_MODULE,
1636 				   0, &card);
1637 
1638 		if (err < 0) {
1639 			dev_err(card->dev, "cannot allocate the card %d\n", i);
1640 			pcxhr_free(mgr);
1641 			return err;
1642 		}
1643 
1644 		strcpy(card->driver, DRIVER_NAME);
1645 		sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
1646 		sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
1647 
1648 		if ((err = pcxhr_create(mgr, card, i)) < 0) {
1649 			snd_card_free(card);
1650 			pcxhr_free(mgr);
1651 			return err;
1652 		}
1653 
1654 		if (i == 0)
1655 			/* init proc interface only for chip0 */
1656 			pcxhr_proc_init(mgr->chip[i]);
1657 
1658 		if ((err = snd_card_register(card)) < 0) {
1659 			pcxhr_free(mgr);
1660 			return err;
1661 		}
1662 	}
1663 
1664 	/* create hostport purgebuffer */
1665 	size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1666 	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1667 				size, &mgr->hostport) < 0) {
1668 		pcxhr_free(mgr);
1669 		return -ENOMEM;
1670 	}
1671 	/* init purgebuffer */
1672 	memset(mgr->hostport.area, 0, size);
1673 
1674 	/* create a DSP loader */
1675 	err = pcxhr_setup_firmware(mgr);
1676 	if (err < 0) {
1677 		pcxhr_free(mgr);
1678 		return err;
1679 	}
1680 
1681 	pci_set_drvdata(pci, mgr);
1682 	dev++;
1683 	return 0;
1684 }
1685 
1686 static void pcxhr_remove(struct pci_dev *pci)
1687 {
1688 	pcxhr_free(pci_get_drvdata(pci));
1689 }
1690 
1691 static struct pci_driver pcxhr_driver = {
1692 	.name = KBUILD_MODNAME,
1693 	.id_table = pcxhr_ids,
1694 	.probe = pcxhr_probe,
1695 	.remove = pcxhr_remove,
1696 };
1697 
1698 module_pci_driver(pcxhr_driver);
1699