1 /* 2 * Driver for Digigram pcxhr compatible soundcards 3 * 4 * main file with alsa callbacks 5 * 6 * Copyright (c) 2004 by Digigram <alsa@digigram.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 21 */ 22 23 24 #include <sound/driver.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/slab.h> 28 #include <linux/pci.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/delay.h> 31 #include <linux/moduleparam.h> 32 #include <linux/mutex.h> 33 34 #include <sound/core.h> 35 #include <sound/initval.h> 36 #include <sound/info.h> 37 #include <sound/control.h> 38 #include <sound/pcm.h> 39 #include <sound/pcm_params.h> 40 #include "pcxhr.h" 41 #include "pcxhr_mixer.h" 42 #include "pcxhr_hwdep.h" 43 #include "pcxhr_core.h" 44 45 #define DRIVER_NAME "pcxhr" 46 47 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>"); 48 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING); 49 MODULE_LICENSE("GPL"); 50 MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}"); 51 52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */ 53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */ 54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */ 55 static int mono[SNDRV_CARDS]; /* capture in mono only */ 56 57 module_param_array(index, int, NULL, 0444); 58 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard"); 59 module_param_array(id, charp, NULL, 0444); 60 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard"); 61 module_param_array(enable, bool, NULL, 0444); 62 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard"); 63 module_param_array(mono, bool, NULL, 0444); 64 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)"); 65 66 enum { 67 PCI_ID_VX882HR, 68 PCI_ID_PCX882HR, 69 PCI_ID_VX881HR, 70 PCI_ID_PCX881HR, 71 PCI_ID_PCX1222HR, 72 PCI_ID_PCX1221HR, 73 PCI_ID_LAST 74 }; 75 76 static struct pci_device_id pcxhr_ids[] = { 77 { 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, }, /* VX882HR */ 78 { 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, }, /* PCX882HR */ 79 { 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, }, /* VX881HR */ 80 { 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, }, /* PCX881HR */ 81 { 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */ 82 { 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */ 83 { 0, } 84 }; 85 86 MODULE_DEVICE_TABLE(pci, pcxhr_ids); 87 88 struct board_parameters { 89 char* board_name; 90 short playback_chips; 91 short capture_chips; 92 short firmware_num; 93 }; 94 static struct board_parameters pcxhr_board_params[] = { 95 [PCI_ID_VX882HR] = { "VX882HR", 4, 4, 41, }, 96 [PCI_ID_PCX882HR] = { "PCX882HR", 4, 4, 41, }, 97 [PCI_ID_VX881HR] = { "VX881HR", 4, 4, 41, }, 98 [PCI_ID_PCX881HR] = { "PCX881HR", 4, 4, 41, }, 99 [PCI_ID_PCX1222HR] = { "PCX1222HR", 6, 1, 42, }, 100 [PCI_ID_PCX1221HR] = { "PCX1221HR", 6, 1, 42, }, 101 }; 102 103 104 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg, 105 unsigned int* realfreq) 106 { 107 unsigned int reg; 108 109 if (freq < 6900 || freq > 110250) 110 return -EINVAL; 111 reg = (28224000 * 10) / freq; 112 reg = (reg + 5) / 10; 113 if (reg < 0x200) 114 *pllreg = reg + 0x800; 115 else if (reg < 0x400) 116 *pllreg = reg & 0x1ff; 117 else if (reg < 0x800) { 118 *pllreg = ((reg >> 1) & 0x1ff) + 0x200; 119 reg &= ~1; 120 } else { 121 *pllreg = ((reg >> 2) & 0x1ff) + 0x400; 122 reg &= ~3; 123 } 124 if (realfreq) 125 *realfreq = ((28224000 * 10) / reg + 5) / 10; 126 return 0; 127 } 128 129 130 #define PCXHR_FREQ_REG_MASK 0x1f 131 #define PCXHR_FREQ_QUARTZ_48000 0x00 132 #define PCXHR_FREQ_QUARTZ_24000 0x01 133 #define PCXHR_FREQ_QUARTZ_12000 0x09 134 #define PCXHR_FREQ_QUARTZ_32000 0x08 135 #define PCXHR_FREQ_QUARTZ_16000 0x04 136 #define PCXHR_FREQ_QUARTZ_8000 0x0c 137 #define PCXHR_FREQ_QUARTZ_44100 0x02 138 #define PCXHR_FREQ_QUARTZ_22050 0x0a 139 #define PCXHR_FREQ_QUARTZ_11025 0x06 140 #define PCXHR_FREQ_PLL 0x05 141 #define PCXHR_FREQ_QUARTZ_192000 0x10 142 #define PCXHR_FREQ_QUARTZ_96000 0x18 143 #define PCXHR_FREQ_QUARTZ_176400 0x14 144 #define PCXHR_FREQ_QUARTZ_88200 0x1c 145 #define PCXHR_FREQ_QUARTZ_128000 0x12 146 #define PCXHR_FREQ_QUARTZ_64000 0x1a 147 148 #define PCXHR_FREQ_WORD_CLOCK 0x0f 149 #define PCXHR_FREQ_SYNC_AES 0x0e 150 #define PCXHR_FREQ_AES_1 0x07 151 #define PCXHR_FREQ_AES_2 0x0b 152 #define PCXHR_FREQ_AES_3 0x03 153 #define PCXHR_FREQ_AES_4 0x0d 154 155 #define PCXHR_MODIFY_CLOCK_S_BIT 0x04 156 157 #define PCXHR_IRQ_TIMER_FREQ 92000 158 #define PCXHR_IRQ_TIMER_PERIOD 48 159 160 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate, 161 unsigned int *reg, unsigned int *freq) 162 { 163 unsigned int val, realfreq, pllreg; 164 struct pcxhr_rmh rmh; 165 int err; 166 167 realfreq = rate; 168 switch (mgr->use_clock_type) { 169 case PCXHR_CLOCK_TYPE_INTERNAL : /* clock by quartz or pll */ 170 switch (rate) { 171 case 48000 : val = PCXHR_FREQ_QUARTZ_48000; break; 172 case 24000 : val = PCXHR_FREQ_QUARTZ_24000; break; 173 case 12000 : val = PCXHR_FREQ_QUARTZ_12000; break; 174 case 32000 : val = PCXHR_FREQ_QUARTZ_32000; break; 175 case 16000 : val = PCXHR_FREQ_QUARTZ_16000; break; 176 case 8000 : val = PCXHR_FREQ_QUARTZ_8000; break; 177 case 44100 : val = PCXHR_FREQ_QUARTZ_44100; break; 178 case 22050 : val = PCXHR_FREQ_QUARTZ_22050; break; 179 case 11025 : val = PCXHR_FREQ_QUARTZ_11025; break; 180 case 192000 : val = PCXHR_FREQ_QUARTZ_192000; break; 181 case 96000 : val = PCXHR_FREQ_QUARTZ_96000; break; 182 case 176400 : val = PCXHR_FREQ_QUARTZ_176400; break; 183 case 88200 : val = PCXHR_FREQ_QUARTZ_88200; break; 184 case 128000 : val = PCXHR_FREQ_QUARTZ_128000; break; 185 case 64000 : val = PCXHR_FREQ_QUARTZ_64000; break; 186 default : 187 val = PCXHR_FREQ_PLL; 188 /* get the value for the pll register */ 189 err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq); 190 if (err) 191 return err; 192 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); 193 rmh.cmd[0] |= IO_NUM_REG_GENCLK; 194 rmh.cmd[1] = pllreg & MASK_DSP_WORD; 195 rmh.cmd[2] = pllreg >> 24; 196 rmh.cmd_len = 3; 197 err = pcxhr_send_msg(mgr, &rmh); 198 if (err < 0) { 199 snd_printk(KERN_ERR 200 "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n", 201 err ); 202 return err; 203 } 204 } 205 break; 206 case PCXHR_CLOCK_TYPE_WORD_CLOCK : val = PCXHR_FREQ_WORD_CLOCK; break; 207 case PCXHR_CLOCK_TYPE_AES_SYNC : val = PCXHR_FREQ_SYNC_AES; break; 208 case PCXHR_CLOCK_TYPE_AES_1 : val = PCXHR_FREQ_AES_1; break; 209 case PCXHR_CLOCK_TYPE_AES_2 : val = PCXHR_FREQ_AES_2; break; 210 case PCXHR_CLOCK_TYPE_AES_3 : val = PCXHR_FREQ_AES_3; break; 211 case PCXHR_CLOCK_TYPE_AES_4 : val = PCXHR_FREQ_AES_4; break; 212 default : return -EINVAL; 213 } 214 *reg = val; 215 *freq = realfreq; 216 return 0; 217 } 218 219 220 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate) 221 { 222 unsigned int val, realfreq, speed; 223 struct pcxhr_rmh rmh; 224 int err, changed; 225 226 if (rate == 0) 227 return 0; /* nothing to do */ 228 229 err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq); 230 if (err) 231 return err; 232 233 /* codec speed modes */ 234 if (rate < 55000) 235 speed = 0; /* single speed */ 236 else if (rate < 100000) 237 speed = 1; /* dual speed */ 238 else 239 speed = 2; /* quad speed */ 240 if (mgr->codec_speed != speed) { 241 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* mute outputs */ 242 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 243 err = pcxhr_send_msg(mgr, &rmh); 244 if (err) 245 return err; 246 247 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE); /* set speed ratio */ 248 rmh.cmd[0] |= IO_NUM_SPEED_RATIO; 249 rmh.cmd[1] = speed; 250 rmh.cmd_len = 2; 251 err = pcxhr_send_msg(mgr, &rmh); 252 if (err) 253 return err; 254 } 255 /* set the new frequency */ 256 snd_printdd("clock register : set %x\n", val); 257 err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed); 258 if (err) 259 return err; 260 mgr->sample_rate_real = realfreq; 261 mgr->cur_clock_type = mgr->use_clock_type; 262 263 /* unmute after codec speed modes */ 264 if (mgr->codec_speed != speed) { 265 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); /* unmute outputs */ 266 rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT; 267 err = pcxhr_send_msg(mgr, &rmh); 268 if (err) 269 return err; 270 mgr->codec_speed = speed; /* save new codec speed */ 271 } 272 273 if (changed) { 274 pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK); 275 rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT; /* resync fifos */ 276 if (rate < PCXHR_IRQ_TIMER_FREQ) 277 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD; 278 else 279 rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2; 280 rmh.cmd[2] = rate; 281 rmh.cmd_len = 3; 282 err = pcxhr_send_msg(mgr, &rmh); 283 if (err) 284 return err; 285 } 286 snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq); 287 return 0; 288 } 289 290 291 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type, 292 int *sample_rate) 293 { 294 struct pcxhr_rmh rmh; 295 unsigned char reg; 296 int err, rate; 297 298 switch (clock_type) { 299 case PCXHR_CLOCK_TYPE_WORD_CLOCK : reg = REG_STATUS_WORD_CLOCK; break; 300 case PCXHR_CLOCK_TYPE_AES_SYNC : reg = REG_STATUS_AES_SYNC; break; 301 case PCXHR_CLOCK_TYPE_AES_1 : reg = REG_STATUS_AES_1; break; 302 case PCXHR_CLOCK_TYPE_AES_2 : reg = REG_STATUS_AES_2; break; 303 case PCXHR_CLOCK_TYPE_AES_3 : reg = REG_STATUS_AES_3; break; 304 case PCXHR_CLOCK_TYPE_AES_4 : reg = REG_STATUS_AES_4; break; 305 default : return -EINVAL; 306 } 307 pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ); 308 rmh.cmd_len = 2; 309 rmh.cmd[0] |= IO_NUM_REG_STATUS; 310 if (mgr->last_reg_stat != reg) { 311 rmh.cmd[1] = reg; 312 err = pcxhr_send_msg(mgr, &rmh); 313 if (err) 314 return err; 315 udelay(100); /* wait minimum 2 sample_frames at 32kHz ! */ 316 mgr->last_reg_stat = reg; 317 } 318 rmh.cmd[1] = REG_STATUS_CURRENT; 319 err = pcxhr_send_msg(mgr, &rmh); 320 if (err) 321 return err; 322 switch (rmh.stat[1] & 0x0f) { 323 case REG_STATUS_SYNC_32000 : rate = 32000; break; 324 case REG_STATUS_SYNC_44100 : rate = 44100; break; 325 case REG_STATUS_SYNC_48000 : rate = 48000; break; 326 case REG_STATUS_SYNC_64000 : rate = 64000; break; 327 case REG_STATUS_SYNC_88200 : rate = 88200; break; 328 case REG_STATUS_SYNC_96000 : rate = 96000; break; 329 case REG_STATUS_SYNC_128000 : rate = 128000; break; 330 case REG_STATUS_SYNC_176400 : rate = 176400; break; 331 case REG_STATUS_SYNC_192000 : rate = 192000; break; 332 default: rate = 0; 333 } 334 snd_printdd("External clock is at %d Hz\n", rate); 335 *sample_rate = rate; 336 return 0; 337 } 338 339 340 /* 341 * start or stop playback/capture substream 342 */ 343 static int pcxhr_set_stream_state(struct pcxhr_stream *stream) 344 { 345 int err; 346 struct snd_pcxhr *chip; 347 struct pcxhr_rmh rmh; 348 int stream_mask, start; 349 350 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) 351 start = 1; 352 else { 353 if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) { 354 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n"); 355 return -EINVAL; 356 } 357 start = 0; 358 } 359 if (!stream->substream) 360 return -EINVAL; 361 362 stream->timer_abs_periods = 0; 363 stream->timer_period_frag = 0; /* reset theoretical stream pos */ 364 stream->timer_buf_periods = 0; 365 stream->timer_is_synced = 0; 366 367 stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number; 368 369 pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM); 370 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 371 stream->pipe->first_audio, 0, stream_mask); 372 373 chip = snd_pcm_substream_chip(stream->substream); 374 375 err = pcxhr_send_msg(chip->mgr, &rmh); 376 if (err) 377 snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err); 378 stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED; 379 return err; 380 } 381 382 #define HEADER_FMT_BASE_LIN 0xfed00000 383 #define HEADER_FMT_BASE_FLOAT 0xfad00000 384 #define HEADER_FMT_INTEL 0x00008000 385 #define HEADER_FMT_24BITS 0x00004000 386 #define HEADER_FMT_16BITS 0x00002000 387 #define HEADER_FMT_UPTO11 0x00000200 388 #define HEADER_FMT_UPTO32 0x00000100 389 #define HEADER_FMT_MONO 0x00000080 390 391 static int pcxhr_set_format(struct pcxhr_stream *stream) 392 { 393 int err, is_capture, sample_rate, stream_num; 394 struct snd_pcxhr *chip; 395 struct pcxhr_rmh rmh; 396 unsigned int header; 397 398 switch (stream->format) { 399 case SNDRV_PCM_FORMAT_U8: 400 header = HEADER_FMT_BASE_LIN; 401 break; 402 case SNDRV_PCM_FORMAT_S16_LE: 403 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL; 404 break; 405 case SNDRV_PCM_FORMAT_S16_BE: 406 header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS; 407 break; 408 case SNDRV_PCM_FORMAT_S24_3LE: 409 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL; 410 break; 411 case SNDRV_PCM_FORMAT_S24_3BE: 412 header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS; 413 break; 414 case SNDRV_PCM_FORMAT_FLOAT_LE: 415 header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL; 416 break; 417 default: 418 snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n"); 419 return -EINVAL; 420 } 421 chip = snd_pcm_substream_chip(stream->substream); 422 423 sample_rate = chip->mgr->sample_rate; 424 if (sample_rate <= 32000 && sample_rate !=0) { 425 if (sample_rate <= 11025) 426 header |= HEADER_FMT_UPTO11; 427 else 428 header |= HEADER_FMT_UPTO32; 429 } 430 if (stream->channels == 1) 431 header |= HEADER_FMT_MONO; 432 433 is_capture = stream->pipe->is_capture; 434 stream_num = is_capture ? 0 : stream->substream->number; 435 436 pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT); 437 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); 438 if (is_capture) 439 rmh.cmd[0] |= 1<<12; 440 rmh.cmd[1] = 0; 441 rmh.cmd[2] = header >> 8; 442 rmh.cmd[3] = (header & 0xff) << 16; 443 rmh.cmd_len = 4; 444 err = pcxhr_send_msg(chip->mgr, &rmh); 445 if (err) 446 snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err); 447 return err; 448 } 449 450 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream) 451 { 452 int err, is_capture, stream_num; 453 struct pcxhr_rmh rmh; 454 struct snd_pcm_substream *subs = stream->substream; 455 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 456 457 is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE); 458 stream_num = is_capture ? 0 : subs->number; 459 460 snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n", 461 is_capture ? 'c' : 'p', 462 chip->chip_idx, (void*)subs->runtime->dma_addr, 463 subs->runtime->dma_bytes, subs->number); 464 465 pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS); 466 pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0); 467 468 snd_assert(subs->runtime->dma_bytes < 0x200000); /* max buffer size is 2 MByte */ 469 rmh.cmd[1] = subs->runtime->dma_bytes * 8; /* size in bits */ 470 rmh.cmd[2] = subs->runtime->dma_addr >> 24; /* most significant byte */ 471 rmh.cmd[2] |= 1<<19; /* this is a circular buffer */ 472 rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD; /* least 3 significant bytes */ 473 rmh.cmd_len = 4; 474 err = pcxhr_send_msg(chip->mgr, &rmh); 475 if (err) 476 snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err); 477 return err; 478 } 479 480 481 #if 0 482 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count) 483 { 484 struct pcxhr_rmh rmh; 485 int err; 486 pcxhr_t *chip = snd_pcm_substream_chip(stream->substream); 487 pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT); 488 pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0, 489 1<<stream->pipe->first_audio); 490 err = pcxhr_send_msg(chip->mgr, &rmh); 491 if (err == 0) { 492 *sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24; 493 *sample_count += (snd_pcm_uframes_t)rmh.stat[1]; 494 } 495 snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count); 496 return err; 497 } 498 #endif 499 500 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream, 501 struct pcxhr_pipe **pipe) 502 { 503 if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) { 504 *pipe = stream->pipe; 505 return 1; 506 } 507 return 0; 508 } 509 510 static void pcxhr_trigger_tasklet(unsigned long arg) 511 { 512 unsigned long flags; 513 int i, j, err; 514 struct pcxhr_pipe *pipe; 515 struct snd_pcxhr *chip; 516 struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg); 517 int capture_mask = 0; 518 int playback_mask = 0; 519 520 #ifdef CONFIG_SND_DEBUG_DETECT 521 struct timeval my_tv1, my_tv2; 522 do_gettimeofday(&my_tv1); 523 #endif 524 mutex_lock(&mgr->setup_mutex); 525 526 /* check the pipes concerned and build pipe_array */ 527 for (i = 0; i < mgr->num_cards; i++) { 528 chip = mgr->chip[i]; 529 for (j = 0; j < chip->nb_streams_capt; j++) { 530 if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe)) 531 capture_mask |= (1 << pipe->first_audio); 532 } 533 for (j = 0; j < chip->nb_streams_play; j++) { 534 if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) { 535 playback_mask |= (1 << pipe->first_audio); 536 break; /* add only once, as all playback streams of 537 * one chip use the same pipe 538 */ 539 } 540 } 541 } 542 if (capture_mask == 0 && playback_mask == 0) { 543 mutex_unlock(&mgr->setup_mutex); 544 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n"); 545 return; 546 } 547 548 snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n", 549 playback_mask, capture_mask); 550 551 /* synchronous stop of all the pipes concerned */ 552 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 0); 553 if (err) { 554 mutex_unlock(&mgr->setup_mutex); 555 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n", 556 playback_mask, capture_mask); 557 return; 558 } 559 560 /* unfortunately the dsp lost format and buffer info with the stop pipe */ 561 for (i = 0; i < mgr->num_cards; i++) { 562 struct pcxhr_stream *stream; 563 chip = mgr->chip[i]; 564 for (j = 0; j < chip->nb_streams_capt; j++) { 565 stream = &chip->capture_stream[j]; 566 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { 567 err = pcxhr_set_format(stream); 568 err = pcxhr_update_r_buffer(stream); 569 } 570 } 571 for (j = 0; j < chip->nb_streams_play; j++) { 572 stream = &chip->playback_stream[j]; 573 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) { 574 err = pcxhr_set_format(stream); 575 err = pcxhr_update_r_buffer(stream); 576 } 577 } 578 } 579 /* start all the streams */ 580 for (i = 0; i < mgr->num_cards; i++) { 581 struct pcxhr_stream *stream; 582 chip = mgr->chip[i]; 583 for (j = 0; j < chip->nb_streams_capt; j++) { 584 stream = &chip->capture_stream[j]; 585 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) 586 err = pcxhr_set_stream_state(stream); 587 } 588 for (j = 0; j < chip->nb_streams_play; j++) { 589 stream = &chip->playback_stream[j]; 590 if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) 591 err = pcxhr_set_stream_state(stream); 592 } 593 } 594 595 /* synchronous start of all the pipes concerned */ 596 err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1); 597 if (err) { 598 mutex_unlock(&mgr->setup_mutex); 599 snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n", 600 playback_mask, capture_mask); 601 return; 602 } 603 604 /* put the streams into the running state now (increment pointer by interrupt) */ 605 spin_lock_irqsave(&mgr->lock, flags); 606 for ( i =0; i < mgr->num_cards; i++) { 607 struct pcxhr_stream *stream; 608 chip = mgr->chip[i]; 609 for(j = 0; j < chip->nb_streams_capt; j++) { 610 stream = &chip->capture_stream[j]; 611 if(stream->status == PCXHR_STREAM_STATUS_STARTED) 612 stream->status = PCXHR_STREAM_STATUS_RUNNING; 613 } 614 for (j = 0; j < chip->nb_streams_play; j++) { 615 stream = &chip->playback_stream[j]; 616 if (stream->status == PCXHR_STREAM_STATUS_STARTED) { 617 /* playback will already have advanced ! */ 618 stream->timer_period_frag += PCXHR_GRANULARITY; 619 stream->status = PCXHR_STREAM_STATUS_RUNNING; 620 } 621 } 622 } 623 spin_unlock_irqrestore(&mgr->lock, flags); 624 625 mutex_unlock(&mgr->setup_mutex); 626 627 #ifdef CONFIG_SND_DEBUG_DETECT 628 do_gettimeofday(&my_tv2); 629 snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n", 630 my_tv2.tv_usec - my_tv1.tv_usec, err); 631 #endif 632 } 633 634 635 /* 636 * trigger callback 637 */ 638 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd) 639 { 640 struct pcxhr_stream *stream; 641 struct snd_pcm_substream *s; 642 643 switch (cmd) { 644 case SNDRV_PCM_TRIGGER_START: 645 snd_printdd("SNDRV_PCM_TRIGGER_START\n"); 646 if (snd_pcm_stream_linked(subs)) { 647 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 648 snd_pcm_group_for_each_entry(s, subs) { 649 stream = s->runtime->private_data; 650 stream->status = 651 PCXHR_STREAM_STATUS_SCHEDULE_RUN; 652 snd_pcm_trigger_done(s, subs); 653 } 654 tasklet_hi_schedule(&chip->mgr->trigger_taskq); 655 } else { 656 stream = subs->runtime->private_data; 657 snd_printdd("Only one Substream %c %d\n", 658 stream->pipe->is_capture ? 'C' : 'P', 659 stream->pipe->first_audio); 660 if (pcxhr_set_format(stream)) 661 return -EINVAL; 662 if (pcxhr_update_r_buffer(stream)) 663 return -EINVAL; 664 665 if (pcxhr_set_stream_state(stream)) 666 return -EINVAL; 667 stream->status = PCXHR_STREAM_STATUS_RUNNING; 668 } 669 break; 670 case SNDRV_PCM_TRIGGER_STOP: 671 snd_printdd("SNDRV_PCM_TRIGGER_STOP\n"); 672 snd_pcm_group_for_each_entry(s, subs) { 673 stream = s->runtime->private_data; 674 stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP; 675 if (pcxhr_set_stream_state(stream)) 676 return -EINVAL; 677 snd_pcm_trigger_done(s, subs); 678 } 679 break; 680 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 681 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 682 /* TODO */ 683 default: 684 return -EINVAL; 685 } 686 return 0; 687 } 688 689 690 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start) 691 { 692 struct pcxhr_rmh rmh; 693 int err; 694 695 pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT); 696 if (start) { 697 mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID; /* last dsp time invalid */ 698 rmh.cmd[0] |= PCXHR_GRANULARITY; 699 } 700 err = pcxhr_send_msg(mgr, &rmh); 701 if (err < 0) 702 snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err); 703 return err; 704 } 705 706 /* 707 * prepare callback for all pcms 708 */ 709 static int pcxhr_prepare(struct snd_pcm_substream *subs) 710 { 711 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 712 struct pcxhr_mgr *mgr = chip->mgr; 713 /* 714 struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data; 715 */ 716 int err = 0; 717 718 snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n", 719 subs->runtime->period_size, subs->runtime->periods, 720 subs->runtime->buffer_size); 721 722 /* 723 if(subs->runtime->period_size <= PCXHR_GRANULARITY) { 724 snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n", 725 (unsigned int)subs->runtime->period_size); 726 return -EINVAL; 727 } 728 */ 729 730 mutex_lock(&mgr->setup_mutex); 731 732 do { 733 /* if the stream was stopped before, format and buffer were reset */ 734 /* 735 if(stream->status == PCXHR_STREAM_STATUS_STOPPED) { 736 err = pcxhr_set_format(stream); 737 if(err) break; 738 err = pcxhr_update_r_buffer(stream); 739 if(err) break; 740 } 741 */ 742 743 /* only the first stream can choose the sample rate */ 744 /* the further opened streams will be limited to its frequency (see open) */ 745 /* set the clock only once (first stream) */ 746 if (mgr->sample_rate != subs->runtime->rate) { 747 err = pcxhr_set_clock(mgr, subs->runtime->rate); 748 if (err) 749 break; 750 if (mgr->sample_rate == 0) 751 /* start the DSP-timer */ 752 err = pcxhr_hardware_timer(mgr, 1); 753 mgr->sample_rate = subs->runtime->rate; 754 } 755 } while(0); /* do only once (so we can use break instead of goto) */ 756 757 mutex_unlock(&mgr->setup_mutex); 758 759 return err; 760 } 761 762 763 /* 764 * HW_PARAMS callback for all pcms 765 */ 766 static int pcxhr_hw_params(struct snd_pcm_substream *subs, 767 struct snd_pcm_hw_params *hw) 768 { 769 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 770 struct pcxhr_mgr *mgr = chip->mgr; 771 struct pcxhr_stream *stream = subs->runtime->private_data; 772 snd_pcm_format_t format; 773 int err; 774 int channels; 775 776 /* set up channels */ 777 channels = params_channels(hw); 778 779 /* set up format for the stream */ 780 format = params_format(hw); 781 782 mutex_lock(&mgr->setup_mutex); 783 784 stream->channels = channels; 785 stream->format = format; 786 787 /* set the format to the board */ 788 /* 789 err = pcxhr_set_format(stream); 790 if(err) { 791 mutex_unlock(&mgr->setup_mutex); 792 return err; 793 } 794 */ 795 /* allocate buffer */ 796 err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw)); 797 798 /* 799 if (err > 0) { 800 err = pcxhr_update_r_buffer(stream); 801 } 802 */ 803 mutex_unlock(&mgr->setup_mutex); 804 805 return err; 806 } 807 808 static int pcxhr_hw_free(struct snd_pcm_substream *subs) 809 { 810 snd_pcm_lib_free_pages(subs); 811 return 0; 812 } 813 814 815 /* 816 * CONFIGURATION SPACE for all pcms, mono pcm must update channels_max 817 */ 818 static struct snd_pcm_hardware pcxhr_caps = 819 { 820 .info = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 821 SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START | 822 0 /*SNDRV_PCM_INFO_PAUSE*/), 823 .formats = ( SNDRV_PCM_FMTBIT_U8 | 824 SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE | 825 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE | 826 SNDRV_PCM_FMTBIT_FLOAT_LE ), 827 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000, 828 .rate_min = 8000, 829 .rate_max = 192000, 830 .channels_min = 1, 831 .channels_max = 2, 832 .buffer_bytes_max = (32*1024), 833 /* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */ 834 .period_bytes_min = (2*PCXHR_GRANULARITY), 835 .period_bytes_max = (16*1024), 836 .periods_min = 2, 837 .periods_max = (32*1024/PCXHR_GRANULARITY), 838 }; 839 840 841 static int pcxhr_open(struct snd_pcm_substream *subs) 842 { 843 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 844 struct pcxhr_mgr *mgr = chip->mgr; 845 struct snd_pcm_runtime *runtime = subs->runtime; 846 struct pcxhr_stream *stream; 847 int is_capture; 848 849 mutex_lock(&mgr->setup_mutex); 850 851 /* copy the struct snd_pcm_hardware struct */ 852 runtime->hw = pcxhr_caps; 853 854 if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) { 855 snd_printdd("pcxhr_open playback chip%d subs%d\n", 856 chip->chip_idx, subs->number); 857 is_capture = 0; 858 stream = &chip->playback_stream[subs->number]; 859 } else { 860 snd_printdd("pcxhr_open capture chip%d subs%d\n", 861 chip->chip_idx, subs->number); 862 is_capture = 1; 863 if (mgr->mono_capture) 864 runtime->hw.channels_max = 1; 865 else 866 runtime->hw.channels_min = 2; 867 stream = &chip->capture_stream[subs->number]; 868 } 869 if (stream->status != PCXHR_STREAM_STATUS_FREE){ 870 /* streams in use */ 871 snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n", 872 chip->chip_idx, subs->number); 873 mutex_unlock(&mgr->setup_mutex); 874 return -EBUSY; 875 } 876 877 /* if a sample rate is already used or fixed by external clock, 878 * the stream cannot change 879 */ 880 if (mgr->sample_rate) 881 runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate; 882 else { 883 if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) { 884 int external_rate; 885 if (pcxhr_get_external_clock(mgr, mgr->use_clock_type, 886 &external_rate) || 887 external_rate == 0) { 888 /* cannot detect the external clock rate */ 889 mutex_unlock(&mgr->setup_mutex); 890 return -EBUSY; 891 } 892 runtime->hw.rate_min = runtime->hw.rate_max = external_rate; 893 } 894 } 895 896 stream->status = PCXHR_STREAM_STATUS_OPEN; 897 stream->substream = subs; 898 stream->channels = 0; /* not configured yet */ 899 900 runtime->private_data = stream; 901 902 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4); 903 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4); 904 905 mgr->ref_count_rate++; 906 907 mutex_unlock(&mgr->setup_mutex); 908 return 0; 909 } 910 911 912 static int pcxhr_close(struct snd_pcm_substream *subs) 913 { 914 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 915 struct pcxhr_mgr *mgr = chip->mgr; 916 struct pcxhr_stream *stream = subs->runtime->private_data; 917 918 mutex_lock(&mgr->setup_mutex); 919 920 snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number); 921 922 /* sample rate released */ 923 if (--mgr->ref_count_rate == 0) { 924 mgr->sample_rate = 0; /* the sample rate is no more locked */ 925 pcxhr_hardware_timer(mgr, 0); /* stop the DSP-timer */ 926 } 927 928 stream->status = PCXHR_STREAM_STATUS_FREE; 929 stream->substream = NULL; 930 931 mutex_unlock(&mgr->setup_mutex); 932 933 return 0; 934 } 935 936 937 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs) 938 { 939 unsigned long flags; 940 u_int32_t timer_period_frag; 941 int timer_buf_periods; 942 struct snd_pcxhr *chip = snd_pcm_substream_chip(subs); 943 struct snd_pcm_runtime *runtime = subs->runtime; 944 struct pcxhr_stream *stream = runtime->private_data; 945 946 spin_lock_irqsave(&chip->mgr->lock, flags); 947 948 /* get the period fragment and the nb of periods in the buffer */ 949 timer_period_frag = stream->timer_period_frag; 950 timer_buf_periods = stream->timer_buf_periods; 951 952 spin_unlock_irqrestore(&chip->mgr->lock, flags); 953 954 return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) + 955 timer_period_frag); 956 } 957 958 959 static struct snd_pcm_ops pcxhr_ops = { 960 .open = pcxhr_open, 961 .close = pcxhr_close, 962 .ioctl = snd_pcm_lib_ioctl, 963 .prepare = pcxhr_prepare, 964 .hw_params = pcxhr_hw_params, 965 .hw_free = pcxhr_hw_free, 966 .trigger = pcxhr_trigger, 967 .pointer = pcxhr_stream_pointer, 968 }; 969 970 /* 971 */ 972 int pcxhr_create_pcm(struct snd_pcxhr *chip) 973 { 974 int err; 975 struct snd_pcm *pcm; 976 char name[32]; 977 978 sprintf(name, "pcxhr %d", chip->chip_idx); 979 if ((err = snd_pcm_new(chip->card, name, 0, 980 chip->nb_streams_play, 981 chip->nb_streams_capt, &pcm)) < 0) { 982 snd_printk(KERN_ERR "cannot create pcm %s\n", name); 983 return err; 984 } 985 pcm->private_data = chip; 986 987 if (chip->nb_streams_play) 988 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops); 989 if (chip->nb_streams_capt) 990 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops); 991 992 pcm->info_flags = 0; 993 strcpy(pcm->name, name); 994 995 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 996 snd_dma_pci_data(chip->mgr->pci), 997 32*1024, 32*1024); 998 chip->pcm = pcm; 999 return 0; 1000 } 1001 1002 static int pcxhr_chip_free(struct snd_pcxhr *chip) 1003 { 1004 kfree(chip); 1005 return 0; 1006 } 1007 1008 static int pcxhr_chip_dev_free(struct snd_device *device) 1009 { 1010 struct snd_pcxhr *chip = device->device_data; 1011 return pcxhr_chip_free(chip); 1012 } 1013 1014 1015 /* 1016 */ 1017 static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx) 1018 { 1019 int err; 1020 struct snd_pcxhr *chip; 1021 static struct snd_device_ops ops = { 1022 .dev_free = pcxhr_chip_dev_free, 1023 }; 1024 1025 mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1026 if (! chip) { 1027 snd_printk(KERN_ERR "cannot allocate chip\n"); 1028 return -ENOMEM; 1029 } 1030 1031 chip->card = card; 1032 chip->chip_idx = idx; 1033 chip->mgr = mgr; 1034 1035 if (idx < mgr->playback_chips) 1036 /* stereo or mono streams */ 1037 chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS; 1038 1039 if (idx < mgr->capture_chips) { 1040 if (mgr->mono_capture) 1041 chip->nb_streams_capt = 2; /* 2 mono streams (left+right) */ 1042 else 1043 chip->nb_streams_capt = 1; /* or 1 stereo stream */ 1044 } 1045 1046 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1047 pcxhr_chip_free(chip); 1048 return err; 1049 } 1050 1051 snd_card_set_dev(card, &mgr->pci->dev); 1052 1053 return 0; 1054 } 1055 1056 /* proc interface */ 1057 static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1058 { 1059 struct snd_pcxhr *chip = entry->private_data; 1060 struct pcxhr_mgr *mgr = chip->mgr; 1061 1062 snd_iprintf(buffer, "\n%s\n", mgr->longname); 1063 1064 /* stats available when embedded DSP is running */ 1065 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1066 struct pcxhr_rmh rmh; 1067 short ver_maj = (mgr->dsp_version >> 16) & 0xff; 1068 short ver_min = (mgr->dsp_version >> 8) & 0xff; 1069 short ver_build = mgr->dsp_version & 0xff; 1070 snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING); 1071 snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build); 1072 if (mgr->board_has_analog) 1073 snd_iprintf(buffer, "analog io available\n"); 1074 else 1075 snd_iprintf(buffer, "digital only board\n"); 1076 1077 /* calc cpu load of the dsp */ 1078 pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES); 1079 if( ! pcxhr_send_msg(mgr, &rmh) ) { 1080 int cur = rmh.stat[0]; 1081 int ref = rmh.stat[1]; 1082 if (ref > 0) { 1083 if (mgr->sample_rate_real != 0 && 1084 mgr->sample_rate_real != 48000) { 1085 ref = (ref * 48000) / mgr->sample_rate_real; 1086 if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ) 1087 ref *= 2; 1088 } 1089 cur = 100 - (100 * cur) / ref; 1090 snd_iprintf(buffer, "cpu load %d%%\n", cur); 1091 snd_iprintf(buffer, "buffer pool %d/%d kWords\n", 1092 rmh.stat[2], rmh.stat[3]); 1093 } 1094 } 1095 snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY); 1096 snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err); 1097 snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n", 1098 mgr->async_err_pipe_xrun); 1099 snd_iprintf(buffer, "dsp async stream xrun errors : %d\n", 1100 mgr->async_err_stream_xrun); 1101 snd_iprintf(buffer, "dsp async last other error : %x\n", 1102 mgr->async_err_other_last); 1103 /* debug zone dsp */ 1104 rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS; 1105 rmh.cmd_len = 1; 1106 rmh.stat_len = PCXHR_SIZE_MAX_STATUS; 1107 rmh.dsp_stat = 0; 1108 rmh.cmd_idx = CMD_LAST_INDEX; 1109 if( ! pcxhr_send_msg(mgr, &rmh) ) { 1110 int i; 1111 for (i = 0; i < rmh.stat_len; i++) 1112 snd_iprintf(buffer, "debug[%02d] = %06x\n", i, rmh.stat[i]); 1113 } 1114 } else 1115 snd_iprintf(buffer, "no firmware loaded\n"); 1116 snd_iprintf(buffer, "\n"); 1117 } 1118 static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer) 1119 { 1120 struct snd_pcxhr *chip = entry->private_data; 1121 struct pcxhr_mgr *mgr = chip->mgr; 1122 static char *texts[7] = { 1123 "Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4" 1124 }; 1125 1126 snd_iprintf(buffer, "\n%s\n", mgr->longname); 1127 snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]); 1128 snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real); 1129 1130 /* commands available when embedded DSP is running */ 1131 if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) { 1132 int i, err, sample_rate; 1133 for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) { 1134 err = pcxhr_get_external_clock(mgr, i, &sample_rate); 1135 if (err) 1136 break; 1137 snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate); 1138 } 1139 } else 1140 snd_iprintf(buffer, "no firmware loaded\n"); 1141 snd_iprintf(buffer, "\n"); 1142 } 1143 1144 static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip) 1145 { 1146 struct snd_info_entry *entry; 1147 1148 if (! snd_card_proc_new(chip->card, "info", &entry)) 1149 snd_info_set_text_ops(entry, chip, pcxhr_proc_info); 1150 if (! snd_card_proc_new(chip->card, "sync", &entry)) 1151 snd_info_set_text_ops(entry, chip, pcxhr_proc_sync); 1152 } 1153 /* end of proc interface */ 1154 1155 /* 1156 * release all the cards assigned to a manager instance 1157 */ 1158 static int pcxhr_free(struct pcxhr_mgr *mgr) 1159 { 1160 unsigned int i; 1161 1162 for (i = 0; i < mgr->num_cards; i++) { 1163 if (mgr->chip[i]) 1164 snd_card_free(mgr->chip[i]->card); 1165 } 1166 1167 /* reset board if some firmware was loaded */ 1168 if(mgr->dsp_loaded) { 1169 pcxhr_reset_board(mgr); 1170 snd_printdd("reset pcxhr !\n"); 1171 } 1172 1173 /* release irq */ 1174 if (mgr->irq >= 0) 1175 free_irq(mgr->irq, mgr); 1176 1177 pci_release_regions(mgr->pci); 1178 1179 /* free hostport purgebuffer */ 1180 if (mgr->hostport.area) { 1181 snd_dma_free_pages(&mgr->hostport); 1182 mgr->hostport.area = NULL; 1183 } 1184 1185 kfree(mgr->prmh); 1186 1187 pci_disable_device(mgr->pci); 1188 kfree(mgr); 1189 return 0; 1190 } 1191 1192 /* 1193 * probe function - creates the card manager 1194 */ 1195 static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) 1196 { 1197 static int dev; 1198 struct pcxhr_mgr *mgr; 1199 unsigned int i; 1200 int err; 1201 size_t size; 1202 char *card_name; 1203 1204 if (dev >= SNDRV_CARDS) 1205 return -ENODEV; 1206 if (! enable[dev]) { 1207 dev++; 1208 return -ENOENT; 1209 } 1210 1211 /* enable PCI device */ 1212 if ((err = pci_enable_device(pci)) < 0) 1213 return err; 1214 pci_set_master(pci); 1215 1216 /* check if we can restrict PCI DMA transfers to 32 bits */ 1217 if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) { 1218 snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n"); 1219 pci_disable_device(pci); 1220 return -ENXIO; 1221 } 1222 1223 /* alloc card manager */ 1224 mgr = kzalloc(sizeof(*mgr), GFP_KERNEL); 1225 if (! mgr) { 1226 pci_disable_device(pci); 1227 return -ENOMEM; 1228 } 1229 1230 snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV); 1231 card_name = pcxhr_board_params[pci_id->driver_data].board_name; 1232 mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips; 1233 mgr->capture_chips = pcxhr_board_params[pci_id->driver_data].capture_chips; 1234 mgr->firmware_num = pcxhr_board_params[pci_id->driver_data].firmware_num; 1235 mgr->mono_capture = mono[dev]; 1236 1237 /* resource assignment */ 1238 if ((err = pci_request_regions(pci, card_name)) < 0) { 1239 kfree(mgr); 1240 pci_disable_device(pci); 1241 return err; 1242 } 1243 for (i = 0; i < 3; i++) 1244 mgr->port[i] = pci_resource_start(pci, i); 1245 1246 mgr->pci = pci; 1247 mgr->irq = -1; 1248 1249 if (request_irq(pci->irq, pcxhr_interrupt, IRQF_SHARED, 1250 card_name, mgr)) { 1251 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 1252 pcxhr_free(mgr); 1253 return -EBUSY; 1254 } 1255 mgr->irq = pci->irq; 1256 1257 sprintf(mgr->shortname, "Digigram %s", card_name); 1258 sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname, 1259 mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq); 1260 1261 /* ISR spinlock */ 1262 spin_lock_init(&mgr->lock); 1263 spin_lock_init(&mgr->msg_lock); 1264 1265 /* init setup mutex*/ 1266 mutex_init(&mgr->setup_mutex); 1267 1268 /* init taslket */ 1269 tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr); 1270 tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr); 1271 mgr->prmh = kmalloc(sizeof(*mgr->prmh) + 1272 sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS), 1273 GFP_KERNEL); 1274 if (! mgr->prmh) { 1275 pcxhr_free(mgr); 1276 return -ENOMEM; 1277 } 1278 1279 for (i=0; i < PCXHR_MAX_CARDS; i++) { 1280 struct snd_card *card; 1281 char tmpid[16]; 1282 int idx; 1283 1284 if (i >= max(mgr->playback_chips, mgr->capture_chips)) 1285 break; 1286 mgr->num_cards++; 1287 1288 if (index[dev] < 0) 1289 idx = index[dev]; 1290 else 1291 idx = index[dev] + i; 1292 1293 snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i); 1294 card = snd_card_new(idx, tmpid, THIS_MODULE, 0); 1295 1296 if (! card) { 1297 snd_printk(KERN_ERR "cannot allocate the card %d\n", i); 1298 pcxhr_free(mgr); 1299 return -ENOMEM; 1300 } 1301 1302 strcpy(card->driver, DRIVER_NAME); 1303 sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i); 1304 sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i); 1305 1306 if ((err = pcxhr_create(mgr, card, i)) < 0) { 1307 pcxhr_free(mgr); 1308 return err; 1309 } 1310 1311 if (i == 0) 1312 /* init proc interface only for chip0 */ 1313 pcxhr_proc_init(mgr->chip[i]); 1314 1315 if ((err = snd_card_register(card)) < 0) { 1316 pcxhr_free(mgr); 1317 return err; 1318 } 1319 } 1320 1321 /* create hostport purgebuffer */ 1322 size = PAGE_ALIGN(sizeof(struct pcxhr_hostport)); 1323 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1324 size, &mgr->hostport) < 0) { 1325 pcxhr_free(mgr); 1326 return -ENOMEM; 1327 } 1328 /* init purgebuffer */ 1329 memset(mgr->hostport.area, 0, size); 1330 1331 /* create a DSP loader */ 1332 err = pcxhr_setup_firmware(mgr); 1333 if (err < 0) { 1334 pcxhr_free(mgr); 1335 return err; 1336 } 1337 1338 pci_set_drvdata(pci, mgr); 1339 dev++; 1340 return 0; 1341 } 1342 1343 static void __devexit pcxhr_remove(struct pci_dev *pci) 1344 { 1345 pcxhr_free(pci_get_drvdata(pci)); 1346 pci_set_drvdata(pci, NULL); 1347 } 1348 1349 static struct pci_driver driver = { 1350 .name = "Digigram pcxhr", 1351 .id_table = pcxhr_ids, 1352 .probe = pcxhr_probe, 1353 .remove = __devexit_p(pcxhr_remove), 1354 }; 1355 1356 static int __init pcxhr_module_init(void) 1357 { 1358 return pci_register_driver(&driver); 1359 } 1360 1361 static void __exit pcxhr_module_exit(void) 1362 { 1363 pci_unregister_driver(&driver); 1364 } 1365 1366 module_init(pcxhr_module_init) 1367 module_exit(pcxhr_module_exit) 1368