xref: /openbmc/linux/sound/pci/pcxhr/pcxhr.c (revision 643d1f7f)
1 /*
2  * Driver for Digigram pcxhr compatible soundcards
3  *
4  * main file with alsa callbacks
5  *
6  * Copyright (c) 2004 by Digigram <alsa@digigram.com>
7  *
8  *   This program is free software; you can redistribute it and/or modify
9  *   it under the terms of the GNU General Public License as published by
10  *   the Free Software Foundation; either version 2 of the License, or
11  *   (at your option) any later version.
12  *
13  *   This program is distributed in the hope that it will be useful,
14  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *   GNU General Public License for more details.
17  *
18  *   You should have received a copy of the GNU General Public License
19  *   along with this program; if not, write to the Free Software
20  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21  */
22 
23 
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/slab.h>
27 #include <linux/pci.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/delay.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mutex.h>
32 
33 #include <sound/core.h>
34 #include <sound/initval.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include "pcxhr.h"
40 #include "pcxhr_mixer.h"
41 #include "pcxhr_hwdep.h"
42 #include "pcxhr_core.h"
43 
44 #define DRIVER_NAME "pcxhr"
45 
46 MODULE_AUTHOR("Markus Bollinger <bollinger@digigram.com>");
47 MODULE_DESCRIPTION("Digigram " DRIVER_NAME " " PCXHR_DRIVER_VERSION_STRING);
48 MODULE_LICENSE("GPL");
49 MODULE_SUPPORTED_DEVICE("{{Digigram," DRIVER_NAME "}}");
50 
51 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;		/* Index 0-MAX */
52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;		/* ID for this card */
53 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;	/* Enable this card */
54 static int mono[SNDRV_CARDS];					/* capture in mono only */
55 
56 module_param_array(index, int, NULL, 0444);
57 MODULE_PARM_DESC(index, "Index value for Digigram " DRIVER_NAME " soundcard");
58 module_param_array(id, charp, NULL, 0444);
59 MODULE_PARM_DESC(id, "ID string for Digigram " DRIVER_NAME " soundcard");
60 module_param_array(enable, bool, NULL, 0444);
61 MODULE_PARM_DESC(enable, "Enable Digigram " DRIVER_NAME " soundcard");
62 module_param_array(mono, bool, NULL, 0444);
63 MODULE_PARM_DESC(mono, "Mono capture mode (default is stereo)");
64 
65 enum {
66 	PCI_ID_VX882HR,
67 	PCI_ID_PCX882HR,
68 	PCI_ID_VX881HR,
69 	PCI_ID_PCX881HR,
70 	PCI_ID_PCX1222HR,
71 	PCI_ID_PCX1221HR,
72 	PCI_ID_LAST
73 };
74 
75 static struct pci_device_id pcxhr_ids[] = {
76 	{ 0x10b5, 0x9656, 0x1369, 0xb001, 0, 0, PCI_ID_VX882HR, },   /* VX882HR */
77 	{ 0x10b5, 0x9656, 0x1369, 0xb101, 0, 0, PCI_ID_PCX882HR, },  /* PCX882HR */
78 	{ 0x10b5, 0x9656, 0x1369, 0xb201, 0, 0, PCI_ID_VX881HR, },   /* VX881HR */
79 	{ 0x10b5, 0x9656, 0x1369, 0xb301, 0, 0, PCI_ID_PCX881HR, },  /* PCX881HR */
80 	{ 0x10b5, 0x9656, 0x1369, 0xb501, 0, 0, PCI_ID_PCX1222HR, }, /* PCX1222HR */
81 	{ 0x10b5, 0x9656, 0x1369, 0xb701, 0, 0, PCI_ID_PCX1221HR, }, /* PCX1221HR */
82 	{ 0, }
83 };
84 
85 MODULE_DEVICE_TABLE(pci, pcxhr_ids);
86 
87 struct board_parameters {
88 	char* board_name;
89 	short playback_chips;
90 	short capture_chips;
91 	short firmware_num;
92 };
93 static struct board_parameters pcxhr_board_params[] = {
94 [PCI_ID_VX882HR] =	{ "VX882HR",   4, 4, 41, },
95 [PCI_ID_PCX882HR] =	{ "PCX882HR",  4, 4, 41, },
96 [PCI_ID_VX881HR] =	{ "VX881HR",   4, 4, 41, },
97 [PCI_ID_PCX881HR] =	{ "PCX881HR",  4, 4, 41, },
98 [PCI_ID_PCX1222HR] =	{ "PCX1222HR", 6, 1, 42, },
99 [PCI_ID_PCX1221HR] =	{ "PCX1221HR", 6, 1, 42, },
100 };
101 
102 
103 static int pcxhr_pll_freq_register(unsigned int freq, unsigned int* pllreg,
104 				   unsigned int* realfreq)
105 {
106 	unsigned int reg;
107 
108 	if (freq < 6900 || freq > 110250)
109 		return -EINVAL;
110 	reg = (28224000 * 10) / freq;
111 	reg = (reg + 5) / 10;
112 	if (reg < 0x200)
113 		*pllreg = reg + 0x800;
114 	else if (reg < 0x400)
115 		*pllreg = reg & 0x1ff;
116 	else if (reg < 0x800) {
117 		*pllreg = ((reg >> 1) & 0x1ff) + 0x200;
118 		reg &= ~1;
119 	} else {
120 		*pllreg = ((reg >> 2) & 0x1ff) + 0x400;
121 		reg &= ~3;
122 	}
123 	if (realfreq)
124 		*realfreq = ((28224000 * 10) / reg + 5) / 10;
125 	return 0;
126 }
127 
128 
129 #define PCXHR_FREQ_REG_MASK		0x1f
130 #define PCXHR_FREQ_QUARTZ_48000		0x00
131 #define PCXHR_FREQ_QUARTZ_24000		0x01
132 #define PCXHR_FREQ_QUARTZ_12000		0x09
133 #define PCXHR_FREQ_QUARTZ_32000		0x08
134 #define PCXHR_FREQ_QUARTZ_16000		0x04
135 #define PCXHR_FREQ_QUARTZ_8000		0x0c
136 #define PCXHR_FREQ_QUARTZ_44100		0x02
137 #define PCXHR_FREQ_QUARTZ_22050		0x0a
138 #define PCXHR_FREQ_QUARTZ_11025		0x06
139 #define PCXHR_FREQ_PLL			0x05
140 #define PCXHR_FREQ_QUARTZ_192000	0x10
141 #define PCXHR_FREQ_QUARTZ_96000		0x18
142 #define PCXHR_FREQ_QUARTZ_176400	0x14
143 #define PCXHR_FREQ_QUARTZ_88200		0x1c
144 #define PCXHR_FREQ_QUARTZ_128000	0x12
145 #define PCXHR_FREQ_QUARTZ_64000		0x1a
146 
147 #define PCXHR_FREQ_WORD_CLOCK		0x0f
148 #define PCXHR_FREQ_SYNC_AES		0x0e
149 #define PCXHR_FREQ_AES_1		0x07
150 #define PCXHR_FREQ_AES_2		0x0b
151 #define PCXHR_FREQ_AES_3		0x03
152 #define PCXHR_FREQ_AES_4		0x0d
153 
154 #define PCXHR_MODIFY_CLOCK_S_BIT	0x04
155 
156 #define PCXHR_IRQ_TIMER_FREQ		92000
157 #define PCXHR_IRQ_TIMER_PERIOD		48
158 
159 static int pcxhr_get_clock_reg(struct pcxhr_mgr *mgr, unsigned int rate,
160 			       unsigned int *reg, unsigned int *freq)
161 {
162 	unsigned int val, realfreq, pllreg;
163 	struct pcxhr_rmh rmh;
164 	int err;
165 
166 	realfreq = rate;
167 	switch (mgr->use_clock_type) {
168 	case PCXHR_CLOCK_TYPE_INTERNAL :	/* clock by quartz or pll */
169 		switch (rate) {
170 		case 48000 :	val = PCXHR_FREQ_QUARTZ_48000;	break;
171 		case 24000 :	val = PCXHR_FREQ_QUARTZ_24000;	break;
172 		case 12000 :	val = PCXHR_FREQ_QUARTZ_12000;	break;
173 		case 32000 :	val = PCXHR_FREQ_QUARTZ_32000;	break;
174 		case 16000 :	val = PCXHR_FREQ_QUARTZ_16000;	break;
175 		case 8000 :	val = PCXHR_FREQ_QUARTZ_8000;	break;
176 		case 44100 :	val = PCXHR_FREQ_QUARTZ_44100;	break;
177 		case 22050 :	val = PCXHR_FREQ_QUARTZ_22050;	break;
178 		case 11025 :	val = PCXHR_FREQ_QUARTZ_11025;	break;
179 		case 192000 :	val = PCXHR_FREQ_QUARTZ_192000;	break;
180 		case 96000 :	val = PCXHR_FREQ_QUARTZ_96000;	break;
181 		case 176400 :	val = PCXHR_FREQ_QUARTZ_176400;	break;
182 		case 88200 :	val = PCXHR_FREQ_QUARTZ_88200;	break;
183 		case 128000 :	val = PCXHR_FREQ_QUARTZ_128000;	break;
184 		case 64000 :	val = PCXHR_FREQ_QUARTZ_64000;	break;
185 		default :
186 			val = PCXHR_FREQ_PLL;
187 			/* get the value for the pll register */
188 			err = pcxhr_pll_freq_register(rate, &pllreg, &realfreq);
189 			if (err)
190 				return err;
191 			pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
192 			rmh.cmd[0] |= IO_NUM_REG_GENCLK;
193 			rmh.cmd[1]  = pllreg & MASK_DSP_WORD;
194 			rmh.cmd[2]  = pllreg >> 24;
195 			rmh.cmd_len = 3;
196 			err = pcxhr_send_msg(mgr, &rmh);
197 			if (err < 0) {
198 				snd_printk(KERN_ERR
199 					   "error CMD_ACCESS_IO_WRITE for PLL register : %x!\n",
200 					   err );
201 				return err;
202 			}
203 		}
204 		break;
205 	case PCXHR_CLOCK_TYPE_WORD_CLOCK :	val = PCXHR_FREQ_WORD_CLOCK;	break;
206 	case PCXHR_CLOCK_TYPE_AES_SYNC :	val = PCXHR_FREQ_SYNC_AES;	break;
207 	case PCXHR_CLOCK_TYPE_AES_1 :		val = PCXHR_FREQ_AES_1;		break;
208 	case PCXHR_CLOCK_TYPE_AES_2 :		val = PCXHR_FREQ_AES_2;		break;
209 	case PCXHR_CLOCK_TYPE_AES_3 :		val = PCXHR_FREQ_AES_3;		break;
210 	case PCXHR_CLOCK_TYPE_AES_4 :		val = PCXHR_FREQ_AES_4;		break;
211 	default : return -EINVAL;
212 	}
213 	*reg = val;
214 	*freq = realfreq;
215 	return 0;
216 }
217 
218 
219 int pcxhr_set_clock(struct pcxhr_mgr *mgr, unsigned int rate)
220 {
221 	unsigned int val, realfreq, speed;
222 	struct pcxhr_rmh rmh;
223 	int err, changed;
224 
225 	if (rate == 0)
226 		return 0; /* nothing to do */
227 
228 	err = pcxhr_get_clock_reg(mgr, rate, &val, &realfreq);
229 	if (err)
230 		return err;
231 
232 	/* codec speed modes */
233 	if (rate < 55000)
234 		speed = 0;	/* single speed */
235 	else if (rate < 100000)
236 		speed = 1;	/* dual speed */
237 	else
238 		speed = 2;	/* quad speed */
239 	if (mgr->codec_speed != speed) {
240 		pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);	/* mute outputs */
241 		rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
242 		err = pcxhr_send_msg(mgr, &rmh);
243 		if (err)
244 			return err;
245 
246 		pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);	/* set speed ratio */
247 		rmh.cmd[0] |= IO_NUM_SPEED_RATIO;
248 		rmh.cmd[1] = speed;
249 		rmh.cmd_len = 2;
250 		err = pcxhr_send_msg(mgr, &rmh);
251 		if (err)
252 			return err;
253 	}
254 	/* set the new frequency */
255 	snd_printdd("clock register : set %x\n", val);
256 	err = pcxhr_write_io_num_reg_cont(mgr, PCXHR_FREQ_REG_MASK, val, &changed);
257 	if (err)
258 		return err;
259 	mgr->sample_rate_real = realfreq;
260 	mgr->cur_clock_type = mgr->use_clock_type;
261 
262 	/* unmute after codec speed modes */
263 	if (mgr->codec_speed != speed) {
264 		pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);	/* unmute outputs */
265 		rmh.cmd[0] |= IO_NUM_REG_MUTE_OUT;
266 		err = pcxhr_send_msg(mgr, &rmh);
267 		if (err)
268 			return err;
269 		mgr->codec_speed = speed;			/* save new codec speed */
270 	}
271 
272 	if (changed) {
273 		pcxhr_init_rmh(&rmh, CMD_MODIFY_CLOCK);
274 		rmh.cmd[0] |= PCXHR_MODIFY_CLOCK_S_BIT;		/* resync fifos  */
275 		if (rate < PCXHR_IRQ_TIMER_FREQ)
276 			rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD;
277 		else
278 			rmh.cmd[1] = PCXHR_IRQ_TIMER_PERIOD * 2;
279 		rmh.cmd[2] = rate;
280 		rmh.cmd_len = 3;
281 		err = pcxhr_send_msg(mgr, &rmh);
282 		if (err)
283 			return err;
284 	}
285 	snd_printdd("pcxhr_set_clock to %dHz (realfreq=%d)\n", rate, realfreq);
286 	return 0;
287 }
288 
289 
290 int pcxhr_get_external_clock(struct pcxhr_mgr *mgr, enum pcxhr_clock_type clock_type,
291 			     int *sample_rate)
292 {
293 	struct pcxhr_rmh rmh;
294 	unsigned char reg;
295 	int err, rate;
296 
297 	switch (clock_type) {
298 	case PCXHR_CLOCK_TYPE_WORD_CLOCK :	reg = REG_STATUS_WORD_CLOCK;	break;
299 	case PCXHR_CLOCK_TYPE_AES_SYNC :	reg = REG_STATUS_AES_SYNC;	break;
300 	case PCXHR_CLOCK_TYPE_AES_1 :		reg = REG_STATUS_AES_1;		break;
301 	case PCXHR_CLOCK_TYPE_AES_2 :		reg = REG_STATUS_AES_2;		break;
302 	case PCXHR_CLOCK_TYPE_AES_3 :		reg = REG_STATUS_AES_3;		break;
303 	case PCXHR_CLOCK_TYPE_AES_4 :		reg = REG_STATUS_AES_4;		break;
304 	default : return -EINVAL;
305 	}
306 	pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_READ);
307 	rmh.cmd_len = 2;
308 	rmh.cmd[0] |= IO_NUM_REG_STATUS;
309 	if (mgr->last_reg_stat != reg) {
310 		rmh.cmd[1]  = reg;
311 		err = pcxhr_send_msg(mgr, &rmh);
312 		if (err)
313 			return err;
314 		udelay(100);		/* wait minimum 2 sample_frames at 32kHz ! */
315 		mgr->last_reg_stat = reg;
316 	}
317 	rmh.cmd[1]  = REG_STATUS_CURRENT;
318 	err = pcxhr_send_msg(mgr, &rmh);
319 	if (err)
320 		return err;
321 	switch (rmh.stat[1] & 0x0f) {
322 	case REG_STATUS_SYNC_32000 :	rate = 32000; break;
323 	case REG_STATUS_SYNC_44100 :	rate = 44100; break;
324 	case REG_STATUS_SYNC_48000 :	rate = 48000; break;
325 	case REG_STATUS_SYNC_64000 :	rate = 64000; break;
326 	case REG_STATUS_SYNC_88200 :	rate = 88200; break;
327 	case REG_STATUS_SYNC_96000 :	rate = 96000; break;
328 	case REG_STATUS_SYNC_128000 :	rate = 128000; break;
329 	case REG_STATUS_SYNC_176400 :	rate = 176400; break;
330 	case REG_STATUS_SYNC_192000 :	rate = 192000; break;
331 	default: rate = 0;
332 	}
333 	snd_printdd("External clock is at %d Hz\n", rate);
334 	*sample_rate = rate;
335 	return 0;
336 }
337 
338 
339 /*
340  *  start or stop playback/capture substream
341  */
342 static int pcxhr_set_stream_state(struct pcxhr_stream *stream)
343 {
344 	int err;
345 	struct snd_pcxhr *chip;
346 	struct pcxhr_rmh rmh;
347 	int stream_mask, start;
348 
349 	if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN)
350 		start = 1;
351 	else {
352 		if (stream->status != PCXHR_STREAM_STATUS_SCHEDULE_STOP) {
353 			snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state CANNOT be stopped\n");
354 			return -EINVAL;
355 		}
356 		start = 0;
357 	}
358 	if (!stream->substream)
359 		return -EINVAL;
360 
361 	stream->timer_abs_periods = 0;
362 	stream->timer_period_frag = 0;            /* reset theoretical stream pos */
363 	stream->timer_buf_periods = 0;
364 	stream->timer_is_synced = 0;
365 
366 	stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
367 
368 	pcxhr_init_rmh(&rmh, start ? CMD_START_STREAM : CMD_STOP_STREAM);
369 	pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
370 				  stream->pipe->first_audio, 0, stream_mask);
371 
372 	chip = snd_pcm_substream_chip(stream->substream);
373 
374 	err = pcxhr_send_msg(chip->mgr, &rmh);
375 	if (err)
376 		snd_printk(KERN_ERR "ERROR pcxhr_set_stream_state err=%x;\n", err);
377 	stream->status = start ? PCXHR_STREAM_STATUS_STARTED : PCXHR_STREAM_STATUS_STOPPED;
378 	return err;
379 }
380 
381 #define HEADER_FMT_BASE_LIN		0xfed00000
382 #define HEADER_FMT_BASE_FLOAT		0xfad00000
383 #define HEADER_FMT_INTEL		0x00008000
384 #define HEADER_FMT_24BITS		0x00004000
385 #define HEADER_FMT_16BITS		0x00002000
386 #define HEADER_FMT_UPTO11		0x00000200
387 #define HEADER_FMT_UPTO32		0x00000100
388 #define HEADER_FMT_MONO			0x00000080
389 
390 static int pcxhr_set_format(struct pcxhr_stream *stream)
391 {
392 	int err, is_capture, sample_rate, stream_num;
393 	struct snd_pcxhr *chip;
394 	struct pcxhr_rmh rmh;
395 	unsigned int header;
396 
397 	switch (stream->format) {
398 	case SNDRV_PCM_FORMAT_U8:
399 		header = HEADER_FMT_BASE_LIN;
400 		break;
401 	case SNDRV_PCM_FORMAT_S16_LE:
402 		header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS | HEADER_FMT_INTEL;
403 		break;
404 	case SNDRV_PCM_FORMAT_S16_BE:
405 		header = HEADER_FMT_BASE_LIN | HEADER_FMT_16BITS;
406 		break;
407 	case SNDRV_PCM_FORMAT_S24_3LE:
408 		header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS | HEADER_FMT_INTEL;
409 		break;
410 	case SNDRV_PCM_FORMAT_S24_3BE:
411 		header = HEADER_FMT_BASE_LIN | HEADER_FMT_24BITS;
412 		break;
413 	case SNDRV_PCM_FORMAT_FLOAT_LE:
414 		header = HEADER_FMT_BASE_FLOAT | HEADER_FMT_INTEL;
415 		break;
416 	default:
417 		snd_printk(KERN_ERR "error pcxhr_set_format() : unknown format\n");
418 		return -EINVAL;
419 	}
420 	chip = snd_pcm_substream_chip(stream->substream);
421 
422 	sample_rate = chip->mgr->sample_rate;
423 	if (sample_rate <= 32000 && sample_rate !=0) {
424 		if (sample_rate <= 11025)
425 			header |= HEADER_FMT_UPTO11;
426 		else
427 			header |= HEADER_FMT_UPTO32;
428 	}
429 	if (stream->channels == 1)
430 		header |= HEADER_FMT_MONO;
431 
432 	is_capture = stream->pipe->is_capture;
433 	stream_num = is_capture ? 0 : stream->substream->number;
434 
435 	pcxhr_init_rmh(&rmh, is_capture ? CMD_FORMAT_STREAM_IN : CMD_FORMAT_STREAM_OUT);
436 	pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
437 	if (is_capture)
438 		rmh.cmd[0] |= 1<<12;
439 	rmh.cmd[1] = 0;
440 	rmh.cmd[2] = header >> 8;
441 	rmh.cmd[3] = (header & 0xff) << 16;
442 	rmh.cmd_len = 4;
443 	err = pcxhr_send_msg(chip->mgr, &rmh);
444 	if (err)
445 		snd_printk(KERN_ERR "ERROR pcxhr_set_format err=%x;\n", err);
446 	return err;
447 }
448 
449 static int pcxhr_update_r_buffer(struct pcxhr_stream *stream)
450 {
451 	int err, is_capture, stream_num;
452 	struct pcxhr_rmh rmh;
453 	struct snd_pcm_substream *subs = stream->substream;
454 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
455 
456 	is_capture = (subs->stream == SNDRV_PCM_STREAM_CAPTURE);
457 	stream_num = is_capture ? 0 : subs->number;
458 
459 	snd_printdd("pcxhr_update_r_buffer(pcm%c%d) : addr(%p) bytes(%zx) subs(%d)\n",
460 		    is_capture ? 'c' : 'p',
461 		    chip->chip_idx, (void*)subs->runtime->dma_addr,
462 		    subs->runtime->dma_bytes, subs->number);
463 
464 	pcxhr_init_rmh(&rmh, CMD_UPDATE_R_BUFFERS);
465 	pcxhr_set_pipe_cmd_params(&rmh, is_capture, stream->pipe->first_audio, stream_num, 0);
466 
467 	snd_assert(subs->runtime->dma_bytes < 0x200000);	/* max buffer size is 2 MByte */
468 	rmh.cmd[1] = subs->runtime->dma_bytes * 8;		/* size in bits */
469 	rmh.cmd[2] = subs->runtime->dma_addr >> 24;		/* most significant byte */
470 	rmh.cmd[2] |= 1<<19;					/* this is a circular buffer */
471 	rmh.cmd[3] = subs->runtime->dma_addr & MASK_DSP_WORD;	/* least 3 significant bytes */
472 	rmh.cmd_len = 4;
473 	err = pcxhr_send_msg(chip->mgr, &rmh);
474 	if (err)
475 		snd_printk(KERN_ERR "ERROR CMD_UPDATE_R_BUFFERS err=%x;\n", err);
476 	return err;
477 }
478 
479 
480 #if 0
481 static int pcxhr_pipe_sample_count(struct pcxhr_stream *stream, snd_pcm_uframes_t *sample_count)
482 {
483 	struct pcxhr_rmh rmh;
484 	int err;
485 	pcxhr_t *chip = snd_pcm_substream_chip(stream->substream);
486 	pcxhr_init_rmh(&rmh, CMD_PIPE_SAMPLE_COUNT);
487 	pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture, 0, 0,
488 				  1<<stream->pipe->first_audio);
489 	err = pcxhr_send_msg(chip->mgr, &rmh);
490 	if (err == 0) {
491 		*sample_count = ((snd_pcm_uframes_t)rmh.stat[0]) << 24;
492 		*sample_count += (snd_pcm_uframes_t)rmh.stat[1];
493 	}
494 	snd_printdd("PIPE_SAMPLE_COUNT = %lx\n", *sample_count);
495 	return err;
496 }
497 #endif
498 
499 static inline int pcxhr_stream_scheduled_get_pipe(struct pcxhr_stream *stream,
500 						  struct pcxhr_pipe **pipe)
501 {
502 	if (stream->status == PCXHR_STREAM_STATUS_SCHEDULE_RUN) {
503 		*pipe = stream->pipe;
504 		return 1;
505 	}
506 	return 0;
507 }
508 
509 static void pcxhr_trigger_tasklet(unsigned long arg)
510 {
511 	unsigned long flags;
512 	int i, j, err;
513 	struct pcxhr_pipe *pipe;
514 	struct snd_pcxhr *chip;
515 	struct pcxhr_mgr *mgr = (struct pcxhr_mgr*)(arg);
516 	int capture_mask = 0;
517 	int playback_mask = 0;
518 
519 #ifdef CONFIG_SND_DEBUG_DETECT
520 	struct timeval my_tv1, my_tv2;
521 	do_gettimeofday(&my_tv1);
522 #endif
523 	mutex_lock(&mgr->setup_mutex);
524 
525 	/* check the pipes concerned and build pipe_array */
526 	for (i = 0; i < mgr->num_cards; i++) {
527 		chip = mgr->chip[i];
528 		for (j = 0; j < chip->nb_streams_capt; j++) {
529 			if (pcxhr_stream_scheduled_get_pipe(&chip->capture_stream[j], &pipe))
530 				capture_mask |= (1 << pipe->first_audio);
531 		}
532 		for (j = 0; j < chip->nb_streams_play; j++) {
533 			if (pcxhr_stream_scheduled_get_pipe(&chip->playback_stream[j], &pipe)) {
534 				playback_mask |= (1 << pipe->first_audio);
535 				break;	/* add only once, as all playback streams of
536 					 * one chip use the same pipe
537 					 */
538 			}
539 		}
540 	}
541 	if (capture_mask == 0 && playback_mask == 0) {
542 		mutex_unlock(&mgr->setup_mutex);
543 		snd_printk(KERN_ERR "pcxhr_trigger_tasklet : no pipes\n");
544 		return;
545 	}
546 
547 	snd_printdd("pcxhr_trigger_tasklet : playback_mask=%x capture_mask=%x\n",
548 		    playback_mask, capture_mask);
549 
550 	/* synchronous stop of all the pipes concerned */
551 	err = pcxhr_set_pipe_state(mgr,  playback_mask, capture_mask, 0);
552 	if (err) {
553 		mutex_unlock(&mgr->setup_mutex);
554 		snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error stop pipes (P%x C%x)\n",
555 			   playback_mask, capture_mask);
556 		return;
557 	}
558 
559 	/* unfortunately the dsp lost format and buffer info with the stop pipe */
560 	for (i = 0; i < mgr->num_cards; i++) {
561 		struct pcxhr_stream *stream;
562 		chip = mgr->chip[i];
563 		for (j = 0; j < chip->nb_streams_capt; j++) {
564 			stream = &chip->capture_stream[j];
565 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
566 				err = pcxhr_set_format(stream);
567 				err = pcxhr_update_r_buffer(stream);
568 			}
569 		}
570 		for (j = 0; j < chip->nb_streams_play; j++) {
571 			stream = &chip->playback_stream[j];
572 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe)) {
573 				err = pcxhr_set_format(stream);
574 				err = pcxhr_update_r_buffer(stream);
575 			}
576 		}
577 	}
578 	/* start all the streams */
579 	for (i = 0; i < mgr->num_cards; i++) {
580 		struct pcxhr_stream *stream;
581 		chip = mgr->chip[i];
582 		for (j = 0; j < chip->nb_streams_capt; j++) {
583 			stream = &chip->capture_stream[j];
584 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
585 				err = pcxhr_set_stream_state(stream);
586 		}
587 		for (j = 0; j < chip->nb_streams_play; j++) {
588 			stream = &chip->playback_stream[j];
589 			if (pcxhr_stream_scheduled_get_pipe(stream, &pipe))
590 				err = pcxhr_set_stream_state(stream);
591 		}
592 	}
593 
594 	/* synchronous start of all the pipes concerned */
595 	err = pcxhr_set_pipe_state(mgr, playback_mask, capture_mask, 1);
596 	if (err) {
597 		mutex_unlock(&mgr->setup_mutex);
598 		snd_printk(KERN_ERR "pcxhr_trigger_tasklet : error start pipes (P%x C%x)\n",
599 			   playback_mask, capture_mask);
600 		return;
601 	}
602 
603 	/* put the streams into the running state now (increment pointer by interrupt) */
604 	spin_lock_irqsave(&mgr->lock, flags);
605 	for ( i =0; i < mgr->num_cards; i++) {
606 		struct pcxhr_stream *stream;
607 		chip = mgr->chip[i];
608 		for(j = 0; j < chip->nb_streams_capt; j++) {
609 			stream = &chip->capture_stream[j];
610 			if(stream->status == PCXHR_STREAM_STATUS_STARTED)
611 				stream->status = PCXHR_STREAM_STATUS_RUNNING;
612 		}
613 		for (j = 0; j < chip->nb_streams_play; j++) {
614 			stream = &chip->playback_stream[j];
615 			if (stream->status == PCXHR_STREAM_STATUS_STARTED) {
616 				/* playback will already have advanced ! */
617 				stream->timer_period_frag += PCXHR_GRANULARITY;
618 				stream->status = PCXHR_STREAM_STATUS_RUNNING;
619 			}
620 		}
621 	}
622 	spin_unlock_irqrestore(&mgr->lock, flags);
623 
624 	mutex_unlock(&mgr->setup_mutex);
625 
626 #ifdef CONFIG_SND_DEBUG_DETECT
627 	do_gettimeofday(&my_tv2);
628 	snd_printdd("***TRIGGER TASKLET*** TIME = %ld (err = %x)\n",
629 		    my_tv2.tv_usec - my_tv1.tv_usec, err);
630 #endif
631 }
632 
633 
634 /*
635  *  trigger callback
636  */
637 static int pcxhr_trigger(struct snd_pcm_substream *subs, int cmd)
638 {
639 	struct pcxhr_stream *stream;
640 	struct snd_pcm_substream *s;
641 
642 	switch (cmd) {
643 	case SNDRV_PCM_TRIGGER_START:
644 		snd_printdd("SNDRV_PCM_TRIGGER_START\n");
645 		if (snd_pcm_stream_linked(subs)) {
646 			struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
647 			snd_pcm_group_for_each_entry(s, subs) {
648 				if (snd_pcm_substream_chip(s) != chip)
649 					continue;
650 				stream = s->runtime->private_data;
651 				stream->status =
652 					PCXHR_STREAM_STATUS_SCHEDULE_RUN;
653 				snd_pcm_trigger_done(s, subs);
654 			}
655 			tasklet_hi_schedule(&chip->mgr->trigger_taskq);
656 		} else {
657 			stream = subs->runtime->private_data;
658 			snd_printdd("Only one Substream %c %d\n",
659 				    stream->pipe->is_capture ? 'C' : 'P',
660 				    stream->pipe->first_audio);
661 			if (pcxhr_set_format(stream))
662 				return -EINVAL;
663 			if (pcxhr_update_r_buffer(stream))
664 				return -EINVAL;
665 
666 			stream->status = PCXHR_STREAM_STATUS_SCHEDULE_RUN;
667 			if (pcxhr_set_stream_state(stream))
668 				return -EINVAL;
669 			stream->status = PCXHR_STREAM_STATUS_RUNNING;
670 		}
671 		break;
672 	case SNDRV_PCM_TRIGGER_STOP:
673 		snd_printdd("SNDRV_PCM_TRIGGER_STOP\n");
674 		snd_pcm_group_for_each_entry(s, subs) {
675 			stream = s->runtime->private_data;
676 			stream->status = PCXHR_STREAM_STATUS_SCHEDULE_STOP;
677 			if (pcxhr_set_stream_state(stream))
678 				return -EINVAL;
679 			snd_pcm_trigger_done(s, subs);
680 		}
681 		break;
682 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
683 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
684 		/* TODO */
685 	default:
686 		return -EINVAL;
687 	}
688 	return 0;
689 }
690 
691 
692 static int pcxhr_hardware_timer(struct pcxhr_mgr *mgr, int start)
693 {
694 	struct pcxhr_rmh rmh;
695 	int err;
696 
697 	pcxhr_init_rmh(&rmh, CMD_SET_TIMER_INTERRUPT);
698 	if (start) {
699 		mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;	/* last dsp time invalid */
700 		rmh.cmd[0] |= PCXHR_GRANULARITY;
701 	}
702 	err = pcxhr_send_msg(mgr, &rmh);
703 	if (err < 0)
704 		snd_printk(KERN_ERR "error pcxhr_hardware_timer err(%x)\n", err);
705 	return err;
706 }
707 
708 /*
709  *  prepare callback for all pcms
710  */
711 static int pcxhr_prepare(struct snd_pcm_substream *subs)
712 {
713 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
714 	struct pcxhr_mgr *mgr = chip->mgr;
715 	/*
716 	struct pcxhr_stream *stream = (pcxhr_stream_t*)subs->runtime->private_data;
717 	*/
718 	int err = 0;
719 
720 	snd_printdd("pcxhr_prepare : period_size(%lx) periods(%x) buffer_size(%lx)\n",
721 		    subs->runtime->period_size, subs->runtime->periods,
722 		    subs->runtime->buffer_size);
723 
724 	/*
725 	if(subs->runtime->period_size <= PCXHR_GRANULARITY) {
726 		snd_printk(KERN_ERR "pcxhr_prepare : error period_size too small (%x)\n",
727 			   (unsigned int)subs->runtime->period_size);
728 		return -EINVAL;
729 	}
730 	*/
731 
732 	mutex_lock(&mgr->setup_mutex);
733 
734 	do {
735 		/* if the stream was stopped before, format and buffer were reset */
736 		/*
737 		if(stream->status == PCXHR_STREAM_STATUS_STOPPED) {
738 			err = pcxhr_set_format(stream);
739 			if(err) break;
740 			err = pcxhr_update_r_buffer(stream);
741 			if(err) break;
742 		}
743 		*/
744 
745 		/* only the first stream can choose the sample rate */
746 		/* the further opened streams will be limited to its frequency (see open) */
747 		/* set the clock only once (first stream) */
748 		if (mgr->sample_rate != subs->runtime->rate) {
749 			err = pcxhr_set_clock(mgr, subs->runtime->rate);
750 			if (err)
751 				break;
752 			if (mgr->sample_rate == 0)
753 				/* start the DSP-timer */
754 				err = pcxhr_hardware_timer(mgr, 1);
755 			mgr->sample_rate = subs->runtime->rate;
756 		}
757 	} while(0);	/* do only once (so we can use break instead of goto) */
758 
759 	mutex_unlock(&mgr->setup_mutex);
760 
761 	return err;
762 }
763 
764 
765 /*
766  *  HW_PARAMS callback for all pcms
767  */
768 static int pcxhr_hw_params(struct snd_pcm_substream *subs,
769 			   struct snd_pcm_hw_params *hw)
770 {
771 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
772 	struct pcxhr_mgr *mgr = chip->mgr;
773 	struct pcxhr_stream *stream = subs->runtime->private_data;
774 	snd_pcm_format_t format;
775 	int err;
776 	int channels;
777 
778 	/* set up channels */
779 	channels = params_channels(hw);
780 
781 	/*  set up format for the stream */
782 	format = params_format(hw);
783 
784 	mutex_lock(&mgr->setup_mutex);
785 
786 	stream->channels = channels;
787 	stream->format = format;
788 
789 	/* set the format to the board */
790 	/*
791 	err = pcxhr_set_format(stream);
792 	if(err) {
793 		mutex_unlock(&mgr->setup_mutex);
794 		return err;
795 	}
796 	*/
797 	/* allocate buffer */
798 	err = snd_pcm_lib_malloc_pages(subs, params_buffer_bytes(hw));
799 
800 	/*
801 	if (err > 0) {
802 		err = pcxhr_update_r_buffer(stream);
803 	}
804 	*/
805 	mutex_unlock(&mgr->setup_mutex);
806 
807 	return err;
808 }
809 
810 static int pcxhr_hw_free(struct snd_pcm_substream *subs)
811 {
812 	snd_pcm_lib_free_pages(subs);
813 	return 0;
814 }
815 
816 
817 /*
818  *  CONFIGURATION SPACE for all pcms, mono pcm must update channels_max
819  */
820 static struct snd_pcm_hardware pcxhr_caps =
821 {
822 	.info             = ( SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
823 			      SNDRV_PCM_INFO_MMAP_VALID | SNDRV_PCM_INFO_SYNC_START |
824 			      0 /*SNDRV_PCM_INFO_PAUSE*/),
825 	.formats	  = ( SNDRV_PCM_FMTBIT_U8 |
826 			      SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
827 			      SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_3BE |
828 			      SNDRV_PCM_FMTBIT_FLOAT_LE ),
829 	.rates            = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_192000,
830 	.rate_min         = 8000,
831 	.rate_max         = 192000,
832 	.channels_min     = 1,
833 	.channels_max     = 2,
834 	.buffer_bytes_max = (32*1024),
835 	/* 1 byte == 1 frame U8 mono (PCXHR_GRANULARITY is frames!) */
836 	.period_bytes_min = (2*PCXHR_GRANULARITY),
837 	.period_bytes_max = (16*1024),
838 	.periods_min      = 2,
839 	.periods_max      = (32*1024/PCXHR_GRANULARITY),
840 };
841 
842 
843 static int pcxhr_open(struct snd_pcm_substream *subs)
844 {
845 	struct snd_pcxhr       *chip = snd_pcm_substream_chip(subs);
846 	struct pcxhr_mgr       *mgr = chip->mgr;
847 	struct snd_pcm_runtime *runtime = subs->runtime;
848 	struct pcxhr_stream    *stream;
849 	int                 is_capture;
850 
851 	mutex_lock(&mgr->setup_mutex);
852 
853 	/* copy the struct snd_pcm_hardware struct */
854 	runtime->hw = pcxhr_caps;
855 
856 	if( subs->stream == SNDRV_PCM_STREAM_PLAYBACK ) {
857 		snd_printdd("pcxhr_open playback chip%d subs%d\n",
858 			    chip->chip_idx, subs->number);
859 		is_capture = 0;
860 		stream = &chip->playback_stream[subs->number];
861 	} else {
862 		snd_printdd("pcxhr_open capture chip%d subs%d\n",
863 			    chip->chip_idx, subs->number);
864 		is_capture = 1;
865 		if (mgr->mono_capture)
866 			runtime->hw.channels_max = 1;
867 		else
868 			runtime->hw.channels_min = 2;
869 		stream = &chip->capture_stream[subs->number];
870 	}
871 	if (stream->status != PCXHR_STREAM_STATUS_FREE){
872 		/* streams in use */
873 		snd_printk(KERN_ERR "pcxhr_open chip%d subs%d in use\n",
874 			   chip->chip_idx, subs->number);
875 		mutex_unlock(&mgr->setup_mutex);
876 		return -EBUSY;
877 	}
878 
879 	/* if a sample rate is already used or fixed by external clock,
880 	 * the stream cannot change
881 	 */
882 	if (mgr->sample_rate)
883 		runtime->hw.rate_min = runtime->hw.rate_max = mgr->sample_rate;
884 	else {
885 		if (mgr->use_clock_type != PCXHR_CLOCK_TYPE_INTERNAL) {
886 			int external_rate;
887 			if (pcxhr_get_external_clock(mgr, mgr->use_clock_type,
888 						     &external_rate) ||
889 			    external_rate == 0) {
890 				/* cannot detect the external clock rate */
891 				mutex_unlock(&mgr->setup_mutex);
892 				return -EBUSY;
893 			}
894 			runtime->hw.rate_min = runtime->hw.rate_max = external_rate;
895 		}
896 	}
897 
898 	stream->status      = PCXHR_STREAM_STATUS_OPEN;
899 	stream->substream   = subs;
900 	stream->channels    = 0; /* not configured yet */
901 
902 	runtime->private_data = stream;
903 
904 	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4);
905 	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 4);
906 
907 	snd_pcm_set_sync(subs);
908 
909 	mgr->ref_count_rate++;
910 
911 	mutex_unlock(&mgr->setup_mutex);
912 	return 0;
913 }
914 
915 
916 static int pcxhr_close(struct snd_pcm_substream *subs)
917 {
918 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
919 	struct pcxhr_mgr *mgr = chip->mgr;
920 	struct pcxhr_stream *stream = subs->runtime->private_data;
921 
922 	mutex_lock(&mgr->setup_mutex);
923 
924 	snd_printdd("pcxhr_close chip%d subs%d\n", chip->chip_idx, subs->number);
925 
926 	/* sample rate released */
927 	if (--mgr->ref_count_rate == 0) {
928 		mgr->sample_rate = 0;		/* the sample rate is no more locked */
929 		pcxhr_hardware_timer(mgr, 0);	/* stop the DSP-timer */
930 	}
931 
932 	stream->status    = PCXHR_STREAM_STATUS_FREE;
933 	stream->substream = NULL;
934 
935 	mutex_unlock(&mgr->setup_mutex);
936 
937 	return 0;
938 }
939 
940 
941 static snd_pcm_uframes_t pcxhr_stream_pointer(struct snd_pcm_substream *subs)
942 {
943 	unsigned long flags;
944 	u_int32_t timer_period_frag;
945 	int timer_buf_periods;
946 	struct snd_pcxhr *chip = snd_pcm_substream_chip(subs);
947 	struct snd_pcm_runtime *runtime = subs->runtime;
948 	struct pcxhr_stream *stream  = runtime->private_data;
949 
950 	spin_lock_irqsave(&chip->mgr->lock, flags);
951 
952 	/* get the period fragment and the nb of periods in the buffer */
953 	timer_period_frag = stream->timer_period_frag;
954 	timer_buf_periods = stream->timer_buf_periods;
955 
956 	spin_unlock_irqrestore(&chip->mgr->lock, flags);
957 
958 	return (snd_pcm_uframes_t)((timer_buf_periods * runtime->period_size) +
959 				   timer_period_frag);
960 }
961 
962 
963 static struct snd_pcm_ops pcxhr_ops = {
964 	.open      = pcxhr_open,
965 	.close     = pcxhr_close,
966 	.ioctl     = snd_pcm_lib_ioctl,
967 	.prepare   = pcxhr_prepare,
968 	.hw_params = pcxhr_hw_params,
969 	.hw_free   = pcxhr_hw_free,
970 	.trigger   = pcxhr_trigger,
971 	.pointer   = pcxhr_stream_pointer,
972 };
973 
974 /*
975  */
976 int pcxhr_create_pcm(struct snd_pcxhr *chip)
977 {
978 	int err;
979 	struct snd_pcm *pcm;
980 	char name[32];
981 
982 	sprintf(name, "pcxhr %d", chip->chip_idx);
983 	if ((err = snd_pcm_new(chip->card, name, 0,
984 			       chip->nb_streams_play,
985 			       chip->nb_streams_capt, &pcm)) < 0) {
986 		snd_printk(KERN_ERR "cannot create pcm %s\n", name);
987 		return err;
988 	}
989 	pcm->private_data = chip;
990 
991 	if (chip->nb_streams_play)
992 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &pcxhr_ops);
993 	if (chip->nb_streams_capt)
994 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &pcxhr_ops);
995 
996 	pcm->info_flags = 0;
997 	strcpy(pcm->name, name);
998 
999 	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1000 					      snd_dma_pci_data(chip->mgr->pci),
1001 					      32*1024, 32*1024);
1002 	chip->pcm = pcm;
1003 	return 0;
1004 }
1005 
1006 static int pcxhr_chip_free(struct snd_pcxhr *chip)
1007 {
1008 	kfree(chip);
1009 	return 0;
1010 }
1011 
1012 static int pcxhr_chip_dev_free(struct snd_device *device)
1013 {
1014 	struct snd_pcxhr *chip = device->device_data;
1015 	return pcxhr_chip_free(chip);
1016 }
1017 
1018 
1019 /*
1020  */
1021 static int __devinit pcxhr_create(struct pcxhr_mgr *mgr, struct snd_card *card, int idx)
1022 {
1023 	int err;
1024 	struct snd_pcxhr *chip;
1025 	static struct snd_device_ops ops = {
1026 		.dev_free = pcxhr_chip_dev_free,
1027 	};
1028 
1029 	mgr->chip[idx] = chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1030 	if (! chip) {
1031 		snd_printk(KERN_ERR "cannot allocate chip\n");
1032 		return -ENOMEM;
1033 	}
1034 
1035 	chip->card = card;
1036 	chip->chip_idx = idx;
1037 	chip->mgr = mgr;
1038 
1039 	if (idx < mgr->playback_chips)
1040 		/* stereo or mono streams */
1041 		chip->nb_streams_play = PCXHR_PLAYBACK_STREAMS;
1042 
1043 	if (idx < mgr->capture_chips) {
1044 		if (mgr->mono_capture)
1045 			chip->nb_streams_capt = 2;	/* 2 mono streams (left+right) */
1046 		else
1047 			chip->nb_streams_capt = 1;	/* or 1 stereo stream */
1048 	}
1049 
1050 	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1051 		pcxhr_chip_free(chip);
1052 		return err;
1053 	}
1054 
1055 	snd_card_set_dev(card, &mgr->pci->dev);
1056 
1057 	return 0;
1058 }
1059 
1060 /* proc interface */
1061 static void pcxhr_proc_info(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1062 {
1063 	struct snd_pcxhr *chip = entry->private_data;
1064 	struct pcxhr_mgr *mgr = chip->mgr;
1065 
1066 	snd_iprintf(buffer, "\n%s\n", mgr->longname);
1067 
1068 	/* stats available when embedded DSP is running */
1069 	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1070 		struct pcxhr_rmh rmh;
1071 		short ver_maj = (mgr->dsp_version >> 16) & 0xff;
1072 		short ver_min = (mgr->dsp_version >> 8) & 0xff;
1073 		short ver_build = mgr->dsp_version & 0xff;
1074 		snd_iprintf(buffer, "module version %s\n", PCXHR_DRIVER_VERSION_STRING);
1075 		snd_iprintf(buffer, "dsp version %d.%d.%d\n", ver_maj, ver_min, ver_build);
1076 		if (mgr->board_has_analog)
1077 			snd_iprintf(buffer, "analog io available\n");
1078 		else
1079 			snd_iprintf(buffer, "digital only board\n");
1080 
1081 		/* calc cpu load of the dsp */
1082 		pcxhr_init_rmh(&rmh, CMD_GET_DSP_RESOURCES);
1083 		if( ! pcxhr_send_msg(mgr, &rmh) ) {
1084 			int cur = rmh.stat[0];
1085 			int ref = rmh.stat[1];
1086 			if (ref > 0) {
1087 				if (mgr->sample_rate_real != 0 &&
1088 				    mgr->sample_rate_real != 48000) {
1089 					ref = (ref * 48000) / mgr->sample_rate_real;
1090 					if (mgr->sample_rate_real >= PCXHR_IRQ_TIMER_FREQ)
1091 						ref *= 2;
1092 				}
1093 				cur = 100 - (100 * cur) / ref;
1094 				snd_iprintf(buffer, "cpu load    %d%%\n", cur);
1095 				snd_iprintf(buffer, "buffer pool %d/%d kWords\n",
1096 					    rmh.stat[2], rmh.stat[3]);
1097 			}
1098 		}
1099 		snd_iprintf(buffer, "dma granularity : %d\n", PCXHR_GRANULARITY);
1100 		snd_iprintf(buffer, "dsp time errors : %d\n", mgr->dsp_time_err);
1101 		snd_iprintf(buffer, "dsp async pipe xrun errors : %d\n",
1102 			    mgr->async_err_pipe_xrun);
1103 		snd_iprintf(buffer, "dsp async stream xrun errors : %d\n",
1104 			    mgr->async_err_stream_xrun);
1105 		snd_iprintf(buffer, "dsp async last other error : %x\n",
1106 			    mgr->async_err_other_last);
1107 		/* debug zone dsp */
1108 		rmh.cmd[0] = 0x4200 + PCXHR_SIZE_MAX_STATUS;
1109 		rmh.cmd_len = 1;
1110 		rmh.stat_len = PCXHR_SIZE_MAX_STATUS;
1111 		rmh.dsp_stat = 0;
1112 		rmh.cmd_idx = CMD_LAST_INDEX;
1113 		if( ! pcxhr_send_msg(mgr, &rmh) ) {
1114 			int i;
1115 			for (i = 0; i < rmh.stat_len; i++)
1116 				snd_iprintf(buffer, "debug[%02d] = %06x\n", i,  rmh.stat[i]);
1117 		}
1118 	} else
1119 		snd_iprintf(buffer, "no firmware loaded\n");
1120 	snd_iprintf(buffer, "\n");
1121 }
1122 static void pcxhr_proc_sync(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1123 {
1124 	struct snd_pcxhr *chip = entry->private_data;
1125 	struct pcxhr_mgr *mgr = chip->mgr;
1126 	static char *texts[7] = {
1127 		"Internal", "Word", "AES Sync", "AES 1", "AES 2", "AES 3", "AES 4"
1128 	};
1129 
1130 	snd_iprintf(buffer, "\n%s\n", mgr->longname);
1131 	snd_iprintf(buffer, "Current Sample Clock\t: %s\n", texts[mgr->cur_clock_type]);
1132 	snd_iprintf(buffer, "Current Sample Rate\t= %d\n", mgr->sample_rate_real);
1133 
1134 	/* commands available when embedded DSP is running */
1135 	if (mgr->dsp_loaded & (1 << PCXHR_FIRMWARE_DSP_MAIN_INDEX)) {
1136 		int i, err, sample_rate;
1137 		for (i = PCXHR_CLOCK_TYPE_WORD_CLOCK; i< (3 + mgr->capture_chips); i++) {
1138 			err = pcxhr_get_external_clock(mgr, i, &sample_rate);
1139 			if (err)
1140 				break;
1141 			snd_iprintf(buffer, "%s Clock\t\t= %d\n", texts[i], sample_rate);
1142 		}
1143 	} else
1144 		snd_iprintf(buffer, "no firmware loaded\n");
1145 	snd_iprintf(buffer, "\n");
1146 }
1147 
1148 static void __devinit pcxhr_proc_init(struct snd_pcxhr *chip)
1149 {
1150 	struct snd_info_entry *entry;
1151 
1152 	if (! snd_card_proc_new(chip->card, "info", &entry))
1153 		snd_info_set_text_ops(entry, chip, pcxhr_proc_info);
1154 	if (! snd_card_proc_new(chip->card, "sync", &entry))
1155 		snd_info_set_text_ops(entry, chip, pcxhr_proc_sync);
1156 }
1157 /* end of proc interface */
1158 
1159 /*
1160  * release all the cards assigned to a manager instance
1161  */
1162 static int pcxhr_free(struct pcxhr_mgr *mgr)
1163 {
1164 	unsigned int i;
1165 
1166 	for (i = 0; i < mgr->num_cards; i++) {
1167 		if (mgr->chip[i])
1168 			snd_card_free(mgr->chip[i]->card);
1169 	}
1170 
1171 	/* reset board if some firmware was loaded */
1172 	if(mgr->dsp_loaded) {
1173 		pcxhr_reset_board(mgr);
1174 		snd_printdd("reset pcxhr !\n");
1175 	}
1176 
1177 	/* release irq  */
1178 	if (mgr->irq >= 0)
1179 		free_irq(mgr->irq, mgr);
1180 
1181 	pci_release_regions(mgr->pci);
1182 
1183 	/* free hostport purgebuffer */
1184 	if (mgr->hostport.area) {
1185 		snd_dma_free_pages(&mgr->hostport);
1186 		mgr->hostport.area = NULL;
1187 	}
1188 
1189 	kfree(mgr->prmh);
1190 
1191 	pci_disable_device(mgr->pci);
1192 	kfree(mgr);
1193 	return 0;
1194 }
1195 
1196 /*
1197  *    probe function - creates the card manager
1198  */
1199 static int __devinit pcxhr_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1200 {
1201 	static int dev;
1202 	struct pcxhr_mgr *mgr;
1203 	unsigned int i;
1204 	int err;
1205 	size_t size;
1206 	char *card_name;
1207 
1208 	if (dev >= SNDRV_CARDS)
1209 		return -ENODEV;
1210 	if (! enable[dev]) {
1211 		dev++;
1212 		return -ENOENT;
1213 	}
1214 
1215 	/* enable PCI device */
1216 	if ((err = pci_enable_device(pci)) < 0)
1217 		return err;
1218 	pci_set_master(pci);
1219 
1220 	/* check if we can restrict PCI DMA transfers to 32 bits */
1221 	if (pci_set_dma_mask(pci, DMA_32BIT_MASK) < 0) {
1222 		snd_printk(KERN_ERR "architecture does not support 32bit PCI busmaster DMA\n");
1223 		pci_disable_device(pci);
1224 		return -ENXIO;
1225 	}
1226 
1227 	/* alloc card manager */
1228 	mgr = kzalloc(sizeof(*mgr), GFP_KERNEL);
1229 	if (! mgr) {
1230 		pci_disable_device(pci);
1231 		return -ENOMEM;
1232 	}
1233 
1234 	snd_assert(pci_id->driver_data < PCI_ID_LAST, return -ENODEV);
1235 	card_name = pcxhr_board_params[pci_id->driver_data].board_name;
1236 	mgr->playback_chips = pcxhr_board_params[pci_id->driver_data].playback_chips;
1237 	mgr->capture_chips  = pcxhr_board_params[pci_id->driver_data].capture_chips;
1238 	mgr->firmware_num  = pcxhr_board_params[pci_id->driver_data].firmware_num;
1239 	mgr->mono_capture = mono[dev];
1240 
1241 	/* resource assignment */
1242 	if ((err = pci_request_regions(pci, card_name)) < 0) {
1243 		kfree(mgr);
1244 		pci_disable_device(pci);
1245 		return err;
1246 	}
1247 	for (i = 0; i < 3; i++)
1248 		mgr->port[i] = pci_resource_start(pci, i);
1249 
1250 	mgr->pci = pci;
1251 	mgr->irq = -1;
1252 
1253 	if (request_irq(pci->irq, pcxhr_interrupt, IRQF_SHARED,
1254 			card_name, mgr)) {
1255 		snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1256 		pcxhr_free(mgr);
1257 		return -EBUSY;
1258 	}
1259 	mgr->irq = pci->irq;
1260 
1261 	sprintf(mgr->shortname, "Digigram %s", card_name);
1262 	sprintf(mgr->longname, "%s at 0x%lx & 0x%lx, 0x%lx irq %i", mgr->shortname,
1263 		mgr->port[0], mgr->port[1], mgr->port[2], mgr->irq);
1264 
1265 	/* ISR spinlock  */
1266 	spin_lock_init(&mgr->lock);
1267 	spin_lock_init(&mgr->msg_lock);
1268 
1269 	/* init setup mutex*/
1270 	mutex_init(&mgr->setup_mutex);
1271 
1272 	/* init taslket */
1273 	tasklet_init(&mgr->msg_taskq, pcxhr_msg_tasklet, (unsigned long) mgr);
1274 	tasklet_init(&mgr->trigger_taskq, pcxhr_trigger_tasklet, (unsigned long) mgr);
1275 	mgr->prmh = kmalloc(sizeof(*mgr->prmh) +
1276 			    sizeof(u32) * (PCXHR_SIZE_MAX_LONG_STATUS - PCXHR_SIZE_MAX_STATUS),
1277 			    GFP_KERNEL);
1278 	if (! mgr->prmh) {
1279 		pcxhr_free(mgr);
1280 		return -ENOMEM;
1281 	}
1282 
1283 	for (i=0; i < PCXHR_MAX_CARDS; i++) {
1284 		struct snd_card *card;
1285 		char tmpid[16];
1286 		int idx;
1287 
1288 		if (i >= max(mgr->playback_chips, mgr->capture_chips))
1289 			break;
1290 		mgr->num_cards++;
1291 
1292 		if (index[dev] < 0)
1293 			idx = index[dev];
1294 		else
1295 			idx = index[dev] + i;
1296 
1297 		snprintf(tmpid, sizeof(tmpid), "%s-%d", id[dev] ? id[dev] : card_name, i);
1298 		card = snd_card_new(idx, tmpid, THIS_MODULE, 0);
1299 
1300 		if (! card) {
1301 			snd_printk(KERN_ERR "cannot allocate the card %d\n", i);
1302 			pcxhr_free(mgr);
1303 			return -ENOMEM;
1304 		}
1305 
1306 		strcpy(card->driver, DRIVER_NAME);
1307 		sprintf(card->shortname, "%s [PCM #%d]", mgr->shortname, i);
1308 		sprintf(card->longname, "%s [PCM #%d]", mgr->longname, i);
1309 
1310 		if ((err = pcxhr_create(mgr, card, i)) < 0) {
1311 			pcxhr_free(mgr);
1312 			return err;
1313 		}
1314 
1315 		if (i == 0)
1316 			/* init proc interface only for chip0 */
1317 			pcxhr_proc_init(mgr->chip[i]);
1318 
1319 		if ((err = snd_card_register(card)) < 0) {
1320 			pcxhr_free(mgr);
1321 			return err;
1322 		}
1323 	}
1324 
1325 	/* create hostport purgebuffer */
1326 	size = PAGE_ALIGN(sizeof(struct pcxhr_hostport));
1327 	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1328 				size, &mgr->hostport) < 0) {
1329 		pcxhr_free(mgr);
1330 		return -ENOMEM;
1331 	}
1332 	/* init purgebuffer */
1333 	memset(mgr->hostport.area, 0, size);
1334 
1335 	/* create a DSP loader */
1336 	err = pcxhr_setup_firmware(mgr);
1337 	if (err < 0) {
1338 		pcxhr_free(mgr);
1339 		return err;
1340 	}
1341 
1342 	pci_set_drvdata(pci, mgr);
1343 	dev++;
1344 	return 0;
1345 }
1346 
1347 static void __devexit pcxhr_remove(struct pci_dev *pci)
1348 {
1349 	pcxhr_free(pci_get_drvdata(pci));
1350 	pci_set_drvdata(pci, NULL);
1351 }
1352 
1353 static struct pci_driver driver = {
1354 	.name = "Digigram pcxhr",
1355 	.id_table = pcxhr_ids,
1356 	.probe = pcxhr_probe,
1357 	.remove = __devexit_p(pcxhr_remove),
1358 };
1359 
1360 static int __init pcxhr_module_init(void)
1361 {
1362 	return pci_register_driver(&driver);
1363 }
1364 
1365 static void __exit pcxhr_module_exit(void)
1366 {
1367 	pci_unregister_driver(&driver);
1368 }
1369 
1370 module_init(pcxhr_module_init)
1371 module_exit(pcxhr_module_exit)
1372