1 #ifndef OXYGEN_REGS_H_INCLUDED 2 #define OXYGEN_REGS_H_INCLUDED 3 4 /* recording channel A */ 5 #define OXYGEN_DMA_A_ADDRESS 0x00 /* 32-bit base address */ 6 #define OXYGEN_DMA_A_COUNT 0x04 /* buffer counter (dwords) */ 7 #define OXYGEN_DMA_A_TCOUNT 0x06 /* interrupt counter (dwords) */ 8 9 /* recording channel B */ 10 #define OXYGEN_DMA_B_ADDRESS 0x08 11 #define OXYGEN_DMA_B_COUNT 0x0c 12 #define OXYGEN_DMA_B_TCOUNT 0x0e 13 14 /* recording channel C */ 15 #define OXYGEN_DMA_C_ADDRESS 0x10 16 #define OXYGEN_DMA_C_COUNT 0x14 17 #define OXYGEN_DMA_C_TCOUNT 0x16 18 19 /* SPDIF playback channel */ 20 #define OXYGEN_DMA_SPDIF_ADDRESS 0x18 21 #define OXYGEN_DMA_SPDIF_COUNT 0x1c 22 #define OXYGEN_DMA_SPDIF_TCOUNT 0x1e 23 24 /* multichannel playback channel */ 25 #define OXYGEN_DMA_MULTICH_ADDRESS 0x20 26 #define OXYGEN_DMA_MULTICH_COUNT 0x24 /* 24 bits */ 27 #define OXYGEN_DMA_MULTICH_TCOUNT 0x28 /* 24 bits */ 28 29 /* AC'97 (front panel) playback channel */ 30 #define OXYGEN_DMA_AC97_ADDRESS 0x30 31 #define OXYGEN_DMA_AC97_COUNT 0x34 32 #define OXYGEN_DMA_AC97_TCOUNT 0x36 33 34 /* all registers 0x00..0x36 return current position on read */ 35 36 #define OXYGEN_DMA_STATUS 0x40 /* 1 = running, 0 = stop */ 37 #define OXYGEN_CHANNEL_A 0x01 38 #define OXYGEN_CHANNEL_B 0x02 39 #define OXYGEN_CHANNEL_C 0x04 40 #define OXYGEN_CHANNEL_SPDIF 0x08 41 #define OXYGEN_CHANNEL_MULTICH 0x10 42 #define OXYGEN_CHANNEL_AC97 0x20 43 44 #define OXYGEN_DMA_PAUSE 0x41 /* 1 = pause */ 45 /* OXYGEN_CHANNEL_* */ 46 47 #define OXYGEN_DMA_RESET 0x42 48 /* OXYGEN_CHANNEL_* */ 49 50 #define OXYGEN_PLAY_CHANNELS 0x43 51 #define OXYGEN_PLAY_CHANNELS_MASK 0x03 52 #define OXYGEN_PLAY_CHANNELS_2 0x00 53 #define OXYGEN_PLAY_CHANNELS_4 0x01 54 #define OXYGEN_PLAY_CHANNELS_6 0x02 55 #define OXYGEN_PLAY_CHANNELS_8 0x03 56 #define OXYGEN_DMA_A_BURST_MASK 0x04 57 #define OXYGEN_DMA_A_BURST_8 0x00 /* dwords */ 58 #define OXYGEN_DMA_A_BURST_16 0x04 59 #define OXYGEN_DMA_MULTICH_BURST_MASK 0x08 60 #define OXYGEN_DMA_MULTICH_BURST_8 0x00 61 #define OXYGEN_DMA_MULTICH_BURST_16 0x08 62 63 #define OXYGEN_INTERRUPT_MASK 0x44 64 /* OXYGEN_CHANNEL_* */ 65 #define OXYGEN_INT_SPDIF_IN_DETECT 0x0100 66 #define OXYGEN_INT_MCU 0x0200 67 #define OXYGEN_INT_2WIRE 0x0400 68 #define OXYGEN_INT_GPIO 0x0800 69 #define OXYGEN_INT_MCB 0x2000 70 #define OXYGEN_INT_AC97 0x4000 71 72 #define OXYGEN_INTERRUPT_STATUS 0x46 73 /* OXYGEN_CHANNEL_* amd OXYGEN_INT_* */ 74 #define OXYGEN_INT_MIDI 0x1000 75 76 #define OXYGEN_MISC 0x48 77 #define OXYGEN_MISC_WRITE_PCI_SUBID 0x01 78 #define OXYGEN_MISC_LATENCY_3F 0x02 79 #define OXYGEN_MISC_REC_C_FROM_SPDIF 0x04 80 #define OXYGEN_MISC_REC_B_FROM_AC97 0x08 81 #define OXYGEN_MISC_REC_A_FROM_MULTICH 0x10 82 #define OXYGEN_MISC_PCI_MEM_W_1_CLOCK 0x20 83 #define OXYGEN_MISC_MIDI 0x40 84 #define OXYGEN_MISC_CRYSTAL_MASK 0x80 85 #define OXYGEN_MISC_CRYSTAL_24576 0x00 86 #define OXYGEN_MISC_CRYSTAL_27 0x80 /* MHz */ 87 88 #define OXYGEN_REC_FORMAT 0x4a 89 #define OXYGEN_REC_FORMAT_A_MASK 0x03 90 #define OXYGEN_REC_FORMAT_A_SHIFT 0 91 #define OXYGEN_REC_FORMAT_B_MASK 0x0c 92 #define OXYGEN_REC_FORMAT_B_SHIFT 2 93 #define OXYGEN_REC_FORMAT_C_MASK 0x30 94 #define OXYGEN_REC_FORMAT_C_SHIFT 4 95 #define OXYGEN_FORMAT_16 0x00 96 #define OXYGEN_FORMAT_24 0x01 97 #define OXYGEN_FORMAT_32 0x02 98 99 #define OXYGEN_PLAY_FORMAT 0x4b 100 #define OXYGEN_SPDIF_FORMAT_MASK 0x03 101 #define OXYGEN_SPDIF_FORMAT_SHIFT 0 102 #define OXYGEN_MULTICH_FORMAT_MASK 0x0c 103 #define OXYGEN_MULTICH_FORMAT_SHIFT 2 104 /* OXYGEN_FORMAT_* */ 105 106 #define OXYGEN_REC_CHANNELS 0x4c 107 #define OXYGEN_REC_CHANNELS_MASK 0x07 108 #define OXYGEN_REC_CHANNELS_2_2_2 0x00 /* DMA A, B, C */ 109 #define OXYGEN_REC_CHANNELS_4_2_2 0x01 110 #define OXYGEN_REC_CHANNELS_6_0_2 0x02 111 #define OXYGEN_REC_CHANNELS_6_2_0 0x03 112 #define OXYGEN_REC_CHANNELS_8_0_0 0x04 113 114 #define OXYGEN_FUNCTION 0x50 115 #define OXYGEN_FUNCTION_CLOCK_MASK 0x01 116 #define OXYGEN_FUNCTION_CLOCK_PLL 0x00 117 #define OXYGEN_FUNCTION_CLOCK_CRYSTAL 0x01 118 #define OXYGEN_FUNCTION_RESET_CODEC 0x02 119 #define OXYGEN_FUNCTION_RESET_POL 0x04 120 #define OXYGEN_FUNCTION_PWDN 0x08 121 #define OXYGEN_FUNCTION_PWDN_EN 0x10 122 #define OXYGEN_FUNCTION_PWDN_POL 0x20 123 #define OXYGEN_FUNCTION_2WIRE_SPI_MASK 0x40 124 #define OXYGEN_FUNCTION_SPI 0x00 125 #define OXYGEN_FUNCTION_2WIRE 0x40 126 #define OXYGEN_FUNCTION_ENABLE_SPI_4_5 0x80 /* 0 = EEPROM */ 127 128 #define OXYGEN_I2S_MULTICH_FORMAT 0x60 129 #define OXYGEN_I2S_RATE_MASK 0x0007 /* LRCK */ 130 #define OXYGEN_RATE_32000 0x0000 131 #define OXYGEN_RATE_44100 0x0001 132 #define OXYGEN_RATE_48000 0x0002 133 #define OXYGEN_RATE_64000 0x0003 134 #define OXYGEN_RATE_88200 0x0004 135 #define OXYGEN_RATE_96000 0x0005 136 #define OXYGEN_RATE_176400 0x0006 137 #define OXYGEN_RATE_192000 0x0007 138 #define OXYGEN_I2S_FORMAT_MASK 0x0008 139 #define OXYGEN_I2S_FORMAT_I2S 0x0000 140 #define OXYGEN_I2S_FORMAT_LJUST 0x0008 141 #define OXYGEN_I2S_MCLK_MASK 0x0030 /* MCLK/LRCK */ 142 #define OXYGEN_I2S_MCLK_SHIFT 4 143 #define MCLK_128 0 144 #define MCLK_256 1 145 #define MCLK_512 2 146 #define OXYGEN_I2S_MCLK(f) (((f) & 3) << OXYGEN_I2S_MCLK_SHIFT) 147 #define OXYGEN_I2S_BITS_MASK 0x00c0 148 #define OXYGEN_I2S_BITS_16 0x0000 149 #define OXYGEN_I2S_BITS_20 0x0040 150 #define OXYGEN_I2S_BITS_24 0x0080 151 #define OXYGEN_I2S_BITS_32 0x00c0 152 #define OXYGEN_I2S_MASTER 0x0100 153 #define OXYGEN_I2S_BCLK_MASK 0x0600 /* BCLK/LRCK */ 154 #define OXYGEN_I2S_BCLK_64 0x0000 155 #define OXYGEN_I2S_BCLK_128 0x0200 156 #define OXYGEN_I2S_BCLK_256 0x0400 157 #define OXYGEN_I2S_MUTE_MCLK 0x0800 158 159 #define OXYGEN_I2S_A_FORMAT 0x62 160 #define OXYGEN_I2S_B_FORMAT 0x64 161 #define OXYGEN_I2S_C_FORMAT 0x66 162 /* like OXYGEN_I2S_MULTICH_FORMAT */ 163 164 #define OXYGEN_SPDIF_CONTROL 0x70 165 #define OXYGEN_SPDIF_OUT_ENABLE 0x00000002 166 #define OXYGEN_SPDIF_LOOPBACK 0x00000004 /* in to out */ 167 #define OXYGEN_SPDIF_SENSE_MASK 0x00000008 168 #define OXYGEN_SPDIF_LOCK_MASK 0x00000010 169 #define OXYGEN_SPDIF_RATE_MASK 0x00000020 170 #define OXYGEN_SPDIF_SPDVALID 0x00000040 171 #define OXYGEN_SPDIF_SENSE_PAR 0x00000200 172 #define OXYGEN_SPDIF_LOCK_PAR 0x00000400 173 #define OXYGEN_SPDIF_SENSE_STATUS 0x00000800 174 #define OXYGEN_SPDIF_LOCK_STATUS 0x00001000 175 #define OXYGEN_SPDIF_SENSE_INT 0x00002000 /* r/wc */ 176 #define OXYGEN_SPDIF_LOCK_INT 0x00004000 /* r/wc */ 177 #define OXYGEN_SPDIF_RATE_INT 0x00008000 /* r/wc */ 178 #define OXYGEN_SPDIF_IN_CLOCK_MASK 0x00010000 179 #define OXYGEN_SPDIF_IN_CLOCK_96 0x00000000 /* <= 96 kHz */ 180 #define OXYGEN_SPDIF_IN_CLOCK_192 0x00010000 /* > 96 kHz */ 181 #define OXYGEN_SPDIF_OUT_RATE_MASK 0x07000000 182 #define OXYGEN_SPDIF_OUT_RATE_SHIFT 24 183 /* OXYGEN_RATE_* << OXYGEN_SPDIF_OUT_RATE_SHIFT */ 184 185 #define OXYGEN_SPDIF_OUTPUT_BITS 0x74 186 #define OXYGEN_SPDIF_NONAUDIO 0x00000002 187 #define OXYGEN_SPDIF_C 0x00000004 188 #define OXYGEN_SPDIF_PREEMPHASIS 0x00000008 189 #define OXYGEN_SPDIF_CATEGORY_MASK 0x000007f0 190 #define OXYGEN_SPDIF_CATEGORY_SHIFT 4 191 #define OXYGEN_SPDIF_ORIGINAL 0x00000800 192 #define OXYGEN_SPDIF_CS_RATE_MASK 0x0000f000 193 #define OXYGEN_SPDIF_CS_RATE_SHIFT 12 194 #define OXYGEN_SPDIF_V 0x00010000 /* 0 = valid */ 195 196 #define OXYGEN_SPDIF_INPUT_BITS 0x78 197 /* 32 bits, IEC958_AES_* */ 198 199 #define OXYGEN_EEPROM_CONTROL 0x80 200 #define OXYGEN_EEPROM_ADDRESS_MASK 0x7f 201 #define OXYGEN_EEPROM_DIR_MASK 0x80 202 #define OXYGEN_EEPROM_DIR_READ 0x00 203 #define OXYGEN_EEPROM_DIR_WRITE 0x80 204 205 #define OXYGEN_EEPROM_STATUS 0x81 206 #define OXYGEN_EEPROM_VALID 0x40 207 #define OXYGEN_EEPROM_BUSY 0x80 208 209 #define OXYGEN_EEPROM_DATA 0x82 /* 16 bits */ 210 211 #define OXYGEN_2WIRE_CONTROL 0x90 212 #define OXYGEN_2WIRE_DIR_MASK 0x01 213 #define OXYGEN_2WIRE_DIR_WRITE 0x00 214 #define OXYGEN_2WIRE_DIR_READ 0x01 215 #define OXYGEN_2WIRE_ADDRESS_MASK 0xfe /* slave device address */ 216 #define OXYGEN_2WIRE_ADDRESS_SHIFT 1 217 218 #define OXYGEN_2WIRE_MAP 0x91 /* address, 8 bits */ 219 #define OXYGEN_2WIRE_DATA 0x92 /* data, 16 bits */ 220 221 #define OXYGEN_2WIRE_BUS_STATUS 0x94 222 #define OXYGEN_2WIRE_BUSY 0x0001 223 #define OXYGEN_2WIRE_LENGTH_MASK 0x0002 224 #define OXYGEN_2WIRE_LENGTH_8 0x0000 225 #define OXYGEN_2WIRE_LENGTH_16 0x0002 226 #define OXYGEN_2WIRE_MANUAL_READ 0x0004 /* 0 = auto read */ 227 #define OXYGEN_2WIRE_WRITE_MAP_ONLY 0x0008 228 #define OXYGEN_2WIRE_SLAVE_AD_MASK 0x0030 /* AD0, AD1 */ 229 #define OXYGEN_2WIRE_INTERRUPT_MASK 0x0040 /* 0 = int. if not responding */ 230 #define OXYGEN_2WIRE_SLAVE_NO_RESPONSE 0x0080 231 #define OXYGEN_2WIRE_SPEED_MASK 0x0100 232 #define OXYGEN_2WIRE_SPEED_STANDARD 0x0000 233 #define OXYGEN_2WIRE_SPEED_FAST 0x0100 234 #define OXYGEN_2WIRE_CLOCK_SYNC 0x0200 235 #define OXYGEN_2WIRE_BUS_RESET 0x0400 236 237 #define OXYGEN_SPI_CONTROL 0x98 238 #define OXYGEN_SPI_BUSY 0x01 /* read */ 239 #define OXYGEN_SPI_TRIGGER 0x01 /* write */ 240 #define OXYGEN_SPI_DATA_LENGTH_MASK 0x02 241 #define OXYGEN_SPI_DATA_LENGTH_2 0x00 242 #define OXYGEN_SPI_DATA_LENGTH_3 0x02 243 #define OXYGEN_SPI_CLOCK_MASK 0x0c 244 #define OXYGEN_SPI_CLOCK_160 0x00 /* ns */ 245 #define OXYGEN_SPI_CLOCK_320 0x04 246 #define OXYGEN_SPI_CLOCK_640 0x08 247 #define OXYGEN_SPI_CLOCK_1280 0x0c 248 #define OXYGEN_SPI_CODEC_MASK 0x70 /* 0..5 */ 249 #define OXYGEN_SPI_CODEC_SHIFT 4 250 #define OXYGEN_SPI_CEN_MASK 0x80 251 #define OXYGEN_SPI_CEN_LATCH_CLOCK_LO 0x00 252 #define OXYGEN_SPI_CEN_LATCH_CLOCK_HI 0x80 253 254 #define OXYGEN_SPI_DATA1 0x99 255 #define OXYGEN_SPI_DATA2 0x9a 256 #define OXYGEN_SPI_DATA3 0x9b 257 258 #define OXYGEN_MPU401 0xa0 259 260 #define OXYGEN_MPU401_CONTROL 0xa2 261 #define OXYGEN_MPU401_LOOPBACK 0x01 /* TXD to RXD */ 262 263 #define OXYGEN_GPI_DATA 0xa4 264 /* bits 0..5 = pin XGPI0..XGPI5 */ 265 266 #define OXYGEN_GPI_INTERRUPT_MASK 0xa5 267 /* bits 0..5, 1 = enable */ 268 269 #define OXYGEN_GPIO_DATA 0xa6 270 /* bits 0..9 */ 271 272 #define OXYGEN_GPIO_CONTROL 0xa8 273 /* bits 0..9, 0 = input, 1 = output */ 274 #define OXYGEN_GPIO1_XSLAVE_RDY 0x8000 275 276 #define OXYGEN_GPIO_INTERRUPT_MASK 0xaa 277 /* bits 0..9, 1 = enable */ 278 279 #define OXYGEN_DEVICE_SENSE 0xac 280 #define OXYGEN_HEAD_PHONE_DETECT 0x01 281 #define OXYGEN_HEAD_PHONE_MASK 0x06 282 #define OXYGEN_HEAD_PHONE_PASSIVE_SPK 0x00 283 #define OXYGEN_HEAD_PHONE_HP 0x02 284 #define OXYGEN_HEAD_PHONE_ACTIVE_SPK 0x04 285 286 #define OXYGEN_MCU_2WIRE_DATA 0xb0 287 288 #define OXYGEN_MCU_2WIRE_MAP 0xb2 289 290 #define OXYGEN_MCU_2WIRE_STATUS 0xb3 291 #define OXYGEN_MCU_2WIRE_BUSY 0x01 292 #define OXYGEN_MCU_2WIRE_LENGTH_MASK 0x06 293 #define OXYGEN_MCU_2WIRE_LENGTH_1 0x00 294 #define OXYGEN_MCU_2WIRE_LENGTH_2 0x02 295 #define OXYGEN_MCU_2WIRE_LENGTH_3 0x04 296 #define OXYGEN_MCU_2WIRE_WRITE 0x08 /* r/wc */ 297 #define OXYGEN_MCU_2WIRE_READ 0x10 /* r/wc */ 298 #define OXYGEN_MCU_2WIRE_DRV_XACT_FAIL 0x20 /* r/wc */ 299 #define OXYGEN_MCU_2WIRE_RESET 0x40 300 301 #define OXYGEN_MCU_2WIRE_CONTROL 0xb4 302 #define OXYGEN_MCU_2WIRE_DRV_ACK 0x01 303 #define OXYGEN_MCU_2WIRE_DRV_XACT 0x02 304 #define OXYGEN_MCU_2WIRE_INT_MASK 0x04 305 #define OXYGEN_MCU_2WIRE_SYNC_MASK 0x08 306 #define OXYGEN_MCU_2WIRE_SYNC_RDY_PIN 0x00 307 #define OXYGEN_MCU_2WIRE_SYNC_DATA 0x08 308 #define OXYGEN_MCU_2WIRE_ADDRESS_MASK 0x30 309 #define OXYGEN_MCU_2WIRE_ADDRESS_10 0x00 310 #define OXYGEN_MCU_2WIRE_ADDRESS_12 0x10 311 #define OXYGEN_MCU_2WIRE_ADDRESS_14 0x20 312 #define OXYGEN_MCU_2WIRE_ADDRESS_16 0x30 313 #define OXYGEN_MCU_2WIRE_INT_POL 0x40 314 #define OXYGEN_MCU_2WIRE_SYNC_ENABLE 0x80 315 316 #define OXYGEN_PLAY_ROUTING 0xc0 317 #define OXYGEN_PLAY_MUTE01 0x0001 318 #define OXYGEN_PLAY_MUTE23 0x0002 319 #define OXYGEN_PLAY_MUTE45 0x0004 320 #define OXYGEN_PLAY_MUTE67 0x0008 321 #define OXYGEN_PLAY_MUTE_MASK 0x000f 322 #define OXYGEN_PLAY_MULTICH_MASK 0x0010 323 #define OXYGEN_PLAY_MULTICH_I2S_DAC 0x0000 324 #define OXYGEN_PLAY_MULTICH_AC97 0x0010 325 #define OXYGEN_PLAY_SPDIF_MASK 0x00e0 326 #define OXYGEN_PLAY_SPDIF_SPDIF 0x0000 327 #define OXYGEN_PLAY_SPDIF_MULTICH_01 0x0020 328 #define OXYGEN_PLAY_SPDIF_MULTICH_23 0x0040 329 #define OXYGEN_PLAY_SPDIF_MULTICH_45 0x0060 330 #define OXYGEN_PLAY_SPDIF_MULTICH_67 0x0080 331 #define OXYGEN_PLAY_SPDIF_REC_A 0x00a0 332 #define OXYGEN_PLAY_SPDIF_REC_B 0x00c0 333 #define OXYGEN_PLAY_SPDIF_I2S_ADC_3 0x00e0 334 #define OXYGEN_PLAY_DAC0_SOURCE_MASK 0x0300 335 #define OXYGEN_PLAY_DAC0_SOURCE_SHIFT 8 336 #define OXYGEN_PLAY_DAC1_SOURCE_MASK 0x0c00 337 #define OXYGEN_PLAY_DAC1_SOURCE_SHIFT 10 338 #define OXYGEN_PLAY_DAC2_SOURCE_MASK 0x3000 339 #define OXYGEN_PLAY_DAC2_SOURCE_SHIFT 12 340 #define OXYGEN_PLAY_DAC3_SOURCE_MASK 0xc000 341 #define OXYGEN_PLAY_DAC3_SOURCE_SHIFT 14 342 343 #define OXYGEN_REC_ROUTING 0xc2 344 #define OXYGEN_MUTE_I2S_ADC_1 0x01 345 #define OXYGEN_MUTE_I2S_ADC_2 0x02 346 #define OXYGEN_MUTE_I2S_ADC_3 0x04 347 #define OXYGEN_REC_A_ROUTE_MASK 0x08 348 #define OXYGEN_REC_A_ROUTE_I2S_ADC_1 0x00 349 #define OXYGEN_REC_A_ROUTE_AC97_0 0x08 350 #define OXYGEN_REC_B_ROUTE_MASK 0x10 351 #define OXYGEN_REC_B_ROUTE_I2S_ADC_2 0x00 352 #define OXYGEN_REC_B_ROUTE_AC97_1 0x10 353 #define OXYGEN_REC_C_ROUTE_MASK 0x20 354 #define OXYGEN_REC_C_ROUTE_SPDIF 0x00 355 #define OXYGEN_REC_C_ROUTE_I2S_ADC_3 0x20 356 357 #define OXYGEN_ADC_MONITOR 0xc3 358 #define OXYGEN_ADC_MONITOR_A 0x01 359 #define OXYGEN_ADC_MONITOR_A_HALF_VOL 0x02 360 #define OXYGEN_ADC_MONITOR_B 0x04 361 #define OXYGEN_ADC_MONITOR_B_HALF_VOL 0x08 362 #define OXYGEN_ADC_MONITOR_C 0x10 363 #define OXYGEN_ADC_MONITOR_C_HALF_VOL 0x20 364 365 #define OXYGEN_A_MONITOR_ROUTING 0xc4 366 #define OXYGEN_A_MONITOR_ROUTE_0_MASK 0x03 367 #define OXYGEN_A_MONITOR_ROUTE_0_SHIFT 0 368 #define OXYGEN_A_MONITOR_ROUTE_1_MASK 0x0c 369 #define OXYGEN_A_MONITOR_ROUTE_1_SHIFT 2 370 #define OXYGEN_A_MONITOR_ROUTE_2_MASK 0x30 371 #define OXYGEN_A_MONITOR_ROUTE_2_SHIFT 4 372 #define OXYGEN_A_MONITOR_ROUTE_3_MASK 0xc0 373 #define OXYGEN_A_MONITOR_ROUTE_3_SHIFT 6 374 375 #define OXYGEN_AC97_CONTROL 0xd0 376 #define OXYGEN_AC97_COLD_RESET 0x0001 377 #define OXYGEN_AC97_SUSPENDED 0x0002 /* read */ 378 #define OXYGEN_AC97_RESUME 0x0002 /* write */ 379 #define OXYGEN_AC97_CLOCK_DISABLE 0x0004 380 #define OXYGEN_AC97_NO_CODEC_0 0x0008 381 #define OXYGEN_AC97_CODEC_0 0x0010 382 #define OXYGEN_AC97_CODEC_1 0x0020 383 384 #define OXYGEN_AC97_INTERRUPT_MASK 0xd2 385 #define OXYGEN_AC97_INT_READ_DONE 0x01 386 #define OXYGEN_AC97_INT_WRITE_DONE 0x02 387 #define OXYGEN_AC97_INT_CODEC_0 0x10 388 #define OXYGEN_AC97_INT_CODEC_1 0x20 389 390 #define OXYGEN_AC97_INTERRUPT_STATUS 0xd3 391 /* OXYGEN_AC97_INT_* */ 392 393 #define OXYGEN_AC97_OUT_CONFIG 0xd4 394 #define OXYGEN_AC97_CODEC1_SLOT3 0x00000001 395 #define OXYGEN_AC97_CODEC1_SLOT3_VSR 0x00000002 396 #define OXYGEN_AC97_CODEC1_SLOT4 0x00000010 397 #define OXYGEN_AC97_CODEC1_SLOT4_VSR 0x00000020 398 #define OXYGEN_AC97_CODEC0_FRONTL 0x00000100 399 #define OXYGEN_AC97_CODEC0_FRONTR 0x00000200 400 #define OXYGEN_AC97_CODEC0_SIDEL 0x00000400 401 #define OXYGEN_AC97_CODEC0_SIDER 0x00000800 402 #define OXYGEN_AC97_CODEC0_CENTER 0x00001000 403 #define OXYGEN_AC97_CODEC0_BASE 0x00002000 404 #define OXYGEN_AC97_CODEC0_REARL 0x00004000 405 #define OXYGEN_AC97_CODEC0_REARR 0x00008000 406 407 #define OXYGEN_AC97_IN_CONFIG 0xd8 408 #define OXYGEN_AC97_CODEC1_LINEL 0x00000001 409 #define OXYGEN_AC97_CODEC1_LINEL_VSR 0x00000002 410 #define OXYGEN_AC97_CODEC1_LINEL_16 0x00000000 411 #define OXYGEN_AC97_CODEC1_LINEL_18 0x00000004 412 #define OXYGEN_AC97_CODEC1_LINEL_20 0x00000008 413 #define OXYGEN_AC97_CODEC1_LINER 0x00000010 414 #define OXYGEN_AC97_CODEC1_LINER_VSR 0x00000020 415 #define OXYGEN_AC97_CODEC1_LINER_16 0x00000000 416 #define OXYGEN_AC97_CODEC1_LINER_18 0x00000040 417 #define OXYGEN_AC97_CODEC1_LINER_20 0x00000080 418 #define OXYGEN_AC97_CODEC0_LINEL 0x00000100 419 #define OXYGEN_AC97_CODEC0_LINER 0x00000200 420 421 #define OXYGEN_AC97_REGS 0xdc 422 #define OXYGEN_AC97_REG_DATA_MASK 0x0000ffff 423 #define OXYGEN_AC97_REG_ADDR_MASK 0x007f0000 424 #define OXYGEN_AC97_REG_ADDR_SHIFT 16 425 #define OXYGEN_AC97_REG_DIR_MASK 0x00800000 426 #define OXYGEN_AC97_REG_DIR_WRITE 0x00000000 427 #define OXYGEN_AC97_REG_DIR_READ 0x00800000 428 #define OXYGEN_AC97_REG_CODEC_MASK 0x01000000 429 #define OXYGEN_AC97_REG_CODEC_SHIFT 24 430 431 #define OXYGEN_TEST 0xe0 432 #define OXYGEN_TEST_RAM_SUCCEEDED 0x01 433 #define OXYGEN_TEST_PLAYBACK_RAM 0x02 434 #define OXYGEN_TEST_RECORD_RAM 0x04 435 #define OXYGEN_TEST_PLL 0x08 436 #define OXYGEN_TEST_2WIRE_LOOPBACK 0x10 437 438 #define OXYGEN_DMA_FLUSH 0xe1 439 /* OXYGEN_CHANNEL_* */ 440 441 #define OXYGEN_CODEC_VERSION 0xe4 442 #define OXYGEN_CODEC_ID_MASK 0x07 443 444 #define OXYGEN_REVISION 0xe6 445 #define OXYGEN_PACKAGE_ID_MASK 0x0007 446 #define OXYGEN_PACKAGE_ID_8786 0x0004 447 #define OXYGEN_PACKAGE_ID_8787 0x0006 448 #define OXYGEN_PACKAGE_ID_8788 0x0007 449 #define OXYGEN_REVISION_MASK 0xfff8 450 #define OXYGEN_REVISION_2 0x0008 451 452 #define OXYGEN_OFFSIN_48K 0xe8 453 #define OXYGEN_OFFSBASE_48K 0xe9 454 #define OXYGEN_OFFSBASE_MASK 0x0fff 455 #define OXYGEN_OFFSIN_44K 0xec 456 #define OXYGEN_OFFSBASE_44K 0xed 457 458 #endif 459