1 /* 2 * C-Media CMI8788 driver - main driver module 3 * 4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de> 5 * 6 * 7 * This driver is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License, version 2. 9 * 10 * This driver is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this driver; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/mutex.h> 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <sound/ac97_codec.h> 26 #include <sound/asoundef.h> 27 #include <sound/core.h> 28 #include <sound/info.h> 29 #include <sound/mpu401.h> 30 #include <sound/pcm.h> 31 #include "oxygen.h" 32 #include "cm9780.h" 33 34 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 35 MODULE_DESCRIPTION("C-Media CMI8788 helper library"); 36 MODULE_LICENSE("GPL v2"); 37 38 #define DRIVER "oxygen" 39 40 static inline int oxygen_uart_input_ready(struct oxygen *chip) 41 { 42 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY); 43 } 44 45 static void oxygen_read_uart(struct oxygen *chip) 46 { 47 if (unlikely(!oxygen_uart_input_ready(chip))) { 48 /* no data, but read it anyway to clear the interrupt */ 49 oxygen_read8(chip, OXYGEN_MPU401); 50 return; 51 } 52 do { 53 u8 data = oxygen_read8(chip, OXYGEN_MPU401); 54 if (data == MPU401_ACK) 55 continue; 56 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input)) 57 chip->uart_input_count = 0; 58 chip->uart_input[chip->uart_input_count++] = data; 59 } while (oxygen_uart_input_ready(chip)); 60 if (chip->model.uart_input) 61 chip->model.uart_input(chip); 62 } 63 64 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id) 65 { 66 struct oxygen *chip = dev_id; 67 unsigned int status, clear, elapsed_streams, i; 68 69 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS); 70 if (!status) 71 return IRQ_NONE; 72 73 spin_lock(&chip->reg_lock); 74 75 clear = status & (OXYGEN_CHANNEL_A | 76 OXYGEN_CHANNEL_B | 77 OXYGEN_CHANNEL_C | 78 OXYGEN_CHANNEL_SPDIF | 79 OXYGEN_CHANNEL_MULTICH | 80 OXYGEN_CHANNEL_AC97 | 81 OXYGEN_INT_SPDIF_IN_DETECT | 82 OXYGEN_INT_GPIO | 83 OXYGEN_INT_AC97); 84 if (clear) { 85 if (clear & OXYGEN_INT_SPDIF_IN_DETECT) 86 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT; 87 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 88 chip->interrupt_mask & ~clear); 89 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 90 chip->interrupt_mask); 91 } 92 93 elapsed_streams = status & chip->pcm_running; 94 95 spin_unlock(&chip->reg_lock); 96 97 for (i = 0; i < PCM_COUNT; ++i) 98 if ((elapsed_streams & (1 << i)) && chip->streams[i]) 99 snd_pcm_period_elapsed(chip->streams[i]); 100 101 if (status & OXYGEN_INT_SPDIF_IN_DETECT) { 102 spin_lock(&chip->reg_lock); 103 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 104 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT | 105 OXYGEN_SPDIF_RATE_INT)) { 106 /* write the interrupt bit(s) to clear */ 107 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i); 108 schedule_work(&chip->spdif_input_bits_work); 109 } 110 spin_unlock(&chip->reg_lock); 111 } 112 113 if (status & OXYGEN_INT_GPIO) 114 schedule_work(&chip->gpio_work); 115 116 if (status & OXYGEN_INT_MIDI) { 117 if (chip->midi) 118 snd_mpu401_uart_interrupt(0, chip->midi->private_data); 119 else 120 oxygen_read_uart(chip); 121 } 122 123 if (status & OXYGEN_INT_AC97) 124 wake_up(&chip->ac97_waitqueue); 125 126 return IRQ_HANDLED; 127 } 128 129 static void oxygen_spdif_input_bits_changed(struct work_struct *work) 130 { 131 struct oxygen *chip = container_of(work, struct oxygen, 132 spdif_input_bits_work); 133 u32 reg; 134 135 /* 136 * This function gets called when there is new activity on the SPDIF 137 * input, or when we lose lock on the input signal, or when the rate 138 * changes. 139 */ 140 msleep(1); 141 spin_lock_irq(&chip->reg_lock); 142 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 143 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | 144 OXYGEN_SPDIF_LOCK_STATUS)) 145 == OXYGEN_SPDIF_SENSE_STATUS) { 146 /* 147 * If we detect activity on the SPDIF input but cannot lock to 148 * a signal, the clock bit is likely to be wrong. 149 */ 150 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK; 151 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); 152 spin_unlock_irq(&chip->reg_lock); 153 msleep(1); 154 spin_lock_irq(&chip->reg_lock); 155 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 156 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | 157 OXYGEN_SPDIF_LOCK_STATUS)) 158 == OXYGEN_SPDIF_SENSE_STATUS) { 159 /* nothing detected with either clock; give up */ 160 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK) 161 == OXYGEN_SPDIF_IN_CLOCK_192) { 162 /* 163 * Reset clock to <= 96 kHz because this is 164 * more likely to be received next time. 165 */ 166 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK; 167 reg |= OXYGEN_SPDIF_IN_CLOCK_96; 168 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); 169 } 170 } 171 } 172 spin_unlock_irq(&chip->reg_lock); 173 174 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) { 175 spin_lock_irq(&chip->reg_lock); 176 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; 177 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 178 chip->interrupt_mask); 179 spin_unlock_irq(&chip->reg_lock); 180 181 /* 182 * We don't actually know that any channel status bits have 183 * changed, but let's send a notification just to be sure. 184 */ 185 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 186 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id); 187 } 188 } 189 190 static void oxygen_gpio_changed(struct work_struct *work) 191 { 192 struct oxygen *chip = container_of(work, struct oxygen, gpio_work); 193 194 if (chip->model.gpio_changed) 195 chip->model.gpio_changed(chip); 196 } 197 198 #ifdef CONFIG_PROC_FS 199 static void oxygen_proc_read(struct snd_info_entry *entry, 200 struct snd_info_buffer *buffer) 201 { 202 struct oxygen *chip = entry->private_data; 203 int i, j; 204 205 snd_iprintf(buffer, "CMI8788\n\n"); 206 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) { 207 snd_iprintf(buffer, "%02x:", i); 208 for (j = 0; j < 0x10; ++j) 209 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j)); 210 snd_iprintf(buffer, "\n"); 211 } 212 if (mutex_lock_interruptible(&chip->mutex) < 0) 213 return; 214 if (chip->has_ac97_0) { 215 snd_iprintf(buffer, "\nAC97\n"); 216 for (i = 0; i < 0x80; i += 0x10) { 217 snd_iprintf(buffer, "%02x:", i); 218 for (j = 0; j < 0x10; j += 2) 219 snd_iprintf(buffer, " %04x", 220 oxygen_read_ac97(chip, 0, i + j)); 221 snd_iprintf(buffer, "\n"); 222 } 223 } 224 if (chip->has_ac97_1) { 225 snd_iprintf(buffer, "\nAC97 2\n"); 226 for (i = 0; i < 0x80; i += 0x10) { 227 snd_iprintf(buffer, "%02x:", i); 228 for (j = 0; j < 0x10; j += 2) 229 snd_iprintf(buffer, " %04x", 230 oxygen_read_ac97(chip, 1, i + j)); 231 snd_iprintf(buffer, "\n"); 232 } 233 } 234 mutex_unlock(&chip->mutex); 235 } 236 237 static void oxygen_proc_init(struct oxygen *chip) 238 { 239 struct snd_info_entry *entry; 240 241 if (!snd_card_proc_new(chip->card, "cmi8788", &entry)) 242 snd_info_set_text_ops(entry, chip, oxygen_proc_read); 243 } 244 #else 245 #define oxygen_proc_init(chip) 246 #endif 247 248 static const struct pci_device_id * 249 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[]) 250 { 251 u16 subdevice; 252 253 /* 254 * Make sure the EEPROM pins are available, i.e., not used for SPI. 255 * (This function is called before we initialize or use SPI.) 256 */ 257 oxygen_clear_bits8(chip, OXYGEN_FUNCTION, 258 OXYGEN_FUNCTION_ENABLE_SPI_4_5); 259 /* 260 * Read the subsystem device ID directly from the EEPROM, because the 261 * chip didn't if the first EEPROM word was overwritten. 262 */ 263 subdevice = oxygen_read_eeprom(chip, 2); 264 /* use default ID if EEPROM is missing */ 265 if (subdevice == 0xffff) 266 subdevice = 0x8788; 267 /* 268 * We use only the subsystem device ID for searching because it is 269 * unique even without the subsystem vendor ID, which may have been 270 * overwritten in the EEPROM. 271 */ 272 for (; ids->vendor; ++ids) 273 if (ids->subdevice == subdevice && 274 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA) 275 return ids; 276 return NULL; 277 } 278 279 static void oxygen_restore_eeprom(struct oxygen *chip, 280 const struct pci_device_id *id) 281 { 282 u16 eeprom_id; 283 284 eeprom_id = oxygen_read_eeprom(chip, 0); 285 if (eeprom_id != OXYGEN_EEPROM_ID && 286 (eeprom_id != 0xffff || id->subdevice != 0x8788)) { 287 /* 288 * This function gets called only when a known card model has 289 * been detected, i.e., we know there is a valid subsystem 290 * product ID at index 2 in the EEPROM. Therefore, we have 291 * been able to deduce the correct subsystem vendor ID, and 292 * this is enough information to restore the original EEPROM 293 * contents. 294 */ 295 oxygen_write_eeprom(chip, 1, id->subvendor); 296 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID); 297 298 oxygen_set_bits8(chip, OXYGEN_MISC, 299 OXYGEN_MISC_WRITE_PCI_SUBID); 300 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, 301 id->subvendor); 302 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID, 303 id->subdevice); 304 oxygen_clear_bits8(chip, OXYGEN_MISC, 305 OXYGEN_MISC_WRITE_PCI_SUBID); 306 307 snd_printk(KERN_INFO "EEPROM ID restored\n"); 308 } 309 } 310 311 static void configure_pcie_bridge(struct pci_dev *pci) 312 { 313 enum { PEX811X, PI7C9X110 }; 314 static const struct pci_device_id bridge_ids[] = { 315 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X }, 316 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X }, 317 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 }, 318 { } 319 }; 320 struct pci_dev *bridge; 321 const struct pci_device_id *id; 322 u32 tmp; 323 324 if (!pci->bus || !pci->bus->self) 325 return; 326 bridge = pci->bus->self; 327 328 id = pci_match_id(bridge_ids, bridge); 329 if (!id) 330 return; 331 332 switch (id->driver_data) { 333 case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */ 334 pci_read_config_dword(bridge, 0x48, &tmp); 335 tmp |= 1; /* enable blind prefetching */ 336 tmp |= 1 << 11; /* enable beacon generation */ 337 pci_write_config_dword(bridge, 0x48, tmp); 338 339 pci_write_config_dword(bridge, 0x84, 0x0c); 340 pci_read_config_dword(bridge, 0x88, &tmp); 341 tmp &= ~(7 << 27); 342 tmp |= 2 << 27; /* set prefetch size to 128 bytes */ 343 pci_write_config_dword(bridge, 0x88, tmp); 344 break; 345 346 case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */ 347 pci_read_config_dword(bridge, 0x40, &tmp); 348 tmp |= 1; /* park the PCI arbiter to the sound chip */ 349 pci_write_config_dword(bridge, 0x40, tmp); 350 break; 351 } 352 } 353 354 static void oxygen_init(struct oxygen *chip) 355 { 356 unsigned int i; 357 358 chip->dac_routing = 1; 359 for (i = 0; i < 8; ++i) 360 chip->dac_volume[i] = chip->model.dac_volume_min; 361 chip->dac_mute = 1; 362 chip->spdif_playback_enable = 1; 363 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL | 364 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT); 365 chip->spdif_pcm_bits = chip->spdif_bits; 366 367 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2) 368 chip->revision = 2; 369 else 370 chip->revision = 1; 371 372 if (chip->revision == 1) 373 oxygen_set_bits8(chip, OXYGEN_MISC, 374 OXYGEN_MISC_PCI_MEM_W_1_CLOCK); 375 376 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); 377 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; 378 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0; 379 380 oxygen_write8_masked(chip, OXYGEN_FUNCTION, 381 OXYGEN_FUNCTION_RESET_CODEC | 382 chip->model.function_flags, 383 OXYGEN_FUNCTION_RESET_CODEC | 384 OXYGEN_FUNCTION_2WIRE_SPI_MASK | 385 OXYGEN_FUNCTION_ENABLE_SPI_4_5); 386 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0); 387 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0); 388 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS, 389 OXYGEN_PLAY_CHANNELS_2 | 390 OXYGEN_DMA_A_BURST_8 | 391 OXYGEN_DMA_MULTICH_BURST_8); 392 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 393 oxygen_write8_masked(chip, OXYGEN_MISC, 394 chip->model.misc_flags, 395 OXYGEN_MISC_WRITE_PCI_SUBID | 396 OXYGEN_MISC_REC_C_FROM_SPDIF | 397 OXYGEN_MISC_REC_B_FROM_AC97 | 398 OXYGEN_MISC_REC_A_FROM_MULTICH | 399 OXYGEN_MISC_MIDI); 400 oxygen_write8(chip, OXYGEN_REC_FORMAT, 401 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) | 402 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) | 403 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT)); 404 oxygen_write8(chip, OXYGEN_PLAY_FORMAT, 405 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) | 406 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT)); 407 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2); 408 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, 409 OXYGEN_RATE_48000 | chip->model.dac_i2s_format | 410 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | 411 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); 412 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) 413 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 414 OXYGEN_RATE_48000 | chip->model.adc_i2s_format | 415 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | 416 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); 417 else 418 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 419 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); 420 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 | 421 CAPTURE_2_FROM_I2S_2)) 422 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 423 OXYGEN_RATE_48000 | chip->model.adc_i2s_format | 424 OXYGEN_I2S_MCLK_256 | OXYGEN_I2S_BITS_16 | 425 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64); 426 else 427 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 428 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); 429 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 430 OXYGEN_I2S_MASTER | OXYGEN_I2S_MUTE_MCLK); 431 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, 432 OXYGEN_SPDIF_OUT_ENABLE | 433 OXYGEN_SPDIF_LOOPBACK); 434 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) 435 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, 436 OXYGEN_SPDIF_SENSE_MASK | 437 OXYGEN_SPDIF_LOCK_MASK | 438 OXYGEN_SPDIF_RATE_MASK | 439 OXYGEN_SPDIF_LOCK_PAR | 440 OXYGEN_SPDIF_IN_CLOCK_96, 441 OXYGEN_SPDIF_SENSE_MASK | 442 OXYGEN_SPDIF_LOCK_MASK | 443 OXYGEN_SPDIF_RATE_MASK | 444 OXYGEN_SPDIF_SENSE_PAR | 445 OXYGEN_SPDIF_LOCK_PAR | 446 OXYGEN_SPDIF_IN_CLOCK_MASK); 447 else 448 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, 449 OXYGEN_SPDIF_SENSE_MASK | 450 OXYGEN_SPDIF_LOCK_MASK | 451 OXYGEN_SPDIF_RATE_MASK); 452 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); 453 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, 454 OXYGEN_2WIRE_LENGTH_8 | 455 OXYGEN_2WIRE_INTERRUPT_MASK | 456 OXYGEN_2WIRE_SPEED_STANDARD); 457 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK); 458 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0); 459 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0); 460 oxygen_write16(chip, OXYGEN_PLAY_ROUTING, 461 OXYGEN_PLAY_MULTICH_I2S_DAC | 462 OXYGEN_PLAY_SPDIF_SPDIF | 463 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | 464 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | 465 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | 466 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT)); 467 oxygen_write8(chip, OXYGEN_REC_ROUTING, 468 OXYGEN_REC_A_ROUTE_I2S_ADC_1 | 469 OXYGEN_REC_B_ROUTE_I2S_ADC_2 | 470 OXYGEN_REC_C_ROUTE_SPDIF); 471 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0); 472 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, 473 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) | 474 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) | 475 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) | 476 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT)); 477 478 if (chip->has_ac97_0 | chip->has_ac97_1) 479 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 480 OXYGEN_AC97_INT_READ_DONE | 481 OXYGEN_AC97_INT_WRITE_DONE); 482 else 483 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0); 484 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0); 485 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0); 486 if (!(chip->has_ac97_0 | chip->has_ac97_1)) 487 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, 488 OXYGEN_AC97_CLOCK_DISABLE); 489 if (!chip->has_ac97_0) { 490 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, 491 OXYGEN_AC97_NO_CODEC_0); 492 } else { 493 oxygen_write_ac97(chip, 0, AC97_RESET, 0); 494 msleep(1); 495 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP, 496 CM9780_GPIO0IO | CM9780_GPIO1IO); 497 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER, 498 CM9780_BSTSEL | CM9780_STRO_MIC | 499 CM9780_MIX2FR | CM9780_PCBSW); 500 oxygen_ac97_set_bits(chip, 0, CM9780_JACK, 501 CM9780_RSOE | CM9780_CBOE | 502 CM9780_SSOE | CM9780_FROE | 503 CM9780_MIC2MIC | CM9780_LI2LI); 504 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000); 505 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000); 506 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808); 507 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808); 508 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808); 509 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808); 510 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808); 511 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000); 512 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080); 513 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080); 514 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, 515 CM9780_GPO0); 516 /* power down unused ADCs and DACs */ 517 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN, 518 AC97_PD_PR0 | AC97_PD_PR1); 519 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS, 520 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK); 521 } 522 if (chip->has_ac97_1) { 523 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG, 524 OXYGEN_AC97_CODEC1_SLOT3 | 525 OXYGEN_AC97_CODEC1_SLOT4); 526 oxygen_write_ac97(chip, 1, AC97_RESET, 0); 527 msleep(1); 528 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000); 529 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000); 530 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000); 531 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808); 532 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808); 533 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808); 534 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808); 535 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808); 536 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808); 537 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000); 538 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000); 539 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040); 540 } 541 } 542 543 static void oxygen_shutdown(struct oxygen *chip) 544 { 545 spin_lock_irq(&chip->reg_lock); 546 chip->interrupt_mask = 0; 547 chip->pcm_running = 0; 548 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 549 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 550 spin_unlock_irq(&chip->reg_lock); 551 } 552 553 static void oxygen_card_free(struct snd_card *card) 554 { 555 struct oxygen *chip = card->private_data; 556 557 oxygen_shutdown(chip); 558 if (chip->irq >= 0) 559 free_irq(chip->irq, chip); 560 flush_scheduled_work(); 561 chip->model.cleanup(chip); 562 kfree(chip->model_data); 563 mutex_destroy(&chip->mutex); 564 pci_release_regions(chip->pci); 565 pci_disable_device(chip->pci); 566 } 567 568 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id, 569 struct module *owner, 570 const struct pci_device_id *ids, 571 int (*get_model)(struct oxygen *chip, 572 const struct pci_device_id *id 573 ) 574 ) 575 { 576 struct snd_card *card; 577 struct oxygen *chip; 578 const struct pci_device_id *pci_id; 579 int err; 580 581 err = snd_card_create(index, id, owner, sizeof(*chip), &card); 582 if (err < 0) 583 return err; 584 585 chip = card->private_data; 586 chip->card = card; 587 chip->pci = pci; 588 chip->irq = -1; 589 spin_lock_init(&chip->reg_lock); 590 mutex_init(&chip->mutex); 591 INIT_WORK(&chip->spdif_input_bits_work, 592 oxygen_spdif_input_bits_changed); 593 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed); 594 init_waitqueue_head(&chip->ac97_waitqueue); 595 596 err = pci_enable_device(pci); 597 if (err < 0) 598 goto err_card; 599 600 err = pci_request_regions(pci, DRIVER); 601 if (err < 0) { 602 snd_printk(KERN_ERR "cannot reserve PCI resources\n"); 603 goto err_pci_enable; 604 } 605 606 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) || 607 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) { 608 snd_printk(KERN_ERR "invalid PCI I/O range\n"); 609 err = -ENXIO; 610 goto err_pci_regions; 611 } 612 chip->addr = pci_resource_start(pci, 0); 613 614 pci_id = oxygen_search_pci_id(chip, ids); 615 if (!pci_id) { 616 err = -ENODEV; 617 goto err_pci_regions; 618 } 619 oxygen_restore_eeprom(chip, pci_id); 620 err = get_model(chip, pci_id); 621 if (err < 0) 622 goto err_pci_regions; 623 624 if (chip->model.model_data_size) { 625 chip->model_data = kzalloc(chip->model.model_data_size, 626 GFP_KERNEL); 627 if (!chip->model_data) { 628 err = -ENOMEM; 629 goto err_pci_regions; 630 } 631 } 632 633 pci_set_master(pci); 634 snd_card_set_dev(card, &pci->dev); 635 card->private_free = oxygen_card_free; 636 637 configure_pcie_bridge(pci); 638 oxygen_init(chip); 639 chip->model.init(chip); 640 641 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED, 642 DRIVER, chip); 643 if (err < 0) { 644 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq); 645 goto err_card; 646 } 647 chip->irq = pci->irq; 648 649 strcpy(card->driver, chip->model.chip); 650 strcpy(card->shortname, chip->model.shortname); 651 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i", 652 chip->model.longname, chip->revision, chip->addr, chip->irq); 653 strcpy(card->mixername, chip->model.chip); 654 snd_component_add(card, chip->model.chip); 655 656 err = oxygen_pcm_init(chip); 657 if (err < 0) 658 goto err_card; 659 660 err = oxygen_mixer_init(chip); 661 if (err < 0) 662 goto err_card; 663 664 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) { 665 unsigned int info_flags = MPU401_INFO_INTEGRATED; 666 if (chip->model.device_config & MIDI_OUTPUT) 667 info_flags |= MPU401_INFO_OUTPUT; 668 if (chip->model.device_config & MIDI_INPUT) 669 info_flags |= MPU401_INFO_INPUT; 670 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 671 chip->addr + OXYGEN_MPU401, 672 info_flags, 0, 0, 673 &chip->midi); 674 if (err < 0) 675 goto err_card; 676 } 677 678 oxygen_proc_init(chip); 679 680 spin_lock_irq(&chip->reg_lock); 681 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) 682 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; 683 if (chip->has_ac97_0 | chip->has_ac97_1) 684 chip->interrupt_mask |= OXYGEN_INT_AC97; 685 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 686 spin_unlock_irq(&chip->reg_lock); 687 688 err = snd_card_register(card); 689 if (err < 0) 690 goto err_card; 691 692 pci_set_drvdata(pci, card); 693 return 0; 694 695 err_pci_regions: 696 pci_release_regions(pci); 697 err_pci_enable: 698 pci_disable_device(pci); 699 err_card: 700 snd_card_free(card); 701 return err; 702 } 703 EXPORT_SYMBOL(oxygen_pci_probe); 704 705 void oxygen_pci_remove(struct pci_dev *pci) 706 { 707 snd_card_free(pci_get_drvdata(pci)); 708 pci_set_drvdata(pci, NULL); 709 } 710 EXPORT_SYMBOL(oxygen_pci_remove); 711 712 #ifdef CONFIG_PM 713 int oxygen_pci_suspend(struct pci_dev *pci, pm_message_t state) 714 { 715 struct snd_card *card = pci_get_drvdata(pci); 716 struct oxygen *chip = card->private_data; 717 unsigned int i, saved_interrupt_mask; 718 719 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 720 721 for (i = 0; i < PCM_COUNT; ++i) 722 if (chip->streams[i]) 723 snd_pcm_suspend(chip->streams[i]); 724 725 if (chip->model.suspend) 726 chip->model.suspend(chip); 727 728 spin_lock_irq(&chip->reg_lock); 729 saved_interrupt_mask = chip->interrupt_mask; 730 chip->interrupt_mask = 0; 731 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 732 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 733 spin_unlock_irq(&chip->reg_lock); 734 735 synchronize_irq(chip->irq); 736 flush_scheduled_work(); 737 chip->interrupt_mask = saved_interrupt_mask; 738 739 pci_disable_device(pci); 740 pci_save_state(pci); 741 pci_set_power_state(pci, pci_choose_state(pci, state)); 742 return 0; 743 } 744 EXPORT_SYMBOL(oxygen_pci_suspend); 745 746 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = { 747 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff, 748 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000 749 }; 750 static const u32 ac97_registers_to_restore[2][0x40 / 32] = { 751 { 0x18284fa2, 0x03060000 }, 752 { 0x00007fa6, 0x00200000 } 753 }; 754 755 static inline int is_bit_set(const u32 *bitmap, unsigned int bit) 756 { 757 return bitmap[bit / 32] & (1 << (bit & 31)); 758 } 759 760 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec) 761 { 762 unsigned int i; 763 764 oxygen_write_ac97(chip, codec, AC97_RESET, 0); 765 msleep(1); 766 for (i = 1; i < 0x40; ++i) 767 if (is_bit_set(ac97_registers_to_restore[codec], i)) 768 oxygen_write_ac97(chip, codec, i * 2, 769 chip->saved_ac97_registers[codec][i]); 770 } 771 772 int oxygen_pci_resume(struct pci_dev *pci) 773 { 774 struct snd_card *card = pci_get_drvdata(pci); 775 struct oxygen *chip = card->private_data; 776 unsigned int i; 777 778 pci_set_power_state(pci, PCI_D0); 779 pci_restore_state(pci); 780 if (pci_enable_device(pci) < 0) { 781 snd_printk(KERN_ERR "cannot reenable device"); 782 snd_card_disconnect(card); 783 return -EIO; 784 } 785 pci_set_master(pci); 786 787 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 788 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 789 for (i = 0; i < OXYGEN_IO_SIZE; ++i) 790 if (is_bit_set(registers_to_restore, i)) 791 oxygen_write8(chip, i, chip->saved_registers._8[i]); 792 if (chip->has_ac97_0) 793 oxygen_restore_ac97(chip, 0); 794 if (chip->has_ac97_1) 795 oxygen_restore_ac97(chip, 1); 796 797 if (chip->model.resume) 798 chip->model.resume(chip); 799 800 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 801 802 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 803 return 0; 804 } 805 EXPORT_SYMBOL(oxygen_pci_resume); 806 #endif /* CONFIG_PM */ 807 808 void oxygen_pci_shutdown(struct pci_dev *pci) 809 { 810 struct snd_card *card = pci_get_drvdata(pci); 811 struct oxygen *chip = card->private_data; 812 813 oxygen_shutdown(chip); 814 chip->model.cleanup(chip); 815 } 816 EXPORT_SYMBOL(oxygen_pci_shutdown); 817