1 /* 2 * C-Media CMI8788 driver - main driver module 3 * 4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de> 5 * 6 * 7 * This driver is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License, version 2. 9 * 10 * This driver is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this driver; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/mutex.h> 23 #include <linux/pci.h> 24 #include <linux/slab.h> 25 #include <linux/module.h> 26 #include <sound/ac97_codec.h> 27 #include <sound/asoundef.h> 28 #include <sound/core.h> 29 #include <sound/info.h> 30 #include <sound/mpu401.h> 31 #include <sound/pcm.h> 32 #include "oxygen.h" 33 #include "cm9780.h" 34 35 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>"); 36 MODULE_DESCRIPTION("C-Media CMI8788 helper library"); 37 MODULE_LICENSE("GPL v2"); 38 39 #define DRIVER "oxygen" 40 41 static inline int oxygen_uart_input_ready(struct oxygen *chip) 42 { 43 return !(oxygen_read8(chip, OXYGEN_MPU401 + 1) & MPU401_RX_EMPTY); 44 } 45 46 static void oxygen_read_uart(struct oxygen *chip) 47 { 48 if (unlikely(!oxygen_uart_input_ready(chip))) { 49 /* no data, but read it anyway to clear the interrupt */ 50 oxygen_read8(chip, OXYGEN_MPU401); 51 return; 52 } 53 do { 54 u8 data = oxygen_read8(chip, OXYGEN_MPU401); 55 if (data == MPU401_ACK) 56 continue; 57 if (chip->uart_input_count >= ARRAY_SIZE(chip->uart_input)) 58 chip->uart_input_count = 0; 59 chip->uart_input[chip->uart_input_count++] = data; 60 } while (oxygen_uart_input_ready(chip)); 61 if (chip->model.uart_input) 62 chip->model.uart_input(chip); 63 } 64 65 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id) 66 { 67 struct oxygen *chip = dev_id; 68 unsigned int status, clear, elapsed_streams, i; 69 70 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS); 71 if (!status) 72 return IRQ_NONE; 73 74 spin_lock(&chip->reg_lock); 75 76 clear = status & (OXYGEN_CHANNEL_A | 77 OXYGEN_CHANNEL_B | 78 OXYGEN_CHANNEL_C | 79 OXYGEN_CHANNEL_SPDIF | 80 OXYGEN_CHANNEL_MULTICH | 81 OXYGEN_CHANNEL_AC97 | 82 OXYGEN_INT_SPDIF_IN_DETECT | 83 OXYGEN_INT_GPIO | 84 OXYGEN_INT_AC97); 85 if (clear) { 86 if (clear & OXYGEN_INT_SPDIF_IN_DETECT) 87 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT; 88 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 89 chip->interrupt_mask & ~clear); 90 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 91 chip->interrupt_mask); 92 } 93 94 elapsed_streams = status & chip->pcm_running; 95 96 spin_unlock(&chip->reg_lock); 97 98 for (i = 0; i < PCM_COUNT; ++i) 99 if ((elapsed_streams & (1 << i)) && chip->streams[i]) 100 snd_pcm_period_elapsed(chip->streams[i]); 101 102 if (status & OXYGEN_INT_SPDIF_IN_DETECT) { 103 spin_lock(&chip->reg_lock); 104 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 105 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT | 106 OXYGEN_SPDIF_RATE_INT)) { 107 /* write the interrupt bit(s) to clear */ 108 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i); 109 schedule_work(&chip->spdif_input_bits_work); 110 } 111 spin_unlock(&chip->reg_lock); 112 } 113 114 if (status & OXYGEN_INT_GPIO) 115 schedule_work(&chip->gpio_work); 116 117 if (status & OXYGEN_INT_MIDI) { 118 if (chip->midi) 119 snd_mpu401_uart_interrupt(0, chip->midi->private_data); 120 else 121 oxygen_read_uart(chip); 122 } 123 124 if (status & OXYGEN_INT_AC97) 125 wake_up(&chip->ac97_waitqueue); 126 127 return IRQ_HANDLED; 128 } 129 130 static void oxygen_spdif_input_bits_changed(struct work_struct *work) 131 { 132 struct oxygen *chip = container_of(work, struct oxygen, 133 spdif_input_bits_work); 134 u32 reg; 135 136 /* 137 * This function gets called when there is new activity on the SPDIF 138 * input, or when we lose lock on the input signal, or when the rate 139 * changes. 140 */ 141 msleep(1); 142 spin_lock_irq(&chip->reg_lock); 143 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 144 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | 145 OXYGEN_SPDIF_LOCK_STATUS)) 146 == OXYGEN_SPDIF_SENSE_STATUS) { 147 /* 148 * If we detect activity on the SPDIF input but cannot lock to 149 * a signal, the clock bit is likely to be wrong. 150 */ 151 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK; 152 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); 153 spin_unlock_irq(&chip->reg_lock); 154 msleep(1); 155 spin_lock_irq(&chip->reg_lock); 156 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL); 157 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS | 158 OXYGEN_SPDIF_LOCK_STATUS)) 159 == OXYGEN_SPDIF_SENSE_STATUS) { 160 /* nothing detected with either clock; give up */ 161 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK) 162 == OXYGEN_SPDIF_IN_CLOCK_192) { 163 /* 164 * Reset clock to <= 96 kHz because this is 165 * more likely to be received next time. 166 */ 167 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK; 168 reg |= OXYGEN_SPDIF_IN_CLOCK_96; 169 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg); 170 } 171 } 172 } 173 spin_unlock_irq(&chip->reg_lock); 174 175 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) { 176 spin_lock_irq(&chip->reg_lock); 177 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; 178 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 179 chip->interrupt_mask); 180 spin_unlock_irq(&chip->reg_lock); 181 182 /* 183 * We don't actually know that any channel status bits have 184 * changed, but let's send a notification just to be sure. 185 */ 186 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE, 187 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id); 188 } 189 } 190 191 static void oxygen_gpio_changed(struct work_struct *work) 192 { 193 struct oxygen *chip = container_of(work, struct oxygen, gpio_work); 194 195 if (chip->model.gpio_changed) 196 chip->model.gpio_changed(chip); 197 } 198 199 static void oxygen_proc_read(struct snd_info_entry *entry, 200 struct snd_info_buffer *buffer) 201 { 202 struct oxygen *chip = entry->private_data; 203 int i, j; 204 205 switch (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_PACKAGE_ID_MASK) { 206 case OXYGEN_PACKAGE_ID_8786: i = '6'; break; 207 case OXYGEN_PACKAGE_ID_8787: i = '7'; break; 208 case OXYGEN_PACKAGE_ID_8788: i = '8'; break; 209 default: i = '?'; break; 210 } 211 snd_iprintf(buffer, "CMI878%c:\n", i); 212 for (i = 0; i < OXYGEN_IO_SIZE; i += 0x10) { 213 snd_iprintf(buffer, "%02x:", i); 214 for (j = 0; j < 0x10; ++j) 215 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j)); 216 snd_iprintf(buffer, "\n"); 217 } 218 if (mutex_lock_interruptible(&chip->mutex) < 0) 219 return; 220 if (chip->has_ac97_0) { 221 snd_iprintf(buffer, "\nAC97:\n"); 222 for (i = 0; i < 0x80; i += 0x10) { 223 snd_iprintf(buffer, "%02x:", i); 224 for (j = 0; j < 0x10; j += 2) 225 snd_iprintf(buffer, " %04x", 226 oxygen_read_ac97(chip, 0, i + j)); 227 snd_iprintf(buffer, "\n"); 228 } 229 } 230 if (chip->has_ac97_1) { 231 snd_iprintf(buffer, "\nAC97 2:\n"); 232 for (i = 0; i < 0x80; i += 0x10) { 233 snd_iprintf(buffer, "%02x:", i); 234 for (j = 0; j < 0x10; j += 2) 235 snd_iprintf(buffer, " %04x", 236 oxygen_read_ac97(chip, 1, i + j)); 237 snd_iprintf(buffer, "\n"); 238 } 239 } 240 mutex_unlock(&chip->mutex); 241 if (chip->model.dump_registers) 242 chip->model.dump_registers(chip, buffer); 243 } 244 245 static void oxygen_proc_init(struct oxygen *chip) 246 { 247 struct snd_info_entry *entry; 248 249 if (!snd_card_proc_new(chip->card, "oxygen", &entry)) 250 snd_info_set_text_ops(entry, chip, oxygen_proc_read); 251 } 252 253 static const struct pci_device_id * 254 oxygen_search_pci_id(struct oxygen *chip, const struct pci_device_id ids[]) 255 { 256 u16 subdevice; 257 258 /* 259 * Make sure the EEPROM pins are available, i.e., not used for SPI. 260 * (This function is called before we initialize or use SPI.) 261 */ 262 oxygen_clear_bits8(chip, OXYGEN_FUNCTION, 263 OXYGEN_FUNCTION_ENABLE_SPI_4_5); 264 /* 265 * Read the subsystem device ID directly from the EEPROM, because the 266 * chip didn't if the first EEPROM word was overwritten. 267 */ 268 subdevice = oxygen_read_eeprom(chip, 2); 269 /* use default ID if EEPROM is missing */ 270 if (subdevice == 0xffff && oxygen_read_eeprom(chip, 1) == 0xffff) 271 subdevice = 0x8788; 272 /* 273 * We use only the subsystem device ID for searching because it is 274 * unique even without the subsystem vendor ID, which may have been 275 * overwritten in the EEPROM. 276 */ 277 for (; ids->vendor; ++ids) 278 if (ids->subdevice == subdevice && 279 ids->driver_data != BROKEN_EEPROM_DRIVER_DATA) 280 return ids; 281 return NULL; 282 } 283 284 static void oxygen_restore_eeprom(struct oxygen *chip, 285 const struct pci_device_id *id) 286 { 287 u16 eeprom_id; 288 289 eeprom_id = oxygen_read_eeprom(chip, 0); 290 if (eeprom_id != OXYGEN_EEPROM_ID && 291 (eeprom_id != 0xffff || id->subdevice != 0x8788)) { 292 /* 293 * This function gets called only when a known card model has 294 * been detected, i.e., we know there is a valid subsystem 295 * product ID at index 2 in the EEPROM. Therefore, we have 296 * been able to deduce the correct subsystem vendor ID, and 297 * this is enough information to restore the original EEPROM 298 * contents. 299 */ 300 oxygen_write_eeprom(chip, 1, id->subvendor); 301 oxygen_write_eeprom(chip, 0, OXYGEN_EEPROM_ID); 302 303 oxygen_set_bits8(chip, OXYGEN_MISC, 304 OXYGEN_MISC_WRITE_PCI_SUBID); 305 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, 306 id->subvendor); 307 pci_write_config_word(chip->pci, PCI_SUBSYSTEM_ID, 308 id->subdevice); 309 oxygen_clear_bits8(chip, OXYGEN_MISC, 310 OXYGEN_MISC_WRITE_PCI_SUBID); 311 312 dev_info(chip->card->dev, "EEPROM ID restored\n"); 313 } 314 } 315 316 static void configure_pcie_bridge(struct pci_dev *pci) 317 { 318 enum { PEX811X, PI7C9X110, XIO2001 }; 319 static const struct pci_device_id bridge_ids[] = { 320 { PCI_VDEVICE(PLX, 0x8111), .driver_data = PEX811X }, 321 { PCI_VDEVICE(PLX, 0x8112), .driver_data = PEX811X }, 322 { PCI_DEVICE(0x12d8, 0xe110), .driver_data = PI7C9X110 }, 323 { PCI_VDEVICE(TI, 0x8240), .driver_data = XIO2001 }, 324 { } 325 }; 326 struct pci_dev *bridge; 327 const struct pci_device_id *id; 328 u32 tmp; 329 330 if (!pci->bus || !pci->bus->self) 331 return; 332 bridge = pci->bus->self; 333 334 id = pci_match_id(bridge_ids, bridge); 335 if (!id) 336 return; 337 338 switch (id->driver_data) { 339 case PEX811X: /* PLX PEX8111/PEX8112 PCIe/PCI bridge */ 340 pci_read_config_dword(bridge, 0x48, &tmp); 341 tmp |= 1; /* enable blind prefetching */ 342 tmp |= 1 << 11; /* enable beacon generation */ 343 pci_write_config_dword(bridge, 0x48, tmp); 344 345 pci_write_config_dword(bridge, 0x84, 0x0c); 346 pci_read_config_dword(bridge, 0x88, &tmp); 347 tmp &= ~(7 << 27); 348 tmp |= 2 << 27; /* set prefetch size to 128 bytes */ 349 pci_write_config_dword(bridge, 0x88, tmp); 350 break; 351 352 case PI7C9X110: /* Pericom PI7C9X110 PCIe/PCI bridge */ 353 pci_read_config_dword(bridge, 0x40, &tmp); 354 tmp |= 1; /* park the PCI arbiter to the sound chip */ 355 pci_write_config_dword(bridge, 0x40, tmp); 356 break; 357 358 case XIO2001: /* Texas Instruments XIO2001 PCIe/PCI bridge */ 359 pci_read_config_dword(bridge, 0xe8, &tmp); 360 tmp &= ~0xf; /* request length limit: 64 bytes */ 361 tmp &= ~(0xf << 8); 362 tmp |= 1 << 8; /* request count limit: one buffer */ 363 pci_write_config_dword(bridge, 0xe8, tmp); 364 break; 365 } 366 } 367 368 static void oxygen_init(struct oxygen *chip) 369 { 370 unsigned int i; 371 372 chip->dac_routing = 1; 373 for (i = 0; i < 8; ++i) 374 chip->dac_volume[i] = chip->model.dac_volume_min; 375 chip->dac_mute = 1; 376 chip->spdif_playback_enable = 1; 377 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL | 378 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT); 379 chip->spdif_pcm_bits = chip->spdif_bits; 380 381 if (!(oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)) 382 oxygen_set_bits8(chip, OXYGEN_MISC, 383 OXYGEN_MISC_PCI_MEM_W_1_CLOCK); 384 385 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL); 386 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0; 387 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0; 388 389 oxygen_write8_masked(chip, OXYGEN_FUNCTION, 390 OXYGEN_FUNCTION_RESET_CODEC | 391 chip->model.function_flags, 392 OXYGEN_FUNCTION_RESET_CODEC | 393 OXYGEN_FUNCTION_2WIRE_SPI_MASK | 394 OXYGEN_FUNCTION_ENABLE_SPI_4_5); 395 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0); 396 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0); 397 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS, 398 OXYGEN_PLAY_CHANNELS_2 | 399 OXYGEN_DMA_A_BURST_8 | 400 OXYGEN_DMA_MULTICH_BURST_8); 401 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 402 oxygen_write8_masked(chip, OXYGEN_MISC, 403 chip->model.misc_flags, 404 OXYGEN_MISC_WRITE_PCI_SUBID | 405 OXYGEN_MISC_REC_C_FROM_SPDIF | 406 OXYGEN_MISC_REC_B_FROM_AC97 | 407 OXYGEN_MISC_REC_A_FROM_MULTICH | 408 OXYGEN_MISC_MIDI); 409 oxygen_write8(chip, OXYGEN_REC_FORMAT, 410 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) | 411 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) | 412 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT)); 413 oxygen_write8(chip, OXYGEN_PLAY_FORMAT, 414 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) | 415 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT)); 416 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2); 417 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT, 418 OXYGEN_RATE_48000 | 419 chip->model.dac_i2s_format | 420 OXYGEN_I2S_MCLK(chip->model.dac_mclks) | 421 OXYGEN_I2S_BITS_16 | 422 OXYGEN_I2S_MASTER | 423 OXYGEN_I2S_BCLK_64); 424 if (chip->model.device_config & CAPTURE_0_FROM_I2S_1) 425 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 426 OXYGEN_RATE_48000 | 427 chip->model.adc_i2s_format | 428 OXYGEN_I2S_MCLK(chip->model.adc_mclks) | 429 OXYGEN_I2S_BITS_16 | 430 OXYGEN_I2S_MASTER | 431 OXYGEN_I2S_BCLK_64); 432 else 433 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT, 434 OXYGEN_I2S_MASTER | 435 OXYGEN_I2S_MUTE_MCLK); 436 if (chip->model.device_config & (CAPTURE_0_FROM_I2S_2 | 437 CAPTURE_2_FROM_I2S_2)) 438 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 439 OXYGEN_RATE_48000 | 440 chip->model.adc_i2s_format | 441 OXYGEN_I2S_MCLK(chip->model.adc_mclks) | 442 OXYGEN_I2S_BITS_16 | 443 OXYGEN_I2S_MASTER | 444 OXYGEN_I2S_BCLK_64); 445 else 446 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT, 447 OXYGEN_I2S_MASTER | 448 OXYGEN_I2S_MUTE_MCLK); 449 if (chip->model.device_config & CAPTURE_3_FROM_I2S_3) 450 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 451 OXYGEN_RATE_48000 | 452 chip->model.adc_i2s_format | 453 OXYGEN_I2S_MCLK(chip->model.adc_mclks) | 454 OXYGEN_I2S_BITS_16 | 455 OXYGEN_I2S_MASTER | 456 OXYGEN_I2S_BCLK_64); 457 else 458 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT, 459 OXYGEN_I2S_MASTER | 460 OXYGEN_I2S_MUTE_MCLK); 461 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, 462 OXYGEN_SPDIF_OUT_ENABLE | 463 OXYGEN_SPDIF_LOOPBACK); 464 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) 465 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL, 466 OXYGEN_SPDIF_SENSE_MASK | 467 OXYGEN_SPDIF_LOCK_MASK | 468 OXYGEN_SPDIF_RATE_MASK | 469 OXYGEN_SPDIF_LOCK_PAR | 470 OXYGEN_SPDIF_IN_CLOCK_96, 471 OXYGEN_SPDIF_SENSE_MASK | 472 OXYGEN_SPDIF_LOCK_MASK | 473 OXYGEN_SPDIF_RATE_MASK | 474 OXYGEN_SPDIF_SENSE_PAR | 475 OXYGEN_SPDIF_LOCK_PAR | 476 OXYGEN_SPDIF_IN_CLOCK_MASK); 477 else 478 oxygen_clear_bits32(chip, OXYGEN_SPDIF_CONTROL, 479 OXYGEN_SPDIF_SENSE_MASK | 480 OXYGEN_SPDIF_LOCK_MASK | 481 OXYGEN_SPDIF_RATE_MASK); 482 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits); 483 oxygen_write16(chip, OXYGEN_2WIRE_BUS_STATUS, 484 OXYGEN_2WIRE_LENGTH_8 | 485 OXYGEN_2WIRE_INTERRUPT_MASK | 486 OXYGEN_2WIRE_SPEED_STANDARD); 487 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK); 488 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0); 489 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0); 490 oxygen_write16(chip, OXYGEN_PLAY_ROUTING, 491 OXYGEN_PLAY_MULTICH_I2S_DAC | 492 OXYGEN_PLAY_SPDIF_SPDIF | 493 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) | 494 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) | 495 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) | 496 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT)); 497 oxygen_write8(chip, OXYGEN_REC_ROUTING, 498 OXYGEN_REC_A_ROUTE_I2S_ADC_1 | 499 OXYGEN_REC_B_ROUTE_I2S_ADC_2 | 500 OXYGEN_REC_C_ROUTE_SPDIF); 501 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0); 502 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING, 503 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) | 504 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) | 505 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) | 506 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT)); 507 508 if (chip->has_ac97_0 | chip->has_ac97_1) 509 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 510 OXYGEN_AC97_INT_READ_DONE | 511 OXYGEN_AC97_INT_WRITE_DONE); 512 else 513 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK, 0); 514 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0); 515 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0); 516 if (!(chip->has_ac97_0 | chip->has_ac97_1)) 517 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, 518 OXYGEN_AC97_CLOCK_DISABLE); 519 if (!chip->has_ac97_0) { 520 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL, 521 OXYGEN_AC97_NO_CODEC_0); 522 } else { 523 oxygen_write_ac97(chip, 0, AC97_RESET, 0); 524 msleep(1); 525 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP, 526 CM9780_GPIO0IO | CM9780_GPIO1IO); 527 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER, 528 CM9780_BSTSEL | CM9780_STRO_MIC | 529 CM9780_MIX2FR | CM9780_PCBSW); 530 oxygen_ac97_set_bits(chip, 0, CM9780_JACK, 531 CM9780_RSOE | CM9780_CBOE | 532 CM9780_SSOE | CM9780_FROE | 533 CM9780_MIC2MIC | CM9780_LI2LI); 534 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000); 535 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000); 536 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808); 537 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808); 538 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808); 539 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808); 540 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808); 541 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000); 542 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080); 543 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080); 544 oxygen_ac97_clear_bits(chip, 0, CM9780_GPIO_STATUS, 545 CM9780_GPO0); 546 /* power down unused ADCs and DACs */ 547 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN, 548 AC97_PD_PR0 | AC97_PD_PR1); 549 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS, 550 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK); 551 } 552 if (chip->has_ac97_1) { 553 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG, 554 OXYGEN_AC97_CODEC1_SLOT3 | 555 OXYGEN_AC97_CODEC1_SLOT4); 556 oxygen_write_ac97(chip, 1, AC97_RESET, 0); 557 msleep(1); 558 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000); 559 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000); 560 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000); 561 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808); 562 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808); 563 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808); 564 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808); 565 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808); 566 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808); 567 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000); 568 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000); 569 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040); 570 } 571 } 572 573 static void oxygen_shutdown(struct oxygen *chip) 574 { 575 spin_lock_irq(&chip->reg_lock); 576 chip->interrupt_mask = 0; 577 chip->pcm_running = 0; 578 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 579 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 580 spin_unlock_irq(&chip->reg_lock); 581 } 582 583 static void oxygen_card_free(struct snd_card *card) 584 { 585 struct oxygen *chip = card->private_data; 586 587 oxygen_shutdown(chip); 588 if (chip->irq >= 0) 589 free_irq(chip->irq, chip); 590 flush_work(&chip->spdif_input_bits_work); 591 flush_work(&chip->gpio_work); 592 chip->model.cleanup(chip); 593 kfree(chip->model_data); 594 mutex_destroy(&chip->mutex); 595 pci_release_regions(chip->pci); 596 pci_disable_device(chip->pci); 597 } 598 599 int oxygen_pci_probe(struct pci_dev *pci, int index, char *id, 600 struct module *owner, 601 const struct pci_device_id *ids, 602 int (*get_model)(struct oxygen *chip, 603 const struct pci_device_id *id 604 ) 605 ) 606 { 607 struct snd_card *card; 608 struct oxygen *chip; 609 const struct pci_device_id *pci_id; 610 int err; 611 612 err = snd_card_new(&pci->dev, index, id, owner, 613 sizeof(*chip), &card); 614 if (err < 0) 615 return err; 616 617 chip = card->private_data; 618 chip->card = card; 619 chip->pci = pci; 620 chip->irq = -1; 621 spin_lock_init(&chip->reg_lock); 622 mutex_init(&chip->mutex); 623 INIT_WORK(&chip->spdif_input_bits_work, 624 oxygen_spdif_input_bits_changed); 625 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed); 626 init_waitqueue_head(&chip->ac97_waitqueue); 627 628 err = pci_enable_device(pci); 629 if (err < 0) 630 goto err_card; 631 632 err = pci_request_regions(pci, DRIVER); 633 if (err < 0) { 634 dev_err(card->dev, "cannot reserve PCI resources\n"); 635 goto err_pci_enable; 636 } 637 638 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) || 639 pci_resource_len(pci, 0) < OXYGEN_IO_SIZE) { 640 dev_err(card->dev, "invalid PCI I/O range\n"); 641 err = -ENXIO; 642 goto err_pci_regions; 643 } 644 chip->addr = pci_resource_start(pci, 0); 645 646 pci_id = oxygen_search_pci_id(chip, ids); 647 if (!pci_id) { 648 err = -ENODEV; 649 goto err_pci_regions; 650 } 651 oxygen_restore_eeprom(chip, pci_id); 652 err = get_model(chip, pci_id); 653 if (err < 0) 654 goto err_pci_regions; 655 656 if (chip->model.model_data_size) { 657 chip->model_data = kzalloc(chip->model.model_data_size, 658 GFP_KERNEL); 659 if (!chip->model_data) { 660 err = -ENOMEM; 661 goto err_pci_regions; 662 } 663 } 664 665 pci_set_master(pci); 666 card->private_free = oxygen_card_free; 667 668 configure_pcie_bridge(pci); 669 oxygen_init(chip); 670 chip->model.init(chip); 671 672 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED, 673 KBUILD_MODNAME, chip); 674 if (err < 0) { 675 dev_err(card->dev, "cannot grab interrupt %d\n", pci->irq); 676 goto err_card; 677 } 678 chip->irq = pci->irq; 679 680 strcpy(card->driver, chip->model.chip); 681 strcpy(card->shortname, chip->model.shortname); 682 sprintf(card->longname, "%s at %#lx, irq %i", 683 chip->model.longname, chip->addr, chip->irq); 684 strcpy(card->mixername, chip->model.chip); 685 snd_component_add(card, chip->model.chip); 686 687 err = oxygen_pcm_init(chip); 688 if (err < 0) 689 goto err_card; 690 691 err = oxygen_mixer_init(chip); 692 if (err < 0) 693 goto err_card; 694 695 if (chip->model.device_config & (MIDI_OUTPUT | MIDI_INPUT)) { 696 unsigned int info_flags = 697 MPU401_INFO_INTEGRATED | MPU401_INFO_IRQ_HOOK; 698 if (chip->model.device_config & MIDI_OUTPUT) 699 info_flags |= MPU401_INFO_OUTPUT; 700 if (chip->model.device_config & MIDI_INPUT) 701 info_flags |= MPU401_INFO_INPUT; 702 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI, 703 chip->addr + OXYGEN_MPU401, 704 info_flags, -1, &chip->midi); 705 if (err < 0) 706 goto err_card; 707 } 708 709 oxygen_proc_init(chip); 710 711 spin_lock_irq(&chip->reg_lock); 712 if (chip->model.device_config & CAPTURE_1_FROM_SPDIF) 713 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT; 714 if (chip->has_ac97_0 | chip->has_ac97_1) 715 chip->interrupt_mask |= OXYGEN_INT_AC97; 716 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 717 spin_unlock_irq(&chip->reg_lock); 718 719 err = snd_card_register(card); 720 if (err < 0) 721 goto err_card; 722 723 pci_set_drvdata(pci, card); 724 return 0; 725 726 err_pci_regions: 727 pci_release_regions(pci); 728 err_pci_enable: 729 pci_disable_device(pci); 730 err_card: 731 snd_card_free(card); 732 return err; 733 } 734 EXPORT_SYMBOL(oxygen_pci_probe); 735 736 void oxygen_pci_remove(struct pci_dev *pci) 737 { 738 snd_card_free(pci_get_drvdata(pci)); 739 } 740 EXPORT_SYMBOL(oxygen_pci_remove); 741 742 #ifdef CONFIG_PM_SLEEP 743 static int oxygen_pci_suspend(struct device *dev) 744 { 745 struct snd_card *card = dev_get_drvdata(dev); 746 struct oxygen *chip = card->private_data; 747 unsigned int i, saved_interrupt_mask; 748 749 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 750 751 for (i = 0; i < PCM_COUNT; ++i) 752 snd_pcm_suspend(chip->streams[i]); 753 754 if (chip->model.suspend) 755 chip->model.suspend(chip); 756 757 spin_lock_irq(&chip->reg_lock); 758 saved_interrupt_mask = chip->interrupt_mask; 759 chip->interrupt_mask = 0; 760 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 761 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 762 spin_unlock_irq(&chip->reg_lock); 763 764 synchronize_irq(chip->irq); 765 flush_work(&chip->spdif_input_bits_work); 766 flush_work(&chip->gpio_work); 767 chip->interrupt_mask = saved_interrupt_mask; 768 return 0; 769 } 770 771 static const u32 registers_to_restore[OXYGEN_IO_SIZE / 32] = { 772 0xffffffff, 0x00ff077f, 0x00011d08, 0x007f00ff, 773 0x00300000, 0x00000fe4, 0x0ff7001f, 0x00000000 774 }; 775 static const u32 ac97_registers_to_restore[2][0x40 / 32] = { 776 { 0x18284fa2, 0x03060000 }, 777 { 0x00007fa6, 0x00200000 } 778 }; 779 780 static inline int is_bit_set(const u32 *bitmap, unsigned int bit) 781 { 782 return bitmap[bit / 32] & (1 << (bit & 31)); 783 } 784 785 static void oxygen_restore_ac97(struct oxygen *chip, unsigned int codec) 786 { 787 unsigned int i; 788 789 oxygen_write_ac97(chip, codec, AC97_RESET, 0); 790 msleep(1); 791 for (i = 1; i < 0x40; ++i) 792 if (is_bit_set(ac97_registers_to_restore[codec], i)) 793 oxygen_write_ac97(chip, codec, i * 2, 794 chip->saved_ac97_registers[codec][i]); 795 } 796 797 static int oxygen_pci_resume(struct device *dev) 798 { 799 struct snd_card *card = dev_get_drvdata(dev); 800 struct oxygen *chip = card->private_data; 801 unsigned int i; 802 803 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0); 804 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0); 805 for (i = 0; i < OXYGEN_IO_SIZE; ++i) 806 if (is_bit_set(registers_to_restore, i)) 807 oxygen_write8(chip, i, chip->saved_registers._8[i]); 808 if (chip->has_ac97_0) 809 oxygen_restore_ac97(chip, 0); 810 if (chip->has_ac97_1) 811 oxygen_restore_ac97(chip, 1); 812 813 if (chip->model.resume) 814 chip->model.resume(chip); 815 816 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask); 817 818 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 819 return 0; 820 } 821 822 SIMPLE_DEV_PM_OPS(oxygen_pci_pm, oxygen_pci_suspend, oxygen_pci_resume); 823 EXPORT_SYMBOL(oxygen_pci_pm); 824 #endif /* CONFIG_PM_SLEEP */ 825 826 void oxygen_pci_shutdown(struct pci_dev *pci) 827 { 828 struct snd_card *card = pci_get_drvdata(pci); 829 struct oxygen *chip = card->private_data; 830 831 oxygen_shutdown(chip); 832 chip->model.cleanup(chip); 833 } 834 EXPORT_SYMBOL(oxygen_pci_shutdown); 835