1 /* -*- linux-c -*- * 2 * 3 * ALSA driver for the digigram lx6464es interface 4 * low-level interface 5 * 6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, 21 * Boston, MA 02111-1307, USA. 22 * 23 */ 24 25 /* #define RMH_DEBUG 1 */ 26 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 31 #include "lx6464es.h" 32 #include "lx_core.h" 33 34 /* low-level register access */ 35 36 static const unsigned long dsp_port_offsets[] = { 37 0, 38 0x400, 39 0x401, 40 0x402, 41 0x403, 42 0x404, 43 0x405, 44 0x406, 45 0x407, 46 0x408, 47 0x409, 48 0x40a, 49 0x40b, 50 0x40c, 51 52 0x410, 53 0x411, 54 0x412, 55 0x413, 56 0x414, 57 0x415, 58 0x416, 59 60 0x420, 61 0x430, 62 0x431, 63 0x432, 64 0x433, 65 0x434, 66 0x440 67 }; 68 69 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port) 70 { 71 void __iomem *base_address = chip->port_dsp_bar; 72 return base_address + dsp_port_offsets[port]*4; 73 } 74 75 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port) 76 { 77 void __iomem *address = lx_dsp_register(chip, port); 78 return ioread32(address); 79 } 80 81 void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, u32 len) 82 { 83 void __iomem *address = lx_dsp_register(chip, port); 84 memcpy_fromio(data, address, len*sizeof(u32)); 85 } 86 87 88 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data) 89 { 90 void __iomem *address = lx_dsp_register(chip, port); 91 iowrite32(data, address); 92 } 93 94 void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, const u32 *data, 95 u32 len) 96 { 97 void __iomem *address = lx_dsp_register(chip, port); 98 memcpy_toio(address, data, len*sizeof(u32)); 99 } 100 101 102 static const unsigned long plx_port_offsets[] = { 103 0x04, 104 0x40, 105 0x44, 106 0x48, 107 0x4c, 108 0x50, 109 0x54, 110 0x58, 111 0x5c, 112 0x64, 113 0x68, 114 0x6C 115 }; 116 117 static void __iomem *lx_plx_register(struct lx6464es *chip, int port) 118 { 119 void __iomem *base_address = chip->port_plx_remapped; 120 return base_address + plx_port_offsets[port]; 121 } 122 123 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port) 124 { 125 void __iomem *address = lx_plx_register(chip, port); 126 return ioread32(address); 127 } 128 129 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data) 130 { 131 void __iomem *address = lx_plx_register(chip, port); 132 iowrite32(data, address); 133 } 134 135 u32 lx_plx_mbox_read(struct lx6464es *chip, int mbox_nr) 136 { 137 int index; 138 139 switch (mbox_nr) { 140 case 1: 141 index = ePLX_MBOX1; break; 142 case 2: 143 index = ePLX_MBOX2; break; 144 case 3: 145 index = ePLX_MBOX3; break; 146 case 4: 147 index = ePLX_MBOX4; break; 148 case 5: 149 index = ePLX_MBOX5; break; 150 case 6: 151 index = ePLX_MBOX6; break; 152 case 7: 153 index = ePLX_MBOX7; break; 154 case 0: /* reserved for HF flags */ 155 snd_BUG(); 156 default: 157 return 0xdeadbeef; 158 } 159 160 return lx_plx_reg_read(chip, index); 161 } 162 163 int lx_plx_mbox_write(struct lx6464es *chip, int mbox_nr, u32 value) 164 { 165 int index = -1; 166 167 switch (mbox_nr) { 168 case 1: 169 index = ePLX_MBOX1; break; 170 case 3: 171 index = ePLX_MBOX3; break; 172 case 4: 173 index = ePLX_MBOX4; break; 174 case 5: 175 index = ePLX_MBOX5; break; 176 case 6: 177 index = ePLX_MBOX6; break; 178 case 7: 179 index = ePLX_MBOX7; break; 180 case 0: /* reserved for HF flags */ 181 case 2: /* reserved for Pipe States 182 * the DSP keeps an image of it */ 183 snd_BUG(); 184 return -EBADRQC; 185 } 186 187 lx_plx_reg_write(chip, index, value); 188 return 0; 189 } 190 191 192 /* rmh */ 193 194 #ifdef CONFIG_SND_DEBUG 195 #define CMD_NAME(a) a 196 #else 197 #define CMD_NAME(a) NULL 198 #endif 199 200 #define Reg_CSM_MR 0x00000002 201 #define Reg_CSM_MC 0x00000001 202 203 struct dsp_cmd_info { 204 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits 205 * word).*/ 206 u16 dcCmdLength; /* Command length in words of 24 bits.*/ 207 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for 208 * random. */ 209 u16 dcStatusLength; /* Status length (if fixed).*/ 210 char *dcOpName; 211 }; 212 213 /* 214 Initialization and control data for the Microblaze interface 215 - OpCode: 216 the opcode field of the command set at the proper offset 217 - CmdLength 218 the number of command words 219 - StatusType 220 offset in the status registers: 0 means that the return value may be 221 different from 0, and must be read 222 - StatusLength 223 the number of status words (in addition to the return value) 224 */ 225 226 static struct dsp_cmd_info dsp_commands[] = 227 { 228 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/ 229 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") }, 230 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/ 231 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") }, 232 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/ 233 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") }, 234 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/ 235 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") }, 236 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/ 237 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") }, 238 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/ 239 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") }, 240 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/ 241 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") }, 242 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/ 243 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") }, 244 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/ 245 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") }, 246 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/ 247 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") }, 248 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/ 249 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") }, 250 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/ 251 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") }, 252 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/ 253 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") }, 254 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/ 255 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") }, 256 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/ 257 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") }, 258 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/ 259 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") }, 260 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/ 261 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") }, 262 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/ 263 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") }, 264 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/ 265 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") }, 266 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/ 267 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") }, 268 }; 269 270 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd) 271 { 272 snd_BUG_ON(cmd >= CMD_14_INVALID); 273 274 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; 275 rmh->cmd_len = dsp_commands[cmd].dcCmdLength; 276 rmh->stat_len = dsp_commands[cmd].dcStatusLength; 277 rmh->dsp_stat = dsp_commands[cmd].dcStatusType; 278 rmh->cmd_idx = cmd; 279 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); 280 281 #ifdef CONFIG_SND_DEBUG 282 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); 283 #endif 284 #ifdef RMH_DEBUG 285 rmh->cmd_idx = cmd; 286 #endif 287 } 288 289 #ifdef RMH_DEBUG 290 #define LXRMH "lx6464es rmh: " 291 static void lx_message_dump(struct lx_rmh *rmh) 292 { 293 u8 idx = rmh->cmd_idx; 294 int i; 295 296 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName); 297 298 for (i = 0; i != rmh->cmd_len; ++i) 299 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]); 300 301 for (i = 0; i != rmh->stat_len; ++i) 302 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]); 303 snd_printk("\n"); 304 } 305 #else 306 static inline void lx_message_dump(struct lx_rmh *rmh) 307 {} 308 #endif 309 310 311 312 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */ 313 #define XILINX_TIMEOUT_MS 40 314 #define XILINX_POLL_NO_SLEEP 100 315 #define XILINX_POLL_ITERATIONS 150 316 317 #if 0 /* not used now */ 318 static int lx_message_send(struct lx6464es *chip, struct lx_rmh *rmh) 319 { 320 u32 reg = ED_DSP_TIMED_OUT; 321 int dwloop; 322 int answer_received; 323 324 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { 325 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg); 326 return -EBUSY; 327 } 328 329 /* write command */ 330 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); 331 332 snd_BUG_ON(atomic_read(&chip->send_message_locked) != 0); 333 atomic_set(&chip->send_message_locked, 1); 334 335 /* MicoBlaze gogogo */ 336 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); 337 338 /* wait for interrupt to answer */ 339 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS; ++dwloop) { 340 answer_received = atomic_read(&chip->send_message_locked); 341 if (answer_received == 0) 342 break; 343 msleep(1); 344 } 345 346 if (answer_received == 0) { 347 /* in Debug mode verify Reg_CSM_MR */ 348 snd_BUG_ON(!(lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR)); 349 350 /* command finished, read status */ 351 if (rmh->dsp_stat == 0) 352 reg = lx_dsp_reg_read(chip, eReg_CRM1); 353 else 354 reg = 0; 355 } else { 356 int i; 357 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! " 358 "Interrupts disabled?\n"); 359 360 /* attente bit Reg_CSM_MR */ 361 for (i = 0; i != XILINX_POLL_ITERATIONS; i++) { 362 if ((lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR)) { 363 if (rmh->dsp_stat == 0) 364 reg = lx_dsp_reg_read(chip, eReg_CRM1); 365 else 366 reg = 0; 367 goto polling_successful; 368 } 369 370 if (i > XILINX_POLL_NO_SLEEP) 371 msleep(1); 372 } 373 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send! " 374 "polling failed\n"); 375 376 polling_successful: 377 atomic_set(&chip->send_message_locked, 0); 378 } 379 380 if ((reg & ERROR_VALUE) == 0) { 381 /* read response */ 382 if (rmh->stat_len) { 383 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); 384 385 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, 386 rmh->stat_len); 387 } 388 } else 389 snd_printk(KERN_WARNING LXP "lx_message_send: error_value %x\n", 390 reg); 391 392 /* clear Reg_CSM_MR */ 393 lx_dsp_reg_write(chip, eReg_CSM, 0); 394 395 switch (reg) { 396 case ED_DSP_TIMED_OUT: 397 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n"); 398 return -ETIMEDOUT; 399 400 case ED_DSP_CRASHED: 401 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n"); 402 return -EAGAIN; 403 } 404 405 lx_message_dump(rmh); 406 return 0; 407 } 408 #endif /* not used now */ 409 410 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh) 411 { 412 u32 reg = ED_DSP_TIMED_OUT; 413 int dwloop; 414 415 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { 416 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg); 417 return -EBUSY; 418 } 419 420 /* write command */ 421 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); 422 423 /* MicoBlaze gogogo */ 424 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); 425 426 /* wait for interrupt to answer */ 427 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { 428 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) { 429 if (rmh->dsp_stat == 0) 430 reg = lx_dsp_reg_read(chip, eReg_CRM1); 431 else 432 reg = 0; 433 goto polling_successful; 434 } else 435 udelay(1); 436 } 437 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send_atomic! " 438 "polling failed\n"); 439 440 polling_successful: 441 if ((reg & ERROR_VALUE) == 0) { 442 /* read response */ 443 if (rmh->stat_len) { 444 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); 445 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, 446 rmh->stat_len); 447 } 448 } else 449 snd_printk(LXP "rmh error: %08x\n", reg); 450 451 /* clear Reg_CSM_MR */ 452 lx_dsp_reg_write(chip, eReg_CSM, 0); 453 454 switch (reg) { 455 case ED_DSP_TIMED_OUT: 456 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n"); 457 return -ETIMEDOUT; 458 459 case ED_DSP_CRASHED: 460 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n"); 461 return -EAGAIN; 462 } 463 464 lx_message_dump(rmh); 465 466 return reg; 467 } 468 469 470 /* low-level dsp access */ 471 int __devinit lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) 472 { 473 u16 ret; 474 unsigned long flags; 475 476 spin_lock_irqsave(&chip->msg_lock, flags); 477 478 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 479 ret = lx_message_send_atomic(chip, &chip->rmh); 480 481 *rdsp_version = chip->rmh.stat[1]; 482 spin_unlock_irqrestore(&chip->msg_lock, flags); 483 return ret; 484 } 485 486 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) 487 { 488 u16 ret = 0; 489 unsigned long flags; 490 u32 freq_raw = 0; 491 u32 freq = 0; 492 u32 frequency = 0; 493 494 spin_lock_irqsave(&chip->msg_lock, flags); 495 496 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 497 ret = lx_message_send_atomic(chip, &chip->rmh); 498 499 if (ret == 0) { 500 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; 501 freq = freq_raw & XES_FREQ_COUNT8_MASK; 502 503 if ((freq < XES_FREQ_COUNT8_48_MAX) || 504 (freq > XES_FREQ_COUNT8_44_MIN)) 505 frequency = 0; /* unknown */ 506 else if (freq >= XES_FREQ_COUNT8_44_MAX) 507 frequency = 44100; 508 else 509 frequency = 48000; 510 } 511 512 spin_unlock_irqrestore(&chip->msg_lock, flags); 513 514 *rfreq = frequency * chip->freq_ratio; 515 516 return ret; 517 } 518 519 int lx_dsp_get_mac(struct lx6464es *chip, u8 *mac_address) 520 { 521 u32 macmsb, maclsb; 522 523 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; 524 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; 525 526 /* todo: endianess handling */ 527 mac_address[5] = ((u8 *)(&maclsb))[0]; 528 mac_address[4] = ((u8 *)(&maclsb))[1]; 529 mac_address[3] = ((u8 *)(&maclsb))[2]; 530 mac_address[2] = ((u8 *)(&macmsb))[0]; 531 mac_address[1] = ((u8 *)(&macmsb))[1]; 532 mac_address[0] = ((u8 *)(&macmsb))[2]; 533 534 return 0; 535 } 536 537 538 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran) 539 { 540 unsigned long flags; 541 int ret; 542 543 spin_lock_irqsave(&chip->msg_lock, flags); 544 545 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY); 546 chip->rmh.cmd[0] |= gran; 547 548 ret = lx_message_send_atomic(chip, &chip->rmh); 549 spin_unlock_irqrestore(&chip->msg_lock, flags); 550 return ret; 551 } 552 553 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data) 554 { 555 unsigned long flags; 556 int ret; 557 558 spin_lock_irqsave(&chip->msg_lock, flags); 559 560 lx_message_init(&chip->rmh, CMD_04_GET_EVENT); 561 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */ 562 563 ret = lx_message_send_atomic(chip, &chip->rmh); 564 565 if (!ret) 566 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32)); 567 568 spin_unlock_irqrestore(&chip->msg_lock, flags); 569 return ret; 570 } 571 572 #define CSES_TIMEOUT 100 /* microseconds */ 573 #define CSES_CE 0x0001 574 #define CSES_BROADCAST 0x0002 575 #define CSES_UPDATE_LDSV 0x0004 576 577 int lx_dsp_es_check_pipeline(struct lx6464es *chip) 578 { 579 int i; 580 581 for (i = 0; i != CSES_TIMEOUT; ++i) { 582 /* 583 * le bit CSES_UPDATE_LDSV est à 1 dés que le macprog 584 * est pret. il re-passe à 0 lorsque le premier read a 585 * été fait. pour l'instant on retire le test car ce bit 586 * passe a 1 environ 200 à 400 ms aprés que le registre 587 * confES à été écrit (kick du xilinx ES). 588 * 589 * On ne teste que le bit CE. 590 * */ 591 592 u32 cses = lx_dsp_reg_read(chip, eReg_CSES); 593 594 if ((cses & CSES_CE) == 0) 595 return 0; 596 597 udelay(1); 598 } 599 600 return -ETIMEDOUT; 601 } 602 603 604 #define PIPE_INFO_TO_CMD(capture, pipe) \ 605 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET) 606 607 608 609 /* low-level pipe handling */ 610 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, 611 int channels) 612 { 613 int err; 614 unsigned long flags; 615 616 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 617 618 spin_lock_irqsave(&chip->msg_lock, flags); 619 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE); 620 621 chip->rmh.cmd[0] |= pipe_cmd; 622 chip->rmh.cmd[0] |= channels; 623 624 err = lx_message_send_atomic(chip, &chip->rmh); 625 spin_unlock_irqrestore(&chip->msg_lock, flags); 626 627 if (err != 0) 628 snd_printk(KERN_ERR "lx6464es: could not allocate pipe\n"); 629 630 return err; 631 } 632 633 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture) 634 { 635 int err; 636 unsigned long flags; 637 638 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 639 640 spin_lock_irqsave(&chip->msg_lock, flags); 641 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE); 642 643 chip->rmh.cmd[0] |= pipe_cmd; 644 645 err = lx_message_send_atomic(chip, &chip->rmh); 646 spin_unlock_irqrestore(&chip->msg_lock, flags); 647 648 return err; 649 } 650 651 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, 652 u32 *r_needed, u32 *r_freed, u32 *size_array) 653 { 654 int err; 655 unsigned long flags; 656 657 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 658 659 #ifdef CONFIG_SND_DEBUG 660 if (size_array) 661 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); 662 #endif 663 664 *r_needed = 0; 665 *r_freed = 0; 666 667 spin_lock_irqsave(&chip->msg_lock, flags); 668 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS); 669 670 chip->rmh.cmd[0] |= pipe_cmd; 671 672 err = lx_message_send_atomic(chip, &chip->rmh); 673 674 if (!err) { 675 int i; 676 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 677 u32 stat = chip->rmh.stat[i]; 678 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) { 679 /* finished */ 680 *r_freed += 1; 681 if (size_array) 682 size_array[i] = stat & MASK_DATA_SIZE; 683 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET)) 684 == 0) 685 /* free */ 686 *r_needed += 1; 687 } 688 689 #if 0 690 snd_printdd(LXP "CMD_08_ASK_BUFFERS: needed %d, freed %d\n", 691 *r_needed, *r_freed); 692 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 693 for (i = 0; i != chip->rmh.stat_len; ++i) 694 snd_printdd(" stat[%d]: %x, %x\n", i, 695 chip->rmh.stat[i], 696 chip->rmh.stat[i] & MASK_DATA_SIZE); 697 } 698 #endif 699 } 700 701 spin_unlock_irqrestore(&chip->msg_lock, flags); 702 return err; 703 } 704 705 706 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture) 707 { 708 int err; 709 unsigned long flags; 710 711 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 712 713 spin_lock_irqsave(&chip->msg_lock, flags); 714 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE); 715 716 chip->rmh.cmd[0] |= pipe_cmd; 717 718 err = lx_message_send_atomic(chip, &chip->rmh); 719 720 spin_unlock_irqrestore(&chip->msg_lock, flags); 721 return err; 722 } 723 724 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture) 725 { 726 int err; 727 unsigned long flags; 728 729 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 730 731 spin_lock_irqsave(&chip->msg_lock, flags); 732 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE); 733 734 chip->rmh.cmd[0] |= pipe_cmd; 735 736 err = lx_message_send_atomic(chip, &chip->rmh); 737 738 spin_unlock_irqrestore(&chip->msg_lock, flags); 739 return err; 740 } 741 742 743 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture) 744 { 745 int err; 746 747 err = lx_pipe_wait_for_idle(chip, pipe, is_capture); 748 if (err < 0) 749 return err; 750 751 err = lx_pipe_toggle_state(chip, pipe, is_capture); 752 753 return err; 754 } 755 756 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture) 757 { 758 int err = 0; 759 760 err = lx_pipe_wait_for_start(chip, pipe, is_capture); 761 if (err < 0) 762 return err; 763 764 err = lx_pipe_toggle_state(chip, pipe, is_capture); 765 766 return err; 767 } 768 769 770 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, 771 u64 *rsample_count) 772 { 773 int err; 774 unsigned long flags; 775 776 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 777 778 spin_lock_irqsave(&chip->msg_lock, flags); 779 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 780 781 chip->rmh.cmd[0] |= pipe_cmd; 782 chip->rmh.stat_len = 2; /* need all words here! */ 783 784 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */ 785 786 if (err != 0) 787 snd_printk(KERN_ERR 788 "lx6464es: could not query pipe's sample count\n"); 789 else { 790 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 791 << 24) /* hi part */ 792 + chip->rmh.stat[1]; /* lo part */ 793 } 794 795 spin_unlock_irqrestore(&chip->msg_lock, flags); 796 return err; 797 } 798 799 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate) 800 { 801 int err; 802 unsigned long flags; 803 804 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 805 806 spin_lock_irqsave(&chip->msg_lock, flags); 807 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 808 809 chip->rmh.cmd[0] |= pipe_cmd; 810 811 err = lx_message_send_atomic(chip, &chip->rmh); 812 813 if (err != 0) 814 snd_printk(KERN_ERR "lx6464es: could not query pipe's state\n"); 815 else 816 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; 817 818 spin_unlock_irqrestore(&chip->msg_lock, flags); 819 return err; 820 } 821 822 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe, 823 int is_capture, u16 state) 824 { 825 int i; 826 827 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms: 828 * timeout 50 ms */ 829 for (i = 0; i != 50; ++i) { 830 u16 current_state; 831 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state); 832 833 if (err < 0) 834 return err; 835 836 if (current_state == state) 837 return 0; 838 839 mdelay(1); 840 } 841 842 return -ETIMEDOUT; 843 } 844 845 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture) 846 { 847 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN); 848 } 849 850 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture) 851 { 852 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE); 853 } 854 855 /* low-level stream handling */ 856 int lx_stream_set_state(struct lx6464es *chip, u32 pipe, 857 int is_capture, enum stream_state_t state) 858 { 859 int err; 860 unsigned long flags; 861 862 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 863 864 spin_lock_irqsave(&chip->msg_lock, flags); 865 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE); 866 867 chip->rmh.cmd[0] |= pipe_cmd; 868 chip->rmh.cmd[0] |= state; 869 870 err = lx_message_send_atomic(chip, &chip->rmh); 871 spin_unlock_irqrestore(&chip->msg_lock, flags); 872 873 return err; 874 } 875 876 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, 877 u32 pipe, int is_capture) 878 { 879 int err; 880 unsigned long flags; 881 882 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 883 884 u32 channels = runtime->channels; 885 886 if (runtime->channels != channels) 887 snd_printk(KERN_ERR LXP "channel count mismatch: %d vs %d", 888 runtime->channels, channels); 889 890 spin_lock_irqsave(&chip->msg_lock, flags); 891 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM); 892 893 chip->rmh.cmd[0] |= pipe_cmd; 894 895 if (runtime->sample_bits == 16) 896 /* 16 bit format */ 897 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); 898 899 if (snd_pcm_format_little_endian(runtime->format)) 900 /* little endian/intel format */ 901 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); 902 903 chip->rmh.cmd[0] |= channels-1; 904 905 err = lx_message_send_atomic(chip, &chip->rmh); 906 spin_unlock_irqrestore(&chip->msg_lock, flags); 907 908 return err; 909 } 910 911 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, 912 int *rstate) 913 { 914 int err; 915 unsigned long flags; 916 917 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 918 919 spin_lock_irqsave(&chip->msg_lock, flags); 920 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 921 922 chip->rmh.cmd[0] |= pipe_cmd; 923 924 err = lx_message_send_atomic(chip, &chip->rmh); 925 926 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; 927 928 spin_unlock_irqrestore(&chip->msg_lock, flags); 929 return err; 930 } 931 932 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, 933 u64 *r_bytepos) 934 { 935 int err; 936 unsigned long flags; 937 938 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 939 940 spin_lock_irqsave(&chip->msg_lock, flags); 941 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 942 943 chip->rmh.cmd[0] |= pipe_cmd; 944 945 err = lx_message_send_atomic(chip, &chip->rmh); 946 947 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 948 << 32) /* hi part */ 949 + chip->rmh.stat[1]; /* lo part */ 950 951 spin_unlock_irqrestore(&chip->msg_lock, flags); 952 return err; 953 } 954 955 /* low-level buffer handling */ 956 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, 957 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, 958 u32 *r_buffer_index) 959 { 960 int err; 961 unsigned long flags; 962 963 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 964 965 spin_lock_irqsave(&chip->msg_lock, flags); 966 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER); 967 968 chip->rmh.cmd[0] |= pipe_cmd; 969 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ 970 971 /* todo: pause request, circular buffer */ 972 973 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE; 974 chip->rmh.cmd[2] = buf_address_lo; 975 976 if (buf_address_hi) { 977 chip->rmh.cmd_len = 4; 978 chip->rmh.cmd[3] = buf_address_hi; 979 chip->rmh.cmd[0] |= BF_64BITS_ADR; 980 } 981 982 err = lx_message_send_atomic(chip, &chip->rmh); 983 984 if (err == 0) { 985 *r_buffer_index = chip->rmh.stat[0]; 986 goto done; 987 } 988 989 if (err == EB_RBUFFERS_TABLE_OVERFLOW) 990 snd_printk(LXP "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n"); 991 992 if (err == EB_INVALID_STREAM) 993 snd_printk(LXP "lx_buffer_give EB_INVALID_STREAM\n"); 994 995 if (err == EB_CMD_REFUSED) 996 snd_printk(LXP "lx_buffer_give EB_CMD_REFUSED\n"); 997 998 done: 999 spin_unlock_irqrestore(&chip->msg_lock, flags); 1000 return err; 1001 } 1002 1003 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, 1004 u32 *r_buffer_size) 1005 { 1006 int err; 1007 unsigned long flags; 1008 1009 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 1010 1011 spin_lock_irqsave(&chip->msg_lock, flags); 1012 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 1013 1014 chip->rmh.cmd[0] |= pipe_cmd; 1015 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the 1016 * microblaze will seek for it */ 1017 1018 err = lx_message_send_atomic(chip, &chip->rmh); 1019 1020 if (err == 0) 1021 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; 1022 1023 spin_unlock_irqrestore(&chip->msg_lock, flags); 1024 return err; 1025 } 1026 1027 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, 1028 u32 buffer_index) 1029 { 1030 int err; 1031 unsigned long flags; 1032 1033 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 1034 1035 spin_lock_irqsave(&chip->msg_lock, flags); 1036 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 1037 1038 chip->rmh.cmd[0] |= pipe_cmd; 1039 chip->rmh.cmd[0] |= buffer_index; 1040 1041 err = lx_message_send_atomic(chip, &chip->rmh); 1042 1043 spin_unlock_irqrestore(&chip->msg_lock, flags); 1044 return err; 1045 } 1046 1047 1048 /* low-level gain/peak handling 1049 * 1050 * \todo: can we unmute capture/playback channels independently? 1051 * 1052 * */ 1053 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute) 1054 { 1055 int err; 1056 unsigned long flags; 1057 1058 /* bit set to 1: channel muted */ 1059 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; 1060 1061 spin_lock_irqsave(&chip->msg_lock, flags); 1062 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE); 1063 1064 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); 1065 1066 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */ 1067 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ 1068 1069 snd_printk("mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], 1070 chip->rmh.cmd[2]); 1071 1072 err = lx_message_send_atomic(chip, &chip->rmh); 1073 1074 spin_unlock_irqrestore(&chip->msg_lock, flags); 1075 return err; 1076 } 1077 1078 static u32 peak_map[] = { 1079 0x00000109, /* -90.308dB */ 1080 0x0000083B, /* -72.247dB */ 1081 0x000020C4, /* -60.205dB */ 1082 0x00008273, /* -48.030dB */ 1083 0x00020756, /* -36.005dB */ 1084 0x00040C37, /* -30.001dB */ 1085 0x00081385, /* -24.002dB */ 1086 0x00101D3F, /* -18.000dB */ 1087 0x0016C310, /* -15.000dB */ 1088 0x002026F2, /* -12.001dB */ 1089 0x002D6A86, /* -9.000dB */ 1090 0x004026E6, /* -6.004dB */ 1091 0x005A9DF6, /* -3.000dB */ 1092 0x0065AC8B, /* -2.000dB */ 1093 0x00721481, /* -1.000dB */ 1094 0x007FFFFF, /* FS */ 1095 }; 1096 1097 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, 1098 u32 *r_levels) 1099 { 1100 int err = 0; 1101 unsigned long flags; 1102 int i; 1103 spin_lock_irqsave(&chip->msg_lock, flags); 1104 1105 for (i = 0; i < channels; i += 4) { 1106 u32 s0, s1, s2, s3; 1107 1108 lx_message_init(&chip->rmh, CMD_12_GET_PEAK); 1109 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); 1110 1111 err = lx_message_send_atomic(chip, &chip->rmh); 1112 1113 if (err == 0) { 1114 s0 = peak_map[chip->rmh.stat[0] & 0x0F]; 1115 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; 1116 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; 1117 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; 1118 } else 1119 s0 = s1 = s2 = s3 = 0; 1120 1121 r_levels[0] = s0; 1122 r_levels[1] = s1; 1123 r_levels[2] = s2; 1124 r_levels[3] = s3; 1125 1126 r_levels += 4; 1127 } 1128 1129 spin_unlock_irqrestore(&chip->msg_lock, flags); 1130 return err; 1131 } 1132 1133 /* interrupt handling */ 1134 #define PCX_IRQ_NONE 0 1135 #define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit nø 13 */ 1136 #define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit nø 08 */ 1137 #define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit nø 09 */ 1138 1139 static u32 lx_interrupt_test_ack(struct lx6464es *chip) 1140 { 1141 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS); 1142 1143 /* Test if PCI Doorbell interrupt is active */ 1144 if (irqcs & IRQCS_ACTIVE_PCIDB) { 1145 u32 temp; 1146 irqcs = PCX_IRQ_NONE; 1147 1148 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) { 1149 /* RAZ interrupt */ 1150 irqcs |= temp; 1151 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp); 1152 } 1153 1154 return irqcs; 1155 } 1156 return PCX_IRQ_NONE; 1157 } 1158 1159 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc, 1160 int *r_async_pending, int *r_async_escmd) 1161 { 1162 u32 irq_async; 1163 u32 irqsrc = lx_interrupt_test_ack(chip); 1164 1165 if (irqsrc == PCX_IRQ_NONE) 1166 return 0; 1167 1168 *r_irqsrc = irqsrc; 1169 1170 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response 1171 * (set by xilinx) + EOB */ 1172 1173 if (irq_async & MASK_SYS_STATUS_ESA) { 1174 irq_async &= ~MASK_SYS_STATUS_ESA; 1175 *r_async_escmd = 1; 1176 } 1177 1178 if (irqsrc & MASK_SYS_STATUS_CMD_DONE) 1179 /* xilinx command notification */ 1180 atomic_set(&chip->send_message_locked, 0); 1181 1182 if (irq_async) { 1183 /* snd_printd("interrupt: async event pending\n"); */ 1184 *r_async_pending = 1; 1185 } 1186 1187 return 1; 1188 } 1189 1190 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc, 1191 int *r_freq_changed, 1192 u64 *r_notified_in_pipe_mask, 1193 u64 *r_notified_out_pipe_mask) 1194 { 1195 int err; 1196 u32 stat[9]; /* answer from CMD_04_GET_EVENT */ 1197 1198 /* On peut optimiser pour ne pas lire les evenements vides 1199 * les mots de réponse sont dans l'ordre suivant : 1200 * Stat[0] mot de status général 1201 * Stat[1] fin de buffer OUT pF 1202 * Stat[2] fin de buffer OUT pf 1203 * Stat[3] fin de buffer IN pF 1204 * Stat[4] fin de buffer IN pf 1205 * Stat[5] underrun poid fort 1206 * Stat[6] underrun poid faible 1207 * Stat[7] overrun poid fort 1208 * Stat[8] overrun poid faible 1209 * */ 1210 1211 u64 orun_mask; 1212 u64 urun_mask; 1213 #if 0 1214 int has_underrun = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0; 1215 int has_overrun = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0; 1216 #endif 1217 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; 1218 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; 1219 1220 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; 1221 1222 err = lx_dsp_read_async_events(chip, stat); 1223 if (err < 0) 1224 return err; 1225 1226 if (eb_pending_in) { 1227 *r_notified_in_pipe_mask = ((u64)stat[3] << 32) 1228 + stat[4]; 1229 snd_printdd(LXP "interrupt: EOBI pending %llx\n", 1230 *r_notified_in_pipe_mask); 1231 } 1232 if (eb_pending_out) { 1233 *r_notified_out_pipe_mask = ((u64)stat[1] << 32) 1234 + stat[2]; 1235 snd_printdd(LXP "interrupt: EOBO pending %llx\n", 1236 *r_notified_out_pipe_mask); 1237 } 1238 1239 orun_mask = ((u64)stat[7] << 32) + stat[8]; 1240 urun_mask = ((u64)stat[5] << 32) + stat[6]; 1241 1242 /* todo: handle xrun notification */ 1243 1244 return err; 1245 } 1246 1247 static int lx_interrupt_request_new_buffer(struct lx6464es *chip, 1248 struct lx_stream *lx_stream) 1249 { 1250 struct snd_pcm_substream *substream = lx_stream->stream; 1251 int is_capture = lx_stream->is_capture; 1252 int err; 1253 unsigned long flags; 1254 1255 const u32 channels = substream->runtime->channels; 1256 const u32 bytes_per_frame = channels * 3; 1257 const u32 period_size = substream->runtime->period_size; 1258 const u32 period_bytes = period_size * bytes_per_frame; 1259 const u32 pos = lx_stream->frame_pos; 1260 const u32 next_pos = ((pos+1) == substream->runtime->periods) ? 1261 0 : pos + 1; 1262 1263 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes; 1264 u32 buf_hi = 0; 1265 u32 buf_lo = 0; 1266 u32 buffer_index = 0; 1267 1268 u32 needed, freed; 1269 u32 size_array[MAX_STREAM_BUFFER]; 1270 1271 snd_printdd("->lx_interrupt_request_new_buffer\n"); 1272 1273 spin_lock_irqsave(&chip->lock, flags); 1274 1275 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); 1276 snd_printdd(LXP "interrupt: needed %d, freed %d\n", needed, freed); 1277 1278 unpack_pointer(buf, &buf_lo, &buf_hi); 1279 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, 1280 &buffer_index); 1281 snd_printdd(LXP "interrupt: gave buffer index %x on %p (%d bytes)\n", 1282 buffer_index, (void *)buf, period_bytes); 1283 1284 lx_stream->frame_pos = next_pos; 1285 spin_unlock_irqrestore(&chip->lock, flags); 1286 1287 return err; 1288 } 1289 1290 void lx_tasklet_playback(unsigned long data) 1291 { 1292 struct lx6464es *chip = (struct lx6464es *)data; 1293 struct lx_stream *lx_stream = &chip->playback_stream; 1294 int err; 1295 1296 snd_printdd("->lx_tasklet_playback\n"); 1297 1298 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1299 if (err < 0) 1300 snd_printk(KERN_ERR LXP 1301 "cannot request new buffer for playback\n"); 1302 1303 snd_pcm_period_elapsed(lx_stream->stream); 1304 } 1305 1306 void lx_tasklet_capture(unsigned long data) 1307 { 1308 struct lx6464es *chip = (struct lx6464es *)data; 1309 struct lx_stream *lx_stream = &chip->capture_stream; 1310 int err; 1311 1312 snd_printdd("->lx_tasklet_capture\n"); 1313 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1314 if (err < 0) 1315 snd_printk(KERN_ERR LXP 1316 "cannot request new buffer for capture\n"); 1317 1318 snd_pcm_period_elapsed(lx_stream->stream); 1319 } 1320 1321 1322 1323 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip, 1324 u64 notified_in_pipe_mask, 1325 u64 notified_out_pipe_mask) 1326 { 1327 int err = 0; 1328 1329 if (notified_in_pipe_mask) { 1330 snd_printdd(LXP "requesting audio transfer for capture\n"); 1331 tasklet_hi_schedule(&chip->tasklet_capture); 1332 } 1333 1334 if (notified_out_pipe_mask) { 1335 snd_printdd(LXP "requesting audio transfer for playback\n"); 1336 tasklet_hi_schedule(&chip->tasklet_playback); 1337 } 1338 1339 return err; 1340 } 1341 1342 1343 irqreturn_t lx_interrupt(int irq, void *dev_id) 1344 { 1345 struct lx6464es *chip = dev_id; 1346 int async_pending, async_escmd; 1347 u32 irqsrc; 1348 1349 spin_lock(&chip->lock); 1350 1351 snd_printdd("**************************************************\n"); 1352 1353 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) { 1354 spin_unlock(&chip->lock); 1355 snd_printdd("IRQ_NONE\n"); 1356 return IRQ_NONE; /* this device did not cause the interrupt */ 1357 } 1358 1359 if (irqsrc & MASK_SYS_STATUS_CMD_DONE) 1360 goto exit; 1361 1362 #if 0 1363 if (irqsrc & MASK_SYS_STATUS_EOBI) 1364 snd_printdd(LXP "interrupt: EOBI\n"); 1365 1366 if (irqsrc & MASK_SYS_STATUS_EOBO) 1367 snd_printdd(LXP "interrupt: EOBO\n"); 1368 1369 if (irqsrc & MASK_SYS_STATUS_URUN) 1370 snd_printdd(LXP "interrupt: URUN\n"); 1371 1372 if (irqsrc & MASK_SYS_STATUS_ORUN) 1373 snd_printdd(LXP "interrupt: ORUN\n"); 1374 #endif 1375 1376 if (async_pending) { 1377 u64 notified_in_pipe_mask = 0; 1378 u64 notified_out_pipe_mask = 0; 1379 int freq_changed; 1380 int err; 1381 1382 /* handle async events */ 1383 err = lx_interrupt_handle_async_events(chip, irqsrc, 1384 &freq_changed, 1385 ¬ified_in_pipe_mask, 1386 ¬ified_out_pipe_mask); 1387 if (err) 1388 snd_printk(KERN_ERR LXP 1389 "error handling async events\n"); 1390 1391 err = lx_interrupt_handle_audio_transfer(chip, 1392 notified_in_pipe_mask, 1393 notified_out_pipe_mask 1394 ); 1395 if (err) 1396 snd_printk(KERN_ERR LXP 1397 "error during audio transfer\n"); 1398 } 1399 1400 if (async_escmd) { 1401 #if 0 1402 /* backdoor for ethersound commands 1403 * 1404 * for now, we do not need this 1405 * 1406 * */ 1407 1408 snd_printdd("lx6464es: interrupt requests escmd handling\n"); 1409 #endif 1410 } 1411 1412 exit: 1413 spin_unlock(&chip->lock); 1414 return IRQ_HANDLED; /* this device caused the interrupt */ 1415 } 1416 1417 1418 static void lx_irq_set(struct lx6464es *chip, int enable) 1419 { 1420 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); 1421 1422 /* enable/disable interrupts 1423 * 1424 * Set the Doorbell and PCI interrupt enable bits 1425 * 1426 * */ 1427 if (enable) 1428 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1429 else 1430 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1431 lx_plx_reg_write(chip, ePLX_IRQCS, reg); 1432 } 1433 1434 void lx_irq_enable(struct lx6464es *chip) 1435 { 1436 snd_printdd("->lx_irq_enable\n"); 1437 lx_irq_set(chip, 1); 1438 } 1439 1440 void lx_irq_disable(struct lx6464es *chip) 1441 { 1442 snd_printdd("->lx_irq_disable\n"); 1443 lx_irq_set(chip, 0); 1444 } 1445