1 /* -*- linux-c -*- * 2 * 3 * ALSA driver for the digigram lx6464es interface 4 * low-level interface 5 * 6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, 21 * Boston, MA 02111-1307, USA. 22 * 23 */ 24 25 /* #define RMH_DEBUG 1 */ 26 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 31 #include "lx6464es.h" 32 #include "lx_core.h" 33 34 /* low-level register access */ 35 36 static const unsigned long dsp_port_offsets[] = { 37 0, 38 0x400, 39 0x401, 40 0x402, 41 0x403, 42 0x404, 43 0x405, 44 0x406, 45 0x407, 46 0x408, 47 0x409, 48 0x40a, 49 0x40b, 50 0x40c, 51 52 0x410, 53 0x411, 54 0x412, 55 0x413, 56 0x414, 57 0x415, 58 0x416, 59 60 0x420, 61 0x430, 62 0x431, 63 0x432, 64 0x433, 65 0x434, 66 0x440 67 }; 68 69 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port) 70 { 71 void __iomem *base_address = chip->port_dsp_bar; 72 return base_address + dsp_port_offsets[port]*4; 73 } 74 75 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port) 76 { 77 void __iomem *address = lx_dsp_register(chip, port); 78 return ioread32(address); 79 } 80 81 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, 82 u32 len) 83 { 84 u32 __iomem *address = lx_dsp_register(chip, port); 85 int i; 86 87 /* we cannot use memcpy_fromio */ 88 for (i = 0; i != len; ++i) 89 data[i] = ioread32(address + i); 90 } 91 92 93 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data) 94 { 95 void __iomem *address = lx_dsp_register(chip, port); 96 iowrite32(data, address); 97 } 98 99 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, 100 const u32 *data, u32 len) 101 { 102 u32 __iomem *address = lx_dsp_register(chip, port); 103 int i; 104 105 /* we cannot use memcpy_to */ 106 for (i = 0; i != len; ++i) 107 iowrite32(data[i], address + i); 108 } 109 110 111 static const unsigned long plx_port_offsets[] = { 112 0x04, 113 0x40, 114 0x44, 115 0x48, 116 0x4c, 117 0x50, 118 0x54, 119 0x58, 120 0x5c, 121 0x64, 122 0x68, 123 0x6C 124 }; 125 126 static void __iomem *lx_plx_register(struct lx6464es *chip, int port) 127 { 128 void __iomem *base_address = chip->port_plx_remapped; 129 return base_address + plx_port_offsets[port]; 130 } 131 132 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port) 133 { 134 void __iomem *address = lx_plx_register(chip, port); 135 return ioread32(address); 136 } 137 138 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data) 139 { 140 void __iomem *address = lx_plx_register(chip, port); 141 iowrite32(data, address); 142 } 143 144 /* rmh */ 145 146 #ifdef CONFIG_SND_DEBUG 147 #define CMD_NAME(a) a 148 #else 149 #define CMD_NAME(a) NULL 150 #endif 151 152 #define Reg_CSM_MR 0x00000002 153 #define Reg_CSM_MC 0x00000001 154 155 struct dsp_cmd_info { 156 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits 157 * word).*/ 158 u16 dcCmdLength; /* Command length in words of 24 bits.*/ 159 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for 160 * random. */ 161 u16 dcStatusLength; /* Status length (if fixed).*/ 162 char *dcOpName; 163 }; 164 165 /* 166 Initialization and control data for the Microblaze interface 167 - OpCode: 168 the opcode field of the command set at the proper offset 169 - CmdLength 170 the number of command words 171 - StatusType 172 offset in the status registers: 0 means that the return value may be 173 different from 0, and must be read 174 - StatusLength 175 the number of status words (in addition to the return value) 176 */ 177 178 static struct dsp_cmd_info dsp_commands[] = 179 { 180 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/ 181 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") }, 182 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/ 183 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") }, 184 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/ 185 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") }, 186 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/ 187 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") }, 188 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/ 189 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") }, 190 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/ 191 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") }, 192 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/ 193 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") }, 194 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/ 195 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") }, 196 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/ 197 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") }, 198 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/ 199 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") }, 200 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/ 201 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") }, 202 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/ 203 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") }, 204 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/ 205 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") }, 206 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/ 207 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") }, 208 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/ 209 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") }, 210 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/ 211 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") }, 212 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/ 213 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") }, 214 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/ 215 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") }, 216 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/ 217 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") }, 218 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/ 219 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") }, 220 }; 221 222 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd) 223 { 224 snd_BUG_ON(cmd >= CMD_14_INVALID); 225 226 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; 227 rmh->cmd_len = dsp_commands[cmd].dcCmdLength; 228 rmh->stat_len = dsp_commands[cmd].dcStatusLength; 229 rmh->dsp_stat = dsp_commands[cmd].dcStatusType; 230 rmh->cmd_idx = cmd; 231 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); 232 233 #ifdef CONFIG_SND_DEBUG 234 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); 235 #endif 236 #ifdef RMH_DEBUG 237 rmh->cmd_idx = cmd; 238 #endif 239 } 240 241 #ifdef RMH_DEBUG 242 #define LXRMH "lx6464es rmh: " 243 static void lx_message_dump(struct lx_rmh *rmh) 244 { 245 u8 idx = rmh->cmd_idx; 246 int i; 247 248 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName); 249 250 for (i = 0; i != rmh->cmd_len; ++i) 251 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]); 252 253 for (i = 0; i != rmh->stat_len; ++i) 254 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]); 255 snd_printk("\n"); 256 } 257 #else 258 static inline void lx_message_dump(struct lx_rmh *rmh) 259 {} 260 #endif 261 262 263 264 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */ 265 #define XILINX_TIMEOUT_MS 40 266 #define XILINX_POLL_NO_SLEEP 100 267 #define XILINX_POLL_ITERATIONS 150 268 269 270 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh) 271 { 272 u32 reg = ED_DSP_TIMED_OUT; 273 int dwloop; 274 275 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { 276 dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg); 277 return -EBUSY; 278 } 279 280 /* write command */ 281 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); 282 283 /* MicoBlaze gogogo */ 284 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); 285 286 /* wait for device to answer */ 287 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { 288 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) { 289 if (rmh->dsp_stat == 0) 290 reg = lx_dsp_reg_read(chip, eReg_CRM1); 291 else 292 reg = 0; 293 goto polling_successful; 294 } else 295 udelay(1); 296 } 297 dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! " 298 "polling failed\n"); 299 300 polling_successful: 301 if ((reg & ERROR_VALUE) == 0) { 302 /* read response */ 303 if (rmh->stat_len) { 304 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); 305 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, 306 rmh->stat_len); 307 } 308 } else 309 dev_err(chip->card->dev, "rmh error: %08x\n", reg); 310 311 /* clear Reg_CSM_MR */ 312 lx_dsp_reg_write(chip, eReg_CSM, 0); 313 314 switch (reg) { 315 case ED_DSP_TIMED_OUT: 316 dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n"); 317 return -ETIMEDOUT; 318 319 case ED_DSP_CRASHED: 320 dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n"); 321 return -EAGAIN; 322 } 323 324 lx_message_dump(rmh); 325 326 return reg; 327 } 328 329 330 /* low-level dsp access */ 331 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) 332 { 333 u16 ret; 334 unsigned long flags; 335 336 spin_lock_irqsave(&chip->msg_lock, flags); 337 338 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 339 ret = lx_message_send_atomic(chip, &chip->rmh); 340 341 *rdsp_version = chip->rmh.stat[1]; 342 spin_unlock_irqrestore(&chip->msg_lock, flags); 343 return ret; 344 } 345 346 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) 347 { 348 u16 ret = 0; 349 unsigned long flags; 350 u32 freq_raw = 0; 351 u32 freq = 0; 352 u32 frequency = 0; 353 354 spin_lock_irqsave(&chip->msg_lock, flags); 355 356 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 357 ret = lx_message_send_atomic(chip, &chip->rmh); 358 359 if (ret == 0) { 360 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; 361 freq = freq_raw & XES_FREQ_COUNT8_MASK; 362 363 if ((freq < XES_FREQ_COUNT8_48_MAX) || 364 (freq > XES_FREQ_COUNT8_44_MIN)) 365 frequency = 0; /* unknown */ 366 else if (freq >= XES_FREQ_COUNT8_44_MAX) 367 frequency = 44100; 368 else 369 frequency = 48000; 370 } 371 372 spin_unlock_irqrestore(&chip->msg_lock, flags); 373 374 *rfreq = frequency * chip->freq_ratio; 375 376 return ret; 377 } 378 379 int lx_dsp_get_mac(struct lx6464es *chip) 380 { 381 u32 macmsb, maclsb; 382 383 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; 384 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; 385 386 /* todo: endianess handling */ 387 chip->mac_address[5] = ((u8 *)(&maclsb))[0]; 388 chip->mac_address[4] = ((u8 *)(&maclsb))[1]; 389 chip->mac_address[3] = ((u8 *)(&maclsb))[2]; 390 chip->mac_address[2] = ((u8 *)(&macmsb))[0]; 391 chip->mac_address[1] = ((u8 *)(&macmsb))[1]; 392 chip->mac_address[0] = ((u8 *)(&macmsb))[2]; 393 394 return 0; 395 } 396 397 398 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran) 399 { 400 unsigned long flags; 401 int ret; 402 403 spin_lock_irqsave(&chip->msg_lock, flags); 404 405 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY); 406 chip->rmh.cmd[0] |= gran; 407 408 ret = lx_message_send_atomic(chip, &chip->rmh); 409 spin_unlock_irqrestore(&chip->msg_lock, flags); 410 return ret; 411 } 412 413 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data) 414 { 415 unsigned long flags; 416 int ret; 417 418 spin_lock_irqsave(&chip->msg_lock, flags); 419 420 lx_message_init(&chip->rmh, CMD_04_GET_EVENT); 421 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */ 422 423 ret = lx_message_send_atomic(chip, &chip->rmh); 424 425 if (!ret) 426 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32)); 427 428 spin_unlock_irqrestore(&chip->msg_lock, flags); 429 return ret; 430 } 431 432 #define CSES_TIMEOUT 100 /* microseconds */ 433 #define CSES_CE 0x0001 434 #define CSES_BROADCAST 0x0002 435 #define CSES_UPDATE_LDSV 0x0004 436 437 #define PIPE_INFO_TO_CMD(capture, pipe) \ 438 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET) 439 440 441 442 /* low-level pipe handling */ 443 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, 444 int channels) 445 { 446 int err; 447 unsigned long flags; 448 449 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 450 451 spin_lock_irqsave(&chip->msg_lock, flags); 452 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE); 453 454 chip->rmh.cmd[0] |= pipe_cmd; 455 chip->rmh.cmd[0] |= channels; 456 457 err = lx_message_send_atomic(chip, &chip->rmh); 458 spin_unlock_irqrestore(&chip->msg_lock, flags); 459 460 if (err != 0) 461 dev_err(chip->card->dev, "could not allocate pipe\n"); 462 463 return err; 464 } 465 466 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture) 467 { 468 int err; 469 unsigned long flags; 470 471 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 472 473 spin_lock_irqsave(&chip->msg_lock, flags); 474 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE); 475 476 chip->rmh.cmd[0] |= pipe_cmd; 477 478 err = lx_message_send_atomic(chip, &chip->rmh); 479 spin_unlock_irqrestore(&chip->msg_lock, flags); 480 481 return err; 482 } 483 484 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, 485 u32 *r_needed, u32 *r_freed, u32 *size_array) 486 { 487 int err; 488 unsigned long flags; 489 490 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 491 492 #ifdef CONFIG_SND_DEBUG 493 if (size_array) 494 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); 495 #endif 496 497 *r_needed = 0; 498 *r_freed = 0; 499 500 spin_lock_irqsave(&chip->msg_lock, flags); 501 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS); 502 503 chip->rmh.cmd[0] |= pipe_cmd; 504 505 err = lx_message_send_atomic(chip, &chip->rmh); 506 507 if (!err) { 508 int i; 509 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 510 u32 stat = chip->rmh.stat[i]; 511 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) { 512 /* finished */ 513 *r_freed += 1; 514 if (size_array) 515 size_array[i] = stat & MASK_DATA_SIZE; 516 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET)) 517 == 0) 518 /* free */ 519 *r_needed += 1; 520 } 521 522 #if 0 523 dev_dbg(chip->card->dev, 524 "CMD_08_ASK_BUFFERS: needed %d, freed %d\n", 525 *r_needed, *r_freed); 526 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 527 for (i = 0; i != chip->rmh.stat_len; ++i) 528 dev_dbg(chip->card->dev, 529 " stat[%d]: %x, %x\n", i, 530 chip->rmh.stat[i], 531 chip->rmh.stat[i] & MASK_DATA_SIZE); 532 } 533 #endif 534 } 535 536 spin_unlock_irqrestore(&chip->msg_lock, flags); 537 return err; 538 } 539 540 541 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture) 542 { 543 int err; 544 unsigned long flags; 545 546 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 547 548 spin_lock_irqsave(&chip->msg_lock, flags); 549 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE); 550 551 chip->rmh.cmd[0] |= pipe_cmd; 552 553 err = lx_message_send_atomic(chip, &chip->rmh); 554 555 spin_unlock_irqrestore(&chip->msg_lock, flags); 556 return err; 557 } 558 559 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture) 560 { 561 int err; 562 unsigned long flags; 563 564 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 565 566 spin_lock_irqsave(&chip->msg_lock, flags); 567 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE); 568 569 chip->rmh.cmd[0] |= pipe_cmd; 570 571 err = lx_message_send_atomic(chip, &chip->rmh); 572 573 spin_unlock_irqrestore(&chip->msg_lock, flags); 574 return err; 575 } 576 577 578 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture) 579 { 580 int err; 581 582 err = lx_pipe_wait_for_idle(chip, pipe, is_capture); 583 if (err < 0) 584 return err; 585 586 err = lx_pipe_toggle_state(chip, pipe, is_capture); 587 588 return err; 589 } 590 591 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture) 592 { 593 int err = 0; 594 595 err = lx_pipe_wait_for_start(chip, pipe, is_capture); 596 if (err < 0) 597 return err; 598 599 err = lx_pipe_toggle_state(chip, pipe, is_capture); 600 601 return err; 602 } 603 604 605 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, 606 u64 *rsample_count) 607 { 608 int err; 609 unsigned long flags; 610 611 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 612 613 spin_lock_irqsave(&chip->msg_lock, flags); 614 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 615 616 chip->rmh.cmd[0] |= pipe_cmd; 617 chip->rmh.stat_len = 2; /* need all words here! */ 618 619 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */ 620 621 if (err != 0) 622 dev_err(chip->card->dev, 623 "could not query pipe's sample count\n"); 624 else { 625 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 626 << 24) /* hi part */ 627 + chip->rmh.stat[1]; /* lo part */ 628 } 629 630 spin_unlock_irqrestore(&chip->msg_lock, flags); 631 return err; 632 } 633 634 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate) 635 { 636 int err; 637 unsigned long flags; 638 639 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 640 641 spin_lock_irqsave(&chip->msg_lock, flags); 642 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 643 644 chip->rmh.cmd[0] |= pipe_cmd; 645 646 err = lx_message_send_atomic(chip, &chip->rmh); 647 648 if (err != 0) 649 dev_err(chip->card->dev, "could not query pipe's state\n"); 650 else 651 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; 652 653 spin_unlock_irqrestore(&chip->msg_lock, flags); 654 return err; 655 } 656 657 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe, 658 int is_capture, u16 state) 659 { 660 int i; 661 662 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms: 663 * timeout 50 ms */ 664 for (i = 0; i != 50; ++i) { 665 u16 current_state; 666 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state); 667 668 if (err < 0) 669 return err; 670 671 if (current_state == state) 672 return 0; 673 674 mdelay(1); 675 } 676 677 return -ETIMEDOUT; 678 } 679 680 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture) 681 { 682 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN); 683 } 684 685 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture) 686 { 687 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE); 688 } 689 690 /* low-level stream handling */ 691 int lx_stream_set_state(struct lx6464es *chip, u32 pipe, 692 int is_capture, enum stream_state_t state) 693 { 694 int err; 695 unsigned long flags; 696 697 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 698 699 spin_lock_irqsave(&chip->msg_lock, flags); 700 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE); 701 702 chip->rmh.cmd[0] |= pipe_cmd; 703 chip->rmh.cmd[0] |= state; 704 705 err = lx_message_send_atomic(chip, &chip->rmh); 706 spin_unlock_irqrestore(&chip->msg_lock, flags); 707 708 return err; 709 } 710 711 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, 712 u32 pipe, int is_capture) 713 { 714 int err; 715 unsigned long flags; 716 717 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 718 719 u32 channels = runtime->channels; 720 721 if (runtime->channels != channels) 722 dev_err(chip->card->dev, "channel count mismatch: %d vs %d", 723 runtime->channels, channels); 724 725 spin_lock_irqsave(&chip->msg_lock, flags); 726 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM); 727 728 chip->rmh.cmd[0] |= pipe_cmd; 729 730 if (runtime->sample_bits == 16) 731 /* 16 bit format */ 732 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); 733 734 if (snd_pcm_format_little_endian(runtime->format)) 735 /* little endian/intel format */ 736 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); 737 738 chip->rmh.cmd[0] |= channels-1; 739 740 err = lx_message_send_atomic(chip, &chip->rmh); 741 spin_unlock_irqrestore(&chip->msg_lock, flags); 742 743 return err; 744 } 745 746 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, 747 int *rstate) 748 { 749 int err; 750 unsigned long flags; 751 752 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 753 754 spin_lock_irqsave(&chip->msg_lock, flags); 755 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 756 757 chip->rmh.cmd[0] |= pipe_cmd; 758 759 err = lx_message_send_atomic(chip, &chip->rmh); 760 761 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; 762 763 spin_unlock_irqrestore(&chip->msg_lock, flags); 764 return err; 765 } 766 767 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, 768 u64 *r_bytepos) 769 { 770 int err; 771 unsigned long flags; 772 773 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 774 775 spin_lock_irqsave(&chip->msg_lock, flags); 776 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 777 778 chip->rmh.cmd[0] |= pipe_cmd; 779 780 err = lx_message_send_atomic(chip, &chip->rmh); 781 782 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 783 << 32) /* hi part */ 784 + chip->rmh.stat[1]; /* lo part */ 785 786 spin_unlock_irqrestore(&chip->msg_lock, flags); 787 return err; 788 } 789 790 /* low-level buffer handling */ 791 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, 792 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, 793 u32 *r_buffer_index) 794 { 795 int err; 796 unsigned long flags; 797 798 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 799 800 spin_lock_irqsave(&chip->msg_lock, flags); 801 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER); 802 803 chip->rmh.cmd[0] |= pipe_cmd; 804 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ 805 806 /* todo: pause request, circular buffer */ 807 808 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE; 809 chip->rmh.cmd[2] = buf_address_lo; 810 811 if (buf_address_hi) { 812 chip->rmh.cmd_len = 4; 813 chip->rmh.cmd[3] = buf_address_hi; 814 chip->rmh.cmd[0] |= BF_64BITS_ADR; 815 } 816 817 err = lx_message_send_atomic(chip, &chip->rmh); 818 819 if (err == 0) { 820 *r_buffer_index = chip->rmh.stat[0]; 821 goto done; 822 } 823 824 if (err == EB_RBUFFERS_TABLE_OVERFLOW) 825 dev_err(chip->card->dev, 826 "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n"); 827 828 if (err == EB_INVALID_STREAM) 829 dev_err(chip->card->dev, 830 "lx_buffer_give EB_INVALID_STREAM\n"); 831 832 if (err == EB_CMD_REFUSED) 833 dev_err(chip->card->dev, 834 "lx_buffer_give EB_CMD_REFUSED\n"); 835 836 done: 837 spin_unlock_irqrestore(&chip->msg_lock, flags); 838 return err; 839 } 840 841 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, 842 u32 *r_buffer_size) 843 { 844 int err; 845 unsigned long flags; 846 847 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 848 849 spin_lock_irqsave(&chip->msg_lock, flags); 850 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 851 852 chip->rmh.cmd[0] |= pipe_cmd; 853 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the 854 * microblaze will seek for it */ 855 856 err = lx_message_send_atomic(chip, &chip->rmh); 857 858 if (err == 0) 859 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; 860 861 spin_unlock_irqrestore(&chip->msg_lock, flags); 862 return err; 863 } 864 865 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, 866 u32 buffer_index) 867 { 868 int err; 869 unsigned long flags; 870 871 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 872 873 spin_lock_irqsave(&chip->msg_lock, flags); 874 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 875 876 chip->rmh.cmd[0] |= pipe_cmd; 877 chip->rmh.cmd[0] |= buffer_index; 878 879 err = lx_message_send_atomic(chip, &chip->rmh); 880 881 spin_unlock_irqrestore(&chip->msg_lock, flags); 882 return err; 883 } 884 885 886 /* low-level gain/peak handling 887 * 888 * \todo: can we unmute capture/playback channels independently? 889 * 890 * */ 891 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute) 892 { 893 int err; 894 unsigned long flags; 895 896 /* bit set to 1: channel muted */ 897 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; 898 899 spin_lock_irqsave(&chip->msg_lock, flags); 900 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE); 901 902 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); 903 904 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */ 905 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ 906 907 dev_dbg(chip->card->dev, 908 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], 909 chip->rmh.cmd[2]); 910 911 err = lx_message_send_atomic(chip, &chip->rmh); 912 913 spin_unlock_irqrestore(&chip->msg_lock, flags); 914 return err; 915 } 916 917 static u32 peak_map[] = { 918 0x00000109, /* -90.308dB */ 919 0x0000083B, /* -72.247dB */ 920 0x000020C4, /* -60.205dB */ 921 0x00008273, /* -48.030dB */ 922 0x00020756, /* -36.005dB */ 923 0x00040C37, /* -30.001dB */ 924 0x00081385, /* -24.002dB */ 925 0x00101D3F, /* -18.000dB */ 926 0x0016C310, /* -15.000dB */ 927 0x002026F2, /* -12.001dB */ 928 0x002D6A86, /* -9.000dB */ 929 0x004026E6, /* -6.004dB */ 930 0x005A9DF6, /* -3.000dB */ 931 0x0065AC8B, /* -2.000dB */ 932 0x00721481, /* -1.000dB */ 933 0x007FFFFF, /* FS */ 934 }; 935 936 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, 937 u32 *r_levels) 938 { 939 int err = 0; 940 unsigned long flags; 941 int i; 942 spin_lock_irqsave(&chip->msg_lock, flags); 943 944 for (i = 0; i < channels; i += 4) { 945 u32 s0, s1, s2, s3; 946 947 lx_message_init(&chip->rmh, CMD_12_GET_PEAK); 948 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); 949 950 err = lx_message_send_atomic(chip, &chip->rmh); 951 952 if (err == 0) { 953 s0 = peak_map[chip->rmh.stat[0] & 0x0F]; 954 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; 955 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; 956 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; 957 } else 958 s0 = s1 = s2 = s3 = 0; 959 960 r_levels[0] = s0; 961 r_levels[1] = s1; 962 r_levels[2] = s2; 963 r_levels[3] = s3; 964 965 r_levels += 4; 966 } 967 968 spin_unlock_irqrestore(&chip->msg_lock, flags); 969 return err; 970 } 971 972 /* interrupt handling */ 973 #define PCX_IRQ_NONE 0 974 #define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit nø 13 */ 975 #define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit nø 08 */ 976 #define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit nø 09 */ 977 978 static u32 lx_interrupt_test_ack(struct lx6464es *chip) 979 { 980 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS); 981 982 /* Test if PCI Doorbell interrupt is active */ 983 if (irqcs & IRQCS_ACTIVE_PCIDB) { 984 u32 temp; 985 irqcs = PCX_IRQ_NONE; 986 987 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) { 988 /* RAZ interrupt */ 989 irqcs |= temp; 990 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp); 991 } 992 993 return irqcs; 994 } 995 return PCX_IRQ_NONE; 996 } 997 998 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc, 999 int *r_async_pending, int *r_async_escmd) 1000 { 1001 u32 irq_async; 1002 u32 irqsrc = lx_interrupt_test_ack(chip); 1003 1004 if (irqsrc == PCX_IRQ_NONE) 1005 return 0; 1006 1007 *r_irqsrc = irqsrc; 1008 1009 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response 1010 * (set by xilinx) + EOB */ 1011 1012 if (irq_async & MASK_SYS_STATUS_ESA) { 1013 irq_async &= ~MASK_SYS_STATUS_ESA; 1014 *r_async_escmd = 1; 1015 } 1016 1017 if (irq_async) { 1018 /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */ 1019 *r_async_pending = 1; 1020 } 1021 1022 return 1; 1023 } 1024 1025 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc, 1026 int *r_freq_changed, 1027 u64 *r_notified_in_pipe_mask, 1028 u64 *r_notified_out_pipe_mask) 1029 { 1030 int err; 1031 u32 stat[9]; /* answer from CMD_04_GET_EVENT */ 1032 1033 /* On peut optimiser pour ne pas lire les evenements vides 1034 * les mots de réponse sont dans l'ordre suivant : 1035 * Stat[0] mot de status général 1036 * Stat[1] fin de buffer OUT pF 1037 * Stat[2] fin de buffer OUT pf 1038 * Stat[3] fin de buffer IN pF 1039 * Stat[4] fin de buffer IN pf 1040 * Stat[5] underrun poid fort 1041 * Stat[6] underrun poid faible 1042 * Stat[7] overrun poid fort 1043 * Stat[8] overrun poid faible 1044 * */ 1045 1046 u64 orun_mask; 1047 u64 urun_mask; 1048 #if 0 1049 int has_underrun = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0; 1050 int has_overrun = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0; 1051 #endif 1052 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; 1053 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; 1054 1055 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; 1056 1057 err = lx_dsp_read_async_events(chip, stat); 1058 if (err < 0) 1059 return err; 1060 1061 if (eb_pending_in) { 1062 *r_notified_in_pipe_mask = ((u64)stat[3] << 32) 1063 + stat[4]; 1064 dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n", 1065 *r_notified_in_pipe_mask); 1066 } 1067 if (eb_pending_out) { 1068 *r_notified_out_pipe_mask = ((u64)stat[1] << 32) 1069 + stat[2]; 1070 dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n", 1071 *r_notified_out_pipe_mask); 1072 } 1073 1074 orun_mask = ((u64)stat[7] << 32) + stat[8]; 1075 urun_mask = ((u64)stat[5] << 32) + stat[6]; 1076 1077 /* todo: handle xrun notification */ 1078 1079 return err; 1080 } 1081 1082 static int lx_interrupt_request_new_buffer(struct lx6464es *chip, 1083 struct lx_stream *lx_stream) 1084 { 1085 struct snd_pcm_substream *substream = lx_stream->stream; 1086 const unsigned int is_capture = lx_stream->is_capture; 1087 int err; 1088 unsigned long flags; 1089 1090 const u32 channels = substream->runtime->channels; 1091 const u32 bytes_per_frame = channels * 3; 1092 const u32 period_size = substream->runtime->period_size; 1093 const u32 period_bytes = period_size * bytes_per_frame; 1094 const u32 pos = lx_stream->frame_pos; 1095 const u32 next_pos = ((pos+1) == substream->runtime->periods) ? 1096 0 : pos + 1; 1097 1098 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes; 1099 u32 buf_hi = 0; 1100 u32 buf_lo = 0; 1101 u32 buffer_index = 0; 1102 1103 u32 needed, freed; 1104 u32 size_array[MAX_STREAM_BUFFER]; 1105 1106 dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n"); 1107 1108 spin_lock_irqsave(&chip->lock, flags); 1109 1110 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); 1111 dev_dbg(chip->card->dev, 1112 "interrupt: needed %d, freed %d\n", needed, freed); 1113 1114 unpack_pointer(buf, &buf_lo, &buf_hi); 1115 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, 1116 &buffer_index); 1117 dev_dbg(chip->card->dev, 1118 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n", 1119 buffer_index, (unsigned long)buf, period_bytes); 1120 1121 lx_stream->frame_pos = next_pos; 1122 spin_unlock_irqrestore(&chip->lock, flags); 1123 1124 return err; 1125 } 1126 1127 void lx_tasklet_playback(unsigned long data) 1128 { 1129 struct lx6464es *chip = (struct lx6464es *)data; 1130 struct lx_stream *lx_stream = &chip->playback_stream; 1131 int err; 1132 1133 dev_dbg(chip->card->dev, "->lx_tasklet_playback\n"); 1134 1135 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1136 if (err < 0) 1137 dev_err(chip->card->dev, 1138 "cannot request new buffer for playback\n"); 1139 1140 snd_pcm_period_elapsed(lx_stream->stream); 1141 } 1142 1143 void lx_tasklet_capture(unsigned long data) 1144 { 1145 struct lx6464es *chip = (struct lx6464es *)data; 1146 struct lx_stream *lx_stream = &chip->capture_stream; 1147 int err; 1148 1149 dev_dbg(chip->card->dev, "->lx_tasklet_capture\n"); 1150 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1151 if (err < 0) 1152 dev_err(chip->card->dev, 1153 "cannot request new buffer for capture\n"); 1154 1155 snd_pcm_period_elapsed(lx_stream->stream); 1156 } 1157 1158 1159 1160 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip, 1161 u64 notified_in_pipe_mask, 1162 u64 notified_out_pipe_mask) 1163 { 1164 int err = 0; 1165 1166 if (notified_in_pipe_mask) { 1167 dev_dbg(chip->card->dev, 1168 "requesting audio transfer for capture\n"); 1169 tasklet_hi_schedule(&chip->tasklet_capture); 1170 } 1171 1172 if (notified_out_pipe_mask) { 1173 dev_dbg(chip->card->dev, 1174 "requesting audio transfer for playback\n"); 1175 tasklet_hi_schedule(&chip->tasklet_playback); 1176 } 1177 1178 return err; 1179 } 1180 1181 1182 irqreturn_t lx_interrupt(int irq, void *dev_id) 1183 { 1184 struct lx6464es *chip = dev_id; 1185 int async_pending, async_escmd; 1186 u32 irqsrc; 1187 1188 spin_lock(&chip->lock); 1189 1190 dev_dbg(chip->card->dev, 1191 "**************************************************\n"); 1192 1193 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) { 1194 spin_unlock(&chip->lock); 1195 dev_dbg(chip->card->dev, "IRQ_NONE\n"); 1196 return IRQ_NONE; /* this device did not cause the interrupt */ 1197 } 1198 1199 if (irqsrc & MASK_SYS_STATUS_CMD_DONE) 1200 goto exit; 1201 1202 #if 0 1203 if (irqsrc & MASK_SYS_STATUS_EOBI) 1204 dev_dgg(chip->card->dev, "interrupt: EOBI\n"); 1205 1206 if (irqsrc & MASK_SYS_STATUS_EOBO) 1207 dev_dbg(chip->card->dev, "interrupt: EOBO\n"); 1208 1209 if (irqsrc & MASK_SYS_STATUS_URUN) 1210 dev_dbg(chip->card->dev, "interrupt: URUN\n"); 1211 1212 if (irqsrc & MASK_SYS_STATUS_ORUN) 1213 dev_dbg(chip->card->dev, "interrupt: ORUN\n"); 1214 #endif 1215 1216 if (async_pending) { 1217 u64 notified_in_pipe_mask = 0; 1218 u64 notified_out_pipe_mask = 0; 1219 int freq_changed; 1220 int err; 1221 1222 /* handle async events */ 1223 err = lx_interrupt_handle_async_events(chip, irqsrc, 1224 &freq_changed, 1225 ¬ified_in_pipe_mask, 1226 ¬ified_out_pipe_mask); 1227 if (err) 1228 dev_err(chip->card->dev, 1229 "error handling async events\n"); 1230 1231 err = lx_interrupt_handle_audio_transfer(chip, 1232 notified_in_pipe_mask, 1233 notified_out_pipe_mask 1234 ); 1235 if (err) 1236 dev_err(chip->card->dev, 1237 "error during audio transfer\n"); 1238 } 1239 1240 if (async_escmd) { 1241 #if 0 1242 /* backdoor for ethersound commands 1243 * 1244 * for now, we do not need this 1245 * 1246 * */ 1247 1248 dev_dbg(chip->card->dev, "interrupt requests escmd handling\n"); 1249 #endif 1250 } 1251 1252 exit: 1253 spin_unlock(&chip->lock); 1254 return IRQ_HANDLED; /* this device caused the interrupt */ 1255 } 1256 1257 1258 static void lx_irq_set(struct lx6464es *chip, int enable) 1259 { 1260 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); 1261 1262 /* enable/disable interrupts 1263 * 1264 * Set the Doorbell and PCI interrupt enable bits 1265 * 1266 * */ 1267 if (enable) 1268 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1269 else 1270 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1271 lx_plx_reg_write(chip, ePLX_IRQCS, reg); 1272 } 1273 1274 void lx_irq_enable(struct lx6464es *chip) 1275 { 1276 dev_dbg(chip->card->dev, "->lx_irq_enable\n"); 1277 lx_irq_set(chip, 1); 1278 } 1279 1280 void lx_irq_disable(struct lx6464es *chip) 1281 { 1282 dev_dbg(chip->card->dev, "->lx_irq_disable\n"); 1283 lx_irq_set(chip, 0); 1284 } 1285