1 /* -*- linux-c -*- * 2 * 3 * ALSA driver for the digigram lx6464es interface 4 * low-level interface 5 * 6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, 21 * Boston, MA 02111-1307, USA. 22 * 23 */ 24 25 /* #define RMH_DEBUG 1 */ 26 27 #include <linux/bitops.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/delay.h> 31 32 #include "lx6464es.h" 33 #include "lx_core.h" 34 35 /* low-level register access */ 36 37 static const unsigned long dsp_port_offsets[] = { 38 0, 39 0x400, 40 0x401, 41 0x402, 42 0x403, 43 0x404, 44 0x405, 45 0x406, 46 0x407, 47 0x408, 48 0x409, 49 0x40a, 50 0x40b, 51 0x40c, 52 53 0x410, 54 0x411, 55 0x412, 56 0x413, 57 0x414, 58 0x415, 59 0x416, 60 61 0x420, 62 0x430, 63 0x431, 64 0x432, 65 0x433, 66 0x434, 67 0x440 68 }; 69 70 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port) 71 { 72 void __iomem *base_address = chip->port_dsp_bar; 73 return base_address + dsp_port_offsets[port]*4; 74 } 75 76 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port) 77 { 78 void __iomem *address = lx_dsp_register(chip, port); 79 return ioread32(address); 80 } 81 82 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, 83 u32 len) 84 { 85 u32 __iomem *address = lx_dsp_register(chip, port); 86 int i; 87 88 /* we cannot use memcpy_fromio */ 89 for (i = 0; i != len; ++i) 90 data[i] = ioread32(address + i); 91 } 92 93 94 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data) 95 { 96 void __iomem *address = lx_dsp_register(chip, port); 97 iowrite32(data, address); 98 } 99 100 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, 101 const u32 *data, u32 len) 102 { 103 u32 __iomem *address = lx_dsp_register(chip, port); 104 int i; 105 106 /* we cannot use memcpy_to */ 107 for (i = 0; i != len; ++i) 108 iowrite32(data[i], address + i); 109 } 110 111 112 static const unsigned long plx_port_offsets[] = { 113 0x04, 114 0x40, 115 0x44, 116 0x48, 117 0x4c, 118 0x50, 119 0x54, 120 0x58, 121 0x5c, 122 0x64, 123 0x68, 124 0x6C 125 }; 126 127 static void __iomem *lx_plx_register(struct lx6464es *chip, int port) 128 { 129 void __iomem *base_address = chip->port_plx_remapped; 130 return base_address + plx_port_offsets[port]; 131 } 132 133 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port) 134 { 135 void __iomem *address = lx_plx_register(chip, port); 136 return ioread32(address); 137 } 138 139 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data) 140 { 141 void __iomem *address = lx_plx_register(chip, port); 142 iowrite32(data, address); 143 } 144 145 /* rmh */ 146 147 #ifdef CONFIG_SND_DEBUG 148 #define CMD_NAME(a) a 149 #else 150 #define CMD_NAME(a) NULL 151 #endif 152 153 #define Reg_CSM_MR 0x00000002 154 #define Reg_CSM_MC 0x00000001 155 156 struct dsp_cmd_info { 157 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits 158 * word).*/ 159 u16 dcCmdLength; /* Command length in words of 24 bits.*/ 160 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for 161 * random. */ 162 u16 dcStatusLength; /* Status length (if fixed).*/ 163 char *dcOpName; 164 }; 165 166 /* 167 Initialization and control data for the Microblaze interface 168 - OpCode: 169 the opcode field of the command set at the proper offset 170 - CmdLength 171 the number of command words 172 - StatusType 173 offset in the status registers: 0 means that the return value may be 174 different from 0, and must be read 175 - StatusLength 176 the number of status words (in addition to the return value) 177 */ 178 179 static struct dsp_cmd_info dsp_commands[] = 180 { 181 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/ 182 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") }, 183 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/ 184 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") }, 185 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/ 186 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") }, 187 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/ 188 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") }, 189 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/ 190 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") }, 191 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/ 192 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") }, 193 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/ 194 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") }, 195 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/ 196 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") }, 197 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/ 198 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") }, 199 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/ 200 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") }, 201 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/ 202 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") }, 203 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/ 204 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") }, 205 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/ 206 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") }, 207 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/ 208 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") }, 209 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/ 210 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") }, 211 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/ 212 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") }, 213 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/ 214 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") }, 215 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/ 216 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") }, 217 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/ 218 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") }, 219 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/ 220 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") }, 221 }; 222 223 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd) 224 { 225 snd_BUG_ON(cmd >= CMD_14_INVALID); 226 227 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; 228 rmh->cmd_len = dsp_commands[cmd].dcCmdLength; 229 rmh->stat_len = dsp_commands[cmd].dcStatusLength; 230 rmh->dsp_stat = dsp_commands[cmd].dcStatusType; 231 rmh->cmd_idx = cmd; 232 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); 233 234 #ifdef CONFIG_SND_DEBUG 235 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); 236 #endif 237 #ifdef RMH_DEBUG 238 rmh->cmd_idx = cmd; 239 #endif 240 } 241 242 #ifdef RMH_DEBUG 243 #define LXRMH "lx6464es rmh: " 244 static void lx_message_dump(struct lx_rmh *rmh) 245 { 246 u8 idx = rmh->cmd_idx; 247 int i; 248 249 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName); 250 251 for (i = 0; i != rmh->cmd_len; ++i) 252 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]); 253 254 for (i = 0; i != rmh->stat_len; ++i) 255 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]); 256 snd_printk("\n"); 257 } 258 #else 259 static inline void lx_message_dump(struct lx_rmh *rmh) 260 {} 261 #endif 262 263 264 265 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */ 266 #define XILINX_TIMEOUT_MS 40 267 #define XILINX_POLL_NO_SLEEP 100 268 #define XILINX_POLL_ITERATIONS 150 269 270 271 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh) 272 { 273 u32 reg = ED_DSP_TIMED_OUT; 274 int dwloop; 275 276 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { 277 dev_err(chip->card->dev, "PIOSendMessage eReg_CSM %x\n", reg); 278 return -EBUSY; 279 } 280 281 /* write command */ 282 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); 283 284 /* MicoBlaze gogogo */ 285 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); 286 287 /* wait for device to answer */ 288 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { 289 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) { 290 if (rmh->dsp_stat == 0) 291 reg = lx_dsp_reg_read(chip, eReg_CRM1); 292 else 293 reg = 0; 294 goto polling_successful; 295 } else 296 udelay(1); 297 } 298 dev_warn(chip->card->dev, "TIMEOUT lx_message_send_atomic! " 299 "polling failed\n"); 300 301 polling_successful: 302 if ((reg & ERROR_VALUE) == 0) { 303 /* read response */ 304 if (rmh->stat_len) { 305 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); 306 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, 307 rmh->stat_len); 308 } 309 } else 310 dev_err(chip->card->dev, "rmh error: %08x\n", reg); 311 312 /* clear Reg_CSM_MR */ 313 lx_dsp_reg_write(chip, eReg_CSM, 0); 314 315 switch (reg) { 316 case ED_DSP_TIMED_OUT: 317 dev_warn(chip->card->dev, "lx_message_send: dsp timeout\n"); 318 return -ETIMEDOUT; 319 320 case ED_DSP_CRASHED: 321 dev_warn(chip->card->dev, "lx_message_send: dsp crashed\n"); 322 return -EAGAIN; 323 } 324 325 lx_message_dump(rmh); 326 327 return reg; 328 } 329 330 331 /* low-level dsp access */ 332 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) 333 { 334 u16 ret; 335 unsigned long flags; 336 337 spin_lock_irqsave(&chip->msg_lock, flags); 338 339 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 340 ret = lx_message_send_atomic(chip, &chip->rmh); 341 342 *rdsp_version = chip->rmh.stat[1]; 343 spin_unlock_irqrestore(&chip->msg_lock, flags); 344 return ret; 345 } 346 347 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) 348 { 349 u16 ret = 0; 350 unsigned long flags; 351 u32 freq_raw = 0; 352 u32 freq = 0; 353 u32 frequency = 0; 354 355 spin_lock_irqsave(&chip->msg_lock, flags); 356 357 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 358 ret = lx_message_send_atomic(chip, &chip->rmh); 359 360 if (ret == 0) { 361 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; 362 freq = freq_raw & XES_FREQ_COUNT8_MASK; 363 364 if ((freq < XES_FREQ_COUNT8_48_MAX) || 365 (freq > XES_FREQ_COUNT8_44_MIN)) 366 frequency = 0; /* unknown */ 367 else if (freq >= XES_FREQ_COUNT8_44_MAX) 368 frequency = 44100; 369 else 370 frequency = 48000; 371 } 372 373 spin_unlock_irqrestore(&chip->msg_lock, flags); 374 375 *rfreq = frequency * chip->freq_ratio; 376 377 return ret; 378 } 379 380 int lx_dsp_get_mac(struct lx6464es *chip) 381 { 382 u32 macmsb, maclsb; 383 384 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; 385 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; 386 387 /* todo: endianess handling */ 388 chip->mac_address[5] = ((u8 *)(&maclsb))[0]; 389 chip->mac_address[4] = ((u8 *)(&maclsb))[1]; 390 chip->mac_address[3] = ((u8 *)(&maclsb))[2]; 391 chip->mac_address[2] = ((u8 *)(&macmsb))[0]; 392 chip->mac_address[1] = ((u8 *)(&macmsb))[1]; 393 chip->mac_address[0] = ((u8 *)(&macmsb))[2]; 394 395 return 0; 396 } 397 398 399 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran) 400 { 401 unsigned long flags; 402 int ret; 403 404 spin_lock_irqsave(&chip->msg_lock, flags); 405 406 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY); 407 chip->rmh.cmd[0] |= gran; 408 409 ret = lx_message_send_atomic(chip, &chip->rmh); 410 spin_unlock_irqrestore(&chip->msg_lock, flags); 411 return ret; 412 } 413 414 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data) 415 { 416 unsigned long flags; 417 int ret; 418 419 spin_lock_irqsave(&chip->msg_lock, flags); 420 421 lx_message_init(&chip->rmh, CMD_04_GET_EVENT); 422 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */ 423 424 ret = lx_message_send_atomic(chip, &chip->rmh); 425 426 if (!ret) 427 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32)); 428 429 spin_unlock_irqrestore(&chip->msg_lock, flags); 430 return ret; 431 } 432 433 #define PIPE_INFO_TO_CMD(capture, pipe) \ 434 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET) 435 436 437 438 /* low-level pipe handling */ 439 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, 440 int channels) 441 { 442 int err; 443 unsigned long flags; 444 445 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 446 447 spin_lock_irqsave(&chip->msg_lock, flags); 448 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE); 449 450 chip->rmh.cmd[0] |= pipe_cmd; 451 chip->rmh.cmd[0] |= channels; 452 453 err = lx_message_send_atomic(chip, &chip->rmh); 454 spin_unlock_irqrestore(&chip->msg_lock, flags); 455 456 if (err != 0) 457 dev_err(chip->card->dev, "could not allocate pipe\n"); 458 459 return err; 460 } 461 462 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture) 463 { 464 int err; 465 unsigned long flags; 466 467 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 468 469 spin_lock_irqsave(&chip->msg_lock, flags); 470 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE); 471 472 chip->rmh.cmd[0] |= pipe_cmd; 473 474 err = lx_message_send_atomic(chip, &chip->rmh); 475 spin_unlock_irqrestore(&chip->msg_lock, flags); 476 477 return err; 478 } 479 480 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, 481 u32 *r_needed, u32 *r_freed, u32 *size_array) 482 { 483 int err; 484 unsigned long flags; 485 486 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 487 488 #ifdef CONFIG_SND_DEBUG 489 if (size_array) 490 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); 491 #endif 492 493 *r_needed = 0; 494 *r_freed = 0; 495 496 spin_lock_irqsave(&chip->msg_lock, flags); 497 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS); 498 499 chip->rmh.cmd[0] |= pipe_cmd; 500 501 err = lx_message_send_atomic(chip, &chip->rmh); 502 503 if (!err) { 504 int i; 505 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 506 u32 stat = chip->rmh.stat[i]; 507 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) { 508 /* finished */ 509 *r_freed += 1; 510 if (size_array) 511 size_array[i] = stat & MASK_DATA_SIZE; 512 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET)) 513 == 0) 514 /* free */ 515 *r_needed += 1; 516 } 517 518 dev_dbg(chip->card->dev, 519 "CMD_08_ASK_BUFFERS: needed %d, freed %d\n", 520 *r_needed, *r_freed); 521 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 522 for (i = 0; i != chip->rmh.stat_len; ++i) 523 dev_dbg(chip->card->dev, 524 " stat[%d]: %x, %x\n", i, 525 chip->rmh.stat[i], 526 chip->rmh.stat[i] & MASK_DATA_SIZE); 527 } 528 } 529 530 spin_unlock_irqrestore(&chip->msg_lock, flags); 531 return err; 532 } 533 534 535 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture) 536 { 537 int err; 538 unsigned long flags; 539 540 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 541 542 spin_lock_irqsave(&chip->msg_lock, flags); 543 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE); 544 545 chip->rmh.cmd[0] |= pipe_cmd; 546 547 err = lx_message_send_atomic(chip, &chip->rmh); 548 549 spin_unlock_irqrestore(&chip->msg_lock, flags); 550 return err; 551 } 552 553 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture) 554 { 555 int err; 556 unsigned long flags; 557 558 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 559 560 spin_lock_irqsave(&chip->msg_lock, flags); 561 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE); 562 563 chip->rmh.cmd[0] |= pipe_cmd; 564 565 err = lx_message_send_atomic(chip, &chip->rmh); 566 567 spin_unlock_irqrestore(&chip->msg_lock, flags); 568 return err; 569 } 570 571 572 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture) 573 { 574 int err; 575 576 err = lx_pipe_wait_for_idle(chip, pipe, is_capture); 577 if (err < 0) 578 return err; 579 580 err = lx_pipe_toggle_state(chip, pipe, is_capture); 581 582 return err; 583 } 584 585 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture) 586 { 587 int err = 0; 588 589 err = lx_pipe_wait_for_start(chip, pipe, is_capture); 590 if (err < 0) 591 return err; 592 593 err = lx_pipe_toggle_state(chip, pipe, is_capture); 594 595 return err; 596 } 597 598 599 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, 600 u64 *rsample_count) 601 { 602 int err; 603 unsigned long flags; 604 605 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 606 607 spin_lock_irqsave(&chip->msg_lock, flags); 608 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 609 610 chip->rmh.cmd[0] |= pipe_cmd; 611 chip->rmh.stat_len = 2; /* need all words here! */ 612 613 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */ 614 615 if (err != 0) 616 dev_err(chip->card->dev, 617 "could not query pipe's sample count\n"); 618 else { 619 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 620 << 24) /* hi part */ 621 + chip->rmh.stat[1]; /* lo part */ 622 } 623 624 spin_unlock_irqrestore(&chip->msg_lock, flags); 625 return err; 626 } 627 628 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate) 629 { 630 int err; 631 unsigned long flags; 632 633 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 634 635 spin_lock_irqsave(&chip->msg_lock, flags); 636 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 637 638 chip->rmh.cmd[0] |= pipe_cmd; 639 640 err = lx_message_send_atomic(chip, &chip->rmh); 641 642 if (err != 0) 643 dev_err(chip->card->dev, "could not query pipe's state\n"); 644 else 645 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; 646 647 spin_unlock_irqrestore(&chip->msg_lock, flags); 648 return err; 649 } 650 651 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe, 652 int is_capture, u16 state) 653 { 654 int i; 655 656 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms: 657 * timeout 50 ms */ 658 for (i = 0; i != 50; ++i) { 659 u16 current_state; 660 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state); 661 662 if (err < 0) 663 return err; 664 665 if (current_state == state) 666 return 0; 667 668 mdelay(1); 669 } 670 671 return -ETIMEDOUT; 672 } 673 674 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture) 675 { 676 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN); 677 } 678 679 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture) 680 { 681 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE); 682 } 683 684 /* low-level stream handling */ 685 int lx_stream_set_state(struct lx6464es *chip, u32 pipe, 686 int is_capture, enum stream_state_t state) 687 { 688 int err; 689 unsigned long flags; 690 691 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 692 693 spin_lock_irqsave(&chip->msg_lock, flags); 694 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE); 695 696 chip->rmh.cmd[0] |= pipe_cmd; 697 chip->rmh.cmd[0] |= state; 698 699 err = lx_message_send_atomic(chip, &chip->rmh); 700 spin_unlock_irqrestore(&chip->msg_lock, flags); 701 702 return err; 703 } 704 705 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, 706 u32 pipe, int is_capture) 707 { 708 int err; 709 unsigned long flags; 710 711 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 712 713 u32 channels = runtime->channels; 714 715 if (runtime->channels != channels) 716 dev_err(chip->card->dev, "channel count mismatch: %d vs %d", 717 runtime->channels, channels); 718 719 spin_lock_irqsave(&chip->msg_lock, flags); 720 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM); 721 722 chip->rmh.cmd[0] |= pipe_cmd; 723 724 if (runtime->sample_bits == 16) 725 /* 16 bit format */ 726 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); 727 728 if (snd_pcm_format_little_endian(runtime->format)) 729 /* little endian/intel format */ 730 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); 731 732 chip->rmh.cmd[0] |= channels-1; 733 734 err = lx_message_send_atomic(chip, &chip->rmh); 735 spin_unlock_irqrestore(&chip->msg_lock, flags); 736 737 return err; 738 } 739 740 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, 741 int *rstate) 742 { 743 int err; 744 unsigned long flags; 745 746 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 747 748 spin_lock_irqsave(&chip->msg_lock, flags); 749 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 750 751 chip->rmh.cmd[0] |= pipe_cmd; 752 753 err = lx_message_send_atomic(chip, &chip->rmh); 754 755 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; 756 757 spin_unlock_irqrestore(&chip->msg_lock, flags); 758 return err; 759 } 760 761 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, 762 u64 *r_bytepos) 763 { 764 int err; 765 unsigned long flags; 766 767 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 768 769 spin_lock_irqsave(&chip->msg_lock, flags); 770 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 771 772 chip->rmh.cmd[0] |= pipe_cmd; 773 774 err = lx_message_send_atomic(chip, &chip->rmh); 775 776 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 777 << 32) /* hi part */ 778 + chip->rmh.stat[1]; /* lo part */ 779 780 spin_unlock_irqrestore(&chip->msg_lock, flags); 781 return err; 782 } 783 784 /* low-level buffer handling */ 785 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, 786 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, 787 u32 *r_buffer_index) 788 { 789 int err; 790 unsigned long flags; 791 792 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 793 794 spin_lock_irqsave(&chip->msg_lock, flags); 795 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER); 796 797 chip->rmh.cmd[0] |= pipe_cmd; 798 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ 799 800 /* todo: pause request, circular buffer */ 801 802 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE; 803 chip->rmh.cmd[2] = buf_address_lo; 804 805 if (buf_address_hi) { 806 chip->rmh.cmd_len = 4; 807 chip->rmh.cmd[3] = buf_address_hi; 808 chip->rmh.cmd[0] |= BF_64BITS_ADR; 809 } 810 811 err = lx_message_send_atomic(chip, &chip->rmh); 812 813 if (err == 0) { 814 *r_buffer_index = chip->rmh.stat[0]; 815 goto done; 816 } 817 818 if (err == EB_RBUFFERS_TABLE_OVERFLOW) 819 dev_err(chip->card->dev, 820 "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n"); 821 822 if (err == EB_INVALID_STREAM) 823 dev_err(chip->card->dev, 824 "lx_buffer_give EB_INVALID_STREAM\n"); 825 826 if (err == EB_CMD_REFUSED) 827 dev_err(chip->card->dev, 828 "lx_buffer_give EB_CMD_REFUSED\n"); 829 830 done: 831 spin_unlock_irqrestore(&chip->msg_lock, flags); 832 return err; 833 } 834 835 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, 836 u32 *r_buffer_size) 837 { 838 int err; 839 unsigned long flags; 840 841 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 842 843 spin_lock_irqsave(&chip->msg_lock, flags); 844 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 845 846 chip->rmh.cmd[0] |= pipe_cmd; 847 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the 848 * microblaze will seek for it */ 849 850 err = lx_message_send_atomic(chip, &chip->rmh); 851 852 if (err == 0) 853 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; 854 855 spin_unlock_irqrestore(&chip->msg_lock, flags); 856 return err; 857 } 858 859 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, 860 u32 buffer_index) 861 { 862 int err; 863 unsigned long flags; 864 865 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 866 867 spin_lock_irqsave(&chip->msg_lock, flags); 868 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 869 870 chip->rmh.cmd[0] |= pipe_cmd; 871 chip->rmh.cmd[0] |= buffer_index; 872 873 err = lx_message_send_atomic(chip, &chip->rmh); 874 875 spin_unlock_irqrestore(&chip->msg_lock, flags); 876 return err; 877 } 878 879 880 /* low-level gain/peak handling 881 * 882 * \todo: can we unmute capture/playback channels independently? 883 * 884 * */ 885 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute) 886 { 887 int err; 888 unsigned long flags; 889 890 /* bit set to 1: channel muted */ 891 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; 892 893 spin_lock_irqsave(&chip->msg_lock, flags); 894 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE); 895 896 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); 897 898 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */ 899 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ 900 901 dev_dbg(chip->card->dev, 902 "mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], 903 chip->rmh.cmd[2]); 904 905 err = lx_message_send_atomic(chip, &chip->rmh); 906 907 spin_unlock_irqrestore(&chip->msg_lock, flags); 908 return err; 909 } 910 911 static u32 peak_map[] = { 912 0x00000109, /* -90.308dB */ 913 0x0000083B, /* -72.247dB */ 914 0x000020C4, /* -60.205dB */ 915 0x00008273, /* -48.030dB */ 916 0x00020756, /* -36.005dB */ 917 0x00040C37, /* -30.001dB */ 918 0x00081385, /* -24.002dB */ 919 0x00101D3F, /* -18.000dB */ 920 0x0016C310, /* -15.000dB */ 921 0x002026F2, /* -12.001dB */ 922 0x002D6A86, /* -9.000dB */ 923 0x004026E6, /* -6.004dB */ 924 0x005A9DF6, /* -3.000dB */ 925 0x0065AC8B, /* -2.000dB */ 926 0x00721481, /* -1.000dB */ 927 0x007FFFFF, /* FS */ 928 }; 929 930 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, 931 u32 *r_levels) 932 { 933 int err = 0; 934 unsigned long flags; 935 int i; 936 spin_lock_irqsave(&chip->msg_lock, flags); 937 938 for (i = 0; i < channels; i += 4) { 939 u32 s0, s1, s2, s3; 940 941 lx_message_init(&chip->rmh, CMD_12_GET_PEAK); 942 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); 943 944 err = lx_message_send_atomic(chip, &chip->rmh); 945 946 if (err == 0) { 947 s0 = peak_map[chip->rmh.stat[0] & 0x0F]; 948 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; 949 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; 950 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; 951 } else 952 s0 = s1 = s2 = s3 = 0; 953 954 r_levels[0] = s0; 955 r_levels[1] = s1; 956 r_levels[2] = s2; 957 r_levels[3] = s3; 958 959 r_levels += 4; 960 } 961 962 spin_unlock_irqrestore(&chip->msg_lock, flags); 963 return err; 964 } 965 966 /* interrupt handling */ 967 #define PCX_IRQ_NONE 0 968 #define IRQCS_ACTIVE_PCIDB BIT(13) 969 #define IRQCS_ENABLE_PCIIRQ BIT(8) 970 #define IRQCS_ENABLE_PCIDB BIT(9) 971 972 static u32 lx_interrupt_test_ack(struct lx6464es *chip) 973 { 974 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS); 975 976 /* Test if PCI Doorbell interrupt is active */ 977 if (irqcs & IRQCS_ACTIVE_PCIDB) { 978 u32 temp; 979 irqcs = PCX_IRQ_NONE; 980 981 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) { 982 /* RAZ interrupt */ 983 irqcs |= temp; 984 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp); 985 } 986 987 return irqcs; 988 } 989 return PCX_IRQ_NONE; 990 } 991 992 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc, 993 int *r_async_pending, int *r_async_escmd) 994 { 995 u32 irq_async; 996 u32 irqsrc = lx_interrupt_test_ack(chip); 997 998 if (irqsrc == PCX_IRQ_NONE) 999 return 0; 1000 1001 *r_irqsrc = irqsrc; 1002 1003 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response 1004 * (set by xilinx) + EOB */ 1005 1006 if (irq_async & MASK_SYS_STATUS_ESA) { 1007 irq_async &= ~MASK_SYS_STATUS_ESA; 1008 *r_async_escmd = 1; 1009 } 1010 1011 if (irq_async) { 1012 /* dev_dbg(chip->card->dev, "interrupt: async event pending\n"); */ 1013 *r_async_pending = 1; 1014 } 1015 1016 return 1; 1017 } 1018 1019 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc, 1020 int *r_freq_changed, 1021 u64 *r_notified_in_pipe_mask, 1022 u64 *r_notified_out_pipe_mask) 1023 { 1024 int err; 1025 u32 stat[9]; /* answer from CMD_04_GET_EVENT */ 1026 1027 /* We can optimize this to not read dumb events. 1028 * Answer words are in the following order: 1029 * Stat[0] general status 1030 * Stat[1] end of buffer OUT pF 1031 * Stat[2] end of buffer OUT pf 1032 * Stat[3] end of buffer IN pF 1033 * Stat[4] end of buffer IN pf 1034 * Stat[5] MSB underrun 1035 * Stat[6] LSB underrun 1036 * Stat[7] MSB overrun 1037 * Stat[8] LSB overrun 1038 * */ 1039 1040 u64 orun_mask; 1041 u64 urun_mask; 1042 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; 1043 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; 1044 1045 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; 1046 1047 err = lx_dsp_read_async_events(chip, stat); 1048 if (err < 0) 1049 return err; 1050 1051 if (eb_pending_in) { 1052 *r_notified_in_pipe_mask = ((u64)stat[3] << 32) 1053 + stat[4]; 1054 dev_dbg(chip->card->dev, "interrupt: EOBI pending %llx\n", 1055 *r_notified_in_pipe_mask); 1056 } 1057 if (eb_pending_out) { 1058 *r_notified_out_pipe_mask = ((u64)stat[1] << 32) 1059 + stat[2]; 1060 dev_dbg(chip->card->dev, "interrupt: EOBO pending %llx\n", 1061 *r_notified_out_pipe_mask); 1062 } 1063 1064 orun_mask = ((u64)stat[7] << 32) + stat[8]; 1065 urun_mask = ((u64)stat[5] << 32) + stat[6]; 1066 1067 /* todo: handle xrun notification */ 1068 1069 return err; 1070 } 1071 1072 static int lx_interrupt_request_new_buffer(struct lx6464es *chip, 1073 struct lx_stream *lx_stream) 1074 { 1075 struct snd_pcm_substream *substream = lx_stream->stream; 1076 const unsigned int is_capture = lx_stream->is_capture; 1077 int err; 1078 unsigned long flags; 1079 1080 const u32 channels = substream->runtime->channels; 1081 const u32 bytes_per_frame = channels * 3; 1082 const u32 period_size = substream->runtime->period_size; 1083 const u32 period_bytes = period_size * bytes_per_frame; 1084 const u32 pos = lx_stream->frame_pos; 1085 const u32 next_pos = ((pos+1) == substream->runtime->periods) ? 1086 0 : pos + 1; 1087 1088 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes; 1089 u32 buf_hi = 0; 1090 u32 buf_lo = 0; 1091 u32 buffer_index = 0; 1092 1093 u32 needed, freed; 1094 u32 size_array[MAX_STREAM_BUFFER]; 1095 1096 dev_dbg(chip->card->dev, "->lx_interrupt_request_new_buffer\n"); 1097 1098 spin_lock_irqsave(&chip->lock, flags); 1099 1100 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); 1101 dev_dbg(chip->card->dev, 1102 "interrupt: needed %d, freed %d\n", needed, freed); 1103 1104 unpack_pointer(buf, &buf_lo, &buf_hi); 1105 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, 1106 &buffer_index); 1107 dev_dbg(chip->card->dev, 1108 "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n", 1109 buffer_index, (unsigned long)buf, period_bytes); 1110 1111 lx_stream->frame_pos = next_pos; 1112 spin_unlock_irqrestore(&chip->lock, flags); 1113 1114 return err; 1115 } 1116 1117 void lx_tasklet_playback(unsigned long data) 1118 { 1119 struct lx6464es *chip = (struct lx6464es *)data; 1120 struct lx_stream *lx_stream = &chip->playback_stream; 1121 int err; 1122 1123 dev_dbg(chip->card->dev, "->lx_tasklet_playback\n"); 1124 1125 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1126 if (err < 0) 1127 dev_err(chip->card->dev, 1128 "cannot request new buffer for playback\n"); 1129 1130 snd_pcm_period_elapsed(lx_stream->stream); 1131 } 1132 1133 void lx_tasklet_capture(unsigned long data) 1134 { 1135 struct lx6464es *chip = (struct lx6464es *)data; 1136 struct lx_stream *lx_stream = &chip->capture_stream; 1137 int err; 1138 1139 dev_dbg(chip->card->dev, "->lx_tasklet_capture\n"); 1140 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1141 if (err < 0) 1142 dev_err(chip->card->dev, 1143 "cannot request new buffer for capture\n"); 1144 1145 snd_pcm_period_elapsed(lx_stream->stream); 1146 } 1147 1148 1149 1150 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip, 1151 u64 notified_in_pipe_mask, 1152 u64 notified_out_pipe_mask) 1153 { 1154 int err = 0; 1155 1156 if (notified_in_pipe_mask) { 1157 dev_dbg(chip->card->dev, 1158 "requesting audio transfer for capture\n"); 1159 tasklet_hi_schedule(&chip->tasklet_capture); 1160 } 1161 1162 if (notified_out_pipe_mask) { 1163 dev_dbg(chip->card->dev, 1164 "requesting audio transfer for playback\n"); 1165 tasklet_hi_schedule(&chip->tasklet_playback); 1166 } 1167 1168 return err; 1169 } 1170 1171 1172 irqreturn_t lx_interrupt(int irq, void *dev_id) 1173 { 1174 struct lx6464es *chip = dev_id; 1175 int async_pending, async_escmd; 1176 u32 irqsrc; 1177 1178 spin_lock(&chip->lock); 1179 1180 dev_dbg(chip->card->dev, 1181 "**************************************************\n"); 1182 1183 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) { 1184 spin_unlock(&chip->lock); 1185 dev_dbg(chip->card->dev, "IRQ_NONE\n"); 1186 return IRQ_NONE; /* this device did not cause the interrupt */ 1187 } 1188 1189 if (irqsrc & MASK_SYS_STATUS_CMD_DONE) 1190 goto exit; 1191 1192 if (irqsrc & MASK_SYS_STATUS_EOBI) 1193 dev_dbg(chip->card->dev, "interrupt: EOBI\n"); 1194 1195 if (irqsrc & MASK_SYS_STATUS_EOBO) 1196 dev_dbg(chip->card->dev, "interrupt: EOBO\n"); 1197 1198 if (irqsrc & MASK_SYS_STATUS_URUN) 1199 dev_dbg(chip->card->dev, "interrupt: URUN\n"); 1200 1201 if (irqsrc & MASK_SYS_STATUS_ORUN) 1202 dev_dbg(chip->card->dev, "interrupt: ORUN\n"); 1203 1204 if (async_pending) { 1205 u64 notified_in_pipe_mask = 0; 1206 u64 notified_out_pipe_mask = 0; 1207 int freq_changed; 1208 int err; 1209 1210 /* handle async events */ 1211 err = lx_interrupt_handle_async_events(chip, irqsrc, 1212 &freq_changed, 1213 ¬ified_in_pipe_mask, 1214 ¬ified_out_pipe_mask); 1215 if (err) 1216 dev_err(chip->card->dev, 1217 "error handling async events\n"); 1218 1219 err = lx_interrupt_handle_audio_transfer(chip, 1220 notified_in_pipe_mask, 1221 notified_out_pipe_mask 1222 ); 1223 if (err) 1224 dev_err(chip->card->dev, 1225 "error during audio transfer\n"); 1226 } 1227 1228 if (async_escmd) { 1229 /* backdoor for ethersound commands 1230 * 1231 * for now, we do not need this 1232 * 1233 * */ 1234 1235 dev_dbg(chip->card->dev, "interrupt requests escmd handling\n"); 1236 } 1237 1238 exit: 1239 spin_unlock(&chip->lock); 1240 return IRQ_HANDLED; /* this device caused the interrupt */ 1241 } 1242 1243 1244 static void lx_irq_set(struct lx6464es *chip, int enable) 1245 { 1246 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); 1247 1248 /* enable/disable interrupts 1249 * 1250 * Set the Doorbell and PCI interrupt enable bits 1251 * 1252 * */ 1253 if (enable) 1254 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1255 else 1256 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1257 lx_plx_reg_write(chip, ePLX_IRQCS, reg); 1258 } 1259 1260 void lx_irq_enable(struct lx6464es *chip) 1261 { 1262 dev_dbg(chip->card->dev, "->lx_irq_enable\n"); 1263 lx_irq_set(chip, 1); 1264 } 1265 1266 void lx_irq_disable(struct lx6464es *chip) 1267 { 1268 dev_dbg(chip->card->dev, "->lx_irq_disable\n"); 1269 lx_irq_set(chip, 0); 1270 } 1271