1 /* -*- linux-c -*- * 2 * 3 * ALSA driver for the digigram lx6464es interface 4 * low-level interface 5 * 6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; see the file COPYING. If not, write to 20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, 21 * Boston, MA 02111-1307, USA. 22 * 23 */ 24 25 /* #define RMH_DEBUG 1 */ 26 27 #include <linux/module.h> 28 #include <linux/pci.h> 29 #include <linux/delay.h> 30 31 #include "lx6464es.h" 32 #include "lx_core.h" 33 34 /* low-level register access */ 35 36 static const unsigned long dsp_port_offsets[] = { 37 0, 38 0x400, 39 0x401, 40 0x402, 41 0x403, 42 0x404, 43 0x405, 44 0x406, 45 0x407, 46 0x408, 47 0x409, 48 0x40a, 49 0x40b, 50 0x40c, 51 52 0x410, 53 0x411, 54 0x412, 55 0x413, 56 0x414, 57 0x415, 58 0x416, 59 60 0x420, 61 0x430, 62 0x431, 63 0x432, 64 0x433, 65 0x434, 66 0x440 67 }; 68 69 static void __iomem *lx_dsp_register(struct lx6464es *chip, int port) 70 { 71 void __iomem *base_address = chip->port_dsp_bar; 72 return base_address + dsp_port_offsets[port]*4; 73 } 74 75 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port) 76 { 77 void __iomem *address = lx_dsp_register(chip, port); 78 return ioread32(address); 79 } 80 81 static void lx_dsp_reg_readbuf(struct lx6464es *chip, int port, u32 *data, 82 u32 len) 83 { 84 u32 __iomem *address = lx_dsp_register(chip, port); 85 int i; 86 87 /* we cannot use memcpy_fromio */ 88 for (i = 0; i != len; ++i) 89 data[i] = ioread32(address + i); 90 } 91 92 93 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data) 94 { 95 void __iomem *address = lx_dsp_register(chip, port); 96 iowrite32(data, address); 97 } 98 99 static void lx_dsp_reg_writebuf(struct lx6464es *chip, int port, 100 const u32 *data, u32 len) 101 { 102 u32 __iomem *address = lx_dsp_register(chip, port); 103 int i; 104 105 /* we cannot use memcpy_to */ 106 for (i = 0; i != len; ++i) 107 iowrite32(data[i], address + i); 108 } 109 110 111 static const unsigned long plx_port_offsets[] = { 112 0x04, 113 0x40, 114 0x44, 115 0x48, 116 0x4c, 117 0x50, 118 0x54, 119 0x58, 120 0x5c, 121 0x64, 122 0x68, 123 0x6C 124 }; 125 126 static void __iomem *lx_plx_register(struct lx6464es *chip, int port) 127 { 128 void __iomem *base_address = chip->port_plx_remapped; 129 return base_address + plx_port_offsets[port]; 130 } 131 132 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port) 133 { 134 void __iomem *address = lx_plx_register(chip, port); 135 return ioread32(address); 136 } 137 138 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data) 139 { 140 void __iomem *address = lx_plx_register(chip, port); 141 iowrite32(data, address); 142 } 143 144 /* rmh */ 145 146 #ifdef CONFIG_SND_DEBUG 147 #define CMD_NAME(a) a 148 #else 149 #define CMD_NAME(a) NULL 150 #endif 151 152 #define Reg_CSM_MR 0x00000002 153 #define Reg_CSM_MC 0x00000001 154 155 struct dsp_cmd_info { 156 u32 dcCodeOp; /* Op Code of the command (usually 1st 24-bits 157 * word).*/ 158 u16 dcCmdLength; /* Command length in words of 24 bits.*/ 159 u16 dcStatusType; /* Status type: 0 for fixed length, 1 for 160 * random. */ 161 u16 dcStatusLength; /* Status length (if fixed).*/ 162 char *dcOpName; 163 }; 164 165 /* 166 Initialization and control data for the Microblaze interface 167 - OpCode: 168 the opcode field of the command set at the proper offset 169 - CmdLength 170 the number of command words 171 - StatusType 172 offset in the status registers: 0 means that the return value may be 173 different from 0, and must be read 174 - StatusLength 175 the number of status words (in addition to the return value) 176 */ 177 178 static struct dsp_cmd_info dsp_commands[] = 179 { 180 { (CMD_00_INFO_DEBUG << OPCODE_OFFSET) , 1 /*custom*/ 181 , 1 , 0 /**/ , CMD_NAME("INFO_DEBUG") }, 182 { (CMD_01_GET_SYS_CFG << OPCODE_OFFSET) , 1 /**/ 183 , 1 , 2 /**/ , CMD_NAME("GET_SYS_CFG") }, 184 { (CMD_02_SET_GRANULARITY << OPCODE_OFFSET) , 1 /**/ 185 , 1 , 0 /**/ , CMD_NAME("SET_GRANULARITY") }, 186 { (CMD_03_SET_TIMER_IRQ << OPCODE_OFFSET) , 1 /**/ 187 , 1 , 0 /**/ , CMD_NAME("SET_TIMER_IRQ") }, 188 { (CMD_04_GET_EVENT << OPCODE_OFFSET) , 1 /**/ 189 , 1 , 0 /*up to 10*/ , CMD_NAME("GET_EVENT") }, 190 { (CMD_05_GET_PIPES << OPCODE_OFFSET) , 1 /**/ 191 , 1 , 2 /*up to 4*/ , CMD_NAME("GET_PIPES") }, 192 { (CMD_06_ALLOCATE_PIPE << OPCODE_OFFSET) , 1 /**/ 193 , 0 , 0 /**/ , CMD_NAME("ALLOCATE_PIPE") }, 194 { (CMD_07_RELEASE_PIPE << OPCODE_OFFSET) , 1 /**/ 195 , 0 , 0 /**/ , CMD_NAME("RELEASE_PIPE") }, 196 { (CMD_08_ASK_BUFFERS << OPCODE_OFFSET) , 1 /**/ 197 , 1 , MAX_STREAM_BUFFER , CMD_NAME("ASK_BUFFERS") }, 198 { (CMD_09_STOP_PIPE << OPCODE_OFFSET) , 1 /**/ 199 , 0 , 0 /*up to 2*/ , CMD_NAME("STOP_PIPE") }, 200 { (CMD_0A_GET_PIPE_SPL_COUNT << OPCODE_OFFSET) , 1 /**/ 201 , 1 , 1 /*up to 2*/ , CMD_NAME("GET_PIPE_SPL_COUNT") }, 202 { (CMD_0B_TOGGLE_PIPE_STATE << OPCODE_OFFSET) , 1 /*up to 5*/ 203 , 1 , 0 /**/ , CMD_NAME("TOGGLE_PIPE_STATE") }, 204 { (CMD_0C_DEF_STREAM << OPCODE_OFFSET) , 1 /*up to 4*/ 205 , 1 , 0 /**/ , CMD_NAME("DEF_STREAM") }, 206 { (CMD_0D_SET_MUTE << OPCODE_OFFSET) , 3 /**/ 207 , 1 , 0 /**/ , CMD_NAME("SET_MUTE") }, 208 { (CMD_0E_GET_STREAM_SPL_COUNT << OPCODE_OFFSET) , 1/**/ 209 , 1 , 2 /**/ , CMD_NAME("GET_STREAM_SPL_COUNT") }, 210 { (CMD_0F_UPDATE_BUFFER << OPCODE_OFFSET) , 3 /*up to 4*/ 211 , 0 , 1 /**/ , CMD_NAME("UPDATE_BUFFER") }, 212 { (CMD_10_GET_BUFFER << OPCODE_OFFSET) , 1 /**/ 213 , 1 , 4 /**/ , CMD_NAME("GET_BUFFER") }, 214 { (CMD_11_CANCEL_BUFFER << OPCODE_OFFSET) , 1 /**/ 215 , 1 , 1 /*up to 4*/ , CMD_NAME("CANCEL_BUFFER") }, 216 { (CMD_12_GET_PEAK << OPCODE_OFFSET) , 1 /**/ 217 , 1 , 1 /**/ , CMD_NAME("GET_PEAK") }, 218 { (CMD_13_SET_STREAM_STATE << OPCODE_OFFSET) , 1 /**/ 219 , 1 , 0 /**/ , CMD_NAME("SET_STREAM_STATE") }, 220 }; 221 222 static void lx_message_init(struct lx_rmh *rmh, enum cmd_mb_opcodes cmd) 223 { 224 snd_BUG_ON(cmd >= CMD_14_INVALID); 225 226 rmh->cmd[0] = dsp_commands[cmd].dcCodeOp; 227 rmh->cmd_len = dsp_commands[cmd].dcCmdLength; 228 rmh->stat_len = dsp_commands[cmd].dcStatusLength; 229 rmh->dsp_stat = dsp_commands[cmd].dcStatusType; 230 rmh->cmd_idx = cmd; 231 memset(&rmh->cmd[1], 0, (REG_CRM_NUMBER - 1) * sizeof(u32)); 232 233 #ifdef CONFIG_SND_DEBUG 234 memset(rmh->stat, 0, REG_CRM_NUMBER * sizeof(u32)); 235 #endif 236 #ifdef RMH_DEBUG 237 rmh->cmd_idx = cmd; 238 #endif 239 } 240 241 #ifdef RMH_DEBUG 242 #define LXRMH "lx6464es rmh: " 243 static void lx_message_dump(struct lx_rmh *rmh) 244 { 245 u8 idx = rmh->cmd_idx; 246 int i; 247 248 snd_printk(LXRMH "command %s\n", dsp_commands[idx].dcOpName); 249 250 for (i = 0; i != rmh->cmd_len; ++i) 251 snd_printk(LXRMH "\tcmd[%d] %08x\n", i, rmh->cmd[i]); 252 253 for (i = 0; i != rmh->stat_len; ++i) 254 snd_printk(LXRMH "\tstat[%d]: %08x\n", i, rmh->stat[i]); 255 snd_printk("\n"); 256 } 257 #else 258 static inline void lx_message_dump(struct lx_rmh *rmh) 259 {} 260 #endif 261 262 263 264 /* sleep 500 - 100 = 400 times 100us -> the timeout is >= 40 ms */ 265 #define XILINX_TIMEOUT_MS 40 266 #define XILINX_POLL_NO_SLEEP 100 267 #define XILINX_POLL_ITERATIONS 150 268 269 270 static int lx_message_send_atomic(struct lx6464es *chip, struct lx_rmh *rmh) 271 { 272 u32 reg = ED_DSP_TIMED_OUT; 273 int dwloop; 274 275 if (lx_dsp_reg_read(chip, eReg_CSM) & (Reg_CSM_MC | Reg_CSM_MR)) { 276 snd_printk(KERN_ERR LXP "PIOSendMessage eReg_CSM %x\n", reg); 277 return -EBUSY; 278 } 279 280 /* write command */ 281 lx_dsp_reg_writebuf(chip, eReg_CRM1, rmh->cmd, rmh->cmd_len); 282 283 /* MicoBlaze gogogo */ 284 lx_dsp_reg_write(chip, eReg_CSM, Reg_CSM_MC); 285 286 /* wait for device to answer */ 287 for (dwloop = 0; dwloop != XILINX_TIMEOUT_MS * 1000; ++dwloop) { 288 if (lx_dsp_reg_read(chip, eReg_CSM) & Reg_CSM_MR) { 289 if (rmh->dsp_stat == 0) 290 reg = lx_dsp_reg_read(chip, eReg_CRM1); 291 else 292 reg = 0; 293 goto polling_successful; 294 } else 295 udelay(1); 296 } 297 snd_printk(KERN_WARNING LXP "TIMEOUT lx_message_send_atomic! " 298 "polling failed\n"); 299 300 polling_successful: 301 if ((reg & ERROR_VALUE) == 0) { 302 /* read response */ 303 if (rmh->stat_len) { 304 snd_BUG_ON(rmh->stat_len >= (REG_CRM_NUMBER-1)); 305 lx_dsp_reg_readbuf(chip, eReg_CRM2, rmh->stat, 306 rmh->stat_len); 307 } 308 } else 309 snd_printk(LXP "rmh error: %08x\n", reg); 310 311 /* clear Reg_CSM_MR */ 312 lx_dsp_reg_write(chip, eReg_CSM, 0); 313 314 switch (reg) { 315 case ED_DSP_TIMED_OUT: 316 snd_printk(KERN_WARNING LXP "lx_message_send: dsp timeout\n"); 317 return -ETIMEDOUT; 318 319 case ED_DSP_CRASHED: 320 snd_printk(KERN_WARNING LXP "lx_message_send: dsp crashed\n"); 321 return -EAGAIN; 322 } 323 324 lx_message_dump(rmh); 325 326 return reg; 327 } 328 329 330 /* low-level dsp access */ 331 int lx_dsp_get_version(struct lx6464es *chip, u32 *rdsp_version) 332 { 333 u16 ret; 334 unsigned long flags; 335 336 spin_lock_irqsave(&chip->msg_lock, flags); 337 338 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 339 ret = lx_message_send_atomic(chip, &chip->rmh); 340 341 *rdsp_version = chip->rmh.stat[1]; 342 spin_unlock_irqrestore(&chip->msg_lock, flags); 343 return ret; 344 } 345 346 int lx_dsp_get_clock_frequency(struct lx6464es *chip, u32 *rfreq) 347 { 348 u16 ret = 0; 349 unsigned long flags; 350 u32 freq_raw = 0; 351 u32 freq = 0; 352 u32 frequency = 0; 353 354 spin_lock_irqsave(&chip->msg_lock, flags); 355 356 lx_message_init(&chip->rmh, CMD_01_GET_SYS_CFG); 357 ret = lx_message_send_atomic(chip, &chip->rmh); 358 359 if (ret == 0) { 360 freq_raw = chip->rmh.stat[0] >> FREQ_FIELD_OFFSET; 361 freq = freq_raw & XES_FREQ_COUNT8_MASK; 362 363 if ((freq < XES_FREQ_COUNT8_48_MAX) || 364 (freq > XES_FREQ_COUNT8_44_MIN)) 365 frequency = 0; /* unknown */ 366 else if (freq >= XES_FREQ_COUNT8_44_MAX) 367 frequency = 44100; 368 else 369 frequency = 48000; 370 } 371 372 spin_unlock_irqrestore(&chip->msg_lock, flags); 373 374 *rfreq = frequency * chip->freq_ratio; 375 376 return ret; 377 } 378 379 int lx_dsp_get_mac(struct lx6464es *chip) 380 { 381 u32 macmsb, maclsb; 382 383 macmsb = lx_dsp_reg_read(chip, eReg_ADMACESMSB) & 0x00FFFFFF; 384 maclsb = lx_dsp_reg_read(chip, eReg_ADMACESLSB) & 0x00FFFFFF; 385 386 /* todo: endianess handling */ 387 chip->mac_address[5] = ((u8 *)(&maclsb))[0]; 388 chip->mac_address[4] = ((u8 *)(&maclsb))[1]; 389 chip->mac_address[3] = ((u8 *)(&maclsb))[2]; 390 chip->mac_address[2] = ((u8 *)(&macmsb))[0]; 391 chip->mac_address[1] = ((u8 *)(&macmsb))[1]; 392 chip->mac_address[0] = ((u8 *)(&macmsb))[2]; 393 394 return 0; 395 } 396 397 398 int lx_dsp_set_granularity(struct lx6464es *chip, u32 gran) 399 { 400 unsigned long flags; 401 int ret; 402 403 spin_lock_irqsave(&chip->msg_lock, flags); 404 405 lx_message_init(&chip->rmh, CMD_02_SET_GRANULARITY); 406 chip->rmh.cmd[0] |= gran; 407 408 ret = lx_message_send_atomic(chip, &chip->rmh); 409 spin_unlock_irqrestore(&chip->msg_lock, flags); 410 return ret; 411 } 412 413 int lx_dsp_read_async_events(struct lx6464es *chip, u32 *data) 414 { 415 unsigned long flags; 416 int ret; 417 418 spin_lock_irqsave(&chip->msg_lock, flags); 419 420 lx_message_init(&chip->rmh, CMD_04_GET_EVENT); 421 chip->rmh.stat_len = 9; /* we don't necessarily need the full length */ 422 423 ret = lx_message_send_atomic(chip, &chip->rmh); 424 425 if (!ret) 426 memcpy(data, chip->rmh.stat, chip->rmh.stat_len * sizeof(u32)); 427 428 spin_unlock_irqrestore(&chip->msg_lock, flags); 429 return ret; 430 } 431 432 #define CSES_TIMEOUT 100 /* microseconds */ 433 #define CSES_CE 0x0001 434 #define CSES_BROADCAST 0x0002 435 #define CSES_UPDATE_LDSV 0x0004 436 437 #define PIPE_INFO_TO_CMD(capture, pipe) \ 438 ((u32)((u32)(pipe) | ((capture) ? ID_IS_CAPTURE : 0L)) << ID_OFFSET) 439 440 441 442 /* low-level pipe handling */ 443 int lx_pipe_allocate(struct lx6464es *chip, u32 pipe, int is_capture, 444 int channels) 445 { 446 int err; 447 unsigned long flags; 448 449 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 450 451 spin_lock_irqsave(&chip->msg_lock, flags); 452 lx_message_init(&chip->rmh, CMD_06_ALLOCATE_PIPE); 453 454 chip->rmh.cmd[0] |= pipe_cmd; 455 chip->rmh.cmd[0] |= channels; 456 457 err = lx_message_send_atomic(chip, &chip->rmh); 458 spin_unlock_irqrestore(&chip->msg_lock, flags); 459 460 if (err != 0) 461 snd_printk(KERN_ERR "lx6464es: could not allocate pipe\n"); 462 463 return err; 464 } 465 466 int lx_pipe_release(struct lx6464es *chip, u32 pipe, int is_capture) 467 { 468 int err; 469 unsigned long flags; 470 471 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 472 473 spin_lock_irqsave(&chip->msg_lock, flags); 474 lx_message_init(&chip->rmh, CMD_07_RELEASE_PIPE); 475 476 chip->rmh.cmd[0] |= pipe_cmd; 477 478 err = lx_message_send_atomic(chip, &chip->rmh); 479 spin_unlock_irqrestore(&chip->msg_lock, flags); 480 481 return err; 482 } 483 484 int lx_buffer_ask(struct lx6464es *chip, u32 pipe, int is_capture, 485 u32 *r_needed, u32 *r_freed, u32 *size_array) 486 { 487 int err; 488 unsigned long flags; 489 490 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 491 492 #ifdef CONFIG_SND_DEBUG 493 if (size_array) 494 memset(size_array, 0, sizeof(u32)*MAX_STREAM_BUFFER); 495 #endif 496 497 *r_needed = 0; 498 *r_freed = 0; 499 500 spin_lock_irqsave(&chip->msg_lock, flags); 501 lx_message_init(&chip->rmh, CMD_08_ASK_BUFFERS); 502 503 chip->rmh.cmd[0] |= pipe_cmd; 504 505 err = lx_message_send_atomic(chip, &chip->rmh); 506 507 if (!err) { 508 int i; 509 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 510 u32 stat = chip->rmh.stat[i]; 511 if (stat & (BF_EOB << BUFF_FLAGS_OFFSET)) { 512 /* finished */ 513 *r_freed += 1; 514 if (size_array) 515 size_array[i] = stat & MASK_DATA_SIZE; 516 } else if ((stat & (BF_VALID << BUFF_FLAGS_OFFSET)) 517 == 0) 518 /* free */ 519 *r_needed += 1; 520 } 521 522 #if 0 523 snd_printdd(LXP "CMD_08_ASK_BUFFERS: needed %d, freed %d\n", 524 *r_needed, *r_freed); 525 for (i = 0; i < MAX_STREAM_BUFFER; ++i) { 526 for (i = 0; i != chip->rmh.stat_len; ++i) 527 snd_printdd(" stat[%d]: %x, %x\n", i, 528 chip->rmh.stat[i], 529 chip->rmh.stat[i] & MASK_DATA_SIZE); 530 } 531 #endif 532 } 533 534 spin_unlock_irqrestore(&chip->msg_lock, flags); 535 return err; 536 } 537 538 539 int lx_pipe_stop(struct lx6464es *chip, u32 pipe, int is_capture) 540 { 541 int err; 542 unsigned long flags; 543 544 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 545 546 spin_lock_irqsave(&chip->msg_lock, flags); 547 lx_message_init(&chip->rmh, CMD_09_STOP_PIPE); 548 549 chip->rmh.cmd[0] |= pipe_cmd; 550 551 err = lx_message_send_atomic(chip, &chip->rmh); 552 553 spin_unlock_irqrestore(&chip->msg_lock, flags); 554 return err; 555 } 556 557 static int lx_pipe_toggle_state(struct lx6464es *chip, u32 pipe, int is_capture) 558 { 559 int err; 560 unsigned long flags; 561 562 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 563 564 spin_lock_irqsave(&chip->msg_lock, flags); 565 lx_message_init(&chip->rmh, CMD_0B_TOGGLE_PIPE_STATE); 566 567 chip->rmh.cmd[0] |= pipe_cmd; 568 569 err = lx_message_send_atomic(chip, &chip->rmh); 570 571 spin_unlock_irqrestore(&chip->msg_lock, flags); 572 return err; 573 } 574 575 576 int lx_pipe_start(struct lx6464es *chip, u32 pipe, int is_capture) 577 { 578 int err; 579 580 err = lx_pipe_wait_for_idle(chip, pipe, is_capture); 581 if (err < 0) 582 return err; 583 584 err = lx_pipe_toggle_state(chip, pipe, is_capture); 585 586 return err; 587 } 588 589 int lx_pipe_pause(struct lx6464es *chip, u32 pipe, int is_capture) 590 { 591 int err = 0; 592 593 err = lx_pipe_wait_for_start(chip, pipe, is_capture); 594 if (err < 0) 595 return err; 596 597 err = lx_pipe_toggle_state(chip, pipe, is_capture); 598 599 return err; 600 } 601 602 603 int lx_pipe_sample_count(struct lx6464es *chip, u32 pipe, int is_capture, 604 u64 *rsample_count) 605 { 606 int err; 607 unsigned long flags; 608 609 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 610 611 spin_lock_irqsave(&chip->msg_lock, flags); 612 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 613 614 chip->rmh.cmd[0] |= pipe_cmd; 615 chip->rmh.stat_len = 2; /* need all words here! */ 616 617 err = lx_message_send_atomic(chip, &chip->rmh); /* don't sleep! */ 618 619 if (err != 0) 620 snd_printk(KERN_ERR 621 "lx6464es: could not query pipe's sample count\n"); 622 else { 623 *rsample_count = ((u64)(chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 624 << 24) /* hi part */ 625 + chip->rmh.stat[1]; /* lo part */ 626 } 627 628 spin_unlock_irqrestore(&chip->msg_lock, flags); 629 return err; 630 } 631 632 int lx_pipe_state(struct lx6464es *chip, u32 pipe, int is_capture, u16 *rstate) 633 { 634 int err; 635 unsigned long flags; 636 637 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 638 639 spin_lock_irqsave(&chip->msg_lock, flags); 640 lx_message_init(&chip->rmh, CMD_0A_GET_PIPE_SPL_COUNT); 641 642 chip->rmh.cmd[0] |= pipe_cmd; 643 644 err = lx_message_send_atomic(chip, &chip->rmh); 645 646 if (err != 0) 647 snd_printk(KERN_ERR "lx6464es: could not query pipe's state\n"); 648 else 649 *rstate = (chip->rmh.stat[0] >> PSTATE_OFFSET) & 0x0F; 650 651 spin_unlock_irqrestore(&chip->msg_lock, flags); 652 return err; 653 } 654 655 static int lx_pipe_wait_for_state(struct lx6464es *chip, u32 pipe, 656 int is_capture, u16 state) 657 { 658 int i; 659 660 /* max 2*PCMOnlyGranularity = 2*1024 at 44100 = < 50 ms: 661 * timeout 50 ms */ 662 for (i = 0; i != 50; ++i) { 663 u16 current_state; 664 int err = lx_pipe_state(chip, pipe, is_capture, ¤t_state); 665 666 if (err < 0) 667 return err; 668 669 if (current_state == state) 670 return 0; 671 672 mdelay(1); 673 } 674 675 return -ETIMEDOUT; 676 } 677 678 int lx_pipe_wait_for_start(struct lx6464es *chip, u32 pipe, int is_capture) 679 { 680 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_RUN); 681 } 682 683 int lx_pipe_wait_for_idle(struct lx6464es *chip, u32 pipe, int is_capture) 684 { 685 return lx_pipe_wait_for_state(chip, pipe, is_capture, PSTATE_IDLE); 686 } 687 688 /* low-level stream handling */ 689 int lx_stream_set_state(struct lx6464es *chip, u32 pipe, 690 int is_capture, enum stream_state_t state) 691 { 692 int err; 693 unsigned long flags; 694 695 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 696 697 spin_lock_irqsave(&chip->msg_lock, flags); 698 lx_message_init(&chip->rmh, CMD_13_SET_STREAM_STATE); 699 700 chip->rmh.cmd[0] |= pipe_cmd; 701 chip->rmh.cmd[0] |= state; 702 703 err = lx_message_send_atomic(chip, &chip->rmh); 704 spin_unlock_irqrestore(&chip->msg_lock, flags); 705 706 return err; 707 } 708 709 int lx_stream_set_format(struct lx6464es *chip, struct snd_pcm_runtime *runtime, 710 u32 pipe, int is_capture) 711 { 712 int err; 713 unsigned long flags; 714 715 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 716 717 u32 channels = runtime->channels; 718 719 if (runtime->channels != channels) 720 snd_printk(KERN_ERR LXP "channel count mismatch: %d vs %d", 721 runtime->channels, channels); 722 723 spin_lock_irqsave(&chip->msg_lock, flags); 724 lx_message_init(&chip->rmh, CMD_0C_DEF_STREAM); 725 726 chip->rmh.cmd[0] |= pipe_cmd; 727 728 if (runtime->sample_bits == 16) 729 /* 16 bit format */ 730 chip->rmh.cmd[0] |= (STREAM_FMT_16b << STREAM_FMT_OFFSET); 731 732 if (snd_pcm_format_little_endian(runtime->format)) 733 /* little endian/intel format */ 734 chip->rmh.cmd[0] |= (STREAM_FMT_intel << STREAM_FMT_OFFSET); 735 736 chip->rmh.cmd[0] |= channels-1; 737 738 err = lx_message_send_atomic(chip, &chip->rmh); 739 spin_unlock_irqrestore(&chip->msg_lock, flags); 740 741 return err; 742 } 743 744 int lx_stream_state(struct lx6464es *chip, u32 pipe, int is_capture, 745 int *rstate) 746 { 747 int err; 748 unsigned long flags; 749 750 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 751 752 spin_lock_irqsave(&chip->msg_lock, flags); 753 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 754 755 chip->rmh.cmd[0] |= pipe_cmd; 756 757 err = lx_message_send_atomic(chip, &chip->rmh); 758 759 *rstate = (chip->rmh.stat[0] & SF_START) ? START_STATE : PAUSE_STATE; 760 761 spin_unlock_irqrestore(&chip->msg_lock, flags); 762 return err; 763 } 764 765 int lx_stream_sample_position(struct lx6464es *chip, u32 pipe, int is_capture, 766 u64 *r_bytepos) 767 { 768 int err; 769 unsigned long flags; 770 771 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 772 773 spin_lock_irqsave(&chip->msg_lock, flags); 774 lx_message_init(&chip->rmh, CMD_0E_GET_STREAM_SPL_COUNT); 775 776 chip->rmh.cmd[0] |= pipe_cmd; 777 778 err = lx_message_send_atomic(chip, &chip->rmh); 779 780 *r_bytepos = ((u64) (chip->rmh.stat[0] & MASK_SPL_COUNT_HI) 781 << 32) /* hi part */ 782 + chip->rmh.stat[1]; /* lo part */ 783 784 spin_unlock_irqrestore(&chip->msg_lock, flags); 785 return err; 786 } 787 788 /* low-level buffer handling */ 789 int lx_buffer_give(struct lx6464es *chip, u32 pipe, int is_capture, 790 u32 buffer_size, u32 buf_address_lo, u32 buf_address_hi, 791 u32 *r_buffer_index) 792 { 793 int err; 794 unsigned long flags; 795 796 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 797 798 spin_lock_irqsave(&chip->msg_lock, flags); 799 lx_message_init(&chip->rmh, CMD_0F_UPDATE_BUFFER); 800 801 chip->rmh.cmd[0] |= pipe_cmd; 802 chip->rmh.cmd[0] |= BF_NOTIFY_EOB; /* request interrupt notification */ 803 804 /* todo: pause request, circular buffer */ 805 806 chip->rmh.cmd[1] = buffer_size & MASK_DATA_SIZE; 807 chip->rmh.cmd[2] = buf_address_lo; 808 809 if (buf_address_hi) { 810 chip->rmh.cmd_len = 4; 811 chip->rmh.cmd[3] = buf_address_hi; 812 chip->rmh.cmd[0] |= BF_64BITS_ADR; 813 } 814 815 err = lx_message_send_atomic(chip, &chip->rmh); 816 817 if (err == 0) { 818 *r_buffer_index = chip->rmh.stat[0]; 819 goto done; 820 } 821 822 if (err == EB_RBUFFERS_TABLE_OVERFLOW) 823 snd_printk(LXP "lx_buffer_give EB_RBUFFERS_TABLE_OVERFLOW\n"); 824 825 if (err == EB_INVALID_STREAM) 826 snd_printk(LXP "lx_buffer_give EB_INVALID_STREAM\n"); 827 828 if (err == EB_CMD_REFUSED) 829 snd_printk(LXP "lx_buffer_give EB_CMD_REFUSED\n"); 830 831 done: 832 spin_unlock_irqrestore(&chip->msg_lock, flags); 833 return err; 834 } 835 836 int lx_buffer_free(struct lx6464es *chip, u32 pipe, int is_capture, 837 u32 *r_buffer_size) 838 { 839 int err; 840 unsigned long flags; 841 842 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 843 844 spin_lock_irqsave(&chip->msg_lock, flags); 845 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 846 847 chip->rmh.cmd[0] |= pipe_cmd; 848 chip->rmh.cmd[0] |= MASK_BUFFER_ID; /* ask for the current buffer: the 849 * microblaze will seek for it */ 850 851 err = lx_message_send_atomic(chip, &chip->rmh); 852 853 if (err == 0) 854 *r_buffer_size = chip->rmh.stat[0] & MASK_DATA_SIZE; 855 856 spin_unlock_irqrestore(&chip->msg_lock, flags); 857 return err; 858 } 859 860 int lx_buffer_cancel(struct lx6464es *chip, u32 pipe, int is_capture, 861 u32 buffer_index) 862 { 863 int err; 864 unsigned long flags; 865 866 u32 pipe_cmd = PIPE_INFO_TO_CMD(is_capture, pipe); 867 868 spin_lock_irqsave(&chip->msg_lock, flags); 869 lx_message_init(&chip->rmh, CMD_11_CANCEL_BUFFER); 870 871 chip->rmh.cmd[0] |= pipe_cmd; 872 chip->rmh.cmd[0] |= buffer_index; 873 874 err = lx_message_send_atomic(chip, &chip->rmh); 875 876 spin_unlock_irqrestore(&chip->msg_lock, flags); 877 return err; 878 } 879 880 881 /* low-level gain/peak handling 882 * 883 * \todo: can we unmute capture/playback channels independently? 884 * 885 * */ 886 int lx_level_unmute(struct lx6464es *chip, int is_capture, int unmute) 887 { 888 int err; 889 unsigned long flags; 890 891 /* bit set to 1: channel muted */ 892 u64 mute_mask = unmute ? 0 : 0xFFFFFFFFFFFFFFFFLLU; 893 894 spin_lock_irqsave(&chip->msg_lock, flags); 895 lx_message_init(&chip->rmh, CMD_0D_SET_MUTE); 896 897 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, 0); 898 899 chip->rmh.cmd[1] = (u32)(mute_mask >> (u64)32); /* hi part */ 900 chip->rmh.cmd[2] = (u32)(mute_mask & (u64)0xFFFFFFFF); /* lo part */ 901 902 snd_printk("mute %x %x %x\n", chip->rmh.cmd[0], chip->rmh.cmd[1], 903 chip->rmh.cmd[2]); 904 905 err = lx_message_send_atomic(chip, &chip->rmh); 906 907 spin_unlock_irqrestore(&chip->msg_lock, flags); 908 return err; 909 } 910 911 static u32 peak_map[] = { 912 0x00000109, /* -90.308dB */ 913 0x0000083B, /* -72.247dB */ 914 0x000020C4, /* -60.205dB */ 915 0x00008273, /* -48.030dB */ 916 0x00020756, /* -36.005dB */ 917 0x00040C37, /* -30.001dB */ 918 0x00081385, /* -24.002dB */ 919 0x00101D3F, /* -18.000dB */ 920 0x0016C310, /* -15.000dB */ 921 0x002026F2, /* -12.001dB */ 922 0x002D6A86, /* -9.000dB */ 923 0x004026E6, /* -6.004dB */ 924 0x005A9DF6, /* -3.000dB */ 925 0x0065AC8B, /* -2.000dB */ 926 0x00721481, /* -1.000dB */ 927 0x007FFFFF, /* FS */ 928 }; 929 930 int lx_level_peaks(struct lx6464es *chip, int is_capture, int channels, 931 u32 *r_levels) 932 { 933 int err = 0; 934 unsigned long flags; 935 int i; 936 spin_lock_irqsave(&chip->msg_lock, flags); 937 938 for (i = 0; i < channels; i += 4) { 939 u32 s0, s1, s2, s3; 940 941 lx_message_init(&chip->rmh, CMD_12_GET_PEAK); 942 chip->rmh.cmd[0] |= PIPE_INFO_TO_CMD(is_capture, i); 943 944 err = lx_message_send_atomic(chip, &chip->rmh); 945 946 if (err == 0) { 947 s0 = peak_map[chip->rmh.stat[0] & 0x0F]; 948 s1 = peak_map[(chip->rmh.stat[0] >> 4) & 0xf]; 949 s2 = peak_map[(chip->rmh.stat[0] >> 8) & 0xf]; 950 s3 = peak_map[(chip->rmh.stat[0] >> 12) & 0xf]; 951 } else 952 s0 = s1 = s2 = s3 = 0; 953 954 r_levels[0] = s0; 955 r_levels[1] = s1; 956 r_levels[2] = s2; 957 r_levels[3] = s3; 958 959 r_levels += 4; 960 } 961 962 spin_unlock_irqrestore(&chip->msg_lock, flags); 963 return err; 964 } 965 966 /* interrupt handling */ 967 #define PCX_IRQ_NONE 0 968 #define IRQCS_ACTIVE_PCIDB 0x00002000L /* Bit nø 13 */ 969 #define IRQCS_ENABLE_PCIIRQ 0x00000100L /* Bit nø 08 */ 970 #define IRQCS_ENABLE_PCIDB 0x00000200L /* Bit nø 09 */ 971 972 static u32 lx_interrupt_test_ack(struct lx6464es *chip) 973 { 974 u32 irqcs = lx_plx_reg_read(chip, ePLX_IRQCS); 975 976 /* Test if PCI Doorbell interrupt is active */ 977 if (irqcs & IRQCS_ACTIVE_PCIDB) { 978 u32 temp; 979 irqcs = PCX_IRQ_NONE; 980 981 while ((temp = lx_plx_reg_read(chip, ePLX_L2PCIDB))) { 982 /* RAZ interrupt */ 983 irqcs |= temp; 984 lx_plx_reg_write(chip, ePLX_L2PCIDB, temp); 985 } 986 987 return irqcs; 988 } 989 return PCX_IRQ_NONE; 990 } 991 992 static int lx_interrupt_ack(struct lx6464es *chip, u32 *r_irqsrc, 993 int *r_async_pending, int *r_async_escmd) 994 { 995 u32 irq_async; 996 u32 irqsrc = lx_interrupt_test_ack(chip); 997 998 if (irqsrc == PCX_IRQ_NONE) 999 return 0; 1000 1001 *r_irqsrc = irqsrc; 1002 1003 irq_async = irqsrc & MASK_SYS_ASYNC_EVENTS; /* + EtherSound response 1004 * (set by xilinx) + EOB */ 1005 1006 if (irq_async & MASK_SYS_STATUS_ESA) { 1007 irq_async &= ~MASK_SYS_STATUS_ESA; 1008 *r_async_escmd = 1; 1009 } 1010 1011 if (irq_async) { 1012 /* snd_printd("interrupt: async event pending\n"); */ 1013 *r_async_pending = 1; 1014 } 1015 1016 return 1; 1017 } 1018 1019 static int lx_interrupt_handle_async_events(struct lx6464es *chip, u32 irqsrc, 1020 int *r_freq_changed, 1021 u64 *r_notified_in_pipe_mask, 1022 u64 *r_notified_out_pipe_mask) 1023 { 1024 int err; 1025 u32 stat[9]; /* answer from CMD_04_GET_EVENT */ 1026 1027 /* On peut optimiser pour ne pas lire les evenements vides 1028 * les mots de réponse sont dans l'ordre suivant : 1029 * Stat[0] mot de status général 1030 * Stat[1] fin de buffer OUT pF 1031 * Stat[2] fin de buffer OUT pf 1032 * Stat[3] fin de buffer IN pF 1033 * Stat[4] fin de buffer IN pf 1034 * Stat[5] underrun poid fort 1035 * Stat[6] underrun poid faible 1036 * Stat[7] overrun poid fort 1037 * Stat[8] overrun poid faible 1038 * */ 1039 1040 u64 orun_mask; 1041 u64 urun_mask; 1042 #if 0 1043 int has_underrun = (irqsrc & MASK_SYS_STATUS_URUN) ? 1 : 0; 1044 int has_overrun = (irqsrc & MASK_SYS_STATUS_ORUN) ? 1 : 0; 1045 #endif 1046 int eb_pending_out = (irqsrc & MASK_SYS_STATUS_EOBO) ? 1 : 0; 1047 int eb_pending_in = (irqsrc & MASK_SYS_STATUS_EOBI) ? 1 : 0; 1048 1049 *r_freq_changed = (irqsrc & MASK_SYS_STATUS_FREQ) ? 1 : 0; 1050 1051 err = lx_dsp_read_async_events(chip, stat); 1052 if (err < 0) 1053 return err; 1054 1055 if (eb_pending_in) { 1056 *r_notified_in_pipe_mask = ((u64)stat[3] << 32) 1057 + stat[4]; 1058 snd_printdd(LXP "interrupt: EOBI pending %llx\n", 1059 *r_notified_in_pipe_mask); 1060 } 1061 if (eb_pending_out) { 1062 *r_notified_out_pipe_mask = ((u64)stat[1] << 32) 1063 + stat[2]; 1064 snd_printdd(LXP "interrupt: EOBO pending %llx\n", 1065 *r_notified_out_pipe_mask); 1066 } 1067 1068 orun_mask = ((u64)stat[7] << 32) + stat[8]; 1069 urun_mask = ((u64)stat[5] << 32) + stat[6]; 1070 1071 /* todo: handle xrun notification */ 1072 1073 return err; 1074 } 1075 1076 static int lx_interrupt_request_new_buffer(struct lx6464es *chip, 1077 struct lx_stream *lx_stream) 1078 { 1079 struct snd_pcm_substream *substream = lx_stream->stream; 1080 const unsigned int is_capture = lx_stream->is_capture; 1081 int err; 1082 unsigned long flags; 1083 1084 const u32 channels = substream->runtime->channels; 1085 const u32 bytes_per_frame = channels * 3; 1086 const u32 period_size = substream->runtime->period_size; 1087 const u32 period_bytes = period_size * bytes_per_frame; 1088 const u32 pos = lx_stream->frame_pos; 1089 const u32 next_pos = ((pos+1) == substream->runtime->periods) ? 1090 0 : pos + 1; 1091 1092 dma_addr_t buf = substream->dma_buffer.addr + pos * period_bytes; 1093 u32 buf_hi = 0; 1094 u32 buf_lo = 0; 1095 u32 buffer_index = 0; 1096 1097 u32 needed, freed; 1098 u32 size_array[MAX_STREAM_BUFFER]; 1099 1100 snd_printdd("->lx_interrupt_request_new_buffer\n"); 1101 1102 spin_lock_irqsave(&chip->lock, flags); 1103 1104 err = lx_buffer_ask(chip, 0, is_capture, &needed, &freed, size_array); 1105 snd_printdd(LXP "interrupt: needed %d, freed %d\n", needed, freed); 1106 1107 unpack_pointer(buf, &buf_lo, &buf_hi); 1108 err = lx_buffer_give(chip, 0, is_capture, period_bytes, buf_lo, buf_hi, 1109 &buffer_index); 1110 snd_printdd(LXP "interrupt: gave buffer index %x on 0x%lx (%d bytes)\n", 1111 buffer_index, (unsigned long)buf, period_bytes); 1112 1113 lx_stream->frame_pos = next_pos; 1114 spin_unlock_irqrestore(&chip->lock, flags); 1115 1116 return err; 1117 } 1118 1119 void lx_tasklet_playback(unsigned long data) 1120 { 1121 struct lx6464es *chip = (struct lx6464es *)data; 1122 struct lx_stream *lx_stream = &chip->playback_stream; 1123 int err; 1124 1125 snd_printdd("->lx_tasklet_playback\n"); 1126 1127 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1128 if (err < 0) 1129 snd_printk(KERN_ERR LXP 1130 "cannot request new buffer for playback\n"); 1131 1132 snd_pcm_period_elapsed(lx_stream->stream); 1133 } 1134 1135 void lx_tasklet_capture(unsigned long data) 1136 { 1137 struct lx6464es *chip = (struct lx6464es *)data; 1138 struct lx_stream *lx_stream = &chip->capture_stream; 1139 int err; 1140 1141 snd_printdd("->lx_tasklet_capture\n"); 1142 err = lx_interrupt_request_new_buffer(chip, lx_stream); 1143 if (err < 0) 1144 snd_printk(KERN_ERR LXP 1145 "cannot request new buffer for capture\n"); 1146 1147 snd_pcm_period_elapsed(lx_stream->stream); 1148 } 1149 1150 1151 1152 static int lx_interrupt_handle_audio_transfer(struct lx6464es *chip, 1153 u64 notified_in_pipe_mask, 1154 u64 notified_out_pipe_mask) 1155 { 1156 int err = 0; 1157 1158 if (notified_in_pipe_mask) { 1159 snd_printdd(LXP "requesting audio transfer for capture\n"); 1160 tasklet_hi_schedule(&chip->tasklet_capture); 1161 } 1162 1163 if (notified_out_pipe_mask) { 1164 snd_printdd(LXP "requesting audio transfer for playback\n"); 1165 tasklet_hi_schedule(&chip->tasklet_playback); 1166 } 1167 1168 return err; 1169 } 1170 1171 1172 irqreturn_t lx_interrupt(int irq, void *dev_id) 1173 { 1174 struct lx6464es *chip = dev_id; 1175 int async_pending, async_escmd; 1176 u32 irqsrc; 1177 1178 spin_lock(&chip->lock); 1179 1180 snd_printdd("**************************************************\n"); 1181 1182 if (!lx_interrupt_ack(chip, &irqsrc, &async_pending, &async_escmd)) { 1183 spin_unlock(&chip->lock); 1184 snd_printdd("IRQ_NONE\n"); 1185 return IRQ_NONE; /* this device did not cause the interrupt */ 1186 } 1187 1188 if (irqsrc & MASK_SYS_STATUS_CMD_DONE) 1189 goto exit; 1190 1191 #if 0 1192 if (irqsrc & MASK_SYS_STATUS_EOBI) 1193 snd_printdd(LXP "interrupt: EOBI\n"); 1194 1195 if (irqsrc & MASK_SYS_STATUS_EOBO) 1196 snd_printdd(LXP "interrupt: EOBO\n"); 1197 1198 if (irqsrc & MASK_SYS_STATUS_URUN) 1199 snd_printdd(LXP "interrupt: URUN\n"); 1200 1201 if (irqsrc & MASK_SYS_STATUS_ORUN) 1202 snd_printdd(LXP "interrupt: ORUN\n"); 1203 #endif 1204 1205 if (async_pending) { 1206 u64 notified_in_pipe_mask = 0; 1207 u64 notified_out_pipe_mask = 0; 1208 int freq_changed; 1209 int err; 1210 1211 /* handle async events */ 1212 err = lx_interrupt_handle_async_events(chip, irqsrc, 1213 &freq_changed, 1214 ¬ified_in_pipe_mask, 1215 ¬ified_out_pipe_mask); 1216 if (err) 1217 snd_printk(KERN_ERR LXP 1218 "error handling async events\n"); 1219 1220 err = lx_interrupt_handle_audio_transfer(chip, 1221 notified_in_pipe_mask, 1222 notified_out_pipe_mask 1223 ); 1224 if (err) 1225 snd_printk(KERN_ERR LXP 1226 "error during audio transfer\n"); 1227 } 1228 1229 if (async_escmd) { 1230 #if 0 1231 /* backdoor for ethersound commands 1232 * 1233 * for now, we do not need this 1234 * 1235 * */ 1236 1237 snd_printdd("lx6464es: interrupt requests escmd handling\n"); 1238 #endif 1239 } 1240 1241 exit: 1242 spin_unlock(&chip->lock); 1243 return IRQ_HANDLED; /* this device caused the interrupt */ 1244 } 1245 1246 1247 static void lx_irq_set(struct lx6464es *chip, int enable) 1248 { 1249 u32 reg = lx_plx_reg_read(chip, ePLX_IRQCS); 1250 1251 /* enable/disable interrupts 1252 * 1253 * Set the Doorbell and PCI interrupt enable bits 1254 * 1255 * */ 1256 if (enable) 1257 reg |= (IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1258 else 1259 reg &= ~(IRQCS_ENABLE_PCIIRQ | IRQCS_ENABLE_PCIDB); 1260 lx_plx_reg_write(chip, ePLX_IRQCS, reg); 1261 } 1262 1263 void lx_irq_enable(struct lx6464es *chip) 1264 { 1265 snd_printdd("->lx_irq_enable\n"); 1266 lx_irq_set(chip, 1); 1267 } 1268 1269 void lx_irq_disable(struct lx6464es *chip) 1270 { 1271 snd_printdd("->lx_irq_disable\n"); 1272 lx_irq_set(chip, 0); 1273 } 1274