xref: /openbmc/linux/sound/pci/intel8x0m.c (revision f42b3800)
1 /*
2  *   ALSA modem driver for Intel ICH (i8x0) chipsets
3  *
4  *	Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz>
5  *
6  *   This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version
7  *   of ALSA ICH sound driver intel8x0.c .
8  *
9  *
10  *   This program is free software; you can redistribute it and/or modify
11  *   it under the terms of the GNU General Public License as published by
12  *   the Free Software Foundation; either version 2 of the License, or
13  *   (at your option) any later version.
14  *
15  *   This program is distributed in the hope that it will be useful,
16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  *   GNU General Public License for more details.
19  *
20  *   You should have received a copy of the GNU General Public License
21  *   along with this program; if not, write to the Free Software
22  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
23  *
24  */
25 
26 #include <asm/io.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/moduleparam.h>
33 #include <sound/core.h>
34 #include <sound/pcm.h>
35 #include <sound/ac97_codec.h>
36 #include <sound/info.h>
37 #include <sound/initval.h>
38 
39 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
40 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; "
41 		   "SiS 7013; NVidia MCP/2/2S/3 modems");
42 MODULE_LICENSE("GPL");
43 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH},"
44 		"{Intel,82901AB-ICH0},"
45 		"{Intel,82801BA-ICH2},"
46 		"{Intel,82801CA-ICH3},"
47 		"{Intel,82801DB-ICH4},"
48 		"{Intel,ICH5},"
49 		"{Intel,ICH6},"
50 		"{Intel,ICH7},"
51 	        "{Intel,MX440},"
52 		"{SiS,7013},"
53 		"{NVidia,NForce Modem},"
54 		"{NVidia,NForce2 Modem},"
55 		"{NVidia,NForce2s Modem},"
56 		"{NVidia,NForce3 Modem},"
57 		"{AMD,AMD768}}");
58 
59 static int index = -2; /* Exclude the first card */
60 static char *id = SNDRV_DEFAULT_STR1;	/* ID for this card */
61 static int ac97_clock;
62 
63 module_param(index, int, 0444);
64 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard.");
65 module_param(id, charp, 0444);
66 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard.");
67 module_param(ac97_clock, int, 0444);
68 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect).");
69 
70 /* just for backward compatibility */
71 static int enable;
72 module_param(enable, bool, 0444);
73 
74 /*
75  *  Direct registers
76  */
77 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE };
78 
79 #define ICHREG(x) ICH_REG_##x
80 
81 #define DEFINE_REGSET(name,base) \
82 enum { \
83 	ICH_REG_##name##_BDBAR	= base + 0x0,	/* dword - buffer descriptor list base address */ \
84 	ICH_REG_##name##_CIV	= base + 0x04,	/* byte - current index value */ \
85 	ICH_REG_##name##_LVI	= base + 0x05,	/* byte - last valid index */ \
86 	ICH_REG_##name##_SR	= base + 0x06,	/* byte - status register */ \
87 	ICH_REG_##name##_PICB	= base + 0x08,	/* word - position in current buffer */ \
88 	ICH_REG_##name##_PIV	= base + 0x0a,	/* byte - prefetched index value */ \
89 	ICH_REG_##name##_CR	= base + 0x0b,	/* byte - control register */ \
90 };
91 
92 /* busmaster blocks */
93 DEFINE_REGSET(OFF, 0);		/* offset */
94 
95 /* values for each busmaster block */
96 
97 /* LVI */
98 #define ICH_REG_LVI_MASK		0x1f
99 
100 /* SR */
101 #define ICH_FIFOE			0x10	/* FIFO error */
102 #define ICH_BCIS			0x08	/* buffer completion interrupt status */
103 #define ICH_LVBCI			0x04	/* last valid buffer completion interrupt */
104 #define ICH_CELV			0x02	/* current equals last valid */
105 #define ICH_DCH				0x01	/* DMA controller halted */
106 
107 /* PIV */
108 #define ICH_REG_PIV_MASK		0x1f	/* mask */
109 
110 /* CR */
111 #define ICH_IOCE			0x10	/* interrupt on completion enable */
112 #define ICH_FEIE			0x08	/* fifo error interrupt enable */
113 #define ICH_LVBIE			0x04	/* last valid buffer interrupt enable */
114 #define ICH_RESETREGS			0x02	/* reset busmaster registers */
115 #define ICH_STARTBM			0x01	/* start busmaster operation */
116 
117 
118 /* global block */
119 #define ICH_REG_GLOB_CNT		0x3c	/* dword - global control */
120 #define   ICH_TRIE		0x00000040	/* tertiary resume interrupt enable */
121 #define   ICH_SRIE		0x00000020	/* secondary resume interrupt enable */
122 #define   ICH_PRIE		0x00000010	/* primary resume interrupt enable */
123 #define   ICH_ACLINK		0x00000008	/* AClink shut off */
124 #define   ICH_AC97WARM		0x00000004	/* AC'97 warm reset */
125 #define   ICH_AC97COLD		0x00000002	/* AC'97 cold reset */
126 #define   ICH_GIE		0x00000001	/* GPI interrupt enable */
127 #define ICH_REG_GLOB_STA		0x40	/* dword - global status */
128 #define   ICH_TRI		0x20000000	/* ICH4: tertiary (AC_SDIN2) resume interrupt */
129 #define   ICH_TCR		0x10000000	/* ICH4: tertiary (AC_SDIN2) codec ready */
130 #define   ICH_BCS		0x08000000	/* ICH4: bit clock stopped */
131 #define   ICH_SPINT		0x04000000	/* ICH4: S/PDIF interrupt */
132 #define   ICH_P2INT		0x02000000	/* ICH4: PCM2-In interrupt */
133 #define   ICH_M2INT		0x01000000	/* ICH4: Mic2-In interrupt */
134 #define   ICH_SAMPLE_CAP	0x00c00000	/* ICH4: sample capability bits (RO) */
135 #define   ICH_MULTICHAN_CAP	0x00300000	/* ICH4: multi-channel capability bits (RO) */
136 #define   ICH_MD3		0x00020000	/* modem power down semaphore */
137 #define   ICH_AD3		0x00010000	/* audio power down semaphore */
138 #define   ICH_RCS		0x00008000	/* read completion status */
139 #define   ICH_BIT3		0x00004000	/* bit 3 slot 12 */
140 #define   ICH_BIT2		0x00002000	/* bit 2 slot 12 */
141 #define   ICH_BIT1		0x00001000	/* bit 1 slot 12 */
142 #define   ICH_SRI		0x00000800	/* secondary (AC_SDIN1) resume interrupt */
143 #define   ICH_PRI		0x00000400	/* primary (AC_SDIN0) resume interrupt */
144 #define   ICH_SCR		0x00000200	/* secondary (AC_SDIN1) codec ready */
145 #define   ICH_PCR		0x00000100	/* primary (AC_SDIN0) codec ready */
146 #define   ICH_MCINT		0x00000080	/* MIC capture interrupt */
147 #define   ICH_POINT		0x00000040	/* playback interrupt */
148 #define   ICH_PIINT		0x00000020	/* capture interrupt */
149 #define   ICH_NVSPINT		0x00000010	/* nforce spdif interrupt */
150 #define   ICH_MOINT		0x00000004	/* modem playback interrupt */
151 #define   ICH_MIINT		0x00000002	/* modem capture interrupt */
152 #define   ICH_GSCI		0x00000001	/* GPI status change interrupt */
153 #define ICH_REG_ACC_SEMA		0x44	/* byte - codec write semaphore */
154 #define   ICH_CAS		0x01		/* codec access semaphore */
155 
156 #define ICH_MAX_FRAGS		32		/* max hw frags */
157 
158 
159 /*
160  *
161  */
162 
163 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT };
164 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT };
165 
166 #define get_ichdev(substream) (substream->runtime->private_data)
167 
168 struct ichdev {
169 	unsigned int ichd;			/* ich device number */
170 	unsigned long reg_offset;		/* offset to bmaddr */
171 	u32 *bdbar;				/* CPU address (32bit) */
172 	unsigned int bdbar_addr;		/* PCI bus address (32bit) */
173 	struct snd_pcm_substream *substream;
174 	unsigned int physbuf;			/* physical address (32bit) */
175         unsigned int size;
176         unsigned int fragsize;
177         unsigned int fragsize1;
178         unsigned int position;
179         int frags;
180         int lvi;
181         int lvi_frag;
182 	int civ;
183 	int ack;
184 	int ack_reload;
185 	unsigned int ack_bit;
186 	unsigned int roff_sr;
187 	unsigned int roff_picb;
188 	unsigned int int_sta_mask;		/* interrupt status mask */
189 	unsigned int ali_slot;			/* ALI DMA slot */
190 	struct snd_ac97 *ac97;
191 };
192 
193 struct intel8x0m {
194 	unsigned int device_type;
195 
196 	int irq;
197 
198 	void __iomem *addr;
199 	void __iomem *bmaddr;
200 
201 	struct pci_dev *pci;
202 	struct snd_card *card;
203 
204 	int pcm_devs;
205 	struct snd_pcm *pcm[2];
206 	struct ichdev ichd[2];
207 
208 	unsigned int in_ac97_init: 1;
209 
210 	struct snd_ac97_bus *ac97_bus;
211 	struct snd_ac97 *ac97;
212 
213 	spinlock_t reg_lock;
214 
215 	struct snd_dma_buffer bdbars;
216 	u32 bdbars_count;
217 	u32 int_sta_reg;		/* interrupt status register */
218 	u32 int_sta_mask;		/* interrupt status mask */
219 	unsigned int pcm_pos_shift;
220 };
221 
222 static struct pci_device_id snd_intel8x0m_ids[] = {
223 	{ 0x8086, 0x2416, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* 82801AA */
224 	{ 0x8086, 0x2426, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* 82901AB */
225 	{ 0x8086, 0x2446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* 82801BA */
226 	{ 0x8086, 0x2486, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* ICH3 */
227 	{ 0x8086, 0x24c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH4 */
228 	{ 0x8086, 0x24d6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH5 */
229 	{ 0x8086, 0x266d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* ICH6 */
230 	{ 0x8086, 0x27dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* ICH7 */
231 	{ 0x8086, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* 440MX */
232 	{ 0x1022, 0x7446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* AMD768 */
233 	{ 0x1039, 0x7013, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS },	/* SI7013 */
234 	{ 0x10de, 0x01c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */
235 	{ 0x10de, 0x0069, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */
236 	{ 0x10de, 0x0089, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2s */
237 	{ 0x10de, 0x00d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */
238 #if 0
239 	{ 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL },	/* AMD8111 */
240 	{ 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI },   /* Ali5455 */
241 #endif
242 	{ 0, }
243 };
244 
245 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids);
246 
247 /*
248  *  Lowlevel I/O - busmaster
249  */
250 
251 static inline u8 igetbyte(struct intel8x0m *chip, u32 offset)
252 {
253 	return ioread8(chip->bmaddr + offset);
254 }
255 
256 static inline u16 igetword(struct intel8x0m *chip, u32 offset)
257 {
258 	return ioread16(chip->bmaddr + offset);
259 }
260 
261 static inline u32 igetdword(struct intel8x0m *chip, u32 offset)
262 {
263 	return ioread32(chip->bmaddr + offset);
264 }
265 
266 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val)
267 {
268 	iowrite8(val, chip->bmaddr + offset);
269 }
270 
271 static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val)
272 {
273 	iowrite16(val, chip->bmaddr + offset);
274 }
275 
276 static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val)
277 {
278 	iowrite32(val, chip->bmaddr + offset);
279 }
280 
281 /*
282  *  Lowlevel I/O - AC'97 registers
283  */
284 
285 static inline u16 iagetword(struct intel8x0m *chip, u32 offset)
286 {
287 	return ioread16(chip->addr + offset);
288 }
289 
290 static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val)
291 {
292 	iowrite16(val, chip->addr + offset);
293 }
294 
295 /*
296  *  Basic I/O
297  */
298 
299 /*
300  * access to AC97 codec via normal i/o (for ICH and SIS7013)
301  */
302 
303 /* return the GLOB_STA bit for the corresponding codec */
304 static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec)
305 {
306 	static unsigned int codec_bit[3] = {
307 		ICH_PCR, ICH_SCR, ICH_TCR
308 	};
309 	snd_assert(codec < 3, return ICH_PCR);
310 	return codec_bit[codec];
311 }
312 
313 static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec)
314 {
315 	int time;
316 
317 	if (codec > 1)
318 		return -EIO;
319 	codec = get_ich_codec_bit(chip, codec);
320 
321 	/* codec ready ? */
322 	if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0)
323 		return -EIO;
324 
325 	/* Anyone holding a semaphore for 1 msec should be shot... */
326 	time = 100;
327       	do {
328       		if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS))
329       			return 0;
330 		udelay(10);
331 	} while (time--);
332 
333 	/* access to some forbidden (non existant) ac97 registers will not
334 	 * reset the semaphore. So even if you don't get the semaphore, still
335 	 * continue the access. We don't need the semaphore anyway. */
336 	snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n",
337 			igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA)));
338 	iagetword(chip, 0);	/* clear semaphore flag */
339 	/* I don't care about the semaphore */
340 	return -EBUSY;
341 }
342 
343 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97,
344 				     unsigned short reg,
345 				     unsigned short val)
346 {
347 	struct intel8x0m *chip = ac97->private_data;
348 
349 	if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
350 		if (! chip->in_ac97_init)
351 			snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
352 	}
353 	iaputword(chip, reg + ac97->num * 0x80, val);
354 }
355 
356 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97,
357 					      unsigned short reg)
358 {
359 	struct intel8x0m *chip = ac97->private_data;
360 	unsigned short res;
361 	unsigned int tmp;
362 
363 	if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) {
364 		if (! chip->in_ac97_init)
365 			snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg);
366 		res = 0xffff;
367 	} else {
368 		res = iagetword(chip, reg + ac97->num * 0x80);
369 		if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) {
370 			/* reset RCS and preserve other R/WC bits */
371 			iputdword(chip, ICHREG(GLOB_STA),
372 				  tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI));
373 			if (! chip->in_ac97_init)
374 				snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg);
375 			res = 0xffff;
376 		}
377 	}
378 	if (reg == AC97_GPIO_STATUS)
379 		iagetword(chip, 0); /* clear semaphore */
380 	return res;
381 }
382 
383 
384 /*
385  * DMA I/O
386  */
387 static void snd_intel8x0_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev)
388 {
389 	int idx;
390 	u32 *bdbar = ichdev->bdbar;
391 	unsigned long port = ichdev->reg_offset;
392 
393 	iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr);
394 	if (ichdev->size == ichdev->fragsize) {
395 		ichdev->ack_reload = ichdev->ack = 2;
396 		ichdev->fragsize1 = ichdev->fragsize >> 1;
397 		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) {
398 			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf);
399 			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
400 						     ichdev->fragsize1 >> chip->pcm_pos_shift);
401 			bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1));
402 			bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */
403 						     ichdev->fragsize1 >> chip->pcm_pos_shift);
404 		}
405 		ichdev->frags = 2;
406 	} else {
407 		ichdev->ack_reload = ichdev->ack = 1;
408 		ichdev->fragsize1 = ichdev->fragsize;
409 		for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) {
410 			bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size));
411 			bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */
412 						     ichdev->fragsize >> chip->pcm_pos_shift);
413 			// printk("bdbar[%i] = 0x%x [0x%x]\n", idx + 0, bdbar[idx + 0], bdbar[idx + 1]);
414 		}
415 		ichdev->frags = ichdev->size / ichdev->fragsize;
416 	}
417 	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK);
418 	ichdev->civ = 0;
419 	iputbyte(chip, port + ICH_REG_OFF_CIV, 0);
420 	ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags;
421 	ichdev->position = 0;
422 #if 0
423 	printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n",
424 			ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1);
425 #endif
426 	/* clear interrupts */
427 	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
428 }
429 
430 /*
431  *  Interrupt handler
432  */
433 
434 static inline void snd_intel8x0_update(struct intel8x0m *chip, struct ichdev *ichdev)
435 {
436 	unsigned long port = ichdev->reg_offset;
437 	int civ, i, step;
438 	int ack = 0;
439 
440 	civ = igetbyte(chip, port + ICH_REG_OFF_CIV);
441 	if (civ == ichdev->civ) {
442 		// snd_printd("civ same %d\n", civ);
443 		step = 1;
444 		ichdev->civ++;
445 		ichdev->civ &= ICH_REG_LVI_MASK;
446 	} else {
447 		step = civ - ichdev->civ;
448 		if (step < 0)
449 			step += ICH_REG_LVI_MASK + 1;
450 		// if (step != 1)
451 		//	snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ);
452 		ichdev->civ = civ;
453 	}
454 
455 	ichdev->position += step * ichdev->fragsize1;
456 	ichdev->position %= ichdev->size;
457 	ichdev->lvi += step;
458 	ichdev->lvi &= ICH_REG_LVI_MASK;
459 	iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi);
460 	for (i = 0; i < step; i++) {
461 		ichdev->lvi_frag++;
462 		ichdev->lvi_frag %= ichdev->frags;
463 		ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf +
464 							     ichdev->lvi_frag *
465 							     ichdev->fragsize1);
466 #if 0
467 		printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n",
468 		       ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2],
469 		       ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port),
470 		       inl(port + 4), inb(port + ICH_REG_OFF_CR));
471 #endif
472 		if (--ichdev->ack == 0) {
473 			ichdev->ack = ichdev->ack_reload;
474 			ack = 1;
475 		}
476 	}
477 	if (ack && ichdev->substream) {
478 		spin_unlock(&chip->reg_lock);
479 		snd_pcm_period_elapsed(ichdev->substream);
480 		spin_lock(&chip->reg_lock);
481 	}
482 	iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI);
483 }
484 
485 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id)
486 {
487 	struct intel8x0m *chip = dev_id;
488 	struct ichdev *ichdev;
489 	unsigned int status;
490 	unsigned int i;
491 
492 	spin_lock(&chip->reg_lock);
493 	status = igetdword(chip, chip->int_sta_reg);
494 	if (status == 0xffffffff) { /* we are not yet resumed */
495 		spin_unlock(&chip->reg_lock);
496 		return IRQ_NONE;
497 	}
498 	if ((status & chip->int_sta_mask) == 0) {
499 		if (status)
500 			iputdword(chip, chip->int_sta_reg, status);
501 		spin_unlock(&chip->reg_lock);
502 		return IRQ_NONE;
503 	}
504 
505 	for (i = 0; i < chip->bdbars_count; i++) {
506 		ichdev = &chip->ichd[i];
507 		if (status & ichdev->int_sta_mask)
508 			snd_intel8x0_update(chip, ichdev);
509 	}
510 
511 	/* ack them */
512 	iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask);
513 	spin_unlock(&chip->reg_lock);
514 
515 	return IRQ_HANDLED;
516 }
517 
518 /*
519  *  PCM part
520  */
521 
522 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
523 {
524 	struct intel8x0m *chip = snd_pcm_substream_chip(substream);
525 	struct ichdev *ichdev = get_ichdev(substream);
526 	unsigned char val = 0;
527 	unsigned long port = ichdev->reg_offset;
528 
529 	switch (cmd) {
530 	case SNDRV_PCM_TRIGGER_START:
531 	case SNDRV_PCM_TRIGGER_RESUME:
532 		val = ICH_IOCE | ICH_STARTBM;
533 		break;
534 	case SNDRV_PCM_TRIGGER_STOP:
535 	case SNDRV_PCM_TRIGGER_SUSPEND:
536 		val = 0;
537 		break;
538 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
539 		val = ICH_IOCE;
540 		break;
541 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
542 		val = ICH_IOCE | ICH_STARTBM;
543 		break;
544 	default:
545 		return -EINVAL;
546 	}
547 	iputbyte(chip, port + ICH_REG_OFF_CR, val);
548 	if (cmd == SNDRV_PCM_TRIGGER_STOP) {
549 		/* wait until DMA stopped */
550 		while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ;
551 		/* reset whole DMA things */
552 		iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS);
553 	}
554 	return 0;
555 }
556 
557 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream,
558 				  struct snd_pcm_hw_params *hw_params)
559 {
560 	return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
561 }
562 
563 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream)
564 {
565 	return snd_pcm_lib_free_pages(substream);
566 }
567 
568 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream)
569 {
570 	struct intel8x0m *chip = snd_pcm_substream_chip(substream);
571 	struct ichdev *ichdev = get_ichdev(substream);
572 	size_t ptr1, ptr;
573 
574 	ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift;
575 	if (ptr1 != 0)
576 		ptr = ichdev->fragsize1 - ptr1;
577 	else
578 		ptr = 0;
579 	ptr += ichdev->position;
580 	if (ptr >= ichdev->size)
581 		return 0;
582 	return bytes_to_frames(substream->runtime, ptr);
583 }
584 
585 static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream)
586 {
587 	struct intel8x0m *chip = snd_pcm_substream_chip(substream);
588 	struct snd_pcm_runtime *runtime = substream->runtime;
589 	struct ichdev *ichdev = get_ichdev(substream);
590 
591 	ichdev->physbuf = runtime->dma_addr;
592 	ichdev->size = snd_pcm_lib_buffer_bytes(substream);
593 	ichdev->fragsize = snd_pcm_lib_period_bytes(substream);
594 	snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate);
595 	snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0);
596 	snd_intel8x0_setup_periods(chip, ichdev);
597 	return 0;
598 }
599 
600 static struct snd_pcm_hardware snd_intel8x0m_stream =
601 {
602 	.info =			(SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
603 				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
604 				 SNDRV_PCM_INFO_MMAP_VALID |
605 				 SNDRV_PCM_INFO_PAUSE |
606 				 SNDRV_PCM_INFO_RESUME),
607 	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
608 	.rates =		SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
609 	.rate_min =		8000,
610 	.rate_max =		16000,
611 	.channels_min =		1,
612 	.channels_max =		1,
613 	.buffer_bytes_max =	64 * 1024,
614 	.period_bytes_min =	32,
615 	.period_bytes_max =	64 * 1024,
616 	.periods_min =		1,
617 	.periods_max =		1024,
618 	.fifo_size =		0,
619 };
620 
621 
622 static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev)
623 {
624 	static unsigned int rates[] = { 8000,  9600, 12000, 16000 };
625 	static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
626 		.count = ARRAY_SIZE(rates),
627 		.list = rates,
628 		.mask = 0,
629 	};
630 	struct snd_pcm_runtime *runtime = substream->runtime;
631 	int err;
632 
633 	ichdev->substream = substream;
634 	runtime->hw = snd_intel8x0m_stream;
635 	err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
636 					 &hw_constraints_rates);
637 	if ( err < 0 )
638 		return err;
639 	runtime->private_data = ichdev;
640 	return 0;
641 }
642 
643 static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream)
644 {
645 	struct intel8x0m *chip = snd_pcm_substream_chip(substream);
646 
647 	return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]);
648 }
649 
650 static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream)
651 {
652 	struct intel8x0m *chip = snd_pcm_substream_chip(substream);
653 
654 	chip->ichd[ICHD_MDMOUT].substream = NULL;
655 	return 0;
656 }
657 
658 static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream)
659 {
660 	struct intel8x0m *chip = snd_pcm_substream_chip(substream);
661 
662 	return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]);
663 }
664 
665 static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream)
666 {
667 	struct intel8x0m *chip = snd_pcm_substream_chip(substream);
668 
669 	chip->ichd[ICHD_MDMIN].substream = NULL;
670 	return 0;
671 }
672 
673 
674 static struct snd_pcm_ops snd_intel8x0m_playback_ops = {
675 	.open =		snd_intel8x0m_playback_open,
676 	.close =	snd_intel8x0m_playback_close,
677 	.ioctl =	snd_pcm_lib_ioctl,
678 	.hw_params =	snd_intel8x0_hw_params,
679 	.hw_free =	snd_intel8x0_hw_free,
680 	.prepare =	snd_intel8x0m_pcm_prepare,
681 	.trigger =	snd_intel8x0_pcm_trigger,
682 	.pointer =	snd_intel8x0_pcm_pointer,
683 };
684 
685 static struct snd_pcm_ops snd_intel8x0m_capture_ops = {
686 	.open =		snd_intel8x0m_capture_open,
687 	.close =	snd_intel8x0m_capture_close,
688 	.ioctl =	snd_pcm_lib_ioctl,
689 	.hw_params =	snd_intel8x0_hw_params,
690 	.hw_free =	snd_intel8x0_hw_free,
691 	.prepare =	snd_intel8x0m_pcm_prepare,
692 	.trigger =	snd_intel8x0_pcm_trigger,
693 	.pointer =	snd_intel8x0_pcm_pointer,
694 };
695 
696 
697 struct ich_pcm_table {
698 	char *suffix;
699 	struct snd_pcm_ops *playback_ops;
700 	struct snd_pcm_ops *capture_ops;
701 	size_t prealloc_size;
702 	size_t prealloc_max_size;
703 	int ac97_idx;
704 };
705 
706 static int __devinit snd_intel8x0_pcm1(struct intel8x0m *chip, int device,
707 				       struct ich_pcm_table *rec)
708 {
709 	struct snd_pcm *pcm;
710 	int err;
711 	char name[32];
712 
713 	if (rec->suffix)
714 		sprintf(name, "Intel ICH - %s", rec->suffix);
715 	else
716 		strcpy(name, "Intel ICH");
717 	err = snd_pcm_new(chip->card, name, device,
718 			  rec->playback_ops ? 1 : 0,
719 			  rec->capture_ops ? 1 : 0, &pcm);
720 	if (err < 0)
721 		return err;
722 
723 	if (rec->playback_ops)
724 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops);
725 	if (rec->capture_ops)
726 		snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops);
727 
728 	pcm->private_data = chip;
729 	pcm->info_flags = 0;
730 	pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
731 	if (rec->suffix)
732 		sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix);
733 	else
734 		strcpy(pcm->name, chip->card->shortname);
735 	chip->pcm[device] = pcm;
736 
737 	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
738 					      snd_dma_pci_data(chip->pci),
739 					      rec->prealloc_size,
740 					      rec->prealloc_max_size);
741 
742 	return 0;
743 }
744 
745 static struct ich_pcm_table intel_pcms[] __devinitdata = {
746 	{
747 		.suffix = "Modem",
748 		.playback_ops = &snd_intel8x0m_playback_ops,
749 		.capture_ops = &snd_intel8x0m_capture_ops,
750 		.prealloc_size = 32 * 1024,
751 		.prealloc_max_size = 64 * 1024,
752 	},
753 };
754 
755 static int __devinit snd_intel8x0_pcm(struct intel8x0m *chip)
756 {
757 	int i, tblsize, device, err;
758 	struct ich_pcm_table *tbl, *rec;
759 
760 #if 1
761 	tbl = intel_pcms;
762 	tblsize = 1;
763 #else
764 	switch (chip->device_type) {
765 	case DEVICE_NFORCE:
766 		tbl = nforce_pcms;
767 		tblsize = ARRAY_SIZE(nforce_pcms);
768 		break;
769 	case DEVICE_ALI:
770 		tbl = ali_pcms;
771 		tblsize = ARRAY_SIZE(ali_pcms);
772 		break;
773 	default:
774 		tbl = intel_pcms;
775 		tblsize = 2;
776 		break;
777 	}
778 #endif
779 	device = 0;
780 	for (i = 0; i < tblsize; i++) {
781 		rec = tbl + i;
782 		if (i > 0 && rec->ac97_idx) {
783 			/* activate PCM only when associated AC'97 codec */
784 			if (! chip->ichd[rec->ac97_idx].ac97)
785 				continue;
786 		}
787 		err = snd_intel8x0_pcm1(chip, device, rec);
788 		if (err < 0)
789 			return err;
790 		device++;
791 	}
792 
793 	chip->pcm_devs = device;
794 	return 0;
795 }
796 
797 
798 /*
799  *  Mixer part
800  */
801 
802 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
803 {
804 	struct intel8x0m *chip = bus->private_data;
805 	chip->ac97_bus = NULL;
806 }
807 
808 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97)
809 {
810 	struct intel8x0m *chip = ac97->private_data;
811 	chip->ac97 = NULL;
812 }
813 
814 
815 static int __devinit snd_intel8x0_mixer(struct intel8x0m *chip, int ac97_clock)
816 {
817 	struct snd_ac97_bus *pbus;
818 	struct snd_ac97_template ac97;
819 	struct snd_ac97 *x97;
820 	int err;
821 	unsigned int glob_sta = 0;
822 	static struct snd_ac97_bus_ops ops = {
823 		.write = snd_intel8x0_codec_write,
824 		.read = snd_intel8x0_codec_read,
825 	};
826 
827 	chip->in_ac97_init = 1;
828 
829 	memset(&ac97, 0, sizeof(ac97));
830 	ac97.private_data = chip;
831 	ac97.private_free = snd_intel8x0_mixer_free_ac97;
832 	ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE;
833 
834 	glob_sta = igetdword(chip, ICHREG(GLOB_STA));
835 
836 	if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
837 		goto __err;
838 	pbus->private_free = snd_intel8x0_mixer_free_ac97_bus;
839 	if (ac97_clock >= 8000 && ac97_clock <= 48000)
840 		pbus->clock = ac97_clock;
841 	chip->ac97_bus = pbus;
842 
843 	ac97.pci = chip->pci;
844 	ac97.num = glob_sta & ICH_SCR ? 1 : 0;
845 	if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) {
846 		snd_printk(KERN_ERR "Unable to initialize codec #%d\n", ac97.num);
847 		if (ac97.num == 0)
848 			goto __err;
849 		return err;
850 	}
851 	chip->ac97 = x97;
852 	if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) {
853 		chip->ichd[ICHD_MDMIN].ac97 = x97;
854 		chip->ichd[ICHD_MDMOUT].ac97 = x97;
855 	}
856 
857 	chip->in_ac97_init = 0;
858 	return 0;
859 
860  __err:
861 	/* clear the cold-reset bit for the next chance */
862 	if (chip->device_type != DEVICE_ALI)
863 		iputdword(chip, ICHREG(GLOB_CNT),
864 			  igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD);
865 	return err;
866 }
867 
868 
869 /*
870  *
871  */
872 
873 static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing)
874 {
875 	unsigned long end_time;
876 	unsigned int cnt, status, nstatus;
877 
878 	/* put logic to right state */
879 	/* first clear status bits */
880 	status = ICH_RCS | ICH_MIINT | ICH_MOINT;
881 	cnt = igetdword(chip, ICHREG(GLOB_STA));
882 	iputdword(chip, ICHREG(GLOB_STA), cnt & status);
883 
884 	/* ACLink on, 2 channels */
885 	cnt = igetdword(chip, ICHREG(GLOB_CNT));
886 	cnt &= ~(ICH_ACLINK);
887 	/* finish cold or do warm reset */
888 	cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM;
889 	iputdword(chip, ICHREG(GLOB_CNT), cnt);
890 	end_time = (jiffies + (HZ / 4)) + 1;
891 	do {
892 		if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0)
893 			goto __ok;
894 		schedule_timeout_uninterruptible(1);
895 	} while (time_after_eq(end_time, jiffies));
896 	snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n",
897 		   igetdword(chip, ICHREG(GLOB_CNT)));
898 	return -EIO;
899 
900       __ok:
901 	if (probing) {
902 		/* wait for any codec ready status.
903 		 * Once it becomes ready it should remain ready
904 		 * as long as we do not disable the ac97 link.
905 		 */
906 		end_time = jiffies + HZ;
907 		do {
908 			status = igetdword(chip, ICHREG(GLOB_STA)) &
909 				(ICH_PCR | ICH_SCR | ICH_TCR);
910 			if (status)
911 				break;
912 			schedule_timeout_uninterruptible(1);
913 		} while (time_after_eq(end_time, jiffies));
914 		if (! status) {
915 			/* no codec is found */
916 			snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n",
917 				   igetdword(chip, ICHREG(GLOB_STA)));
918 			return -EIO;
919 		}
920 
921 		/* up to two codecs (modem cannot be tertiary with ICH4) */
922 		nstatus = ICH_PCR | ICH_SCR;
923 
924 		/* wait for other codecs ready status. */
925 		end_time = jiffies + HZ / 4;
926 		while (status != nstatus && time_after_eq(end_time, jiffies)) {
927 			schedule_timeout_uninterruptible(1);
928 			status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus;
929 		}
930 
931 	} else {
932 		/* resume phase */
933 		status = 0;
934 		if (chip->ac97)
935 			status |= get_ich_codec_bit(chip, chip->ac97->num);
936 		/* wait until all the probed codecs are ready */
937 		end_time = jiffies + HZ;
938 		do {
939 			nstatus = igetdword(chip, ICHREG(GLOB_STA)) &
940 				(ICH_PCR | ICH_SCR | ICH_TCR);
941 			if (status == nstatus)
942 				break;
943 			schedule_timeout_uninterruptible(1);
944 		} while (time_after_eq(end_time, jiffies));
945 	}
946 
947 	if (chip->device_type == DEVICE_SIS) {
948 		/* unmute the output on SIS7012 */
949 		iputword(chip, 0x4c, igetword(chip, 0x4c) | 1);
950 	}
951 
952       	return 0;
953 }
954 
955 static int snd_intel8x0_chip_init(struct intel8x0m *chip, int probing)
956 {
957 	unsigned int i;
958 	int err;
959 
960 	if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0)
961 		return err;
962 	iagetword(chip, 0);	/* clear semaphore flag */
963 
964 	/* disable interrupts */
965 	for (i = 0; i < chip->bdbars_count; i++)
966 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
967 	/* reset channels */
968 	for (i = 0; i < chip->bdbars_count; i++)
969 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
970 	/* initialize Buffer Descriptor Lists */
971 	for (i = 0; i < chip->bdbars_count; i++)
972 		iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr);
973 	return 0;
974 }
975 
976 static int snd_intel8x0_free(struct intel8x0m *chip)
977 {
978 	unsigned int i;
979 
980 	if (chip->irq < 0)
981 		goto __hw_end;
982 	/* disable interrupts */
983 	for (i = 0; i < chip->bdbars_count; i++)
984 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00);
985 	/* reset channels */
986 	for (i = 0; i < chip->bdbars_count; i++)
987 		iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS);
988 	/* --- */
989 	synchronize_irq(chip->irq);
990       __hw_end:
991 	if (chip->bdbars.area)
992 		snd_dma_free_pages(&chip->bdbars);
993 	if (chip->addr)
994 		pci_iounmap(chip->pci, chip->addr);
995 	if (chip->bmaddr)
996 		pci_iounmap(chip->pci, chip->bmaddr);
997 	if (chip->irq >= 0)
998 		free_irq(chip->irq, chip);
999 	pci_release_regions(chip->pci);
1000 	pci_disable_device(chip->pci);
1001 	kfree(chip);
1002 	return 0;
1003 }
1004 
1005 #ifdef CONFIG_PM
1006 /*
1007  * power management
1008  */
1009 static int intel8x0m_suspend(struct pci_dev *pci, pm_message_t state)
1010 {
1011 	struct snd_card *card = pci_get_drvdata(pci);
1012 	struct intel8x0m *chip = card->private_data;
1013 	int i;
1014 
1015 	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1016 	for (i = 0; i < chip->pcm_devs; i++)
1017 		snd_pcm_suspend_all(chip->pcm[i]);
1018 	snd_ac97_suspend(chip->ac97);
1019 	if (chip->irq >= 0) {
1020 		synchronize_irq(chip->irq);
1021 		free_irq(chip->irq, chip);
1022 		chip->irq = -1;
1023 	}
1024 	pci_disable_device(pci);
1025 	pci_save_state(pci);
1026 	pci_set_power_state(pci, pci_choose_state(pci, state));
1027 	return 0;
1028 }
1029 
1030 static int intel8x0m_resume(struct pci_dev *pci)
1031 {
1032 	struct snd_card *card = pci_get_drvdata(pci);
1033 	struct intel8x0m *chip = card->private_data;
1034 
1035 	pci_set_power_state(pci, PCI_D0);
1036 	pci_restore_state(pci);
1037 	if (pci_enable_device(pci) < 0) {
1038 		printk(KERN_ERR "intel8x0m: pci_enable_device failed, "
1039 		       "disabling device\n");
1040 		snd_card_disconnect(card);
1041 		return -EIO;
1042 	}
1043 	pci_set_master(pci);
1044 	if (request_irq(pci->irq, snd_intel8x0_interrupt,
1045 			IRQF_SHARED, card->shortname, chip)) {
1046 		printk(KERN_ERR "intel8x0m: unable to grab IRQ %d, "
1047 		       "disabling device\n", pci->irq);
1048 		snd_card_disconnect(card);
1049 		return -EIO;
1050 	}
1051 	chip->irq = pci->irq;
1052 	snd_intel8x0_chip_init(chip, 0);
1053 	snd_ac97_resume(chip->ac97);
1054 
1055 	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1056 	return 0;
1057 }
1058 #endif /* CONFIG_PM */
1059 
1060 #ifdef CONFIG_PROC_FS
1061 static void snd_intel8x0m_proc_read(struct snd_info_entry * entry,
1062 				   struct snd_info_buffer *buffer)
1063 {
1064 	struct intel8x0m *chip = entry->private_data;
1065 	unsigned int tmp;
1066 
1067 	snd_iprintf(buffer, "Intel8x0m\n\n");
1068 	if (chip->device_type == DEVICE_ALI)
1069 		return;
1070 	tmp = igetdword(chip, ICHREG(GLOB_STA));
1071 	snd_iprintf(buffer, "Global control        : 0x%08x\n",
1072 		    igetdword(chip, ICHREG(GLOB_CNT)));
1073 	snd_iprintf(buffer, "Global status         : 0x%08x\n", tmp);
1074 	snd_iprintf(buffer, "AC'97 codecs ready    :%s%s%s%s\n",
1075 			tmp & ICH_PCR ? " primary" : "",
1076 			tmp & ICH_SCR ? " secondary" : "",
1077 			tmp & ICH_TCR ? " tertiary" : "",
1078 			(tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : "");
1079 }
1080 
1081 static void __devinit snd_intel8x0m_proc_init(struct intel8x0m * chip)
1082 {
1083 	struct snd_info_entry *entry;
1084 
1085 	if (! snd_card_proc_new(chip->card, "intel8x0m", &entry))
1086 		snd_info_set_text_ops(entry, chip, snd_intel8x0m_proc_read);
1087 }
1088 #else /* !CONFIG_PROC_FS */
1089 #define snd_intel8x0m_proc_init(chip)
1090 #endif /* CONFIG_PROC_FS */
1091 
1092 
1093 static int snd_intel8x0_dev_free(struct snd_device *device)
1094 {
1095 	struct intel8x0m *chip = device->device_data;
1096 	return snd_intel8x0_free(chip);
1097 }
1098 
1099 struct ich_reg_info {
1100 	unsigned int int_sta_mask;
1101 	unsigned int offset;
1102 };
1103 
1104 static int __devinit snd_intel8x0m_create(struct snd_card *card,
1105 					 struct pci_dev *pci,
1106 					 unsigned long device_type,
1107 					 struct intel8x0m ** r_intel8x0)
1108 {
1109 	struct intel8x0m *chip;
1110 	int err;
1111 	unsigned int i;
1112 	unsigned int int_sta_masks;
1113 	struct ichdev *ichdev;
1114 	static struct snd_device_ops ops = {
1115 		.dev_free =	snd_intel8x0_dev_free,
1116 	};
1117 	static struct ich_reg_info intel_regs[2] = {
1118 		{ ICH_MIINT, 0 },
1119 		{ ICH_MOINT, 0x10 },
1120 	};
1121 	struct ich_reg_info *tbl;
1122 
1123 	*r_intel8x0 = NULL;
1124 
1125 	if ((err = pci_enable_device(pci)) < 0)
1126 		return err;
1127 
1128 	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1129 	if (chip == NULL) {
1130 		pci_disable_device(pci);
1131 		return -ENOMEM;
1132 	}
1133 	spin_lock_init(&chip->reg_lock);
1134 	chip->device_type = device_type;
1135 	chip->card = card;
1136 	chip->pci = pci;
1137 	chip->irq = -1;
1138 
1139 	if ((err = pci_request_regions(pci, card->shortname)) < 0) {
1140 		kfree(chip);
1141 		pci_disable_device(pci);
1142 		return err;
1143 	}
1144 
1145 	if (device_type == DEVICE_ALI) {
1146 		/* ALI5455 has no ac97 region */
1147 		chip->bmaddr = pci_iomap(pci, 0, 0);
1148 		goto port_inited;
1149 	}
1150 
1151 	if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */
1152 		chip->addr = pci_iomap(pci, 2, 0);
1153 	else
1154 		chip->addr = pci_iomap(pci, 0, 0);
1155 	if (!chip->addr) {
1156 		snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1157 		snd_intel8x0_free(chip);
1158 		return -EIO;
1159 	}
1160 	if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */
1161 		chip->bmaddr = pci_iomap(pci, 3, 0);
1162 	else
1163 		chip->bmaddr = pci_iomap(pci, 1, 0);
1164 	if (!chip->bmaddr) {
1165 		snd_printk(KERN_ERR "Controller space ioremap problem\n");
1166 		snd_intel8x0_free(chip);
1167 		return -EIO;
1168 	}
1169 
1170  port_inited:
1171 	if (request_irq(pci->irq, snd_intel8x0_interrupt, IRQF_SHARED,
1172 			card->shortname, chip)) {
1173 		snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1174 		snd_intel8x0_free(chip);
1175 		return -EBUSY;
1176 	}
1177 	chip->irq = pci->irq;
1178 	pci_set_master(pci);
1179 	synchronize_irq(chip->irq);
1180 
1181 	/* initialize offsets */
1182 	chip->bdbars_count = 2;
1183 	tbl = intel_regs;
1184 
1185 	for (i = 0; i < chip->bdbars_count; i++) {
1186 		ichdev = &chip->ichd[i];
1187 		ichdev->ichd = i;
1188 		ichdev->reg_offset = tbl[i].offset;
1189 		ichdev->int_sta_mask = tbl[i].int_sta_mask;
1190 		if (device_type == DEVICE_SIS) {
1191 			/* SiS 7013 swaps the registers */
1192 			ichdev->roff_sr = ICH_REG_OFF_PICB;
1193 			ichdev->roff_picb = ICH_REG_OFF_SR;
1194 		} else {
1195 			ichdev->roff_sr = ICH_REG_OFF_SR;
1196 			ichdev->roff_picb = ICH_REG_OFF_PICB;
1197 		}
1198 		if (device_type == DEVICE_ALI)
1199 			ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10;
1200 	}
1201 	/* SIS7013 handles the pcm data in bytes, others are in words */
1202 	chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1;
1203 
1204 	/* allocate buffer descriptor lists */
1205 	/* the start of each lists must be aligned to 8 bytes */
1206 	if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1207 				chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2,
1208 				&chip->bdbars) < 0) {
1209 		snd_intel8x0_free(chip);
1210 		return -ENOMEM;
1211 	}
1212 	/* tables must be aligned to 8 bytes here, but the kernel pages
1213 	   are much bigger, so we don't care (on i386) */
1214 	int_sta_masks = 0;
1215 	for (i = 0; i < chip->bdbars_count; i++) {
1216 		ichdev = &chip->ichd[i];
1217 		ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2);
1218 		ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2);
1219 		int_sta_masks |= ichdev->int_sta_mask;
1220 	}
1221 	chip->int_sta_reg = ICH_REG_GLOB_STA;
1222 	chip->int_sta_mask = int_sta_masks;
1223 
1224 	if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) {
1225 		snd_intel8x0_free(chip);
1226 		return err;
1227 	}
1228 
1229 	if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1230 		snd_intel8x0_free(chip);
1231 		return err;
1232 	}
1233 
1234 	snd_card_set_dev(card, &pci->dev);
1235 
1236 	*r_intel8x0 = chip;
1237 	return 0;
1238 }
1239 
1240 static struct shortname_table {
1241 	unsigned int id;
1242 	const char *s;
1243 } shortnames[] __devinitdata = {
1244 	{ PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" },
1245 	{ PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" },
1246 	{ PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" },
1247 	{ PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" },
1248 	{ PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" },
1249 	{ PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" },
1250 	{ PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" },
1251 	{ PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" },
1252 	{ PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" },
1253 	{ 0x7446, "AMD AMD768" },
1254 	{ PCI_DEVICE_ID_SI_7013, "SiS SI7013" },
1255 	{ PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" },
1256 	{ PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" },
1257 	{ PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" },
1258 	{ PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" },
1259 #if 0
1260 	{ 0x5455, "ALi M5455" },
1261 	{ 0x746d, "AMD AMD8111" },
1262 #endif
1263 	{ 0 },
1264 };
1265 
1266 static int __devinit snd_intel8x0m_probe(struct pci_dev *pci,
1267 					const struct pci_device_id *pci_id)
1268 {
1269 	struct snd_card *card;
1270 	struct intel8x0m *chip;
1271 	int err;
1272 	struct shortname_table *name;
1273 
1274 	card = snd_card_new(index, id, THIS_MODULE, 0);
1275 	if (card == NULL)
1276 		return -ENOMEM;
1277 
1278 	strcpy(card->driver, "ICH-MODEM");
1279 	strcpy(card->shortname, "Intel ICH");
1280 	for (name = shortnames; name->id; name++) {
1281 		if (pci->device == name->id) {
1282 			strcpy(card->shortname, name->s);
1283 			break;
1284 		}
1285 	}
1286 	strcat(card->shortname," Modem");
1287 
1288 	if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) {
1289 		snd_card_free(card);
1290 		return err;
1291 	}
1292 	card->private_data = chip;
1293 
1294 	if ((err = snd_intel8x0_mixer(chip, ac97_clock)) < 0) {
1295 		snd_card_free(card);
1296 		return err;
1297 	}
1298 	if ((err = snd_intel8x0_pcm(chip)) < 0) {
1299 		snd_card_free(card);
1300 		return err;
1301 	}
1302 
1303 	snd_intel8x0m_proc_init(chip);
1304 
1305 	sprintf(card->longname, "%s at irq %i",
1306 		card->shortname, chip->irq);
1307 
1308 	if ((err = snd_card_register(card)) < 0) {
1309 		snd_card_free(card);
1310 		return err;
1311 	}
1312 	pci_set_drvdata(pci, card);
1313 	return 0;
1314 }
1315 
1316 static void __devexit snd_intel8x0m_remove(struct pci_dev *pci)
1317 {
1318 	snd_card_free(pci_get_drvdata(pci));
1319 	pci_set_drvdata(pci, NULL);
1320 }
1321 
1322 static struct pci_driver driver = {
1323 	.name = "Intel ICH Modem",
1324 	.id_table = snd_intel8x0m_ids,
1325 	.probe = snd_intel8x0m_probe,
1326 	.remove = __devexit_p(snd_intel8x0m_remove),
1327 #ifdef CONFIG_PM
1328 	.suspend = intel8x0m_suspend,
1329 	.resume = intel8x0m_resume,
1330 #endif
1331 };
1332 
1333 
1334 static int __init alsa_card_intel8x0m_init(void)
1335 {
1336 	return pci_register_driver(&driver);
1337 }
1338 
1339 static void __exit alsa_card_intel8x0m_exit(void)
1340 {
1341 	pci_unregister_driver(&driver);
1342 }
1343 
1344 module_init(alsa_card_intel8x0m_init)
1345 module_exit(alsa_card_intel8x0m_exit)
1346