1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA modem driver for Intel ICH (i8x0) chipsets 4 * 5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 6 * 7 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version 8 * of ALSA ICH sound driver intel8x0.c . 9 */ 10 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/slab.h> 17 #include <linux/module.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/ac97_codec.h> 21 #include <sound/info.h> 22 #include <sound/initval.h> 23 24 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 25 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; " 26 "SiS 7013; NVidia MCP/2/2S/3 modems"); 27 MODULE_LICENSE("GPL"); 28 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 29 "{Intel,82901AB-ICH0}," 30 "{Intel,82801BA-ICH2}," 31 "{Intel,82801CA-ICH3}," 32 "{Intel,82801DB-ICH4}," 33 "{Intel,ICH5}," 34 "{Intel,ICH6}," 35 "{Intel,ICH7}," 36 "{Intel,MX440}," 37 "{SiS,7013}," 38 "{NVidia,NForce Modem}," 39 "{NVidia,NForce2 Modem}," 40 "{NVidia,NForce2s Modem}," 41 "{NVidia,NForce3 Modem}," 42 "{AMD,AMD768}}"); 43 44 static int index = -2; /* Exclude the first card */ 45 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 46 static int ac97_clock; 47 48 module_param(index, int, 0444); 49 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); 50 module_param(id, charp, 0444); 51 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); 52 module_param(ac97_clock, int, 0444); 53 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 54 55 /* just for backward compatibility */ 56 static bool enable; 57 module_param(enable, bool, 0444); 58 59 /* 60 * Direct registers 61 */ 62 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 63 64 #define ICHREG(x) ICH_REG_##x 65 66 #define DEFINE_REGSET(name,base) \ 67 enum { \ 68 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 69 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 70 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 71 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 72 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 73 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 74 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 75 }; 76 77 /* busmaster blocks */ 78 DEFINE_REGSET(OFF, 0); /* offset */ 79 80 /* values for each busmaster block */ 81 82 /* LVI */ 83 #define ICH_REG_LVI_MASK 0x1f 84 85 /* SR */ 86 #define ICH_FIFOE 0x10 /* FIFO error */ 87 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 88 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 89 #define ICH_CELV 0x02 /* current equals last valid */ 90 #define ICH_DCH 0x01 /* DMA controller halted */ 91 92 /* PIV */ 93 #define ICH_REG_PIV_MASK 0x1f /* mask */ 94 95 /* CR */ 96 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 97 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 98 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 99 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 100 #define ICH_STARTBM 0x01 /* start busmaster operation */ 101 102 103 /* global block */ 104 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ 105 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 106 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 107 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 108 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 109 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 110 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 111 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 112 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */ 113 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 114 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 115 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 116 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 117 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 118 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 119 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 120 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 121 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 122 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 123 #define ICH_RCS 0x00008000 /* read completion status */ 124 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 125 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 126 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 127 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 128 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 129 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 130 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 131 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 132 #define ICH_POINT 0x00000040 /* playback interrupt */ 133 #define ICH_PIINT 0x00000020 /* capture interrupt */ 134 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 135 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 136 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 137 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 138 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ 139 #define ICH_CAS 0x01 /* codec access semaphore */ 140 141 #define ICH_MAX_FRAGS 32 /* max hw frags */ 142 143 144 /* 145 * 146 */ 147 148 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; 149 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; 150 151 #define get_ichdev(substream) (substream->runtime->private_data) 152 153 struct ichdev { 154 unsigned int ichd; /* ich device number */ 155 unsigned long reg_offset; /* offset to bmaddr */ 156 __le32 *bdbar; /* CPU address (32bit) */ 157 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 158 struct snd_pcm_substream *substream; 159 unsigned int physbuf; /* physical address (32bit) */ 160 unsigned int size; 161 unsigned int fragsize; 162 unsigned int fragsize1; 163 unsigned int position; 164 int frags; 165 int lvi; 166 int lvi_frag; 167 int civ; 168 int ack; 169 int ack_reload; 170 unsigned int ack_bit; 171 unsigned int roff_sr; 172 unsigned int roff_picb; 173 unsigned int int_sta_mask; /* interrupt status mask */ 174 unsigned int ali_slot; /* ALI DMA slot */ 175 struct snd_ac97 *ac97; 176 }; 177 178 struct intel8x0m { 179 unsigned int device_type; 180 181 int irq; 182 183 void __iomem *addr; 184 void __iomem *bmaddr; 185 186 struct pci_dev *pci; 187 struct snd_card *card; 188 189 int pcm_devs; 190 struct snd_pcm *pcm[2]; 191 struct ichdev ichd[2]; 192 193 unsigned int in_ac97_init: 1; 194 195 struct snd_ac97_bus *ac97_bus; 196 struct snd_ac97 *ac97; 197 198 spinlock_t reg_lock; 199 200 struct snd_dma_buffer bdbars; 201 u32 bdbars_count; 202 u32 int_sta_reg; /* interrupt status register */ 203 u32 int_sta_mask; /* interrupt status mask */ 204 unsigned int pcm_pos_shift; 205 }; 206 207 static const struct pci_device_id snd_intel8x0m_ids[] = { 208 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */ 209 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */ 210 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */ 211 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */ 212 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */ 213 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */ 214 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */ 215 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */ 216 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */ 217 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */ 218 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */ 219 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */ 220 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */ 221 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */ 222 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */ 223 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */ 224 #if 0 225 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 226 #endif 227 { 0, } 228 }; 229 230 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); 231 232 /* 233 * Lowlevel I/O - busmaster 234 */ 235 236 static inline u8 igetbyte(struct intel8x0m *chip, u32 offset) 237 { 238 return ioread8(chip->bmaddr + offset); 239 } 240 241 static inline u16 igetword(struct intel8x0m *chip, u32 offset) 242 { 243 return ioread16(chip->bmaddr + offset); 244 } 245 246 static inline u32 igetdword(struct intel8x0m *chip, u32 offset) 247 { 248 return ioread32(chip->bmaddr + offset); 249 } 250 251 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val) 252 { 253 iowrite8(val, chip->bmaddr + offset); 254 } 255 256 static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val) 257 { 258 iowrite16(val, chip->bmaddr + offset); 259 } 260 261 static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val) 262 { 263 iowrite32(val, chip->bmaddr + offset); 264 } 265 266 /* 267 * Lowlevel I/O - AC'97 registers 268 */ 269 270 static inline u16 iagetword(struct intel8x0m *chip, u32 offset) 271 { 272 return ioread16(chip->addr + offset); 273 } 274 275 static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val) 276 { 277 iowrite16(val, chip->addr + offset); 278 } 279 280 /* 281 * Basic I/O 282 */ 283 284 /* 285 * access to AC97 codec via normal i/o (for ICH and SIS7013) 286 */ 287 288 /* return the GLOB_STA bit for the corresponding codec */ 289 static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec) 290 { 291 static unsigned int codec_bit[3] = { 292 ICH_PCR, ICH_SCR, ICH_TCR 293 }; 294 if (snd_BUG_ON(codec >= 3)) 295 return ICH_PCR; 296 return codec_bit[codec]; 297 } 298 299 static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec) 300 { 301 int time; 302 303 if (codec > 1) 304 return -EIO; 305 codec = get_ich_codec_bit(chip, codec); 306 307 /* codec ready ? */ 308 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 309 return -EIO; 310 311 /* Anyone holding a semaphore for 1 msec should be shot... */ 312 time = 100; 313 do { 314 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 315 return 0; 316 udelay(10); 317 } while (time--); 318 319 /* access to some forbidden (non existent) ac97 registers will not 320 * reset the semaphore. So even if you don't get the semaphore, still 321 * continue the access. We don't need the semaphore anyway. */ 322 dev_err(chip->card->dev, 323 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 324 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 325 iagetword(chip, 0); /* clear semaphore flag */ 326 /* I don't care about the semaphore */ 327 return -EBUSY; 328 } 329 330 static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97, 331 unsigned short reg, 332 unsigned short val) 333 { 334 struct intel8x0m *chip = ac97->private_data; 335 336 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 337 if (! chip->in_ac97_init) 338 dev_err(chip->card->dev, 339 "codec_write %d: semaphore is not ready for register 0x%x\n", 340 ac97->num, reg); 341 } 342 iaputword(chip, reg + ac97->num * 0x80, val); 343 } 344 345 static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97, 346 unsigned short reg) 347 { 348 struct intel8x0m *chip = ac97->private_data; 349 unsigned short res; 350 unsigned int tmp; 351 352 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 353 if (! chip->in_ac97_init) 354 dev_err(chip->card->dev, 355 "codec_read %d: semaphore is not ready for register 0x%x\n", 356 ac97->num, reg); 357 res = 0xffff; 358 } else { 359 res = iagetword(chip, reg + ac97->num * 0x80); 360 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 361 /* reset RCS and preserve other R/WC bits */ 362 iputdword(chip, ICHREG(GLOB_STA), 363 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 364 if (! chip->in_ac97_init) 365 dev_err(chip->card->dev, 366 "codec_read %d: read timeout for register 0x%x\n", 367 ac97->num, reg); 368 res = 0xffff; 369 } 370 } 371 if (reg == AC97_GPIO_STATUS) 372 iagetword(chip, 0); /* clear semaphore */ 373 return res; 374 } 375 376 377 /* 378 * DMA I/O 379 */ 380 static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev) 381 { 382 int idx; 383 __le32 *bdbar = ichdev->bdbar; 384 unsigned long port = ichdev->reg_offset; 385 386 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 387 if (ichdev->size == ichdev->fragsize) { 388 ichdev->ack_reload = ichdev->ack = 2; 389 ichdev->fragsize1 = ichdev->fragsize >> 1; 390 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 391 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 392 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 393 ichdev->fragsize1 >> chip->pcm_pos_shift); 394 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 395 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 396 ichdev->fragsize1 >> chip->pcm_pos_shift); 397 } 398 ichdev->frags = 2; 399 } else { 400 ichdev->ack_reload = ichdev->ack = 1; 401 ichdev->fragsize1 = ichdev->fragsize; 402 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 403 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 404 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 405 ichdev->fragsize >> chip->pcm_pos_shift); 406 /* 407 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", 408 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 409 */ 410 } 411 ichdev->frags = ichdev->size / ichdev->fragsize; 412 } 413 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 414 ichdev->civ = 0; 415 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 416 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 417 ichdev->position = 0; 418 #if 0 419 dev_dbg(chip->card->dev, 420 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 421 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, 422 ichdev->fragsize1); 423 #endif 424 /* clear interrupts */ 425 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 426 } 427 428 /* 429 * Interrupt handler 430 */ 431 432 static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev) 433 { 434 unsigned long port = ichdev->reg_offset; 435 int civ, i, step; 436 int ack = 0; 437 438 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 439 if (civ == ichdev->civ) { 440 // snd_printd("civ same %d\n", civ); 441 step = 1; 442 ichdev->civ++; 443 ichdev->civ &= ICH_REG_LVI_MASK; 444 } else { 445 step = civ - ichdev->civ; 446 if (step < 0) 447 step += ICH_REG_LVI_MASK + 1; 448 // if (step != 1) 449 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 450 ichdev->civ = civ; 451 } 452 453 ichdev->position += step * ichdev->fragsize1; 454 ichdev->position %= ichdev->size; 455 ichdev->lvi += step; 456 ichdev->lvi &= ICH_REG_LVI_MASK; 457 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 458 for (i = 0; i < step; i++) { 459 ichdev->lvi_frag++; 460 ichdev->lvi_frag %= ichdev->frags; 461 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + 462 ichdev->lvi_frag * 463 ichdev->fragsize1); 464 #if 0 465 dev_dbg(chip->card->dev, 466 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 467 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 468 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 469 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 470 #endif 471 if (--ichdev->ack == 0) { 472 ichdev->ack = ichdev->ack_reload; 473 ack = 1; 474 } 475 } 476 if (ack && ichdev->substream) { 477 spin_unlock(&chip->reg_lock); 478 snd_pcm_period_elapsed(ichdev->substream); 479 spin_lock(&chip->reg_lock); 480 } 481 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 482 } 483 484 static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id) 485 { 486 struct intel8x0m *chip = dev_id; 487 struct ichdev *ichdev; 488 unsigned int status; 489 unsigned int i; 490 491 spin_lock(&chip->reg_lock); 492 status = igetdword(chip, chip->int_sta_reg); 493 if (status == 0xffffffff) { /* we are not yet resumed */ 494 spin_unlock(&chip->reg_lock); 495 return IRQ_NONE; 496 } 497 if ((status & chip->int_sta_mask) == 0) { 498 if (status) 499 iputdword(chip, chip->int_sta_reg, status); 500 spin_unlock(&chip->reg_lock); 501 return IRQ_NONE; 502 } 503 504 for (i = 0; i < chip->bdbars_count; i++) { 505 ichdev = &chip->ichd[i]; 506 if (status & ichdev->int_sta_mask) 507 snd_intel8x0m_update(chip, ichdev); 508 } 509 510 /* ack them */ 511 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 512 spin_unlock(&chip->reg_lock); 513 514 return IRQ_HANDLED; 515 } 516 517 /* 518 * PCM part 519 */ 520 521 static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 522 { 523 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 524 struct ichdev *ichdev = get_ichdev(substream); 525 unsigned char val = 0; 526 unsigned long port = ichdev->reg_offset; 527 528 switch (cmd) { 529 case SNDRV_PCM_TRIGGER_START: 530 case SNDRV_PCM_TRIGGER_RESUME: 531 val = ICH_IOCE | ICH_STARTBM; 532 break; 533 case SNDRV_PCM_TRIGGER_STOP: 534 case SNDRV_PCM_TRIGGER_SUSPEND: 535 val = 0; 536 break; 537 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 538 val = ICH_IOCE; 539 break; 540 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 541 val = ICH_IOCE | ICH_STARTBM; 542 break; 543 default: 544 return -EINVAL; 545 } 546 iputbyte(chip, port + ICH_REG_OFF_CR, val); 547 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 548 /* wait until DMA stopped */ 549 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 550 /* reset whole DMA things */ 551 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 552 } 553 return 0; 554 } 555 556 static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream) 557 { 558 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 559 struct ichdev *ichdev = get_ichdev(substream); 560 size_t ptr1, ptr; 561 562 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; 563 if (ptr1 != 0) 564 ptr = ichdev->fragsize1 - ptr1; 565 else 566 ptr = 0; 567 ptr += ichdev->position; 568 if (ptr >= ichdev->size) 569 return 0; 570 return bytes_to_frames(substream->runtime, ptr); 571 } 572 573 static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream) 574 { 575 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 576 struct snd_pcm_runtime *runtime = substream->runtime; 577 struct ichdev *ichdev = get_ichdev(substream); 578 579 ichdev->physbuf = runtime->dma_addr; 580 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 581 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 582 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); 583 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); 584 snd_intel8x0m_setup_periods(chip, ichdev); 585 return 0; 586 } 587 588 static const struct snd_pcm_hardware snd_intel8x0m_stream = 589 { 590 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 591 SNDRV_PCM_INFO_BLOCK_TRANSFER | 592 SNDRV_PCM_INFO_MMAP_VALID | 593 SNDRV_PCM_INFO_PAUSE | 594 SNDRV_PCM_INFO_RESUME), 595 .formats = SNDRV_PCM_FMTBIT_S16_LE, 596 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, 597 .rate_min = 8000, 598 .rate_max = 16000, 599 .channels_min = 1, 600 .channels_max = 1, 601 .buffer_bytes_max = 64 * 1024, 602 .period_bytes_min = 32, 603 .period_bytes_max = 64 * 1024, 604 .periods_min = 1, 605 .periods_max = 1024, 606 .fifo_size = 0, 607 }; 608 609 610 static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 611 { 612 static const unsigned int rates[] = { 8000, 9600, 12000, 16000 }; 613 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { 614 .count = ARRAY_SIZE(rates), 615 .list = rates, 616 .mask = 0, 617 }; 618 struct snd_pcm_runtime *runtime = substream->runtime; 619 int err; 620 621 ichdev->substream = substream; 622 runtime->hw = snd_intel8x0m_stream; 623 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 624 &hw_constraints_rates); 625 if ( err < 0 ) 626 return err; 627 runtime->private_data = ichdev; 628 return 0; 629 } 630 631 static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream) 632 { 633 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 634 635 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); 636 } 637 638 static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream) 639 { 640 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 641 642 chip->ichd[ICHD_MDMOUT].substream = NULL; 643 return 0; 644 } 645 646 static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream) 647 { 648 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 649 650 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); 651 } 652 653 static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream) 654 { 655 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 656 657 chip->ichd[ICHD_MDMIN].substream = NULL; 658 return 0; 659 } 660 661 662 static const struct snd_pcm_ops snd_intel8x0m_playback_ops = { 663 .open = snd_intel8x0m_playback_open, 664 .close = snd_intel8x0m_playback_close, 665 .ioctl = snd_pcm_lib_ioctl, 666 .prepare = snd_intel8x0m_pcm_prepare, 667 .trigger = snd_intel8x0m_pcm_trigger, 668 .pointer = snd_intel8x0m_pcm_pointer, 669 }; 670 671 static const struct snd_pcm_ops snd_intel8x0m_capture_ops = { 672 .open = snd_intel8x0m_capture_open, 673 .close = snd_intel8x0m_capture_close, 674 .ioctl = snd_pcm_lib_ioctl, 675 .prepare = snd_intel8x0m_pcm_prepare, 676 .trigger = snd_intel8x0m_pcm_trigger, 677 .pointer = snd_intel8x0m_pcm_pointer, 678 }; 679 680 681 struct ich_pcm_table { 682 char *suffix; 683 const struct snd_pcm_ops *playback_ops; 684 const struct snd_pcm_ops *capture_ops; 685 size_t prealloc_size; 686 size_t prealloc_max_size; 687 int ac97_idx; 688 }; 689 690 static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device, 691 struct ich_pcm_table *rec) 692 { 693 struct snd_pcm *pcm; 694 int err; 695 char name[32]; 696 697 if (rec->suffix) 698 sprintf(name, "Intel ICH - %s", rec->suffix); 699 else 700 strcpy(name, "Intel ICH"); 701 err = snd_pcm_new(chip->card, name, device, 702 rec->playback_ops ? 1 : 0, 703 rec->capture_ops ? 1 : 0, &pcm); 704 if (err < 0) 705 return err; 706 707 if (rec->playback_ops) 708 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 709 if (rec->capture_ops) 710 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 711 712 pcm->private_data = chip; 713 pcm->info_flags = 0; 714 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 715 if (rec->suffix) 716 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 717 else 718 strcpy(pcm->name, chip->card->shortname); 719 chip->pcm[device] = pcm; 720 721 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 722 &chip->pci->dev, 723 rec->prealloc_size, 724 rec->prealloc_max_size); 725 726 return 0; 727 } 728 729 static struct ich_pcm_table intel_pcms[] = { 730 { 731 .suffix = "Modem", 732 .playback_ops = &snd_intel8x0m_playback_ops, 733 .capture_ops = &snd_intel8x0m_capture_ops, 734 .prealloc_size = 32 * 1024, 735 .prealloc_max_size = 64 * 1024, 736 }, 737 }; 738 739 static int snd_intel8x0m_pcm(struct intel8x0m *chip) 740 { 741 int i, tblsize, device, err; 742 struct ich_pcm_table *tbl, *rec; 743 744 #if 1 745 tbl = intel_pcms; 746 tblsize = 1; 747 #else 748 switch (chip->device_type) { 749 case DEVICE_NFORCE: 750 tbl = nforce_pcms; 751 tblsize = ARRAY_SIZE(nforce_pcms); 752 break; 753 case DEVICE_ALI: 754 tbl = ali_pcms; 755 tblsize = ARRAY_SIZE(ali_pcms); 756 break; 757 default: 758 tbl = intel_pcms; 759 tblsize = 2; 760 break; 761 } 762 #endif 763 device = 0; 764 for (i = 0; i < tblsize; i++) { 765 rec = tbl + i; 766 if (i > 0 && rec->ac97_idx) { 767 /* activate PCM only when associated AC'97 codec */ 768 if (! chip->ichd[rec->ac97_idx].ac97) 769 continue; 770 } 771 err = snd_intel8x0m_pcm1(chip, device, rec); 772 if (err < 0) 773 return err; 774 device++; 775 } 776 777 chip->pcm_devs = device; 778 return 0; 779 } 780 781 782 /* 783 * Mixer part 784 */ 785 786 static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 787 { 788 struct intel8x0m *chip = bus->private_data; 789 chip->ac97_bus = NULL; 790 } 791 792 static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97) 793 { 794 struct intel8x0m *chip = ac97->private_data; 795 chip->ac97 = NULL; 796 } 797 798 799 static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock) 800 { 801 struct snd_ac97_bus *pbus; 802 struct snd_ac97_template ac97; 803 struct snd_ac97 *x97; 804 int err; 805 unsigned int glob_sta = 0; 806 static struct snd_ac97_bus_ops ops = { 807 .write = snd_intel8x0m_codec_write, 808 .read = snd_intel8x0m_codec_read, 809 }; 810 811 chip->in_ac97_init = 1; 812 813 memset(&ac97, 0, sizeof(ac97)); 814 ac97.private_data = chip; 815 ac97.private_free = snd_intel8x0m_mixer_free_ac97; 816 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE; 817 818 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 819 820 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 821 goto __err; 822 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus; 823 if (ac97_clock >= 8000 && ac97_clock <= 48000) 824 pbus->clock = ac97_clock; 825 chip->ac97_bus = pbus; 826 827 ac97.pci = chip->pci; 828 ac97.num = glob_sta & ICH_SCR ? 1 : 0; 829 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) { 830 dev_err(chip->card->dev, 831 "Unable to initialize codec #%d\n", ac97.num); 832 if (ac97.num == 0) 833 goto __err; 834 return err; 835 } 836 chip->ac97 = x97; 837 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { 838 chip->ichd[ICHD_MDMIN].ac97 = x97; 839 chip->ichd[ICHD_MDMOUT].ac97 = x97; 840 } 841 842 chip->in_ac97_init = 0; 843 return 0; 844 845 __err: 846 /* clear the cold-reset bit for the next chance */ 847 if (chip->device_type != DEVICE_ALI) 848 iputdword(chip, ICHREG(GLOB_CNT), 849 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 850 return err; 851 } 852 853 854 /* 855 * 856 */ 857 858 static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing) 859 { 860 unsigned long end_time; 861 unsigned int cnt, status, nstatus; 862 863 /* put logic to right state */ 864 /* first clear status bits */ 865 status = ICH_RCS | ICH_MIINT | ICH_MOINT; 866 cnt = igetdword(chip, ICHREG(GLOB_STA)); 867 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 868 869 /* ACLink on, 2 channels */ 870 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 871 cnt &= ~(ICH_ACLINK); 872 /* finish cold or do warm reset */ 873 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 874 iputdword(chip, ICHREG(GLOB_CNT), cnt); 875 usleep_range(500, 1000); /* give warm reset some time */ 876 end_time = jiffies + HZ / 4; 877 do { 878 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 879 goto __ok; 880 schedule_timeout_uninterruptible(1); 881 } while (time_after_eq(end_time, jiffies)); 882 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", 883 igetdword(chip, ICHREG(GLOB_CNT))); 884 return -EIO; 885 886 __ok: 887 if (probing) { 888 /* wait for any codec ready status. 889 * Once it becomes ready it should remain ready 890 * as long as we do not disable the ac97 link. 891 */ 892 end_time = jiffies + HZ; 893 do { 894 status = igetdword(chip, ICHREG(GLOB_STA)) & 895 (ICH_PCR | ICH_SCR | ICH_TCR); 896 if (status) 897 break; 898 schedule_timeout_uninterruptible(1); 899 } while (time_after_eq(end_time, jiffies)); 900 if (! status) { 901 /* no codec is found */ 902 dev_err(chip->card->dev, 903 "codec_ready: codec is not ready [0x%x]\n", 904 igetdword(chip, ICHREG(GLOB_STA))); 905 return -EIO; 906 } 907 908 /* up to two codecs (modem cannot be tertiary with ICH4) */ 909 nstatus = ICH_PCR | ICH_SCR; 910 911 /* wait for other codecs ready status. */ 912 end_time = jiffies + HZ / 4; 913 while (status != nstatus && time_after_eq(end_time, jiffies)) { 914 schedule_timeout_uninterruptible(1); 915 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 916 } 917 918 } else { 919 /* resume phase */ 920 status = 0; 921 if (chip->ac97) 922 status |= get_ich_codec_bit(chip, chip->ac97->num); 923 /* wait until all the probed codecs are ready */ 924 end_time = jiffies + HZ; 925 do { 926 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 927 (ICH_PCR | ICH_SCR | ICH_TCR); 928 if (status == nstatus) 929 break; 930 schedule_timeout_uninterruptible(1); 931 } while (time_after_eq(end_time, jiffies)); 932 } 933 934 if (chip->device_type == DEVICE_SIS) { 935 /* unmute the output on SIS7012 */ 936 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 937 } 938 939 return 0; 940 } 941 942 static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing) 943 { 944 unsigned int i; 945 int err; 946 947 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0) 948 return err; 949 iagetword(chip, 0); /* clear semaphore flag */ 950 951 /* disable interrupts */ 952 for (i = 0; i < chip->bdbars_count; i++) 953 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 954 /* reset channels */ 955 for (i = 0; i < chip->bdbars_count; i++) 956 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 957 /* initialize Buffer Descriptor Lists */ 958 for (i = 0; i < chip->bdbars_count; i++) 959 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 960 return 0; 961 } 962 963 static int snd_intel8x0m_free(struct intel8x0m *chip) 964 { 965 unsigned int i; 966 967 if (chip->irq < 0) 968 goto __hw_end; 969 /* disable interrupts */ 970 for (i = 0; i < chip->bdbars_count; i++) 971 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 972 /* reset channels */ 973 for (i = 0; i < chip->bdbars_count; i++) 974 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 975 __hw_end: 976 if (chip->irq >= 0) 977 free_irq(chip->irq, chip); 978 if (chip->bdbars.area) 979 snd_dma_free_pages(&chip->bdbars); 980 if (chip->addr) 981 pci_iounmap(chip->pci, chip->addr); 982 if (chip->bmaddr) 983 pci_iounmap(chip->pci, chip->bmaddr); 984 pci_release_regions(chip->pci); 985 pci_disable_device(chip->pci); 986 kfree(chip); 987 return 0; 988 } 989 990 #ifdef CONFIG_PM_SLEEP 991 /* 992 * power management 993 */ 994 static int intel8x0m_suspend(struct device *dev) 995 { 996 struct snd_card *card = dev_get_drvdata(dev); 997 struct intel8x0m *chip = card->private_data; 998 999 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1000 snd_ac97_suspend(chip->ac97); 1001 if (chip->irq >= 0) { 1002 free_irq(chip->irq, chip); 1003 chip->irq = -1; 1004 } 1005 return 0; 1006 } 1007 1008 static int intel8x0m_resume(struct device *dev) 1009 { 1010 struct pci_dev *pci = to_pci_dev(dev); 1011 struct snd_card *card = dev_get_drvdata(dev); 1012 struct intel8x0m *chip = card->private_data; 1013 1014 if (request_irq(pci->irq, snd_intel8x0m_interrupt, 1015 IRQF_SHARED, KBUILD_MODNAME, chip)) { 1016 dev_err(dev, "unable to grab IRQ %d, disabling device\n", 1017 pci->irq); 1018 snd_card_disconnect(card); 1019 return -EIO; 1020 } 1021 chip->irq = pci->irq; 1022 snd_intel8x0m_chip_init(chip, 0); 1023 snd_ac97_resume(chip->ac97); 1024 1025 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1026 return 0; 1027 } 1028 1029 static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume); 1030 #define INTEL8X0M_PM_OPS &intel8x0m_pm 1031 #else 1032 #define INTEL8X0M_PM_OPS NULL 1033 #endif /* CONFIG_PM_SLEEP */ 1034 1035 static void snd_intel8x0m_proc_read(struct snd_info_entry * entry, 1036 struct snd_info_buffer *buffer) 1037 { 1038 struct intel8x0m *chip = entry->private_data; 1039 unsigned int tmp; 1040 1041 snd_iprintf(buffer, "Intel8x0m\n\n"); 1042 if (chip->device_type == DEVICE_ALI) 1043 return; 1044 tmp = igetdword(chip, ICHREG(GLOB_STA)); 1045 snd_iprintf(buffer, "Global control : 0x%08x\n", 1046 igetdword(chip, ICHREG(GLOB_CNT))); 1047 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 1048 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 1049 tmp & ICH_PCR ? " primary" : "", 1050 tmp & ICH_SCR ? " secondary" : "", 1051 tmp & ICH_TCR ? " tertiary" : "", 1052 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 1053 } 1054 1055 static void snd_intel8x0m_proc_init(struct intel8x0m *chip) 1056 { 1057 snd_card_ro_proc_new(chip->card, "intel8x0m", chip, 1058 snd_intel8x0m_proc_read); 1059 } 1060 1061 static int snd_intel8x0m_dev_free(struct snd_device *device) 1062 { 1063 struct intel8x0m *chip = device->device_data; 1064 return snd_intel8x0m_free(chip); 1065 } 1066 1067 struct ich_reg_info { 1068 unsigned int int_sta_mask; 1069 unsigned int offset; 1070 }; 1071 1072 static int snd_intel8x0m_create(struct snd_card *card, 1073 struct pci_dev *pci, 1074 unsigned long device_type, 1075 struct intel8x0m **r_intel8x0m) 1076 { 1077 struct intel8x0m *chip; 1078 int err; 1079 unsigned int i; 1080 unsigned int int_sta_masks; 1081 struct ichdev *ichdev; 1082 static struct snd_device_ops ops = { 1083 .dev_free = snd_intel8x0m_dev_free, 1084 }; 1085 static struct ich_reg_info intel_regs[2] = { 1086 { ICH_MIINT, 0 }, 1087 { ICH_MOINT, 0x10 }, 1088 }; 1089 struct ich_reg_info *tbl; 1090 1091 *r_intel8x0m = NULL; 1092 1093 if ((err = pci_enable_device(pci)) < 0) 1094 return err; 1095 1096 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1097 if (chip == NULL) { 1098 pci_disable_device(pci); 1099 return -ENOMEM; 1100 } 1101 spin_lock_init(&chip->reg_lock); 1102 chip->device_type = device_type; 1103 chip->card = card; 1104 chip->pci = pci; 1105 chip->irq = -1; 1106 1107 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 1108 kfree(chip); 1109 pci_disable_device(pci); 1110 return err; 1111 } 1112 1113 if (device_type == DEVICE_ALI) { 1114 /* ALI5455 has no ac97 region */ 1115 chip->bmaddr = pci_iomap(pci, 0, 0); 1116 goto port_inited; 1117 } 1118 1119 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 1120 chip->addr = pci_iomap(pci, 2, 0); 1121 else 1122 chip->addr = pci_iomap(pci, 0, 0); 1123 if (!chip->addr) { 1124 dev_err(card->dev, "AC'97 space ioremap problem\n"); 1125 snd_intel8x0m_free(chip); 1126 return -EIO; 1127 } 1128 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 1129 chip->bmaddr = pci_iomap(pci, 3, 0); 1130 else 1131 chip->bmaddr = pci_iomap(pci, 1, 0); 1132 if (!chip->bmaddr) { 1133 dev_err(card->dev, "Controller space ioremap problem\n"); 1134 snd_intel8x0m_free(chip); 1135 return -EIO; 1136 } 1137 1138 port_inited: 1139 /* initialize offsets */ 1140 chip->bdbars_count = 2; 1141 tbl = intel_regs; 1142 1143 for (i = 0; i < chip->bdbars_count; i++) { 1144 ichdev = &chip->ichd[i]; 1145 ichdev->ichd = i; 1146 ichdev->reg_offset = tbl[i].offset; 1147 ichdev->int_sta_mask = tbl[i].int_sta_mask; 1148 if (device_type == DEVICE_SIS) { 1149 /* SiS 7013 swaps the registers */ 1150 ichdev->roff_sr = ICH_REG_OFF_PICB; 1151 ichdev->roff_picb = ICH_REG_OFF_SR; 1152 } else { 1153 ichdev->roff_sr = ICH_REG_OFF_SR; 1154 ichdev->roff_picb = ICH_REG_OFF_PICB; 1155 } 1156 if (device_type == DEVICE_ALI) 1157 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 1158 } 1159 /* SIS7013 handles the pcm data in bytes, others are in words */ 1160 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 1161 1162 /* allocate buffer descriptor lists */ 1163 /* the start of each lists must be aligned to 8 bytes */ 1164 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 1165 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 1166 &chip->bdbars) < 0) { 1167 snd_intel8x0m_free(chip); 1168 return -ENOMEM; 1169 } 1170 /* tables must be aligned to 8 bytes here, but the kernel pages 1171 are much bigger, so we don't care (on i386) */ 1172 int_sta_masks = 0; 1173 for (i = 0; i < chip->bdbars_count; i++) { 1174 ichdev = &chip->ichd[i]; 1175 ichdev->bdbar = ((__le32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 1176 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 1177 int_sta_masks |= ichdev->int_sta_mask; 1178 } 1179 chip->int_sta_reg = ICH_REG_GLOB_STA; 1180 chip->int_sta_mask = int_sta_masks; 1181 1182 pci_set_master(pci); 1183 1184 if ((err = snd_intel8x0m_chip_init(chip, 1)) < 0) { 1185 snd_intel8x0m_free(chip); 1186 return err; 1187 } 1188 1189 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED, 1190 KBUILD_MODNAME, chip)) { 1191 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 1192 snd_intel8x0m_free(chip); 1193 return -EBUSY; 1194 } 1195 chip->irq = pci->irq; 1196 1197 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1198 snd_intel8x0m_free(chip); 1199 return err; 1200 } 1201 1202 *r_intel8x0m = chip; 1203 return 0; 1204 } 1205 1206 static struct shortname_table { 1207 unsigned int id; 1208 const char *s; 1209 } shortnames[] = { 1210 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" }, 1211 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" }, 1212 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, 1213 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, 1214 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" }, 1215 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" }, 1216 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" }, 1217 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" }, 1218 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" }, 1219 { 0x7446, "AMD AMD768" }, 1220 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, 1221 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" }, 1222 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, 1223 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, 1224 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, 1225 { 0x746e, "AMD AMD8111" }, 1226 #if 0 1227 { 0x5455, "ALi M5455" }, 1228 #endif 1229 { 0 }, 1230 }; 1231 1232 static int snd_intel8x0m_probe(struct pci_dev *pci, 1233 const struct pci_device_id *pci_id) 1234 { 1235 struct snd_card *card; 1236 struct intel8x0m *chip; 1237 int err; 1238 struct shortname_table *name; 1239 1240 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 1241 if (err < 0) 1242 return err; 1243 1244 strcpy(card->driver, "ICH-MODEM"); 1245 strcpy(card->shortname, "Intel ICH"); 1246 for (name = shortnames; name->id; name++) { 1247 if (pci->device == name->id) { 1248 strcpy(card->shortname, name->s); 1249 break; 1250 } 1251 } 1252 strcat(card->shortname," Modem"); 1253 1254 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) { 1255 snd_card_free(card); 1256 return err; 1257 } 1258 card->private_data = chip; 1259 1260 if ((err = snd_intel8x0m_mixer(chip, ac97_clock)) < 0) { 1261 snd_card_free(card); 1262 return err; 1263 } 1264 if ((err = snd_intel8x0m_pcm(chip)) < 0) { 1265 snd_card_free(card); 1266 return err; 1267 } 1268 1269 snd_intel8x0m_proc_init(chip); 1270 1271 sprintf(card->longname, "%s at irq %i", 1272 card->shortname, chip->irq); 1273 1274 if ((err = snd_card_register(card)) < 0) { 1275 snd_card_free(card); 1276 return err; 1277 } 1278 pci_set_drvdata(pci, card); 1279 return 0; 1280 } 1281 1282 static void snd_intel8x0m_remove(struct pci_dev *pci) 1283 { 1284 snd_card_free(pci_get_drvdata(pci)); 1285 } 1286 1287 static struct pci_driver intel8x0m_driver = { 1288 .name = KBUILD_MODNAME, 1289 .id_table = snd_intel8x0m_ids, 1290 .probe = snd_intel8x0m_probe, 1291 .remove = snd_intel8x0m_remove, 1292 .driver = { 1293 .pm = INTEL8X0M_PM_OPS, 1294 }, 1295 }; 1296 1297 module_pci_driver(intel8x0m_driver); 1298