1 /* 2 * ALSA modem driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 5 * 6 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version 7 * of ALSA ICH sound driver intel8x0.c . 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 23 * 24 */ 25 26 #include <linux/io.h> 27 #include <linux/delay.h> 28 #include <linux/interrupt.h> 29 #include <linux/init.h> 30 #include <linux/pci.h> 31 #include <linux/slab.h> 32 #include <linux/module.h> 33 #include <sound/core.h> 34 #include <sound/pcm.h> 35 #include <sound/ac97_codec.h> 36 #include <sound/info.h> 37 #include <sound/initval.h> 38 39 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 40 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; " 41 "SiS 7013; NVidia MCP/2/2S/3 modems"); 42 MODULE_LICENSE("GPL"); 43 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 44 "{Intel,82901AB-ICH0}," 45 "{Intel,82801BA-ICH2}," 46 "{Intel,82801CA-ICH3}," 47 "{Intel,82801DB-ICH4}," 48 "{Intel,ICH5}," 49 "{Intel,ICH6}," 50 "{Intel,ICH7}," 51 "{Intel,MX440}," 52 "{SiS,7013}," 53 "{NVidia,NForce Modem}," 54 "{NVidia,NForce2 Modem}," 55 "{NVidia,NForce2s Modem}," 56 "{NVidia,NForce3 Modem}," 57 "{AMD,AMD768}}"); 58 59 static int index = -2; /* Exclude the first card */ 60 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 61 static int ac97_clock; 62 63 module_param(index, int, 0444); 64 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); 65 module_param(id, charp, 0444); 66 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); 67 module_param(ac97_clock, int, 0444); 68 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 69 70 /* just for backward compatibility */ 71 static bool enable; 72 module_param(enable, bool, 0444); 73 74 /* 75 * Direct registers 76 */ 77 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 78 79 #define ICHREG(x) ICH_REG_##x 80 81 #define DEFINE_REGSET(name,base) \ 82 enum { \ 83 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 84 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 85 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 86 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 87 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 88 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 89 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 90 }; 91 92 /* busmaster blocks */ 93 DEFINE_REGSET(OFF, 0); /* offset */ 94 95 /* values for each busmaster block */ 96 97 /* LVI */ 98 #define ICH_REG_LVI_MASK 0x1f 99 100 /* SR */ 101 #define ICH_FIFOE 0x10 /* FIFO error */ 102 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 103 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 104 #define ICH_CELV 0x02 /* current equals last valid */ 105 #define ICH_DCH 0x01 /* DMA controller halted */ 106 107 /* PIV */ 108 #define ICH_REG_PIV_MASK 0x1f /* mask */ 109 110 /* CR */ 111 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 112 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 113 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 114 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 115 #define ICH_STARTBM 0x01 /* start busmaster operation */ 116 117 118 /* global block */ 119 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ 120 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 121 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 122 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 123 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 124 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 125 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 126 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 127 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */ 128 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 129 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 130 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 131 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 132 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 133 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 134 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 135 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 136 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 137 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 138 #define ICH_RCS 0x00008000 /* read completion status */ 139 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 140 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 141 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 142 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 143 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 144 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 145 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 146 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 147 #define ICH_POINT 0x00000040 /* playback interrupt */ 148 #define ICH_PIINT 0x00000020 /* capture interrupt */ 149 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 150 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 151 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 152 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 153 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ 154 #define ICH_CAS 0x01 /* codec access semaphore */ 155 156 #define ICH_MAX_FRAGS 32 /* max hw frags */ 157 158 159 /* 160 * 161 */ 162 163 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; 164 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; 165 166 #define get_ichdev(substream) (substream->runtime->private_data) 167 168 struct ichdev { 169 unsigned int ichd; /* ich device number */ 170 unsigned long reg_offset; /* offset to bmaddr */ 171 u32 *bdbar; /* CPU address (32bit) */ 172 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 173 struct snd_pcm_substream *substream; 174 unsigned int physbuf; /* physical address (32bit) */ 175 unsigned int size; 176 unsigned int fragsize; 177 unsigned int fragsize1; 178 unsigned int position; 179 int frags; 180 int lvi; 181 int lvi_frag; 182 int civ; 183 int ack; 184 int ack_reload; 185 unsigned int ack_bit; 186 unsigned int roff_sr; 187 unsigned int roff_picb; 188 unsigned int int_sta_mask; /* interrupt status mask */ 189 unsigned int ali_slot; /* ALI DMA slot */ 190 struct snd_ac97 *ac97; 191 }; 192 193 struct intel8x0m { 194 unsigned int device_type; 195 196 int irq; 197 198 void __iomem *addr; 199 void __iomem *bmaddr; 200 201 struct pci_dev *pci; 202 struct snd_card *card; 203 204 int pcm_devs; 205 struct snd_pcm *pcm[2]; 206 struct ichdev ichd[2]; 207 208 unsigned int in_ac97_init: 1; 209 210 struct snd_ac97_bus *ac97_bus; 211 struct snd_ac97 *ac97; 212 213 spinlock_t reg_lock; 214 215 struct snd_dma_buffer bdbars; 216 u32 bdbars_count; 217 u32 int_sta_reg; /* interrupt status register */ 218 u32 int_sta_mask; /* interrupt status mask */ 219 unsigned int pcm_pos_shift; 220 }; 221 222 static const struct pci_device_id snd_intel8x0m_ids[] = { 223 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */ 224 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */ 225 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */ 226 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */ 227 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */ 228 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */ 229 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */ 230 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */ 231 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */ 232 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */ 233 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */ 234 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */ 235 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */ 236 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */ 237 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */ 238 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */ 239 #if 0 240 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 241 #endif 242 { 0, } 243 }; 244 245 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); 246 247 /* 248 * Lowlevel I/O - busmaster 249 */ 250 251 static inline u8 igetbyte(struct intel8x0m *chip, u32 offset) 252 { 253 return ioread8(chip->bmaddr + offset); 254 } 255 256 static inline u16 igetword(struct intel8x0m *chip, u32 offset) 257 { 258 return ioread16(chip->bmaddr + offset); 259 } 260 261 static inline u32 igetdword(struct intel8x0m *chip, u32 offset) 262 { 263 return ioread32(chip->bmaddr + offset); 264 } 265 266 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val) 267 { 268 iowrite8(val, chip->bmaddr + offset); 269 } 270 271 static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val) 272 { 273 iowrite16(val, chip->bmaddr + offset); 274 } 275 276 static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val) 277 { 278 iowrite32(val, chip->bmaddr + offset); 279 } 280 281 /* 282 * Lowlevel I/O - AC'97 registers 283 */ 284 285 static inline u16 iagetword(struct intel8x0m *chip, u32 offset) 286 { 287 return ioread16(chip->addr + offset); 288 } 289 290 static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val) 291 { 292 iowrite16(val, chip->addr + offset); 293 } 294 295 /* 296 * Basic I/O 297 */ 298 299 /* 300 * access to AC97 codec via normal i/o (for ICH and SIS7013) 301 */ 302 303 /* return the GLOB_STA bit for the corresponding codec */ 304 static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec) 305 { 306 static unsigned int codec_bit[3] = { 307 ICH_PCR, ICH_SCR, ICH_TCR 308 }; 309 if (snd_BUG_ON(codec >= 3)) 310 return ICH_PCR; 311 return codec_bit[codec]; 312 } 313 314 static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec) 315 { 316 int time; 317 318 if (codec > 1) 319 return -EIO; 320 codec = get_ich_codec_bit(chip, codec); 321 322 /* codec ready ? */ 323 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 324 return -EIO; 325 326 /* Anyone holding a semaphore for 1 msec should be shot... */ 327 time = 100; 328 do { 329 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 330 return 0; 331 udelay(10); 332 } while (time--); 333 334 /* access to some forbidden (non existent) ac97 registers will not 335 * reset the semaphore. So even if you don't get the semaphore, still 336 * continue the access. We don't need the semaphore anyway. */ 337 dev_err(chip->card->dev, 338 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 339 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 340 iagetword(chip, 0); /* clear semaphore flag */ 341 /* I don't care about the semaphore */ 342 return -EBUSY; 343 } 344 345 static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97, 346 unsigned short reg, 347 unsigned short val) 348 { 349 struct intel8x0m *chip = ac97->private_data; 350 351 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 352 if (! chip->in_ac97_init) 353 dev_err(chip->card->dev, 354 "codec_write %d: semaphore is not ready for register 0x%x\n", 355 ac97->num, reg); 356 } 357 iaputword(chip, reg + ac97->num * 0x80, val); 358 } 359 360 static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97, 361 unsigned short reg) 362 { 363 struct intel8x0m *chip = ac97->private_data; 364 unsigned short res; 365 unsigned int tmp; 366 367 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 368 if (! chip->in_ac97_init) 369 dev_err(chip->card->dev, 370 "codec_read %d: semaphore is not ready for register 0x%x\n", 371 ac97->num, reg); 372 res = 0xffff; 373 } else { 374 res = iagetword(chip, reg + ac97->num * 0x80); 375 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 376 /* reset RCS and preserve other R/WC bits */ 377 iputdword(chip, ICHREG(GLOB_STA), 378 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 379 if (! chip->in_ac97_init) 380 dev_err(chip->card->dev, 381 "codec_read %d: read timeout for register 0x%x\n", 382 ac97->num, reg); 383 res = 0xffff; 384 } 385 } 386 if (reg == AC97_GPIO_STATUS) 387 iagetword(chip, 0); /* clear semaphore */ 388 return res; 389 } 390 391 392 /* 393 * DMA I/O 394 */ 395 static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev) 396 { 397 int idx; 398 u32 *bdbar = ichdev->bdbar; 399 unsigned long port = ichdev->reg_offset; 400 401 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 402 if (ichdev->size == ichdev->fragsize) { 403 ichdev->ack_reload = ichdev->ack = 2; 404 ichdev->fragsize1 = ichdev->fragsize >> 1; 405 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 406 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 407 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 408 ichdev->fragsize1 >> chip->pcm_pos_shift); 409 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 410 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 411 ichdev->fragsize1 >> chip->pcm_pos_shift); 412 } 413 ichdev->frags = 2; 414 } else { 415 ichdev->ack_reload = ichdev->ack = 1; 416 ichdev->fragsize1 = ichdev->fragsize; 417 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 418 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 419 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 420 ichdev->fragsize >> chip->pcm_pos_shift); 421 /* 422 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", 423 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 424 */ 425 } 426 ichdev->frags = ichdev->size / ichdev->fragsize; 427 } 428 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 429 ichdev->civ = 0; 430 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 431 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 432 ichdev->position = 0; 433 #if 0 434 dev_dbg(chip->card->dev, 435 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 436 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, 437 ichdev->fragsize1); 438 #endif 439 /* clear interrupts */ 440 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 441 } 442 443 /* 444 * Interrupt handler 445 */ 446 447 static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev) 448 { 449 unsigned long port = ichdev->reg_offset; 450 int civ, i, step; 451 int ack = 0; 452 453 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 454 if (civ == ichdev->civ) { 455 // snd_printd("civ same %d\n", civ); 456 step = 1; 457 ichdev->civ++; 458 ichdev->civ &= ICH_REG_LVI_MASK; 459 } else { 460 step = civ - ichdev->civ; 461 if (step < 0) 462 step += ICH_REG_LVI_MASK + 1; 463 // if (step != 1) 464 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 465 ichdev->civ = civ; 466 } 467 468 ichdev->position += step * ichdev->fragsize1; 469 ichdev->position %= ichdev->size; 470 ichdev->lvi += step; 471 ichdev->lvi &= ICH_REG_LVI_MASK; 472 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 473 for (i = 0; i < step; i++) { 474 ichdev->lvi_frag++; 475 ichdev->lvi_frag %= ichdev->frags; 476 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + 477 ichdev->lvi_frag * 478 ichdev->fragsize1); 479 #if 0 480 dev_dbg(chip->card->dev, 481 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 482 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 483 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 484 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 485 #endif 486 if (--ichdev->ack == 0) { 487 ichdev->ack = ichdev->ack_reload; 488 ack = 1; 489 } 490 } 491 if (ack && ichdev->substream) { 492 spin_unlock(&chip->reg_lock); 493 snd_pcm_period_elapsed(ichdev->substream); 494 spin_lock(&chip->reg_lock); 495 } 496 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 497 } 498 499 static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id) 500 { 501 struct intel8x0m *chip = dev_id; 502 struct ichdev *ichdev; 503 unsigned int status; 504 unsigned int i; 505 506 spin_lock(&chip->reg_lock); 507 status = igetdword(chip, chip->int_sta_reg); 508 if (status == 0xffffffff) { /* we are not yet resumed */ 509 spin_unlock(&chip->reg_lock); 510 return IRQ_NONE; 511 } 512 if ((status & chip->int_sta_mask) == 0) { 513 if (status) 514 iputdword(chip, chip->int_sta_reg, status); 515 spin_unlock(&chip->reg_lock); 516 return IRQ_NONE; 517 } 518 519 for (i = 0; i < chip->bdbars_count; i++) { 520 ichdev = &chip->ichd[i]; 521 if (status & ichdev->int_sta_mask) 522 snd_intel8x0m_update(chip, ichdev); 523 } 524 525 /* ack them */ 526 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 527 spin_unlock(&chip->reg_lock); 528 529 return IRQ_HANDLED; 530 } 531 532 /* 533 * PCM part 534 */ 535 536 static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 537 { 538 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 539 struct ichdev *ichdev = get_ichdev(substream); 540 unsigned char val = 0; 541 unsigned long port = ichdev->reg_offset; 542 543 switch (cmd) { 544 case SNDRV_PCM_TRIGGER_START: 545 case SNDRV_PCM_TRIGGER_RESUME: 546 val = ICH_IOCE | ICH_STARTBM; 547 break; 548 case SNDRV_PCM_TRIGGER_STOP: 549 case SNDRV_PCM_TRIGGER_SUSPEND: 550 val = 0; 551 break; 552 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 553 val = ICH_IOCE; 554 break; 555 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 556 val = ICH_IOCE | ICH_STARTBM; 557 break; 558 default: 559 return -EINVAL; 560 } 561 iputbyte(chip, port + ICH_REG_OFF_CR, val); 562 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 563 /* wait until DMA stopped */ 564 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 565 /* reset whole DMA things */ 566 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 567 } 568 return 0; 569 } 570 571 static int snd_intel8x0m_hw_params(struct snd_pcm_substream *substream, 572 struct snd_pcm_hw_params *hw_params) 573 { 574 return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 575 } 576 577 static int snd_intel8x0m_hw_free(struct snd_pcm_substream *substream) 578 { 579 return snd_pcm_lib_free_pages(substream); 580 } 581 582 static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream) 583 { 584 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 585 struct ichdev *ichdev = get_ichdev(substream); 586 size_t ptr1, ptr; 587 588 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; 589 if (ptr1 != 0) 590 ptr = ichdev->fragsize1 - ptr1; 591 else 592 ptr = 0; 593 ptr += ichdev->position; 594 if (ptr >= ichdev->size) 595 return 0; 596 return bytes_to_frames(substream->runtime, ptr); 597 } 598 599 static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream) 600 { 601 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 602 struct snd_pcm_runtime *runtime = substream->runtime; 603 struct ichdev *ichdev = get_ichdev(substream); 604 605 ichdev->physbuf = runtime->dma_addr; 606 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 607 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 608 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); 609 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); 610 snd_intel8x0m_setup_periods(chip, ichdev); 611 return 0; 612 } 613 614 static struct snd_pcm_hardware snd_intel8x0m_stream = 615 { 616 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 617 SNDRV_PCM_INFO_BLOCK_TRANSFER | 618 SNDRV_PCM_INFO_MMAP_VALID | 619 SNDRV_PCM_INFO_PAUSE | 620 SNDRV_PCM_INFO_RESUME), 621 .formats = SNDRV_PCM_FMTBIT_S16_LE, 622 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, 623 .rate_min = 8000, 624 .rate_max = 16000, 625 .channels_min = 1, 626 .channels_max = 1, 627 .buffer_bytes_max = 64 * 1024, 628 .period_bytes_min = 32, 629 .period_bytes_max = 64 * 1024, 630 .periods_min = 1, 631 .periods_max = 1024, 632 .fifo_size = 0, 633 }; 634 635 636 static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 637 { 638 static unsigned int rates[] = { 8000, 9600, 12000, 16000 }; 639 static struct snd_pcm_hw_constraint_list hw_constraints_rates = { 640 .count = ARRAY_SIZE(rates), 641 .list = rates, 642 .mask = 0, 643 }; 644 struct snd_pcm_runtime *runtime = substream->runtime; 645 int err; 646 647 ichdev->substream = substream; 648 runtime->hw = snd_intel8x0m_stream; 649 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 650 &hw_constraints_rates); 651 if ( err < 0 ) 652 return err; 653 runtime->private_data = ichdev; 654 return 0; 655 } 656 657 static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream) 658 { 659 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 660 661 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); 662 } 663 664 static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream) 665 { 666 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 667 668 chip->ichd[ICHD_MDMOUT].substream = NULL; 669 return 0; 670 } 671 672 static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream) 673 { 674 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 675 676 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); 677 } 678 679 static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream) 680 { 681 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 682 683 chip->ichd[ICHD_MDMIN].substream = NULL; 684 return 0; 685 } 686 687 688 static struct snd_pcm_ops snd_intel8x0m_playback_ops = { 689 .open = snd_intel8x0m_playback_open, 690 .close = snd_intel8x0m_playback_close, 691 .ioctl = snd_pcm_lib_ioctl, 692 .hw_params = snd_intel8x0m_hw_params, 693 .hw_free = snd_intel8x0m_hw_free, 694 .prepare = snd_intel8x0m_pcm_prepare, 695 .trigger = snd_intel8x0m_pcm_trigger, 696 .pointer = snd_intel8x0m_pcm_pointer, 697 }; 698 699 static struct snd_pcm_ops snd_intel8x0m_capture_ops = { 700 .open = snd_intel8x0m_capture_open, 701 .close = snd_intel8x0m_capture_close, 702 .ioctl = snd_pcm_lib_ioctl, 703 .hw_params = snd_intel8x0m_hw_params, 704 .hw_free = snd_intel8x0m_hw_free, 705 .prepare = snd_intel8x0m_pcm_prepare, 706 .trigger = snd_intel8x0m_pcm_trigger, 707 .pointer = snd_intel8x0m_pcm_pointer, 708 }; 709 710 711 struct ich_pcm_table { 712 char *suffix; 713 struct snd_pcm_ops *playback_ops; 714 struct snd_pcm_ops *capture_ops; 715 size_t prealloc_size; 716 size_t prealloc_max_size; 717 int ac97_idx; 718 }; 719 720 static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device, 721 struct ich_pcm_table *rec) 722 { 723 struct snd_pcm *pcm; 724 int err; 725 char name[32]; 726 727 if (rec->suffix) 728 sprintf(name, "Intel ICH - %s", rec->suffix); 729 else 730 strcpy(name, "Intel ICH"); 731 err = snd_pcm_new(chip->card, name, device, 732 rec->playback_ops ? 1 : 0, 733 rec->capture_ops ? 1 : 0, &pcm); 734 if (err < 0) 735 return err; 736 737 if (rec->playback_ops) 738 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 739 if (rec->capture_ops) 740 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 741 742 pcm->private_data = chip; 743 pcm->info_flags = 0; 744 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 745 if (rec->suffix) 746 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 747 else 748 strcpy(pcm->name, chip->card->shortname); 749 chip->pcm[device] = pcm; 750 751 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 752 snd_dma_pci_data(chip->pci), 753 rec->prealloc_size, 754 rec->prealloc_max_size); 755 756 return 0; 757 } 758 759 static struct ich_pcm_table intel_pcms[] = { 760 { 761 .suffix = "Modem", 762 .playback_ops = &snd_intel8x0m_playback_ops, 763 .capture_ops = &snd_intel8x0m_capture_ops, 764 .prealloc_size = 32 * 1024, 765 .prealloc_max_size = 64 * 1024, 766 }, 767 }; 768 769 static int snd_intel8x0m_pcm(struct intel8x0m *chip) 770 { 771 int i, tblsize, device, err; 772 struct ich_pcm_table *tbl, *rec; 773 774 #if 1 775 tbl = intel_pcms; 776 tblsize = 1; 777 #else 778 switch (chip->device_type) { 779 case DEVICE_NFORCE: 780 tbl = nforce_pcms; 781 tblsize = ARRAY_SIZE(nforce_pcms); 782 break; 783 case DEVICE_ALI: 784 tbl = ali_pcms; 785 tblsize = ARRAY_SIZE(ali_pcms); 786 break; 787 default: 788 tbl = intel_pcms; 789 tblsize = 2; 790 break; 791 } 792 #endif 793 device = 0; 794 for (i = 0; i < tblsize; i++) { 795 rec = tbl + i; 796 if (i > 0 && rec->ac97_idx) { 797 /* activate PCM only when associated AC'97 codec */ 798 if (! chip->ichd[rec->ac97_idx].ac97) 799 continue; 800 } 801 err = snd_intel8x0m_pcm1(chip, device, rec); 802 if (err < 0) 803 return err; 804 device++; 805 } 806 807 chip->pcm_devs = device; 808 return 0; 809 } 810 811 812 /* 813 * Mixer part 814 */ 815 816 static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 817 { 818 struct intel8x0m *chip = bus->private_data; 819 chip->ac97_bus = NULL; 820 } 821 822 static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97) 823 { 824 struct intel8x0m *chip = ac97->private_data; 825 chip->ac97 = NULL; 826 } 827 828 829 static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock) 830 { 831 struct snd_ac97_bus *pbus; 832 struct snd_ac97_template ac97; 833 struct snd_ac97 *x97; 834 int err; 835 unsigned int glob_sta = 0; 836 static struct snd_ac97_bus_ops ops = { 837 .write = snd_intel8x0m_codec_write, 838 .read = snd_intel8x0m_codec_read, 839 }; 840 841 chip->in_ac97_init = 1; 842 843 memset(&ac97, 0, sizeof(ac97)); 844 ac97.private_data = chip; 845 ac97.private_free = snd_intel8x0m_mixer_free_ac97; 846 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE; 847 848 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 849 850 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 851 goto __err; 852 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus; 853 if (ac97_clock >= 8000 && ac97_clock <= 48000) 854 pbus->clock = ac97_clock; 855 chip->ac97_bus = pbus; 856 857 ac97.pci = chip->pci; 858 ac97.num = glob_sta & ICH_SCR ? 1 : 0; 859 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) { 860 dev_err(chip->card->dev, 861 "Unable to initialize codec #%d\n", ac97.num); 862 if (ac97.num == 0) 863 goto __err; 864 return err; 865 } 866 chip->ac97 = x97; 867 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { 868 chip->ichd[ICHD_MDMIN].ac97 = x97; 869 chip->ichd[ICHD_MDMOUT].ac97 = x97; 870 } 871 872 chip->in_ac97_init = 0; 873 return 0; 874 875 __err: 876 /* clear the cold-reset bit for the next chance */ 877 if (chip->device_type != DEVICE_ALI) 878 iputdword(chip, ICHREG(GLOB_CNT), 879 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 880 return err; 881 } 882 883 884 /* 885 * 886 */ 887 888 static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing) 889 { 890 unsigned long end_time; 891 unsigned int cnt, status, nstatus; 892 893 /* put logic to right state */ 894 /* first clear status bits */ 895 status = ICH_RCS | ICH_MIINT | ICH_MOINT; 896 cnt = igetdword(chip, ICHREG(GLOB_STA)); 897 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 898 899 /* ACLink on, 2 channels */ 900 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 901 cnt &= ~(ICH_ACLINK); 902 /* finish cold or do warm reset */ 903 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 904 iputdword(chip, ICHREG(GLOB_CNT), cnt); 905 usleep_range(500, 1000); /* give warm reset some time */ 906 end_time = jiffies + HZ / 4; 907 do { 908 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 909 goto __ok; 910 schedule_timeout_uninterruptible(1); 911 } while (time_after_eq(end_time, jiffies)); 912 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", 913 igetdword(chip, ICHREG(GLOB_CNT))); 914 return -EIO; 915 916 __ok: 917 if (probing) { 918 /* wait for any codec ready status. 919 * Once it becomes ready it should remain ready 920 * as long as we do not disable the ac97 link. 921 */ 922 end_time = jiffies + HZ; 923 do { 924 status = igetdword(chip, ICHREG(GLOB_STA)) & 925 (ICH_PCR | ICH_SCR | ICH_TCR); 926 if (status) 927 break; 928 schedule_timeout_uninterruptible(1); 929 } while (time_after_eq(end_time, jiffies)); 930 if (! status) { 931 /* no codec is found */ 932 dev_err(chip->card->dev, 933 "codec_ready: codec is not ready [0x%x]\n", 934 igetdword(chip, ICHREG(GLOB_STA))); 935 return -EIO; 936 } 937 938 /* up to two codecs (modem cannot be tertiary with ICH4) */ 939 nstatus = ICH_PCR | ICH_SCR; 940 941 /* wait for other codecs ready status. */ 942 end_time = jiffies + HZ / 4; 943 while (status != nstatus && time_after_eq(end_time, jiffies)) { 944 schedule_timeout_uninterruptible(1); 945 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 946 } 947 948 } else { 949 /* resume phase */ 950 status = 0; 951 if (chip->ac97) 952 status |= get_ich_codec_bit(chip, chip->ac97->num); 953 /* wait until all the probed codecs are ready */ 954 end_time = jiffies + HZ; 955 do { 956 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 957 (ICH_PCR | ICH_SCR | ICH_TCR); 958 if (status == nstatus) 959 break; 960 schedule_timeout_uninterruptible(1); 961 } while (time_after_eq(end_time, jiffies)); 962 } 963 964 if (chip->device_type == DEVICE_SIS) { 965 /* unmute the output on SIS7012 */ 966 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 967 } 968 969 return 0; 970 } 971 972 static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing) 973 { 974 unsigned int i; 975 int err; 976 977 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0) 978 return err; 979 iagetword(chip, 0); /* clear semaphore flag */ 980 981 /* disable interrupts */ 982 for (i = 0; i < chip->bdbars_count; i++) 983 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 984 /* reset channels */ 985 for (i = 0; i < chip->bdbars_count; i++) 986 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 987 /* initialize Buffer Descriptor Lists */ 988 for (i = 0; i < chip->bdbars_count; i++) 989 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 990 return 0; 991 } 992 993 static int snd_intel8x0m_free(struct intel8x0m *chip) 994 { 995 unsigned int i; 996 997 if (chip->irq < 0) 998 goto __hw_end; 999 /* disable interrupts */ 1000 for (i = 0; i < chip->bdbars_count; i++) 1001 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 1002 /* reset channels */ 1003 for (i = 0; i < chip->bdbars_count; i++) 1004 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 1005 __hw_end: 1006 if (chip->irq >= 0) 1007 free_irq(chip->irq, chip); 1008 if (chip->bdbars.area) 1009 snd_dma_free_pages(&chip->bdbars); 1010 if (chip->addr) 1011 pci_iounmap(chip->pci, chip->addr); 1012 if (chip->bmaddr) 1013 pci_iounmap(chip->pci, chip->bmaddr); 1014 pci_release_regions(chip->pci); 1015 pci_disable_device(chip->pci); 1016 kfree(chip); 1017 return 0; 1018 } 1019 1020 #ifdef CONFIG_PM_SLEEP 1021 /* 1022 * power management 1023 */ 1024 static int intel8x0m_suspend(struct device *dev) 1025 { 1026 struct snd_card *card = dev_get_drvdata(dev); 1027 struct intel8x0m *chip = card->private_data; 1028 int i; 1029 1030 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1031 for (i = 0; i < chip->pcm_devs; i++) 1032 snd_pcm_suspend_all(chip->pcm[i]); 1033 snd_ac97_suspend(chip->ac97); 1034 if (chip->irq >= 0) { 1035 free_irq(chip->irq, chip); 1036 chip->irq = -1; 1037 } 1038 return 0; 1039 } 1040 1041 static int intel8x0m_resume(struct device *dev) 1042 { 1043 struct pci_dev *pci = to_pci_dev(dev); 1044 struct snd_card *card = dev_get_drvdata(dev); 1045 struct intel8x0m *chip = card->private_data; 1046 1047 if (request_irq(pci->irq, snd_intel8x0m_interrupt, 1048 IRQF_SHARED, KBUILD_MODNAME, chip)) { 1049 dev_err(dev, "unable to grab IRQ %d, disabling device\n", 1050 pci->irq); 1051 snd_card_disconnect(card); 1052 return -EIO; 1053 } 1054 chip->irq = pci->irq; 1055 snd_intel8x0m_chip_init(chip, 0); 1056 snd_ac97_resume(chip->ac97); 1057 1058 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1059 return 0; 1060 } 1061 1062 static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume); 1063 #define INTEL8X0M_PM_OPS &intel8x0m_pm 1064 #else 1065 #define INTEL8X0M_PM_OPS NULL 1066 #endif /* CONFIG_PM_SLEEP */ 1067 1068 static void snd_intel8x0m_proc_read(struct snd_info_entry * entry, 1069 struct snd_info_buffer *buffer) 1070 { 1071 struct intel8x0m *chip = entry->private_data; 1072 unsigned int tmp; 1073 1074 snd_iprintf(buffer, "Intel8x0m\n\n"); 1075 if (chip->device_type == DEVICE_ALI) 1076 return; 1077 tmp = igetdword(chip, ICHREG(GLOB_STA)); 1078 snd_iprintf(buffer, "Global control : 0x%08x\n", 1079 igetdword(chip, ICHREG(GLOB_CNT))); 1080 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 1081 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 1082 tmp & ICH_PCR ? " primary" : "", 1083 tmp & ICH_SCR ? " secondary" : "", 1084 tmp & ICH_TCR ? " tertiary" : "", 1085 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 1086 } 1087 1088 static void snd_intel8x0m_proc_init(struct intel8x0m *chip) 1089 { 1090 struct snd_info_entry *entry; 1091 1092 if (! snd_card_proc_new(chip->card, "intel8x0m", &entry)) 1093 snd_info_set_text_ops(entry, chip, snd_intel8x0m_proc_read); 1094 } 1095 1096 static int snd_intel8x0m_dev_free(struct snd_device *device) 1097 { 1098 struct intel8x0m *chip = device->device_data; 1099 return snd_intel8x0m_free(chip); 1100 } 1101 1102 struct ich_reg_info { 1103 unsigned int int_sta_mask; 1104 unsigned int offset; 1105 }; 1106 1107 static int snd_intel8x0m_create(struct snd_card *card, 1108 struct pci_dev *pci, 1109 unsigned long device_type, 1110 struct intel8x0m **r_intel8x0m) 1111 { 1112 struct intel8x0m *chip; 1113 int err; 1114 unsigned int i; 1115 unsigned int int_sta_masks; 1116 struct ichdev *ichdev; 1117 static struct snd_device_ops ops = { 1118 .dev_free = snd_intel8x0m_dev_free, 1119 }; 1120 static struct ich_reg_info intel_regs[2] = { 1121 { ICH_MIINT, 0 }, 1122 { ICH_MOINT, 0x10 }, 1123 }; 1124 struct ich_reg_info *tbl; 1125 1126 *r_intel8x0m = NULL; 1127 1128 if ((err = pci_enable_device(pci)) < 0) 1129 return err; 1130 1131 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1132 if (chip == NULL) { 1133 pci_disable_device(pci); 1134 return -ENOMEM; 1135 } 1136 spin_lock_init(&chip->reg_lock); 1137 chip->device_type = device_type; 1138 chip->card = card; 1139 chip->pci = pci; 1140 chip->irq = -1; 1141 1142 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 1143 kfree(chip); 1144 pci_disable_device(pci); 1145 return err; 1146 } 1147 1148 if (device_type == DEVICE_ALI) { 1149 /* ALI5455 has no ac97 region */ 1150 chip->bmaddr = pci_iomap(pci, 0, 0); 1151 goto port_inited; 1152 } 1153 1154 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 1155 chip->addr = pci_iomap(pci, 2, 0); 1156 else 1157 chip->addr = pci_iomap(pci, 0, 0); 1158 if (!chip->addr) { 1159 dev_err(card->dev, "AC'97 space ioremap problem\n"); 1160 snd_intel8x0m_free(chip); 1161 return -EIO; 1162 } 1163 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 1164 chip->bmaddr = pci_iomap(pci, 3, 0); 1165 else 1166 chip->bmaddr = pci_iomap(pci, 1, 0); 1167 if (!chip->bmaddr) { 1168 dev_err(card->dev, "Controller space ioremap problem\n"); 1169 snd_intel8x0m_free(chip); 1170 return -EIO; 1171 } 1172 1173 port_inited: 1174 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED, 1175 KBUILD_MODNAME, chip)) { 1176 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 1177 snd_intel8x0m_free(chip); 1178 return -EBUSY; 1179 } 1180 chip->irq = pci->irq; 1181 pci_set_master(pci); 1182 synchronize_irq(chip->irq); 1183 1184 /* initialize offsets */ 1185 chip->bdbars_count = 2; 1186 tbl = intel_regs; 1187 1188 for (i = 0; i < chip->bdbars_count; i++) { 1189 ichdev = &chip->ichd[i]; 1190 ichdev->ichd = i; 1191 ichdev->reg_offset = tbl[i].offset; 1192 ichdev->int_sta_mask = tbl[i].int_sta_mask; 1193 if (device_type == DEVICE_SIS) { 1194 /* SiS 7013 swaps the registers */ 1195 ichdev->roff_sr = ICH_REG_OFF_PICB; 1196 ichdev->roff_picb = ICH_REG_OFF_SR; 1197 } else { 1198 ichdev->roff_sr = ICH_REG_OFF_SR; 1199 ichdev->roff_picb = ICH_REG_OFF_PICB; 1200 } 1201 if (device_type == DEVICE_ALI) 1202 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 1203 } 1204 /* SIS7013 handles the pcm data in bytes, others are in words */ 1205 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 1206 1207 /* allocate buffer descriptor lists */ 1208 /* the start of each lists must be aligned to 8 bytes */ 1209 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 1210 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 1211 &chip->bdbars) < 0) { 1212 snd_intel8x0m_free(chip); 1213 return -ENOMEM; 1214 } 1215 /* tables must be aligned to 8 bytes here, but the kernel pages 1216 are much bigger, so we don't care (on i386) */ 1217 int_sta_masks = 0; 1218 for (i = 0; i < chip->bdbars_count; i++) { 1219 ichdev = &chip->ichd[i]; 1220 ichdev->bdbar = ((u32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 1221 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 1222 int_sta_masks |= ichdev->int_sta_mask; 1223 } 1224 chip->int_sta_reg = ICH_REG_GLOB_STA; 1225 chip->int_sta_mask = int_sta_masks; 1226 1227 if ((err = snd_intel8x0m_chip_init(chip, 1)) < 0) { 1228 snd_intel8x0m_free(chip); 1229 return err; 1230 } 1231 1232 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1233 snd_intel8x0m_free(chip); 1234 return err; 1235 } 1236 1237 *r_intel8x0m = chip; 1238 return 0; 1239 } 1240 1241 static struct shortname_table { 1242 unsigned int id; 1243 const char *s; 1244 } shortnames[] = { 1245 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" }, 1246 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" }, 1247 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, 1248 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, 1249 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" }, 1250 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" }, 1251 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" }, 1252 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" }, 1253 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" }, 1254 { 0x7446, "AMD AMD768" }, 1255 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, 1256 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" }, 1257 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, 1258 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, 1259 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, 1260 { 0x746e, "AMD AMD8111" }, 1261 #if 0 1262 { 0x5455, "ALi M5455" }, 1263 #endif 1264 { 0 }, 1265 }; 1266 1267 static int snd_intel8x0m_probe(struct pci_dev *pci, 1268 const struct pci_device_id *pci_id) 1269 { 1270 struct snd_card *card; 1271 struct intel8x0m *chip; 1272 int err; 1273 struct shortname_table *name; 1274 1275 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 1276 if (err < 0) 1277 return err; 1278 1279 strcpy(card->driver, "ICH-MODEM"); 1280 strcpy(card->shortname, "Intel ICH"); 1281 for (name = shortnames; name->id; name++) { 1282 if (pci->device == name->id) { 1283 strcpy(card->shortname, name->s); 1284 break; 1285 } 1286 } 1287 strcat(card->shortname," Modem"); 1288 1289 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) { 1290 snd_card_free(card); 1291 return err; 1292 } 1293 card->private_data = chip; 1294 1295 if ((err = snd_intel8x0m_mixer(chip, ac97_clock)) < 0) { 1296 snd_card_free(card); 1297 return err; 1298 } 1299 if ((err = snd_intel8x0m_pcm(chip)) < 0) { 1300 snd_card_free(card); 1301 return err; 1302 } 1303 1304 snd_intel8x0m_proc_init(chip); 1305 1306 sprintf(card->longname, "%s at irq %i", 1307 card->shortname, chip->irq); 1308 1309 if ((err = snd_card_register(card)) < 0) { 1310 snd_card_free(card); 1311 return err; 1312 } 1313 pci_set_drvdata(pci, card); 1314 return 0; 1315 } 1316 1317 static void snd_intel8x0m_remove(struct pci_dev *pci) 1318 { 1319 snd_card_free(pci_get_drvdata(pci)); 1320 } 1321 1322 static struct pci_driver intel8x0m_driver = { 1323 .name = KBUILD_MODNAME, 1324 .id_table = snd_intel8x0m_ids, 1325 .probe = snd_intel8x0m_probe, 1326 .remove = snd_intel8x0m_remove, 1327 .driver = { 1328 .pm = INTEL8X0M_PM_OPS, 1329 }, 1330 }; 1331 1332 module_pci_driver(intel8x0m_driver); 1333