1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA modem driver for Intel ICH (i8x0) chipsets 4 * 5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 6 * 7 * This is modified (by Sasha Khapyorsky <sashak@alsa-project.org>) version 8 * of ALSA ICH sound driver intel8x0.c . 9 */ 10 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/interrupt.h> 14 #include <linux/init.h> 15 #include <linux/pci.h> 16 #include <linux/slab.h> 17 #include <linux/module.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/ac97_codec.h> 21 #include <sound/info.h> 22 #include <sound/initval.h> 23 24 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 25 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; " 26 "SiS 7013; NVidia MCP/2/2S/3 modems"); 27 MODULE_LICENSE("GPL"); 28 29 static int index = -2; /* Exclude the first card */ 30 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 31 static int ac97_clock; 32 33 module_param(index, int, 0444); 34 MODULE_PARM_DESC(index, "Index value for Intel i8x0 modemcard."); 35 module_param(id, charp, 0444); 36 MODULE_PARM_DESC(id, "ID string for Intel i8x0 modemcard."); 37 module_param(ac97_clock, int, 0444); 38 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 39 40 /* just for backward compatibility */ 41 static bool enable; 42 module_param(enable, bool, 0444); 43 44 /* 45 * Direct registers 46 */ 47 enum { DEVICE_INTEL, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 48 49 #define ICHREG(x) ICH_REG_##x 50 51 #define DEFINE_REGSET(name,base) \ 52 enum { \ 53 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 54 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 55 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 56 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 57 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 58 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 59 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 60 }; 61 62 /* busmaster blocks */ 63 DEFINE_REGSET(OFF, 0); /* offset */ 64 65 /* values for each busmaster block */ 66 67 /* LVI */ 68 #define ICH_REG_LVI_MASK 0x1f 69 70 /* SR */ 71 #define ICH_FIFOE 0x10 /* FIFO error */ 72 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 73 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 74 #define ICH_CELV 0x02 /* current equals last valid */ 75 #define ICH_DCH 0x01 /* DMA controller halted */ 76 77 /* PIV */ 78 #define ICH_REG_PIV_MASK 0x1f /* mask */ 79 80 /* CR */ 81 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 82 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 83 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 84 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 85 #define ICH_STARTBM 0x01 /* start busmaster operation */ 86 87 88 /* global block */ 89 #define ICH_REG_GLOB_CNT 0x3c /* dword - global control */ 90 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 91 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 92 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 93 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 94 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 95 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 96 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 97 #define ICH_REG_GLOB_STA 0x40 /* dword - global status */ 98 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 99 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 100 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 101 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 102 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 103 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 104 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 105 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 106 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 107 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 108 #define ICH_RCS 0x00008000 /* read completion status */ 109 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 110 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 111 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 112 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 113 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 114 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 115 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 116 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 117 #define ICH_POINT 0x00000040 /* playback interrupt */ 118 #define ICH_PIINT 0x00000020 /* capture interrupt */ 119 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 120 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 121 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 122 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 123 #define ICH_REG_ACC_SEMA 0x44 /* byte - codec write semaphore */ 124 #define ICH_CAS 0x01 /* codec access semaphore */ 125 126 #define ICH_MAX_FRAGS 32 /* max hw frags */ 127 128 129 /* 130 * 131 */ 132 133 enum { ICHD_MDMIN, ICHD_MDMOUT, ICHD_MDMLAST = ICHD_MDMOUT }; 134 enum { ALID_MDMIN, ALID_MDMOUT, ALID_MDMLAST = ALID_MDMOUT }; 135 136 #define get_ichdev(substream) (substream->runtime->private_data) 137 138 struct ichdev { 139 unsigned int ichd; /* ich device number */ 140 unsigned long reg_offset; /* offset to bmaddr */ 141 __le32 *bdbar; /* CPU address (32bit) */ 142 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 143 struct snd_pcm_substream *substream; 144 unsigned int physbuf; /* physical address (32bit) */ 145 unsigned int size; 146 unsigned int fragsize; 147 unsigned int fragsize1; 148 unsigned int position; 149 int frags; 150 int lvi; 151 int lvi_frag; 152 int civ; 153 int ack; 154 int ack_reload; 155 unsigned int ack_bit; 156 unsigned int roff_sr; 157 unsigned int roff_picb; 158 unsigned int int_sta_mask; /* interrupt status mask */ 159 unsigned int ali_slot; /* ALI DMA slot */ 160 struct snd_ac97 *ac97; 161 }; 162 163 struct intel8x0m { 164 unsigned int device_type; 165 166 int irq; 167 168 void __iomem *addr; 169 void __iomem *bmaddr; 170 171 struct pci_dev *pci; 172 struct snd_card *card; 173 174 int pcm_devs; 175 struct snd_pcm *pcm[2]; 176 struct ichdev ichd[2]; 177 178 unsigned int in_ac97_init: 1; 179 180 struct snd_ac97_bus *ac97_bus; 181 struct snd_ac97 *ac97; 182 183 spinlock_t reg_lock; 184 185 struct snd_dma_buffer bdbars; 186 u32 bdbars_count; 187 u32 int_sta_reg; /* interrupt status register */ 188 u32 int_sta_mask; /* interrupt status mask */ 189 unsigned int pcm_pos_shift; 190 }; 191 192 static const struct pci_device_id snd_intel8x0m_ids[] = { 193 { PCI_VDEVICE(INTEL, 0x2416), DEVICE_INTEL }, /* 82801AA */ 194 { PCI_VDEVICE(INTEL, 0x2426), DEVICE_INTEL }, /* 82901AB */ 195 { PCI_VDEVICE(INTEL, 0x2446), DEVICE_INTEL }, /* 82801BA */ 196 { PCI_VDEVICE(INTEL, 0x2486), DEVICE_INTEL }, /* ICH3 */ 197 { PCI_VDEVICE(INTEL, 0x24c6), DEVICE_INTEL }, /* ICH4 */ 198 { PCI_VDEVICE(INTEL, 0x24d6), DEVICE_INTEL }, /* ICH5 */ 199 { PCI_VDEVICE(INTEL, 0x266d), DEVICE_INTEL }, /* ICH6 */ 200 { PCI_VDEVICE(INTEL, 0x27dd), DEVICE_INTEL }, /* ICH7 */ 201 { PCI_VDEVICE(INTEL, 0x7196), DEVICE_INTEL }, /* 440MX */ 202 { PCI_VDEVICE(AMD, 0x7446), DEVICE_INTEL }, /* AMD768 */ 203 { PCI_VDEVICE(SI, 0x7013), DEVICE_SIS }, /* SI7013 */ 204 { PCI_VDEVICE(NVIDIA, 0x01c1), DEVICE_NFORCE }, /* NFORCE */ 205 { PCI_VDEVICE(NVIDIA, 0x0069), DEVICE_NFORCE }, /* NFORCE2 */ 206 { PCI_VDEVICE(NVIDIA, 0x0089), DEVICE_NFORCE }, /* NFORCE2s */ 207 { PCI_VDEVICE(NVIDIA, 0x00d9), DEVICE_NFORCE }, /* NFORCE3 */ 208 { PCI_VDEVICE(AMD, 0x746e), DEVICE_INTEL }, /* AMD8111 */ 209 #if 0 210 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 211 #endif 212 { 0, } 213 }; 214 215 MODULE_DEVICE_TABLE(pci, snd_intel8x0m_ids); 216 217 /* 218 * Lowlevel I/O - busmaster 219 */ 220 221 static inline u8 igetbyte(struct intel8x0m *chip, u32 offset) 222 { 223 return ioread8(chip->bmaddr + offset); 224 } 225 226 static inline u16 igetword(struct intel8x0m *chip, u32 offset) 227 { 228 return ioread16(chip->bmaddr + offset); 229 } 230 231 static inline u32 igetdword(struct intel8x0m *chip, u32 offset) 232 { 233 return ioread32(chip->bmaddr + offset); 234 } 235 236 static inline void iputbyte(struct intel8x0m *chip, u32 offset, u8 val) 237 { 238 iowrite8(val, chip->bmaddr + offset); 239 } 240 241 static inline void iputword(struct intel8x0m *chip, u32 offset, u16 val) 242 { 243 iowrite16(val, chip->bmaddr + offset); 244 } 245 246 static inline void iputdword(struct intel8x0m *chip, u32 offset, u32 val) 247 { 248 iowrite32(val, chip->bmaddr + offset); 249 } 250 251 /* 252 * Lowlevel I/O - AC'97 registers 253 */ 254 255 static inline u16 iagetword(struct intel8x0m *chip, u32 offset) 256 { 257 return ioread16(chip->addr + offset); 258 } 259 260 static inline void iaputword(struct intel8x0m *chip, u32 offset, u16 val) 261 { 262 iowrite16(val, chip->addr + offset); 263 } 264 265 /* 266 * Basic I/O 267 */ 268 269 /* 270 * access to AC97 codec via normal i/o (for ICH and SIS7013) 271 */ 272 273 /* return the GLOB_STA bit for the corresponding codec */ 274 static unsigned int get_ich_codec_bit(struct intel8x0m *chip, unsigned int codec) 275 { 276 static const unsigned int codec_bit[3] = { 277 ICH_PCR, ICH_SCR, ICH_TCR 278 }; 279 if (snd_BUG_ON(codec >= 3)) 280 return ICH_PCR; 281 return codec_bit[codec]; 282 } 283 284 static int snd_intel8x0m_codec_semaphore(struct intel8x0m *chip, unsigned int codec) 285 { 286 int time; 287 288 if (codec > 1) 289 return -EIO; 290 codec = get_ich_codec_bit(chip, codec); 291 292 /* codec ready ? */ 293 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 294 return -EIO; 295 296 /* Anyone holding a semaphore for 1 msec should be shot... */ 297 time = 100; 298 do { 299 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 300 return 0; 301 udelay(10); 302 } while (time--); 303 304 /* access to some forbidden (non existent) ac97 registers will not 305 * reset the semaphore. So even if you don't get the semaphore, still 306 * continue the access. We don't need the semaphore anyway. */ 307 dev_err(chip->card->dev, 308 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 309 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 310 iagetword(chip, 0); /* clear semaphore flag */ 311 /* I don't care about the semaphore */ 312 return -EBUSY; 313 } 314 315 static void snd_intel8x0m_codec_write(struct snd_ac97 *ac97, 316 unsigned short reg, 317 unsigned short val) 318 { 319 struct intel8x0m *chip = ac97->private_data; 320 321 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 322 if (! chip->in_ac97_init) 323 dev_err(chip->card->dev, 324 "codec_write %d: semaphore is not ready for register 0x%x\n", 325 ac97->num, reg); 326 } 327 iaputword(chip, reg + ac97->num * 0x80, val); 328 } 329 330 static unsigned short snd_intel8x0m_codec_read(struct snd_ac97 *ac97, 331 unsigned short reg) 332 { 333 struct intel8x0m *chip = ac97->private_data; 334 unsigned short res; 335 unsigned int tmp; 336 337 if (snd_intel8x0m_codec_semaphore(chip, ac97->num) < 0) { 338 if (! chip->in_ac97_init) 339 dev_err(chip->card->dev, 340 "codec_read %d: semaphore is not ready for register 0x%x\n", 341 ac97->num, reg); 342 res = 0xffff; 343 } else { 344 res = iagetword(chip, reg + ac97->num * 0x80); 345 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 346 /* reset RCS and preserve other R/WC bits */ 347 iputdword(chip, ICHREG(GLOB_STA), 348 tmp & ~(ICH_SRI|ICH_PRI|ICH_TRI|ICH_GSCI)); 349 if (! chip->in_ac97_init) 350 dev_err(chip->card->dev, 351 "codec_read %d: read timeout for register 0x%x\n", 352 ac97->num, reg); 353 res = 0xffff; 354 } 355 } 356 if (reg == AC97_GPIO_STATUS) 357 iagetword(chip, 0); /* clear semaphore */ 358 return res; 359 } 360 361 362 /* 363 * DMA I/O 364 */ 365 static void snd_intel8x0m_setup_periods(struct intel8x0m *chip, struct ichdev *ichdev) 366 { 367 int idx; 368 __le32 *bdbar = ichdev->bdbar; 369 unsigned long port = ichdev->reg_offset; 370 371 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 372 if (ichdev->size == ichdev->fragsize) { 373 ichdev->ack_reload = ichdev->ack = 2; 374 ichdev->fragsize1 = ichdev->fragsize >> 1; 375 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 376 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 377 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 378 ichdev->fragsize1 >> chip->pcm_pos_shift); 379 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 380 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 381 ichdev->fragsize1 >> chip->pcm_pos_shift); 382 } 383 ichdev->frags = 2; 384 } else { 385 ichdev->ack_reload = ichdev->ack = 1; 386 ichdev->fragsize1 = ichdev->fragsize; 387 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 388 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + (((idx >> 1) * ichdev->fragsize) % ichdev->size)); 389 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 390 ichdev->fragsize >> chip->pcm_pos_shift); 391 /* 392 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", 393 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 394 */ 395 } 396 ichdev->frags = ichdev->size / ichdev->fragsize; 397 } 398 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 399 ichdev->civ = 0; 400 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 401 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 402 ichdev->position = 0; 403 #if 0 404 dev_dbg(chip->card->dev, 405 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 406 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, 407 ichdev->fragsize1); 408 #endif 409 /* clear interrupts */ 410 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 411 } 412 413 /* 414 * Interrupt handler 415 */ 416 417 static inline void snd_intel8x0m_update(struct intel8x0m *chip, struct ichdev *ichdev) 418 { 419 unsigned long port = ichdev->reg_offset; 420 int civ, i, step; 421 int ack = 0; 422 423 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 424 if (civ == ichdev->civ) { 425 // snd_printd("civ same %d\n", civ); 426 step = 1; 427 ichdev->civ++; 428 ichdev->civ &= ICH_REG_LVI_MASK; 429 } else { 430 step = civ - ichdev->civ; 431 if (step < 0) 432 step += ICH_REG_LVI_MASK + 1; 433 // if (step != 1) 434 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 435 ichdev->civ = civ; 436 } 437 438 ichdev->position += step * ichdev->fragsize1; 439 ichdev->position %= ichdev->size; 440 ichdev->lvi += step; 441 ichdev->lvi &= ICH_REG_LVI_MASK; 442 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 443 for (i = 0; i < step; i++) { 444 ichdev->lvi_frag++; 445 ichdev->lvi_frag %= ichdev->frags; 446 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + 447 ichdev->lvi_frag * 448 ichdev->fragsize1); 449 #if 0 450 dev_dbg(chip->card->dev, 451 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 452 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 453 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 454 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 455 #endif 456 if (--ichdev->ack == 0) { 457 ichdev->ack = ichdev->ack_reload; 458 ack = 1; 459 } 460 } 461 if (ack && ichdev->substream) { 462 spin_unlock(&chip->reg_lock); 463 snd_pcm_period_elapsed(ichdev->substream); 464 spin_lock(&chip->reg_lock); 465 } 466 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 467 } 468 469 static irqreturn_t snd_intel8x0m_interrupt(int irq, void *dev_id) 470 { 471 struct intel8x0m *chip = dev_id; 472 struct ichdev *ichdev; 473 unsigned int status; 474 unsigned int i; 475 476 spin_lock(&chip->reg_lock); 477 status = igetdword(chip, chip->int_sta_reg); 478 if (status == 0xffffffff) { /* we are not yet resumed */ 479 spin_unlock(&chip->reg_lock); 480 return IRQ_NONE; 481 } 482 if ((status & chip->int_sta_mask) == 0) { 483 if (status) 484 iputdword(chip, chip->int_sta_reg, status); 485 spin_unlock(&chip->reg_lock); 486 return IRQ_NONE; 487 } 488 489 for (i = 0; i < chip->bdbars_count; i++) { 490 ichdev = &chip->ichd[i]; 491 if (status & ichdev->int_sta_mask) 492 snd_intel8x0m_update(chip, ichdev); 493 } 494 495 /* ack them */ 496 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 497 spin_unlock(&chip->reg_lock); 498 499 return IRQ_HANDLED; 500 } 501 502 /* 503 * PCM part 504 */ 505 506 static int snd_intel8x0m_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 507 { 508 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 509 struct ichdev *ichdev = get_ichdev(substream); 510 unsigned char val = 0; 511 unsigned long port = ichdev->reg_offset; 512 513 switch (cmd) { 514 case SNDRV_PCM_TRIGGER_START: 515 case SNDRV_PCM_TRIGGER_RESUME: 516 val = ICH_IOCE | ICH_STARTBM; 517 break; 518 case SNDRV_PCM_TRIGGER_STOP: 519 case SNDRV_PCM_TRIGGER_SUSPEND: 520 val = 0; 521 break; 522 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 523 val = ICH_IOCE; 524 break; 525 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 526 val = ICH_IOCE | ICH_STARTBM; 527 break; 528 default: 529 return -EINVAL; 530 } 531 iputbyte(chip, port + ICH_REG_OFF_CR, val); 532 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 533 /* wait until DMA stopped */ 534 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 535 /* reset whole DMA things */ 536 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 537 } 538 return 0; 539 } 540 541 static snd_pcm_uframes_t snd_intel8x0m_pcm_pointer(struct snd_pcm_substream *substream) 542 { 543 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 544 struct ichdev *ichdev = get_ichdev(substream); 545 size_t ptr1, ptr; 546 547 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << chip->pcm_pos_shift; 548 if (ptr1 != 0) 549 ptr = ichdev->fragsize1 - ptr1; 550 else 551 ptr = 0; 552 ptr += ichdev->position; 553 if (ptr >= ichdev->size) 554 return 0; 555 return bytes_to_frames(substream->runtime, ptr); 556 } 557 558 static int snd_intel8x0m_pcm_prepare(struct snd_pcm_substream *substream) 559 { 560 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 561 struct snd_pcm_runtime *runtime = substream->runtime; 562 struct ichdev *ichdev = get_ichdev(substream); 563 564 ichdev->physbuf = runtime->dma_addr; 565 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 566 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 567 snd_ac97_write(ichdev->ac97, AC97_LINE1_RATE, runtime->rate); 568 snd_ac97_write(ichdev->ac97, AC97_LINE1_LEVEL, 0); 569 snd_intel8x0m_setup_periods(chip, ichdev); 570 return 0; 571 } 572 573 static const struct snd_pcm_hardware snd_intel8x0m_stream = 574 { 575 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 576 SNDRV_PCM_INFO_BLOCK_TRANSFER | 577 SNDRV_PCM_INFO_MMAP_VALID | 578 SNDRV_PCM_INFO_PAUSE | 579 SNDRV_PCM_INFO_RESUME), 580 .formats = SNDRV_PCM_FMTBIT_S16_LE, 581 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT, 582 .rate_min = 8000, 583 .rate_max = 16000, 584 .channels_min = 1, 585 .channels_max = 1, 586 .buffer_bytes_max = 64 * 1024, 587 .period_bytes_min = 32, 588 .period_bytes_max = 64 * 1024, 589 .periods_min = 1, 590 .periods_max = 1024, 591 .fifo_size = 0, 592 }; 593 594 595 static int snd_intel8x0m_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 596 { 597 static const unsigned int rates[] = { 8000, 9600, 12000, 16000 }; 598 static const struct snd_pcm_hw_constraint_list hw_constraints_rates = { 599 .count = ARRAY_SIZE(rates), 600 .list = rates, 601 .mask = 0, 602 }; 603 struct snd_pcm_runtime *runtime = substream->runtime; 604 int err; 605 606 ichdev->substream = substream; 607 runtime->hw = snd_intel8x0m_stream; 608 err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, 609 &hw_constraints_rates); 610 if ( err < 0 ) 611 return err; 612 runtime->private_data = ichdev; 613 return 0; 614 } 615 616 static int snd_intel8x0m_playback_open(struct snd_pcm_substream *substream) 617 { 618 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 619 620 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMOUT]); 621 } 622 623 static int snd_intel8x0m_playback_close(struct snd_pcm_substream *substream) 624 { 625 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 626 627 chip->ichd[ICHD_MDMOUT].substream = NULL; 628 return 0; 629 } 630 631 static int snd_intel8x0m_capture_open(struct snd_pcm_substream *substream) 632 { 633 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 634 635 return snd_intel8x0m_pcm_open(substream, &chip->ichd[ICHD_MDMIN]); 636 } 637 638 static int snd_intel8x0m_capture_close(struct snd_pcm_substream *substream) 639 { 640 struct intel8x0m *chip = snd_pcm_substream_chip(substream); 641 642 chip->ichd[ICHD_MDMIN].substream = NULL; 643 return 0; 644 } 645 646 647 static const struct snd_pcm_ops snd_intel8x0m_playback_ops = { 648 .open = snd_intel8x0m_playback_open, 649 .close = snd_intel8x0m_playback_close, 650 .prepare = snd_intel8x0m_pcm_prepare, 651 .trigger = snd_intel8x0m_pcm_trigger, 652 .pointer = snd_intel8x0m_pcm_pointer, 653 }; 654 655 static const struct snd_pcm_ops snd_intel8x0m_capture_ops = { 656 .open = snd_intel8x0m_capture_open, 657 .close = snd_intel8x0m_capture_close, 658 .prepare = snd_intel8x0m_pcm_prepare, 659 .trigger = snd_intel8x0m_pcm_trigger, 660 .pointer = snd_intel8x0m_pcm_pointer, 661 }; 662 663 664 struct ich_pcm_table { 665 char *suffix; 666 const struct snd_pcm_ops *playback_ops; 667 const struct snd_pcm_ops *capture_ops; 668 size_t prealloc_size; 669 size_t prealloc_max_size; 670 int ac97_idx; 671 }; 672 673 static int snd_intel8x0m_pcm1(struct intel8x0m *chip, int device, 674 const struct ich_pcm_table *rec) 675 { 676 struct snd_pcm *pcm; 677 int err; 678 char name[32]; 679 680 if (rec->suffix) 681 sprintf(name, "Intel ICH - %s", rec->suffix); 682 else 683 strcpy(name, "Intel ICH"); 684 err = snd_pcm_new(chip->card, name, device, 685 rec->playback_ops ? 1 : 0, 686 rec->capture_ops ? 1 : 0, &pcm); 687 if (err < 0) 688 return err; 689 690 if (rec->playback_ops) 691 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 692 if (rec->capture_ops) 693 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 694 695 pcm->private_data = chip; 696 pcm->info_flags = 0; 697 pcm->dev_class = SNDRV_PCM_CLASS_MODEM; 698 if (rec->suffix) 699 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 700 else 701 strcpy(pcm->name, chip->card->shortname); 702 chip->pcm[device] = pcm; 703 704 snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV, 705 &chip->pci->dev, 706 rec->prealloc_size, 707 rec->prealloc_max_size); 708 709 return 0; 710 } 711 712 static const struct ich_pcm_table intel_pcms[] = { 713 { 714 .suffix = "Modem", 715 .playback_ops = &snd_intel8x0m_playback_ops, 716 .capture_ops = &snd_intel8x0m_capture_ops, 717 .prealloc_size = 32 * 1024, 718 .prealloc_max_size = 64 * 1024, 719 }, 720 }; 721 722 static int snd_intel8x0m_pcm(struct intel8x0m *chip) 723 { 724 int i, tblsize, device, err; 725 const struct ich_pcm_table *tbl, *rec; 726 727 #if 1 728 tbl = intel_pcms; 729 tblsize = 1; 730 #else 731 switch (chip->device_type) { 732 case DEVICE_NFORCE: 733 tbl = nforce_pcms; 734 tblsize = ARRAY_SIZE(nforce_pcms); 735 break; 736 case DEVICE_ALI: 737 tbl = ali_pcms; 738 tblsize = ARRAY_SIZE(ali_pcms); 739 break; 740 default: 741 tbl = intel_pcms; 742 tblsize = 2; 743 break; 744 } 745 #endif 746 device = 0; 747 for (i = 0; i < tblsize; i++) { 748 rec = tbl + i; 749 if (i > 0 && rec->ac97_idx) { 750 /* activate PCM only when associated AC'97 codec */ 751 if (! chip->ichd[rec->ac97_idx].ac97) 752 continue; 753 } 754 err = snd_intel8x0m_pcm1(chip, device, rec); 755 if (err < 0) 756 return err; 757 device++; 758 } 759 760 chip->pcm_devs = device; 761 return 0; 762 } 763 764 765 /* 766 * Mixer part 767 */ 768 769 static void snd_intel8x0m_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 770 { 771 struct intel8x0m *chip = bus->private_data; 772 chip->ac97_bus = NULL; 773 } 774 775 static void snd_intel8x0m_mixer_free_ac97(struct snd_ac97 *ac97) 776 { 777 struct intel8x0m *chip = ac97->private_data; 778 chip->ac97 = NULL; 779 } 780 781 782 static int snd_intel8x0m_mixer(struct intel8x0m *chip, int ac97_clock) 783 { 784 struct snd_ac97_bus *pbus; 785 struct snd_ac97_template ac97; 786 struct snd_ac97 *x97; 787 int err; 788 unsigned int glob_sta = 0; 789 static const struct snd_ac97_bus_ops ops = { 790 .write = snd_intel8x0m_codec_write, 791 .read = snd_intel8x0m_codec_read, 792 }; 793 794 chip->in_ac97_init = 1; 795 796 memset(&ac97, 0, sizeof(ac97)); 797 ac97.private_data = chip; 798 ac97.private_free = snd_intel8x0m_mixer_free_ac97; 799 ac97.scaps = AC97_SCAP_SKIP_AUDIO | AC97_SCAP_POWER_SAVE; 800 801 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 802 803 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0) 804 goto __err; 805 pbus->private_free = snd_intel8x0m_mixer_free_ac97_bus; 806 if (ac97_clock >= 8000 && ac97_clock <= 48000) 807 pbus->clock = ac97_clock; 808 chip->ac97_bus = pbus; 809 810 ac97.pci = chip->pci; 811 ac97.num = glob_sta & ICH_SCR ? 1 : 0; 812 if ((err = snd_ac97_mixer(pbus, &ac97, &x97)) < 0) { 813 dev_err(chip->card->dev, 814 "Unable to initialize codec #%d\n", ac97.num); 815 if (ac97.num == 0) 816 goto __err; 817 return err; 818 } 819 chip->ac97 = x97; 820 if(ac97_is_modem(x97) && !chip->ichd[ICHD_MDMIN].ac97) { 821 chip->ichd[ICHD_MDMIN].ac97 = x97; 822 chip->ichd[ICHD_MDMOUT].ac97 = x97; 823 } 824 825 chip->in_ac97_init = 0; 826 return 0; 827 828 __err: 829 /* clear the cold-reset bit for the next chance */ 830 if (chip->device_type != DEVICE_ALI) 831 iputdword(chip, ICHREG(GLOB_CNT), 832 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 833 return err; 834 } 835 836 837 /* 838 * 839 */ 840 841 static int snd_intel8x0m_ich_chip_init(struct intel8x0m *chip, int probing) 842 { 843 unsigned long end_time; 844 unsigned int cnt, status, nstatus; 845 846 /* put logic to right state */ 847 /* first clear status bits */ 848 status = ICH_RCS | ICH_MIINT | ICH_MOINT; 849 cnt = igetdword(chip, ICHREG(GLOB_STA)); 850 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 851 852 /* ACLink on, 2 channels */ 853 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 854 cnt &= ~(ICH_ACLINK); 855 /* finish cold or do warm reset */ 856 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 857 iputdword(chip, ICHREG(GLOB_CNT), cnt); 858 usleep_range(500, 1000); /* give warm reset some time */ 859 end_time = jiffies + HZ / 4; 860 do { 861 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 862 goto __ok; 863 schedule_timeout_uninterruptible(1); 864 } while (time_after_eq(end_time, jiffies)); 865 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", 866 igetdword(chip, ICHREG(GLOB_CNT))); 867 return -EIO; 868 869 __ok: 870 if (probing) { 871 /* wait for any codec ready status. 872 * Once it becomes ready it should remain ready 873 * as long as we do not disable the ac97 link. 874 */ 875 end_time = jiffies + HZ; 876 do { 877 status = igetdword(chip, ICHREG(GLOB_STA)) & 878 (ICH_PCR | ICH_SCR | ICH_TCR); 879 if (status) 880 break; 881 schedule_timeout_uninterruptible(1); 882 } while (time_after_eq(end_time, jiffies)); 883 if (! status) { 884 /* no codec is found */ 885 dev_err(chip->card->dev, 886 "codec_ready: codec is not ready [0x%x]\n", 887 igetdword(chip, ICHREG(GLOB_STA))); 888 return -EIO; 889 } 890 891 /* up to two codecs (modem cannot be tertiary with ICH4) */ 892 nstatus = ICH_PCR | ICH_SCR; 893 894 /* wait for other codecs ready status. */ 895 end_time = jiffies + HZ / 4; 896 while (status != nstatus && time_after_eq(end_time, jiffies)) { 897 schedule_timeout_uninterruptible(1); 898 status |= igetdword(chip, ICHREG(GLOB_STA)) & nstatus; 899 } 900 901 } else { 902 /* resume phase */ 903 status = 0; 904 if (chip->ac97) 905 status |= get_ich_codec_bit(chip, chip->ac97->num); 906 /* wait until all the probed codecs are ready */ 907 end_time = jiffies + HZ; 908 do { 909 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 910 (ICH_PCR | ICH_SCR | ICH_TCR); 911 if (status == nstatus) 912 break; 913 schedule_timeout_uninterruptible(1); 914 } while (time_after_eq(end_time, jiffies)); 915 } 916 917 if (chip->device_type == DEVICE_SIS) { 918 /* unmute the output on SIS7012 */ 919 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 920 } 921 922 return 0; 923 } 924 925 static int snd_intel8x0m_chip_init(struct intel8x0m *chip, int probing) 926 { 927 unsigned int i; 928 int err; 929 930 if ((err = snd_intel8x0m_ich_chip_init(chip, probing)) < 0) 931 return err; 932 iagetword(chip, 0); /* clear semaphore flag */ 933 934 /* disable interrupts */ 935 for (i = 0; i < chip->bdbars_count; i++) 936 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 937 /* reset channels */ 938 for (i = 0; i < chip->bdbars_count; i++) 939 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 940 /* initialize Buffer Descriptor Lists */ 941 for (i = 0; i < chip->bdbars_count; i++) 942 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, chip->ichd[i].bdbar_addr); 943 return 0; 944 } 945 946 static int snd_intel8x0m_free(struct intel8x0m *chip) 947 { 948 unsigned int i; 949 950 if (chip->irq < 0) 951 goto __hw_end; 952 /* disable interrupts */ 953 for (i = 0; i < chip->bdbars_count; i++) 954 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 955 /* reset channels */ 956 for (i = 0; i < chip->bdbars_count; i++) 957 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 958 __hw_end: 959 if (chip->irq >= 0) 960 free_irq(chip->irq, chip); 961 if (chip->bdbars.area) 962 snd_dma_free_pages(&chip->bdbars); 963 if (chip->addr) 964 pci_iounmap(chip->pci, chip->addr); 965 if (chip->bmaddr) 966 pci_iounmap(chip->pci, chip->bmaddr); 967 pci_release_regions(chip->pci); 968 pci_disable_device(chip->pci); 969 kfree(chip); 970 return 0; 971 } 972 973 #ifdef CONFIG_PM_SLEEP 974 /* 975 * power management 976 */ 977 static int intel8x0m_suspend(struct device *dev) 978 { 979 struct snd_card *card = dev_get_drvdata(dev); 980 struct intel8x0m *chip = card->private_data; 981 982 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 983 snd_ac97_suspend(chip->ac97); 984 if (chip->irq >= 0) { 985 free_irq(chip->irq, chip); 986 chip->irq = -1; 987 card->sync_irq = -1; 988 } 989 return 0; 990 } 991 992 static int intel8x0m_resume(struct device *dev) 993 { 994 struct pci_dev *pci = to_pci_dev(dev); 995 struct snd_card *card = dev_get_drvdata(dev); 996 struct intel8x0m *chip = card->private_data; 997 998 if (request_irq(pci->irq, snd_intel8x0m_interrupt, 999 IRQF_SHARED, KBUILD_MODNAME, chip)) { 1000 dev_err(dev, "unable to grab IRQ %d, disabling device\n", 1001 pci->irq); 1002 snd_card_disconnect(card); 1003 return -EIO; 1004 } 1005 chip->irq = pci->irq; 1006 card->sync_irq = chip->irq; 1007 snd_intel8x0m_chip_init(chip, 0); 1008 snd_ac97_resume(chip->ac97); 1009 1010 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1011 return 0; 1012 } 1013 1014 static SIMPLE_DEV_PM_OPS(intel8x0m_pm, intel8x0m_suspend, intel8x0m_resume); 1015 #define INTEL8X0M_PM_OPS &intel8x0m_pm 1016 #else 1017 #define INTEL8X0M_PM_OPS NULL 1018 #endif /* CONFIG_PM_SLEEP */ 1019 1020 static void snd_intel8x0m_proc_read(struct snd_info_entry * entry, 1021 struct snd_info_buffer *buffer) 1022 { 1023 struct intel8x0m *chip = entry->private_data; 1024 unsigned int tmp; 1025 1026 snd_iprintf(buffer, "Intel8x0m\n\n"); 1027 if (chip->device_type == DEVICE_ALI) 1028 return; 1029 tmp = igetdword(chip, ICHREG(GLOB_STA)); 1030 snd_iprintf(buffer, "Global control : 0x%08x\n", 1031 igetdword(chip, ICHREG(GLOB_CNT))); 1032 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 1033 snd_iprintf(buffer, "AC'97 codecs ready :%s%s%s%s\n", 1034 tmp & ICH_PCR ? " primary" : "", 1035 tmp & ICH_SCR ? " secondary" : "", 1036 tmp & ICH_TCR ? " tertiary" : "", 1037 (tmp & (ICH_PCR | ICH_SCR | ICH_TCR)) == 0 ? " none" : ""); 1038 } 1039 1040 static void snd_intel8x0m_proc_init(struct intel8x0m *chip) 1041 { 1042 snd_card_ro_proc_new(chip->card, "intel8x0m", chip, 1043 snd_intel8x0m_proc_read); 1044 } 1045 1046 static int snd_intel8x0m_dev_free(struct snd_device *device) 1047 { 1048 struct intel8x0m *chip = device->device_data; 1049 return snd_intel8x0m_free(chip); 1050 } 1051 1052 struct ich_reg_info { 1053 unsigned int int_sta_mask; 1054 unsigned int offset; 1055 }; 1056 1057 static int snd_intel8x0m_create(struct snd_card *card, 1058 struct pci_dev *pci, 1059 unsigned long device_type, 1060 struct intel8x0m **r_intel8x0m) 1061 { 1062 struct intel8x0m *chip; 1063 int err; 1064 unsigned int i; 1065 unsigned int int_sta_masks; 1066 struct ichdev *ichdev; 1067 static const struct snd_device_ops ops = { 1068 .dev_free = snd_intel8x0m_dev_free, 1069 }; 1070 static const struct ich_reg_info intel_regs[2] = { 1071 { ICH_MIINT, 0 }, 1072 { ICH_MOINT, 0x10 }, 1073 }; 1074 const struct ich_reg_info *tbl; 1075 1076 *r_intel8x0m = NULL; 1077 1078 if ((err = pci_enable_device(pci)) < 0) 1079 return err; 1080 1081 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 1082 if (chip == NULL) { 1083 pci_disable_device(pci); 1084 return -ENOMEM; 1085 } 1086 spin_lock_init(&chip->reg_lock); 1087 chip->device_type = device_type; 1088 chip->card = card; 1089 chip->pci = pci; 1090 chip->irq = -1; 1091 1092 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 1093 kfree(chip); 1094 pci_disable_device(pci); 1095 return err; 1096 } 1097 1098 if (device_type == DEVICE_ALI) { 1099 /* ALI5455 has no ac97 region */ 1100 chip->bmaddr = pci_iomap(pci, 0, 0); 1101 goto port_inited; 1102 } 1103 1104 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 1105 chip->addr = pci_iomap(pci, 2, 0); 1106 else 1107 chip->addr = pci_iomap(pci, 0, 0); 1108 if (!chip->addr) { 1109 dev_err(card->dev, "AC'97 space ioremap problem\n"); 1110 snd_intel8x0m_free(chip); 1111 return -EIO; 1112 } 1113 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 1114 chip->bmaddr = pci_iomap(pci, 3, 0); 1115 else 1116 chip->bmaddr = pci_iomap(pci, 1, 0); 1117 1118 port_inited: 1119 if (!chip->bmaddr) { 1120 dev_err(card->dev, "Controller space ioremap problem\n"); 1121 snd_intel8x0m_free(chip); 1122 return -EIO; 1123 } 1124 1125 /* initialize offsets */ 1126 chip->bdbars_count = 2; 1127 tbl = intel_regs; 1128 1129 for (i = 0; i < chip->bdbars_count; i++) { 1130 ichdev = &chip->ichd[i]; 1131 ichdev->ichd = i; 1132 ichdev->reg_offset = tbl[i].offset; 1133 ichdev->int_sta_mask = tbl[i].int_sta_mask; 1134 if (device_type == DEVICE_SIS) { 1135 /* SiS 7013 swaps the registers */ 1136 ichdev->roff_sr = ICH_REG_OFF_PICB; 1137 ichdev->roff_picb = ICH_REG_OFF_SR; 1138 } else { 1139 ichdev->roff_sr = ICH_REG_OFF_SR; 1140 ichdev->roff_picb = ICH_REG_OFF_PICB; 1141 } 1142 if (device_type == DEVICE_ALI) 1143 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 1144 } 1145 /* SIS7013 handles the pcm data in bytes, others are in words */ 1146 chip->pcm_pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 1147 1148 /* allocate buffer descriptor lists */ 1149 /* the start of each lists must be aligned to 8 bytes */ 1150 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, 1151 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 1152 &chip->bdbars) < 0) { 1153 snd_intel8x0m_free(chip); 1154 return -ENOMEM; 1155 } 1156 /* tables must be aligned to 8 bytes here, but the kernel pages 1157 are much bigger, so we don't care (on i386) */ 1158 int_sta_masks = 0; 1159 for (i = 0; i < chip->bdbars_count; i++) { 1160 ichdev = &chip->ichd[i]; 1161 ichdev->bdbar = ((__le32 *)chip->bdbars.area) + (i * ICH_MAX_FRAGS * 2); 1162 ichdev->bdbar_addr = chip->bdbars.addr + (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 1163 int_sta_masks |= ichdev->int_sta_mask; 1164 } 1165 chip->int_sta_reg = ICH_REG_GLOB_STA; 1166 chip->int_sta_mask = int_sta_masks; 1167 1168 pci_set_master(pci); 1169 1170 if ((err = snd_intel8x0m_chip_init(chip, 1)) < 0) { 1171 snd_intel8x0m_free(chip); 1172 return err; 1173 } 1174 1175 if (request_irq(pci->irq, snd_intel8x0m_interrupt, IRQF_SHARED, 1176 KBUILD_MODNAME, chip)) { 1177 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 1178 snd_intel8x0m_free(chip); 1179 return -EBUSY; 1180 } 1181 chip->irq = pci->irq; 1182 card->sync_irq = chip->irq; 1183 1184 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 1185 snd_intel8x0m_free(chip); 1186 return err; 1187 } 1188 1189 *r_intel8x0m = chip; 1190 return 0; 1191 } 1192 1193 static struct shortname_table { 1194 unsigned int id; 1195 const char *s; 1196 } shortnames[] = { 1197 { PCI_DEVICE_ID_INTEL_82801AA_6, "Intel 82801AA-ICH" }, 1198 { PCI_DEVICE_ID_INTEL_82801AB_6, "Intel 82901AB-ICH0" }, 1199 { PCI_DEVICE_ID_INTEL_82801BA_6, "Intel 82801BA-ICH2" }, 1200 { PCI_DEVICE_ID_INTEL_440MX_6, "Intel 440MX" }, 1201 { PCI_DEVICE_ID_INTEL_82801CA_6, "Intel 82801CA-ICH3" }, 1202 { PCI_DEVICE_ID_INTEL_82801DB_6, "Intel 82801DB-ICH4" }, 1203 { PCI_DEVICE_ID_INTEL_82801EB_6, "Intel ICH5" }, 1204 { PCI_DEVICE_ID_INTEL_ICH6_17, "Intel ICH6" }, 1205 { PCI_DEVICE_ID_INTEL_ICH7_19, "Intel ICH7" }, 1206 { 0x7446, "AMD AMD768" }, 1207 { PCI_DEVICE_ID_SI_7013, "SiS SI7013" }, 1208 { PCI_DEVICE_ID_NVIDIA_MCP1_MODEM, "NVidia nForce" }, 1209 { PCI_DEVICE_ID_NVIDIA_MCP2_MODEM, "NVidia nForce2" }, 1210 { PCI_DEVICE_ID_NVIDIA_MCP2S_MODEM, "NVidia nForce2s" }, 1211 { PCI_DEVICE_ID_NVIDIA_MCP3_MODEM, "NVidia nForce3" }, 1212 { 0x746e, "AMD AMD8111" }, 1213 #if 0 1214 { 0x5455, "ALi M5455" }, 1215 #endif 1216 { 0 }, 1217 }; 1218 1219 static int snd_intel8x0m_probe(struct pci_dev *pci, 1220 const struct pci_device_id *pci_id) 1221 { 1222 struct snd_card *card; 1223 struct intel8x0m *chip; 1224 int err; 1225 struct shortname_table *name; 1226 1227 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 1228 if (err < 0) 1229 return err; 1230 1231 strcpy(card->driver, "ICH-MODEM"); 1232 strcpy(card->shortname, "Intel ICH"); 1233 for (name = shortnames; name->id; name++) { 1234 if (pci->device == name->id) { 1235 strcpy(card->shortname, name->s); 1236 break; 1237 } 1238 } 1239 strcat(card->shortname," Modem"); 1240 1241 if ((err = snd_intel8x0m_create(card, pci, pci_id->driver_data, &chip)) < 0) { 1242 snd_card_free(card); 1243 return err; 1244 } 1245 card->private_data = chip; 1246 1247 if ((err = snd_intel8x0m_mixer(chip, ac97_clock)) < 0) { 1248 snd_card_free(card); 1249 return err; 1250 } 1251 if ((err = snd_intel8x0m_pcm(chip)) < 0) { 1252 snd_card_free(card); 1253 return err; 1254 } 1255 1256 snd_intel8x0m_proc_init(chip); 1257 1258 sprintf(card->longname, "%s at irq %i", 1259 card->shortname, chip->irq); 1260 1261 if ((err = snd_card_register(card)) < 0) { 1262 snd_card_free(card); 1263 return err; 1264 } 1265 pci_set_drvdata(pci, card); 1266 return 0; 1267 } 1268 1269 static void snd_intel8x0m_remove(struct pci_dev *pci) 1270 { 1271 snd_card_free(pci_get_drvdata(pci)); 1272 } 1273 1274 static struct pci_driver intel8x0m_driver = { 1275 .name = KBUILD_MODNAME, 1276 .id_table = snd_intel8x0m_ids, 1277 .probe = snd_intel8x0m_probe, 1278 .remove = snd_intel8x0m_remove, 1279 .driver = { 1280 .pm = INTEL8X0M_PM_OPS, 1281 }, 1282 }; 1283 1284 module_pci_driver(intel8x0m_driver); 1285