1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for Intel ICH (i8x0) chipsets 4 * 5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 12 */ 13 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 #include <linux/init.h> 18 #include <linux/pci.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/ac97_codec.h> 24 #include <sound/info.h> 25 #include <sound/initval.h> 26 27 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 29 MODULE_LICENSE("GPL"); 30 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 31 "{Intel,82901AB-ICH0}," 32 "{Intel,82801BA-ICH2}," 33 "{Intel,82801CA-ICH3}," 34 "{Intel,82801DB-ICH4}," 35 "{Intel,ICH5}," 36 "{Intel,ICH6}," 37 "{Intel,ICH7}," 38 "{Intel,6300ESB}," 39 "{Intel,ESB2}," 40 "{Intel,MX440}," 41 "{SiS,SI7012}," 42 "{NVidia,nForce Audio}," 43 "{NVidia,nForce2 Audio}," 44 "{NVidia,nForce3 Audio}," 45 "{NVidia,MCP04}," 46 "{NVidia,MCP501}," 47 "{NVidia,CK804}," 48 "{NVidia,CK8}," 49 "{NVidia,CK8S}," 50 "{AMD,AMD768}," 51 "{AMD,AMD8111}," 52 "{ALI,M5455}}"); 53 54 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 55 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 56 static int ac97_clock; 57 static char *ac97_quirk; 58 static bool buggy_semaphore; 59 static int buggy_irq = -1; /* auto-check */ 60 static bool xbox; 61 static int spdif_aclink = -1; 62 static int inside_vm = -1; 63 64 module_param(index, int, 0444); 65 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 66 module_param(id, charp, 0444); 67 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 68 module_param(ac97_clock, int, 0444); 69 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = whitelist + auto-detect, 1 = force autodetect)."); 70 module_param(ac97_quirk, charp, 0444); 71 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 72 module_param(buggy_semaphore, bool, 0444); 73 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 74 module_param(buggy_irq, bint, 0444); 75 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 76 module_param(xbox, bool, 0444); 77 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 78 module_param(spdif_aclink, int, 0444); 79 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 80 module_param(inside_vm, bint, 0444); 81 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization."); 82 83 /* just for backward compatibility */ 84 static bool enable; 85 module_param(enable, bool, 0444); 86 static int joystick; 87 module_param(joystick, int, 0444); 88 89 /* 90 * Direct registers 91 */ 92 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 93 94 #define ICHREG(x) ICH_REG_##x 95 96 #define DEFINE_REGSET(name,base) \ 97 enum { \ 98 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 99 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 100 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 101 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 102 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 103 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 104 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 105 }; 106 107 /* busmaster blocks */ 108 DEFINE_REGSET(OFF, 0); /* offset */ 109 DEFINE_REGSET(PI, 0x00); /* PCM in */ 110 DEFINE_REGSET(PO, 0x10); /* PCM out */ 111 DEFINE_REGSET(MC, 0x20); /* Mic in */ 112 113 /* ICH4 busmaster blocks */ 114 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 115 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 116 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 117 118 /* values for each busmaster block */ 119 120 /* LVI */ 121 #define ICH_REG_LVI_MASK 0x1f 122 123 /* SR */ 124 #define ICH_FIFOE 0x10 /* FIFO error */ 125 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 126 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 127 #define ICH_CELV 0x02 /* current equals last valid */ 128 #define ICH_DCH 0x01 /* DMA controller halted */ 129 130 /* PIV */ 131 #define ICH_REG_PIV_MASK 0x1f /* mask */ 132 133 /* CR */ 134 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 135 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 136 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 137 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 138 #define ICH_STARTBM 0x01 /* start busmaster operation */ 139 140 141 /* global block */ 142 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 143 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 144 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 145 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 146 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 147 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 148 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 149 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ 150 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ 151 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 152 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 153 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 154 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 155 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 156 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 157 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 158 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 159 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 160 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 161 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 162 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 163 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 164 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 165 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 166 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 167 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 168 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 169 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 170 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 171 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 172 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 173 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 174 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 175 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 176 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 177 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 178 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 179 #define ICH_RCS 0x00008000 /* read completion status */ 180 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 181 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 182 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 183 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 184 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 185 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 186 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 187 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 188 #define ICH_POINT 0x00000040 /* playback interrupt */ 189 #define ICH_PIINT 0x00000020 /* capture interrupt */ 190 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 191 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 192 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 193 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 194 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 195 #define ICH_CAS 0x01 /* codec access semaphore */ 196 #define ICH_REG_SDM 0x80 197 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 198 #define ICH_DI2L_SHIFT 6 199 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 200 #define ICH_DI1L_SHIFT 4 201 #define ICH_SE 0x00000008 /* steer enable */ 202 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 203 204 #define ICH_MAX_FRAGS 32 /* max hw frags */ 205 206 207 /* 208 * registers for Ali5455 209 */ 210 211 /* ALi 5455 busmaster blocks */ 212 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 213 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 214 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 215 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 216 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 217 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 218 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 219 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 220 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 221 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 222 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 223 224 enum { 225 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 226 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 227 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 228 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 229 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 230 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 231 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 232 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 233 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 234 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 235 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 236 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 237 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 238 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 239 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 240 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 241 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 242 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 243 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 244 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 245 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 246 }; 247 248 #define ALI_CAS_SEM_BUSY 0x80000000 249 #define ALI_CPR_ADDR_SECONDARY 0x100 250 #define ALI_CPR_ADDR_READ 0x80 251 #define ALI_CSPSR_CODEC_READY 0x08 252 #define ALI_CSPSR_READ_OK 0x02 253 #define ALI_CSPSR_WRITE_OK 0x01 254 255 /* interrupts for the whole chip by interrupt status register finish */ 256 257 #define ALI_INT_MICIN2 (1<<26) 258 #define ALI_INT_PCMIN2 (1<<25) 259 #define ALI_INT_I2SIN (1<<24) 260 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 261 #define ALI_INT_SPDIFIN (1<<22) 262 #define ALI_INT_LFEOUT (1<<21) 263 #define ALI_INT_CENTEROUT (1<<20) 264 #define ALI_INT_CODECSPDIFOUT (1<<19) 265 #define ALI_INT_MICIN (1<<18) 266 #define ALI_INT_PCMOUT (1<<17) 267 #define ALI_INT_PCMIN (1<<16) 268 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 269 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 270 #define ALI_INT_GPIO (1<<1) 271 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ 272 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 273 274 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 275 #define ICH_ALI_SC_AC97_DBL (1<<30) 276 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 277 #define ICH_ALI_SC_IN_BITS (3<<18) 278 #define ICH_ALI_SC_OUT_BITS (3<<16) 279 #define ICH_ALI_SC_6CH_CFG (3<<14) 280 #define ICH_ALI_SC_PCM_4 (1<<8) 281 #define ICH_ALI_SC_PCM_6 (2<<8) 282 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 283 284 #define ICH_ALI_SS_SEC_ID (3<<5) 285 #define ICH_ALI_SS_PRI_ID (3<<3) 286 287 #define ICH_ALI_IF_AC97SP (1<<21) 288 #define ICH_ALI_IF_MC (1<<20) 289 #define ICH_ALI_IF_PI (1<<19) 290 #define ICH_ALI_IF_MC2 (1<<18) 291 #define ICH_ALI_IF_PI2 (1<<17) 292 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 293 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 294 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 295 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 296 #define ICH_ALI_IF_PO_SPDF (1<<3) 297 #define ICH_ALI_IF_PO (1<<1) 298 299 /* 300 * 301 */ 302 303 enum { 304 ICHD_PCMIN, 305 ICHD_PCMOUT, 306 ICHD_MIC, 307 ICHD_MIC2, 308 ICHD_PCM2IN, 309 ICHD_SPBAR, 310 ICHD_LAST = ICHD_SPBAR 311 }; 312 enum { 313 NVD_PCMIN, 314 NVD_PCMOUT, 315 NVD_MIC, 316 NVD_SPBAR, 317 NVD_LAST = NVD_SPBAR 318 }; 319 enum { 320 ALID_PCMIN, 321 ALID_PCMOUT, 322 ALID_MIC, 323 ALID_AC97SPDIFOUT, 324 ALID_SPDIFIN, 325 ALID_SPDIFOUT, 326 ALID_LAST = ALID_SPDIFOUT 327 }; 328 329 #define get_ichdev(substream) (substream->runtime->private_data) 330 331 struct ichdev { 332 unsigned int ichd; /* ich device number */ 333 unsigned long reg_offset; /* offset to bmaddr */ 334 __le32 *bdbar; /* CPU address (32bit) */ 335 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 336 struct snd_pcm_substream *substream; 337 unsigned int physbuf; /* physical address (32bit) */ 338 unsigned int size; 339 unsigned int fragsize; 340 unsigned int fragsize1; 341 unsigned int position; 342 unsigned int pos_shift; 343 unsigned int last_pos; 344 int frags; 345 int lvi; 346 int lvi_frag; 347 int civ; 348 int ack; 349 int ack_reload; 350 unsigned int ack_bit; 351 unsigned int roff_sr; 352 unsigned int roff_picb; 353 unsigned int int_sta_mask; /* interrupt status mask */ 354 unsigned int ali_slot; /* ALI DMA slot */ 355 struct ac97_pcm *pcm; 356 int pcm_open_flag; 357 unsigned int suspended: 1; 358 }; 359 360 struct intel8x0 { 361 unsigned int device_type; 362 363 int irq; 364 365 void __iomem *addr; 366 void __iomem *bmaddr; 367 368 struct pci_dev *pci; 369 struct snd_card *card; 370 371 int pcm_devs; 372 struct snd_pcm *pcm[6]; 373 struct ichdev ichd[6]; 374 375 unsigned multi4: 1, 376 multi6: 1, 377 multi8 :1, 378 dra: 1, 379 smp20bit: 1; 380 unsigned in_ac97_init: 1, 381 in_sdin_init: 1; 382 unsigned in_measurement: 1; /* during ac97 clock measurement */ 383 unsigned fix_nocache: 1; /* workaround for 440MX */ 384 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 385 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 386 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ 387 unsigned inside_vm: 1; /* enable VM optimization */ 388 389 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 390 unsigned int sdm_saved; /* SDM reg value */ 391 392 struct snd_ac97_bus *ac97_bus; 393 struct snd_ac97 *ac97[3]; 394 unsigned int ac97_sdin[3]; 395 unsigned int max_codecs, ncodecs; 396 unsigned int *codec_bit; 397 unsigned int codec_isr_bits; 398 unsigned int codec_ready_bits; 399 400 spinlock_t reg_lock; 401 402 u32 bdbars_count; 403 struct snd_dma_buffer bdbars; 404 u32 int_sta_reg; /* interrupt status register */ 405 u32 int_sta_mask; /* interrupt status mask */ 406 }; 407 408 static const struct pci_device_id snd_intel8x0_ids[] = { 409 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */ 410 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */ 411 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */ 412 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */ 413 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */ 414 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */ 415 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */ 416 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */ 417 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */ 418 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */ 419 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */ 420 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */ 421 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */ 422 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */ 423 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */ 424 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */ 425 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */ 426 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */ 427 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */ 428 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */ 429 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */ 430 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */ 431 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 432 { 0, } 433 }; 434 435 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 436 437 /* 438 * Lowlevel I/O - busmaster 439 */ 440 441 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) 442 { 443 return ioread8(chip->bmaddr + offset); 444 } 445 446 static inline u16 igetword(struct intel8x0 *chip, u32 offset) 447 { 448 return ioread16(chip->bmaddr + offset); 449 } 450 451 static inline u32 igetdword(struct intel8x0 *chip, u32 offset) 452 { 453 return ioread32(chip->bmaddr + offset); 454 } 455 456 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) 457 { 458 iowrite8(val, chip->bmaddr + offset); 459 } 460 461 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) 462 { 463 iowrite16(val, chip->bmaddr + offset); 464 } 465 466 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) 467 { 468 iowrite32(val, chip->bmaddr + offset); 469 } 470 471 /* 472 * Lowlevel I/O - AC'97 registers 473 */ 474 475 static inline u16 iagetword(struct intel8x0 *chip, u32 offset) 476 { 477 return ioread16(chip->addr + offset); 478 } 479 480 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) 481 { 482 iowrite16(val, chip->addr + offset); 483 } 484 485 /* 486 * Basic I/O 487 */ 488 489 /* 490 * access to AC97 codec via normal i/o (for ICH and SIS7012) 491 */ 492 493 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 494 { 495 int time; 496 497 if (codec > 2) 498 return -EIO; 499 if (chip->in_sdin_init) { 500 /* we don't know the ready bit assignment at the moment */ 501 /* so we check any */ 502 codec = chip->codec_isr_bits; 503 } else { 504 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 505 } 506 507 /* codec ready ? */ 508 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 509 return -EIO; 510 511 if (chip->buggy_semaphore) 512 return 0; /* just ignore ... */ 513 514 /* Anyone holding a semaphore for 1 msec should be shot... */ 515 time = 100; 516 do { 517 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 518 return 0; 519 udelay(10); 520 } while (time--); 521 522 /* access to some forbidden (non existent) ac97 registers will not 523 * reset the semaphore. So even if you don't get the semaphore, still 524 * continue the access. We don't need the semaphore anyway. */ 525 dev_err(chip->card->dev, 526 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 527 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 528 iagetword(chip, 0); /* clear semaphore flag */ 529 /* I don't care about the semaphore */ 530 return -EBUSY; 531 } 532 533 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 534 unsigned short reg, 535 unsigned short val) 536 { 537 struct intel8x0 *chip = ac97->private_data; 538 539 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 540 if (! chip->in_ac97_init) 541 dev_err(chip->card->dev, 542 "codec_write %d: semaphore is not ready for register 0x%x\n", 543 ac97->num, reg); 544 } 545 iaputword(chip, reg + ac97->num * 0x80, val); 546 } 547 548 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 549 unsigned short reg) 550 { 551 struct intel8x0 *chip = ac97->private_data; 552 unsigned short res; 553 unsigned int tmp; 554 555 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 556 if (! chip->in_ac97_init) 557 dev_err(chip->card->dev, 558 "codec_read %d: semaphore is not ready for register 0x%x\n", 559 ac97->num, reg); 560 res = 0xffff; 561 } else { 562 res = iagetword(chip, reg + ac97->num * 0x80); 563 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 564 /* reset RCS and preserve other R/WC bits */ 565 iputdword(chip, ICHREG(GLOB_STA), tmp & 566 ~(chip->codec_ready_bits | ICH_GSCI)); 567 if (! chip->in_ac97_init) 568 dev_err(chip->card->dev, 569 "codec_read %d: read timeout for register 0x%x\n", 570 ac97->num, reg); 571 res = 0xffff; 572 } 573 } 574 return res; 575 } 576 577 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, 578 unsigned int codec) 579 { 580 unsigned int tmp; 581 582 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 583 iagetword(chip, codec * 0x80); 584 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 585 /* reset RCS and preserve other R/WC bits */ 586 iputdword(chip, ICHREG(GLOB_STA), tmp & 587 ~(chip->codec_ready_bits | ICH_GSCI)); 588 } 589 } 590 } 591 592 /* 593 * access to AC97 for Ali5455 594 */ 595 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) 596 { 597 int count = 0; 598 for (count = 0; count < 0x7f; count++) { 599 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 600 if (val & mask) 601 return 0; 602 } 603 if (! chip->in_ac97_init) 604 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n"); 605 return -EBUSY; 606 } 607 608 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) 609 { 610 int time = 100; 611 if (chip->buggy_semaphore) 612 return 0; /* just ignore ... */ 613 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 614 udelay(1); 615 if (! time && ! chip->in_ac97_init) 616 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n"); 617 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 618 } 619 620 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) 621 { 622 struct intel8x0 *chip = ac97->private_data; 623 unsigned short data = 0xffff; 624 625 if (snd_intel8x0_ali_codec_semaphore(chip)) 626 goto __err; 627 reg |= ALI_CPR_ADDR_READ; 628 if (ac97->num) 629 reg |= ALI_CPR_ADDR_SECONDARY; 630 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 631 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 632 goto __err; 633 data = igetword(chip, ICHREG(ALI_SPR)); 634 __err: 635 return data; 636 } 637 638 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, 639 unsigned short val) 640 { 641 struct intel8x0 *chip = ac97->private_data; 642 643 if (snd_intel8x0_ali_codec_semaphore(chip)) 644 return; 645 iputword(chip, ICHREG(ALI_CPR), val); 646 if (ac97->num) 647 reg |= ALI_CPR_ADDR_SECONDARY; 648 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 649 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 650 } 651 652 653 /* 654 * DMA I/O 655 */ 656 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 657 { 658 int idx; 659 __le32 *bdbar = ichdev->bdbar; 660 unsigned long port = ichdev->reg_offset; 661 662 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 663 if (ichdev->size == ichdev->fragsize) { 664 ichdev->ack_reload = ichdev->ack = 2; 665 ichdev->fragsize1 = ichdev->fragsize >> 1; 666 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 667 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 668 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 669 ichdev->fragsize1 >> ichdev->pos_shift); 670 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 671 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 672 ichdev->fragsize1 >> ichdev->pos_shift); 673 } 674 ichdev->frags = 2; 675 } else { 676 ichdev->ack_reload = ichdev->ack = 1; 677 ichdev->fragsize1 = ichdev->fragsize; 678 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 679 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + 680 (((idx >> 1) * ichdev->fragsize) % 681 ichdev->size)); 682 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 683 ichdev->fragsize >> ichdev->pos_shift); 684 #if 0 685 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", 686 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 687 #endif 688 } 689 ichdev->frags = ichdev->size / ichdev->fragsize; 690 } 691 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 692 ichdev->civ = 0; 693 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 694 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 695 ichdev->position = 0; 696 #if 0 697 dev_dbg(chip->card->dev, 698 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 699 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, 700 ichdev->fragsize1); 701 #endif 702 /* clear interrupts */ 703 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 704 } 705 706 /* 707 * Interrupt handler 708 */ 709 710 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) 711 { 712 unsigned long port = ichdev->reg_offset; 713 unsigned long flags; 714 int status, civ, i, step; 715 int ack = 0; 716 717 spin_lock_irqsave(&chip->reg_lock, flags); 718 status = igetbyte(chip, port + ichdev->roff_sr); 719 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 720 if (!(status & ICH_BCIS)) { 721 step = 0; 722 } else if (civ == ichdev->civ) { 723 // snd_printd("civ same %d\n", civ); 724 step = 1; 725 ichdev->civ++; 726 ichdev->civ &= ICH_REG_LVI_MASK; 727 } else { 728 step = civ - ichdev->civ; 729 if (step < 0) 730 step += ICH_REG_LVI_MASK + 1; 731 // if (step != 1) 732 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 733 ichdev->civ = civ; 734 } 735 736 ichdev->position += step * ichdev->fragsize1; 737 if (! chip->in_measurement) 738 ichdev->position %= ichdev->size; 739 ichdev->lvi += step; 740 ichdev->lvi &= ICH_REG_LVI_MASK; 741 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 742 for (i = 0; i < step; i++) { 743 ichdev->lvi_frag++; 744 ichdev->lvi_frag %= ichdev->frags; 745 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 746 #if 0 747 dev_dbg(chip->card->dev, 748 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 749 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 750 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 751 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 752 #endif 753 if (--ichdev->ack == 0) { 754 ichdev->ack = ichdev->ack_reload; 755 ack = 1; 756 } 757 } 758 spin_unlock_irqrestore(&chip->reg_lock, flags); 759 if (ack && ichdev->substream) { 760 snd_pcm_period_elapsed(ichdev->substream); 761 } 762 iputbyte(chip, port + ichdev->roff_sr, 763 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 764 } 765 766 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 767 { 768 struct intel8x0 *chip = dev_id; 769 struct ichdev *ichdev; 770 unsigned int status; 771 unsigned int i; 772 773 status = igetdword(chip, chip->int_sta_reg); 774 if (status == 0xffffffff) /* we are not yet resumed */ 775 return IRQ_NONE; 776 777 if ((status & chip->int_sta_mask) == 0) { 778 if (status) { 779 /* ack */ 780 iputdword(chip, chip->int_sta_reg, status); 781 if (! chip->buggy_irq) 782 status = 0; 783 } 784 return IRQ_RETVAL(status); 785 } 786 787 for (i = 0; i < chip->bdbars_count; i++) { 788 ichdev = &chip->ichd[i]; 789 if (status & ichdev->int_sta_mask) 790 snd_intel8x0_update(chip, ichdev); 791 } 792 793 /* ack them */ 794 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 795 796 return IRQ_HANDLED; 797 } 798 799 /* 800 * PCM part 801 */ 802 803 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 804 { 805 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 806 struct ichdev *ichdev = get_ichdev(substream); 807 unsigned char val = 0; 808 unsigned long port = ichdev->reg_offset; 809 810 switch (cmd) { 811 case SNDRV_PCM_TRIGGER_RESUME: 812 ichdev->suspended = 0; 813 /* fall through */ 814 case SNDRV_PCM_TRIGGER_START: 815 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 816 val = ICH_IOCE | ICH_STARTBM; 817 ichdev->last_pos = ichdev->position; 818 break; 819 case SNDRV_PCM_TRIGGER_SUSPEND: 820 ichdev->suspended = 1; 821 /* fall through */ 822 case SNDRV_PCM_TRIGGER_STOP: 823 val = 0; 824 break; 825 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 826 val = ICH_IOCE; 827 break; 828 default: 829 return -EINVAL; 830 } 831 iputbyte(chip, port + ICH_REG_OFF_CR, val); 832 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 833 /* wait until DMA stopped */ 834 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 835 /* reset whole DMA things */ 836 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 837 } 838 return 0; 839 } 840 841 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) 842 { 843 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 844 struct ichdev *ichdev = get_ichdev(substream); 845 unsigned long port = ichdev->reg_offset; 846 static int fiforeg[] = { 847 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) 848 }; 849 unsigned int val, fifo; 850 851 val = igetdword(chip, ICHREG(ALI_DMACR)); 852 switch (cmd) { 853 case SNDRV_PCM_TRIGGER_RESUME: 854 ichdev->suspended = 0; 855 /* fall through */ 856 case SNDRV_PCM_TRIGGER_START: 857 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 858 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 859 /* clear FIFO for synchronization of channels */ 860 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 861 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 862 fifo |= 0x83 << (ichdev->ali_slot % 4); 863 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 864 } 865 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 866 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 867 /* start DMA */ 868 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); 869 break; 870 case SNDRV_PCM_TRIGGER_SUSPEND: 871 ichdev->suspended = 1; 872 /* fall through */ 873 case SNDRV_PCM_TRIGGER_STOP: 874 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 875 /* pause */ 876 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); 877 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 878 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 879 ; 880 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 881 break; 882 /* reset whole DMA things */ 883 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 884 /* clear interrupts */ 885 iputbyte(chip, port + ICH_REG_OFF_SR, 886 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 887 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 888 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 889 break; 890 default: 891 return -EINVAL; 892 } 893 return 0; 894 } 895 896 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 897 struct snd_pcm_hw_params *hw_params) 898 { 899 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 900 struct ichdev *ichdev = get_ichdev(substream); 901 int dbl = params_rate(hw_params) > 48000; 902 int err; 903 904 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 905 if (err < 0) 906 return err; 907 if (ichdev->pcm_open_flag) { 908 snd_ac97_pcm_close(ichdev->pcm); 909 ichdev->pcm_open_flag = 0; 910 } 911 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 912 params_channels(hw_params), 913 ichdev->pcm->r[dbl].slots); 914 if (err >= 0) { 915 ichdev->pcm_open_flag = 1; 916 /* Force SPDIF setting */ 917 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 918 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, 919 params_rate(hw_params)); 920 } 921 return err; 922 } 923 924 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 925 { 926 struct ichdev *ichdev = get_ichdev(substream); 927 928 if (ichdev->pcm_open_flag) { 929 snd_ac97_pcm_close(ichdev->pcm); 930 ichdev->pcm_open_flag = 0; 931 } 932 return snd_pcm_lib_free_pages(substream); 933 } 934 935 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, 936 struct snd_pcm_runtime *runtime) 937 { 938 unsigned int cnt; 939 int dbl = runtime->rate > 48000; 940 941 spin_lock_irq(&chip->reg_lock); 942 switch (chip->device_type) { 943 case DEVICE_ALI: 944 cnt = igetdword(chip, ICHREG(ALI_SCR)); 945 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 946 if (runtime->channels == 4 || dbl) 947 cnt |= ICH_ALI_SC_PCM_4; 948 else if (runtime->channels == 6) 949 cnt |= ICH_ALI_SC_PCM_6; 950 iputdword(chip, ICHREG(ALI_SCR), cnt); 951 break; 952 case DEVICE_SIS: 953 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 954 cnt &= ~ICH_SIS_PCM_246_MASK; 955 if (runtime->channels == 4 || dbl) 956 cnt |= ICH_SIS_PCM_4; 957 else if (runtime->channels == 6) 958 cnt |= ICH_SIS_PCM_6; 959 iputdword(chip, ICHREG(GLOB_CNT), cnt); 960 break; 961 default: 962 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 963 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 964 if (runtime->channels == 4 || dbl) 965 cnt |= ICH_PCM_4; 966 else if (runtime->channels == 6) 967 cnt |= ICH_PCM_6; 968 else if (runtime->channels == 8) 969 cnt |= ICH_PCM_8; 970 if (chip->device_type == DEVICE_NFORCE) { 971 /* reset to 2ch once to keep the 6 channel data in alignment, 972 * to start from Front Left always 973 */ 974 if (cnt & ICH_PCM_246_MASK) { 975 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 976 spin_unlock_irq(&chip->reg_lock); 977 msleep(50); /* grrr... */ 978 spin_lock_irq(&chip->reg_lock); 979 } 980 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 981 if (runtime->sample_bits > 16) 982 cnt |= ICH_PCM_20BIT; 983 } 984 iputdword(chip, ICHREG(GLOB_CNT), cnt); 985 break; 986 } 987 spin_unlock_irq(&chip->reg_lock); 988 } 989 990 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) 991 { 992 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 993 struct snd_pcm_runtime *runtime = substream->runtime; 994 struct ichdev *ichdev = get_ichdev(substream); 995 996 ichdev->physbuf = runtime->dma_addr; 997 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 998 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 999 if (ichdev->ichd == ICHD_PCMOUT) { 1000 snd_intel8x0_setup_pcm_out(chip, runtime); 1001 if (chip->device_type == DEVICE_INTEL_ICH4) 1002 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1003 } 1004 snd_intel8x0_setup_periods(chip, ichdev); 1005 return 0; 1006 } 1007 1008 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 1009 { 1010 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1011 struct ichdev *ichdev = get_ichdev(substream); 1012 size_t ptr1, ptr; 1013 int civ, timeout = 10; 1014 unsigned int position; 1015 1016 spin_lock(&chip->reg_lock); 1017 do { 1018 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1019 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1020 position = ichdev->position; 1021 if (ptr1 == 0) { 1022 udelay(10); 1023 continue; 1024 } 1025 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) 1026 continue; 1027 1028 /* IO read operation is very expensive inside virtual machine 1029 * as it is emulated. The probability that subsequent PICB read 1030 * will return different result is high enough to loop till 1031 * timeout here. 1032 * Same CIV is strict enough condition to be sure that PICB 1033 * is valid inside VM on emulated card. */ 1034 if (chip->inside_vm) 1035 break; 1036 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1037 break; 1038 } while (timeout--); 1039 ptr = ichdev->last_pos; 1040 if (ptr1 != 0) { 1041 ptr1 <<= ichdev->pos_shift; 1042 ptr = ichdev->fragsize1 - ptr1; 1043 ptr += position; 1044 if (ptr < ichdev->last_pos) { 1045 unsigned int pos_base, last_base; 1046 pos_base = position / ichdev->fragsize1; 1047 last_base = ichdev->last_pos / ichdev->fragsize1; 1048 /* another sanity check; ptr1 can go back to full 1049 * before the base position is updated 1050 */ 1051 if (pos_base == last_base) 1052 ptr = ichdev->last_pos; 1053 } 1054 } 1055 ichdev->last_pos = ptr; 1056 spin_unlock(&chip->reg_lock); 1057 if (ptr >= ichdev->size) 1058 return 0; 1059 return bytes_to_frames(substream->runtime, ptr); 1060 } 1061 1062 static const struct snd_pcm_hardware snd_intel8x0_stream = 1063 { 1064 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1065 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1066 SNDRV_PCM_INFO_MMAP_VALID | 1067 SNDRV_PCM_INFO_PAUSE | 1068 SNDRV_PCM_INFO_RESUME), 1069 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1070 .rates = SNDRV_PCM_RATE_48000, 1071 .rate_min = 48000, 1072 .rate_max = 48000, 1073 .channels_min = 2, 1074 .channels_max = 2, 1075 .buffer_bytes_max = 128 * 1024, 1076 .period_bytes_min = 32, 1077 .period_bytes_max = 128 * 1024, 1078 .periods_min = 1, 1079 .periods_max = 1024, 1080 .fifo_size = 0, 1081 }; 1082 1083 static const unsigned int channels4[] = { 1084 2, 4, 1085 }; 1086 1087 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { 1088 .count = ARRAY_SIZE(channels4), 1089 .list = channels4, 1090 .mask = 0, 1091 }; 1092 1093 static const unsigned int channels6[] = { 1094 2, 4, 6, 1095 }; 1096 1097 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { 1098 .count = ARRAY_SIZE(channels6), 1099 .list = channels6, 1100 .mask = 0, 1101 }; 1102 1103 static const unsigned int channels8[] = { 1104 2, 4, 6, 8, 1105 }; 1106 1107 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = { 1108 .count = ARRAY_SIZE(channels8), 1109 .list = channels8, 1110 .mask = 0, 1111 }; 1112 1113 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 1114 { 1115 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1116 struct snd_pcm_runtime *runtime = substream->runtime; 1117 int err; 1118 1119 ichdev->substream = substream; 1120 runtime->hw = snd_intel8x0_stream; 1121 runtime->hw.rates = ichdev->pcm->rates; 1122 snd_pcm_limit_hw_rates(runtime); 1123 if (chip->device_type == DEVICE_SIS) { 1124 runtime->hw.buffer_bytes_max = 64*1024; 1125 runtime->hw.period_bytes_max = 64*1024; 1126 } 1127 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1128 return err; 1129 runtime->private_data = ichdev; 1130 return 0; 1131 } 1132 1133 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) 1134 { 1135 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1136 struct snd_pcm_runtime *runtime = substream->runtime; 1137 int err; 1138 1139 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1140 if (err < 0) 1141 return err; 1142 1143 if (chip->multi8) { 1144 runtime->hw.channels_max = 8; 1145 snd_pcm_hw_constraint_list(runtime, 0, 1146 SNDRV_PCM_HW_PARAM_CHANNELS, 1147 &hw_constraints_channels8); 1148 } else if (chip->multi6) { 1149 runtime->hw.channels_max = 6; 1150 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1151 &hw_constraints_channels6); 1152 } else if (chip->multi4) { 1153 runtime->hw.channels_max = 4; 1154 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1155 &hw_constraints_channels4); 1156 } 1157 if (chip->dra) { 1158 snd_ac97_pcm_double_rate_rules(runtime); 1159 } 1160 if (chip->smp20bit) { 1161 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1162 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1163 } 1164 return 0; 1165 } 1166 1167 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) 1168 { 1169 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1170 1171 chip->ichd[ICHD_PCMOUT].substream = NULL; 1172 return 0; 1173 } 1174 1175 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) 1176 { 1177 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1178 1179 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1180 } 1181 1182 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) 1183 { 1184 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1185 1186 chip->ichd[ICHD_PCMIN].substream = NULL; 1187 return 0; 1188 } 1189 1190 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) 1191 { 1192 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1193 1194 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1195 } 1196 1197 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) 1198 { 1199 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1200 1201 chip->ichd[ICHD_MIC].substream = NULL; 1202 return 0; 1203 } 1204 1205 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) 1206 { 1207 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1208 1209 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1210 } 1211 1212 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) 1213 { 1214 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1215 1216 chip->ichd[ICHD_MIC2].substream = NULL; 1217 return 0; 1218 } 1219 1220 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) 1221 { 1222 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1223 1224 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1225 } 1226 1227 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) 1228 { 1229 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1230 1231 chip->ichd[ICHD_PCM2IN].substream = NULL; 1232 return 0; 1233 } 1234 1235 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) 1236 { 1237 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1238 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1239 1240 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1241 } 1242 1243 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) 1244 { 1245 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1246 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1247 1248 chip->ichd[idx].substream = NULL; 1249 return 0; 1250 } 1251 1252 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) 1253 { 1254 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1255 unsigned int val; 1256 1257 spin_lock_irq(&chip->reg_lock); 1258 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1259 val |= ICH_ALI_IF_AC97SP; 1260 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1261 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1262 spin_unlock_irq(&chip->reg_lock); 1263 1264 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1265 } 1266 1267 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) 1268 { 1269 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1270 unsigned int val; 1271 1272 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1273 spin_lock_irq(&chip->reg_lock); 1274 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1275 val &= ~ICH_ALI_IF_AC97SP; 1276 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1277 spin_unlock_irq(&chip->reg_lock); 1278 1279 return 0; 1280 } 1281 1282 #if 0 // NYI 1283 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) 1284 { 1285 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1286 1287 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1288 } 1289 1290 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) 1291 { 1292 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1293 1294 chip->ichd[ALID_SPDIFIN].substream = NULL; 1295 return 0; 1296 } 1297 1298 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) 1299 { 1300 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1301 1302 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1303 } 1304 1305 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) 1306 { 1307 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1308 1309 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1310 return 0; 1311 } 1312 #endif 1313 1314 static const struct snd_pcm_ops snd_intel8x0_playback_ops = { 1315 .open = snd_intel8x0_playback_open, 1316 .close = snd_intel8x0_playback_close, 1317 .ioctl = snd_pcm_lib_ioctl, 1318 .hw_params = snd_intel8x0_hw_params, 1319 .hw_free = snd_intel8x0_hw_free, 1320 .prepare = snd_intel8x0_pcm_prepare, 1321 .trigger = snd_intel8x0_pcm_trigger, 1322 .pointer = snd_intel8x0_pcm_pointer, 1323 }; 1324 1325 static const struct snd_pcm_ops snd_intel8x0_capture_ops = { 1326 .open = snd_intel8x0_capture_open, 1327 .close = snd_intel8x0_capture_close, 1328 .ioctl = snd_pcm_lib_ioctl, 1329 .hw_params = snd_intel8x0_hw_params, 1330 .hw_free = snd_intel8x0_hw_free, 1331 .prepare = snd_intel8x0_pcm_prepare, 1332 .trigger = snd_intel8x0_pcm_trigger, 1333 .pointer = snd_intel8x0_pcm_pointer, 1334 }; 1335 1336 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { 1337 .open = snd_intel8x0_mic_open, 1338 .close = snd_intel8x0_mic_close, 1339 .ioctl = snd_pcm_lib_ioctl, 1340 .hw_params = snd_intel8x0_hw_params, 1341 .hw_free = snd_intel8x0_hw_free, 1342 .prepare = snd_intel8x0_pcm_prepare, 1343 .trigger = snd_intel8x0_pcm_trigger, 1344 .pointer = snd_intel8x0_pcm_pointer, 1345 }; 1346 1347 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { 1348 .open = snd_intel8x0_mic2_open, 1349 .close = snd_intel8x0_mic2_close, 1350 .ioctl = snd_pcm_lib_ioctl, 1351 .hw_params = snd_intel8x0_hw_params, 1352 .hw_free = snd_intel8x0_hw_free, 1353 .prepare = snd_intel8x0_pcm_prepare, 1354 .trigger = snd_intel8x0_pcm_trigger, 1355 .pointer = snd_intel8x0_pcm_pointer, 1356 }; 1357 1358 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = { 1359 .open = snd_intel8x0_capture2_open, 1360 .close = snd_intel8x0_capture2_close, 1361 .ioctl = snd_pcm_lib_ioctl, 1362 .hw_params = snd_intel8x0_hw_params, 1363 .hw_free = snd_intel8x0_hw_free, 1364 .prepare = snd_intel8x0_pcm_prepare, 1365 .trigger = snd_intel8x0_pcm_trigger, 1366 .pointer = snd_intel8x0_pcm_pointer, 1367 }; 1368 1369 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = { 1370 .open = snd_intel8x0_spdif_open, 1371 .close = snd_intel8x0_spdif_close, 1372 .ioctl = snd_pcm_lib_ioctl, 1373 .hw_params = snd_intel8x0_hw_params, 1374 .hw_free = snd_intel8x0_hw_free, 1375 .prepare = snd_intel8x0_pcm_prepare, 1376 .trigger = snd_intel8x0_pcm_trigger, 1377 .pointer = snd_intel8x0_pcm_pointer, 1378 }; 1379 1380 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { 1381 .open = snd_intel8x0_playback_open, 1382 .close = snd_intel8x0_playback_close, 1383 .ioctl = snd_pcm_lib_ioctl, 1384 .hw_params = snd_intel8x0_hw_params, 1385 .hw_free = snd_intel8x0_hw_free, 1386 .prepare = snd_intel8x0_pcm_prepare, 1387 .trigger = snd_intel8x0_ali_trigger, 1388 .pointer = snd_intel8x0_pcm_pointer, 1389 }; 1390 1391 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { 1392 .open = snd_intel8x0_capture_open, 1393 .close = snd_intel8x0_capture_close, 1394 .ioctl = snd_pcm_lib_ioctl, 1395 .hw_params = snd_intel8x0_hw_params, 1396 .hw_free = snd_intel8x0_hw_free, 1397 .prepare = snd_intel8x0_pcm_prepare, 1398 .trigger = snd_intel8x0_ali_trigger, 1399 .pointer = snd_intel8x0_pcm_pointer, 1400 }; 1401 1402 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { 1403 .open = snd_intel8x0_mic_open, 1404 .close = snd_intel8x0_mic_close, 1405 .ioctl = snd_pcm_lib_ioctl, 1406 .hw_params = snd_intel8x0_hw_params, 1407 .hw_free = snd_intel8x0_hw_free, 1408 .prepare = snd_intel8x0_pcm_prepare, 1409 .trigger = snd_intel8x0_ali_trigger, 1410 .pointer = snd_intel8x0_pcm_pointer, 1411 }; 1412 1413 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { 1414 .open = snd_intel8x0_ali_ac97spdifout_open, 1415 .close = snd_intel8x0_ali_ac97spdifout_close, 1416 .ioctl = snd_pcm_lib_ioctl, 1417 .hw_params = snd_intel8x0_hw_params, 1418 .hw_free = snd_intel8x0_hw_free, 1419 .prepare = snd_intel8x0_pcm_prepare, 1420 .trigger = snd_intel8x0_ali_trigger, 1421 .pointer = snd_intel8x0_pcm_pointer, 1422 }; 1423 1424 #if 0 // NYI 1425 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { 1426 .open = snd_intel8x0_ali_spdifin_open, 1427 .close = snd_intel8x0_ali_spdifin_close, 1428 .ioctl = snd_pcm_lib_ioctl, 1429 .hw_params = snd_intel8x0_hw_params, 1430 .hw_free = snd_intel8x0_hw_free, 1431 .prepare = snd_intel8x0_pcm_prepare, 1432 .trigger = snd_intel8x0_pcm_trigger, 1433 .pointer = snd_intel8x0_pcm_pointer, 1434 }; 1435 1436 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { 1437 .open = snd_intel8x0_ali_spdifout_open, 1438 .close = snd_intel8x0_ali_spdifout_close, 1439 .ioctl = snd_pcm_lib_ioctl, 1440 .hw_params = snd_intel8x0_hw_params, 1441 .hw_free = snd_intel8x0_hw_free, 1442 .prepare = snd_intel8x0_pcm_prepare, 1443 .trigger = snd_intel8x0_pcm_trigger, 1444 .pointer = snd_intel8x0_pcm_pointer, 1445 }; 1446 #endif // NYI 1447 1448 struct ich_pcm_table { 1449 char *suffix; 1450 const struct snd_pcm_ops *playback_ops; 1451 const struct snd_pcm_ops *capture_ops; 1452 size_t prealloc_size; 1453 size_t prealloc_max_size; 1454 int ac97_idx; 1455 }; 1456 1457 #define intel8x0_dma_type(chip) \ 1458 ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV) 1459 1460 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device, 1461 struct ich_pcm_table *rec) 1462 { 1463 struct snd_pcm *pcm; 1464 int err; 1465 char name[32]; 1466 1467 if (rec->suffix) 1468 sprintf(name, "Intel ICH - %s", rec->suffix); 1469 else 1470 strcpy(name, "Intel ICH"); 1471 err = snd_pcm_new(chip->card, name, device, 1472 rec->playback_ops ? 1 : 0, 1473 rec->capture_ops ? 1 : 0, &pcm); 1474 if (err < 0) 1475 return err; 1476 1477 if (rec->playback_ops) 1478 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1479 if (rec->capture_ops) 1480 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1481 1482 pcm->private_data = chip; 1483 pcm->info_flags = 0; 1484 if (rec->suffix) 1485 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1486 else 1487 strcpy(pcm->name, chip->card->shortname); 1488 chip->pcm[device] = pcm; 1489 1490 snd_pcm_lib_preallocate_pages_for_all(pcm, intel8x0_dma_type(chip), 1491 snd_dma_pci_data(chip->pci), 1492 rec->prealloc_size, rec->prealloc_max_size); 1493 1494 if (rec->playback_ops && 1495 rec->playback_ops->open == snd_intel8x0_playback_open) { 1496 struct snd_pcm_chmap *chmap; 1497 int chs = 2; 1498 if (chip->multi8) 1499 chs = 8; 1500 else if (chip->multi6) 1501 chs = 6; 1502 else if (chip->multi4) 1503 chs = 4; 1504 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1505 snd_pcm_alt_chmaps, chs, 0, 1506 &chmap); 1507 if (err < 0) 1508 return err; 1509 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; 1510 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; 1511 } 1512 1513 return 0; 1514 } 1515 1516 static struct ich_pcm_table intel_pcms[] = { 1517 { 1518 .playback_ops = &snd_intel8x0_playback_ops, 1519 .capture_ops = &snd_intel8x0_capture_ops, 1520 .prealloc_size = 64 * 1024, 1521 .prealloc_max_size = 128 * 1024, 1522 }, 1523 { 1524 .suffix = "MIC ADC", 1525 .capture_ops = &snd_intel8x0_capture_mic_ops, 1526 .prealloc_size = 0, 1527 .prealloc_max_size = 128 * 1024, 1528 .ac97_idx = ICHD_MIC, 1529 }, 1530 { 1531 .suffix = "MIC2 ADC", 1532 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1533 .prealloc_size = 0, 1534 .prealloc_max_size = 128 * 1024, 1535 .ac97_idx = ICHD_MIC2, 1536 }, 1537 { 1538 .suffix = "ADC2", 1539 .capture_ops = &snd_intel8x0_capture2_ops, 1540 .prealloc_size = 0, 1541 .prealloc_max_size = 128 * 1024, 1542 .ac97_idx = ICHD_PCM2IN, 1543 }, 1544 { 1545 .suffix = "IEC958", 1546 .playback_ops = &snd_intel8x0_spdif_ops, 1547 .prealloc_size = 64 * 1024, 1548 .prealloc_max_size = 128 * 1024, 1549 .ac97_idx = ICHD_SPBAR, 1550 }, 1551 }; 1552 1553 static struct ich_pcm_table nforce_pcms[] = { 1554 { 1555 .playback_ops = &snd_intel8x0_playback_ops, 1556 .capture_ops = &snd_intel8x0_capture_ops, 1557 .prealloc_size = 64 * 1024, 1558 .prealloc_max_size = 128 * 1024, 1559 }, 1560 { 1561 .suffix = "MIC ADC", 1562 .capture_ops = &snd_intel8x0_capture_mic_ops, 1563 .prealloc_size = 0, 1564 .prealloc_max_size = 128 * 1024, 1565 .ac97_idx = NVD_MIC, 1566 }, 1567 { 1568 .suffix = "IEC958", 1569 .playback_ops = &snd_intel8x0_spdif_ops, 1570 .prealloc_size = 64 * 1024, 1571 .prealloc_max_size = 128 * 1024, 1572 .ac97_idx = NVD_SPBAR, 1573 }, 1574 }; 1575 1576 static struct ich_pcm_table ali_pcms[] = { 1577 { 1578 .playback_ops = &snd_intel8x0_ali_playback_ops, 1579 .capture_ops = &snd_intel8x0_ali_capture_ops, 1580 .prealloc_size = 64 * 1024, 1581 .prealloc_max_size = 128 * 1024, 1582 }, 1583 { 1584 .suffix = "MIC ADC", 1585 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1586 .prealloc_size = 0, 1587 .prealloc_max_size = 128 * 1024, 1588 .ac97_idx = ALID_MIC, 1589 }, 1590 { 1591 .suffix = "IEC958", 1592 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1593 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ 1594 .prealloc_size = 64 * 1024, 1595 .prealloc_max_size = 128 * 1024, 1596 .ac97_idx = ALID_AC97SPDIFOUT, 1597 }, 1598 #if 0 // NYI 1599 { 1600 .suffix = "HW IEC958", 1601 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1602 .prealloc_size = 64 * 1024, 1603 .prealloc_max_size = 128 * 1024, 1604 }, 1605 #endif 1606 }; 1607 1608 static int snd_intel8x0_pcm(struct intel8x0 *chip) 1609 { 1610 int i, tblsize, device, err; 1611 struct ich_pcm_table *tbl, *rec; 1612 1613 switch (chip->device_type) { 1614 case DEVICE_INTEL_ICH4: 1615 tbl = intel_pcms; 1616 tblsize = ARRAY_SIZE(intel_pcms); 1617 if (spdif_aclink) 1618 tblsize--; 1619 break; 1620 case DEVICE_NFORCE: 1621 tbl = nforce_pcms; 1622 tblsize = ARRAY_SIZE(nforce_pcms); 1623 if (spdif_aclink) 1624 tblsize--; 1625 break; 1626 case DEVICE_ALI: 1627 tbl = ali_pcms; 1628 tblsize = ARRAY_SIZE(ali_pcms); 1629 break; 1630 default: 1631 tbl = intel_pcms; 1632 tblsize = 2; 1633 break; 1634 } 1635 1636 device = 0; 1637 for (i = 0; i < tblsize; i++) { 1638 rec = tbl + i; 1639 if (i > 0 && rec->ac97_idx) { 1640 /* activate PCM only when associated AC'97 codec */ 1641 if (! chip->ichd[rec->ac97_idx].pcm) 1642 continue; 1643 } 1644 err = snd_intel8x0_pcm1(chip, device, rec); 1645 if (err < 0) 1646 return err; 1647 device++; 1648 } 1649 1650 chip->pcm_devs = device; 1651 return 0; 1652 } 1653 1654 1655 /* 1656 * Mixer part 1657 */ 1658 1659 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1660 { 1661 struct intel8x0 *chip = bus->private_data; 1662 chip->ac97_bus = NULL; 1663 } 1664 1665 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 1666 { 1667 struct intel8x0 *chip = ac97->private_data; 1668 chip->ac97[ac97->num] = NULL; 1669 } 1670 1671 static const struct ac97_pcm ac97_pcm_defs[] = { 1672 /* front PCM */ 1673 { 1674 .exclusive = 1, 1675 .r = { { 1676 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1677 (1 << AC97_SLOT_PCM_RIGHT) | 1678 (1 << AC97_SLOT_PCM_CENTER) | 1679 (1 << AC97_SLOT_PCM_SLEFT) | 1680 (1 << AC97_SLOT_PCM_SRIGHT) | 1681 (1 << AC97_SLOT_LFE) 1682 }, 1683 { 1684 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1685 (1 << AC97_SLOT_PCM_RIGHT) | 1686 (1 << AC97_SLOT_PCM_LEFT_0) | 1687 (1 << AC97_SLOT_PCM_RIGHT_0) 1688 } 1689 } 1690 }, 1691 /* PCM IN #1 */ 1692 { 1693 .stream = 1, 1694 .exclusive = 1, 1695 .r = { { 1696 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1697 (1 << AC97_SLOT_PCM_RIGHT) 1698 } 1699 } 1700 }, 1701 /* MIC IN #1 */ 1702 { 1703 .stream = 1, 1704 .exclusive = 1, 1705 .r = { { 1706 .slots = (1 << AC97_SLOT_MIC) 1707 } 1708 } 1709 }, 1710 /* S/PDIF PCM */ 1711 { 1712 .exclusive = 1, 1713 .spdif = 1, 1714 .r = { { 1715 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1716 (1 << AC97_SLOT_SPDIF_RIGHT2) 1717 } 1718 } 1719 }, 1720 /* PCM IN #2 */ 1721 { 1722 .stream = 1, 1723 .exclusive = 1, 1724 .r = { { 1725 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1726 (1 << AC97_SLOT_PCM_RIGHT) 1727 } 1728 } 1729 }, 1730 /* MIC IN #2 */ 1731 { 1732 .stream = 1, 1733 .exclusive = 1, 1734 .r = { { 1735 .slots = (1 << AC97_SLOT_MIC) 1736 } 1737 } 1738 }, 1739 }; 1740 1741 static const struct ac97_quirk ac97_quirks[] = { 1742 { 1743 .subvendor = 0x0e11, 1744 .subdevice = 0x000e, 1745 .name = "Compaq Deskpro EN", /* AD1885 */ 1746 .type = AC97_TUNE_HP_ONLY 1747 }, 1748 { 1749 .subvendor = 0x0e11, 1750 .subdevice = 0x008a, 1751 .name = "Compaq Evo W4000", /* AD1885 */ 1752 .type = AC97_TUNE_HP_ONLY 1753 }, 1754 { 1755 .subvendor = 0x0e11, 1756 .subdevice = 0x00b8, 1757 .name = "Compaq Evo D510C", 1758 .type = AC97_TUNE_HP_ONLY 1759 }, 1760 { 1761 .subvendor = 0x0e11, 1762 .subdevice = 0x0860, 1763 .name = "HP/Compaq nx7010", 1764 .type = AC97_TUNE_MUTE_LED 1765 }, 1766 { 1767 .subvendor = 0x1014, 1768 .subdevice = 0x0534, 1769 .name = "ThinkPad X31", 1770 .type = AC97_TUNE_INV_EAPD 1771 }, 1772 { 1773 .subvendor = 0x1014, 1774 .subdevice = 0x1f00, 1775 .name = "MS-9128", 1776 .type = AC97_TUNE_ALC_JACK 1777 }, 1778 { 1779 .subvendor = 0x1014, 1780 .subdevice = 0x0267, 1781 .name = "IBM NetVista A30p", /* AD1981B */ 1782 .type = AC97_TUNE_HP_ONLY 1783 }, 1784 { 1785 .subvendor = 0x1025, 1786 .subdevice = 0x0082, 1787 .name = "Acer Travelmate 2310", 1788 .type = AC97_TUNE_HP_ONLY 1789 }, 1790 { 1791 .subvendor = 0x1025, 1792 .subdevice = 0x0083, 1793 .name = "Acer Aspire 3003LCi", 1794 .type = AC97_TUNE_HP_ONLY 1795 }, 1796 { 1797 .subvendor = 0x1028, 1798 .subdevice = 0x00d8, 1799 .name = "Dell Precision 530", /* AD1885 */ 1800 .type = AC97_TUNE_HP_ONLY 1801 }, 1802 { 1803 .subvendor = 0x1028, 1804 .subdevice = 0x010d, 1805 .name = "Dell", /* which model? AD1885 */ 1806 .type = AC97_TUNE_HP_ONLY 1807 }, 1808 { 1809 .subvendor = 0x1028, 1810 .subdevice = 0x0126, 1811 .name = "Dell Optiplex GX260", /* AD1981A */ 1812 .type = AC97_TUNE_HP_ONLY 1813 }, 1814 { 1815 .subvendor = 0x1028, 1816 .subdevice = 0x012c, 1817 .name = "Dell Precision 650", /* AD1981A */ 1818 .type = AC97_TUNE_HP_ONLY 1819 }, 1820 { 1821 .subvendor = 0x1028, 1822 .subdevice = 0x012d, 1823 .name = "Dell Precision 450", /* AD1981B*/ 1824 .type = AC97_TUNE_HP_ONLY 1825 }, 1826 { 1827 .subvendor = 0x1028, 1828 .subdevice = 0x0147, 1829 .name = "Dell", /* which model? AD1981B*/ 1830 .type = AC97_TUNE_HP_ONLY 1831 }, 1832 { 1833 .subvendor = 0x1028, 1834 .subdevice = 0x0151, 1835 .name = "Dell Optiplex GX270", /* AD1981B */ 1836 .type = AC97_TUNE_HP_ONLY 1837 }, 1838 { 1839 .subvendor = 0x1028, 1840 .subdevice = 0x014e, 1841 .name = "Dell D800", /* STAC9750/51 */ 1842 .type = AC97_TUNE_HP_ONLY 1843 }, 1844 { 1845 .subvendor = 0x1028, 1846 .subdevice = 0x0163, 1847 .name = "Dell Unknown", /* STAC9750/51 */ 1848 .type = AC97_TUNE_HP_ONLY 1849 }, 1850 { 1851 .subvendor = 0x1028, 1852 .subdevice = 0x016a, 1853 .name = "Dell Inspiron 8600", /* STAC9750/51 */ 1854 .type = AC97_TUNE_HP_ONLY 1855 }, 1856 { 1857 .subvendor = 0x1028, 1858 .subdevice = 0x0182, 1859 .name = "Dell Latitude D610", /* STAC9750/51 */ 1860 .type = AC97_TUNE_HP_ONLY 1861 }, 1862 { 1863 .subvendor = 0x1028, 1864 .subdevice = 0x0186, 1865 .name = "Dell Latitude D810", /* cf. Malone #41015 */ 1866 .type = AC97_TUNE_HP_MUTE_LED 1867 }, 1868 { 1869 .subvendor = 0x1028, 1870 .subdevice = 0x0188, 1871 .name = "Dell Inspiron 6000", 1872 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */ 1873 }, 1874 { 1875 .subvendor = 0x1028, 1876 .subdevice = 0x0189, 1877 .name = "Dell Inspiron 9300", 1878 .type = AC97_TUNE_HP_MUTE_LED 1879 }, 1880 { 1881 .subvendor = 0x1028, 1882 .subdevice = 0x0191, 1883 .name = "Dell Inspiron 8600", 1884 .type = AC97_TUNE_HP_ONLY 1885 }, 1886 { 1887 .subvendor = 0x103c, 1888 .subdevice = 0x006d, 1889 .name = "HP zv5000", 1890 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1891 }, 1892 { /* FIXME: which codec? */ 1893 .subvendor = 0x103c, 1894 .subdevice = 0x00c3, 1895 .name = "HP xw6000", 1896 .type = AC97_TUNE_HP_ONLY 1897 }, 1898 { 1899 .subvendor = 0x103c, 1900 .subdevice = 0x088c, 1901 .name = "HP nc8000", 1902 .type = AC97_TUNE_HP_MUTE_LED 1903 }, 1904 { 1905 .subvendor = 0x103c, 1906 .subdevice = 0x0890, 1907 .name = "HP nc6000", 1908 .type = AC97_TUNE_MUTE_LED 1909 }, 1910 { 1911 .subvendor = 0x103c, 1912 .subdevice = 0x129d, 1913 .name = "HP xw8000", 1914 .type = AC97_TUNE_HP_ONLY 1915 }, 1916 { 1917 .subvendor = 0x103c, 1918 .subdevice = 0x0938, 1919 .name = "HP nc4200", 1920 .type = AC97_TUNE_HP_MUTE_LED 1921 }, 1922 { 1923 .subvendor = 0x103c, 1924 .subdevice = 0x099c, 1925 .name = "HP nx6110/nc6120", 1926 .type = AC97_TUNE_HP_MUTE_LED 1927 }, 1928 { 1929 .subvendor = 0x103c, 1930 .subdevice = 0x0944, 1931 .name = "HP nc6220", 1932 .type = AC97_TUNE_HP_MUTE_LED 1933 }, 1934 { 1935 .subvendor = 0x103c, 1936 .subdevice = 0x0934, 1937 .name = "HP nc8220", 1938 .type = AC97_TUNE_HP_MUTE_LED 1939 }, 1940 { 1941 .subvendor = 0x103c, 1942 .subdevice = 0x12f1, 1943 .name = "HP xw8200", /* AD1981B*/ 1944 .type = AC97_TUNE_HP_ONLY 1945 }, 1946 { 1947 .subvendor = 0x103c, 1948 .subdevice = 0x12f2, 1949 .name = "HP xw6200", 1950 .type = AC97_TUNE_HP_ONLY 1951 }, 1952 { 1953 .subvendor = 0x103c, 1954 .subdevice = 0x3008, 1955 .name = "HP xw4200", /* AD1981B*/ 1956 .type = AC97_TUNE_HP_ONLY 1957 }, 1958 { 1959 .subvendor = 0x104d, 1960 .subdevice = 0x8144, 1961 .name = "Sony", 1962 .type = AC97_TUNE_INV_EAPD 1963 }, 1964 { 1965 .subvendor = 0x104d, 1966 .subdevice = 0x8197, 1967 .name = "Sony S1XP", 1968 .type = AC97_TUNE_INV_EAPD 1969 }, 1970 { 1971 .subvendor = 0x104d, 1972 .subdevice = 0x81c0, 1973 .name = "Sony VAIO VGN-T350P", /*AD1981B*/ 1974 .type = AC97_TUNE_INV_EAPD 1975 }, 1976 { 1977 .subvendor = 0x104d, 1978 .subdevice = 0x81c5, 1979 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/ 1980 .type = AC97_TUNE_INV_EAPD 1981 }, 1982 { 1983 .subvendor = 0x1043, 1984 .subdevice = 0x80f3, 1985 .name = "ASUS ICH5/AD1985", 1986 .type = AC97_TUNE_AD_SHARING 1987 }, 1988 { 1989 .subvendor = 0x10cf, 1990 .subdevice = 0x11c3, 1991 .name = "Fujitsu-Siemens E4010", 1992 .type = AC97_TUNE_HP_ONLY 1993 }, 1994 { 1995 .subvendor = 0x10cf, 1996 .subdevice = 0x1225, 1997 .name = "Fujitsu-Siemens T3010", 1998 .type = AC97_TUNE_HP_ONLY 1999 }, 2000 { 2001 .subvendor = 0x10cf, 2002 .subdevice = 0x1253, 2003 .name = "Fujitsu S6210", /* STAC9750/51 */ 2004 .type = AC97_TUNE_HP_ONLY 2005 }, 2006 { 2007 .subvendor = 0x10cf, 2008 .subdevice = 0x127d, 2009 .name = "Fujitsu Lifebook P7010", 2010 .type = AC97_TUNE_HP_ONLY 2011 }, 2012 { 2013 .subvendor = 0x10cf, 2014 .subdevice = 0x127e, 2015 .name = "Fujitsu Lifebook C1211D", 2016 .type = AC97_TUNE_HP_ONLY 2017 }, 2018 { 2019 .subvendor = 0x10cf, 2020 .subdevice = 0x12ec, 2021 .name = "Fujitsu-Siemens 4010", 2022 .type = AC97_TUNE_HP_ONLY 2023 }, 2024 { 2025 .subvendor = 0x10cf, 2026 .subdevice = 0x12f2, 2027 .name = "Fujitsu-Siemens Celsius H320", 2028 .type = AC97_TUNE_SWAP_HP 2029 }, 2030 { 2031 .subvendor = 0x10f1, 2032 .subdevice = 0x2665, 2033 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 2034 .type = AC97_TUNE_HP_ONLY 2035 }, 2036 { 2037 .subvendor = 0x10f1, 2038 .subdevice = 0x2885, 2039 .name = "AMD64 Mobo", /* ALC650 */ 2040 .type = AC97_TUNE_HP_ONLY 2041 }, 2042 { 2043 .subvendor = 0x10f1, 2044 .subdevice = 0x2895, 2045 .name = "Tyan Thunder K8WE", 2046 .type = AC97_TUNE_HP_ONLY 2047 }, 2048 { 2049 .subvendor = 0x10f7, 2050 .subdevice = 0x834c, 2051 .name = "Panasonic CF-R4", 2052 .type = AC97_TUNE_HP_ONLY, 2053 }, 2054 { 2055 .subvendor = 0x110a, 2056 .subdevice = 0x0056, 2057 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 2058 .type = AC97_TUNE_HP_ONLY 2059 }, 2060 { 2061 .subvendor = 0x11d4, 2062 .subdevice = 0x5375, 2063 .name = "ADI AD1985 (discrete)", 2064 .type = AC97_TUNE_HP_ONLY 2065 }, 2066 { 2067 .subvendor = 0x1462, 2068 .subdevice = 0x5470, 2069 .name = "MSI P4 ATX 645 Ultra", 2070 .type = AC97_TUNE_HP_ONLY 2071 }, 2072 { 2073 .subvendor = 0x161f, 2074 .subdevice = 0x202f, 2075 .name = "Gateway M520", 2076 .type = AC97_TUNE_INV_EAPD 2077 }, 2078 { 2079 .subvendor = 0x161f, 2080 .subdevice = 0x203a, 2081 .name = "Gateway 4525GZ", /* AD1981B */ 2082 .type = AC97_TUNE_INV_EAPD 2083 }, 2084 { 2085 .subvendor = 0x1734, 2086 .subdevice = 0x0088, 2087 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 2088 .type = AC97_TUNE_HP_ONLY 2089 }, 2090 { 2091 .subvendor = 0x8086, 2092 .subdevice = 0x2000, 2093 .mask = 0xfff0, 2094 .name = "Intel ICH5/AD1985", 2095 .type = AC97_TUNE_AD_SHARING 2096 }, 2097 { 2098 .subvendor = 0x8086, 2099 .subdevice = 0x4000, 2100 .mask = 0xfff0, 2101 .name = "Intel ICH5/AD1985", 2102 .type = AC97_TUNE_AD_SHARING 2103 }, 2104 { 2105 .subvendor = 0x8086, 2106 .subdevice = 0x4856, 2107 .name = "Intel D845WN (82801BA)", 2108 .type = AC97_TUNE_SWAP_HP 2109 }, 2110 { 2111 .subvendor = 0x8086, 2112 .subdevice = 0x4d44, 2113 .name = "Intel D850EMV2", /* AD1885 */ 2114 .type = AC97_TUNE_HP_ONLY 2115 }, 2116 { 2117 .subvendor = 0x8086, 2118 .subdevice = 0x4d56, 2119 .name = "Intel ICH/AD1885", 2120 .type = AC97_TUNE_HP_ONLY 2121 }, 2122 { 2123 .subvendor = 0x8086, 2124 .subdevice = 0x6000, 2125 .mask = 0xfff0, 2126 .name = "Intel ICH5/AD1985", 2127 .type = AC97_TUNE_AD_SHARING 2128 }, 2129 { 2130 .subvendor = 0x8086, 2131 .subdevice = 0xe000, 2132 .mask = 0xfff0, 2133 .name = "Intel ICH5/AD1985", 2134 .type = AC97_TUNE_AD_SHARING 2135 }, 2136 #if 0 /* FIXME: this seems wrong on most boards */ 2137 { 2138 .subvendor = 0x8086, 2139 .subdevice = 0xa000, 2140 .mask = 0xfff0, 2141 .name = "Intel ICH5/AD1985", 2142 .type = AC97_TUNE_HP_ONLY 2143 }, 2144 #endif 2145 { } /* terminator */ 2146 }; 2147 2148 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, 2149 const char *quirk_override) 2150 { 2151 struct snd_ac97_bus *pbus; 2152 struct snd_ac97_template ac97; 2153 int err; 2154 unsigned int i, codecs; 2155 unsigned int glob_sta = 0; 2156 struct snd_ac97_bus_ops *ops; 2157 static struct snd_ac97_bus_ops standard_bus_ops = { 2158 .write = snd_intel8x0_codec_write, 2159 .read = snd_intel8x0_codec_read, 2160 }; 2161 static struct snd_ac97_bus_ops ali_bus_ops = { 2162 .write = snd_intel8x0_ali_codec_write, 2163 .read = snd_intel8x0_ali_codec_read, 2164 }; 2165 2166 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 2167 if (!spdif_aclink) { 2168 switch (chip->device_type) { 2169 case DEVICE_NFORCE: 2170 chip->spdif_idx = NVD_SPBAR; 2171 break; 2172 case DEVICE_ALI: 2173 chip->spdif_idx = ALID_AC97SPDIFOUT; 2174 break; 2175 case DEVICE_INTEL_ICH4: 2176 chip->spdif_idx = ICHD_SPBAR; 2177 break; 2178 } 2179 } 2180 2181 chip->in_ac97_init = 1; 2182 2183 memset(&ac97, 0, sizeof(ac97)); 2184 ac97.private_data = chip; 2185 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2186 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 2187 if (chip->xbox) 2188 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2189 if (chip->device_type != DEVICE_ALI) { 2190 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2191 ops = &standard_bus_ops; 2192 chip->in_sdin_init = 1; 2193 codecs = 0; 2194 for (i = 0; i < chip->max_codecs; i++) { 2195 if (! (glob_sta & chip->codec_bit[i])) 2196 continue; 2197 if (chip->device_type == DEVICE_INTEL_ICH4) { 2198 snd_intel8x0_codec_read_test(chip, codecs); 2199 chip->ac97_sdin[codecs] = 2200 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2201 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3)) 2202 chip->ac97_sdin[codecs] = 0; 2203 } else 2204 chip->ac97_sdin[codecs] = i; 2205 codecs++; 2206 } 2207 chip->in_sdin_init = 0; 2208 if (! codecs) 2209 codecs = 1; 2210 } else { 2211 ops = &ali_bus_ops; 2212 codecs = 1; 2213 /* detect the secondary codec */ 2214 for (i = 0; i < 100; i++) { 2215 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2216 if (reg & 0x40) { 2217 codecs = 2; 2218 break; 2219 } 2220 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2221 udelay(1); 2222 } 2223 } 2224 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2225 goto __err; 2226 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2227 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2228 pbus->clock = ac97_clock; 2229 /* FIXME: my test board doesn't work well with VRA... */ 2230 if (chip->device_type == DEVICE_ALI) 2231 pbus->no_vra = 1; 2232 else 2233 pbus->dra = 1; 2234 chip->ac97_bus = pbus; 2235 chip->ncodecs = codecs; 2236 2237 ac97.pci = chip->pci; 2238 for (i = 0; i < codecs; i++) { 2239 ac97.num = i; 2240 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2241 if (err != -EACCES) 2242 dev_err(chip->card->dev, 2243 "Unable to initialize codec #%d\n", i); 2244 if (i == 0) 2245 goto __err; 2246 } 2247 } 2248 /* tune up the primary codec */ 2249 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2250 /* enable separate SDINs for ICH4 */ 2251 if (chip->device_type == DEVICE_INTEL_ICH4) 2252 pbus->isdin = 1; 2253 /* find the available PCM streams */ 2254 i = ARRAY_SIZE(ac97_pcm_defs); 2255 if (chip->device_type != DEVICE_INTEL_ICH4) 2256 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2257 if (chip->spdif_idx < 0) 2258 i--; /* do not allocate S/PDIF */ 2259 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2260 if (err < 0) 2261 goto __err; 2262 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2263 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2264 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2265 if (chip->spdif_idx >= 0) 2266 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2267 if (chip->device_type == DEVICE_INTEL_ICH4) { 2268 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2269 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2270 } 2271 /* enable separate SDINs for ICH4 */ 2272 if (chip->device_type == DEVICE_INTEL_ICH4) { 2273 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2274 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2275 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2276 if (pcm) { 2277 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2278 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2279 for (i = 1; i < 4; i++) { 2280 if (pcm->r[0].codec[i]) { 2281 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2282 break; 2283 } 2284 } 2285 } else { 2286 tmp &= ~ICH_SE; /* steer disable */ 2287 } 2288 iputbyte(chip, ICHREG(SDM), tmp); 2289 } 2290 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2291 chip->multi4 = 1; 2292 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) { 2293 chip->multi6 = 1; 2294 if (chip->ac97[0]->flags & AC97_HAS_8CH) 2295 chip->multi8 = 1; 2296 } 2297 } 2298 if (pbus->pcms[0].r[1].rslots[0]) { 2299 chip->dra = 1; 2300 } 2301 if (chip->device_type == DEVICE_INTEL_ICH4) { 2302 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2303 chip->smp20bit = 1; 2304 } 2305 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2306 /* 48kHz only */ 2307 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2308 } 2309 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2310 /* use slot 10/11 for SPDIF */ 2311 u32 val; 2312 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2313 val |= ICH_PCM_SPDIF_1011; 2314 iputdword(chip, ICHREG(GLOB_CNT), val); 2315 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2316 } 2317 chip->in_ac97_init = 0; 2318 return 0; 2319 2320 __err: 2321 /* clear the cold-reset bit for the next chance */ 2322 if (chip->device_type != DEVICE_ALI) 2323 iputdword(chip, ICHREG(GLOB_CNT), 2324 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2325 return err; 2326 } 2327 2328 2329 /* 2330 * 2331 */ 2332 2333 static void do_ali_reset(struct intel8x0 *chip) 2334 { 2335 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2336 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2337 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2338 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2339 iputdword(chip, ICHREG(ALI_INTERFACECR), 2340 ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2341 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2342 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2343 } 2344 2345 #ifdef CONFIG_SND_AC97_POWER_SAVE 2346 static struct snd_pci_quirk ich_chip_reset_mode[] = { 2347 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1), 2348 { } /* end */ 2349 }; 2350 2351 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip) 2352 { 2353 unsigned int cnt; 2354 /* ACLink on, 2 channels */ 2355 2356 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2357 return -EIO; 2358 2359 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2360 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2361 2362 /* do cold reset - the full ac97 powerdown may leave the controller 2363 * in a warm state but actually it cannot communicate with the codec. 2364 */ 2365 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); 2366 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2367 udelay(10); 2368 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); 2369 msleep(1); 2370 return 0; 2371 } 2372 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \ 2373 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2374 #else 2375 #define snd_intel8x0_ich_chip_cold_reset(chip) 0 2376 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0) 2377 #endif 2378 2379 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip) 2380 { 2381 unsigned long end_time; 2382 unsigned int cnt; 2383 /* ACLink on, 2 channels */ 2384 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2385 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2386 /* finish cold or do warm reset */ 2387 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2388 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2389 end_time = (jiffies + (HZ / 4)) + 1; 2390 do { 2391 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2392 return 0; 2393 schedule_timeout_uninterruptible(1); 2394 } while (time_after_eq(end_time, jiffies)); 2395 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", 2396 igetdword(chip, ICHREG(GLOB_CNT))); 2397 return -EIO; 2398 } 2399 2400 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) 2401 { 2402 unsigned long end_time; 2403 unsigned int status, nstatus; 2404 unsigned int cnt; 2405 int err; 2406 2407 /* put logic to right state */ 2408 /* first clear status bits */ 2409 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2410 if (chip->device_type == DEVICE_NFORCE) 2411 status |= ICH_NVSPINT; 2412 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2413 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2414 2415 if (snd_intel8x0_ich_chip_can_cold_reset(chip)) 2416 err = snd_intel8x0_ich_chip_cold_reset(chip); 2417 else 2418 err = snd_intel8x0_ich_chip_reset(chip); 2419 if (err < 0) 2420 return err; 2421 2422 if (probing) { 2423 /* wait for any codec ready status. 2424 * Once it becomes ready it should remain ready 2425 * as long as we do not disable the ac97 link. 2426 */ 2427 end_time = jiffies + HZ; 2428 do { 2429 status = igetdword(chip, ICHREG(GLOB_STA)) & 2430 chip->codec_isr_bits; 2431 if (status) 2432 break; 2433 schedule_timeout_uninterruptible(1); 2434 } while (time_after_eq(end_time, jiffies)); 2435 if (! status) { 2436 /* no codec is found */ 2437 dev_err(chip->card->dev, 2438 "codec_ready: codec is not ready [0x%x]\n", 2439 igetdword(chip, ICHREG(GLOB_STA))); 2440 return -EIO; 2441 } 2442 2443 /* wait for other codecs ready status. */ 2444 end_time = jiffies + HZ / 4; 2445 while (status != chip->codec_isr_bits && 2446 time_after_eq(end_time, jiffies)) { 2447 schedule_timeout_uninterruptible(1); 2448 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2449 chip->codec_isr_bits; 2450 } 2451 2452 } else { 2453 /* resume phase */ 2454 int i; 2455 status = 0; 2456 for (i = 0; i < chip->ncodecs; i++) 2457 if (chip->ac97[i]) 2458 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2459 /* wait until all the probed codecs are ready */ 2460 end_time = jiffies + HZ; 2461 do { 2462 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 2463 chip->codec_isr_bits; 2464 if (status == nstatus) 2465 break; 2466 schedule_timeout_uninterruptible(1); 2467 } while (time_after_eq(end_time, jiffies)); 2468 } 2469 2470 if (chip->device_type == DEVICE_SIS) { 2471 /* unmute the output on SIS7012 */ 2472 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2473 } 2474 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2475 /* enable SPDIF interrupt */ 2476 unsigned int val; 2477 pci_read_config_dword(chip->pci, 0x4c, &val); 2478 val |= 0x1000000; 2479 pci_write_config_dword(chip->pci, 0x4c, val); 2480 } 2481 return 0; 2482 } 2483 2484 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) 2485 { 2486 u32 reg; 2487 int i = 0; 2488 2489 reg = igetdword(chip, ICHREG(ALI_SCR)); 2490 if ((reg & 2) == 0) /* Cold required */ 2491 reg |= 2; 2492 else 2493 reg |= 1; /* Warm */ 2494 reg &= ~0x80000000; /* ACLink on */ 2495 iputdword(chip, ICHREG(ALI_SCR), reg); 2496 2497 for (i = 0; i < HZ / 2; i++) { 2498 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2499 goto __ok; 2500 schedule_timeout_uninterruptible(1); 2501 } 2502 dev_err(chip->card->dev, "AC'97 reset failed.\n"); 2503 if (probing) 2504 return -EIO; 2505 2506 __ok: 2507 for (i = 0; i < HZ / 2; i++) { 2508 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2509 if (reg & 0x80) /* primary codec */ 2510 break; 2511 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2512 schedule_timeout_uninterruptible(1); 2513 } 2514 2515 do_ali_reset(chip); 2516 return 0; 2517 } 2518 2519 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) 2520 { 2521 unsigned int i, timeout; 2522 int err; 2523 2524 if (chip->device_type != DEVICE_ALI) { 2525 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2526 return err; 2527 iagetword(chip, 0); /* clear semaphore flag */ 2528 } else { 2529 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2530 return err; 2531 } 2532 2533 /* disable interrupts */ 2534 for (i = 0; i < chip->bdbars_count; i++) 2535 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2536 /* reset channels */ 2537 for (i = 0; i < chip->bdbars_count; i++) 2538 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2539 for (i = 0; i < chip->bdbars_count; i++) { 2540 timeout = 100000; 2541 while (--timeout != 0) { 2542 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) 2543 break; 2544 } 2545 if (timeout == 0) 2546 dev_err(chip->card->dev, "reset of registers failed?\n"); 2547 } 2548 /* initialize Buffer Descriptor Lists */ 2549 for (i = 0; i < chip->bdbars_count; i++) 2550 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, 2551 chip->ichd[i].bdbar_addr); 2552 return 0; 2553 } 2554 2555 static int snd_intel8x0_free(struct intel8x0 *chip) 2556 { 2557 unsigned int i; 2558 2559 if (chip->irq < 0) 2560 goto __hw_end; 2561 /* disable interrupts */ 2562 for (i = 0; i < chip->bdbars_count; i++) 2563 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2564 /* reset channels */ 2565 for (i = 0; i < chip->bdbars_count; i++) 2566 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2567 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2568 /* stop the spdif interrupt */ 2569 unsigned int val; 2570 pci_read_config_dword(chip->pci, 0x4c, &val); 2571 val &= ~0x1000000; 2572 pci_write_config_dword(chip->pci, 0x4c, val); 2573 } 2574 /* --- */ 2575 2576 __hw_end: 2577 if (chip->irq >= 0) 2578 free_irq(chip->irq, chip); 2579 if (chip->bdbars.area) 2580 snd_dma_free_pages(&chip->bdbars); 2581 if (chip->addr) 2582 pci_iounmap(chip->pci, chip->addr); 2583 if (chip->bmaddr) 2584 pci_iounmap(chip->pci, chip->bmaddr); 2585 pci_release_regions(chip->pci); 2586 pci_disable_device(chip->pci); 2587 kfree(chip); 2588 return 0; 2589 } 2590 2591 #ifdef CONFIG_PM_SLEEP 2592 /* 2593 * power management 2594 */ 2595 static int intel8x0_suspend(struct device *dev) 2596 { 2597 struct snd_card *card = dev_get_drvdata(dev); 2598 struct intel8x0 *chip = card->private_data; 2599 int i; 2600 2601 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2602 for (i = 0; i < chip->ncodecs; i++) 2603 snd_ac97_suspend(chip->ac97[i]); 2604 if (chip->device_type == DEVICE_INTEL_ICH4) 2605 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2606 2607 if (chip->irq >= 0) { 2608 free_irq(chip->irq, chip); 2609 chip->irq = -1; 2610 } 2611 return 0; 2612 } 2613 2614 static int intel8x0_resume(struct device *dev) 2615 { 2616 struct pci_dev *pci = to_pci_dev(dev); 2617 struct snd_card *card = dev_get_drvdata(dev); 2618 struct intel8x0 *chip = card->private_data; 2619 int i; 2620 2621 snd_intel8x0_chip_init(chip, 0); 2622 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2623 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2624 dev_err(dev, "unable to grab IRQ %d, disabling device\n", 2625 pci->irq); 2626 snd_card_disconnect(card); 2627 return -EIO; 2628 } 2629 chip->irq = pci->irq; 2630 synchronize_irq(chip->irq); 2631 2632 /* re-initialize mixer stuff */ 2633 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2634 /* enable separate SDINs for ICH4 */ 2635 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2636 /* use slot 10/11 for SPDIF */ 2637 iputdword(chip, ICHREG(GLOB_CNT), 2638 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2639 ICH_PCM_SPDIF_1011); 2640 } 2641 2642 for (i = 0; i < chip->ncodecs; i++) 2643 snd_ac97_resume(chip->ac97[i]); 2644 2645 /* resume status */ 2646 for (i = 0; i < chip->bdbars_count; i++) { 2647 struct ichdev *ichdev = &chip->ichd[i]; 2648 unsigned long port = ichdev->reg_offset; 2649 if (! ichdev->substream || ! ichdev->suspended) 2650 continue; 2651 if (ichdev->ichd == ICHD_PCMOUT) 2652 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2653 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2654 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2655 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2656 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2657 } 2658 2659 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2660 return 0; 2661 } 2662 2663 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume); 2664 #define INTEL8X0_PM_OPS &intel8x0_pm 2665 #else 2666 #define INTEL8X0_PM_OPS NULL 2667 #endif /* CONFIG_PM_SLEEP */ 2668 2669 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2670 2671 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip) 2672 { 2673 struct snd_pcm_substream *subs; 2674 struct ichdev *ichdev; 2675 unsigned long port; 2676 unsigned long pos, pos1, t; 2677 int civ, timeout = 1000, attempt = 1; 2678 ktime_t start_time, stop_time; 2679 2680 if (chip->ac97_bus->clock != 48000) 2681 return; /* specified in module option */ 2682 2683 __again: 2684 subs = chip->pcm[0]->streams[0].substream; 2685 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2686 dev_warn(chip->card->dev, 2687 "no playback buffer allocated - aborting measure ac97 clock\n"); 2688 return; 2689 } 2690 ichdev = &chip->ichd[ICHD_PCMOUT]; 2691 ichdev->physbuf = subs->dma_buffer.addr; 2692 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE; 2693 ichdev->substream = NULL; /* don't process interrupts */ 2694 2695 /* set rate */ 2696 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2697 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n", 2698 chip->ac97_bus->clock); 2699 return; 2700 } 2701 snd_intel8x0_setup_periods(chip, ichdev); 2702 port = ichdev->reg_offset; 2703 spin_lock_irq(&chip->reg_lock); 2704 chip->in_measurement = 1; 2705 /* trigger */ 2706 if (chip->device_type != DEVICE_ALI) 2707 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2708 else { 2709 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2710 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2711 } 2712 start_time = ktime_get(); 2713 spin_unlock_irq(&chip->reg_lock); 2714 msleep(50); 2715 spin_lock_irq(&chip->reg_lock); 2716 /* check the position */ 2717 do { 2718 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 2719 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 2720 if (pos1 == 0) { 2721 udelay(10); 2722 continue; 2723 } 2724 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 2725 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 2726 break; 2727 } while (timeout--); 2728 if (pos1 == 0) { /* oops, this value is not reliable */ 2729 pos = 0; 2730 } else { 2731 pos = ichdev->fragsize1; 2732 pos -= pos1 << ichdev->pos_shift; 2733 pos += ichdev->position; 2734 } 2735 chip->in_measurement = 0; 2736 stop_time = ktime_get(); 2737 /* stop */ 2738 if (chip->device_type == DEVICE_ALI) { 2739 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); 2740 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2741 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2742 ; 2743 } else { 2744 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2745 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2746 ; 2747 } 2748 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2749 spin_unlock_irq(&chip->reg_lock); 2750 2751 if (pos == 0) { 2752 dev_err(chip->card->dev, 2753 "measure - unreliable DMA position..\n"); 2754 __retry: 2755 if (attempt < 3) { 2756 msleep(300); 2757 attempt++; 2758 goto __again; 2759 } 2760 goto __end; 2761 } 2762 2763 pos /= 4; 2764 t = ktime_us_delta(stop_time, start_time); 2765 dev_info(chip->card->dev, 2766 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos); 2767 if (t == 0) { 2768 dev_err(chip->card->dev, "?? calculation error..\n"); 2769 goto __retry; 2770 } 2771 pos *= 1000; 2772 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2773 if (pos < 40000 || pos >= 60000) { 2774 /* abnormal value. hw problem? */ 2775 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos); 2776 goto __retry; 2777 } else if (pos > 40500 && pos < 41500) 2778 /* first exception - 41000Hz reference clock */ 2779 chip->ac97_bus->clock = 41000; 2780 else if (pos > 43600 && pos < 44600) 2781 /* second exception - 44100HZ reference clock */ 2782 chip->ac97_bus->clock = 44100; 2783 else if (pos < 47500 || pos > 48500) 2784 /* not 48000Hz, tuning the clock.. */ 2785 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2786 __end: 2787 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock); 2788 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2789 } 2790 2791 static struct snd_pci_quirk intel8x0_clock_list[] = { 2792 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000), 2793 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000), 2794 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100), 2795 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000), 2796 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000), 2797 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000), 2798 { } /* terminator */ 2799 }; 2800 2801 static int intel8x0_in_clock_list(struct intel8x0 *chip) 2802 { 2803 struct pci_dev *pci = chip->pci; 2804 const struct snd_pci_quirk *wl; 2805 2806 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list); 2807 if (!wl) 2808 return 0; 2809 dev_info(chip->card->dev, "white list rate for %04x:%04x is %i\n", 2810 pci->subsystem_vendor, pci->subsystem_device, wl->value); 2811 chip->ac97_bus->clock = wl->value; 2812 return 1; 2813 } 2814 2815 static void snd_intel8x0_proc_read(struct snd_info_entry * entry, 2816 struct snd_info_buffer *buffer) 2817 { 2818 struct intel8x0 *chip = entry->private_data; 2819 unsigned int tmp; 2820 2821 snd_iprintf(buffer, "Intel8x0\n\n"); 2822 if (chip->device_type == DEVICE_ALI) 2823 return; 2824 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2825 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2826 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2827 if (chip->device_type == DEVICE_INTEL_ICH4) 2828 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2829 snd_iprintf(buffer, "AC'97 codecs ready :"); 2830 if (tmp & chip->codec_isr_bits) { 2831 int i; 2832 static const char *codecs[3] = { 2833 "primary", "secondary", "tertiary" 2834 }; 2835 for (i = 0; i < chip->max_codecs; i++) 2836 if (tmp & chip->codec_bit[i]) 2837 snd_iprintf(buffer, " %s", codecs[i]); 2838 } else 2839 snd_iprintf(buffer, " none"); 2840 snd_iprintf(buffer, "\n"); 2841 if (chip->device_type == DEVICE_INTEL_ICH4 || 2842 chip->device_type == DEVICE_SIS) 2843 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2844 chip->ac97_sdin[0], 2845 chip->ac97_sdin[1], 2846 chip->ac97_sdin[2]); 2847 } 2848 2849 static void snd_intel8x0_proc_init(struct intel8x0 *chip) 2850 { 2851 snd_card_ro_proc_new(chip->card, "intel8x0", chip, 2852 snd_intel8x0_proc_read); 2853 } 2854 2855 static int snd_intel8x0_dev_free(struct snd_device *device) 2856 { 2857 struct intel8x0 *chip = device->device_data; 2858 return snd_intel8x0_free(chip); 2859 } 2860 2861 struct ich_reg_info { 2862 unsigned int int_sta_mask; 2863 unsigned int offset; 2864 }; 2865 2866 static unsigned int ich_codec_bits[3] = { 2867 ICH_PCR, ICH_SCR, ICH_TCR 2868 }; 2869 static unsigned int sis_codec_bits[3] = { 2870 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2871 }; 2872 2873 static int snd_intel8x0_inside_vm(struct pci_dev *pci) 2874 { 2875 int result = inside_vm; 2876 char *msg = NULL; 2877 2878 /* check module parameter first (override detection) */ 2879 if (result >= 0) { 2880 msg = result ? "enable (forced) VM" : "disable (forced) VM"; 2881 goto fini; 2882 } 2883 2884 /* check for known (emulated) devices */ 2885 result = 0; 2886 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET && 2887 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) { 2888 /* KVM emulated sound, PCI SSID: 1af4:1100 */ 2889 msg = "enable KVM"; 2890 result = 1; 2891 } else if (pci->subsystem_vendor == 0x1ab8) { 2892 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */ 2893 msg = "enable Parallels VM"; 2894 result = 1; 2895 } 2896 2897 fini: 2898 if (msg != NULL) 2899 dev_info(&pci->dev, "%s optimization\n", msg); 2900 2901 return result; 2902 } 2903 2904 static int snd_intel8x0_create(struct snd_card *card, 2905 struct pci_dev *pci, 2906 unsigned long device_type, 2907 struct intel8x0 **r_intel8x0) 2908 { 2909 struct intel8x0 *chip; 2910 int err; 2911 unsigned int i; 2912 unsigned int int_sta_masks; 2913 struct ichdev *ichdev; 2914 static struct snd_device_ops ops = { 2915 .dev_free = snd_intel8x0_dev_free, 2916 }; 2917 2918 static unsigned int bdbars[] = { 2919 3, /* DEVICE_INTEL */ 2920 6, /* DEVICE_INTEL_ICH4 */ 2921 3, /* DEVICE_SIS */ 2922 6, /* DEVICE_ALI */ 2923 4, /* DEVICE_NFORCE */ 2924 }; 2925 static struct ich_reg_info intel_regs[6] = { 2926 { ICH_PIINT, 0 }, 2927 { ICH_POINT, 0x10 }, 2928 { ICH_MCINT, 0x20 }, 2929 { ICH_M2INT, 0x40 }, 2930 { ICH_P2INT, 0x50 }, 2931 { ICH_SPINT, 0x60 }, 2932 }; 2933 static struct ich_reg_info nforce_regs[4] = { 2934 { ICH_PIINT, 0 }, 2935 { ICH_POINT, 0x10 }, 2936 { ICH_MCINT, 0x20 }, 2937 { ICH_NVSPINT, 0x70 }, 2938 }; 2939 static struct ich_reg_info ali_regs[6] = { 2940 { ALI_INT_PCMIN, 0x40 }, 2941 { ALI_INT_PCMOUT, 0x50 }, 2942 { ALI_INT_MICIN, 0x60 }, 2943 { ALI_INT_CODECSPDIFOUT, 0x70 }, 2944 { ALI_INT_SPDIFIN, 0xa0 }, 2945 { ALI_INT_SPDIFOUT, 0xb0 }, 2946 }; 2947 struct ich_reg_info *tbl; 2948 2949 *r_intel8x0 = NULL; 2950 2951 if ((err = pci_enable_device(pci)) < 0) 2952 return err; 2953 2954 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2955 if (chip == NULL) { 2956 pci_disable_device(pci); 2957 return -ENOMEM; 2958 } 2959 spin_lock_init(&chip->reg_lock); 2960 chip->device_type = device_type; 2961 chip->card = card; 2962 chip->pci = pci; 2963 chip->irq = -1; 2964 2965 /* module parameters */ 2966 chip->buggy_irq = buggy_irq; 2967 chip->buggy_semaphore = buggy_semaphore; 2968 if (xbox) 2969 chip->xbox = 1; 2970 2971 chip->inside_vm = snd_intel8x0_inside_vm(pci); 2972 2973 /* 2974 * Intel 82443MX running a 100MHz processor system bus has a hardware 2975 * bug, which aborts PCI busmaster for audio transfer. A workaround 2976 * is to set the pages as non-cached. For details, see the errata in 2977 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf 2978 */ 2979 if (pci->vendor == PCI_VENDOR_ID_INTEL && 2980 pci->device == PCI_DEVICE_ID_INTEL_440MX) 2981 chip->fix_nocache = 1; /* enable workaround */ 2982 2983 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 2984 kfree(chip); 2985 pci_disable_device(pci); 2986 return err; 2987 } 2988 2989 if (device_type == DEVICE_ALI) { 2990 /* ALI5455 has no ac97 region */ 2991 chip->bmaddr = pci_iomap(pci, 0, 0); 2992 goto port_inited; 2993 } 2994 2995 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 2996 chip->addr = pci_iomap(pci, 2, 0); 2997 else 2998 chip->addr = pci_iomap(pci, 0, 0); 2999 if (!chip->addr) { 3000 dev_err(card->dev, "AC'97 space ioremap problem\n"); 3001 snd_intel8x0_free(chip); 3002 return -EIO; 3003 } 3004 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 3005 chip->bmaddr = pci_iomap(pci, 3, 0); 3006 else 3007 chip->bmaddr = pci_iomap(pci, 1, 0); 3008 3009 port_inited: 3010 if (!chip->bmaddr) { 3011 dev_err(card->dev, "Controller space ioremap problem\n"); 3012 snd_intel8x0_free(chip); 3013 return -EIO; 3014 } 3015 chip->bdbars_count = bdbars[device_type]; 3016 3017 /* initialize offsets */ 3018 switch (device_type) { 3019 case DEVICE_NFORCE: 3020 tbl = nforce_regs; 3021 break; 3022 case DEVICE_ALI: 3023 tbl = ali_regs; 3024 break; 3025 default: 3026 tbl = intel_regs; 3027 break; 3028 } 3029 for (i = 0; i < chip->bdbars_count; i++) { 3030 ichdev = &chip->ichd[i]; 3031 ichdev->ichd = i; 3032 ichdev->reg_offset = tbl[i].offset; 3033 ichdev->int_sta_mask = tbl[i].int_sta_mask; 3034 if (device_type == DEVICE_SIS) { 3035 /* SiS 7012 swaps the registers */ 3036 ichdev->roff_sr = ICH_REG_OFF_PICB; 3037 ichdev->roff_picb = ICH_REG_OFF_SR; 3038 } else { 3039 ichdev->roff_sr = ICH_REG_OFF_SR; 3040 ichdev->roff_picb = ICH_REG_OFF_PICB; 3041 } 3042 if (device_type == DEVICE_ALI) 3043 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 3044 /* SIS7012 handles the pcm data in bytes, others are in samples */ 3045 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 3046 } 3047 3048 /* allocate buffer descriptor lists */ 3049 /* the start of each lists must be aligned to 8 bytes */ 3050 if (snd_dma_alloc_pages(intel8x0_dma_type(chip), snd_dma_pci_data(pci), 3051 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 3052 &chip->bdbars) < 0) { 3053 snd_intel8x0_free(chip); 3054 dev_err(card->dev, "cannot allocate buffer descriptors\n"); 3055 return -ENOMEM; 3056 } 3057 /* tables must be aligned to 8 bytes here, but the kernel pages 3058 are much bigger, so we don't care (on i386) */ 3059 int_sta_masks = 0; 3060 for (i = 0; i < chip->bdbars_count; i++) { 3061 ichdev = &chip->ichd[i]; 3062 ichdev->bdbar = ((__le32 *)chip->bdbars.area) + 3063 (i * ICH_MAX_FRAGS * 2); 3064 ichdev->bdbar_addr = chip->bdbars.addr + 3065 (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 3066 int_sta_masks |= ichdev->int_sta_mask; 3067 } 3068 chip->int_sta_reg = device_type == DEVICE_ALI ? 3069 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 3070 chip->int_sta_mask = int_sta_masks; 3071 3072 pci_set_master(pci); 3073 3074 switch(chip->device_type) { 3075 case DEVICE_INTEL_ICH4: 3076 /* ICH4 can have three codecs */ 3077 chip->max_codecs = 3; 3078 chip->codec_bit = ich_codec_bits; 3079 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 3080 break; 3081 case DEVICE_SIS: 3082 /* recent SIS7012 can have three codecs */ 3083 chip->max_codecs = 3; 3084 chip->codec_bit = sis_codec_bits; 3085 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 3086 break; 3087 default: 3088 /* others up to two codecs */ 3089 chip->max_codecs = 2; 3090 chip->codec_bit = ich_codec_bits; 3091 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 3092 break; 3093 } 3094 for (i = 0; i < chip->max_codecs; i++) 3095 chip->codec_isr_bits |= chip->codec_bit[i]; 3096 3097 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 3098 snd_intel8x0_free(chip); 3099 return err; 3100 } 3101 3102 /* request irq after initializaing int_sta_mask, etc */ 3103 if (request_irq(pci->irq, snd_intel8x0_interrupt, 3104 IRQF_SHARED, KBUILD_MODNAME, chip)) { 3105 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 3106 snd_intel8x0_free(chip); 3107 return -EBUSY; 3108 } 3109 chip->irq = pci->irq; 3110 3111 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3112 snd_intel8x0_free(chip); 3113 return err; 3114 } 3115 3116 *r_intel8x0 = chip; 3117 return 0; 3118 } 3119 3120 static struct shortname_table { 3121 unsigned int id; 3122 const char *s; 3123 } shortnames[] = { 3124 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 3125 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 3126 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 3127 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 3128 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 3129 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 3130 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 3131 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 3132 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 3133 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 3134 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 3135 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 3136 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 3137 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 3138 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 3139 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 3140 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 3141 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 3142 { 0x003a, "NVidia MCP04" }, 3143 { 0x746d, "AMD AMD8111" }, 3144 { 0x7445, "AMD AMD768" }, 3145 { 0x5455, "ALi M5455" }, 3146 { 0, NULL }, 3147 }; 3148 3149 static struct snd_pci_quirk spdif_aclink_defaults[] = { 3150 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), 3151 { } /* end */ 3152 }; 3153 3154 /* look up white/black list for SPDIF over ac-link */ 3155 static int check_default_spdif_aclink(struct pci_dev *pci) 3156 { 3157 const struct snd_pci_quirk *w; 3158 3159 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); 3160 if (w) { 3161 if (w->value) 3162 dev_dbg(&pci->dev, 3163 "Using SPDIF over AC-Link for %s\n", 3164 snd_pci_quirk_name(w)); 3165 else 3166 dev_dbg(&pci->dev, 3167 "Using integrated SPDIF DMA for %s\n", 3168 snd_pci_quirk_name(w)); 3169 return w->value; 3170 } 3171 return 0; 3172 } 3173 3174 static int snd_intel8x0_probe(struct pci_dev *pci, 3175 const struct pci_device_id *pci_id) 3176 { 3177 struct snd_card *card; 3178 struct intel8x0 *chip; 3179 int err; 3180 struct shortname_table *name; 3181 3182 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 3183 if (err < 0) 3184 return err; 3185 3186 if (spdif_aclink < 0) 3187 spdif_aclink = check_default_spdif_aclink(pci); 3188 3189 strcpy(card->driver, "ICH"); 3190 if (!spdif_aclink) { 3191 switch (pci_id->driver_data) { 3192 case DEVICE_NFORCE: 3193 strcpy(card->driver, "NFORCE"); 3194 break; 3195 case DEVICE_INTEL_ICH4: 3196 strcpy(card->driver, "ICH4"); 3197 } 3198 } 3199 3200 strcpy(card->shortname, "Intel ICH"); 3201 for (name = shortnames; name->id; name++) { 3202 if (pci->device == name->id) { 3203 strcpy(card->shortname, name->s); 3204 break; 3205 } 3206 } 3207 3208 if (buggy_irq < 0) { 3209 /* some Nforce[2] and ICH boards have problems with IRQ handling. 3210 * Needs to return IRQ_HANDLED for unknown irqs. 3211 */ 3212 if (pci_id->driver_data == DEVICE_NFORCE) 3213 buggy_irq = 1; 3214 else 3215 buggy_irq = 0; 3216 } 3217 3218 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 3219 &chip)) < 0) { 3220 snd_card_free(card); 3221 return err; 3222 } 3223 card->private_data = chip; 3224 3225 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { 3226 snd_card_free(card); 3227 return err; 3228 } 3229 if ((err = snd_intel8x0_pcm(chip)) < 0) { 3230 snd_card_free(card); 3231 return err; 3232 } 3233 3234 snd_intel8x0_proc_init(chip); 3235 3236 snprintf(card->longname, sizeof(card->longname), 3237 "%s with %s at irq %i", card->shortname, 3238 snd_ac97_get_short_name(chip->ac97[0]), chip->irq); 3239 3240 if (ac97_clock == 0 || ac97_clock == 1) { 3241 if (ac97_clock == 0) { 3242 if (intel8x0_in_clock_list(chip) == 0) 3243 intel8x0_measure_ac97_clock(chip); 3244 } else { 3245 intel8x0_measure_ac97_clock(chip); 3246 } 3247 } 3248 3249 if ((err = snd_card_register(card)) < 0) { 3250 snd_card_free(card); 3251 return err; 3252 } 3253 pci_set_drvdata(pci, card); 3254 return 0; 3255 } 3256 3257 static void snd_intel8x0_remove(struct pci_dev *pci) 3258 { 3259 snd_card_free(pci_get_drvdata(pci)); 3260 } 3261 3262 static struct pci_driver intel8x0_driver = { 3263 .name = KBUILD_MODNAME, 3264 .id_table = snd_intel8x0_ids, 3265 .probe = snd_intel8x0_probe, 3266 .remove = snd_intel8x0_remove, 3267 .driver = { 3268 .pm = INTEL8X0_PM_OPS, 3269 }, 3270 }; 3271 3272 module_pci_driver(intel8x0_driver); 3273