1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA driver for Intel ICH (i8x0) chipsets 4 * 5 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 12 */ 13 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/interrupt.h> 17 #include <linux/init.h> 18 #include <linux/pci.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <sound/core.h> 22 #include <sound/pcm.h> 23 #include <sound/ac97_codec.h> 24 #include <sound/info.h> 25 #include <sound/initval.h> 26 27 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 28 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 29 MODULE_LICENSE("GPL"); 30 31 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 32 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 33 static int ac97_clock; 34 static char *ac97_quirk; 35 static bool buggy_semaphore; 36 static int buggy_irq = -1; /* auto-check */ 37 static bool xbox; 38 static int spdif_aclink = -1; 39 static int inside_vm = -1; 40 41 module_param(index, int, 0444); 42 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 43 module_param(id, charp, 0444); 44 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 45 module_param(ac97_clock, int, 0444); 46 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = allowlist + auto-detect, 1 = force autodetect)."); 47 module_param(ac97_quirk, charp, 0444); 48 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 49 module_param(buggy_semaphore, bool, 0444); 50 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 51 module_param(buggy_irq, bint, 0444); 52 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 53 module_param(xbox, bool, 0444); 54 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 55 module_param(spdif_aclink, int, 0444); 56 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 57 module_param(inside_vm, bint, 0444); 58 MODULE_PARM_DESC(inside_vm, "KVM/Parallels optimization."); 59 60 /* just for backward compatibility */ 61 static bool enable; 62 module_param(enable, bool, 0444); 63 static int joystick; 64 module_param(joystick, int, 0444); 65 66 /* 67 * Direct registers 68 */ 69 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 70 71 #define ICHREG(x) ICH_REG_##x 72 73 #define DEFINE_REGSET(name,base) \ 74 enum { \ 75 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 76 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 77 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 78 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 79 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 80 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 81 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 82 }; 83 84 /* busmaster blocks */ 85 DEFINE_REGSET(OFF, 0); /* offset */ 86 DEFINE_REGSET(PI, 0x00); /* PCM in */ 87 DEFINE_REGSET(PO, 0x10); /* PCM out */ 88 DEFINE_REGSET(MC, 0x20); /* Mic in */ 89 90 /* ICH4 busmaster blocks */ 91 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 92 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 93 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 94 95 /* values for each busmaster block */ 96 97 /* LVI */ 98 #define ICH_REG_LVI_MASK 0x1f 99 100 /* SR */ 101 #define ICH_FIFOE 0x10 /* FIFO error */ 102 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 103 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 104 #define ICH_CELV 0x02 /* current equals last valid */ 105 #define ICH_DCH 0x01 /* DMA controller halted */ 106 107 /* PIV */ 108 #define ICH_REG_PIV_MASK 0x1f /* mask */ 109 110 /* CR */ 111 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 112 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 113 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 114 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 115 #define ICH_STARTBM 0x01 /* start busmaster operation */ 116 117 118 /* global block */ 119 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 120 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 121 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 122 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 123 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 124 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 125 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 126 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ 127 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ 128 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 129 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 130 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 131 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 132 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 133 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 134 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 135 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 136 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 137 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 138 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 139 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 140 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 141 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 142 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 143 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 144 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 145 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 146 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 147 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 148 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 149 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 150 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 151 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 152 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 153 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 154 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 155 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 156 #define ICH_RCS 0x00008000 /* read completion status */ 157 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 158 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 159 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 160 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 161 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 162 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 163 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 164 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 165 #define ICH_POINT 0x00000040 /* playback interrupt */ 166 #define ICH_PIINT 0x00000020 /* capture interrupt */ 167 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 168 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 169 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 170 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 171 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 172 #define ICH_CAS 0x01 /* codec access semaphore */ 173 #define ICH_REG_SDM 0x80 174 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 175 #define ICH_DI2L_SHIFT 6 176 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 177 #define ICH_DI1L_SHIFT 4 178 #define ICH_SE 0x00000008 /* steer enable */ 179 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 180 181 #define ICH_MAX_FRAGS 32 /* max hw frags */ 182 183 184 /* 185 * registers for Ali5455 186 */ 187 188 /* ALi 5455 busmaster blocks */ 189 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 190 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 191 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 192 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 193 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 194 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 195 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 196 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 197 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 198 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 199 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 200 201 enum { 202 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 203 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 204 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 205 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 206 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 207 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 208 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 209 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 210 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 211 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 212 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 213 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 214 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 215 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 216 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 217 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 218 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 219 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 220 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 221 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 222 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 223 }; 224 225 #define ALI_CAS_SEM_BUSY 0x80000000 226 #define ALI_CPR_ADDR_SECONDARY 0x100 227 #define ALI_CPR_ADDR_READ 0x80 228 #define ALI_CSPSR_CODEC_READY 0x08 229 #define ALI_CSPSR_READ_OK 0x02 230 #define ALI_CSPSR_WRITE_OK 0x01 231 232 /* interrupts for the whole chip by interrupt status register finish */ 233 234 #define ALI_INT_MICIN2 (1<<26) 235 #define ALI_INT_PCMIN2 (1<<25) 236 #define ALI_INT_I2SIN (1<<24) 237 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 238 #define ALI_INT_SPDIFIN (1<<22) 239 #define ALI_INT_LFEOUT (1<<21) 240 #define ALI_INT_CENTEROUT (1<<20) 241 #define ALI_INT_CODECSPDIFOUT (1<<19) 242 #define ALI_INT_MICIN (1<<18) 243 #define ALI_INT_PCMOUT (1<<17) 244 #define ALI_INT_PCMIN (1<<16) 245 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 246 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 247 #define ALI_INT_GPIO (1<<1) 248 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ 249 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 250 251 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 252 #define ICH_ALI_SC_AC97_DBL (1<<30) 253 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 254 #define ICH_ALI_SC_IN_BITS (3<<18) 255 #define ICH_ALI_SC_OUT_BITS (3<<16) 256 #define ICH_ALI_SC_6CH_CFG (3<<14) 257 #define ICH_ALI_SC_PCM_4 (1<<8) 258 #define ICH_ALI_SC_PCM_6 (2<<8) 259 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 260 261 #define ICH_ALI_SS_SEC_ID (3<<5) 262 #define ICH_ALI_SS_PRI_ID (3<<3) 263 264 #define ICH_ALI_IF_AC97SP (1<<21) 265 #define ICH_ALI_IF_MC (1<<20) 266 #define ICH_ALI_IF_PI (1<<19) 267 #define ICH_ALI_IF_MC2 (1<<18) 268 #define ICH_ALI_IF_PI2 (1<<17) 269 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 270 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 271 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 272 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 273 #define ICH_ALI_IF_PO_SPDF (1<<3) 274 #define ICH_ALI_IF_PO (1<<1) 275 276 /* 277 * 278 */ 279 280 enum { 281 ICHD_PCMIN, 282 ICHD_PCMOUT, 283 ICHD_MIC, 284 ICHD_MIC2, 285 ICHD_PCM2IN, 286 ICHD_SPBAR, 287 ICHD_LAST = ICHD_SPBAR 288 }; 289 enum { 290 NVD_PCMIN, 291 NVD_PCMOUT, 292 NVD_MIC, 293 NVD_SPBAR, 294 NVD_LAST = NVD_SPBAR 295 }; 296 enum { 297 ALID_PCMIN, 298 ALID_PCMOUT, 299 ALID_MIC, 300 ALID_AC97SPDIFOUT, 301 ALID_SPDIFIN, 302 ALID_SPDIFOUT, 303 ALID_LAST = ALID_SPDIFOUT 304 }; 305 306 #define get_ichdev(substream) (substream->runtime->private_data) 307 308 struct ichdev { 309 unsigned int ichd; /* ich device number */ 310 unsigned long reg_offset; /* offset to bmaddr */ 311 __le32 *bdbar; /* CPU address (32bit) */ 312 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 313 struct snd_pcm_substream *substream; 314 unsigned int physbuf; /* physical address (32bit) */ 315 unsigned int size; 316 unsigned int fragsize; 317 unsigned int fragsize1; 318 unsigned int position; 319 unsigned int pos_shift; 320 unsigned int last_pos; 321 int frags; 322 int lvi; 323 int lvi_frag; 324 int civ; 325 int ack; 326 int ack_reload; 327 unsigned int ack_bit; 328 unsigned int roff_sr; 329 unsigned int roff_picb; 330 unsigned int int_sta_mask; /* interrupt status mask */ 331 unsigned int ali_slot; /* ALI DMA slot */ 332 struct ac97_pcm *pcm; 333 int pcm_open_flag; 334 unsigned int suspended: 1; 335 }; 336 337 struct intel8x0 { 338 unsigned int device_type; 339 340 int irq; 341 342 void __iomem *addr; 343 void __iomem *bmaddr; 344 345 struct pci_dev *pci; 346 struct snd_card *card; 347 348 int pcm_devs; 349 struct snd_pcm *pcm[6]; 350 struct ichdev ichd[6]; 351 352 unsigned multi4: 1, 353 multi6: 1, 354 multi8 :1, 355 dra: 1, 356 smp20bit: 1; 357 unsigned in_ac97_init: 1, 358 in_sdin_init: 1; 359 unsigned in_measurement: 1; /* during ac97 clock measurement */ 360 unsigned fix_nocache: 1; /* workaround for 440MX */ 361 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 362 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 363 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ 364 unsigned inside_vm: 1; /* enable VM optimization */ 365 366 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 367 unsigned int sdm_saved; /* SDM reg value */ 368 369 struct snd_ac97_bus *ac97_bus; 370 struct snd_ac97 *ac97[3]; 371 unsigned int ac97_sdin[3]; 372 unsigned int max_codecs, ncodecs; 373 const unsigned int *codec_bit; 374 unsigned int codec_isr_bits; 375 unsigned int codec_ready_bits; 376 377 spinlock_t reg_lock; 378 379 u32 bdbars_count; 380 struct snd_dma_buffer bdbars; 381 u32 int_sta_reg; /* interrupt status register */ 382 u32 int_sta_mask; /* interrupt status mask */ 383 }; 384 385 static const struct pci_device_id snd_intel8x0_ids[] = { 386 { PCI_VDEVICE(INTEL, 0x2415), DEVICE_INTEL }, /* 82801AA */ 387 { PCI_VDEVICE(INTEL, 0x2425), DEVICE_INTEL }, /* 82901AB */ 388 { PCI_VDEVICE(INTEL, 0x2445), DEVICE_INTEL }, /* 82801BA */ 389 { PCI_VDEVICE(INTEL, 0x2485), DEVICE_INTEL }, /* ICH3 */ 390 { PCI_VDEVICE(INTEL, 0x24c5), DEVICE_INTEL_ICH4 }, /* ICH4 */ 391 { PCI_VDEVICE(INTEL, 0x24d5), DEVICE_INTEL_ICH4 }, /* ICH5 */ 392 { PCI_VDEVICE(INTEL, 0x25a6), DEVICE_INTEL_ICH4 }, /* ESB */ 393 { PCI_VDEVICE(INTEL, 0x266e), DEVICE_INTEL_ICH4 }, /* ICH6 */ 394 { PCI_VDEVICE(INTEL, 0x27de), DEVICE_INTEL_ICH4 }, /* ICH7 */ 395 { PCI_VDEVICE(INTEL, 0x2698), DEVICE_INTEL_ICH4 }, /* ESB2 */ 396 { PCI_VDEVICE(INTEL, 0x7195), DEVICE_INTEL }, /* 440MX */ 397 { PCI_VDEVICE(SI, 0x7012), DEVICE_SIS }, /* SI7012 */ 398 { PCI_VDEVICE(NVIDIA, 0x01b1), DEVICE_NFORCE }, /* NFORCE */ 399 { PCI_VDEVICE(NVIDIA, 0x003a), DEVICE_NFORCE }, /* MCP04 */ 400 { PCI_VDEVICE(NVIDIA, 0x006a), DEVICE_NFORCE }, /* NFORCE2 */ 401 { PCI_VDEVICE(NVIDIA, 0x0059), DEVICE_NFORCE }, /* CK804 */ 402 { PCI_VDEVICE(NVIDIA, 0x008a), DEVICE_NFORCE }, /* CK8 */ 403 { PCI_VDEVICE(NVIDIA, 0x00da), DEVICE_NFORCE }, /* NFORCE3 */ 404 { PCI_VDEVICE(NVIDIA, 0x00ea), DEVICE_NFORCE }, /* CK8S */ 405 { PCI_VDEVICE(NVIDIA, 0x026b), DEVICE_NFORCE }, /* MCP51 */ 406 { PCI_VDEVICE(AMD, 0x746d), DEVICE_INTEL }, /* AMD8111 */ 407 { PCI_VDEVICE(AMD, 0x7445), DEVICE_INTEL }, /* AMD768 */ 408 { PCI_VDEVICE(AL, 0x5455), DEVICE_ALI }, /* Ali5455 */ 409 { 0, } 410 }; 411 412 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 413 414 /* 415 * Lowlevel I/O - busmaster 416 */ 417 418 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) 419 { 420 return ioread8(chip->bmaddr + offset); 421 } 422 423 static inline u16 igetword(struct intel8x0 *chip, u32 offset) 424 { 425 return ioread16(chip->bmaddr + offset); 426 } 427 428 static inline u32 igetdword(struct intel8x0 *chip, u32 offset) 429 { 430 return ioread32(chip->bmaddr + offset); 431 } 432 433 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) 434 { 435 iowrite8(val, chip->bmaddr + offset); 436 } 437 438 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) 439 { 440 iowrite16(val, chip->bmaddr + offset); 441 } 442 443 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) 444 { 445 iowrite32(val, chip->bmaddr + offset); 446 } 447 448 /* 449 * Lowlevel I/O - AC'97 registers 450 */ 451 452 static inline u16 iagetword(struct intel8x0 *chip, u32 offset) 453 { 454 return ioread16(chip->addr + offset); 455 } 456 457 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) 458 { 459 iowrite16(val, chip->addr + offset); 460 } 461 462 /* 463 * Basic I/O 464 */ 465 466 /* 467 * access to AC97 codec via normal i/o (for ICH and SIS7012) 468 */ 469 470 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 471 { 472 int time; 473 474 if (codec > 2) 475 return -EIO; 476 if (chip->in_sdin_init) { 477 /* we don't know the ready bit assignment at the moment */ 478 /* so we check any */ 479 codec = chip->codec_isr_bits; 480 } else { 481 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 482 } 483 484 /* codec ready ? */ 485 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 486 return -EIO; 487 488 if (chip->buggy_semaphore) 489 return 0; /* just ignore ... */ 490 491 /* Anyone holding a semaphore for 1 msec should be shot... */ 492 time = 100; 493 do { 494 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 495 return 0; 496 udelay(10); 497 } while (time--); 498 499 /* access to some forbidden (non existent) ac97 registers will not 500 * reset the semaphore. So even if you don't get the semaphore, still 501 * continue the access. We don't need the semaphore anyway. */ 502 dev_err(chip->card->dev, 503 "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 504 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 505 iagetword(chip, 0); /* clear semaphore flag */ 506 /* I don't care about the semaphore */ 507 return -EBUSY; 508 } 509 510 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 511 unsigned short reg, 512 unsigned short val) 513 { 514 struct intel8x0 *chip = ac97->private_data; 515 516 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 517 if (! chip->in_ac97_init) 518 dev_err(chip->card->dev, 519 "codec_write %d: semaphore is not ready for register 0x%x\n", 520 ac97->num, reg); 521 } 522 iaputword(chip, reg + ac97->num * 0x80, val); 523 } 524 525 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 526 unsigned short reg) 527 { 528 struct intel8x0 *chip = ac97->private_data; 529 unsigned short res; 530 unsigned int tmp; 531 532 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 533 if (! chip->in_ac97_init) 534 dev_err(chip->card->dev, 535 "codec_read %d: semaphore is not ready for register 0x%x\n", 536 ac97->num, reg); 537 res = 0xffff; 538 } else { 539 res = iagetword(chip, reg + ac97->num * 0x80); 540 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 541 /* reset RCS and preserve other R/WC bits */ 542 iputdword(chip, ICHREG(GLOB_STA), tmp & 543 ~(chip->codec_ready_bits | ICH_GSCI)); 544 if (! chip->in_ac97_init) 545 dev_err(chip->card->dev, 546 "codec_read %d: read timeout for register 0x%x\n", 547 ac97->num, reg); 548 res = 0xffff; 549 } 550 } 551 return res; 552 } 553 554 static void snd_intel8x0_codec_read_test(struct intel8x0 *chip, 555 unsigned int codec) 556 { 557 unsigned int tmp; 558 559 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 560 iagetword(chip, codec * 0x80); 561 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 562 /* reset RCS and preserve other R/WC bits */ 563 iputdword(chip, ICHREG(GLOB_STA), tmp & 564 ~(chip->codec_ready_bits | ICH_GSCI)); 565 } 566 } 567 } 568 569 /* 570 * access to AC97 for Ali5455 571 */ 572 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) 573 { 574 int count = 0; 575 for (count = 0; count < 0x7f; count++) { 576 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 577 if (val & mask) 578 return 0; 579 } 580 if (! chip->in_ac97_init) 581 dev_warn(chip->card->dev, "AC97 codec ready timeout.\n"); 582 return -EBUSY; 583 } 584 585 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) 586 { 587 int time = 100; 588 if (chip->buggy_semaphore) 589 return 0; /* just ignore ... */ 590 while (--time && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 591 udelay(1); 592 if (! time && ! chip->in_ac97_init) 593 dev_warn(chip->card->dev, "ali_codec_semaphore timeout\n"); 594 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 595 } 596 597 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) 598 { 599 struct intel8x0 *chip = ac97->private_data; 600 unsigned short data = 0xffff; 601 602 if (snd_intel8x0_ali_codec_semaphore(chip)) 603 goto __err; 604 reg |= ALI_CPR_ADDR_READ; 605 if (ac97->num) 606 reg |= ALI_CPR_ADDR_SECONDARY; 607 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 608 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 609 goto __err; 610 data = igetword(chip, ICHREG(ALI_SPR)); 611 __err: 612 return data; 613 } 614 615 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, 616 unsigned short val) 617 { 618 struct intel8x0 *chip = ac97->private_data; 619 620 if (snd_intel8x0_ali_codec_semaphore(chip)) 621 return; 622 iputword(chip, ICHREG(ALI_CPR), val); 623 if (ac97->num) 624 reg |= ALI_CPR_ADDR_SECONDARY; 625 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 626 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 627 } 628 629 630 /* 631 * DMA I/O 632 */ 633 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 634 { 635 int idx; 636 __le32 *bdbar = ichdev->bdbar; 637 unsigned long port = ichdev->reg_offset; 638 639 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 640 if (ichdev->size == ichdev->fragsize) { 641 ichdev->ack_reload = ichdev->ack = 2; 642 ichdev->fragsize1 = ichdev->fragsize >> 1; 643 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 644 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 645 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 646 ichdev->fragsize1 >> ichdev->pos_shift); 647 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 648 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 649 ichdev->fragsize1 >> ichdev->pos_shift); 650 } 651 ichdev->frags = 2; 652 } else { 653 ichdev->ack_reload = ichdev->ack = 1; 654 ichdev->fragsize1 = ichdev->fragsize; 655 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 656 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + 657 (((idx >> 1) * ichdev->fragsize) % 658 ichdev->size)); 659 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 660 ichdev->fragsize >> ichdev->pos_shift); 661 #if 0 662 dev_dbg(chip->card->dev, "bdbar[%i] = 0x%x [0x%x]\n", 663 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 664 #endif 665 } 666 ichdev->frags = ichdev->size / ichdev->fragsize; 667 } 668 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 669 ichdev->civ = 0; 670 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 671 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 672 ichdev->position = 0; 673 #if 0 674 dev_dbg(chip->card->dev, 675 "lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 676 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, 677 ichdev->fragsize1); 678 #endif 679 /* clear interrupts */ 680 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 681 } 682 683 /* 684 * Interrupt handler 685 */ 686 687 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) 688 { 689 unsigned long port = ichdev->reg_offset; 690 unsigned long flags; 691 int status, civ, i, step; 692 int ack = 0; 693 694 spin_lock_irqsave(&chip->reg_lock, flags); 695 status = igetbyte(chip, port + ichdev->roff_sr); 696 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 697 if (!(status & ICH_BCIS)) { 698 step = 0; 699 } else if (civ == ichdev->civ) { 700 // snd_printd("civ same %d\n", civ); 701 step = 1; 702 ichdev->civ++; 703 ichdev->civ &= ICH_REG_LVI_MASK; 704 } else { 705 step = civ - ichdev->civ; 706 if (step < 0) 707 step += ICH_REG_LVI_MASK + 1; 708 // if (step != 1) 709 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 710 ichdev->civ = civ; 711 } 712 713 ichdev->position += step * ichdev->fragsize1; 714 if (! chip->in_measurement) 715 ichdev->position %= ichdev->size; 716 ichdev->lvi += step; 717 ichdev->lvi &= ICH_REG_LVI_MASK; 718 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 719 for (i = 0; i < step; i++) { 720 ichdev->lvi_frag++; 721 ichdev->lvi_frag %= ichdev->frags; 722 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 723 #if 0 724 dev_dbg(chip->card->dev, 725 "new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 726 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 727 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 728 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 729 #endif 730 if (--ichdev->ack == 0) { 731 ichdev->ack = ichdev->ack_reload; 732 ack = 1; 733 } 734 } 735 spin_unlock_irqrestore(&chip->reg_lock, flags); 736 if (ack && ichdev->substream) { 737 snd_pcm_period_elapsed(ichdev->substream); 738 } 739 iputbyte(chip, port + ichdev->roff_sr, 740 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 741 } 742 743 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 744 { 745 struct intel8x0 *chip = dev_id; 746 struct ichdev *ichdev; 747 unsigned int status; 748 unsigned int i; 749 750 status = igetdword(chip, chip->int_sta_reg); 751 if (status == 0xffffffff) /* we are not yet resumed */ 752 return IRQ_NONE; 753 754 if ((status & chip->int_sta_mask) == 0) { 755 if (status) { 756 /* ack */ 757 iputdword(chip, chip->int_sta_reg, status); 758 if (! chip->buggy_irq) 759 status = 0; 760 } 761 return IRQ_RETVAL(status); 762 } 763 764 for (i = 0; i < chip->bdbars_count; i++) { 765 ichdev = &chip->ichd[i]; 766 if (status & ichdev->int_sta_mask) 767 snd_intel8x0_update(chip, ichdev); 768 } 769 770 /* ack them */ 771 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 772 773 return IRQ_HANDLED; 774 } 775 776 /* 777 * PCM part 778 */ 779 780 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 781 { 782 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 783 struct ichdev *ichdev = get_ichdev(substream); 784 unsigned char val = 0; 785 unsigned long port = ichdev->reg_offset; 786 787 switch (cmd) { 788 case SNDRV_PCM_TRIGGER_RESUME: 789 ichdev->suspended = 0; 790 fallthrough; 791 case SNDRV_PCM_TRIGGER_START: 792 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 793 val = ICH_IOCE | ICH_STARTBM; 794 ichdev->last_pos = ichdev->position; 795 break; 796 case SNDRV_PCM_TRIGGER_SUSPEND: 797 ichdev->suspended = 1; 798 fallthrough; 799 case SNDRV_PCM_TRIGGER_STOP: 800 val = 0; 801 break; 802 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 803 val = ICH_IOCE; 804 break; 805 default: 806 return -EINVAL; 807 } 808 iputbyte(chip, port + ICH_REG_OFF_CR, val); 809 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 810 /* wait until DMA stopped */ 811 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 812 /* reset whole DMA things */ 813 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 814 } 815 return 0; 816 } 817 818 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) 819 { 820 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 821 struct ichdev *ichdev = get_ichdev(substream); 822 unsigned long port = ichdev->reg_offset; 823 static const int fiforeg[] = { 824 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) 825 }; 826 unsigned int val, fifo; 827 828 val = igetdword(chip, ICHREG(ALI_DMACR)); 829 switch (cmd) { 830 case SNDRV_PCM_TRIGGER_RESUME: 831 ichdev->suspended = 0; 832 fallthrough; 833 case SNDRV_PCM_TRIGGER_START: 834 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 835 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 836 /* clear FIFO for synchronization of channels */ 837 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 838 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 839 fifo |= 0x83 << (ichdev->ali_slot % 4); 840 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 841 } 842 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 843 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 844 /* start DMA */ 845 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); 846 break; 847 case SNDRV_PCM_TRIGGER_SUSPEND: 848 ichdev->suspended = 1; 849 fallthrough; 850 case SNDRV_PCM_TRIGGER_STOP: 851 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 852 /* pause */ 853 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); 854 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 855 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 856 ; 857 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 858 break; 859 /* reset whole DMA things */ 860 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 861 /* clear interrupts */ 862 iputbyte(chip, port + ICH_REG_OFF_SR, 863 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 864 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 865 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 866 break; 867 default: 868 return -EINVAL; 869 } 870 return 0; 871 } 872 873 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 874 struct snd_pcm_hw_params *hw_params) 875 { 876 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 877 struct ichdev *ichdev = get_ichdev(substream); 878 int dbl = params_rate(hw_params) > 48000; 879 int err; 880 881 if (ichdev->pcm_open_flag) { 882 snd_ac97_pcm_close(ichdev->pcm); 883 ichdev->pcm_open_flag = 0; 884 } 885 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 886 params_channels(hw_params), 887 ichdev->pcm->r[dbl].slots); 888 if (err >= 0) { 889 ichdev->pcm_open_flag = 1; 890 /* Force SPDIF setting */ 891 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 892 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, 893 params_rate(hw_params)); 894 } 895 return err; 896 } 897 898 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 899 { 900 struct ichdev *ichdev = get_ichdev(substream); 901 902 if (ichdev->pcm_open_flag) { 903 snd_ac97_pcm_close(ichdev->pcm); 904 ichdev->pcm_open_flag = 0; 905 } 906 return 0; 907 } 908 909 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, 910 struct snd_pcm_runtime *runtime) 911 { 912 unsigned int cnt; 913 int dbl = runtime->rate > 48000; 914 915 spin_lock_irq(&chip->reg_lock); 916 switch (chip->device_type) { 917 case DEVICE_ALI: 918 cnt = igetdword(chip, ICHREG(ALI_SCR)); 919 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 920 if (runtime->channels == 4 || dbl) 921 cnt |= ICH_ALI_SC_PCM_4; 922 else if (runtime->channels == 6) 923 cnt |= ICH_ALI_SC_PCM_6; 924 iputdword(chip, ICHREG(ALI_SCR), cnt); 925 break; 926 case DEVICE_SIS: 927 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 928 cnt &= ~ICH_SIS_PCM_246_MASK; 929 if (runtime->channels == 4 || dbl) 930 cnt |= ICH_SIS_PCM_4; 931 else if (runtime->channels == 6) 932 cnt |= ICH_SIS_PCM_6; 933 iputdword(chip, ICHREG(GLOB_CNT), cnt); 934 break; 935 default: 936 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 937 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 938 if (runtime->channels == 4 || dbl) 939 cnt |= ICH_PCM_4; 940 else if (runtime->channels == 6) 941 cnt |= ICH_PCM_6; 942 else if (runtime->channels == 8) 943 cnt |= ICH_PCM_8; 944 if (chip->device_type == DEVICE_NFORCE) { 945 /* reset to 2ch once to keep the 6 channel data in alignment, 946 * to start from Front Left always 947 */ 948 if (cnt & ICH_PCM_246_MASK) { 949 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 950 spin_unlock_irq(&chip->reg_lock); 951 msleep(50); /* grrr... */ 952 spin_lock_irq(&chip->reg_lock); 953 } 954 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 955 if (runtime->sample_bits > 16) 956 cnt |= ICH_PCM_20BIT; 957 } 958 iputdword(chip, ICHREG(GLOB_CNT), cnt); 959 break; 960 } 961 spin_unlock_irq(&chip->reg_lock); 962 } 963 964 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) 965 { 966 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 967 struct snd_pcm_runtime *runtime = substream->runtime; 968 struct ichdev *ichdev = get_ichdev(substream); 969 970 ichdev->physbuf = runtime->dma_addr; 971 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 972 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 973 if (ichdev->ichd == ICHD_PCMOUT) { 974 snd_intel8x0_setup_pcm_out(chip, runtime); 975 if (chip->device_type == DEVICE_INTEL_ICH4) 976 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 977 } 978 snd_intel8x0_setup_periods(chip, ichdev); 979 return 0; 980 } 981 982 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 983 { 984 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 985 struct ichdev *ichdev = get_ichdev(substream); 986 size_t ptr1, ptr; 987 int civ, timeout = 10; 988 unsigned int position; 989 990 spin_lock(&chip->reg_lock); 991 do { 992 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 993 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 994 position = ichdev->position; 995 if (ptr1 == 0) { 996 udelay(10); 997 continue; 998 } 999 if (civ != igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV)) 1000 continue; 1001 1002 /* IO read operation is very expensive inside virtual machine 1003 * as it is emulated. The probability that subsequent PICB read 1004 * will return different result is high enough to loop till 1005 * timeout here. 1006 * Same CIV is strict enough condition to be sure that PICB 1007 * is valid inside VM on emulated card. */ 1008 if (chip->inside_vm) 1009 break; 1010 if (ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1011 break; 1012 } while (timeout--); 1013 ptr = ichdev->last_pos; 1014 if (ptr1 != 0) { 1015 ptr1 <<= ichdev->pos_shift; 1016 ptr = ichdev->fragsize1 - ptr1; 1017 ptr += position; 1018 if (ptr < ichdev->last_pos) { 1019 unsigned int pos_base, last_base; 1020 pos_base = position / ichdev->fragsize1; 1021 last_base = ichdev->last_pos / ichdev->fragsize1; 1022 /* another sanity check; ptr1 can go back to full 1023 * before the base position is updated 1024 */ 1025 if (pos_base == last_base) 1026 ptr = ichdev->last_pos; 1027 } 1028 } 1029 ichdev->last_pos = ptr; 1030 spin_unlock(&chip->reg_lock); 1031 if (ptr >= ichdev->size) 1032 return 0; 1033 return bytes_to_frames(substream->runtime, ptr); 1034 } 1035 1036 static const struct snd_pcm_hardware snd_intel8x0_stream = 1037 { 1038 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1039 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1040 SNDRV_PCM_INFO_MMAP_VALID | 1041 SNDRV_PCM_INFO_PAUSE | 1042 SNDRV_PCM_INFO_RESUME), 1043 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1044 .rates = SNDRV_PCM_RATE_48000, 1045 .rate_min = 48000, 1046 .rate_max = 48000, 1047 .channels_min = 2, 1048 .channels_max = 2, 1049 .buffer_bytes_max = 128 * 1024, 1050 .period_bytes_min = 32, 1051 .period_bytes_max = 128 * 1024, 1052 .periods_min = 1, 1053 .periods_max = 1024, 1054 .fifo_size = 0, 1055 }; 1056 1057 static const unsigned int channels4[] = { 1058 2, 4, 1059 }; 1060 1061 static const struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { 1062 .count = ARRAY_SIZE(channels4), 1063 .list = channels4, 1064 .mask = 0, 1065 }; 1066 1067 static const unsigned int channels6[] = { 1068 2, 4, 6, 1069 }; 1070 1071 static const struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { 1072 .count = ARRAY_SIZE(channels6), 1073 .list = channels6, 1074 .mask = 0, 1075 }; 1076 1077 static const unsigned int channels8[] = { 1078 2, 4, 6, 8, 1079 }; 1080 1081 static const struct snd_pcm_hw_constraint_list hw_constraints_channels8 = { 1082 .count = ARRAY_SIZE(channels8), 1083 .list = channels8, 1084 .mask = 0, 1085 }; 1086 1087 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 1088 { 1089 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1090 struct snd_pcm_runtime *runtime = substream->runtime; 1091 int err; 1092 1093 ichdev->substream = substream; 1094 runtime->hw = snd_intel8x0_stream; 1095 runtime->hw.rates = ichdev->pcm->rates; 1096 snd_pcm_limit_hw_rates(runtime); 1097 if (chip->device_type == DEVICE_SIS) { 1098 runtime->hw.buffer_bytes_max = 64*1024; 1099 runtime->hw.period_bytes_max = 64*1024; 1100 } 1101 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1102 return err; 1103 runtime->private_data = ichdev; 1104 return 0; 1105 } 1106 1107 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) 1108 { 1109 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1110 struct snd_pcm_runtime *runtime = substream->runtime; 1111 int err; 1112 1113 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1114 if (err < 0) 1115 return err; 1116 1117 if (chip->multi8) { 1118 runtime->hw.channels_max = 8; 1119 snd_pcm_hw_constraint_list(runtime, 0, 1120 SNDRV_PCM_HW_PARAM_CHANNELS, 1121 &hw_constraints_channels8); 1122 } else if (chip->multi6) { 1123 runtime->hw.channels_max = 6; 1124 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1125 &hw_constraints_channels6); 1126 } else if (chip->multi4) { 1127 runtime->hw.channels_max = 4; 1128 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1129 &hw_constraints_channels4); 1130 } 1131 if (chip->dra) { 1132 snd_ac97_pcm_double_rate_rules(runtime); 1133 } 1134 if (chip->smp20bit) { 1135 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1136 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1137 } 1138 return 0; 1139 } 1140 1141 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) 1142 { 1143 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1144 1145 chip->ichd[ICHD_PCMOUT].substream = NULL; 1146 return 0; 1147 } 1148 1149 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) 1150 { 1151 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1152 1153 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1154 } 1155 1156 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) 1157 { 1158 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1159 1160 chip->ichd[ICHD_PCMIN].substream = NULL; 1161 return 0; 1162 } 1163 1164 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) 1165 { 1166 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1167 1168 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1169 } 1170 1171 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) 1172 { 1173 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1174 1175 chip->ichd[ICHD_MIC].substream = NULL; 1176 return 0; 1177 } 1178 1179 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) 1180 { 1181 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1182 1183 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1184 } 1185 1186 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) 1187 { 1188 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1189 1190 chip->ichd[ICHD_MIC2].substream = NULL; 1191 return 0; 1192 } 1193 1194 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) 1195 { 1196 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1197 1198 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1199 } 1200 1201 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) 1202 { 1203 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1204 1205 chip->ichd[ICHD_PCM2IN].substream = NULL; 1206 return 0; 1207 } 1208 1209 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) 1210 { 1211 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1212 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1213 1214 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1215 } 1216 1217 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) 1218 { 1219 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1220 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1221 1222 chip->ichd[idx].substream = NULL; 1223 return 0; 1224 } 1225 1226 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) 1227 { 1228 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1229 unsigned int val; 1230 1231 spin_lock_irq(&chip->reg_lock); 1232 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1233 val |= ICH_ALI_IF_AC97SP; 1234 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1235 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1236 spin_unlock_irq(&chip->reg_lock); 1237 1238 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1239 } 1240 1241 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) 1242 { 1243 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1244 unsigned int val; 1245 1246 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1247 spin_lock_irq(&chip->reg_lock); 1248 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1249 val &= ~ICH_ALI_IF_AC97SP; 1250 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1251 spin_unlock_irq(&chip->reg_lock); 1252 1253 return 0; 1254 } 1255 1256 #if 0 // NYI 1257 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) 1258 { 1259 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1260 1261 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1262 } 1263 1264 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) 1265 { 1266 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1267 1268 chip->ichd[ALID_SPDIFIN].substream = NULL; 1269 return 0; 1270 } 1271 1272 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) 1273 { 1274 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1275 1276 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1277 } 1278 1279 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) 1280 { 1281 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1282 1283 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1284 return 0; 1285 } 1286 #endif 1287 1288 static const struct snd_pcm_ops snd_intel8x0_playback_ops = { 1289 .open = snd_intel8x0_playback_open, 1290 .close = snd_intel8x0_playback_close, 1291 .hw_params = snd_intel8x0_hw_params, 1292 .hw_free = snd_intel8x0_hw_free, 1293 .prepare = snd_intel8x0_pcm_prepare, 1294 .trigger = snd_intel8x0_pcm_trigger, 1295 .pointer = snd_intel8x0_pcm_pointer, 1296 }; 1297 1298 static const struct snd_pcm_ops snd_intel8x0_capture_ops = { 1299 .open = snd_intel8x0_capture_open, 1300 .close = snd_intel8x0_capture_close, 1301 .hw_params = snd_intel8x0_hw_params, 1302 .hw_free = snd_intel8x0_hw_free, 1303 .prepare = snd_intel8x0_pcm_prepare, 1304 .trigger = snd_intel8x0_pcm_trigger, 1305 .pointer = snd_intel8x0_pcm_pointer, 1306 }; 1307 1308 static const struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { 1309 .open = snd_intel8x0_mic_open, 1310 .close = snd_intel8x0_mic_close, 1311 .hw_params = snd_intel8x0_hw_params, 1312 .hw_free = snd_intel8x0_hw_free, 1313 .prepare = snd_intel8x0_pcm_prepare, 1314 .trigger = snd_intel8x0_pcm_trigger, 1315 .pointer = snd_intel8x0_pcm_pointer, 1316 }; 1317 1318 static const struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { 1319 .open = snd_intel8x0_mic2_open, 1320 .close = snd_intel8x0_mic2_close, 1321 .hw_params = snd_intel8x0_hw_params, 1322 .hw_free = snd_intel8x0_hw_free, 1323 .prepare = snd_intel8x0_pcm_prepare, 1324 .trigger = snd_intel8x0_pcm_trigger, 1325 .pointer = snd_intel8x0_pcm_pointer, 1326 }; 1327 1328 static const struct snd_pcm_ops snd_intel8x0_capture2_ops = { 1329 .open = snd_intel8x0_capture2_open, 1330 .close = snd_intel8x0_capture2_close, 1331 .hw_params = snd_intel8x0_hw_params, 1332 .hw_free = snd_intel8x0_hw_free, 1333 .prepare = snd_intel8x0_pcm_prepare, 1334 .trigger = snd_intel8x0_pcm_trigger, 1335 .pointer = snd_intel8x0_pcm_pointer, 1336 }; 1337 1338 static const struct snd_pcm_ops snd_intel8x0_spdif_ops = { 1339 .open = snd_intel8x0_spdif_open, 1340 .close = snd_intel8x0_spdif_close, 1341 .hw_params = snd_intel8x0_hw_params, 1342 .hw_free = snd_intel8x0_hw_free, 1343 .prepare = snd_intel8x0_pcm_prepare, 1344 .trigger = snd_intel8x0_pcm_trigger, 1345 .pointer = snd_intel8x0_pcm_pointer, 1346 }; 1347 1348 static const struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { 1349 .open = snd_intel8x0_playback_open, 1350 .close = snd_intel8x0_playback_close, 1351 .hw_params = snd_intel8x0_hw_params, 1352 .hw_free = snd_intel8x0_hw_free, 1353 .prepare = snd_intel8x0_pcm_prepare, 1354 .trigger = snd_intel8x0_ali_trigger, 1355 .pointer = snd_intel8x0_pcm_pointer, 1356 }; 1357 1358 static const struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { 1359 .open = snd_intel8x0_capture_open, 1360 .close = snd_intel8x0_capture_close, 1361 .hw_params = snd_intel8x0_hw_params, 1362 .hw_free = snd_intel8x0_hw_free, 1363 .prepare = snd_intel8x0_pcm_prepare, 1364 .trigger = snd_intel8x0_ali_trigger, 1365 .pointer = snd_intel8x0_pcm_pointer, 1366 }; 1367 1368 static const struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { 1369 .open = snd_intel8x0_mic_open, 1370 .close = snd_intel8x0_mic_close, 1371 .hw_params = snd_intel8x0_hw_params, 1372 .hw_free = snd_intel8x0_hw_free, 1373 .prepare = snd_intel8x0_pcm_prepare, 1374 .trigger = snd_intel8x0_ali_trigger, 1375 .pointer = snd_intel8x0_pcm_pointer, 1376 }; 1377 1378 static const struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { 1379 .open = snd_intel8x0_ali_ac97spdifout_open, 1380 .close = snd_intel8x0_ali_ac97spdifout_close, 1381 .hw_params = snd_intel8x0_hw_params, 1382 .hw_free = snd_intel8x0_hw_free, 1383 .prepare = snd_intel8x0_pcm_prepare, 1384 .trigger = snd_intel8x0_ali_trigger, 1385 .pointer = snd_intel8x0_pcm_pointer, 1386 }; 1387 1388 #if 0 // NYI 1389 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { 1390 .open = snd_intel8x0_ali_spdifin_open, 1391 .close = snd_intel8x0_ali_spdifin_close, 1392 .hw_params = snd_intel8x0_hw_params, 1393 .hw_free = snd_intel8x0_hw_free, 1394 .prepare = snd_intel8x0_pcm_prepare, 1395 .trigger = snd_intel8x0_pcm_trigger, 1396 .pointer = snd_intel8x0_pcm_pointer, 1397 }; 1398 1399 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { 1400 .open = snd_intel8x0_ali_spdifout_open, 1401 .close = snd_intel8x0_ali_spdifout_close, 1402 .hw_params = snd_intel8x0_hw_params, 1403 .hw_free = snd_intel8x0_hw_free, 1404 .prepare = snd_intel8x0_pcm_prepare, 1405 .trigger = snd_intel8x0_pcm_trigger, 1406 .pointer = snd_intel8x0_pcm_pointer, 1407 }; 1408 #endif // NYI 1409 1410 struct ich_pcm_table { 1411 char *suffix; 1412 const struct snd_pcm_ops *playback_ops; 1413 const struct snd_pcm_ops *capture_ops; 1414 size_t prealloc_size; 1415 size_t prealloc_max_size; 1416 int ac97_idx; 1417 }; 1418 1419 #define intel8x0_dma_type(chip) \ 1420 ((chip)->fix_nocache ? SNDRV_DMA_TYPE_DEV_UC : SNDRV_DMA_TYPE_DEV) 1421 1422 static int snd_intel8x0_pcm1(struct intel8x0 *chip, int device, 1423 const struct ich_pcm_table *rec) 1424 { 1425 struct snd_pcm *pcm; 1426 int err; 1427 char name[32]; 1428 1429 if (rec->suffix) 1430 sprintf(name, "Intel ICH - %s", rec->suffix); 1431 else 1432 strcpy(name, "Intel ICH"); 1433 err = snd_pcm_new(chip->card, name, device, 1434 rec->playback_ops ? 1 : 0, 1435 rec->capture_ops ? 1 : 0, &pcm); 1436 if (err < 0) 1437 return err; 1438 1439 if (rec->playback_ops) 1440 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1441 if (rec->capture_ops) 1442 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1443 1444 pcm->private_data = chip; 1445 pcm->info_flags = 0; 1446 if (rec->suffix) 1447 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1448 else 1449 strcpy(pcm->name, chip->card->shortname); 1450 chip->pcm[device] = pcm; 1451 1452 snd_pcm_set_managed_buffer_all(pcm, intel8x0_dma_type(chip), 1453 &chip->pci->dev, 1454 rec->prealloc_size, rec->prealloc_max_size); 1455 1456 if (rec->playback_ops && 1457 rec->playback_ops->open == snd_intel8x0_playback_open) { 1458 struct snd_pcm_chmap *chmap; 1459 int chs = 2; 1460 if (chip->multi8) 1461 chs = 8; 1462 else if (chip->multi6) 1463 chs = 6; 1464 else if (chip->multi4) 1465 chs = 4; 1466 err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK, 1467 snd_pcm_alt_chmaps, chs, 0, 1468 &chmap); 1469 if (err < 0) 1470 return err; 1471 chmap->channel_mask = SND_PCM_CHMAP_MASK_2468; 1472 chip->ac97[0]->chmaps[SNDRV_PCM_STREAM_PLAYBACK] = chmap; 1473 } 1474 1475 return 0; 1476 } 1477 1478 static const struct ich_pcm_table intel_pcms[] = { 1479 { 1480 .playback_ops = &snd_intel8x0_playback_ops, 1481 .capture_ops = &snd_intel8x0_capture_ops, 1482 .prealloc_size = 64 * 1024, 1483 .prealloc_max_size = 128 * 1024, 1484 }, 1485 { 1486 .suffix = "MIC ADC", 1487 .capture_ops = &snd_intel8x0_capture_mic_ops, 1488 .prealloc_size = 0, 1489 .prealloc_max_size = 128 * 1024, 1490 .ac97_idx = ICHD_MIC, 1491 }, 1492 { 1493 .suffix = "MIC2 ADC", 1494 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1495 .prealloc_size = 0, 1496 .prealloc_max_size = 128 * 1024, 1497 .ac97_idx = ICHD_MIC2, 1498 }, 1499 { 1500 .suffix = "ADC2", 1501 .capture_ops = &snd_intel8x0_capture2_ops, 1502 .prealloc_size = 0, 1503 .prealloc_max_size = 128 * 1024, 1504 .ac97_idx = ICHD_PCM2IN, 1505 }, 1506 { 1507 .suffix = "IEC958", 1508 .playback_ops = &snd_intel8x0_spdif_ops, 1509 .prealloc_size = 64 * 1024, 1510 .prealloc_max_size = 128 * 1024, 1511 .ac97_idx = ICHD_SPBAR, 1512 }, 1513 }; 1514 1515 static const struct ich_pcm_table nforce_pcms[] = { 1516 { 1517 .playback_ops = &snd_intel8x0_playback_ops, 1518 .capture_ops = &snd_intel8x0_capture_ops, 1519 .prealloc_size = 64 * 1024, 1520 .prealloc_max_size = 128 * 1024, 1521 }, 1522 { 1523 .suffix = "MIC ADC", 1524 .capture_ops = &snd_intel8x0_capture_mic_ops, 1525 .prealloc_size = 0, 1526 .prealloc_max_size = 128 * 1024, 1527 .ac97_idx = NVD_MIC, 1528 }, 1529 { 1530 .suffix = "IEC958", 1531 .playback_ops = &snd_intel8x0_spdif_ops, 1532 .prealloc_size = 64 * 1024, 1533 .prealloc_max_size = 128 * 1024, 1534 .ac97_idx = NVD_SPBAR, 1535 }, 1536 }; 1537 1538 static const struct ich_pcm_table ali_pcms[] = { 1539 { 1540 .playback_ops = &snd_intel8x0_ali_playback_ops, 1541 .capture_ops = &snd_intel8x0_ali_capture_ops, 1542 .prealloc_size = 64 * 1024, 1543 .prealloc_max_size = 128 * 1024, 1544 }, 1545 { 1546 .suffix = "MIC ADC", 1547 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1548 .prealloc_size = 0, 1549 .prealloc_max_size = 128 * 1024, 1550 .ac97_idx = ALID_MIC, 1551 }, 1552 { 1553 .suffix = "IEC958", 1554 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1555 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ 1556 .prealloc_size = 64 * 1024, 1557 .prealloc_max_size = 128 * 1024, 1558 .ac97_idx = ALID_AC97SPDIFOUT, 1559 }, 1560 #if 0 // NYI 1561 { 1562 .suffix = "HW IEC958", 1563 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1564 .prealloc_size = 64 * 1024, 1565 .prealloc_max_size = 128 * 1024, 1566 }, 1567 #endif 1568 }; 1569 1570 static int snd_intel8x0_pcm(struct intel8x0 *chip) 1571 { 1572 int i, tblsize, device, err; 1573 const struct ich_pcm_table *tbl, *rec; 1574 1575 switch (chip->device_type) { 1576 case DEVICE_INTEL_ICH4: 1577 tbl = intel_pcms; 1578 tblsize = ARRAY_SIZE(intel_pcms); 1579 if (spdif_aclink) 1580 tblsize--; 1581 break; 1582 case DEVICE_NFORCE: 1583 tbl = nforce_pcms; 1584 tblsize = ARRAY_SIZE(nforce_pcms); 1585 if (spdif_aclink) 1586 tblsize--; 1587 break; 1588 case DEVICE_ALI: 1589 tbl = ali_pcms; 1590 tblsize = ARRAY_SIZE(ali_pcms); 1591 break; 1592 default: 1593 tbl = intel_pcms; 1594 tblsize = 2; 1595 break; 1596 } 1597 1598 device = 0; 1599 for (i = 0; i < tblsize; i++) { 1600 rec = tbl + i; 1601 if (i > 0 && rec->ac97_idx) { 1602 /* activate PCM only when associated AC'97 codec */ 1603 if (! chip->ichd[rec->ac97_idx].pcm) 1604 continue; 1605 } 1606 err = snd_intel8x0_pcm1(chip, device, rec); 1607 if (err < 0) 1608 return err; 1609 device++; 1610 } 1611 1612 chip->pcm_devs = device; 1613 return 0; 1614 } 1615 1616 1617 /* 1618 * Mixer part 1619 */ 1620 1621 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1622 { 1623 struct intel8x0 *chip = bus->private_data; 1624 chip->ac97_bus = NULL; 1625 } 1626 1627 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 1628 { 1629 struct intel8x0 *chip = ac97->private_data; 1630 chip->ac97[ac97->num] = NULL; 1631 } 1632 1633 static const struct ac97_pcm ac97_pcm_defs[] = { 1634 /* front PCM */ 1635 { 1636 .exclusive = 1, 1637 .r = { { 1638 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1639 (1 << AC97_SLOT_PCM_RIGHT) | 1640 (1 << AC97_SLOT_PCM_CENTER) | 1641 (1 << AC97_SLOT_PCM_SLEFT) | 1642 (1 << AC97_SLOT_PCM_SRIGHT) | 1643 (1 << AC97_SLOT_LFE) 1644 }, 1645 { 1646 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1647 (1 << AC97_SLOT_PCM_RIGHT) | 1648 (1 << AC97_SLOT_PCM_LEFT_0) | 1649 (1 << AC97_SLOT_PCM_RIGHT_0) 1650 } 1651 } 1652 }, 1653 /* PCM IN #1 */ 1654 { 1655 .stream = 1, 1656 .exclusive = 1, 1657 .r = { { 1658 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1659 (1 << AC97_SLOT_PCM_RIGHT) 1660 } 1661 } 1662 }, 1663 /* MIC IN #1 */ 1664 { 1665 .stream = 1, 1666 .exclusive = 1, 1667 .r = { { 1668 .slots = (1 << AC97_SLOT_MIC) 1669 } 1670 } 1671 }, 1672 /* S/PDIF PCM */ 1673 { 1674 .exclusive = 1, 1675 .spdif = 1, 1676 .r = { { 1677 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1678 (1 << AC97_SLOT_SPDIF_RIGHT2) 1679 } 1680 } 1681 }, 1682 /* PCM IN #2 */ 1683 { 1684 .stream = 1, 1685 .exclusive = 1, 1686 .r = { { 1687 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1688 (1 << AC97_SLOT_PCM_RIGHT) 1689 } 1690 } 1691 }, 1692 /* MIC IN #2 */ 1693 { 1694 .stream = 1, 1695 .exclusive = 1, 1696 .r = { { 1697 .slots = (1 << AC97_SLOT_MIC) 1698 } 1699 } 1700 }, 1701 }; 1702 1703 static const struct ac97_quirk ac97_quirks[] = { 1704 { 1705 .subvendor = 0x0e11, 1706 .subdevice = 0x000e, 1707 .name = "Compaq Deskpro EN", /* AD1885 */ 1708 .type = AC97_TUNE_HP_ONLY 1709 }, 1710 { 1711 .subvendor = 0x0e11, 1712 .subdevice = 0x008a, 1713 .name = "Compaq Evo W4000", /* AD1885 */ 1714 .type = AC97_TUNE_HP_ONLY 1715 }, 1716 { 1717 .subvendor = 0x0e11, 1718 .subdevice = 0x00b8, 1719 .name = "Compaq Evo D510C", 1720 .type = AC97_TUNE_HP_ONLY 1721 }, 1722 { 1723 .subvendor = 0x0e11, 1724 .subdevice = 0x0860, 1725 .name = "HP/Compaq nx7010", 1726 .type = AC97_TUNE_MUTE_LED 1727 }, 1728 { 1729 .subvendor = 0x1014, 1730 .subdevice = 0x0534, 1731 .name = "ThinkPad X31", 1732 .type = AC97_TUNE_INV_EAPD 1733 }, 1734 { 1735 .subvendor = 0x1014, 1736 .subdevice = 0x1f00, 1737 .name = "MS-9128", 1738 .type = AC97_TUNE_ALC_JACK 1739 }, 1740 { 1741 .subvendor = 0x1014, 1742 .subdevice = 0x0267, 1743 .name = "IBM NetVista A30p", /* AD1981B */ 1744 .type = AC97_TUNE_HP_ONLY 1745 }, 1746 { 1747 .subvendor = 0x1025, 1748 .subdevice = 0x0082, 1749 .name = "Acer Travelmate 2310", 1750 .type = AC97_TUNE_HP_ONLY 1751 }, 1752 { 1753 .subvendor = 0x1025, 1754 .subdevice = 0x0083, 1755 .name = "Acer Aspire 3003LCi", 1756 .type = AC97_TUNE_HP_ONLY 1757 }, 1758 { 1759 .subvendor = 0x1028, 1760 .subdevice = 0x00d8, 1761 .name = "Dell Precision 530", /* AD1885 */ 1762 .type = AC97_TUNE_HP_ONLY 1763 }, 1764 { 1765 .subvendor = 0x1028, 1766 .subdevice = 0x010d, 1767 .name = "Dell", /* which model? AD1885 */ 1768 .type = AC97_TUNE_HP_ONLY 1769 }, 1770 { 1771 .subvendor = 0x1028, 1772 .subdevice = 0x0126, 1773 .name = "Dell Optiplex GX260", /* AD1981A */ 1774 .type = AC97_TUNE_HP_ONLY 1775 }, 1776 { 1777 .subvendor = 0x1028, 1778 .subdevice = 0x012c, 1779 .name = "Dell Precision 650", /* AD1981A */ 1780 .type = AC97_TUNE_HP_ONLY 1781 }, 1782 { 1783 .subvendor = 0x1028, 1784 .subdevice = 0x012d, 1785 .name = "Dell Precision 450", /* AD1981B*/ 1786 .type = AC97_TUNE_HP_ONLY 1787 }, 1788 { 1789 .subvendor = 0x1028, 1790 .subdevice = 0x0147, 1791 .name = "Dell", /* which model? AD1981B*/ 1792 .type = AC97_TUNE_HP_ONLY 1793 }, 1794 { 1795 .subvendor = 0x1028, 1796 .subdevice = 0x0151, 1797 .name = "Dell Optiplex GX270", /* AD1981B */ 1798 .type = AC97_TUNE_HP_ONLY 1799 }, 1800 { 1801 .subvendor = 0x1028, 1802 .subdevice = 0x014e, 1803 .name = "Dell D800", /* STAC9750/51 */ 1804 .type = AC97_TUNE_HP_ONLY 1805 }, 1806 { 1807 .subvendor = 0x1028, 1808 .subdevice = 0x0163, 1809 .name = "Dell Unknown", /* STAC9750/51 */ 1810 .type = AC97_TUNE_HP_ONLY 1811 }, 1812 { 1813 .subvendor = 0x1028, 1814 .subdevice = 0x016a, 1815 .name = "Dell Inspiron 8600", /* STAC9750/51 */ 1816 .type = AC97_TUNE_HP_ONLY 1817 }, 1818 { 1819 .subvendor = 0x1028, 1820 .subdevice = 0x0182, 1821 .name = "Dell Latitude D610", /* STAC9750/51 */ 1822 .type = AC97_TUNE_HP_ONLY 1823 }, 1824 { 1825 .subvendor = 0x1028, 1826 .subdevice = 0x0186, 1827 .name = "Dell Latitude D810", /* cf. Malone #41015 */ 1828 .type = AC97_TUNE_HP_MUTE_LED 1829 }, 1830 { 1831 .subvendor = 0x1028, 1832 .subdevice = 0x0188, 1833 .name = "Dell Inspiron 6000", 1834 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */ 1835 }, 1836 { 1837 .subvendor = 0x1028, 1838 .subdevice = 0x0189, 1839 .name = "Dell Inspiron 9300", 1840 .type = AC97_TUNE_HP_MUTE_LED 1841 }, 1842 { 1843 .subvendor = 0x1028, 1844 .subdevice = 0x0191, 1845 .name = "Dell Inspiron 8600", 1846 .type = AC97_TUNE_HP_ONLY 1847 }, 1848 { 1849 .subvendor = 0x103c, 1850 .subdevice = 0x006d, 1851 .name = "HP zv5000", 1852 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1853 }, 1854 { /* FIXME: which codec? */ 1855 .subvendor = 0x103c, 1856 .subdevice = 0x00c3, 1857 .name = "HP xw6000", 1858 .type = AC97_TUNE_HP_ONLY 1859 }, 1860 { 1861 .subvendor = 0x103c, 1862 .subdevice = 0x088c, 1863 .name = "HP nc8000", 1864 .type = AC97_TUNE_HP_MUTE_LED 1865 }, 1866 { 1867 .subvendor = 0x103c, 1868 .subdevice = 0x0890, 1869 .name = "HP nc6000", 1870 .type = AC97_TUNE_MUTE_LED 1871 }, 1872 { 1873 .subvendor = 0x103c, 1874 .subdevice = 0x129d, 1875 .name = "HP xw8000", 1876 .type = AC97_TUNE_HP_ONLY 1877 }, 1878 { 1879 .subvendor = 0x103c, 1880 .subdevice = 0x0938, 1881 .name = "HP nc4200", 1882 .type = AC97_TUNE_HP_MUTE_LED 1883 }, 1884 { 1885 .subvendor = 0x103c, 1886 .subdevice = 0x099c, 1887 .name = "HP nx6110/nc6120", 1888 .type = AC97_TUNE_HP_MUTE_LED 1889 }, 1890 { 1891 .subvendor = 0x103c, 1892 .subdevice = 0x0944, 1893 .name = "HP nc6220", 1894 .type = AC97_TUNE_HP_MUTE_LED 1895 }, 1896 { 1897 .subvendor = 0x103c, 1898 .subdevice = 0x0934, 1899 .name = "HP nc8220", 1900 .type = AC97_TUNE_HP_MUTE_LED 1901 }, 1902 { 1903 .subvendor = 0x103c, 1904 .subdevice = 0x12f1, 1905 .name = "HP xw8200", /* AD1981B*/ 1906 .type = AC97_TUNE_HP_ONLY 1907 }, 1908 { 1909 .subvendor = 0x103c, 1910 .subdevice = 0x12f2, 1911 .name = "HP xw6200", 1912 .type = AC97_TUNE_HP_ONLY 1913 }, 1914 { 1915 .subvendor = 0x103c, 1916 .subdevice = 0x3008, 1917 .name = "HP xw4200", /* AD1981B*/ 1918 .type = AC97_TUNE_HP_ONLY 1919 }, 1920 { 1921 .subvendor = 0x104d, 1922 .subdevice = 0x8144, 1923 .name = "Sony", 1924 .type = AC97_TUNE_INV_EAPD 1925 }, 1926 { 1927 .subvendor = 0x104d, 1928 .subdevice = 0x8197, 1929 .name = "Sony S1XP", 1930 .type = AC97_TUNE_INV_EAPD 1931 }, 1932 { 1933 .subvendor = 0x104d, 1934 .subdevice = 0x81c0, 1935 .name = "Sony VAIO VGN-T350P", /*AD1981B*/ 1936 .type = AC97_TUNE_INV_EAPD 1937 }, 1938 { 1939 .subvendor = 0x104d, 1940 .subdevice = 0x81c5, 1941 .name = "Sony VAIO VGN-B1VP", /*AD1981B*/ 1942 .type = AC97_TUNE_INV_EAPD 1943 }, 1944 { 1945 .subvendor = 0x1043, 1946 .subdevice = 0x80f3, 1947 .name = "ASUS ICH5/AD1985", 1948 .type = AC97_TUNE_AD_SHARING 1949 }, 1950 { 1951 .subvendor = 0x10cf, 1952 .subdevice = 0x11c3, 1953 .name = "Fujitsu-Siemens E4010", 1954 .type = AC97_TUNE_HP_ONLY 1955 }, 1956 { 1957 .subvendor = 0x10cf, 1958 .subdevice = 0x1225, 1959 .name = "Fujitsu-Siemens T3010", 1960 .type = AC97_TUNE_HP_ONLY 1961 }, 1962 { 1963 .subvendor = 0x10cf, 1964 .subdevice = 0x1253, 1965 .name = "Fujitsu S6210", /* STAC9750/51 */ 1966 .type = AC97_TUNE_HP_ONLY 1967 }, 1968 { 1969 .subvendor = 0x10cf, 1970 .subdevice = 0x127d, 1971 .name = "Fujitsu Lifebook P7010", 1972 .type = AC97_TUNE_HP_ONLY 1973 }, 1974 { 1975 .subvendor = 0x10cf, 1976 .subdevice = 0x127e, 1977 .name = "Fujitsu Lifebook C1211D", 1978 .type = AC97_TUNE_HP_ONLY 1979 }, 1980 { 1981 .subvendor = 0x10cf, 1982 .subdevice = 0x12ec, 1983 .name = "Fujitsu-Siemens 4010", 1984 .type = AC97_TUNE_HP_ONLY 1985 }, 1986 { 1987 .subvendor = 0x10cf, 1988 .subdevice = 0x12f2, 1989 .name = "Fujitsu-Siemens Celsius H320", 1990 .type = AC97_TUNE_SWAP_HP 1991 }, 1992 { 1993 .subvendor = 0x10f1, 1994 .subdevice = 0x2665, 1995 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 1996 .type = AC97_TUNE_HP_ONLY 1997 }, 1998 { 1999 .subvendor = 0x10f1, 2000 .subdevice = 0x2885, 2001 .name = "AMD64 Mobo", /* ALC650 */ 2002 .type = AC97_TUNE_HP_ONLY 2003 }, 2004 { 2005 .subvendor = 0x10f1, 2006 .subdevice = 0x2895, 2007 .name = "Tyan Thunder K8WE", 2008 .type = AC97_TUNE_HP_ONLY 2009 }, 2010 { 2011 .subvendor = 0x10f7, 2012 .subdevice = 0x834c, 2013 .name = "Panasonic CF-R4", 2014 .type = AC97_TUNE_HP_ONLY, 2015 }, 2016 { 2017 .subvendor = 0x110a, 2018 .subdevice = 0x0056, 2019 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 2020 .type = AC97_TUNE_HP_ONLY 2021 }, 2022 { 2023 .subvendor = 0x11d4, 2024 .subdevice = 0x5375, 2025 .name = "ADI AD1985 (discrete)", 2026 .type = AC97_TUNE_HP_ONLY 2027 }, 2028 { 2029 .subvendor = 0x1462, 2030 .subdevice = 0x5470, 2031 .name = "MSI P4 ATX 645 Ultra", 2032 .type = AC97_TUNE_HP_ONLY 2033 }, 2034 { 2035 .subvendor = 0x161f, 2036 .subdevice = 0x202f, 2037 .name = "Gateway M520", 2038 .type = AC97_TUNE_INV_EAPD 2039 }, 2040 { 2041 .subvendor = 0x161f, 2042 .subdevice = 0x203a, 2043 .name = "Gateway 4525GZ", /* AD1981B */ 2044 .type = AC97_TUNE_INV_EAPD 2045 }, 2046 { 2047 .subvendor = 0x1734, 2048 .subdevice = 0x0088, 2049 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 2050 .type = AC97_TUNE_HP_ONLY 2051 }, 2052 { 2053 .subvendor = 0x8086, 2054 .subdevice = 0x2000, 2055 .mask = 0xfff0, 2056 .name = "Intel ICH5/AD1985", 2057 .type = AC97_TUNE_AD_SHARING 2058 }, 2059 { 2060 .subvendor = 0x8086, 2061 .subdevice = 0x4000, 2062 .mask = 0xfff0, 2063 .name = "Intel ICH5/AD1985", 2064 .type = AC97_TUNE_AD_SHARING 2065 }, 2066 { 2067 .subvendor = 0x8086, 2068 .subdevice = 0x4856, 2069 .name = "Intel D845WN (82801BA)", 2070 .type = AC97_TUNE_SWAP_HP 2071 }, 2072 { 2073 .subvendor = 0x8086, 2074 .subdevice = 0x4d44, 2075 .name = "Intel D850EMV2", /* AD1885 */ 2076 .type = AC97_TUNE_HP_ONLY 2077 }, 2078 { 2079 .subvendor = 0x8086, 2080 .subdevice = 0x4d56, 2081 .name = "Intel ICH/AD1885", 2082 .type = AC97_TUNE_HP_ONLY 2083 }, 2084 { 2085 .subvendor = 0x8086, 2086 .subdevice = 0x6000, 2087 .mask = 0xfff0, 2088 .name = "Intel ICH5/AD1985", 2089 .type = AC97_TUNE_AD_SHARING 2090 }, 2091 { 2092 .subvendor = 0x8086, 2093 .subdevice = 0xe000, 2094 .mask = 0xfff0, 2095 .name = "Intel ICH5/AD1985", 2096 .type = AC97_TUNE_AD_SHARING 2097 }, 2098 #if 0 /* FIXME: this seems wrong on most boards */ 2099 { 2100 .subvendor = 0x8086, 2101 .subdevice = 0xa000, 2102 .mask = 0xfff0, 2103 .name = "Intel ICH5/AD1985", 2104 .type = AC97_TUNE_HP_ONLY 2105 }, 2106 #endif 2107 { } /* terminator */ 2108 }; 2109 2110 static int snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, 2111 const char *quirk_override) 2112 { 2113 struct snd_ac97_bus *pbus; 2114 struct snd_ac97_template ac97; 2115 int err; 2116 unsigned int i, codecs; 2117 unsigned int glob_sta = 0; 2118 const struct snd_ac97_bus_ops *ops; 2119 static const struct snd_ac97_bus_ops standard_bus_ops = { 2120 .write = snd_intel8x0_codec_write, 2121 .read = snd_intel8x0_codec_read, 2122 }; 2123 static const struct snd_ac97_bus_ops ali_bus_ops = { 2124 .write = snd_intel8x0_ali_codec_write, 2125 .read = snd_intel8x0_ali_codec_read, 2126 }; 2127 2128 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 2129 if (!spdif_aclink) { 2130 switch (chip->device_type) { 2131 case DEVICE_NFORCE: 2132 chip->spdif_idx = NVD_SPBAR; 2133 break; 2134 case DEVICE_ALI: 2135 chip->spdif_idx = ALID_AC97SPDIFOUT; 2136 break; 2137 case DEVICE_INTEL_ICH4: 2138 chip->spdif_idx = ICHD_SPBAR; 2139 break; 2140 } 2141 } 2142 2143 chip->in_ac97_init = 1; 2144 2145 memset(&ac97, 0, sizeof(ac97)); 2146 ac97.private_data = chip; 2147 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2148 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 2149 if (chip->xbox) 2150 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2151 if (chip->device_type != DEVICE_ALI) { 2152 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2153 ops = &standard_bus_ops; 2154 chip->in_sdin_init = 1; 2155 codecs = 0; 2156 for (i = 0; i < chip->max_codecs; i++) { 2157 if (! (glob_sta & chip->codec_bit[i])) 2158 continue; 2159 if (chip->device_type == DEVICE_INTEL_ICH4) { 2160 snd_intel8x0_codec_read_test(chip, codecs); 2161 chip->ac97_sdin[codecs] = 2162 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2163 if (snd_BUG_ON(chip->ac97_sdin[codecs] >= 3)) 2164 chip->ac97_sdin[codecs] = 0; 2165 } else 2166 chip->ac97_sdin[codecs] = i; 2167 codecs++; 2168 } 2169 chip->in_sdin_init = 0; 2170 if (! codecs) 2171 codecs = 1; 2172 } else { 2173 ops = &ali_bus_ops; 2174 codecs = 1; 2175 /* detect the secondary codec */ 2176 for (i = 0; i < 100; i++) { 2177 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2178 if (reg & 0x40) { 2179 codecs = 2; 2180 break; 2181 } 2182 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2183 udelay(1); 2184 } 2185 } 2186 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2187 goto __err; 2188 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2189 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2190 pbus->clock = ac97_clock; 2191 /* FIXME: my test board doesn't work well with VRA... */ 2192 if (chip->device_type == DEVICE_ALI) 2193 pbus->no_vra = 1; 2194 else 2195 pbus->dra = 1; 2196 chip->ac97_bus = pbus; 2197 chip->ncodecs = codecs; 2198 2199 ac97.pci = chip->pci; 2200 for (i = 0; i < codecs; i++) { 2201 ac97.num = i; 2202 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2203 if (err != -EACCES) 2204 dev_err(chip->card->dev, 2205 "Unable to initialize codec #%d\n", i); 2206 if (i == 0) 2207 goto __err; 2208 } 2209 } 2210 /* tune up the primary codec */ 2211 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2212 /* enable separate SDINs for ICH4 */ 2213 if (chip->device_type == DEVICE_INTEL_ICH4) 2214 pbus->isdin = 1; 2215 /* find the available PCM streams */ 2216 i = ARRAY_SIZE(ac97_pcm_defs); 2217 if (chip->device_type != DEVICE_INTEL_ICH4) 2218 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2219 if (chip->spdif_idx < 0) 2220 i--; /* do not allocate S/PDIF */ 2221 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2222 if (err < 0) 2223 goto __err; 2224 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2225 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2226 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2227 if (chip->spdif_idx >= 0) 2228 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2229 if (chip->device_type == DEVICE_INTEL_ICH4) { 2230 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2231 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2232 } 2233 /* enable separate SDINs for ICH4 */ 2234 if (chip->device_type == DEVICE_INTEL_ICH4) { 2235 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2236 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2237 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2238 if (pcm) { 2239 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2240 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2241 for (i = 1; i < 4; i++) { 2242 if (pcm->r[0].codec[i]) { 2243 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2244 break; 2245 } 2246 } 2247 } else { 2248 tmp &= ~ICH_SE; /* steer disable */ 2249 } 2250 iputbyte(chip, ICHREG(SDM), tmp); 2251 } 2252 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2253 chip->multi4 = 1; 2254 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) { 2255 chip->multi6 = 1; 2256 if (chip->ac97[0]->flags & AC97_HAS_8CH) 2257 chip->multi8 = 1; 2258 } 2259 } 2260 if (pbus->pcms[0].r[1].rslots[0]) { 2261 chip->dra = 1; 2262 } 2263 if (chip->device_type == DEVICE_INTEL_ICH4) { 2264 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2265 chip->smp20bit = 1; 2266 } 2267 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2268 /* 48kHz only */ 2269 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2270 } 2271 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2272 /* use slot 10/11 for SPDIF */ 2273 u32 val; 2274 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2275 val |= ICH_PCM_SPDIF_1011; 2276 iputdword(chip, ICHREG(GLOB_CNT), val); 2277 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2278 } 2279 chip->in_ac97_init = 0; 2280 return 0; 2281 2282 __err: 2283 /* clear the cold-reset bit for the next chance */ 2284 if (chip->device_type != DEVICE_ALI) 2285 iputdword(chip, ICHREG(GLOB_CNT), 2286 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2287 return err; 2288 } 2289 2290 2291 /* 2292 * 2293 */ 2294 2295 static void do_ali_reset(struct intel8x0 *chip) 2296 { 2297 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2298 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2299 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2300 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2301 iputdword(chip, ICHREG(ALI_INTERFACECR), 2302 ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2303 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2304 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2305 } 2306 2307 #ifdef CONFIG_SND_AC97_POWER_SAVE 2308 static const struct snd_pci_quirk ich_chip_reset_mode[] = { 2309 SND_PCI_QUIRK(0x1014, 0x051f, "Thinkpad R32", 1), 2310 { } /* end */ 2311 }; 2312 2313 static int snd_intel8x0_ich_chip_cold_reset(struct intel8x0 *chip) 2314 { 2315 unsigned int cnt; 2316 /* ACLink on, 2 channels */ 2317 2318 if (snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2319 return -EIO; 2320 2321 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2322 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2323 2324 /* do cold reset - the full ac97 powerdown may leave the controller 2325 * in a warm state but actually it cannot communicate with the codec. 2326 */ 2327 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); 2328 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2329 udelay(10); 2330 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); 2331 msleep(1); 2332 return 0; 2333 } 2334 #define snd_intel8x0_ich_chip_can_cold_reset(chip) \ 2335 (!snd_pci_quirk_lookup(chip->pci, ich_chip_reset_mode)) 2336 #else 2337 #define snd_intel8x0_ich_chip_cold_reset(chip) 0 2338 #define snd_intel8x0_ich_chip_can_cold_reset(chip) (0) 2339 #endif 2340 2341 static int snd_intel8x0_ich_chip_reset(struct intel8x0 *chip) 2342 { 2343 unsigned long end_time; 2344 unsigned int cnt; 2345 /* ACLink on, 2 channels */ 2346 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2347 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2348 /* finish cold or do warm reset */ 2349 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2350 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2351 end_time = (jiffies + (HZ / 4)) + 1; 2352 do { 2353 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2354 return 0; 2355 schedule_timeout_uninterruptible(1); 2356 } while (time_after_eq(end_time, jiffies)); 2357 dev_err(chip->card->dev, "AC'97 warm reset still in progress? [0x%x]\n", 2358 igetdword(chip, ICHREG(GLOB_CNT))); 2359 return -EIO; 2360 } 2361 2362 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) 2363 { 2364 unsigned long end_time; 2365 unsigned int status, nstatus; 2366 unsigned int cnt; 2367 int err; 2368 2369 /* put logic to right state */ 2370 /* first clear status bits */ 2371 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2372 if (chip->device_type == DEVICE_NFORCE) 2373 status |= ICH_NVSPINT; 2374 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2375 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2376 2377 if (snd_intel8x0_ich_chip_can_cold_reset(chip)) 2378 err = snd_intel8x0_ich_chip_cold_reset(chip); 2379 else 2380 err = snd_intel8x0_ich_chip_reset(chip); 2381 if (err < 0) 2382 return err; 2383 2384 if (probing) { 2385 /* wait for any codec ready status. 2386 * Once it becomes ready it should remain ready 2387 * as long as we do not disable the ac97 link. 2388 */ 2389 end_time = jiffies + HZ; 2390 do { 2391 status = igetdword(chip, ICHREG(GLOB_STA)) & 2392 chip->codec_isr_bits; 2393 if (status) 2394 break; 2395 schedule_timeout_uninterruptible(1); 2396 } while (time_after_eq(end_time, jiffies)); 2397 if (! status) { 2398 /* no codec is found */ 2399 dev_err(chip->card->dev, 2400 "codec_ready: codec is not ready [0x%x]\n", 2401 igetdword(chip, ICHREG(GLOB_STA))); 2402 return -EIO; 2403 } 2404 2405 /* wait for other codecs ready status. */ 2406 end_time = jiffies + HZ / 4; 2407 while (status != chip->codec_isr_bits && 2408 time_after_eq(end_time, jiffies)) { 2409 schedule_timeout_uninterruptible(1); 2410 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2411 chip->codec_isr_bits; 2412 } 2413 2414 } else { 2415 /* resume phase */ 2416 int i; 2417 status = 0; 2418 for (i = 0; i < chip->ncodecs; i++) 2419 if (chip->ac97[i]) 2420 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2421 /* wait until all the probed codecs are ready */ 2422 end_time = jiffies + HZ; 2423 do { 2424 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 2425 chip->codec_isr_bits; 2426 if (status == nstatus) 2427 break; 2428 schedule_timeout_uninterruptible(1); 2429 } while (time_after_eq(end_time, jiffies)); 2430 } 2431 2432 if (chip->device_type == DEVICE_SIS) { 2433 /* unmute the output on SIS7012 */ 2434 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2435 } 2436 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2437 /* enable SPDIF interrupt */ 2438 unsigned int val; 2439 pci_read_config_dword(chip->pci, 0x4c, &val); 2440 val |= 0x1000000; 2441 pci_write_config_dword(chip->pci, 0x4c, val); 2442 } 2443 return 0; 2444 } 2445 2446 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) 2447 { 2448 u32 reg; 2449 int i = 0; 2450 2451 reg = igetdword(chip, ICHREG(ALI_SCR)); 2452 if ((reg & 2) == 0) /* Cold required */ 2453 reg |= 2; 2454 else 2455 reg |= 1; /* Warm */ 2456 reg &= ~0x80000000; /* ACLink on */ 2457 iputdword(chip, ICHREG(ALI_SCR), reg); 2458 2459 for (i = 0; i < HZ / 2; i++) { 2460 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2461 goto __ok; 2462 schedule_timeout_uninterruptible(1); 2463 } 2464 dev_err(chip->card->dev, "AC'97 reset failed.\n"); 2465 if (probing) 2466 return -EIO; 2467 2468 __ok: 2469 for (i = 0; i < HZ / 2; i++) { 2470 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2471 if (reg & 0x80) /* primary codec */ 2472 break; 2473 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2474 schedule_timeout_uninterruptible(1); 2475 } 2476 2477 do_ali_reset(chip); 2478 return 0; 2479 } 2480 2481 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) 2482 { 2483 unsigned int i, timeout; 2484 int err; 2485 2486 if (chip->device_type != DEVICE_ALI) { 2487 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2488 return err; 2489 iagetword(chip, 0); /* clear semaphore flag */ 2490 } else { 2491 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2492 return err; 2493 } 2494 2495 /* disable interrupts */ 2496 for (i = 0; i < chip->bdbars_count; i++) 2497 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2498 /* reset channels */ 2499 for (i = 0; i < chip->bdbars_count; i++) 2500 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2501 for (i = 0; i < chip->bdbars_count; i++) { 2502 timeout = 100000; 2503 while (--timeout != 0) { 2504 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) 2505 break; 2506 } 2507 if (timeout == 0) 2508 dev_err(chip->card->dev, "reset of registers failed?\n"); 2509 } 2510 /* initialize Buffer Descriptor Lists */ 2511 for (i = 0; i < chip->bdbars_count; i++) 2512 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, 2513 chip->ichd[i].bdbar_addr); 2514 return 0; 2515 } 2516 2517 static int snd_intel8x0_free(struct intel8x0 *chip) 2518 { 2519 unsigned int i; 2520 2521 if (chip->irq < 0) 2522 goto __hw_end; 2523 /* disable interrupts */ 2524 for (i = 0; i < chip->bdbars_count; i++) 2525 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2526 /* reset channels */ 2527 for (i = 0; i < chip->bdbars_count; i++) 2528 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2529 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2530 /* stop the spdif interrupt */ 2531 unsigned int val; 2532 pci_read_config_dword(chip->pci, 0x4c, &val); 2533 val &= ~0x1000000; 2534 pci_write_config_dword(chip->pci, 0x4c, val); 2535 } 2536 /* --- */ 2537 2538 __hw_end: 2539 if (chip->irq >= 0) 2540 free_irq(chip->irq, chip); 2541 if (chip->bdbars.area) 2542 snd_dma_free_pages(&chip->bdbars); 2543 if (chip->addr) 2544 pci_iounmap(chip->pci, chip->addr); 2545 if (chip->bmaddr) 2546 pci_iounmap(chip->pci, chip->bmaddr); 2547 pci_release_regions(chip->pci); 2548 pci_disable_device(chip->pci); 2549 kfree(chip); 2550 return 0; 2551 } 2552 2553 #ifdef CONFIG_PM_SLEEP 2554 /* 2555 * power management 2556 */ 2557 static int intel8x0_suspend(struct device *dev) 2558 { 2559 struct snd_card *card = dev_get_drvdata(dev); 2560 struct intel8x0 *chip = card->private_data; 2561 int i; 2562 2563 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2564 for (i = 0; i < chip->ncodecs; i++) 2565 snd_ac97_suspend(chip->ac97[i]); 2566 if (chip->device_type == DEVICE_INTEL_ICH4) 2567 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2568 2569 if (chip->irq >= 0) { 2570 free_irq(chip->irq, chip); 2571 chip->irq = -1; 2572 card->sync_irq = -1; 2573 } 2574 return 0; 2575 } 2576 2577 static int intel8x0_resume(struct device *dev) 2578 { 2579 struct pci_dev *pci = to_pci_dev(dev); 2580 struct snd_card *card = dev_get_drvdata(dev); 2581 struct intel8x0 *chip = card->private_data; 2582 int i; 2583 2584 snd_intel8x0_chip_init(chip, 0); 2585 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2586 IRQF_SHARED, KBUILD_MODNAME, chip)) { 2587 dev_err(dev, "unable to grab IRQ %d, disabling device\n", 2588 pci->irq); 2589 snd_card_disconnect(card); 2590 return -EIO; 2591 } 2592 chip->irq = pci->irq; 2593 card->sync_irq = chip->irq; 2594 2595 /* re-initialize mixer stuff */ 2596 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2597 /* enable separate SDINs for ICH4 */ 2598 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2599 /* use slot 10/11 for SPDIF */ 2600 iputdword(chip, ICHREG(GLOB_CNT), 2601 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2602 ICH_PCM_SPDIF_1011); 2603 } 2604 2605 for (i = 0; i < chip->ncodecs; i++) 2606 snd_ac97_resume(chip->ac97[i]); 2607 2608 /* resume status */ 2609 for (i = 0; i < chip->bdbars_count; i++) { 2610 struct ichdev *ichdev = &chip->ichd[i]; 2611 unsigned long port = ichdev->reg_offset; 2612 if (! ichdev->substream || ! ichdev->suspended) 2613 continue; 2614 if (ichdev->ichd == ICHD_PCMOUT) 2615 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2616 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2617 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2618 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2619 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2620 } 2621 2622 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2623 return 0; 2624 } 2625 2626 static SIMPLE_DEV_PM_OPS(intel8x0_pm, intel8x0_suspend, intel8x0_resume); 2627 #define INTEL8X0_PM_OPS &intel8x0_pm 2628 #else 2629 #define INTEL8X0_PM_OPS NULL 2630 #endif /* CONFIG_PM_SLEEP */ 2631 2632 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2633 2634 static void intel8x0_measure_ac97_clock(struct intel8x0 *chip) 2635 { 2636 struct snd_pcm_substream *subs; 2637 struct ichdev *ichdev; 2638 unsigned long port; 2639 unsigned long pos, pos1, t; 2640 int civ, timeout = 1000, attempt = 1; 2641 ktime_t start_time, stop_time; 2642 2643 if (chip->ac97_bus->clock != 48000) 2644 return; /* specified in module option */ 2645 2646 __again: 2647 subs = chip->pcm[0]->streams[0].substream; 2648 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2649 dev_warn(chip->card->dev, 2650 "no playback buffer allocated - aborting measure ac97 clock\n"); 2651 return; 2652 } 2653 ichdev = &chip->ichd[ICHD_PCMOUT]; 2654 ichdev->physbuf = subs->dma_buffer.addr; 2655 ichdev->size = ichdev->fragsize = INTEL8X0_TESTBUF_SIZE; 2656 ichdev->substream = NULL; /* don't process interrupts */ 2657 2658 /* set rate */ 2659 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2660 dev_err(chip->card->dev, "cannot set ac97 rate: clock = %d\n", 2661 chip->ac97_bus->clock); 2662 return; 2663 } 2664 snd_intel8x0_setup_periods(chip, ichdev); 2665 port = ichdev->reg_offset; 2666 spin_lock_irq(&chip->reg_lock); 2667 chip->in_measurement = 1; 2668 /* trigger */ 2669 if (chip->device_type != DEVICE_ALI) 2670 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2671 else { 2672 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2673 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2674 } 2675 start_time = ktime_get(); 2676 spin_unlock_irq(&chip->reg_lock); 2677 msleep(50); 2678 spin_lock_irq(&chip->reg_lock); 2679 /* check the position */ 2680 do { 2681 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 2682 pos1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 2683 if (pos1 == 0) { 2684 udelay(10); 2685 continue; 2686 } 2687 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 2688 pos1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 2689 break; 2690 } while (timeout--); 2691 if (pos1 == 0) { /* oops, this value is not reliable */ 2692 pos = 0; 2693 } else { 2694 pos = ichdev->fragsize1; 2695 pos -= pos1 << ichdev->pos_shift; 2696 pos += ichdev->position; 2697 } 2698 chip->in_measurement = 0; 2699 stop_time = ktime_get(); 2700 /* stop */ 2701 if (chip->device_type == DEVICE_ALI) { 2702 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); 2703 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2704 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2705 ; 2706 } else { 2707 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2708 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2709 ; 2710 } 2711 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2712 spin_unlock_irq(&chip->reg_lock); 2713 2714 if (pos == 0) { 2715 dev_err(chip->card->dev, 2716 "measure - unreliable DMA position..\n"); 2717 __retry: 2718 if (attempt < 3) { 2719 msleep(300); 2720 attempt++; 2721 goto __again; 2722 } 2723 goto __end; 2724 } 2725 2726 pos /= 4; 2727 t = ktime_us_delta(stop_time, start_time); 2728 dev_info(chip->card->dev, 2729 "%s: measured %lu usecs (%lu samples)\n", __func__, t, pos); 2730 if (t == 0) { 2731 dev_err(chip->card->dev, "?? calculation error..\n"); 2732 goto __retry; 2733 } 2734 pos *= 1000; 2735 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2736 if (pos < 40000 || pos >= 60000) { 2737 /* abnormal value. hw problem? */ 2738 dev_info(chip->card->dev, "measured clock %ld rejected\n", pos); 2739 goto __retry; 2740 } else if (pos > 40500 && pos < 41500) 2741 /* first exception - 41000Hz reference clock */ 2742 chip->ac97_bus->clock = 41000; 2743 else if (pos > 43600 && pos < 44600) 2744 /* second exception - 44100HZ reference clock */ 2745 chip->ac97_bus->clock = 44100; 2746 else if (pos < 47500 || pos > 48500) 2747 /* not 48000Hz, tuning the clock.. */ 2748 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2749 __end: 2750 dev_info(chip->card->dev, "clocking to %d\n", chip->ac97_bus->clock); 2751 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2752 } 2753 2754 static const struct snd_pci_quirk intel8x0_clock_list[] = { 2755 SND_PCI_QUIRK(0x0e11, 0x008a, "AD1885", 41000), 2756 SND_PCI_QUIRK(0x1014, 0x0581, "AD1981B", 48000), 2757 SND_PCI_QUIRK(0x1028, 0x00be, "AD1885", 44100), 2758 SND_PCI_QUIRK(0x1028, 0x0177, "AD1980", 48000), 2759 SND_PCI_QUIRK(0x1028, 0x01ad, "AD1981B", 48000), 2760 SND_PCI_QUIRK(0x1043, 0x80f3, "AD1985", 48000), 2761 { } /* terminator */ 2762 }; 2763 2764 static int intel8x0_in_clock_list(struct intel8x0 *chip) 2765 { 2766 struct pci_dev *pci = chip->pci; 2767 const struct snd_pci_quirk *wl; 2768 2769 wl = snd_pci_quirk_lookup(pci, intel8x0_clock_list); 2770 if (!wl) 2771 return 0; 2772 dev_info(chip->card->dev, "allow list rate for %04x:%04x is %i\n", 2773 pci->subsystem_vendor, pci->subsystem_device, wl->value); 2774 chip->ac97_bus->clock = wl->value; 2775 return 1; 2776 } 2777 2778 static void snd_intel8x0_proc_read(struct snd_info_entry * entry, 2779 struct snd_info_buffer *buffer) 2780 { 2781 struct intel8x0 *chip = entry->private_data; 2782 unsigned int tmp; 2783 2784 snd_iprintf(buffer, "Intel8x0\n\n"); 2785 if (chip->device_type == DEVICE_ALI) 2786 return; 2787 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2788 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2789 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2790 if (chip->device_type == DEVICE_INTEL_ICH4) 2791 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2792 snd_iprintf(buffer, "AC'97 codecs ready :"); 2793 if (tmp & chip->codec_isr_bits) { 2794 int i; 2795 static const char *codecs[3] = { 2796 "primary", "secondary", "tertiary" 2797 }; 2798 for (i = 0; i < chip->max_codecs; i++) 2799 if (tmp & chip->codec_bit[i]) 2800 snd_iprintf(buffer, " %s", codecs[i]); 2801 } else 2802 snd_iprintf(buffer, " none"); 2803 snd_iprintf(buffer, "\n"); 2804 if (chip->device_type == DEVICE_INTEL_ICH4 || 2805 chip->device_type == DEVICE_SIS) 2806 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2807 chip->ac97_sdin[0], 2808 chip->ac97_sdin[1], 2809 chip->ac97_sdin[2]); 2810 } 2811 2812 static void snd_intel8x0_proc_init(struct intel8x0 *chip) 2813 { 2814 snd_card_ro_proc_new(chip->card, "intel8x0", chip, 2815 snd_intel8x0_proc_read); 2816 } 2817 2818 static int snd_intel8x0_dev_free(struct snd_device *device) 2819 { 2820 struct intel8x0 *chip = device->device_data; 2821 return snd_intel8x0_free(chip); 2822 } 2823 2824 struct ich_reg_info { 2825 unsigned int int_sta_mask; 2826 unsigned int offset; 2827 }; 2828 2829 static const unsigned int ich_codec_bits[3] = { 2830 ICH_PCR, ICH_SCR, ICH_TCR 2831 }; 2832 static const unsigned int sis_codec_bits[3] = { 2833 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2834 }; 2835 2836 static int snd_intel8x0_inside_vm(struct pci_dev *pci) 2837 { 2838 int result = inside_vm; 2839 char *msg = NULL; 2840 2841 /* check module parameter first (override detection) */ 2842 if (result >= 0) { 2843 msg = result ? "enable (forced) VM" : "disable (forced) VM"; 2844 goto fini; 2845 } 2846 2847 /* check for known (emulated) devices */ 2848 result = 0; 2849 if (pci->subsystem_vendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET && 2850 pci->subsystem_device == PCI_SUBDEVICE_ID_QEMU) { 2851 /* KVM emulated sound, PCI SSID: 1af4:1100 */ 2852 msg = "enable KVM"; 2853 result = 1; 2854 } else if (pci->subsystem_vendor == 0x1ab8) { 2855 /* Parallels VM emulated sound, PCI SSID: 1ab8:xxxx */ 2856 msg = "enable Parallels VM"; 2857 result = 1; 2858 } 2859 2860 fini: 2861 if (msg != NULL) 2862 dev_info(&pci->dev, "%s optimization\n", msg); 2863 2864 return result; 2865 } 2866 2867 static int snd_intel8x0_create(struct snd_card *card, 2868 struct pci_dev *pci, 2869 unsigned long device_type, 2870 struct intel8x0 **r_intel8x0) 2871 { 2872 struct intel8x0 *chip; 2873 int err; 2874 unsigned int i; 2875 unsigned int int_sta_masks; 2876 struct ichdev *ichdev; 2877 static const struct snd_device_ops ops = { 2878 .dev_free = snd_intel8x0_dev_free, 2879 }; 2880 2881 static const unsigned int bdbars[] = { 2882 3, /* DEVICE_INTEL */ 2883 6, /* DEVICE_INTEL_ICH4 */ 2884 3, /* DEVICE_SIS */ 2885 6, /* DEVICE_ALI */ 2886 4, /* DEVICE_NFORCE */ 2887 }; 2888 static const struct ich_reg_info intel_regs[6] = { 2889 { ICH_PIINT, 0 }, 2890 { ICH_POINT, 0x10 }, 2891 { ICH_MCINT, 0x20 }, 2892 { ICH_M2INT, 0x40 }, 2893 { ICH_P2INT, 0x50 }, 2894 { ICH_SPINT, 0x60 }, 2895 }; 2896 static const struct ich_reg_info nforce_regs[4] = { 2897 { ICH_PIINT, 0 }, 2898 { ICH_POINT, 0x10 }, 2899 { ICH_MCINT, 0x20 }, 2900 { ICH_NVSPINT, 0x70 }, 2901 }; 2902 static const struct ich_reg_info ali_regs[6] = { 2903 { ALI_INT_PCMIN, 0x40 }, 2904 { ALI_INT_PCMOUT, 0x50 }, 2905 { ALI_INT_MICIN, 0x60 }, 2906 { ALI_INT_CODECSPDIFOUT, 0x70 }, 2907 { ALI_INT_SPDIFIN, 0xa0 }, 2908 { ALI_INT_SPDIFOUT, 0xb0 }, 2909 }; 2910 const struct ich_reg_info *tbl; 2911 2912 *r_intel8x0 = NULL; 2913 2914 if ((err = pci_enable_device(pci)) < 0) 2915 return err; 2916 2917 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2918 if (chip == NULL) { 2919 pci_disable_device(pci); 2920 return -ENOMEM; 2921 } 2922 spin_lock_init(&chip->reg_lock); 2923 chip->device_type = device_type; 2924 chip->card = card; 2925 chip->pci = pci; 2926 chip->irq = -1; 2927 2928 /* module parameters */ 2929 chip->buggy_irq = buggy_irq; 2930 chip->buggy_semaphore = buggy_semaphore; 2931 if (xbox) 2932 chip->xbox = 1; 2933 2934 chip->inside_vm = snd_intel8x0_inside_vm(pci); 2935 2936 /* 2937 * Intel 82443MX running a 100MHz processor system bus has a hardware 2938 * bug, which aborts PCI busmaster for audio transfer. A workaround 2939 * is to set the pages as non-cached. For details, see the errata in 2940 * http://download.intel.com/design/chipsets/specupdt/24505108.pdf 2941 */ 2942 if (pci->vendor == PCI_VENDOR_ID_INTEL && 2943 pci->device == PCI_DEVICE_ID_INTEL_440MX) 2944 chip->fix_nocache = 1; /* enable workaround */ 2945 2946 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 2947 kfree(chip); 2948 pci_disable_device(pci); 2949 return err; 2950 } 2951 2952 if (device_type == DEVICE_ALI) { 2953 /* ALI5455 has no ac97 region */ 2954 chip->bmaddr = pci_iomap(pci, 0, 0); 2955 goto port_inited; 2956 } 2957 2958 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 2959 chip->addr = pci_iomap(pci, 2, 0); 2960 else 2961 chip->addr = pci_iomap(pci, 0, 0); 2962 if (!chip->addr) { 2963 dev_err(card->dev, "AC'97 space ioremap problem\n"); 2964 snd_intel8x0_free(chip); 2965 return -EIO; 2966 } 2967 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 2968 chip->bmaddr = pci_iomap(pci, 3, 0); 2969 else 2970 chip->bmaddr = pci_iomap(pci, 1, 0); 2971 2972 port_inited: 2973 if (!chip->bmaddr) { 2974 dev_err(card->dev, "Controller space ioremap problem\n"); 2975 snd_intel8x0_free(chip); 2976 return -EIO; 2977 } 2978 chip->bdbars_count = bdbars[device_type]; 2979 2980 /* initialize offsets */ 2981 switch (device_type) { 2982 case DEVICE_NFORCE: 2983 tbl = nforce_regs; 2984 break; 2985 case DEVICE_ALI: 2986 tbl = ali_regs; 2987 break; 2988 default: 2989 tbl = intel_regs; 2990 break; 2991 } 2992 for (i = 0; i < chip->bdbars_count; i++) { 2993 ichdev = &chip->ichd[i]; 2994 ichdev->ichd = i; 2995 ichdev->reg_offset = tbl[i].offset; 2996 ichdev->int_sta_mask = tbl[i].int_sta_mask; 2997 if (device_type == DEVICE_SIS) { 2998 /* SiS 7012 swaps the registers */ 2999 ichdev->roff_sr = ICH_REG_OFF_PICB; 3000 ichdev->roff_picb = ICH_REG_OFF_SR; 3001 } else { 3002 ichdev->roff_sr = ICH_REG_OFF_SR; 3003 ichdev->roff_picb = ICH_REG_OFF_PICB; 3004 } 3005 if (device_type == DEVICE_ALI) 3006 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 3007 /* SIS7012 handles the pcm data in bytes, others are in samples */ 3008 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 3009 } 3010 3011 /* allocate buffer descriptor lists */ 3012 /* the start of each lists must be aligned to 8 bytes */ 3013 if (snd_dma_alloc_pages(intel8x0_dma_type(chip), &pci->dev, 3014 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 3015 &chip->bdbars) < 0) { 3016 snd_intel8x0_free(chip); 3017 dev_err(card->dev, "cannot allocate buffer descriptors\n"); 3018 return -ENOMEM; 3019 } 3020 /* tables must be aligned to 8 bytes here, but the kernel pages 3021 are much bigger, so we don't care (on i386) */ 3022 int_sta_masks = 0; 3023 for (i = 0; i < chip->bdbars_count; i++) { 3024 ichdev = &chip->ichd[i]; 3025 ichdev->bdbar = ((__le32 *)chip->bdbars.area) + 3026 (i * ICH_MAX_FRAGS * 2); 3027 ichdev->bdbar_addr = chip->bdbars.addr + 3028 (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 3029 int_sta_masks |= ichdev->int_sta_mask; 3030 } 3031 chip->int_sta_reg = device_type == DEVICE_ALI ? 3032 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 3033 chip->int_sta_mask = int_sta_masks; 3034 3035 pci_set_master(pci); 3036 3037 switch(chip->device_type) { 3038 case DEVICE_INTEL_ICH4: 3039 /* ICH4 can have three codecs */ 3040 chip->max_codecs = 3; 3041 chip->codec_bit = ich_codec_bits; 3042 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 3043 break; 3044 case DEVICE_SIS: 3045 /* recent SIS7012 can have three codecs */ 3046 chip->max_codecs = 3; 3047 chip->codec_bit = sis_codec_bits; 3048 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 3049 break; 3050 default: 3051 /* others up to two codecs */ 3052 chip->max_codecs = 2; 3053 chip->codec_bit = ich_codec_bits; 3054 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 3055 break; 3056 } 3057 for (i = 0; i < chip->max_codecs; i++) 3058 chip->codec_isr_bits |= chip->codec_bit[i]; 3059 3060 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 3061 snd_intel8x0_free(chip); 3062 return err; 3063 } 3064 3065 /* request irq after initializaing int_sta_mask, etc */ 3066 if (request_irq(pci->irq, snd_intel8x0_interrupt, 3067 IRQF_SHARED, KBUILD_MODNAME, chip)) { 3068 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq); 3069 snd_intel8x0_free(chip); 3070 return -EBUSY; 3071 } 3072 chip->irq = pci->irq; 3073 card->sync_irq = chip->irq; 3074 3075 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 3076 snd_intel8x0_free(chip); 3077 return err; 3078 } 3079 3080 *r_intel8x0 = chip; 3081 return 0; 3082 } 3083 3084 static struct shortname_table { 3085 unsigned int id; 3086 const char *s; 3087 } shortnames[] = { 3088 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 3089 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 3090 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 3091 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 3092 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 3093 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 3094 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 3095 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 3096 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 3097 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 3098 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 3099 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 3100 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 3101 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 3102 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 3103 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 3104 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 3105 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 3106 { 0x003a, "NVidia MCP04" }, 3107 { 0x746d, "AMD AMD8111" }, 3108 { 0x7445, "AMD AMD768" }, 3109 { 0x5455, "ALi M5455" }, 3110 { 0, NULL }, 3111 }; 3112 3113 static const struct snd_pci_quirk spdif_aclink_defaults[] = { 3114 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), 3115 { } /* end */ 3116 }; 3117 3118 /* look up allow/deny list for SPDIF over ac-link */ 3119 static int check_default_spdif_aclink(struct pci_dev *pci) 3120 { 3121 const struct snd_pci_quirk *w; 3122 3123 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); 3124 if (w) { 3125 if (w->value) 3126 dev_dbg(&pci->dev, 3127 "Using SPDIF over AC-Link for %s\n", 3128 snd_pci_quirk_name(w)); 3129 else 3130 dev_dbg(&pci->dev, 3131 "Using integrated SPDIF DMA for %s\n", 3132 snd_pci_quirk_name(w)); 3133 return w->value; 3134 } 3135 return 0; 3136 } 3137 3138 static int snd_intel8x0_probe(struct pci_dev *pci, 3139 const struct pci_device_id *pci_id) 3140 { 3141 struct snd_card *card; 3142 struct intel8x0 *chip; 3143 int err; 3144 struct shortname_table *name; 3145 3146 err = snd_card_new(&pci->dev, index, id, THIS_MODULE, 0, &card); 3147 if (err < 0) 3148 return err; 3149 3150 if (spdif_aclink < 0) 3151 spdif_aclink = check_default_spdif_aclink(pci); 3152 3153 strcpy(card->driver, "ICH"); 3154 if (!spdif_aclink) { 3155 switch (pci_id->driver_data) { 3156 case DEVICE_NFORCE: 3157 strcpy(card->driver, "NFORCE"); 3158 break; 3159 case DEVICE_INTEL_ICH4: 3160 strcpy(card->driver, "ICH4"); 3161 } 3162 } 3163 3164 strcpy(card->shortname, "Intel ICH"); 3165 for (name = shortnames; name->id; name++) { 3166 if (pci->device == name->id) { 3167 strcpy(card->shortname, name->s); 3168 break; 3169 } 3170 } 3171 3172 if (buggy_irq < 0) { 3173 /* some Nforce[2] and ICH boards have problems with IRQ handling. 3174 * Needs to return IRQ_HANDLED for unknown irqs. 3175 */ 3176 if (pci_id->driver_data == DEVICE_NFORCE) 3177 buggy_irq = 1; 3178 else 3179 buggy_irq = 0; 3180 } 3181 3182 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 3183 &chip)) < 0) { 3184 snd_card_free(card); 3185 return err; 3186 } 3187 card->private_data = chip; 3188 3189 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { 3190 snd_card_free(card); 3191 return err; 3192 } 3193 if ((err = snd_intel8x0_pcm(chip)) < 0) { 3194 snd_card_free(card); 3195 return err; 3196 } 3197 3198 snd_intel8x0_proc_init(chip); 3199 3200 snprintf(card->longname, sizeof(card->longname), 3201 "%s with %s at irq %i", card->shortname, 3202 snd_ac97_get_short_name(chip->ac97[0]), chip->irq); 3203 3204 if (ac97_clock == 0 || ac97_clock == 1) { 3205 if (ac97_clock == 0) { 3206 if (intel8x0_in_clock_list(chip) == 0) 3207 intel8x0_measure_ac97_clock(chip); 3208 } else { 3209 intel8x0_measure_ac97_clock(chip); 3210 } 3211 } 3212 3213 if ((err = snd_card_register(card)) < 0) { 3214 snd_card_free(card); 3215 return err; 3216 } 3217 pci_set_drvdata(pci, card); 3218 return 0; 3219 } 3220 3221 static void snd_intel8x0_remove(struct pci_dev *pci) 3222 { 3223 snd_card_free(pci_get_drvdata(pci)); 3224 } 3225 3226 static struct pci_driver intel8x0_driver = { 3227 .name = KBUILD_MODNAME, 3228 .id_table = snd_intel8x0_ids, 3229 .probe = snd_intel8x0_probe, 3230 .remove = snd_intel8x0_remove, 3231 .driver = { 3232 .pm = INTEL8X0_PM_OPS, 3233 }, 3234 }; 3235 3236 module_pci_driver(intel8x0_driver); 3237