1 /* 2 * ALSA driver for Intel ICH (i8x0) chipsets 3 * 4 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 5 * 6 * 7 * This code also contains alpha support for SiS 735 chipsets provided 8 * by Mike Pieper <mptei@users.sourceforge.net>. We have no datasheet 9 * for SiS735, so the code is not fully functional. 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 26 * 27 */ 28 29 #include <asm/io.h> 30 #include <linux/delay.h> 31 #include <linux/interrupt.h> 32 #include <linux/init.h> 33 #include <linux/pci.h> 34 #include <linux/slab.h> 35 #include <linux/moduleparam.h> 36 #include <sound/core.h> 37 #include <sound/pcm.h> 38 #include <sound/ac97_codec.h> 39 #include <sound/info.h> 40 #include <sound/initval.h> 41 /* for 440MX workaround */ 42 #include <asm/pgtable.h> 43 #include <asm/cacheflush.h> 44 45 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>"); 46 MODULE_DESCRIPTION("Intel 82801AA,82901AB,i810,i820,i830,i840,i845,MX440; SiS 7012; Ali 5455"); 47 MODULE_LICENSE("GPL"); 48 MODULE_SUPPORTED_DEVICE("{{Intel,82801AA-ICH}," 49 "{Intel,82901AB-ICH0}," 50 "{Intel,82801BA-ICH2}," 51 "{Intel,82801CA-ICH3}," 52 "{Intel,82801DB-ICH4}," 53 "{Intel,ICH5}," 54 "{Intel,ICH6}," 55 "{Intel,ICH7}," 56 "{Intel,6300ESB}," 57 "{Intel,ESB2}," 58 "{Intel,MX440}," 59 "{SiS,SI7012}," 60 "{NVidia,nForce Audio}," 61 "{NVidia,nForce2 Audio}," 62 "{AMD,AMD768}," 63 "{AMD,AMD8111}," 64 "{ALI,M5455}}"); 65 66 static int index = SNDRV_DEFAULT_IDX1; /* Index 0-MAX */ 67 static char *id = SNDRV_DEFAULT_STR1; /* ID for this card */ 68 static int ac97_clock; 69 static char *ac97_quirk; 70 static int buggy_semaphore; 71 static int buggy_irq = -1; /* auto-check */ 72 static int xbox; 73 static int spdif_aclink = -1; 74 75 module_param(index, int, 0444); 76 MODULE_PARM_DESC(index, "Index value for Intel i8x0 soundcard."); 77 module_param(id, charp, 0444); 78 MODULE_PARM_DESC(id, "ID string for Intel i8x0 soundcard."); 79 module_param(ac97_clock, int, 0444); 80 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (0 = auto-detect)."); 81 module_param(ac97_quirk, charp, 0444); 82 MODULE_PARM_DESC(ac97_quirk, "AC'97 workaround for strange hardware."); 83 module_param(buggy_semaphore, bool, 0444); 84 MODULE_PARM_DESC(buggy_semaphore, "Enable workaround for hardwares with problematic codec semaphores."); 85 module_param(buggy_irq, bool, 0444); 86 MODULE_PARM_DESC(buggy_irq, "Enable workaround for buggy interrupts on some motherboards."); 87 module_param(xbox, bool, 0444); 88 MODULE_PARM_DESC(xbox, "Set to 1 for Xbox, if you have problems with the AC'97 codec detection."); 89 module_param(spdif_aclink, int, 0444); 90 MODULE_PARM_DESC(spdif_aclink, "S/PDIF over AC-link."); 91 92 /* just for backward compatibility */ 93 static int enable; 94 module_param(enable, bool, 0444); 95 static int joystick; 96 module_param(joystick, int, 0444); 97 98 /* 99 * Direct registers 100 */ 101 enum { DEVICE_INTEL, DEVICE_INTEL_ICH4, DEVICE_SIS, DEVICE_ALI, DEVICE_NFORCE }; 102 103 #define ICHREG(x) ICH_REG_##x 104 105 #define DEFINE_REGSET(name,base) \ 106 enum { \ 107 ICH_REG_##name##_BDBAR = base + 0x0, /* dword - buffer descriptor list base address */ \ 108 ICH_REG_##name##_CIV = base + 0x04, /* byte - current index value */ \ 109 ICH_REG_##name##_LVI = base + 0x05, /* byte - last valid index */ \ 110 ICH_REG_##name##_SR = base + 0x06, /* byte - status register */ \ 111 ICH_REG_##name##_PICB = base + 0x08, /* word - position in current buffer */ \ 112 ICH_REG_##name##_PIV = base + 0x0a, /* byte - prefetched index value */ \ 113 ICH_REG_##name##_CR = base + 0x0b, /* byte - control register */ \ 114 }; 115 116 /* busmaster blocks */ 117 DEFINE_REGSET(OFF, 0); /* offset */ 118 DEFINE_REGSET(PI, 0x00); /* PCM in */ 119 DEFINE_REGSET(PO, 0x10); /* PCM out */ 120 DEFINE_REGSET(MC, 0x20); /* Mic in */ 121 122 /* ICH4 busmaster blocks */ 123 DEFINE_REGSET(MC2, 0x40); /* Mic in 2 */ 124 DEFINE_REGSET(PI2, 0x50); /* PCM in 2 */ 125 DEFINE_REGSET(SP, 0x60); /* SPDIF out */ 126 127 /* values for each busmaster block */ 128 129 /* LVI */ 130 #define ICH_REG_LVI_MASK 0x1f 131 132 /* SR */ 133 #define ICH_FIFOE 0x10 /* FIFO error */ 134 #define ICH_BCIS 0x08 /* buffer completion interrupt status */ 135 #define ICH_LVBCI 0x04 /* last valid buffer completion interrupt */ 136 #define ICH_CELV 0x02 /* current equals last valid */ 137 #define ICH_DCH 0x01 /* DMA controller halted */ 138 139 /* PIV */ 140 #define ICH_REG_PIV_MASK 0x1f /* mask */ 141 142 /* CR */ 143 #define ICH_IOCE 0x10 /* interrupt on completion enable */ 144 #define ICH_FEIE 0x08 /* fifo error interrupt enable */ 145 #define ICH_LVBIE 0x04 /* last valid buffer interrupt enable */ 146 #define ICH_RESETREGS 0x02 /* reset busmaster registers */ 147 #define ICH_STARTBM 0x01 /* start busmaster operation */ 148 149 150 /* global block */ 151 #define ICH_REG_GLOB_CNT 0x2c /* dword - global control */ 152 #define ICH_PCM_SPDIF_MASK 0xc0000000 /* s/pdif pcm slot mask (ICH4) */ 153 #define ICH_PCM_SPDIF_NONE 0x00000000 /* reserved - undefined */ 154 #define ICH_PCM_SPDIF_78 0x40000000 /* s/pdif pcm on slots 7&8 */ 155 #define ICH_PCM_SPDIF_69 0x80000000 /* s/pdif pcm on slots 6&9 */ 156 #define ICH_PCM_SPDIF_1011 0xc0000000 /* s/pdif pcm on slots 10&11 */ 157 #define ICH_PCM_20BIT 0x00400000 /* 20-bit samples (ICH4) */ 158 #define ICH_PCM_246_MASK 0x00300000 /* chan mask (not all chips) */ 159 #define ICH_PCM_8 0x00300000 /* 8 channels (not all chips) */ 160 #define ICH_PCM_6 0x00200000 /* 6 channels (not all chips) */ 161 #define ICH_PCM_4 0x00100000 /* 4 channels (not all chips) */ 162 #define ICH_PCM_2 0x00000000 /* 2 channels (stereo) */ 163 #define ICH_SIS_PCM_246_MASK 0x000000c0 /* 6 channels (SIS7012) */ 164 #define ICH_SIS_PCM_6 0x00000080 /* 6 channels (SIS7012) */ 165 #define ICH_SIS_PCM_4 0x00000040 /* 4 channels (SIS7012) */ 166 #define ICH_SIS_PCM_2 0x00000000 /* 2 channels (SIS7012) */ 167 #define ICH_TRIE 0x00000040 /* tertiary resume interrupt enable */ 168 #define ICH_SRIE 0x00000020 /* secondary resume interrupt enable */ 169 #define ICH_PRIE 0x00000010 /* primary resume interrupt enable */ 170 #define ICH_ACLINK 0x00000008 /* AClink shut off */ 171 #define ICH_AC97WARM 0x00000004 /* AC'97 warm reset */ 172 #define ICH_AC97COLD 0x00000002 /* AC'97 cold reset */ 173 #define ICH_GIE 0x00000001 /* GPI interrupt enable */ 174 #define ICH_REG_GLOB_STA 0x30 /* dword - global status */ 175 #define ICH_TRI 0x20000000 /* ICH4: tertiary (AC_SDIN2) resume interrupt */ 176 #define ICH_TCR 0x10000000 /* ICH4: tertiary (AC_SDIN2) codec ready */ 177 #define ICH_BCS 0x08000000 /* ICH4: bit clock stopped */ 178 #define ICH_SPINT 0x04000000 /* ICH4: S/PDIF interrupt */ 179 #define ICH_P2INT 0x02000000 /* ICH4: PCM2-In interrupt */ 180 #define ICH_M2INT 0x01000000 /* ICH4: Mic2-In interrupt */ 181 #define ICH_SAMPLE_CAP 0x00c00000 /* ICH4: sample capability bits (RO) */ 182 #define ICH_SAMPLE_16_20 0x00400000 /* ICH4: 16- and 20-bit samples */ 183 #define ICH_MULTICHAN_CAP 0x00300000 /* ICH4: multi-channel capability bits (RO) */ 184 #define ICH_SIS_TRI 0x00080000 /* SIS: tertiary resume irq */ 185 #define ICH_SIS_TCR 0x00040000 /* SIS: tertiary codec ready */ 186 #define ICH_MD3 0x00020000 /* modem power down semaphore */ 187 #define ICH_AD3 0x00010000 /* audio power down semaphore */ 188 #define ICH_RCS 0x00008000 /* read completion status */ 189 #define ICH_BIT3 0x00004000 /* bit 3 slot 12 */ 190 #define ICH_BIT2 0x00002000 /* bit 2 slot 12 */ 191 #define ICH_BIT1 0x00001000 /* bit 1 slot 12 */ 192 #define ICH_SRI 0x00000800 /* secondary (AC_SDIN1) resume interrupt */ 193 #define ICH_PRI 0x00000400 /* primary (AC_SDIN0) resume interrupt */ 194 #define ICH_SCR 0x00000200 /* secondary (AC_SDIN1) codec ready */ 195 #define ICH_PCR 0x00000100 /* primary (AC_SDIN0) codec ready */ 196 #define ICH_MCINT 0x00000080 /* MIC capture interrupt */ 197 #define ICH_POINT 0x00000040 /* playback interrupt */ 198 #define ICH_PIINT 0x00000020 /* capture interrupt */ 199 #define ICH_NVSPINT 0x00000010 /* nforce spdif interrupt */ 200 #define ICH_MOINT 0x00000004 /* modem playback interrupt */ 201 #define ICH_MIINT 0x00000002 /* modem capture interrupt */ 202 #define ICH_GSCI 0x00000001 /* GPI status change interrupt */ 203 #define ICH_REG_ACC_SEMA 0x34 /* byte - codec write semaphore */ 204 #define ICH_CAS 0x01 /* codec access semaphore */ 205 #define ICH_REG_SDM 0x80 206 #define ICH_DI2L_MASK 0x000000c0 /* PCM In 2, Mic In 2 data in line */ 207 #define ICH_DI2L_SHIFT 6 208 #define ICH_DI1L_MASK 0x00000030 /* PCM In 1, Mic In 1 data in line */ 209 #define ICH_DI1L_SHIFT 4 210 #define ICH_SE 0x00000008 /* steer enable */ 211 #define ICH_LDI_MASK 0x00000003 /* last codec read data input */ 212 213 #define ICH_MAX_FRAGS 32 /* max hw frags */ 214 215 216 /* 217 * registers for Ali5455 218 */ 219 220 /* ALi 5455 busmaster blocks */ 221 DEFINE_REGSET(AL_PI, 0x40); /* ALi PCM in */ 222 DEFINE_REGSET(AL_PO, 0x50); /* Ali PCM out */ 223 DEFINE_REGSET(AL_MC, 0x60); /* Ali Mic in */ 224 DEFINE_REGSET(AL_CDC_SPO, 0x70); /* Ali Codec SPDIF out */ 225 DEFINE_REGSET(AL_CENTER, 0x80); /* Ali center out */ 226 DEFINE_REGSET(AL_LFE, 0x90); /* Ali center out */ 227 DEFINE_REGSET(AL_CLR_SPI, 0xa0); /* Ali Controller SPDIF in */ 228 DEFINE_REGSET(AL_CLR_SPO, 0xb0); /* Ali Controller SPDIF out */ 229 DEFINE_REGSET(AL_I2S, 0xc0); /* Ali I2S in */ 230 DEFINE_REGSET(AL_PI2, 0xd0); /* Ali PCM2 in */ 231 DEFINE_REGSET(AL_MC2, 0xe0); /* Ali Mic2 in */ 232 233 enum { 234 ICH_REG_ALI_SCR = 0x00, /* System Control Register */ 235 ICH_REG_ALI_SSR = 0x04, /* System Status Register */ 236 ICH_REG_ALI_DMACR = 0x08, /* DMA Control Register */ 237 ICH_REG_ALI_FIFOCR1 = 0x0c, /* FIFO Control Register 1 */ 238 ICH_REG_ALI_INTERFACECR = 0x10, /* Interface Control Register */ 239 ICH_REG_ALI_INTERRUPTCR = 0x14, /* Interrupt control Register */ 240 ICH_REG_ALI_INTERRUPTSR = 0x18, /* Interrupt Status Register */ 241 ICH_REG_ALI_FIFOCR2 = 0x1c, /* FIFO Control Register 2 */ 242 ICH_REG_ALI_CPR = 0x20, /* Command Port Register */ 243 ICH_REG_ALI_CPR_ADDR = 0x22, /* ac97 addr write */ 244 ICH_REG_ALI_SPR = 0x24, /* Status Port Register */ 245 ICH_REG_ALI_SPR_ADDR = 0x26, /* ac97 addr read */ 246 ICH_REG_ALI_FIFOCR3 = 0x2c, /* FIFO Control Register 3 */ 247 ICH_REG_ALI_TTSR = 0x30, /* Transmit Tag Slot Register */ 248 ICH_REG_ALI_RTSR = 0x34, /* Receive Tag Slot Register */ 249 ICH_REG_ALI_CSPSR = 0x38, /* Command/Status Port Status Register */ 250 ICH_REG_ALI_CAS = 0x3c, /* Codec Write Semaphore Register */ 251 ICH_REG_ALI_HWVOL = 0xf0, /* hardware volume control/status */ 252 ICH_REG_ALI_I2SCR = 0xf4, /* I2S control/status */ 253 ICH_REG_ALI_SPDIFCSR = 0xf8, /* spdif channel status register */ 254 ICH_REG_ALI_SPDIFICS = 0xfc, /* spdif interface control/status */ 255 }; 256 257 #define ALI_CAS_SEM_BUSY 0x80000000 258 #define ALI_CPR_ADDR_SECONDARY 0x100 259 #define ALI_CPR_ADDR_READ 0x80 260 #define ALI_CSPSR_CODEC_READY 0x08 261 #define ALI_CSPSR_READ_OK 0x02 262 #define ALI_CSPSR_WRITE_OK 0x01 263 264 /* interrupts for the whole chip by interrupt status register finish */ 265 266 #define ALI_INT_MICIN2 (1<<26) 267 #define ALI_INT_PCMIN2 (1<<25) 268 #define ALI_INT_I2SIN (1<<24) 269 #define ALI_INT_SPDIFOUT (1<<23) /* controller spdif out INTERRUPT */ 270 #define ALI_INT_SPDIFIN (1<<22) 271 #define ALI_INT_LFEOUT (1<<21) 272 #define ALI_INT_CENTEROUT (1<<20) 273 #define ALI_INT_CODECSPDIFOUT (1<<19) 274 #define ALI_INT_MICIN (1<<18) 275 #define ALI_INT_PCMOUT (1<<17) 276 #define ALI_INT_PCMIN (1<<16) 277 #define ALI_INT_CPRAIS (1<<7) /* command port available */ 278 #define ALI_INT_SPRAIS (1<<5) /* status port available */ 279 #define ALI_INT_GPIO (1<<1) 280 #define ALI_INT_MASK (ALI_INT_SPDIFOUT|ALI_INT_CODECSPDIFOUT|\ 281 ALI_INT_MICIN|ALI_INT_PCMOUT|ALI_INT_PCMIN) 282 283 #define ICH_ALI_SC_RESET (1<<31) /* master reset */ 284 #define ICH_ALI_SC_AC97_DBL (1<<30) 285 #define ICH_ALI_SC_CODEC_SPDF (3<<20) /* 1=7/8, 2=6/9, 3=10/11 */ 286 #define ICH_ALI_SC_IN_BITS (3<<18) 287 #define ICH_ALI_SC_OUT_BITS (3<<16) 288 #define ICH_ALI_SC_6CH_CFG (3<<14) 289 #define ICH_ALI_SC_PCM_4 (1<<8) 290 #define ICH_ALI_SC_PCM_6 (2<<8) 291 #define ICH_ALI_SC_PCM_246_MASK (3<<8) 292 293 #define ICH_ALI_SS_SEC_ID (3<<5) 294 #define ICH_ALI_SS_PRI_ID (3<<3) 295 296 #define ICH_ALI_IF_AC97SP (1<<21) 297 #define ICH_ALI_IF_MC (1<<20) 298 #define ICH_ALI_IF_PI (1<<19) 299 #define ICH_ALI_IF_MC2 (1<<18) 300 #define ICH_ALI_IF_PI2 (1<<17) 301 #define ICH_ALI_IF_LINE_SRC (1<<15) /* 0/1 = slot 3/6 */ 302 #define ICH_ALI_IF_MIC_SRC (1<<14) /* 0/1 = slot 3/6 */ 303 #define ICH_ALI_IF_SPDF_SRC (3<<12) /* 00 = PCM, 01 = AC97-in, 10 = spdif-in, 11 = i2s */ 304 #define ICH_ALI_IF_AC97_OUT (3<<8) /* 00 = PCM, 10 = spdif-in, 11 = i2s */ 305 #define ICH_ALI_IF_PO_SPDF (1<<3) 306 #define ICH_ALI_IF_PO (1<<1) 307 308 /* 309 * 310 */ 311 312 enum { 313 ICHD_PCMIN, 314 ICHD_PCMOUT, 315 ICHD_MIC, 316 ICHD_MIC2, 317 ICHD_PCM2IN, 318 ICHD_SPBAR, 319 ICHD_LAST = ICHD_SPBAR 320 }; 321 enum { 322 NVD_PCMIN, 323 NVD_PCMOUT, 324 NVD_MIC, 325 NVD_SPBAR, 326 NVD_LAST = NVD_SPBAR 327 }; 328 enum { 329 ALID_PCMIN, 330 ALID_PCMOUT, 331 ALID_MIC, 332 ALID_AC97SPDIFOUT, 333 ALID_SPDIFIN, 334 ALID_SPDIFOUT, 335 ALID_LAST = ALID_SPDIFOUT 336 }; 337 338 #define get_ichdev(substream) (substream->runtime->private_data) 339 340 struct ichdev { 341 unsigned int ichd; /* ich device number */ 342 unsigned long reg_offset; /* offset to bmaddr */ 343 u32 *bdbar; /* CPU address (32bit) */ 344 unsigned int bdbar_addr; /* PCI bus address (32bit) */ 345 struct snd_pcm_substream *substream; 346 unsigned int physbuf; /* physical address (32bit) */ 347 unsigned int size; 348 unsigned int fragsize; 349 unsigned int fragsize1; 350 unsigned int position; 351 unsigned int pos_shift; 352 int frags; 353 int lvi; 354 int lvi_frag; 355 int civ; 356 int ack; 357 int ack_reload; 358 unsigned int ack_bit; 359 unsigned int roff_sr; 360 unsigned int roff_picb; 361 unsigned int int_sta_mask; /* interrupt status mask */ 362 unsigned int ali_slot; /* ALI DMA slot */ 363 struct ac97_pcm *pcm; 364 int pcm_open_flag; 365 unsigned int page_attr_changed: 1; 366 unsigned int suspended: 1; 367 }; 368 369 struct intel8x0 { 370 unsigned int device_type; 371 372 int irq; 373 374 void __iomem *addr; 375 void __iomem *bmaddr; 376 377 struct pci_dev *pci; 378 struct snd_card *card; 379 380 int pcm_devs; 381 struct snd_pcm *pcm[6]; 382 struct ichdev ichd[6]; 383 384 unsigned multi4: 1, 385 multi6: 1, 386 multi8 :1, 387 dra: 1, 388 smp20bit: 1; 389 unsigned in_ac97_init: 1, 390 in_sdin_init: 1; 391 unsigned in_measurement: 1; /* during ac97 clock measurement */ 392 unsigned fix_nocache: 1; /* workaround for 440MX */ 393 unsigned buggy_irq: 1; /* workaround for buggy mobos */ 394 unsigned xbox: 1; /* workaround for Xbox AC'97 detection */ 395 unsigned buggy_semaphore: 1; /* workaround for buggy codec semaphore */ 396 397 int spdif_idx; /* SPDIF BAR index; *_SPBAR or -1 if use PCMOUT */ 398 unsigned int sdm_saved; /* SDM reg value */ 399 400 struct snd_ac97_bus *ac97_bus; 401 struct snd_ac97 *ac97[3]; 402 unsigned int ac97_sdin[3]; 403 unsigned int max_codecs, ncodecs; 404 unsigned int *codec_bit; 405 unsigned int codec_isr_bits; 406 unsigned int codec_ready_bits; 407 408 spinlock_t reg_lock; 409 410 u32 bdbars_count; 411 struct snd_dma_buffer bdbars; 412 u32 int_sta_reg; /* interrupt status register */ 413 u32 int_sta_mask; /* interrupt status mask */ 414 }; 415 416 static struct pci_device_id snd_intel8x0_ids[] = { 417 { 0x8086, 0x2415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801AA */ 418 { 0x8086, 0x2425, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82901AB */ 419 { 0x8086, 0x2445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 82801BA */ 420 { 0x8086, 0x2485, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* ICH3 */ 421 { 0x8086, 0x24c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH4 */ 422 { 0x8086, 0x24d5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH5 */ 423 { 0x8086, 0x25a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB */ 424 { 0x8086, 0x266e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH6 */ 425 { 0x8086, 0x27de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ICH7 */ 426 { 0x8086, 0x2698, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL_ICH4 }, /* ESB2 */ 427 { 0x8086, 0x7195, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* 440MX */ 428 { 0x1039, 0x7012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_SIS }, /* SI7012 */ 429 { 0x10de, 0x01b1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE */ 430 { 0x10de, 0x003a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP04 */ 431 { 0x10de, 0x006a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE2 */ 432 { 0x10de, 0x0059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK804 */ 433 { 0x10de, 0x008a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8 */ 434 { 0x10de, 0x00da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* NFORCE3 */ 435 { 0x10de, 0x00ea, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* CK8S */ 436 { 0x10de, 0x026b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_NFORCE }, /* MCP51 */ 437 { 0x1022, 0x746d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD8111 */ 438 { 0x1022, 0x7445, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_INTEL }, /* AMD768 */ 439 { 0x10b9, 0x5455, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DEVICE_ALI }, /* Ali5455 */ 440 { 0, } 441 }; 442 443 MODULE_DEVICE_TABLE(pci, snd_intel8x0_ids); 444 445 /* 446 * Lowlevel I/O - busmaster 447 */ 448 449 static inline u8 igetbyte(struct intel8x0 *chip, u32 offset) 450 { 451 return ioread8(chip->bmaddr + offset); 452 } 453 454 static inline u16 igetword(struct intel8x0 *chip, u32 offset) 455 { 456 return ioread16(chip->bmaddr + offset); 457 } 458 459 static inline u32 igetdword(struct intel8x0 *chip, u32 offset) 460 { 461 return ioread32(chip->bmaddr + offset); 462 } 463 464 static inline void iputbyte(struct intel8x0 *chip, u32 offset, u8 val) 465 { 466 iowrite8(val, chip->bmaddr + offset); 467 } 468 469 static inline void iputword(struct intel8x0 *chip, u32 offset, u16 val) 470 { 471 iowrite16(val, chip->bmaddr + offset); 472 } 473 474 static inline void iputdword(struct intel8x0 *chip, u32 offset, u32 val) 475 { 476 iowrite32(val, chip->bmaddr + offset); 477 } 478 479 /* 480 * Lowlevel I/O - AC'97 registers 481 */ 482 483 static inline u16 iagetword(struct intel8x0 *chip, u32 offset) 484 { 485 return ioread16(chip->addr + offset); 486 } 487 488 static inline void iaputword(struct intel8x0 *chip, u32 offset, u16 val) 489 { 490 iowrite16(val, chip->addr + offset); 491 } 492 493 /* 494 * Basic I/O 495 */ 496 497 /* 498 * access to AC97 codec via normal i/o (for ICH and SIS7012) 499 */ 500 501 static int snd_intel8x0_codec_semaphore(struct intel8x0 *chip, unsigned int codec) 502 { 503 int time; 504 505 if (codec > 2) 506 return -EIO; 507 if (chip->in_sdin_init) { 508 /* we don't know the ready bit assignment at the moment */ 509 /* so we check any */ 510 codec = chip->codec_isr_bits; 511 } else { 512 codec = chip->codec_bit[chip->ac97_sdin[codec]]; 513 } 514 515 /* codec ready ? */ 516 if ((igetdword(chip, ICHREG(GLOB_STA)) & codec) == 0) 517 return -EIO; 518 519 if (chip->buggy_semaphore) 520 return 0; /* just ignore ... */ 521 522 /* Anyone holding a semaphore for 1 msec should be shot... */ 523 time = 100; 524 do { 525 if (!(igetbyte(chip, ICHREG(ACC_SEMA)) & ICH_CAS)) 526 return 0; 527 udelay(10); 528 } while (time--); 529 530 /* access to some forbidden (non existant) ac97 registers will not 531 * reset the semaphore. So even if you don't get the semaphore, still 532 * continue the access. We don't need the semaphore anyway. */ 533 snd_printk(KERN_ERR "codec_semaphore: semaphore is not ready [0x%x][0x%x]\n", 534 igetbyte(chip, ICHREG(ACC_SEMA)), igetdword(chip, ICHREG(GLOB_STA))); 535 iagetword(chip, 0); /* clear semaphore flag */ 536 /* I don't care about the semaphore */ 537 return -EBUSY; 538 } 539 540 static void snd_intel8x0_codec_write(struct snd_ac97 *ac97, 541 unsigned short reg, 542 unsigned short val) 543 { 544 struct intel8x0 *chip = ac97->private_data; 545 546 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 547 if (! chip->in_ac97_init) 548 snd_printk(KERN_ERR "codec_write %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 549 } 550 iaputword(chip, reg + ac97->num * 0x80, val); 551 } 552 553 static unsigned short snd_intel8x0_codec_read(struct snd_ac97 *ac97, 554 unsigned short reg) 555 { 556 struct intel8x0 *chip = ac97->private_data; 557 unsigned short res; 558 unsigned int tmp; 559 560 if (snd_intel8x0_codec_semaphore(chip, ac97->num) < 0) { 561 if (! chip->in_ac97_init) 562 snd_printk(KERN_ERR "codec_read %d: semaphore is not ready for register 0x%x\n", ac97->num, reg); 563 res = 0xffff; 564 } else { 565 res = iagetword(chip, reg + ac97->num * 0x80); 566 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 567 /* reset RCS and preserve other R/WC bits */ 568 iputdword(chip, ICHREG(GLOB_STA), tmp & 569 ~(chip->codec_ready_bits | ICH_GSCI)); 570 if (! chip->in_ac97_init) 571 snd_printk(KERN_ERR "codec_read %d: read timeout for register 0x%x\n", ac97->num, reg); 572 res = 0xffff; 573 } 574 } 575 return res; 576 } 577 578 static void __devinit snd_intel8x0_codec_read_test(struct intel8x0 *chip, 579 unsigned int codec) 580 { 581 unsigned int tmp; 582 583 if (snd_intel8x0_codec_semaphore(chip, codec) >= 0) { 584 iagetword(chip, codec * 0x80); 585 if ((tmp = igetdword(chip, ICHREG(GLOB_STA))) & ICH_RCS) { 586 /* reset RCS and preserve other R/WC bits */ 587 iputdword(chip, ICHREG(GLOB_STA), tmp & 588 ~(chip->codec_ready_bits | ICH_GSCI)); 589 } 590 } 591 } 592 593 /* 594 * access to AC97 for Ali5455 595 */ 596 static int snd_intel8x0_ali_codec_ready(struct intel8x0 *chip, int mask) 597 { 598 int count = 0; 599 for (count = 0; count < 0x7f; count++) { 600 int val = igetbyte(chip, ICHREG(ALI_CSPSR)); 601 if (val & mask) 602 return 0; 603 } 604 if (! chip->in_ac97_init) 605 snd_printd(KERN_WARNING "intel8x0: AC97 codec ready timeout.\n"); 606 return -EBUSY; 607 } 608 609 static int snd_intel8x0_ali_codec_semaphore(struct intel8x0 *chip) 610 { 611 int time = 100; 612 if (chip->buggy_semaphore) 613 return 0; /* just ignore ... */ 614 while (time-- && (igetdword(chip, ICHREG(ALI_CAS)) & ALI_CAS_SEM_BUSY)) 615 udelay(1); 616 if (! time && ! chip->in_ac97_init) 617 snd_printk(KERN_WARNING "ali_codec_semaphore timeout\n"); 618 return snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_CODEC_READY); 619 } 620 621 static unsigned short snd_intel8x0_ali_codec_read(struct snd_ac97 *ac97, unsigned short reg) 622 { 623 struct intel8x0 *chip = ac97->private_data; 624 unsigned short data = 0xffff; 625 626 if (snd_intel8x0_ali_codec_semaphore(chip)) 627 goto __err; 628 reg |= ALI_CPR_ADDR_READ; 629 if (ac97->num) 630 reg |= ALI_CPR_ADDR_SECONDARY; 631 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 632 if (snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_READ_OK)) 633 goto __err; 634 data = igetword(chip, ICHREG(ALI_SPR)); 635 __err: 636 return data; 637 } 638 639 static void snd_intel8x0_ali_codec_write(struct snd_ac97 *ac97, unsigned short reg, 640 unsigned short val) 641 { 642 struct intel8x0 *chip = ac97->private_data; 643 644 if (snd_intel8x0_ali_codec_semaphore(chip)) 645 return; 646 iputword(chip, ICHREG(ALI_CPR), val); 647 if (ac97->num) 648 reg |= ALI_CPR_ADDR_SECONDARY; 649 iputword(chip, ICHREG(ALI_CPR_ADDR), reg); 650 snd_intel8x0_ali_codec_ready(chip, ALI_CSPSR_WRITE_OK); 651 } 652 653 654 /* 655 * DMA I/O 656 */ 657 static void snd_intel8x0_setup_periods(struct intel8x0 *chip, struct ichdev *ichdev) 658 { 659 int idx; 660 u32 *bdbar = ichdev->bdbar; 661 unsigned long port = ichdev->reg_offset; 662 663 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 664 if (ichdev->size == ichdev->fragsize) { 665 ichdev->ack_reload = ichdev->ack = 2; 666 ichdev->fragsize1 = ichdev->fragsize >> 1; 667 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 4) { 668 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf); 669 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 670 ichdev->fragsize1 >> ichdev->pos_shift); 671 bdbar[idx + 2] = cpu_to_le32(ichdev->physbuf + (ichdev->size >> 1)); 672 bdbar[idx + 3] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 673 ichdev->fragsize1 >> ichdev->pos_shift); 674 } 675 ichdev->frags = 2; 676 } else { 677 ichdev->ack_reload = ichdev->ack = 1; 678 ichdev->fragsize1 = ichdev->fragsize; 679 for (idx = 0; idx < (ICH_REG_LVI_MASK + 1) * 2; idx += 2) { 680 bdbar[idx + 0] = cpu_to_le32(ichdev->physbuf + 681 (((idx >> 1) * ichdev->fragsize) % 682 ichdev->size)); 683 bdbar[idx + 1] = cpu_to_le32(0x80000000 | /* interrupt on completion */ 684 ichdev->fragsize >> ichdev->pos_shift); 685 #if 0 686 printk("bdbar[%i] = 0x%x [0x%x]\n", 687 idx + 0, bdbar[idx + 0], bdbar[idx + 1]); 688 #endif 689 } 690 ichdev->frags = ichdev->size / ichdev->fragsize; 691 } 692 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi = ICH_REG_LVI_MASK); 693 ichdev->civ = 0; 694 iputbyte(chip, port + ICH_REG_OFF_CIV, 0); 695 ichdev->lvi_frag = ICH_REG_LVI_MASK % ichdev->frags; 696 ichdev->position = 0; 697 #if 0 698 printk("lvi_frag = %i, frags = %i, period_size = 0x%x, period_size1 = 0x%x\n", 699 ichdev->lvi_frag, ichdev->frags, ichdev->fragsize, ichdev->fragsize1); 700 #endif 701 /* clear interrupts */ 702 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 703 } 704 705 #ifdef __i386__ 706 /* 707 * Intel 82443MX running a 100MHz processor system bus has a hardware bug, 708 * which aborts PCI busmaster for audio transfer. A workaround is to set 709 * the pages as non-cached. For details, see the errata in 710 * http://www.intel.com/design/chipsets/specupdt/245051.htm 711 */ 712 static void fill_nocache(void *buf, int size, int nocache) 713 { 714 size = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; 715 if (nocache) 716 set_pages_uc(virt_to_page(buf), size); 717 else 718 set_pages_wb(virt_to_page(buf), size); 719 } 720 #else 721 #define fill_nocache(buf, size, nocache) do { ; } while (0) 722 #endif 723 724 /* 725 * Interrupt handler 726 */ 727 728 static inline void snd_intel8x0_update(struct intel8x0 *chip, struct ichdev *ichdev) 729 { 730 unsigned long port = ichdev->reg_offset; 731 unsigned long flags; 732 int status, civ, i, step; 733 int ack = 0; 734 735 spin_lock_irqsave(&chip->reg_lock, flags); 736 status = igetbyte(chip, port + ichdev->roff_sr); 737 civ = igetbyte(chip, port + ICH_REG_OFF_CIV); 738 if (!(status & ICH_BCIS)) { 739 step = 0; 740 } else if (civ == ichdev->civ) { 741 // snd_printd("civ same %d\n", civ); 742 step = 1; 743 ichdev->civ++; 744 ichdev->civ &= ICH_REG_LVI_MASK; 745 } else { 746 step = civ - ichdev->civ; 747 if (step < 0) 748 step += ICH_REG_LVI_MASK + 1; 749 // if (step != 1) 750 // snd_printd("step = %d, %d -> %d\n", step, ichdev->civ, civ); 751 ichdev->civ = civ; 752 } 753 754 ichdev->position += step * ichdev->fragsize1; 755 if (! chip->in_measurement) 756 ichdev->position %= ichdev->size; 757 ichdev->lvi += step; 758 ichdev->lvi &= ICH_REG_LVI_MASK; 759 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 760 for (i = 0; i < step; i++) { 761 ichdev->lvi_frag++; 762 ichdev->lvi_frag %= ichdev->frags; 763 ichdev->bdbar[ichdev->lvi * 2] = cpu_to_le32(ichdev->physbuf + ichdev->lvi_frag * ichdev->fragsize1); 764 #if 0 765 printk("new: bdbar[%i] = 0x%x [0x%x], prefetch = %i, all = 0x%x, 0x%x\n", 766 ichdev->lvi * 2, ichdev->bdbar[ichdev->lvi * 2], 767 ichdev->bdbar[ichdev->lvi * 2 + 1], inb(ICH_REG_OFF_PIV + port), 768 inl(port + 4), inb(port + ICH_REG_OFF_CR)); 769 #endif 770 if (--ichdev->ack == 0) { 771 ichdev->ack = ichdev->ack_reload; 772 ack = 1; 773 } 774 } 775 spin_unlock_irqrestore(&chip->reg_lock, flags); 776 if (ack && ichdev->substream) { 777 snd_pcm_period_elapsed(ichdev->substream); 778 } 779 iputbyte(chip, port + ichdev->roff_sr, 780 status & (ICH_FIFOE | ICH_BCIS | ICH_LVBCI)); 781 } 782 783 static irqreturn_t snd_intel8x0_interrupt(int irq, void *dev_id) 784 { 785 struct intel8x0 *chip = dev_id; 786 struct ichdev *ichdev; 787 unsigned int status; 788 unsigned int i; 789 790 status = igetdword(chip, chip->int_sta_reg); 791 if (status == 0xffffffff) /* we are not yet resumed */ 792 return IRQ_NONE; 793 794 if ((status & chip->int_sta_mask) == 0) { 795 if (status) { 796 /* ack */ 797 iputdword(chip, chip->int_sta_reg, status); 798 if (! chip->buggy_irq) 799 status = 0; 800 } 801 return IRQ_RETVAL(status); 802 } 803 804 for (i = 0; i < chip->bdbars_count; i++) { 805 ichdev = &chip->ichd[i]; 806 if (status & ichdev->int_sta_mask) 807 snd_intel8x0_update(chip, ichdev); 808 } 809 810 /* ack them */ 811 iputdword(chip, chip->int_sta_reg, status & chip->int_sta_mask); 812 813 return IRQ_HANDLED; 814 } 815 816 /* 817 * PCM part 818 */ 819 820 static int snd_intel8x0_pcm_trigger(struct snd_pcm_substream *substream, int cmd) 821 { 822 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 823 struct ichdev *ichdev = get_ichdev(substream); 824 unsigned char val = 0; 825 unsigned long port = ichdev->reg_offset; 826 827 switch (cmd) { 828 case SNDRV_PCM_TRIGGER_RESUME: 829 ichdev->suspended = 0; 830 /* fallthru */ 831 case SNDRV_PCM_TRIGGER_START: 832 val = ICH_IOCE | ICH_STARTBM; 833 break; 834 case SNDRV_PCM_TRIGGER_SUSPEND: 835 ichdev->suspended = 1; 836 /* fallthru */ 837 case SNDRV_PCM_TRIGGER_STOP: 838 val = 0; 839 break; 840 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 841 val = ICH_IOCE; 842 break; 843 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 844 val = ICH_IOCE | ICH_STARTBM; 845 break; 846 default: 847 return -EINVAL; 848 } 849 iputbyte(chip, port + ICH_REG_OFF_CR, val); 850 if (cmd == SNDRV_PCM_TRIGGER_STOP) { 851 /* wait until DMA stopped */ 852 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) ; 853 /* reset whole DMA things */ 854 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 855 } 856 return 0; 857 } 858 859 static int snd_intel8x0_ali_trigger(struct snd_pcm_substream *substream, int cmd) 860 { 861 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 862 struct ichdev *ichdev = get_ichdev(substream); 863 unsigned long port = ichdev->reg_offset; 864 static int fiforeg[] = { 865 ICHREG(ALI_FIFOCR1), ICHREG(ALI_FIFOCR2), ICHREG(ALI_FIFOCR3) 866 }; 867 unsigned int val, fifo; 868 869 val = igetdword(chip, ICHREG(ALI_DMACR)); 870 switch (cmd) { 871 case SNDRV_PCM_TRIGGER_RESUME: 872 ichdev->suspended = 0; 873 /* fallthru */ 874 case SNDRV_PCM_TRIGGER_START: 875 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 876 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 877 /* clear FIFO for synchronization of channels */ 878 fifo = igetdword(chip, fiforeg[ichdev->ali_slot / 4]); 879 fifo &= ~(0xff << (ichdev->ali_slot % 4)); 880 fifo |= 0x83 << (ichdev->ali_slot % 4); 881 iputdword(chip, fiforeg[ichdev->ali_slot / 4], fifo); 882 } 883 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 884 val &= ~(1 << (ichdev->ali_slot + 16)); /* clear PAUSE flag */ 885 /* start DMA */ 886 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << ichdev->ali_slot)); 887 break; 888 case SNDRV_PCM_TRIGGER_SUSPEND: 889 ichdev->suspended = 1; 890 /* fallthru */ 891 case SNDRV_PCM_TRIGGER_STOP: 892 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 893 /* pause */ 894 iputdword(chip, ICHREG(ALI_DMACR), val | (1 << (ichdev->ali_slot + 16))); 895 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 896 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 897 ; 898 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) 899 break; 900 /* reset whole DMA things */ 901 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 902 /* clear interrupts */ 903 iputbyte(chip, port + ICH_REG_OFF_SR, 904 igetbyte(chip, port + ICH_REG_OFF_SR) | 0x1e); 905 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 906 igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ichdev->int_sta_mask); 907 break; 908 default: 909 return -EINVAL; 910 } 911 return 0; 912 } 913 914 static int snd_intel8x0_hw_params(struct snd_pcm_substream *substream, 915 struct snd_pcm_hw_params *hw_params) 916 { 917 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 918 struct ichdev *ichdev = get_ichdev(substream); 919 struct snd_pcm_runtime *runtime = substream->runtime; 920 int dbl = params_rate(hw_params) > 48000; 921 int err; 922 923 if (chip->fix_nocache && ichdev->page_attr_changed) { 924 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); /* clear */ 925 ichdev->page_attr_changed = 0; 926 } 927 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); 928 if (err < 0) 929 return err; 930 if (chip->fix_nocache) { 931 if (runtime->dma_area && ! ichdev->page_attr_changed) { 932 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 933 ichdev->page_attr_changed = 1; 934 } 935 } 936 if (ichdev->pcm_open_flag) { 937 snd_ac97_pcm_close(ichdev->pcm); 938 ichdev->pcm_open_flag = 0; 939 } 940 err = snd_ac97_pcm_open(ichdev->pcm, params_rate(hw_params), 941 params_channels(hw_params), 942 ichdev->pcm->r[dbl].slots); 943 if (err >= 0) { 944 ichdev->pcm_open_flag = 1; 945 /* Force SPDIF setting */ 946 if (ichdev->ichd == ICHD_PCMOUT && chip->spdif_idx < 0) 947 snd_ac97_set_rate(ichdev->pcm->r[0].codec[0], AC97_SPDIF, 948 params_rate(hw_params)); 949 } 950 return err; 951 } 952 953 static int snd_intel8x0_hw_free(struct snd_pcm_substream *substream) 954 { 955 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 956 struct ichdev *ichdev = get_ichdev(substream); 957 958 if (ichdev->pcm_open_flag) { 959 snd_ac97_pcm_close(ichdev->pcm); 960 ichdev->pcm_open_flag = 0; 961 } 962 if (chip->fix_nocache && ichdev->page_attr_changed) { 963 fill_nocache(substream->runtime->dma_area, substream->runtime->dma_bytes, 0); 964 ichdev->page_attr_changed = 0; 965 } 966 return snd_pcm_lib_free_pages(substream); 967 } 968 969 static void snd_intel8x0_setup_pcm_out(struct intel8x0 *chip, 970 struct snd_pcm_runtime *runtime) 971 { 972 unsigned int cnt; 973 int dbl = runtime->rate > 48000; 974 975 spin_lock_irq(&chip->reg_lock); 976 switch (chip->device_type) { 977 case DEVICE_ALI: 978 cnt = igetdword(chip, ICHREG(ALI_SCR)); 979 cnt &= ~ICH_ALI_SC_PCM_246_MASK; 980 if (runtime->channels == 4 || dbl) 981 cnt |= ICH_ALI_SC_PCM_4; 982 else if (runtime->channels == 6) 983 cnt |= ICH_ALI_SC_PCM_6; 984 iputdword(chip, ICHREG(ALI_SCR), cnt); 985 break; 986 case DEVICE_SIS: 987 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 988 cnt &= ~ICH_SIS_PCM_246_MASK; 989 if (runtime->channels == 4 || dbl) 990 cnt |= ICH_SIS_PCM_4; 991 else if (runtime->channels == 6) 992 cnt |= ICH_SIS_PCM_6; 993 iputdword(chip, ICHREG(GLOB_CNT), cnt); 994 break; 995 default: 996 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 997 cnt &= ~(ICH_PCM_246_MASK | ICH_PCM_20BIT); 998 if (runtime->channels == 4 || dbl) 999 cnt |= ICH_PCM_4; 1000 else if (runtime->channels == 6) 1001 cnt |= ICH_PCM_6; 1002 else if (runtime->channels == 8) 1003 cnt |= ICH_PCM_8; 1004 if (chip->device_type == DEVICE_NFORCE) { 1005 /* reset to 2ch once to keep the 6 channel data in alignment, 1006 * to start from Front Left always 1007 */ 1008 if (cnt & ICH_PCM_246_MASK) { 1009 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_PCM_246_MASK); 1010 spin_unlock_irq(&chip->reg_lock); 1011 msleep(50); /* grrr... */ 1012 spin_lock_irq(&chip->reg_lock); 1013 } 1014 } else if (chip->device_type == DEVICE_INTEL_ICH4) { 1015 if (runtime->sample_bits > 16) 1016 cnt |= ICH_PCM_20BIT; 1017 } 1018 iputdword(chip, ICHREG(GLOB_CNT), cnt); 1019 break; 1020 } 1021 spin_unlock_irq(&chip->reg_lock); 1022 } 1023 1024 static int snd_intel8x0_pcm_prepare(struct snd_pcm_substream *substream) 1025 { 1026 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1027 struct snd_pcm_runtime *runtime = substream->runtime; 1028 struct ichdev *ichdev = get_ichdev(substream); 1029 1030 ichdev->physbuf = runtime->dma_addr; 1031 ichdev->size = snd_pcm_lib_buffer_bytes(substream); 1032 ichdev->fragsize = snd_pcm_lib_period_bytes(substream); 1033 if (ichdev->ichd == ICHD_PCMOUT) { 1034 snd_intel8x0_setup_pcm_out(chip, runtime); 1035 if (chip->device_type == DEVICE_INTEL_ICH4) 1036 ichdev->pos_shift = (runtime->sample_bits > 16) ? 2 : 1; 1037 } 1038 snd_intel8x0_setup_periods(chip, ichdev); 1039 return 0; 1040 } 1041 1042 static snd_pcm_uframes_t snd_intel8x0_pcm_pointer(struct snd_pcm_substream *substream) 1043 { 1044 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1045 struct ichdev *ichdev = get_ichdev(substream); 1046 size_t ptr1, ptr; 1047 int civ, timeout = 100; 1048 unsigned int position; 1049 1050 spin_lock(&chip->reg_lock); 1051 do { 1052 civ = igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV); 1053 ptr1 = igetword(chip, ichdev->reg_offset + ichdev->roff_picb); 1054 position = ichdev->position; 1055 if (ptr1 == 0) { 1056 udelay(10); 1057 continue; 1058 } 1059 if (civ == igetbyte(chip, ichdev->reg_offset + ICH_REG_OFF_CIV) && 1060 ptr1 == igetword(chip, ichdev->reg_offset + ichdev->roff_picb)) 1061 break; 1062 } while (timeout--); 1063 ptr1 <<= ichdev->pos_shift; 1064 ptr = ichdev->fragsize1 - ptr1; 1065 ptr += position; 1066 spin_unlock(&chip->reg_lock); 1067 if (ptr >= ichdev->size) 1068 return 0; 1069 return bytes_to_frames(substream->runtime, ptr); 1070 } 1071 1072 static struct snd_pcm_hardware snd_intel8x0_stream = 1073 { 1074 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 1075 SNDRV_PCM_INFO_BLOCK_TRANSFER | 1076 SNDRV_PCM_INFO_MMAP_VALID | 1077 SNDRV_PCM_INFO_PAUSE | 1078 SNDRV_PCM_INFO_RESUME), 1079 .formats = SNDRV_PCM_FMTBIT_S16_LE, 1080 .rates = SNDRV_PCM_RATE_48000, 1081 .rate_min = 48000, 1082 .rate_max = 48000, 1083 .channels_min = 2, 1084 .channels_max = 2, 1085 .buffer_bytes_max = 128 * 1024, 1086 .period_bytes_min = 32, 1087 .period_bytes_max = 128 * 1024, 1088 .periods_min = 1, 1089 .periods_max = 1024, 1090 .fifo_size = 0, 1091 }; 1092 1093 static unsigned int channels4[] = { 1094 2, 4, 1095 }; 1096 1097 static struct snd_pcm_hw_constraint_list hw_constraints_channels4 = { 1098 .count = ARRAY_SIZE(channels4), 1099 .list = channels4, 1100 .mask = 0, 1101 }; 1102 1103 static unsigned int channels6[] = { 1104 2, 4, 6, 1105 }; 1106 1107 static struct snd_pcm_hw_constraint_list hw_constraints_channels6 = { 1108 .count = ARRAY_SIZE(channels6), 1109 .list = channels6, 1110 .mask = 0, 1111 }; 1112 1113 static unsigned int channels8[] = { 1114 2, 4, 6, 8, 1115 }; 1116 1117 static struct snd_pcm_hw_constraint_list hw_constraints_channels8 = { 1118 .count = ARRAY_SIZE(channels8), 1119 .list = channels8, 1120 .mask = 0, 1121 }; 1122 1123 static int snd_intel8x0_pcm_open(struct snd_pcm_substream *substream, struct ichdev *ichdev) 1124 { 1125 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1126 struct snd_pcm_runtime *runtime = substream->runtime; 1127 int err; 1128 1129 ichdev->substream = substream; 1130 runtime->hw = snd_intel8x0_stream; 1131 runtime->hw.rates = ichdev->pcm->rates; 1132 snd_pcm_limit_hw_rates(runtime); 1133 if (chip->device_type == DEVICE_SIS) { 1134 runtime->hw.buffer_bytes_max = 64*1024; 1135 runtime->hw.period_bytes_max = 64*1024; 1136 } 1137 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0) 1138 return err; 1139 runtime->private_data = ichdev; 1140 return 0; 1141 } 1142 1143 static int snd_intel8x0_playback_open(struct snd_pcm_substream *substream) 1144 { 1145 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1146 struct snd_pcm_runtime *runtime = substream->runtime; 1147 int err; 1148 1149 err = snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMOUT]); 1150 if (err < 0) 1151 return err; 1152 1153 if (chip->multi8) { 1154 runtime->hw.channels_max = 8; 1155 snd_pcm_hw_constraint_list(runtime, 0, 1156 SNDRV_PCM_HW_PARAM_CHANNELS, 1157 &hw_constraints_channels8); 1158 } else if (chip->multi6) { 1159 runtime->hw.channels_max = 6; 1160 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1161 &hw_constraints_channels6); 1162 } else if (chip->multi4) { 1163 runtime->hw.channels_max = 4; 1164 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS, 1165 &hw_constraints_channels4); 1166 } 1167 if (chip->dra) { 1168 snd_ac97_pcm_double_rate_rules(runtime); 1169 } 1170 if (chip->smp20bit) { 1171 runtime->hw.formats |= SNDRV_PCM_FMTBIT_S32_LE; 1172 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 20); 1173 } 1174 return 0; 1175 } 1176 1177 static int snd_intel8x0_playback_close(struct snd_pcm_substream *substream) 1178 { 1179 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1180 1181 chip->ichd[ICHD_PCMOUT].substream = NULL; 1182 return 0; 1183 } 1184 1185 static int snd_intel8x0_capture_open(struct snd_pcm_substream *substream) 1186 { 1187 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1188 1189 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCMIN]); 1190 } 1191 1192 static int snd_intel8x0_capture_close(struct snd_pcm_substream *substream) 1193 { 1194 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1195 1196 chip->ichd[ICHD_PCMIN].substream = NULL; 1197 return 0; 1198 } 1199 1200 static int snd_intel8x0_mic_open(struct snd_pcm_substream *substream) 1201 { 1202 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1203 1204 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC]); 1205 } 1206 1207 static int snd_intel8x0_mic_close(struct snd_pcm_substream *substream) 1208 { 1209 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1210 1211 chip->ichd[ICHD_MIC].substream = NULL; 1212 return 0; 1213 } 1214 1215 static int snd_intel8x0_mic2_open(struct snd_pcm_substream *substream) 1216 { 1217 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1218 1219 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_MIC2]); 1220 } 1221 1222 static int snd_intel8x0_mic2_close(struct snd_pcm_substream *substream) 1223 { 1224 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1225 1226 chip->ichd[ICHD_MIC2].substream = NULL; 1227 return 0; 1228 } 1229 1230 static int snd_intel8x0_capture2_open(struct snd_pcm_substream *substream) 1231 { 1232 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1233 1234 return snd_intel8x0_pcm_open(substream, &chip->ichd[ICHD_PCM2IN]); 1235 } 1236 1237 static int snd_intel8x0_capture2_close(struct snd_pcm_substream *substream) 1238 { 1239 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1240 1241 chip->ichd[ICHD_PCM2IN].substream = NULL; 1242 return 0; 1243 } 1244 1245 static int snd_intel8x0_spdif_open(struct snd_pcm_substream *substream) 1246 { 1247 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1248 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1249 1250 return snd_intel8x0_pcm_open(substream, &chip->ichd[idx]); 1251 } 1252 1253 static int snd_intel8x0_spdif_close(struct snd_pcm_substream *substream) 1254 { 1255 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1256 int idx = chip->device_type == DEVICE_NFORCE ? NVD_SPBAR : ICHD_SPBAR; 1257 1258 chip->ichd[idx].substream = NULL; 1259 return 0; 1260 } 1261 1262 static int snd_intel8x0_ali_ac97spdifout_open(struct snd_pcm_substream *substream) 1263 { 1264 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1265 unsigned int val; 1266 1267 spin_lock_irq(&chip->reg_lock); 1268 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1269 val |= ICH_ALI_IF_AC97SP; 1270 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1271 /* also needs to set ALI_SC_CODEC_SPDF correctly */ 1272 spin_unlock_irq(&chip->reg_lock); 1273 1274 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_AC97SPDIFOUT]); 1275 } 1276 1277 static int snd_intel8x0_ali_ac97spdifout_close(struct snd_pcm_substream *substream) 1278 { 1279 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1280 unsigned int val; 1281 1282 chip->ichd[ALID_AC97SPDIFOUT].substream = NULL; 1283 spin_lock_irq(&chip->reg_lock); 1284 val = igetdword(chip, ICHREG(ALI_INTERFACECR)); 1285 val &= ~ICH_ALI_IF_AC97SP; 1286 iputdword(chip, ICHREG(ALI_INTERFACECR), val); 1287 spin_unlock_irq(&chip->reg_lock); 1288 1289 return 0; 1290 } 1291 1292 #if 0 // NYI 1293 static int snd_intel8x0_ali_spdifin_open(struct snd_pcm_substream *substream) 1294 { 1295 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1296 1297 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFIN]); 1298 } 1299 1300 static int snd_intel8x0_ali_spdifin_close(struct snd_pcm_substream *substream) 1301 { 1302 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1303 1304 chip->ichd[ALID_SPDIFIN].substream = NULL; 1305 return 0; 1306 } 1307 1308 static int snd_intel8x0_ali_spdifout_open(struct snd_pcm_substream *substream) 1309 { 1310 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1311 1312 return snd_intel8x0_pcm_open(substream, &chip->ichd[ALID_SPDIFOUT]); 1313 } 1314 1315 static int snd_intel8x0_ali_spdifout_close(struct snd_pcm_substream *substream) 1316 { 1317 struct intel8x0 *chip = snd_pcm_substream_chip(substream); 1318 1319 chip->ichd[ALID_SPDIFOUT].substream = NULL; 1320 return 0; 1321 } 1322 #endif 1323 1324 static struct snd_pcm_ops snd_intel8x0_playback_ops = { 1325 .open = snd_intel8x0_playback_open, 1326 .close = snd_intel8x0_playback_close, 1327 .ioctl = snd_pcm_lib_ioctl, 1328 .hw_params = snd_intel8x0_hw_params, 1329 .hw_free = snd_intel8x0_hw_free, 1330 .prepare = snd_intel8x0_pcm_prepare, 1331 .trigger = snd_intel8x0_pcm_trigger, 1332 .pointer = snd_intel8x0_pcm_pointer, 1333 }; 1334 1335 static struct snd_pcm_ops snd_intel8x0_capture_ops = { 1336 .open = snd_intel8x0_capture_open, 1337 .close = snd_intel8x0_capture_close, 1338 .ioctl = snd_pcm_lib_ioctl, 1339 .hw_params = snd_intel8x0_hw_params, 1340 .hw_free = snd_intel8x0_hw_free, 1341 .prepare = snd_intel8x0_pcm_prepare, 1342 .trigger = snd_intel8x0_pcm_trigger, 1343 .pointer = snd_intel8x0_pcm_pointer, 1344 }; 1345 1346 static struct snd_pcm_ops snd_intel8x0_capture_mic_ops = { 1347 .open = snd_intel8x0_mic_open, 1348 .close = snd_intel8x0_mic_close, 1349 .ioctl = snd_pcm_lib_ioctl, 1350 .hw_params = snd_intel8x0_hw_params, 1351 .hw_free = snd_intel8x0_hw_free, 1352 .prepare = snd_intel8x0_pcm_prepare, 1353 .trigger = snd_intel8x0_pcm_trigger, 1354 .pointer = snd_intel8x0_pcm_pointer, 1355 }; 1356 1357 static struct snd_pcm_ops snd_intel8x0_capture_mic2_ops = { 1358 .open = snd_intel8x0_mic2_open, 1359 .close = snd_intel8x0_mic2_close, 1360 .ioctl = snd_pcm_lib_ioctl, 1361 .hw_params = snd_intel8x0_hw_params, 1362 .hw_free = snd_intel8x0_hw_free, 1363 .prepare = snd_intel8x0_pcm_prepare, 1364 .trigger = snd_intel8x0_pcm_trigger, 1365 .pointer = snd_intel8x0_pcm_pointer, 1366 }; 1367 1368 static struct snd_pcm_ops snd_intel8x0_capture2_ops = { 1369 .open = snd_intel8x0_capture2_open, 1370 .close = snd_intel8x0_capture2_close, 1371 .ioctl = snd_pcm_lib_ioctl, 1372 .hw_params = snd_intel8x0_hw_params, 1373 .hw_free = snd_intel8x0_hw_free, 1374 .prepare = snd_intel8x0_pcm_prepare, 1375 .trigger = snd_intel8x0_pcm_trigger, 1376 .pointer = snd_intel8x0_pcm_pointer, 1377 }; 1378 1379 static struct snd_pcm_ops snd_intel8x0_spdif_ops = { 1380 .open = snd_intel8x0_spdif_open, 1381 .close = snd_intel8x0_spdif_close, 1382 .ioctl = snd_pcm_lib_ioctl, 1383 .hw_params = snd_intel8x0_hw_params, 1384 .hw_free = snd_intel8x0_hw_free, 1385 .prepare = snd_intel8x0_pcm_prepare, 1386 .trigger = snd_intel8x0_pcm_trigger, 1387 .pointer = snd_intel8x0_pcm_pointer, 1388 }; 1389 1390 static struct snd_pcm_ops snd_intel8x0_ali_playback_ops = { 1391 .open = snd_intel8x0_playback_open, 1392 .close = snd_intel8x0_playback_close, 1393 .ioctl = snd_pcm_lib_ioctl, 1394 .hw_params = snd_intel8x0_hw_params, 1395 .hw_free = snd_intel8x0_hw_free, 1396 .prepare = snd_intel8x0_pcm_prepare, 1397 .trigger = snd_intel8x0_ali_trigger, 1398 .pointer = snd_intel8x0_pcm_pointer, 1399 }; 1400 1401 static struct snd_pcm_ops snd_intel8x0_ali_capture_ops = { 1402 .open = snd_intel8x0_capture_open, 1403 .close = snd_intel8x0_capture_close, 1404 .ioctl = snd_pcm_lib_ioctl, 1405 .hw_params = snd_intel8x0_hw_params, 1406 .hw_free = snd_intel8x0_hw_free, 1407 .prepare = snd_intel8x0_pcm_prepare, 1408 .trigger = snd_intel8x0_ali_trigger, 1409 .pointer = snd_intel8x0_pcm_pointer, 1410 }; 1411 1412 static struct snd_pcm_ops snd_intel8x0_ali_capture_mic_ops = { 1413 .open = snd_intel8x0_mic_open, 1414 .close = snd_intel8x0_mic_close, 1415 .ioctl = snd_pcm_lib_ioctl, 1416 .hw_params = snd_intel8x0_hw_params, 1417 .hw_free = snd_intel8x0_hw_free, 1418 .prepare = snd_intel8x0_pcm_prepare, 1419 .trigger = snd_intel8x0_ali_trigger, 1420 .pointer = snd_intel8x0_pcm_pointer, 1421 }; 1422 1423 static struct snd_pcm_ops snd_intel8x0_ali_ac97spdifout_ops = { 1424 .open = snd_intel8x0_ali_ac97spdifout_open, 1425 .close = snd_intel8x0_ali_ac97spdifout_close, 1426 .ioctl = snd_pcm_lib_ioctl, 1427 .hw_params = snd_intel8x0_hw_params, 1428 .hw_free = snd_intel8x0_hw_free, 1429 .prepare = snd_intel8x0_pcm_prepare, 1430 .trigger = snd_intel8x0_ali_trigger, 1431 .pointer = snd_intel8x0_pcm_pointer, 1432 }; 1433 1434 #if 0 // NYI 1435 static struct snd_pcm_ops snd_intel8x0_ali_spdifin_ops = { 1436 .open = snd_intel8x0_ali_spdifin_open, 1437 .close = snd_intel8x0_ali_spdifin_close, 1438 .ioctl = snd_pcm_lib_ioctl, 1439 .hw_params = snd_intel8x0_hw_params, 1440 .hw_free = snd_intel8x0_hw_free, 1441 .prepare = snd_intel8x0_pcm_prepare, 1442 .trigger = snd_intel8x0_pcm_trigger, 1443 .pointer = snd_intel8x0_pcm_pointer, 1444 }; 1445 1446 static struct snd_pcm_ops snd_intel8x0_ali_spdifout_ops = { 1447 .open = snd_intel8x0_ali_spdifout_open, 1448 .close = snd_intel8x0_ali_spdifout_close, 1449 .ioctl = snd_pcm_lib_ioctl, 1450 .hw_params = snd_intel8x0_hw_params, 1451 .hw_free = snd_intel8x0_hw_free, 1452 .prepare = snd_intel8x0_pcm_prepare, 1453 .trigger = snd_intel8x0_pcm_trigger, 1454 .pointer = snd_intel8x0_pcm_pointer, 1455 }; 1456 #endif // NYI 1457 1458 struct ich_pcm_table { 1459 char *suffix; 1460 struct snd_pcm_ops *playback_ops; 1461 struct snd_pcm_ops *capture_ops; 1462 size_t prealloc_size; 1463 size_t prealloc_max_size; 1464 int ac97_idx; 1465 }; 1466 1467 static int __devinit snd_intel8x0_pcm1(struct intel8x0 *chip, int device, 1468 struct ich_pcm_table *rec) 1469 { 1470 struct snd_pcm *pcm; 1471 int err; 1472 char name[32]; 1473 1474 if (rec->suffix) 1475 sprintf(name, "Intel ICH - %s", rec->suffix); 1476 else 1477 strcpy(name, "Intel ICH"); 1478 err = snd_pcm_new(chip->card, name, device, 1479 rec->playback_ops ? 1 : 0, 1480 rec->capture_ops ? 1 : 0, &pcm); 1481 if (err < 0) 1482 return err; 1483 1484 if (rec->playback_ops) 1485 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, rec->playback_ops); 1486 if (rec->capture_ops) 1487 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, rec->capture_ops); 1488 1489 pcm->private_data = chip; 1490 pcm->info_flags = 0; 1491 if (rec->suffix) 1492 sprintf(pcm->name, "%s - %s", chip->card->shortname, rec->suffix); 1493 else 1494 strcpy(pcm->name, chip->card->shortname); 1495 chip->pcm[device] = pcm; 1496 1497 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV, 1498 snd_dma_pci_data(chip->pci), 1499 rec->prealloc_size, rec->prealloc_max_size); 1500 1501 return 0; 1502 } 1503 1504 static struct ich_pcm_table intel_pcms[] __devinitdata = { 1505 { 1506 .playback_ops = &snd_intel8x0_playback_ops, 1507 .capture_ops = &snd_intel8x0_capture_ops, 1508 .prealloc_size = 64 * 1024, 1509 .prealloc_max_size = 128 * 1024, 1510 }, 1511 { 1512 .suffix = "MIC ADC", 1513 .capture_ops = &snd_intel8x0_capture_mic_ops, 1514 .prealloc_size = 0, 1515 .prealloc_max_size = 128 * 1024, 1516 .ac97_idx = ICHD_MIC, 1517 }, 1518 { 1519 .suffix = "MIC2 ADC", 1520 .capture_ops = &snd_intel8x0_capture_mic2_ops, 1521 .prealloc_size = 0, 1522 .prealloc_max_size = 128 * 1024, 1523 .ac97_idx = ICHD_MIC2, 1524 }, 1525 { 1526 .suffix = "ADC2", 1527 .capture_ops = &snd_intel8x0_capture2_ops, 1528 .prealloc_size = 0, 1529 .prealloc_max_size = 128 * 1024, 1530 .ac97_idx = ICHD_PCM2IN, 1531 }, 1532 { 1533 .suffix = "IEC958", 1534 .playback_ops = &snd_intel8x0_spdif_ops, 1535 .prealloc_size = 64 * 1024, 1536 .prealloc_max_size = 128 * 1024, 1537 .ac97_idx = ICHD_SPBAR, 1538 }, 1539 }; 1540 1541 static struct ich_pcm_table nforce_pcms[] __devinitdata = { 1542 { 1543 .playback_ops = &snd_intel8x0_playback_ops, 1544 .capture_ops = &snd_intel8x0_capture_ops, 1545 .prealloc_size = 64 * 1024, 1546 .prealloc_max_size = 128 * 1024, 1547 }, 1548 { 1549 .suffix = "MIC ADC", 1550 .capture_ops = &snd_intel8x0_capture_mic_ops, 1551 .prealloc_size = 0, 1552 .prealloc_max_size = 128 * 1024, 1553 .ac97_idx = NVD_MIC, 1554 }, 1555 { 1556 .suffix = "IEC958", 1557 .playback_ops = &snd_intel8x0_spdif_ops, 1558 .prealloc_size = 64 * 1024, 1559 .prealloc_max_size = 128 * 1024, 1560 .ac97_idx = NVD_SPBAR, 1561 }, 1562 }; 1563 1564 static struct ich_pcm_table ali_pcms[] __devinitdata = { 1565 { 1566 .playback_ops = &snd_intel8x0_ali_playback_ops, 1567 .capture_ops = &snd_intel8x0_ali_capture_ops, 1568 .prealloc_size = 64 * 1024, 1569 .prealloc_max_size = 128 * 1024, 1570 }, 1571 { 1572 .suffix = "MIC ADC", 1573 .capture_ops = &snd_intel8x0_ali_capture_mic_ops, 1574 .prealloc_size = 0, 1575 .prealloc_max_size = 128 * 1024, 1576 .ac97_idx = ALID_MIC, 1577 }, 1578 { 1579 .suffix = "IEC958", 1580 .playback_ops = &snd_intel8x0_ali_ac97spdifout_ops, 1581 /* .capture_ops = &snd_intel8x0_ali_spdifin_ops, */ 1582 .prealloc_size = 64 * 1024, 1583 .prealloc_max_size = 128 * 1024, 1584 .ac97_idx = ALID_AC97SPDIFOUT, 1585 }, 1586 #if 0 // NYI 1587 { 1588 .suffix = "HW IEC958", 1589 .playback_ops = &snd_intel8x0_ali_spdifout_ops, 1590 .prealloc_size = 64 * 1024, 1591 .prealloc_max_size = 128 * 1024, 1592 }, 1593 #endif 1594 }; 1595 1596 static int __devinit snd_intel8x0_pcm(struct intel8x0 *chip) 1597 { 1598 int i, tblsize, device, err; 1599 struct ich_pcm_table *tbl, *rec; 1600 1601 switch (chip->device_type) { 1602 case DEVICE_INTEL_ICH4: 1603 tbl = intel_pcms; 1604 tblsize = ARRAY_SIZE(intel_pcms); 1605 if (spdif_aclink) 1606 tblsize--; 1607 break; 1608 case DEVICE_NFORCE: 1609 tbl = nforce_pcms; 1610 tblsize = ARRAY_SIZE(nforce_pcms); 1611 if (spdif_aclink) 1612 tblsize--; 1613 break; 1614 case DEVICE_ALI: 1615 tbl = ali_pcms; 1616 tblsize = ARRAY_SIZE(ali_pcms); 1617 break; 1618 default: 1619 tbl = intel_pcms; 1620 tblsize = 2; 1621 break; 1622 } 1623 1624 device = 0; 1625 for (i = 0; i < tblsize; i++) { 1626 rec = tbl + i; 1627 if (i > 0 && rec->ac97_idx) { 1628 /* activate PCM only when associated AC'97 codec */ 1629 if (! chip->ichd[rec->ac97_idx].pcm) 1630 continue; 1631 } 1632 err = snd_intel8x0_pcm1(chip, device, rec); 1633 if (err < 0) 1634 return err; 1635 device++; 1636 } 1637 1638 chip->pcm_devs = device; 1639 return 0; 1640 } 1641 1642 1643 /* 1644 * Mixer part 1645 */ 1646 1647 static void snd_intel8x0_mixer_free_ac97_bus(struct snd_ac97_bus *bus) 1648 { 1649 struct intel8x0 *chip = bus->private_data; 1650 chip->ac97_bus = NULL; 1651 } 1652 1653 static void snd_intel8x0_mixer_free_ac97(struct snd_ac97 *ac97) 1654 { 1655 struct intel8x0 *chip = ac97->private_data; 1656 chip->ac97[ac97->num] = NULL; 1657 } 1658 1659 static struct ac97_pcm ac97_pcm_defs[] __devinitdata = { 1660 /* front PCM */ 1661 { 1662 .exclusive = 1, 1663 .r = { { 1664 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1665 (1 << AC97_SLOT_PCM_RIGHT) | 1666 (1 << AC97_SLOT_PCM_CENTER) | 1667 (1 << AC97_SLOT_PCM_SLEFT) | 1668 (1 << AC97_SLOT_PCM_SRIGHT) | 1669 (1 << AC97_SLOT_LFE) 1670 }, 1671 { 1672 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1673 (1 << AC97_SLOT_PCM_RIGHT) | 1674 (1 << AC97_SLOT_PCM_LEFT_0) | 1675 (1 << AC97_SLOT_PCM_RIGHT_0) 1676 } 1677 } 1678 }, 1679 /* PCM IN #1 */ 1680 { 1681 .stream = 1, 1682 .exclusive = 1, 1683 .r = { { 1684 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1685 (1 << AC97_SLOT_PCM_RIGHT) 1686 } 1687 } 1688 }, 1689 /* MIC IN #1 */ 1690 { 1691 .stream = 1, 1692 .exclusive = 1, 1693 .r = { { 1694 .slots = (1 << AC97_SLOT_MIC) 1695 } 1696 } 1697 }, 1698 /* S/PDIF PCM */ 1699 { 1700 .exclusive = 1, 1701 .spdif = 1, 1702 .r = { { 1703 .slots = (1 << AC97_SLOT_SPDIF_LEFT2) | 1704 (1 << AC97_SLOT_SPDIF_RIGHT2) 1705 } 1706 } 1707 }, 1708 /* PCM IN #2 */ 1709 { 1710 .stream = 1, 1711 .exclusive = 1, 1712 .r = { { 1713 .slots = (1 << AC97_SLOT_PCM_LEFT) | 1714 (1 << AC97_SLOT_PCM_RIGHT) 1715 } 1716 } 1717 }, 1718 /* MIC IN #2 */ 1719 { 1720 .stream = 1, 1721 .exclusive = 1, 1722 .r = { { 1723 .slots = (1 << AC97_SLOT_MIC) 1724 } 1725 } 1726 }, 1727 }; 1728 1729 static struct ac97_quirk ac97_quirks[] __devinitdata = { 1730 { 1731 .subvendor = 0x0e11, 1732 .subdevice = 0x000e, 1733 .name = "Compaq Deskpro EN", /* AD1885 */ 1734 .type = AC97_TUNE_HP_ONLY 1735 }, 1736 { 1737 .subvendor = 0x0e11, 1738 .subdevice = 0x008a, 1739 .name = "Compaq Evo W4000", /* AD1885 */ 1740 .type = AC97_TUNE_HP_ONLY 1741 }, 1742 { 1743 .subvendor = 0x0e11, 1744 .subdevice = 0x00b8, 1745 .name = "Compaq Evo D510C", 1746 .type = AC97_TUNE_HP_ONLY 1747 }, 1748 { 1749 .subvendor = 0x0e11, 1750 .subdevice = 0x0860, 1751 .name = "HP/Compaq nx7010", 1752 .type = AC97_TUNE_MUTE_LED 1753 }, 1754 { 1755 .subvendor = 0x1014, 1756 .subdevice = 0x1f00, 1757 .name = "MS-9128", 1758 .type = AC97_TUNE_ALC_JACK 1759 }, 1760 { 1761 .subvendor = 0x1014, 1762 .subdevice = 0x0267, 1763 .name = "IBM NetVista A30p", /* AD1981B */ 1764 .type = AC97_TUNE_HP_ONLY 1765 }, 1766 { 1767 .subvendor = 0x1025, 1768 .subdevice = 0x0082, 1769 .name = "Acer Travelmate 2310", 1770 .type = AC97_TUNE_HP_ONLY 1771 }, 1772 { 1773 .subvendor = 0x1025, 1774 .subdevice = 0x0083, 1775 .name = "Acer Aspire 3003LCi", 1776 .type = AC97_TUNE_HP_ONLY 1777 }, 1778 { 1779 .subvendor = 0x1028, 1780 .subdevice = 0x00d8, 1781 .name = "Dell Precision 530", /* AD1885 */ 1782 .type = AC97_TUNE_HP_ONLY 1783 }, 1784 { 1785 .subvendor = 0x1028, 1786 .subdevice = 0x010d, 1787 .name = "Dell", /* which model? AD1885 */ 1788 .type = AC97_TUNE_HP_ONLY 1789 }, 1790 { 1791 .subvendor = 0x1028, 1792 .subdevice = 0x0126, 1793 .name = "Dell Optiplex GX260", /* AD1981A */ 1794 .type = AC97_TUNE_HP_ONLY 1795 }, 1796 { 1797 .subvendor = 0x1028, 1798 .subdevice = 0x012c, 1799 .name = "Dell Precision 650", /* AD1981A */ 1800 .type = AC97_TUNE_HP_ONLY 1801 }, 1802 { 1803 .subvendor = 0x1028, 1804 .subdevice = 0x012d, 1805 .name = "Dell Precision 450", /* AD1981B*/ 1806 .type = AC97_TUNE_HP_ONLY 1807 }, 1808 { 1809 .subvendor = 0x1028, 1810 .subdevice = 0x0147, 1811 .name = "Dell", /* which model? AD1981B*/ 1812 .type = AC97_TUNE_HP_ONLY 1813 }, 1814 { 1815 .subvendor = 0x1028, 1816 .subdevice = 0x0151, 1817 .name = "Dell Optiplex GX270", /* AD1981B */ 1818 .type = AC97_TUNE_HP_ONLY 1819 }, 1820 { 1821 .subvendor = 0x1028, 1822 .subdevice = 0x014e, 1823 .name = "Dell D800", /* STAC9750/51 */ 1824 .type = AC97_TUNE_HP_ONLY 1825 }, 1826 { 1827 .subvendor = 0x1028, 1828 .subdevice = 0x0163, 1829 .name = "Dell Unknown", /* STAC9750/51 */ 1830 .type = AC97_TUNE_HP_ONLY 1831 }, 1832 { 1833 .subvendor = 0x1028, 1834 .subdevice = 0x0186, 1835 .name = "Dell Latitude D810", /* cf. Malone #41015 */ 1836 .type = AC97_TUNE_HP_MUTE_LED 1837 }, 1838 { 1839 .subvendor = 0x1028, 1840 .subdevice = 0x0188, 1841 .name = "Dell Inspiron 6000", 1842 .type = AC97_TUNE_HP_MUTE_LED /* cf. Malone #41015 */ 1843 }, 1844 { 1845 .subvendor = 0x1028, 1846 .subdevice = 0x0191, 1847 .name = "Dell Inspiron 8600", 1848 .type = AC97_TUNE_HP_ONLY 1849 }, 1850 { 1851 .subvendor = 0x103c, 1852 .subdevice = 0x006d, 1853 .name = "HP zv5000", 1854 .type = AC97_TUNE_MUTE_LED /*AD1981B*/ 1855 }, 1856 { /* FIXME: which codec? */ 1857 .subvendor = 0x103c, 1858 .subdevice = 0x00c3, 1859 .name = "HP xw6000", 1860 .type = AC97_TUNE_HP_ONLY 1861 }, 1862 { 1863 .subvendor = 0x103c, 1864 .subdevice = 0x088c, 1865 .name = "HP nc8000", 1866 .type = AC97_TUNE_HP_MUTE_LED 1867 }, 1868 { 1869 .subvendor = 0x103c, 1870 .subdevice = 0x0890, 1871 .name = "HP nc6000", 1872 .type = AC97_TUNE_MUTE_LED 1873 }, 1874 { 1875 .subvendor = 0x103c, 1876 .subdevice = 0x0934, 1877 .name = "HP nx8220", 1878 .type = AC97_TUNE_MUTE_LED 1879 }, 1880 { 1881 .subvendor = 0x103c, 1882 .subdevice = 0x129d, 1883 .name = "HP xw8000", 1884 .type = AC97_TUNE_HP_ONLY 1885 }, 1886 { 1887 .subvendor = 0x103c, 1888 .subdevice = 0x0938, 1889 .name = "HP nc4200", 1890 .type = AC97_TUNE_HP_MUTE_LED 1891 }, 1892 { 1893 .subvendor = 0x103c, 1894 .subdevice = 0x099c, 1895 .name = "HP nx6110/nc6120", 1896 .type = AC97_TUNE_HP_MUTE_LED 1897 }, 1898 { 1899 .subvendor = 0x103c, 1900 .subdevice = 0x0944, 1901 .name = "HP nc6220", 1902 .type = AC97_TUNE_HP_MUTE_LED 1903 }, 1904 { 1905 .subvendor = 0x103c, 1906 .subdevice = 0x0934, 1907 .name = "HP nc8220", 1908 .type = AC97_TUNE_HP_MUTE_LED 1909 }, 1910 { 1911 .subvendor = 0x103c, 1912 .subdevice = 0x12f1, 1913 .name = "HP xw8200", /* AD1981B*/ 1914 .type = AC97_TUNE_HP_ONLY 1915 }, 1916 { 1917 .subvendor = 0x103c, 1918 .subdevice = 0x12f2, 1919 .name = "HP xw6200", 1920 .type = AC97_TUNE_HP_ONLY 1921 }, 1922 { 1923 .subvendor = 0x103c, 1924 .subdevice = 0x3008, 1925 .name = "HP xw4200", /* AD1981B*/ 1926 .type = AC97_TUNE_HP_ONLY 1927 }, 1928 { 1929 .subvendor = 0x104d, 1930 .subdevice = 0x8197, 1931 .name = "Sony S1XP", 1932 .type = AC97_TUNE_INV_EAPD 1933 }, 1934 { 1935 .subvendor = 0x1043, 1936 .subdevice = 0x80f3, 1937 .name = "ASUS ICH5/AD1985", 1938 .type = AC97_TUNE_AD_SHARING 1939 }, 1940 { 1941 .subvendor = 0x10cf, 1942 .subdevice = 0x11c3, 1943 .name = "Fujitsu-Siemens E4010", 1944 .type = AC97_TUNE_HP_ONLY 1945 }, 1946 { 1947 .subvendor = 0x10cf, 1948 .subdevice = 0x1225, 1949 .name = "Fujitsu-Siemens T3010", 1950 .type = AC97_TUNE_HP_ONLY 1951 }, 1952 { 1953 .subvendor = 0x10cf, 1954 .subdevice = 0x1253, 1955 .name = "Fujitsu S6210", /* STAC9750/51 */ 1956 .type = AC97_TUNE_HP_ONLY 1957 }, 1958 { 1959 .subvendor = 0x10cf, 1960 .subdevice = 0x127e, 1961 .name = "Fujitsu Lifebook C1211D", 1962 .type = AC97_TUNE_HP_ONLY 1963 }, 1964 { 1965 .subvendor = 0x10cf, 1966 .subdevice = 0x12ec, 1967 .name = "Fujitsu-Siemens 4010", 1968 .type = AC97_TUNE_HP_ONLY 1969 }, 1970 { 1971 .subvendor = 0x10cf, 1972 .subdevice = 0x12f2, 1973 .name = "Fujitsu-Siemens Celsius H320", 1974 .type = AC97_TUNE_SWAP_HP 1975 }, 1976 { 1977 .subvendor = 0x10f1, 1978 .subdevice = 0x2665, 1979 .name = "Fujitsu-Siemens Celsius", /* AD1981? */ 1980 .type = AC97_TUNE_HP_ONLY 1981 }, 1982 { 1983 .subvendor = 0x10f1, 1984 .subdevice = 0x2885, 1985 .name = "AMD64 Mobo", /* ALC650 */ 1986 .type = AC97_TUNE_HP_ONLY 1987 }, 1988 { 1989 .subvendor = 0x10f1, 1990 .subdevice = 0x2895, 1991 .name = "Tyan Thunder K8WE", 1992 .type = AC97_TUNE_HP_ONLY 1993 }, 1994 { 1995 .subvendor = 0x10f7, 1996 .subdevice = 0x834c, 1997 .name = "Panasonic CF-R4", 1998 .type = AC97_TUNE_HP_ONLY, 1999 }, 2000 { 2001 .subvendor = 0x110a, 2002 .subdevice = 0x0056, 2003 .name = "Fujitsu-Siemens Scenic", /* AD1981? */ 2004 .type = AC97_TUNE_HP_ONLY 2005 }, 2006 { 2007 .subvendor = 0x11d4, 2008 .subdevice = 0x5375, 2009 .name = "ADI AD1985 (discrete)", 2010 .type = AC97_TUNE_HP_ONLY 2011 }, 2012 { 2013 .subvendor = 0x1462, 2014 .subdevice = 0x5470, 2015 .name = "MSI P4 ATX 645 Ultra", 2016 .type = AC97_TUNE_HP_ONLY 2017 }, 2018 { 2019 .subvendor = 0x1734, 2020 .subdevice = 0x0088, 2021 .name = "Fujitsu-Siemens D1522", /* AD1981 */ 2022 .type = AC97_TUNE_HP_ONLY 2023 }, 2024 { 2025 .subvendor = 0x8086, 2026 .subdevice = 0x2000, 2027 .mask = 0xfff0, 2028 .name = "Intel ICH5/AD1985", 2029 .type = AC97_TUNE_AD_SHARING 2030 }, 2031 { 2032 .subvendor = 0x8086, 2033 .subdevice = 0x4000, 2034 .mask = 0xfff0, 2035 .name = "Intel ICH5/AD1985", 2036 .type = AC97_TUNE_AD_SHARING 2037 }, 2038 { 2039 .subvendor = 0x8086, 2040 .subdevice = 0x4856, 2041 .name = "Intel D845WN (82801BA)", 2042 .type = AC97_TUNE_SWAP_HP 2043 }, 2044 { 2045 .subvendor = 0x8086, 2046 .subdevice = 0x4d44, 2047 .name = "Intel D850EMV2", /* AD1885 */ 2048 .type = AC97_TUNE_HP_ONLY 2049 }, 2050 { 2051 .subvendor = 0x8086, 2052 .subdevice = 0x4d56, 2053 .name = "Intel ICH/AD1885", 2054 .type = AC97_TUNE_HP_ONLY 2055 }, 2056 { 2057 .subvendor = 0x8086, 2058 .subdevice = 0x6000, 2059 .mask = 0xfff0, 2060 .name = "Intel ICH5/AD1985", 2061 .type = AC97_TUNE_AD_SHARING 2062 }, 2063 { 2064 .subvendor = 0x8086, 2065 .subdevice = 0xe000, 2066 .mask = 0xfff0, 2067 .name = "Intel ICH5/AD1985", 2068 .type = AC97_TUNE_AD_SHARING 2069 }, 2070 #if 0 /* FIXME: this seems wrong on most boards */ 2071 { 2072 .subvendor = 0x8086, 2073 .subdevice = 0xa000, 2074 .mask = 0xfff0, 2075 .name = "Intel ICH5/AD1985", 2076 .type = AC97_TUNE_HP_ONLY 2077 }, 2078 #endif 2079 { } /* terminator */ 2080 }; 2081 2082 static int __devinit snd_intel8x0_mixer(struct intel8x0 *chip, int ac97_clock, 2083 const char *quirk_override) 2084 { 2085 struct snd_ac97_bus *pbus; 2086 struct snd_ac97_template ac97; 2087 int err; 2088 unsigned int i, codecs; 2089 unsigned int glob_sta = 0; 2090 struct snd_ac97_bus_ops *ops; 2091 static struct snd_ac97_bus_ops standard_bus_ops = { 2092 .write = snd_intel8x0_codec_write, 2093 .read = snd_intel8x0_codec_read, 2094 }; 2095 static struct snd_ac97_bus_ops ali_bus_ops = { 2096 .write = snd_intel8x0_ali_codec_write, 2097 .read = snd_intel8x0_ali_codec_read, 2098 }; 2099 2100 chip->spdif_idx = -1; /* use PCMOUT (or disabled) */ 2101 if (!spdif_aclink) { 2102 switch (chip->device_type) { 2103 case DEVICE_NFORCE: 2104 chip->spdif_idx = NVD_SPBAR; 2105 break; 2106 case DEVICE_ALI: 2107 chip->spdif_idx = ALID_AC97SPDIFOUT; 2108 break; 2109 case DEVICE_INTEL_ICH4: 2110 chip->spdif_idx = ICHD_SPBAR; 2111 break; 2112 }; 2113 } 2114 2115 chip->in_ac97_init = 1; 2116 2117 memset(&ac97, 0, sizeof(ac97)); 2118 ac97.private_data = chip; 2119 ac97.private_free = snd_intel8x0_mixer_free_ac97; 2120 ac97.scaps = AC97_SCAP_SKIP_MODEM | AC97_SCAP_POWER_SAVE; 2121 if (chip->xbox) 2122 ac97.scaps |= AC97_SCAP_DETECT_BY_VENDOR; 2123 if (chip->device_type != DEVICE_ALI) { 2124 glob_sta = igetdword(chip, ICHREG(GLOB_STA)); 2125 ops = &standard_bus_ops; 2126 chip->in_sdin_init = 1; 2127 codecs = 0; 2128 for (i = 0; i < chip->max_codecs; i++) { 2129 if (! (glob_sta & chip->codec_bit[i])) 2130 continue; 2131 if (chip->device_type == DEVICE_INTEL_ICH4) { 2132 snd_intel8x0_codec_read_test(chip, codecs); 2133 chip->ac97_sdin[codecs] = 2134 igetbyte(chip, ICHREG(SDM)) & ICH_LDI_MASK; 2135 snd_assert(chip->ac97_sdin[codecs] < 3, 2136 chip->ac97_sdin[codecs] = 0); 2137 } else 2138 chip->ac97_sdin[codecs] = i; 2139 codecs++; 2140 } 2141 chip->in_sdin_init = 0; 2142 if (! codecs) 2143 codecs = 1; 2144 } else { 2145 ops = &ali_bus_ops; 2146 codecs = 1; 2147 /* detect the secondary codec */ 2148 for (i = 0; i < 100; i++) { 2149 unsigned int reg = igetdword(chip, ICHREG(ALI_RTSR)); 2150 if (reg & 0x40) { 2151 codecs = 2; 2152 break; 2153 } 2154 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x40); 2155 udelay(1); 2156 } 2157 } 2158 if ((err = snd_ac97_bus(chip->card, 0, ops, chip, &pbus)) < 0) 2159 goto __err; 2160 pbus->private_free = snd_intel8x0_mixer_free_ac97_bus; 2161 if (ac97_clock >= 8000 && ac97_clock <= 48000) 2162 pbus->clock = ac97_clock; 2163 /* FIXME: my test board doesn't work well with VRA... */ 2164 if (chip->device_type == DEVICE_ALI) 2165 pbus->no_vra = 1; 2166 else 2167 pbus->dra = 1; 2168 chip->ac97_bus = pbus; 2169 chip->ncodecs = codecs; 2170 2171 ac97.pci = chip->pci; 2172 for (i = 0; i < codecs; i++) { 2173 ac97.num = i; 2174 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) { 2175 if (err != -EACCES) 2176 snd_printk(KERN_ERR "Unable to initialize codec #%d\n", i); 2177 if (i == 0) 2178 goto __err; 2179 } 2180 } 2181 /* tune up the primary codec */ 2182 snd_ac97_tune_hardware(chip->ac97[0], ac97_quirks, quirk_override); 2183 /* enable separate SDINs for ICH4 */ 2184 if (chip->device_type == DEVICE_INTEL_ICH4) 2185 pbus->isdin = 1; 2186 /* find the available PCM streams */ 2187 i = ARRAY_SIZE(ac97_pcm_defs); 2188 if (chip->device_type != DEVICE_INTEL_ICH4) 2189 i -= 2; /* do not allocate PCM2IN and MIC2 */ 2190 if (chip->spdif_idx < 0) 2191 i--; /* do not allocate S/PDIF */ 2192 err = snd_ac97_pcm_assign(pbus, i, ac97_pcm_defs); 2193 if (err < 0) 2194 goto __err; 2195 chip->ichd[ICHD_PCMOUT].pcm = &pbus->pcms[0]; 2196 chip->ichd[ICHD_PCMIN].pcm = &pbus->pcms[1]; 2197 chip->ichd[ICHD_MIC].pcm = &pbus->pcms[2]; 2198 if (chip->spdif_idx >= 0) 2199 chip->ichd[chip->spdif_idx].pcm = &pbus->pcms[3]; 2200 if (chip->device_type == DEVICE_INTEL_ICH4) { 2201 chip->ichd[ICHD_PCM2IN].pcm = &pbus->pcms[4]; 2202 chip->ichd[ICHD_MIC2].pcm = &pbus->pcms[5]; 2203 } 2204 /* enable separate SDINs for ICH4 */ 2205 if (chip->device_type == DEVICE_INTEL_ICH4) { 2206 struct ac97_pcm *pcm = chip->ichd[ICHD_PCM2IN].pcm; 2207 u8 tmp = igetbyte(chip, ICHREG(SDM)); 2208 tmp &= ~(ICH_DI2L_MASK|ICH_DI1L_MASK); 2209 if (pcm) { 2210 tmp |= ICH_SE; /* steer enable for multiple SDINs */ 2211 tmp |= chip->ac97_sdin[0] << ICH_DI1L_SHIFT; 2212 for (i = 1; i < 4; i++) { 2213 if (pcm->r[0].codec[i]) { 2214 tmp |= chip->ac97_sdin[pcm->r[0].codec[1]->num] << ICH_DI2L_SHIFT; 2215 break; 2216 } 2217 } 2218 } else { 2219 tmp &= ~ICH_SE; /* steer disable */ 2220 } 2221 iputbyte(chip, ICHREG(SDM), tmp); 2222 } 2223 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_PCM_SLEFT)) { 2224 chip->multi4 = 1; 2225 if (pbus->pcms[0].r[0].slots & (1 << AC97_SLOT_LFE)) { 2226 chip->multi6 = 1; 2227 if (chip->ac97[0]->flags & AC97_HAS_8CH) 2228 chip->multi8 = 1; 2229 } 2230 } 2231 if (pbus->pcms[0].r[1].rslots[0]) { 2232 chip->dra = 1; 2233 } 2234 if (chip->device_type == DEVICE_INTEL_ICH4) { 2235 if ((igetdword(chip, ICHREG(GLOB_STA)) & ICH_SAMPLE_CAP) == ICH_SAMPLE_16_20) 2236 chip->smp20bit = 1; 2237 } 2238 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2239 /* 48kHz only */ 2240 chip->ichd[chip->spdif_idx].pcm->rates = SNDRV_PCM_RATE_48000; 2241 } 2242 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2243 /* use slot 10/11 for SPDIF */ 2244 u32 val; 2245 val = igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK; 2246 val |= ICH_PCM_SPDIF_1011; 2247 iputdword(chip, ICHREG(GLOB_CNT), val); 2248 snd_ac97_update_bits(chip->ac97[0], AC97_EXTENDED_STATUS, 0x03 << 4, 0x03 << 4); 2249 } 2250 chip->in_ac97_init = 0; 2251 return 0; 2252 2253 __err: 2254 /* clear the cold-reset bit for the next chance */ 2255 if (chip->device_type != DEVICE_ALI) 2256 iputdword(chip, ICHREG(GLOB_CNT), 2257 igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_AC97COLD); 2258 return err; 2259 } 2260 2261 2262 /* 2263 * 2264 */ 2265 2266 static void do_ali_reset(struct intel8x0 *chip) 2267 { 2268 iputdword(chip, ICHREG(ALI_SCR), ICH_ALI_SC_RESET); 2269 iputdword(chip, ICHREG(ALI_FIFOCR1), 0x83838383); 2270 iputdword(chip, ICHREG(ALI_FIFOCR2), 0x83838383); 2271 iputdword(chip, ICHREG(ALI_FIFOCR3), 0x83838383); 2272 iputdword(chip, ICHREG(ALI_INTERFACECR), 2273 ICH_ALI_IF_PI|ICH_ALI_IF_PO); 2274 iputdword(chip, ICHREG(ALI_INTERRUPTCR), 0x00000000); 2275 iputdword(chip, ICHREG(ALI_INTERRUPTSR), 0x00000000); 2276 } 2277 2278 static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) 2279 { 2280 unsigned long end_time; 2281 unsigned int cnt, status, nstatus; 2282 2283 /* put logic to right state */ 2284 /* first clear status bits */ 2285 status = ICH_RCS | ICH_MCINT | ICH_POINT | ICH_PIINT; 2286 if (chip->device_type == DEVICE_NFORCE) 2287 status |= ICH_NVSPINT; 2288 cnt = igetdword(chip, ICHREG(GLOB_STA)); 2289 iputdword(chip, ICHREG(GLOB_STA), cnt & status); 2290 2291 /* ACLink on, 2 channels */ 2292 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2293 cnt &= ~(ICH_ACLINK | ICH_PCM_246_MASK); 2294 #ifdef CONFIG_SND_AC97_POWER_SAVE 2295 /* do cold reset - the full ac97 powerdown may leave the controller 2296 * in a warm state but actually it cannot communicate with the codec. 2297 */ 2298 iputdword(chip, ICHREG(GLOB_CNT), cnt & ~ICH_AC97COLD); 2299 cnt = igetdword(chip, ICHREG(GLOB_CNT)); 2300 udelay(10); 2301 iputdword(chip, ICHREG(GLOB_CNT), cnt | ICH_AC97COLD); 2302 msleep(1); 2303 #else 2304 /* finish cold or do warm reset */ 2305 cnt |= (cnt & ICH_AC97COLD) == 0 ? ICH_AC97COLD : ICH_AC97WARM; 2306 iputdword(chip, ICHREG(GLOB_CNT), cnt); 2307 end_time = (jiffies + (HZ / 4)) + 1; 2308 do { 2309 if ((igetdword(chip, ICHREG(GLOB_CNT)) & ICH_AC97WARM) == 0) 2310 goto __ok; 2311 schedule_timeout_uninterruptible(1); 2312 } while (time_after_eq(end_time, jiffies)); 2313 snd_printk(KERN_ERR "AC'97 warm reset still in progress? [0x%x]\n", 2314 igetdword(chip, ICHREG(GLOB_CNT))); 2315 return -EIO; 2316 2317 __ok: 2318 #endif 2319 if (probing) { 2320 /* wait for any codec ready status. 2321 * Once it becomes ready it should remain ready 2322 * as long as we do not disable the ac97 link. 2323 */ 2324 end_time = jiffies + HZ; 2325 do { 2326 status = igetdword(chip, ICHREG(GLOB_STA)) & 2327 chip->codec_isr_bits; 2328 if (status) 2329 break; 2330 schedule_timeout_uninterruptible(1); 2331 } while (time_after_eq(end_time, jiffies)); 2332 if (! status) { 2333 /* no codec is found */ 2334 snd_printk(KERN_ERR "codec_ready: codec is not ready [0x%x]\n", 2335 igetdword(chip, ICHREG(GLOB_STA))); 2336 return -EIO; 2337 } 2338 2339 /* wait for other codecs ready status. */ 2340 end_time = jiffies + HZ / 4; 2341 while (status != chip->codec_isr_bits && 2342 time_after_eq(end_time, jiffies)) { 2343 schedule_timeout_uninterruptible(1); 2344 status |= igetdword(chip, ICHREG(GLOB_STA)) & 2345 chip->codec_isr_bits; 2346 } 2347 2348 } else { 2349 /* resume phase */ 2350 int i; 2351 status = 0; 2352 for (i = 0; i < chip->ncodecs; i++) 2353 if (chip->ac97[i]) 2354 status |= chip->codec_bit[chip->ac97_sdin[i]]; 2355 /* wait until all the probed codecs are ready */ 2356 end_time = jiffies + HZ; 2357 do { 2358 nstatus = igetdword(chip, ICHREG(GLOB_STA)) & 2359 chip->codec_isr_bits; 2360 if (status == nstatus) 2361 break; 2362 schedule_timeout_uninterruptible(1); 2363 } while (time_after_eq(end_time, jiffies)); 2364 } 2365 2366 if (chip->device_type == DEVICE_SIS) { 2367 /* unmute the output on SIS7012 */ 2368 iputword(chip, 0x4c, igetword(chip, 0x4c) | 1); 2369 } 2370 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2371 /* enable SPDIF interrupt */ 2372 unsigned int val; 2373 pci_read_config_dword(chip->pci, 0x4c, &val); 2374 val |= 0x1000000; 2375 pci_write_config_dword(chip->pci, 0x4c, val); 2376 } 2377 return 0; 2378 } 2379 2380 static int snd_intel8x0_ali_chip_init(struct intel8x0 *chip, int probing) 2381 { 2382 u32 reg; 2383 int i = 0; 2384 2385 reg = igetdword(chip, ICHREG(ALI_SCR)); 2386 if ((reg & 2) == 0) /* Cold required */ 2387 reg |= 2; 2388 else 2389 reg |= 1; /* Warm */ 2390 reg &= ~0x80000000; /* ACLink on */ 2391 iputdword(chip, ICHREG(ALI_SCR), reg); 2392 2393 for (i = 0; i < HZ / 2; i++) { 2394 if (! (igetdword(chip, ICHREG(ALI_INTERRUPTSR)) & ALI_INT_GPIO)) 2395 goto __ok; 2396 schedule_timeout_uninterruptible(1); 2397 } 2398 snd_printk(KERN_ERR "AC'97 reset failed.\n"); 2399 if (probing) 2400 return -EIO; 2401 2402 __ok: 2403 for (i = 0; i < HZ / 2; i++) { 2404 reg = igetdword(chip, ICHREG(ALI_RTSR)); 2405 if (reg & 0x80) /* primary codec */ 2406 break; 2407 iputdword(chip, ICHREG(ALI_RTSR), reg | 0x80); 2408 schedule_timeout_uninterruptible(1); 2409 } 2410 2411 do_ali_reset(chip); 2412 return 0; 2413 } 2414 2415 static int snd_intel8x0_chip_init(struct intel8x0 *chip, int probing) 2416 { 2417 unsigned int i, timeout; 2418 int err; 2419 2420 if (chip->device_type != DEVICE_ALI) { 2421 if ((err = snd_intel8x0_ich_chip_init(chip, probing)) < 0) 2422 return err; 2423 iagetword(chip, 0); /* clear semaphore flag */ 2424 } else { 2425 if ((err = snd_intel8x0_ali_chip_init(chip, probing)) < 0) 2426 return err; 2427 } 2428 2429 /* disable interrupts */ 2430 for (i = 0; i < chip->bdbars_count; i++) 2431 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2432 /* reset channels */ 2433 for (i = 0; i < chip->bdbars_count; i++) 2434 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2435 for (i = 0; i < chip->bdbars_count; i++) { 2436 timeout = 100000; 2437 while (--timeout != 0) { 2438 if ((igetbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset) & ICH_RESETREGS) == 0) 2439 break; 2440 } 2441 if (timeout == 0) 2442 printk(KERN_ERR "intel8x0: reset of registers failed?\n"); 2443 } 2444 /* initialize Buffer Descriptor Lists */ 2445 for (i = 0; i < chip->bdbars_count; i++) 2446 iputdword(chip, ICH_REG_OFF_BDBAR + chip->ichd[i].reg_offset, 2447 chip->ichd[i].bdbar_addr); 2448 return 0; 2449 } 2450 2451 static int snd_intel8x0_free(struct intel8x0 *chip) 2452 { 2453 unsigned int i; 2454 2455 if (chip->irq < 0) 2456 goto __hw_end; 2457 /* disable interrupts */ 2458 for (i = 0; i < chip->bdbars_count; i++) 2459 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, 0x00); 2460 /* reset channels */ 2461 for (i = 0; i < chip->bdbars_count; i++) 2462 iputbyte(chip, ICH_REG_OFF_CR + chip->ichd[i].reg_offset, ICH_RESETREGS); 2463 if (chip->device_type == DEVICE_NFORCE && !spdif_aclink) { 2464 /* stop the spdif interrupt */ 2465 unsigned int val; 2466 pci_read_config_dword(chip->pci, 0x4c, &val); 2467 val &= ~0x1000000; 2468 pci_write_config_dword(chip->pci, 0x4c, val); 2469 } 2470 /* --- */ 2471 2472 __hw_end: 2473 if (chip->irq >= 0) 2474 free_irq(chip->irq, chip); 2475 if (chip->bdbars.area) { 2476 if (chip->fix_nocache) 2477 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 0); 2478 snd_dma_free_pages(&chip->bdbars); 2479 } 2480 if (chip->addr) 2481 pci_iounmap(chip->pci, chip->addr); 2482 if (chip->bmaddr) 2483 pci_iounmap(chip->pci, chip->bmaddr); 2484 pci_release_regions(chip->pci); 2485 pci_disable_device(chip->pci); 2486 kfree(chip); 2487 return 0; 2488 } 2489 2490 #ifdef CONFIG_PM 2491 /* 2492 * power management 2493 */ 2494 static int intel8x0_suspend(struct pci_dev *pci, pm_message_t state) 2495 { 2496 struct snd_card *card = pci_get_drvdata(pci); 2497 struct intel8x0 *chip = card->private_data; 2498 int i; 2499 2500 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 2501 for (i = 0; i < chip->pcm_devs; i++) 2502 snd_pcm_suspend_all(chip->pcm[i]); 2503 /* clear nocache */ 2504 if (chip->fix_nocache) { 2505 for (i = 0; i < chip->bdbars_count; i++) { 2506 struct ichdev *ichdev = &chip->ichd[i]; 2507 if (ichdev->substream && ichdev->page_attr_changed) { 2508 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2509 if (runtime->dma_area) 2510 fill_nocache(runtime->dma_area, runtime->dma_bytes, 0); 2511 } 2512 } 2513 } 2514 for (i = 0; i < chip->ncodecs; i++) 2515 snd_ac97_suspend(chip->ac97[i]); 2516 if (chip->device_type == DEVICE_INTEL_ICH4) 2517 chip->sdm_saved = igetbyte(chip, ICHREG(SDM)); 2518 2519 if (chip->irq >= 0) { 2520 free_irq(chip->irq, chip); 2521 chip->irq = -1; 2522 } 2523 pci_disable_device(pci); 2524 pci_save_state(pci); 2525 /* The call below may disable built-in speaker on some laptops 2526 * after S2RAM. So, don't touch it. 2527 */ 2528 /* pci_set_power_state(pci, pci_choose_state(pci, state)); */ 2529 return 0; 2530 } 2531 2532 static int intel8x0_resume(struct pci_dev *pci) 2533 { 2534 struct snd_card *card = pci_get_drvdata(pci); 2535 struct intel8x0 *chip = card->private_data; 2536 int i; 2537 2538 pci_set_power_state(pci, PCI_D0); 2539 pci_restore_state(pci); 2540 if (pci_enable_device(pci) < 0) { 2541 printk(KERN_ERR "intel8x0: pci_enable_device failed, " 2542 "disabling device\n"); 2543 snd_card_disconnect(card); 2544 return -EIO; 2545 } 2546 pci_set_master(pci); 2547 snd_intel8x0_chip_init(chip, 0); 2548 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2549 IRQF_SHARED, card->shortname, chip)) { 2550 printk(KERN_ERR "intel8x0: unable to grab IRQ %d, " 2551 "disabling device\n", pci->irq); 2552 snd_card_disconnect(card); 2553 return -EIO; 2554 } 2555 chip->irq = pci->irq; 2556 synchronize_irq(chip->irq); 2557 2558 /* re-initialize mixer stuff */ 2559 if (chip->device_type == DEVICE_INTEL_ICH4 && !spdif_aclink) { 2560 /* enable separate SDINs for ICH4 */ 2561 iputbyte(chip, ICHREG(SDM), chip->sdm_saved); 2562 /* use slot 10/11 for SPDIF */ 2563 iputdword(chip, ICHREG(GLOB_CNT), 2564 (igetdword(chip, ICHREG(GLOB_CNT)) & ~ICH_PCM_SPDIF_MASK) | 2565 ICH_PCM_SPDIF_1011); 2566 } 2567 2568 /* refill nocache */ 2569 if (chip->fix_nocache) 2570 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2571 2572 for (i = 0; i < chip->ncodecs; i++) 2573 snd_ac97_resume(chip->ac97[i]); 2574 2575 /* refill nocache */ 2576 if (chip->fix_nocache) { 2577 for (i = 0; i < chip->bdbars_count; i++) { 2578 struct ichdev *ichdev = &chip->ichd[i]; 2579 if (ichdev->substream && ichdev->page_attr_changed) { 2580 struct snd_pcm_runtime *runtime = ichdev->substream->runtime; 2581 if (runtime->dma_area) 2582 fill_nocache(runtime->dma_area, runtime->dma_bytes, 1); 2583 } 2584 } 2585 } 2586 2587 /* resume status */ 2588 for (i = 0; i < chip->bdbars_count; i++) { 2589 struct ichdev *ichdev = &chip->ichd[i]; 2590 unsigned long port = ichdev->reg_offset; 2591 if (! ichdev->substream || ! ichdev->suspended) 2592 continue; 2593 if (ichdev->ichd == ICHD_PCMOUT) 2594 snd_intel8x0_setup_pcm_out(chip, ichdev->substream->runtime); 2595 iputdword(chip, port + ICH_REG_OFF_BDBAR, ichdev->bdbar_addr); 2596 iputbyte(chip, port + ICH_REG_OFF_LVI, ichdev->lvi); 2597 iputbyte(chip, port + ICH_REG_OFF_CIV, ichdev->civ); 2598 iputbyte(chip, port + ichdev->roff_sr, ICH_FIFOE | ICH_BCIS | ICH_LVBCI); 2599 } 2600 2601 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 2602 return 0; 2603 } 2604 #endif /* CONFIG_PM */ 2605 2606 #define INTEL8X0_TESTBUF_SIZE 32768 /* enough large for one shot */ 2607 2608 static void __devinit intel8x0_measure_ac97_clock(struct intel8x0 *chip) 2609 { 2610 struct snd_pcm_substream *subs; 2611 struct ichdev *ichdev; 2612 unsigned long port; 2613 unsigned long pos, t; 2614 struct timeval start_time, stop_time; 2615 2616 if (chip->ac97_bus->clock != 48000) 2617 return; /* specified in module option */ 2618 2619 subs = chip->pcm[0]->streams[0].substream; 2620 if (! subs || subs->dma_buffer.bytes < INTEL8X0_TESTBUF_SIZE) { 2621 snd_printk(KERN_WARNING "no playback buffer allocated - aborting measure ac97 clock\n"); 2622 return; 2623 } 2624 ichdev = &chip->ichd[ICHD_PCMOUT]; 2625 ichdev->physbuf = subs->dma_buffer.addr; 2626 ichdev->size = chip->ichd[ICHD_PCMOUT].fragsize = INTEL8X0_TESTBUF_SIZE; 2627 ichdev->substream = NULL; /* don't process interrupts */ 2628 2629 /* set rate */ 2630 if (snd_ac97_set_rate(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 48000) < 0) { 2631 snd_printk(KERN_ERR "cannot set ac97 rate: clock = %d\n", chip->ac97_bus->clock); 2632 return; 2633 } 2634 snd_intel8x0_setup_periods(chip, ichdev); 2635 port = ichdev->reg_offset; 2636 spin_lock_irq(&chip->reg_lock); 2637 chip->in_measurement = 1; 2638 /* trigger */ 2639 if (chip->device_type != DEVICE_ALI) 2640 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE | ICH_STARTBM); 2641 else { 2642 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_IOCE); 2643 iputdword(chip, ICHREG(ALI_DMACR), 1 << ichdev->ali_slot); 2644 } 2645 do_gettimeofday(&start_time); 2646 spin_unlock_irq(&chip->reg_lock); 2647 msleep(50); 2648 spin_lock_irq(&chip->reg_lock); 2649 /* check the position */ 2650 pos = ichdev->fragsize1; 2651 pos -= igetword(chip, ichdev->reg_offset + ichdev->roff_picb) << ichdev->pos_shift; 2652 pos += ichdev->position; 2653 chip->in_measurement = 0; 2654 do_gettimeofday(&stop_time); 2655 /* stop */ 2656 if (chip->device_type == DEVICE_ALI) { 2657 iputdword(chip, ICHREG(ALI_DMACR), 1 << (ichdev->ali_slot + 16)); 2658 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2659 while (igetbyte(chip, port + ICH_REG_OFF_CR)) 2660 ; 2661 } else { 2662 iputbyte(chip, port + ICH_REG_OFF_CR, 0); 2663 while (!(igetbyte(chip, port + ichdev->roff_sr) & ICH_DCH)) 2664 ; 2665 } 2666 iputbyte(chip, port + ICH_REG_OFF_CR, ICH_RESETREGS); 2667 spin_unlock_irq(&chip->reg_lock); 2668 2669 t = stop_time.tv_sec - start_time.tv_sec; 2670 t *= 1000000; 2671 t += stop_time.tv_usec - start_time.tv_usec; 2672 printk(KERN_INFO "%s: measured %lu usecs\n", __func__, t); 2673 if (t == 0) { 2674 snd_printk(KERN_ERR "?? calculation error..\n"); 2675 return; 2676 } 2677 pos = (pos / 4) * 1000; 2678 pos = (pos / t) * 1000 + ((pos % t) * 1000) / t; 2679 if (pos < 40000 || pos >= 60000) 2680 /* abnormal value. hw problem? */ 2681 printk(KERN_INFO "intel8x0: measured clock %ld rejected\n", pos); 2682 else if (pos < 47500 || pos > 48500) 2683 /* not 48000Hz, tuning the clock.. */ 2684 chip->ac97_bus->clock = (chip->ac97_bus->clock * 48000) / pos; 2685 printk(KERN_INFO "intel8x0: clocking to %d\n", chip->ac97_bus->clock); 2686 snd_ac97_update_power(chip->ac97[0], AC97_PCM_FRONT_DAC_RATE, 0); 2687 } 2688 2689 #ifdef CONFIG_PROC_FS 2690 static void snd_intel8x0_proc_read(struct snd_info_entry * entry, 2691 struct snd_info_buffer *buffer) 2692 { 2693 struct intel8x0 *chip = entry->private_data; 2694 unsigned int tmp; 2695 2696 snd_iprintf(buffer, "Intel8x0\n\n"); 2697 if (chip->device_type == DEVICE_ALI) 2698 return; 2699 tmp = igetdword(chip, ICHREG(GLOB_STA)); 2700 snd_iprintf(buffer, "Global control : 0x%08x\n", igetdword(chip, ICHREG(GLOB_CNT))); 2701 snd_iprintf(buffer, "Global status : 0x%08x\n", tmp); 2702 if (chip->device_type == DEVICE_INTEL_ICH4) 2703 snd_iprintf(buffer, "SDM : 0x%08x\n", igetdword(chip, ICHREG(SDM))); 2704 snd_iprintf(buffer, "AC'97 codecs ready :"); 2705 if (tmp & chip->codec_isr_bits) { 2706 int i; 2707 static const char *codecs[3] = { 2708 "primary", "secondary", "tertiary" 2709 }; 2710 for (i = 0; i < chip->max_codecs; i++) 2711 if (tmp & chip->codec_bit[i]) 2712 snd_iprintf(buffer, " %s", codecs[i]); 2713 } else 2714 snd_iprintf(buffer, " none"); 2715 snd_iprintf(buffer, "\n"); 2716 if (chip->device_type == DEVICE_INTEL_ICH4 || 2717 chip->device_type == DEVICE_SIS) 2718 snd_iprintf(buffer, "AC'97 codecs SDIN : %i %i %i\n", 2719 chip->ac97_sdin[0], 2720 chip->ac97_sdin[1], 2721 chip->ac97_sdin[2]); 2722 } 2723 2724 static void __devinit snd_intel8x0_proc_init(struct intel8x0 * chip) 2725 { 2726 struct snd_info_entry *entry; 2727 2728 if (! snd_card_proc_new(chip->card, "intel8x0", &entry)) 2729 snd_info_set_text_ops(entry, chip, snd_intel8x0_proc_read); 2730 } 2731 #else 2732 #define snd_intel8x0_proc_init(x) 2733 #endif 2734 2735 static int snd_intel8x0_dev_free(struct snd_device *device) 2736 { 2737 struct intel8x0 *chip = device->device_data; 2738 return snd_intel8x0_free(chip); 2739 } 2740 2741 struct ich_reg_info { 2742 unsigned int int_sta_mask; 2743 unsigned int offset; 2744 }; 2745 2746 static unsigned int ich_codec_bits[3] = { 2747 ICH_PCR, ICH_SCR, ICH_TCR 2748 }; 2749 static unsigned int sis_codec_bits[3] = { 2750 ICH_PCR, ICH_SCR, ICH_SIS_TCR 2751 }; 2752 2753 static int __devinit snd_intel8x0_create(struct snd_card *card, 2754 struct pci_dev *pci, 2755 unsigned long device_type, 2756 struct intel8x0 ** r_intel8x0) 2757 { 2758 struct intel8x0 *chip; 2759 int err; 2760 unsigned int i; 2761 unsigned int int_sta_masks; 2762 struct ichdev *ichdev; 2763 static struct snd_device_ops ops = { 2764 .dev_free = snd_intel8x0_dev_free, 2765 }; 2766 2767 static unsigned int bdbars[] = { 2768 3, /* DEVICE_INTEL */ 2769 6, /* DEVICE_INTEL_ICH4 */ 2770 3, /* DEVICE_SIS */ 2771 6, /* DEVICE_ALI */ 2772 4, /* DEVICE_NFORCE */ 2773 }; 2774 static struct ich_reg_info intel_regs[6] = { 2775 { ICH_PIINT, 0 }, 2776 { ICH_POINT, 0x10 }, 2777 { ICH_MCINT, 0x20 }, 2778 { ICH_M2INT, 0x40 }, 2779 { ICH_P2INT, 0x50 }, 2780 { ICH_SPINT, 0x60 }, 2781 }; 2782 static struct ich_reg_info nforce_regs[4] = { 2783 { ICH_PIINT, 0 }, 2784 { ICH_POINT, 0x10 }, 2785 { ICH_MCINT, 0x20 }, 2786 { ICH_NVSPINT, 0x70 }, 2787 }; 2788 static struct ich_reg_info ali_regs[6] = { 2789 { ALI_INT_PCMIN, 0x40 }, 2790 { ALI_INT_PCMOUT, 0x50 }, 2791 { ALI_INT_MICIN, 0x60 }, 2792 { ALI_INT_CODECSPDIFOUT, 0x70 }, 2793 { ALI_INT_SPDIFIN, 0xa0 }, 2794 { ALI_INT_SPDIFOUT, 0xb0 }, 2795 }; 2796 struct ich_reg_info *tbl; 2797 2798 *r_intel8x0 = NULL; 2799 2800 if ((err = pci_enable_device(pci)) < 0) 2801 return err; 2802 2803 chip = kzalloc(sizeof(*chip), GFP_KERNEL); 2804 if (chip == NULL) { 2805 pci_disable_device(pci); 2806 return -ENOMEM; 2807 } 2808 spin_lock_init(&chip->reg_lock); 2809 chip->device_type = device_type; 2810 chip->card = card; 2811 chip->pci = pci; 2812 chip->irq = -1; 2813 2814 /* module parameters */ 2815 chip->buggy_irq = buggy_irq; 2816 chip->buggy_semaphore = buggy_semaphore; 2817 if (xbox) 2818 chip->xbox = 1; 2819 2820 if (pci->vendor == PCI_VENDOR_ID_INTEL && 2821 pci->device == PCI_DEVICE_ID_INTEL_440MX) 2822 chip->fix_nocache = 1; /* enable workaround */ 2823 2824 if ((err = pci_request_regions(pci, card->shortname)) < 0) { 2825 kfree(chip); 2826 pci_disable_device(pci); 2827 return err; 2828 } 2829 2830 if (device_type == DEVICE_ALI) { 2831 /* ALI5455 has no ac97 region */ 2832 chip->bmaddr = pci_iomap(pci, 0, 0); 2833 goto port_inited; 2834 } 2835 2836 if (pci_resource_flags(pci, 2) & IORESOURCE_MEM) /* ICH4 and Nforce */ 2837 chip->addr = pci_iomap(pci, 2, 0); 2838 else 2839 chip->addr = pci_iomap(pci, 0, 0); 2840 if (!chip->addr) { 2841 snd_printk(KERN_ERR "AC'97 space ioremap problem\n"); 2842 snd_intel8x0_free(chip); 2843 return -EIO; 2844 } 2845 if (pci_resource_flags(pci, 3) & IORESOURCE_MEM) /* ICH4 */ 2846 chip->bmaddr = pci_iomap(pci, 3, 0); 2847 else 2848 chip->bmaddr = pci_iomap(pci, 1, 0); 2849 if (!chip->bmaddr) { 2850 snd_printk(KERN_ERR "Controller space ioremap problem\n"); 2851 snd_intel8x0_free(chip); 2852 return -EIO; 2853 } 2854 2855 port_inited: 2856 chip->bdbars_count = bdbars[device_type]; 2857 2858 /* initialize offsets */ 2859 switch (device_type) { 2860 case DEVICE_NFORCE: 2861 tbl = nforce_regs; 2862 break; 2863 case DEVICE_ALI: 2864 tbl = ali_regs; 2865 break; 2866 default: 2867 tbl = intel_regs; 2868 break; 2869 } 2870 for (i = 0; i < chip->bdbars_count; i++) { 2871 ichdev = &chip->ichd[i]; 2872 ichdev->ichd = i; 2873 ichdev->reg_offset = tbl[i].offset; 2874 ichdev->int_sta_mask = tbl[i].int_sta_mask; 2875 if (device_type == DEVICE_SIS) { 2876 /* SiS 7012 swaps the registers */ 2877 ichdev->roff_sr = ICH_REG_OFF_PICB; 2878 ichdev->roff_picb = ICH_REG_OFF_SR; 2879 } else { 2880 ichdev->roff_sr = ICH_REG_OFF_SR; 2881 ichdev->roff_picb = ICH_REG_OFF_PICB; 2882 } 2883 if (device_type == DEVICE_ALI) 2884 ichdev->ali_slot = (ichdev->reg_offset - 0x40) / 0x10; 2885 /* SIS7012 handles the pcm data in bytes, others are in samples */ 2886 ichdev->pos_shift = (device_type == DEVICE_SIS) ? 0 : 1; 2887 } 2888 2889 /* allocate buffer descriptor lists */ 2890 /* the start of each lists must be aligned to 8 bytes */ 2891 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci), 2892 chip->bdbars_count * sizeof(u32) * ICH_MAX_FRAGS * 2, 2893 &chip->bdbars) < 0) { 2894 snd_intel8x0_free(chip); 2895 snd_printk(KERN_ERR "intel8x0: cannot allocate buffer descriptors\n"); 2896 return -ENOMEM; 2897 } 2898 /* tables must be aligned to 8 bytes here, but the kernel pages 2899 are much bigger, so we don't care (on i386) */ 2900 /* workaround for 440MX */ 2901 if (chip->fix_nocache) 2902 fill_nocache(chip->bdbars.area, chip->bdbars.bytes, 1); 2903 int_sta_masks = 0; 2904 for (i = 0; i < chip->bdbars_count; i++) { 2905 ichdev = &chip->ichd[i]; 2906 ichdev->bdbar = ((u32 *)chip->bdbars.area) + 2907 (i * ICH_MAX_FRAGS * 2); 2908 ichdev->bdbar_addr = chip->bdbars.addr + 2909 (i * sizeof(u32) * ICH_MAX_FRAGS * 2); 2910 int_sta_masks |= ichdev->int_sta_mask; 2911 } 2912 chip->int_sta_reg = device_type == DEVICE_ALI ? 2913 ICH_REG_ALI_INTERRUPTSR : ICH_REG_GLOB_STA; 2914 chip->int_sta_mask = int_sta_masks; 2915 2916 pci_set_master(pci); 2917 2918 switch(chip->device_type) { 2919 case DEVICE_INTEL_ICH4: 2920 /* ICH4 can have three codecs */ 2921 chip->max_codecs = 3; 2922 chip->codec_bit = ich_codec_bits; 2923 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_TRI; 2924 break; 2925 case DEVICE_SIS: 2926 /* recent SIS7012 can have three codecs */ 2927 chip->max_codecs = 3; 2928 chip->codec_bit = sis_codec_bits; 2929 chip->codec_ready_bits = ICH_PRI | ICH_SRI | ICH_SIS_TRI; 2930 break; 2931 default: 2932 /* others up to two codecs */ 2933 chip->max_codecs = 2; 2934 chip->codec_bit = ich_codec_bits; 2935 chip->codec_ready_bits = ICH_PRI | ICH_SRI; 2936 break; 2937 } 2938 for (i = 0; i < chip->max_codecs; i++) 2939 chip->codec_isr_bits |= chip->codec_bit[i]; 2940 2941 if ((err = snd_intel8x0_chip_init(chip, 1)) < 0) { 2942 snd_intel8x0_free(chip); 2943 return err; 2944 } 2945 2946 /* request irq after initializaing int_sta_mask, etc */ 2947 if (request_irq(pci->irq, snd_intel8x0_interrupt, 2948 IRQF_SHARED, card->shortname, chip)) { 2949 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq); 2950 snd_intel8x0_free(chip); 2951 return -EBUSY; 2952 } 2953 chip->irq = pci->irq; 2954 2955 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) { 2956 snd_intel8x0_free(chip); 2957 return err; 2958 } 2959 2960 snd_card_set_dev(card, &pci->dev); 2961 2962 *r_intel8x0 = chip; 2963 return 0; 2964 } 2965 2966 static struct shortname_table { 2967 unsigned int id; 2968 const char *s; 2969 } shortnames[] __devinitdata = { 2970 { PCI_DEVICE_ID_INTEL_82801AA_5, "Intel 82801AA-ICH" }, 2971 { PCI_DEVICE_ID_INTEL_82801AB_5, "Intel 82901AB-ICH0" }, 2972 { PCI_DEVICE_ID_INTEL_82801BA_4, "Intel 82801BA-ICH2" }, 2973 { PCI_DEVICE_ID_INTEL_440MX, "Intel 440MX" }, 2974 { PCI_DEVICE_ID_INTEL_82801CA_5, "Intel 82801CA-ICH3" }, 2975 { PCI_DEVICE_ID_INTEL_82801DB_5, "Intel 82801DB-ICH4" }, 2976 { PCI_DEVICE_ID_INTEL_82801EB_5, "Intel ICH5" }, 2977 { PCI_DEVICE_ID_INTEL_ESB_5, "Intel 6300ESB" }, 2978 { PCI_DEVICE_ID_INTEL_ICH6_18, "Intel ICH6" }, 2979 { PCI_DEVICE_ID_INTEL_ICH7_20, "Intel ICH7" }, 2980 { PCI_DEVICE_ID_INTEL_ESB2_14, "Intel ESB2" }, 2981 { PCI_DEVICE_ID_SI_7012, "SiS SI7012" }, 2982 { PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO, "NVidia nForce" }, 2983 { PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO, "NVidia nForce2" }, 2984 { PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO, "NVidia nForce3" }, 2985 { PCI_DEVICE_ID_NVIDIA_CK8S_AUDIO, "NVidia CK8S" }, 2986 { PCI_DEVICE_ID_NVIDIA_CK804_AUDIO, "NVidia CK804" }, 2987 { PCI_DEVICE_ID_NVIDIA_CK8_AUDIO, "NVidia CK8" }, 2988 { 0x003a, "NVidia MCP04" }, 2989 { 0x746d, "AMD AMD8111" }, 2990 { 0x7445, "AMD AMD768" }, 2991 { 0x5455, "ALi M5455" }, 2992 { 0, NULL }, 2993 }; 2994 2995 static struct snd_pci_quirk spdif_aclink_defaults[] __devinitdata = { 2996 SND_PCI_QUIRK(0x147b, 0x1c1a, "ASUS KN8", 1), 2997 { } /* end */ 2998 }; 2999 3000 /* look up white/black list for SPDIF over ac-link */ 3001 static int __devinit check_default_spdif_aclink(struct pci_dev *pci) 3002 { 3003 const struct snd_pci_quirk *w; 3004 3005 w = snd_pci_quirk_lookup(pci, spdif_aclink_defaults); 3006 if (w) { 3007 if (w->value) 3008 snd_printdd(KERN_INFO "intel8x0: Using SPDIF over " 3009 "AC-Link for %s\n", w->name); 3010 else 3011 snd_printdd(KERN_INFO "intel8x0: Using integrated " 3012 "SPDIF DMA for %s\n", w->name); 3013 return w->value; 3014 } 3015 return 0; 3016 } 3017 3018 static int __devinit snd_intel8x0_probe(struct pci_dev *pci, 3019 const struct pci_device_id *pci_id) 3020 { 3021 struct snd_card *card; 3022 struct intel8x0 *chip; 3023 int err; 3024 struct shortname_table *name; 3025 3026 card = snd_card_new(index, id, THIS_MODULE, 0); 3027 if (card == NULL) 3028 return -ENOMEM; 3029 3030 if (spdif_aclink < 0) 3031 spdif_aclink = check_default_spdif_aclink(pci); 3032 3033 strcpy(card->driver, "ICH"); 3034 if (!spdif_aclink) { 3035 switch (pci_id->driver_data) { 3036 case DEVICE_NFORCE: 3037 strcpy(card->driver, "NFORCE"); 3038 break; 3039 case DEVICE_INTEL_ICH4: 3040 strcpy(card->driver, "ICH4"); 3041 } 3042 } 3043 3044 strcpy(card->shortname, "Intel ICH"); 3045 for (name = shortnames; name->id; name++) { 3046 if (pci->device == name->id) { 3047 strcpy(card->shortname, name->s); 3048 break; 3049 } 3050 } 3051 3052 if (buggy_irq < 0) { 3053 /* some Nforce[2] and ICH boards have problems with IRQ handling. 3054 * Needs to return IRQ_HANDLED for unknown irqs. 3055 */ 3056 if (pci_id->driver_data == DEVICE_NFORCE) 3057 buggy_irq = 1; 3058 else 3059 buggy_irq = 0; 3060 } 3061 3062 if ((err = snd_intel8x0_create(card, pci, pci_id->driver_data, 3063 &chip)) < 0) { 3064 snd_card_free(card); 3065 return err; 3066 } 3067 card->private_data = chip; 3068 3069 if ((err = snd_intel8x0_mixer(chip, ac97_clock, ac97_quirk)) < 0) { 3070 snd_card_free(card); 3071 return err; 3072 } 3073 if ((err = snd_intel8x0_pcm(chip)) < 0) { 3074 snd_card_free(card); 3075 return err; 3076 } 3077 3078 snd_intel8x0_proc_init(chip); 3079 3080 snprintf(card->longname, sizeof(card->longname), 3081 "%s with %s at irq %i", card->shortname, 3082 snd_ac97_get_short_name(chip->ac97[0]), chip->irq); 3083 3084 if (! ac97_clock) 3085 intel8x0_measure_ac97_clock(chip); 3086 3087 if ((err = snd_card_register(card)) < 0) { 3088 snd_card_free(card); 3089 return err; 3090 } 3091 pci_set_drvdata(pci, card); 3092 return 0; 3093 } 3094 3095 static void __devexit snd_intel8x0_remove(struct pci_dev *pci) 3096 { 3097 snd_card_free(pci_get_drvdata(pci)); 3098 pci_set_drvdata(pci, NULL); 3099 } 3100 3101 static struct pci_driver driver = { 3102 .name = "Intel ICH", 3103 .id_table = snd_intel8x0_ids, 3104 .probe = snd_intel8x0_probe, 3105 .remove = __devexit_p(snd_intel8x0_remove), 3106 #ifdef CONFIG_PM 3107 .suspend = intel8x0_suspend, 3108 .resume = intel8x0_resume, 3109 #endif 3110 }; 3111 3112 3113 static int __init alsa_card_intel8x0_init(void) 3114 { 3115 return pci_register_driver(&driver); 3116 } 3117 3118 static void __exit alsa_card_intel8x0_exit(void) 3119 { 3120 pci_unregister_driver(&driver); 3121 } 3122 3123 module_init(alsa_card_intel8x0_init) 3124 module_exit(alsa_card_intel8x0_exit) 3125