1 #ifndef __SOUND_ICE1712_H 2 #define __SOUND_ICE1712_H 3 4 /* 5 * ALSA driver for ICEnsemble ICE1712 (Envy24) 6 * 7 * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 25 #include <linux/io.h> 26 #include <sound/control.h> 27 #include <sound/ac97_codec.h> 28 #include <sound/rawmidi.h> 29 #include <sound/i2c.h> 30 #include <sound/ak4xxx-adda.h> 31 #include <sound/ak4114.h> 32 #include <sound/pt2258.h> 33 #include <sound/pcm.h> 34 #include <sound/mpu401.h> 35 36 37 /* 38 * Direct registers 39 */ 40 41 #define ICEREG(ice, x) ((ice)->port + ICE1712_REG_##x) 42 43 #define ICE1712_REG_CONTROL 0x00 /* byte */ 44 #define ICE1712_RESET 0x80 /* soft reset whole chip */ 45 #define ICE1712_SERR_ASSERT_DS_DMA 0x40 /* disabled SERR# assertion for the DS DMA Ch-C irq otherwise enabled */ 46 #define ICE1712_DOS_VOL 0x10 /* DOS WT/FM volume control */ 47 #define ICE1712_SERR_LEVEL 0x08 /* SERR# level otherwise edge */ 48 #define ICE1712_SERR_ASSERT_SB 0x02 /* disabled SERR# assertion for SB irq otherwise enabled */ 49 #define ICE1712_NATIVE 0x01 /* native mode otherwise SB */ 50 #define ICE1712_REG_IRQMASK 0x01 /* byte */ 51 #define ICE1712_IRQ_MPU1 0x80 /* MIDI irq mask */ 52 #define ICE1712_IRQ_TIMER 0x40 /* Timer mask */ 53 #define ICE1712_IRQ_MPU2 0x20 /* Secondary MIDI irq mask */ 54 #define ICE1712_IRQ_PROPCM 0x10 /* professional multi-track */ 55 #define ICE1712_IRQ_FM 0x08 /* FM/MIDI - legacy */ 56 #define ICE1712_IRQ_PBKDS 0x04 /* playback DS channels */ 57 #define ICE1712_IRQ_CONCAP 0x02 /* consumer capture */ 58 #define ICE1712_IRQ_CONPBK 0x01 /* consumer playback */ 59 #define ICE1712_REG_IRQSTAT 0x02 /* byte */ 60 /* look to ICE1712_IRQ_* */ 61 #define ICE1712_REG_INDEX 0x03 /* byte - indirect CCIxx regs */ 62 #define ICE1712_REG_DATA 0x04 /* byte - indirect CCIxx regs */ 63 #define ICE1712_REG_NMI_STAT1 0x05 /* byte */ 64 #define ICE1712_REG_NMI_DATA 0x06 /* byte */ 65 #define ICE1712_REG_NMI_INDEX 0x07 /* byte */ 66 #define ICE1712_REG_AC97_INDEX 0x08 /* byte */ 67 #define ICE1712_REG_AC97_CMD 0x09 /* byte */ 68 #define ICE1712_AC97_COLD 0x80 /* cold reset */ 69 #define ICE1712_AC97_WARM 0x40 /* warm reset */ 70 #define ICE1712_AC97_WRITE 0x20 /* W: write, R: write in progress */ 71 #define ICE1712_AC97_READ 0x10 /* W: read, R: read in progress */ 72 #define ICE1712_AC97_READY 0x08 /* codec ready status bit */ 73 #define ICE1712_AC97_PBK_VSR 0x02 /* playback VSR */ 74 #define ICE1712_AC97_CAP_VSR 0x01 /* capture VSR */ 75 #define ICE1712_REG_AC97_DATA 0x0a /* word (little endian) */ 76 #define ICE1712_REG_MPU1_CTRL 0x0c /* byte */ 77 #define ICE1712_REG_MPU1_DATA 0x0d /* byte */ 78 #define ICE1712_REG_I2C_DEV_ADDR 0x10 /* byte */ 79 #define ICE1712_I2C_WRITE 0x01 /* write direction */ 80 #define ICE1712_REG_I2C_BYTE_ADDR 0x11 /* byte */ 81 #define ICE1712_REG_I2C_DATA 0x12 /* byte */ 82 #define ICE1712_REG_I2C_CTRL 0x13 /* byte */ 83 #define ICE1712_I2C_EEPROM 0x80 /* EEPROM exists */ 84 #define ICE1712_I2C_BUSY 0x01 /* busy bit */ 85 #define ICE1712_REG_CONCAP_ADDR 0x14 /* dword - consumer capture */ 86 #define ICE1712_REG_CONCAP_COUNT 0x18 /* word - current/base count */ 87 #define ICE1712_REG_SERR_SHADOW 0x1b /* byte */ 88 #define ICE1712_REG_MPU2_CTRL 0x1c /* byte */ 89 #define ICE1712_REG_MPU2_DATA 0x1d /* byte */ 90 #define ICE1712_REG_TIMER 0x1e /* word */ 91 92 /* 93 * Indirect registers 94 */ 95 96 #define ICE1712_IREG_PBK_COUNT_LO 0x00 97 #define ICE1712_IREG_PBK_COUNT_HI 0x01 98 #define ICE1712_IREG_PBK_CTRL 0x02 99 #define ICE1712_IREG_PBK_LEFT 0x03 /* left volume */ 100 #define ICE1712_IREG_PBK_RIGHT 0x04 /* right volume */ 101 #define ICE1712_IREG_PBK_SOFT 0x05 /* soft volume */ 102 #define ICE1712_IREG_PBK_RATE_LO 0x06 103 #define ICE1712_IREG_PBK_RATE_MID 0x07 104 #define ICE1712_IREG_PBK_RATE_HI 0x08 105 #define ICE1712_IREG_CAP_COUNT_LO 0x10 106 #define ICE1712_IREG_CAP_COUNT_HI 0x11 107 #define ICE1712_IREG_CAP_CTRL 0x12 108 #define ICE1712_IREG_GPIO_DATA 0x20 109 #define ICE1712_IREG_GPIO_WRITE_MASK 0x21 110 #define ICE1712_IREG_GPIO_DIRECTION 0x22 111 #define ICE1712_IREG_CONSUMER_POWERDOWN 0x30 112 #define ICE1712_IREG_PRO_POWERDOWN 0x31 113 114 /* 115 * Consumer section direct DMA registers 116 */ 117 118 #define ICEDS(ice, x) ((ice)->dmapath_port + ICE1712_DS_##x) 119 120 #define ICE1712_DS_INTMASK 0x00 /* word - interrupt mask */ 121 #define ICE1712_DS_INTSTAT 0x02 /* word - interrupt status */ 122 #define ICE1712_DS_DATA 0x04 /* dword - channel data */ 123 #define ICE1712_DS_INDEX 0x08 /* dword - channel index */ 124 125 /* 126 * Consumer section channel registers 127 */ 128 129 #define ICE1712_DSC_ADDR0 0x00 /* dword - base address 0 */ 130 #define ICE1712_DSC_COUNT0 0x01 /* word - count 0 */ 131 #define ICE1712_DSC_ADDR1 0x02 /* dword - base address 1 */ 132 #define ICE1712_DSC_COUNT1 0x03 /* word - count 1 */ 133 #define ICE1712_DSC_CONTROL 0x04 /* byte - control & status */ 134 #define ICE1712_BUFFER1 0x80 /* buffer1 is active */ 135 #define ICE1712_BUFFER1_AUTO 0x40 /* buffer1 auto init */ 136 #define ICE1712_BUFFER0_AUTO 0x20 /* buffer0 auto init */ 137 #define ICE1712_FLUSH 0x10 /* flush FIFO */ 138 #define ICE1712_STEREO 0x08 /* stereo */ 139 #define ICE1712_16BIT 0x04 /* 16-bit data */ 140 #define ICE1712_PAUSE 0x02 /* pause */ 141 #define ICE1712_START 0x01 /* start */ 142 #define ICE1712_DSC_RATE 0x05 /* dword - rate */ 143 #define ICE1712_DSC_VOLUME 0x06 /* word - volume control */ 144 145 /* 146 * Professional multi-track direct control registers 147 */ 148 149 #define ICEMT(ice, x) ((ice)->profi_port + ICE1712_MT_##x) 150 151 #define ICE1712_MT_IRQ 0x00 /* byte - interrupt mask */ 152 #define ICE1712_MULTI_CAPTURE 0x80 /* capture IRQ */ 153 #define ICE1712_MULTI_PLAYBACK 0x40 /* playback IRQ */ 154 #define ICE1712_MULTI_CAPSTATUS 0x02 /* capture IRQ status */ 155 #define ICE1712_MULTI_PBKSTATUS 0x01 /* playback IRQ status */ 156 #define ICE1712_MT_RATE 0x01 /* byte - sampling rate select */ 157 #define ICE1712_SPDIF_MASTER 0x10 /* S/PDIF input is master clock */ 158 #define ICE1712_MT_I2S_FORMAT 0x02 /* byte - I2S data format */ 159 #define ICE1712_MT_AC97_INDEX 0x04 /* byte - AC'97 index */ 160 #define ICE1712_MT_AC97_CMD 0x05 /* byte - AC'97 command & status */ 161 /* look to ICE1712_AC97_* */ 162 #define ICE1712_MT_AC97_DATA 0x06 /* word - AC'97 data */ 163 #define ICE1712_MT_PLAYBACK_ADDR 0x10 /* dword - playback address */ 164 #define ICE1712_MT_PLAYBACK_SIZE 0x14 /* word - playback size */ 165 #define ICE1712_MT_PLAYBACK_COUNT 0x16 /* word - playback count */ 166 #define ICE1712_MT_PLAYBACK_CONTROL 0x18 /* byte - control */ 167 #define ICE1712_CAPTURE_START_SHADOW 0x04 /* capture start */ 168 #define ICE1712_PLAYBACK_PAUSE 0x02 /* playback pause */ 169 #define ICE1712_PLAYBACK_START 0x01 /* playback start */ 170 #define ICE1712_MT_CAPTURE_ADDR 0x20 /* dword - capture address */ 171 #define ICE1712_MT_CAPTURE_SIZE 0x24 /* word - capture size */ 172 #define ICE1712_MT_CAPTURE_COUNT 0x26 /* word - capture count */ 173 #define ICE1712_MT_CAPTURE_CONTROL 0x28 /* byte - control */ 174 #define ICE1712_CAPTURE_START 0x01 /* capture start */ 175 #define ICE1712_MT_ROUTE_PSDOUT03 0x30 /* word */ 176 #define ICE1712_MT_ROUTE_SPDOUT 0x32 /* word */ 177 #define ICE1712_MT_ROUTE_CAPTURE 0x34 /* dword */ 178 #define ICE1712_MT_MONITOR_VOLUME 0x38 /* word */ 179 #define ICE1712_MT_MONITOR_INDEX 0x3a /* byte */ 180 #define ICE1712_MT_MONITOR_RATE 0x3b /* byte */ 181 #define ICE1712_MT_MONITOR_ROUTECTRL 0x3c /* byte */ 182 #define ICE1712_ROUTE_AC97 0x01 /* route digital mixer output to AC'97 */ 183 #define ICE1712_MT_MONITOR_PEAKINDEX 0x3e /* byte */ 184 #define ICE1712_MT_MONITOR_PEAKDATA 0x3f /* byte */ 185 186 /* 187 * Codec configuration bits 188 */ 189 190 /* PCI[60] System Configuration */ 191 #define ICE1712_CFG_CLOCK 0xc0 192 #define ICE1712_CFG_CLOCK512 0x00 /* 22.5692Mhz, 44.1kHz*512 */ 193 #define ICE1712_CFG_CLOCK384 0x40 /* 16.9344Mhz, 44.1kHz*384 */ 194 #define ICE1712_CFG_EXT 0x80 /* external clock */ 195 #define ICE1712_CFG_2xMPU401 0x20 /* two MPU401 UARTs */ 196 #define ICE1712_CFG_NO_CON_AC97 0x10 /* consumer AC'97 codec is not present */ 197 #define ICE1712_CFG_ADC_MASK 0x0c /* one, two, three, four stereo ADCs */ 198 #define ICE1712_CFG_DAC_MASK 0x03 /* one, two, three, four stereo DACs */ 199 /* PCI[61] AC-Link Configuration */ 200 #define ICE1712_CFG_PRO_I2S 0x80 /* multitrack converter: I2S or AC'97 */ 201 #define ICE1712_CFG_AC97_PACKED 0x01 /* split or packed mode - AC'97 */ 202 /* PCI[62] I2S Features */ 203 #define ICE1712_CFG_I2S_VOLUME 0x80 /* volume/mute capability */ 204 #define ICE1712_CFG_I2S_96KHZ 0x40 /* supports 96kHz sampling */ 205 #define ICE1712_CFG_I2S_RESMASK 0x30 /* resolution mask, 16,18,20,24-bit */ 206 #define ICE1712_CFG_I2S_OTHER 0x0f /* other I2S IDs */ 207 /* PCI[63] S/PDIF Configuration */ 208 #define ICE1712_CFG_I2S_CHIPID 0xfc /* I2S chip ID */ 209 #define ICE1712_CFG_SPDIF_IN 0x02 /* S/PDIF input is present */ 210 #define ICE1712_CFG_SPDIF_OUT 0x01 /* S/PDIF output is present */ 211 212 /* 213 * DMA mode values 214 * identical with DMA_XXX on i386 architecture. 215 */ 216 #define ICE1712_DMA_MODE_WRITE 0x48 217 #define ICE1712_DMA_AUTOINIT 0x10 218 219 220 /* 221 * 222 */ 223 224 struct snd_ice1712; 225 226 struct snd_ice1712_eeprom { 227 unsigned int subvendor; /* PCI[2c-2f] */ 228 unsigned char size; /* size of EEPROM image in bytes */ 229 unsigned char version; /* must be 1 (or 2 for vt1724) */ 230 unsigned char data[32]; 231 unsigned int gpiomask; 232 unsigned int gpiostate; 233 unsigned int gpiodir; 234 }; 235 236 enum { 237 ICE_EEP1_CODEC = 0, /* 06 */ 238 ICE_EEP1_ACLINK, /* 07 */ 239 ICE_EEP1_I2SID, /* 08 */ 240 ICE_EEP1_SPDIF, /* 09 */ 241 ICE_EEP1_GPIO_MASK, /* 0a */ 242 ICE_EEP1_GPIO_STATE, /* 0b */ 243 ICE_EEP1_GPIO_DIR, /* 0c */ 244 ICE_EEP1_AC97_MAIN_LO, /* 0d */ 245 ICE_EEP1_AC97_MAIN_HI, /* 0e */ 246 ICE_EEP1_AC97_PCM_LO, /* 0f */ 247 ICE_EEP1_AC97_PCM_HI, /* 10 */ 248 ICE_EEP1_AC97_REC_LO, /* 11 */ 249 ICE_EEP1_AC97_REC_HI, /* 12 */ 250 ICE_EEP1_AC97_RECSRC, /* 13 */ 251 ICE_EEP1_DAC_ID, /* 14 */ 252 ICE_EEP1_DAC_ID1, 253 ICE_EEP1_DAC_ID2, 254 ICE_EEP1_DAC_ID3, 255 ICE_EEP1_ADC_ID, /* 18 */ 256 ICE_EEP1_ADC_ID1, 257 ICE_EEP1_ADC_ID2, 258 ICE_EEP1_ADC_ID3 259 }; 260 261 #define ice_has_con_ac97(ice) (!((ice)->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) 262 263 264 struct snd_ak4xxx_private { 265 unsigned int cif:1; /* CIF mode */ 266 unsigned char caddr; /* C0 and C1 bits */ 267 unsigned int data_mask; /* DATA gpio bit */ 268 unsigned int clk_mask; /* CLK gpio bit */ 269 unsigned int cs_mask; /* bit mask for select/deselect address */ 270 unsigned int cs_addr; /* bits to select address */ 271 unsigned int cs_none; /* bits to deselect address */ 272 unsigned int add_flags; /* additional bits at init */ 273 unsigned int mask_flags; /* total mask bits */ 274 struct snd_akm4xxx_ops { 275 void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate); 276 } ops; 277 }; 278 279 struct snd_ice1712_spdif { 280 unsigned char cs8403_bits; 281 unsigned char cs8403_stream_bits; 282 struct snd_kcontrol *stream_ctl; 283 284 struct snd_ice1712_spdif_ops { 285 void (*open)(struct snd_ice1712 *, struct snd_pcm_substream *); 286 void (*setup_rate)(struct snd_ice1712 *, int rate); 287 void (*close)(struct snd_ice1712 *, struct snd_pcm_substream *); 288 void (*default_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); 289 int (*default_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); 290 void (*stream_get)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); 291 int (*stream_put)(struct snd_ice1712 *, struct snd_ctl_elem_value *ucontrol); 292 } ops; 293 }; 294 295 struct snd_ice1712_card_info; 296 297 struct snd_ice1712 { 298 unsigned long conp_dma_size; 299 unsigned long conc_dma_size; 300 unsigned long prop_dma_size; 301 unsigned long proc_dma_size; 302 int irq; 303 304 unsigned long port; 305 unsigned long ddma_port; 306 unsigned long dmapath_port; 307 unsigned long profi_port; 308 309 struct pci_dev *pci; 310 struct snd_card *card; 311 struct snd_pcm *pcm; 312 struct snd_pcm *pcm_ds; 313 struct snd_pcm *pcm_pro; 314 struct snd_pcm_substream *playback_con_substream; 315 struct snd_pcm_substream *playback_con_substream_ds[6]; 316 struct snd_pcm_substream *capture_con_substream; 317 struct snd_pcm_substream *playback_pro_substream; 318 struct snd_pcm_substream *capture_pro_substream; 319 unsigned int playback_pro_size; 320 unsigned int capture_pro_size; 321 unsigned int playback_con_virt_addr[6]; 322 unsigned int playback_con_active_buf[6]; 323 unsigned int capture_con_virt_addr; 324 unsigned int ac97_ext_id; 325 struct snd_ac97 *ac97; 326 struct snd_rawmidi *rmidi[2]; 327 328 spinlock_t reg_lock; 329 struct snd_info_entry *proc_entry; 330 331 struct snd_ice1712_eeprom eeprom; 332 struct snd_ice1712_card_info *card_info; 333 334 unsigned int pro_volumes[20]; 335 unsigned int omni:1; /* Delta Omni I/O */ 336 unsigned int dxr_enable:1; /* Terratec DXR enable for DMX6FIRE */ 337 unsigned int vt1724:1; 338 unsigned int vt1720:1; 339 unsigned int has_spdif:1; /* VT1720/4 - has SPDIF I/O */ 340 unsigned int force_pdma4:1; /* VT1720/4 - PDMA4 as non-spdif */ 341 unsigned int force_rdma1:1; /* VT1720/4 - RDMA1 as non-spdif */ 342 unsigned int midi_output:1; /* VT1720/4: MIDI output triggered */ 343 unsigned int midi_input:1; /* VT1720/4: MIDI input triggered */ 344 unsigned int own_routing:1; /* VT1720/4: use own routing ctls */ 345 unsigned int num_total_dacs; /* total DACs */ 346 unsigned int num_total_adcs; /* total ADCs */ 347 unsigned int cur_rate; /* current rate */ 348 349 struct mutex open_mutex; 350 struct snd_pcm_substream *pcm_reserved[4]; 351 struct snd_pcm_hw_constraint_list *hw_rates; /* card-specific rate constraints */ 352 353 unsigned int akm_codecs; 354 struct snd_akm4xxx *akm; 355 struct snd_ice1712_spdif spdif; 356 357 struct mutex i2c_mutex; /* I2C mutex for ICE1724 registers */ 358 struct snd_i2c_bus *i2c; /* I2C bus */ 359 struct snd_i2c_device *cs8427; /* CS8427 I2C device */ 360 unsigned int cs8427_timeout; /* CS8427 reset timeout in HZ/100 */ 361 362 struct ice1712_gpio { 363 unsigned int direction; /* current direction bits */ 364 unsigned int write_mask; /* current mask bits */ 365 unsigned int saved[2]; /* for ewx_i2c */ 366 /* operators */ 367 void (*set_mask)(struct snd_ice1712 *ice, unsigned int data); 368 unsigned int (*get_mask)(struct snd_ice1712 *ice); 369 void (*set_dir)(struct snd_ice1712 *ice, unsigned int data); 370 unsigned int (*get_dir)(struct snd_ice1712 *ice); 371 void (*set_data)(struct snd_ice1712 *ice, unsigned int data); 372 unsigned int (*get_data)(struct snd_ice1712 *ice); 373 /* misc operators - move to another place? */ 374 void (*set_pro_rate)(struct snd_ice1712 *ice, unsigned int rate); 375 void (*i2s_mclk_changed)(struct snd_ice1712 *ice); 376 } gpio; 377 struct mutex gpio_mutex; 378 379 /* other board-specific data */ 380 void *spec; 381 382 /* VT172x specific */ 383 int pro_rate_default; 384 int (*is_spdif_master)(struct snd_ice1712 *ice); 385 unsigned int (*get_rate)(struct snd_ice1712 *ice); 386 void (*set_rate)(struct snd_ice1712 *ice, unsigned int rate); 387 unsigned char (*set_mclk)(struct snd_ice1712 *ice, unsigned int rate); 388 int (*set_spdif_clock)(struct snd_ice1712 *ice, int type); 389 int (*get_spdif_master_type)(struct snd_ice1712 *ice); 390 const char * const *ext_clock_names; 391 int ext_clock_count; 392 void (*pro_open)(struct snd_ice1712 *, struct snd_pcm_substream *); 393 #ifdef CONFIG_PM_SLEEP 394 int (*pm_suspend)(struct snd_ice1712 *); 395 int (*pm_resume)(struct snd_ice1712 *); 396 unsigned int pm_suspend_enabled:1; 397 unsigned int pm_saved_is_spdif_master:1; 398 unsigned int pm_saved_spdif_ctrl; 399 unsigned char pm_saved_spdif_cfg; 400 unsigned int pm_saved_route; 401 #endif 402 }; 403 404 405 /* 406 * gpio access functions 407 */ 408 static inline void snd_ice1712_gpio_set_dir(struct snd_ice1712 *ice, unsigned int bits) 409 { 410 ice->gpio.set_dir(ice, bits); 411 } 412 413 static inline unsigned int snd_ice1712_gpio_get_dir(struct snd_ice1712 *ice) 414 { 415 return ice->gpio.get_dir(ice); 416 } 417 418 static inline void snd_ice1712_gpio_set_mask(struct snd_ice1712 *ice, unsigned int bits) 419 { 420 ice->gpio.set_mask(ice, bits); 421 } 422 423 static inline void snd_ice1712_gpio_write(struct snd_ice1712 *ice, unsigned int val) 424 { 425 ice->gpio.set_data(ice, val); 426 } 427 428 static inline unsigned int snd_ice1712_gpio_read(struct snd_ice1712 *ice) 429 { 430 return ice->gpio.get_data(ice); 431 } 432 433 /* 434 * save and restore gpio status 435 * The access to gpio will be protected by mutex, so don't forget to 436 * restore! 437 */ 438 static inline void snd_ice1712_save_gpio_status(struct snd_ice1712 *ice) 439 { 440 mutex_lock(&ice->gpio_mutex); 441 ice->gpio.saved[0] = ice->gpio.direction; 442 ice->gpio.saved[1] = ice->gpio.write_mask; 443 } 444 445 static inline void snd_ice1712_restore_gpio_status(struct snd_ice1712 *ice) 446 { 447 ice->gpio.set_dir(ice, ice->gpio.saved[0]); 448 ice->gpio.set_mask(ice, ice->gpio.saved[1]); 449 ice->gpio.direction = ice->gpio.saved[0]; 450 ice->gpio.write_mask = ice->gpio.saved[1]; 451 mutex_unlock(&ice->gpio_mutex); 452 } 453 454 /* for bit controls */ 455 #define ICE1712_GPIO(xiface, xname, xindex, mask, invert, xaccess) \ 456 { .iface = xiface, .name = xname, .access = xaccess, .info = snd_ctl_boolean_mono_info, \ 457 .get = snd_ice1712_gpio_get, .put = snd_ice1712_gpio_put, \ 458 .private_value = mask | (invert << 24) } 459 460 int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); 461 int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol); 462 463 /* 464 * set gpio direction, write mask and data 465 */ 466 static inline void snd_ice1712_gpio_write_bits(struct snd_ice1712 *ice, 467 unsigned int mask, unsigned int bits) 468 { 469 unsigned val; 470 471 ice->gpio.direction |= mask; 472 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction); 473 val = snd_ice1712_gpio_read(ice); 474 val &= ~mask; 475 val |= mask & bits; 476 snd_ice1712_gpio_write(ice, val); 477 } 478 479 static inline int snd_ice1712_gpio_read_bits(struct snd_ice1712 *ice, 480 unsigned int mask) 481 { 482 ice->gpio.direction &= ~mask; 483 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction); 484 return snd_ice1712_gpio_read(ice) & mask; 485 } 486 487 /* route access functions */ 488 int snd_ice1724_get_route_val(struct snd_ice1712 *ice, int shift); 489 int snd_ice1724_put_route_val(struct snd_ice1712 *ice, unsigned int val, 490 int shift); 491 492 int snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice); 493 494 int snd_ice1712_akm4xxx_init(struct snd_akm4xxx *ak, 495 const struct snd_akm4xxx *template, 496 const struct snd_ak4xxx_private *priv, 497 struct snd_ice1712 *ice); 498 void snd_ice1712_akm4xxx_free(struct snd_ice1712 *ice); 499 int snd_ice1712_akm4xxx_build_controls(struct snd_ice1712 *ice); 500 501 int snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr); 502 503 static inline void snd_ice1712_write(struct snd_ice1712 *ice, u8 addr, u8 data) 504 { 505 outb(addr, ICEREG(ice, INDEX)); 506 outb(data, ICEREG(ice, DATA)); 507 } 508 509 static inline u8 snd_ice1712_read(struct snd_ice1712 *ice, u8 addr) 510 { 511 outb(addr, ICEREG(ice, INDEX)); 512 return inb(ICEREG(ice, DATA)); 513 } 514 515 516 /* 517 * entry pointer 518 */ 519 520 struct snd_ice1712_card_info { 521 unsigned int subvendor; 522 const char *name; 523 const char *model; 524 const char *driver; 525 int (*chip_init)(struct snd_ice1712 *); 526 void (*chip_exit)(struct snd_ice1712 *); 527 int (*build_controls)(struct snd_ice1712 *); 528 unsigned int no_mpu401:1; 529 unsigned int mpu401_1_info_flags; 530 unsigned int mpu401_2_info_flags; 531 const char *mpu401_1_name; 532 const char *mpu401_2_name; 533 const unsigned int eeprom_size; 534 const unsigned char *eeprom_data; 535 }; 536 537 538 #endif /* __SOUND_ICE1712_H */ 539