1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs 5 * 6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved. 7 * Copyright (c) 2006 ATI Technologies Inc. 8 * Copyright (c) 2008 NVIDIA Corp. All rights reserved. 9 * Copyright (c) 2008 Wei Ni <wni@nvidia.com> 10 * Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi> 11 * 12 * Authors: 13 * Wu Fengguang <wfg@linux.intel.com> 14 * 15 * Maintained by: 16 * Wu Fengguang <wfg@linux.intel.com> 17 */ 18 19 #include <linux/init.h> 20 #include <linux/delay.h> 21 #include <linux/pci.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pm_runtime.h> 25 #include <sound/core.h> 26 #include <sound/jack.h> 27 #include <sound/asoundef.h> 28 #include <sound/tlv.h> 29 #include <sound/hdaudio.h> 30 #include <sound/hda_i915.h> 31 #include <sound/hda_chmap.h> 32 #include <sound/hda_codec.h> 33 #include "hda_local.h" 34 #include "hda_jack.h" 35 #include "hda_controller.h" 36 37 static bool static_hdmi_pcm; 38 module_param(static_hdmi_pcm, bool, 0644); 39 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info"); 40 41 static bool enable_acomp = true; 42 module_param(enable_acomp, bool, 0444); 43 MODULE_PARM_DESC(enable_acomp, "Enable audio component binding (default=yes)"); 44 45 static bool enable_silent_stream = 46 IS_ENABLED(CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM); 47 module_param(enable_silent_stream, bool, 0644); 48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices"); 49 50 static bool enable_all_pins; 51 module_param(enable_all_pins, bool, 0444); 52 MODULE_PARM_DESC(enable_all_pins, "Forcibly enable all pins"); 53 54 struct hdmi_spec_per_cvt { 55 hda_nid_t cvt_nid; 56 bool assigned; /* the stream has been assigned */ 57 bool silent_stream; /* silent stream activated */ 58 unsigned int channels_min; 59 unsigned int channels_max; 60 u32 rates; 61 u64 formats; 62 unsigned int maxbps; 63 }; 64 65 /* max. connections to a widget */ 66 #define HDA_MAX_CONNECTIONS 32 67 68 struct hdmi_spec_per_pin { 69 hda_nid_t pin_nid; 70 int dev_id; 71 /* pin idx, different device entries on the same pin use the same idx */ 72 int pin_nid_idx; 73 int num_mux_nids; 74 hda_nid_t mux_nids[HDA_MAX_CONNECTIONS]; 75 int mux_idx; 76 hda_nid_t cvt_nid; 77 78 struct hda_codec *codec; 79 struct hdmi_eld sink_eld; 80 struct mutex lock; 81 struct delayed_work work; 82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/ 83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */ 84 int repoll_count; 85 bool setup; /* the stream has been set up by prepare callback */ 86 bool silent_stream; 87 int channels; /* current number of channels */ 88 bool non_pcm; 89 bool chmap_set; /* channel-map override by ALSA API? */ 90 unsigned char chmap[8]; /* ALSA API channel-map */ 91 #ifdef CONFIG_SND_PROC_FS 92 struct snd_info_entry *proc_entry; 93 #endif 94 }; 95 96 /* operations used by generic code that can be overridden by patches */ 97 struct hdmi_ops { 98 int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid, 99 int dev_id, unsigned char *buf, int *eld_size); 100 101 void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid, 102 int dev_id, 103 int ca, int active_channels, int conn_type); 104 105 /* enable/disable HBR (HD passthrough) */ 106 int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, 107 int dev_id, bool hbr); 108 109 int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid, 110 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 111 int format); 112 113 void (*pin_cvt_fixup)(struct hda_codec *codec, 114 struct hdmi_spec_per_pin *per_pin, 115 hda_nid_t cvt_nid); 116 }; 117 118 struct hdmi_pcm { 119 struct hda_pcm *pcm; 120 struct snd_jack *jack; 121 struct snd_kcontrol *eld_ctl; 122 }; 123 124 enum { 125 SILENT_STREAM_OFF = 0, 126 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */ 127 SILENT_STREAM_I915, /* Intel i915 extension */ 128 }; 129 130 struct hdmi_spec { 131 struct hda_codec *codec; 132 int num_cvts; 133 struct snd_array cvts; /* struct hdmi_spec_per_cvt */ 134 hda_nid_t cvt_nids[4]; /* only for haswell fix */ 135 136 /* 137 * num_pins is the number of virtual pins 138 * for example, there are 3 pins, and each pin 139 * has 4 device entries, then the num_pins is 12 140 */ 141 int num_pins; 142 /* 143 * num_nids is the number of real pins 144 * In the above example, num_nids is 3 145 */ 146 int num_nids; 147 /* 148 * dev_num is the number of device entries 149 * on each pin. 150 * In the above example, dev_num is 4 151 */ 152 int dev_num; 153 struct snd_array pins; /* struct hdmi_spec_per_pin */ 154 struct hdmi_pcm pcm_rec[8]; 155 struct mutex pcm_lock; 156 struct mutex bind_lock; /* for audio component binding */ 157 /* pcm_bitmap means which pcms have been assigned to pins*/ 158 unsigned long pcm_bitmap; 159 int pcm_used; /* counter of pcm_rec[] */ 160 /* bitmap shows whether the pcm is opened in user space 161 * bit 0 means the first playback PCM (PCM3); 162 * bit 1 means the second playback PCM, and so on. 163 */ 164 unsigned long pcm_in_use; 165 166 struct hdmi_eld temp_eld; 167 struct hdmi_ops ops; 168 169 bool dyn_pin_out; 170 /* hdmi interrupt trigger control flag for Nvidia codec */ 171 bool hdmi_intr_trig_ctrl; 172 bool nv_dp_workaround; /* workaround DP audio infoframe for Nvidia */ 173 174 bool intel_hsw_fixup; /* apply Intel platform-specific fixups */ 175 /* 176 * Non-generic VIA/NVIDIA specific 177 */ 178 struct hda_multi_out multiout; 179 struct hda_pcm_stream pcm_playback; 180 181 bool use_acomp_notifier; /* use eld_notify callback for hotplug */ 182 bool acomp_registered; /* audio component registered in this driver */ 183 bool force_connect; /* force connectivity */ 184 struct drm_audio_component_audio_ops drm_audio_ops; 185 int (*port2pin)(struct hda_codec *, int); /* reverse port/pin mapping */ 186 187 struct hdac_chmap chmap; 188 hda_nid_t vendor_nid; 189 const int *port_map; 190 int port_num; 191 int silent_stream_type; 192 }; 193 194 #ifdef CONFIG_SND_HDA_COMPONENT 195 static inline bool codec_has_acomp(struct hda_codec *codec) 196 { 197 struct hdmi_spec *spec = codec->spec; 198 return spec->use_acomp_notifier; 199 } 200 #else 201 #define codec_has_acomp(codec) false 202 #endif 203 204 struct hdmi_audio_infoframe { 205 u8 type; /* 0x84 */ 206 u8 ver; /* 0x01 */ 207 u8 len; /* 0x0a */ 208 209 u8 checksum; 210 211 u8 CC02_CT47; /* CC in bits 0:2, CT in 4:7 */ 212 u8 SS01_SF24; 213 u8 CXT04; 214 u8 CA; 215 u8 LFEPBL01_LSV36_DM_INH7; 216 }; 217 218 struct dp_audio_infoframe { 219 u8 type; /* 0x84 */ 220 u8 len; /* 0x1b */ 221 u8 ver; /* 0x11 << 2 */ 222 223 u8 CC02_CT47; /* match with HDMI infoframe from this on */ 224 u8 SS01_SF24; 225 u8 CXT04; 226 u8 CA; 227 u8 LFEPBL01_LSV36_DM_INH7; 228 }; 229 230 union audio_infoframe { 231 struct hdmi_audio_infoframe hdmi; 232 struct dp_audio_infoframe dp; 233 DECLARE_FLEX_ARRAY(u8, bytes); 234 }; 235 236 /* 237 * HDMI routines 238 */ 239 240 #define get_pin(spec, idx) \ 241 ((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx)) 242 #define get_cvt(spec, idx) \ 243 ((struct hdmi_spec_per_cvt *)snd_array_elem(&spec->cvts, idx)) 244 /* obtain hdmi_pcm object assigned to idx */ 245 #define get_hdmi_pcm(spec, idx) (&(spec)->pcm_rec[idx]) 246 /* obtain hda_pcm object assigned to idx */ 247 #define get_pcm_rec(spec, idx) (get_hdmi_pcm(spec, idx)->pcm) 248 249 static int pin_id_to_pin_index(struct hda_codec *codec, 250 hda_nid_t pin_nid, int dev_id) 251 { 252 struct hdmi_spec *spec = codec->spec; 253 int pin_idx; 254 struct hdmi_spec_per_pin *per_pin; 255 256 /* 257 * (dev_id == -1) means it is NON-MST pin 258 * return the first virtual pin on this port 259 */ 260 if (dev_id == -1) 261 dev_id = 0; 262 263 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 264 per_pin = get_pin(spec, pin_idx); 265 if ((per_pin->pin_nid == pin_nid) && 266 (per_pin->dev_id == dev_id)) 267 return pin_idx; 268 } 269 270 codec_warn(codec, "HDMI: pin NID 0x%x not registered\n", pin_nid); 271 return -EINVAL; 272 } 273 274 static int hinfo_to_pcm_index(struct hda_codec *codec, 275 struct hda_pcm_stream *hinfo) 276 { 277 struct hdmi_spec *spec = codec->spec; 278 int pcm_idx; 279 280 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) 281 if (get_pcm_rec(spec, pcm_idx)->stream == hinfo) 282 return pcm_idx; 283 284 codec_warn(codec, "HDMI: hinfo %p not tied to a PCM\n", hinfo); 285 return -EINVAL; 286 } 287 288 static int hinfo_to_pin_index(struct hda_codec *codec, 289 struct hda_pcm_stream *hinfo) 290 { 291 struct hdmi_spec *spec = codec->spec; 292 struct hdmi_spec_per_pin *per_pin; 293 int pin_idx; 294 295 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 296 per_pin = get_pin(spec, pin_idx); 297 if (per_pin->pcm && 298 per_pin->pcm->pcm->stream == hinfo) 299 return pin_idx; 300 } 301 302 codec_dbg(codec, "HDMI: hinfo %p (pcm %d) not registered\n", hinfo, 303 hinfo_to_pcm_index(codec, hinfo)); 304 return -EINVAL; 305 } 306 307 static struct hdmi_spec_per_pin *pcm_idx_to_pin(struct hdmi_spec *spec, 308 int pcm_idx) 309 { 310 int i; 311 struct hdmi_spec_per_pin *per_pin; 312 313 for (i = 0; i < spec->num_pins; i++) { 314 per_pin = get_pin(spec, i); 315 if (per_pin->pcm_idx == pcm_idx) 316 return per_pin; 317 } 318 return NULL; 319 } 320 321 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid) 322 { 323 struct hdmi_spec *spec = codec->spec; 324 int cvt_idx; 325 326 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) 327 if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid) 328 return cvt_idx; 329 330 codec_warn(codec, "HDMI: cvt NID 0x%x not registered\n", cvt_nid); 331 return -EINVAL; 332 } 333 334 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol, 335 struct snd_ctl_elem_info *uinfo) 336 { 337 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 338 struct hdmi_spec *spec = codec->spec; 339 struct hdmi_spec_per_pin *per_pin; 340 struct hdmi_eld *eld; 341 int pcm_idx; 342 343 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 344 345 pcm_idx = kcontrol->private_value; 346 mutex_lock(&spec->pcm_lock); 347 per_pin = pcm_idx_to_pin(spec, pcm_idx); 348 if (!per_pin) { 349 /* no pin is bound to the pcm */ 350 uinfo->count = 0; 351 goto unlock; 352 } 353 eld = &per_pin->sink_eld; 354 uinfo->count = eld->eld_valid ? eld->eld_size : 0; 355 356 unlock: 357 mutex_unlock(&spec->pcm_lock); 358 return 0; 359 } 360 361 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol, 362 struct snd_ctl_elem_value *ucontrol) 363 { 364 struct hda_codec *codec = snd_kcontrol_chip(kcontrol); 365 struct hdmi_spec *spec = codec->spec; 366 struct hdmi_spec_per_pin *per_pin; 367 struct hdmi_eld *eld; 368 int pcm_idx; 369 int err = 0; 370 371 pcm_idx = kcontrol->private_value; 372 mutex_lock(&spec->pcm_lock); 373 per_pin = pcm_idx_to_pin(spec, pcm_idx); 374 if (!per_pin) { 375 /* no pin is bound to the pcm */ 376 memset(ucontrol->value.bytes.data, 0, 377 ARRAY_SIZE(ucontrol->value.bytes.data)); 378 goto unlock; 379 } 380 381 eld = &per_pin->sink_eld; 382 if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data) || 383 eld->eld_size > ELD_MAX_SIZE) { 384 snd_BUG(); 385 err = -EINVAL; 386 goto unlock; 387 } 388 389 memset(ucontrol->value.bytes.data, 0, 390 ARRAY_SIZE(ucontrol->value.bytes.data)); 391 if (eld->eld_valid) 392 memcpy(ucontrol->value.bytes.data, eld->eld_buffer, 393 eld->eld_size); 394 395 unlock: 396 mutex_unlock(&spec->pcm_lock); 397 return err; 398 } 399 400 static const struct snd_kcontrol_new eld_bytes_ctl = { 401 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE | 402 SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK, 403 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 404 .name = "ELD", 405 .info = hdmi_eld_ctl_info, 406 .get = hdmi_eld_ctl_get, 407 }; 408 409 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pcm_idx, 410 int device) 411 { 412 struct snd_kcontrol *kctl; 413 struct hdmi_spec *spec = codec->spec; 414 int err; 415 416 kctl = snd_ctl_new1(&eld_bytes_ctl, codec); 417 if (!kctl) 418 return -ENOMEM; 419 kctl->private_value = pcm_idx; 420 kctl->id.device = device; 421 422 /* no pin nid is associated with the kctl now 423 * tbd: associate pin nid to eld ctl later 424 */ 425 err = snd_hda_ctl_add(codec, 0, kctl); 426 if (err < 0) 427 return err; 428 429 get_hdmi_pcm(spec, pcm_idx)->eld_ctl = kctl; 430 return 0; 431 } 432 433 #ifdef BE_PARANOID 434 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 435 int *packet_index, int *byte_index) 436 { 437 int val; 438 439 val = snd_hda_codec_read(codec, pin_nid, 0, 440 AC_VERB_GET_HDMI_DIP_INDEX, 0); 441 442 *packet_index = val >> 5; 443 *byte_index = val & 0x1f; 444 } 445 #endif 446 447 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid, 448 int packet_index, int byte_index) 449 { 450 int val; 451 452 val = (packet_index << 5) | (byte_index & 0x1f); 453 454 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val); 455 } 456 457 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid, 458 unsigned char val) 459 { 460 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val); 461 } 462 463 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid) 464 { 465 struct hdmi_spec *spec = codec->spec; 466 int pin_out; 467 468 /* Unmute */ 469 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 470 snd_hda_codec_write(codec, pin_nid, 0, 471 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE); 472 473 if (spec->dyn_pin_out) 474 /* Disable pin out until stream is active */ 475 pin_out = 0; 476 else 477 /* Enable pin out: some machines with GM965 gets broken output 478 * when the pin is disabled or changed while using with HDMI 479 */ 480 pin_out = PIN_OUT; 481 482 snd_hda_codec_write(codec, pin_nid, 0, 483 AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out); 484 } 485 486 /* 487 * ELD proc files 488 */ 489 490 #ifdef CONFIG_SND_PROC_FS 491 static void print_eld_info(struct snd_info_entry *entry, 492 struct snd_info_buffer *buffer) 493 { 494 struct hdmi_spec_per_pin *per_pin = entry->private_data; 495 496 mutex_lock(&per_pin->lock); 497 snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer, per_pin->pin_nid, 498 per_pin->dev_id, per_pin->cvt_nid); 499 mutex_unlock(&per_pin->lock); 500 } 501 502 static void write_eld_info(struct snd_info_entry *entry, 503 struct snd_info_buffer *buffer) 504 { 505 struct hdmi_spec_per_pin *per_pin = entry->private_data; 506 507 mutex_lock(&per_pin->lock); 508 snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer); 509 mutex_unlock(&per_pin->lock); 510 } 511 512 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index) 513 { 514 char name[32]; 515 struct hda_codec *codec = per_pin->codec; 516 struct snd_info_entry *entry; 517 int err; 518 519 snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index); 520 err = snd_card_proc_new(codec->card, name, &entry); 521 if (err < 0) 522 return err; 523 524 snd_info_set_text_ops(entry, per_pin, print_eld_info); 525 entry->c.text.write = write_eld_info; 526 entry->mode |= 0200; 527 per_pin->proc_entry = entry; 528 529 return 0; 530 } 531 532 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 533 { 534 if (!per_pin->codec->bus->shutdown) { 535 snd_info_free_entry(per_pin->proc_entry); 536 per_pin->proc_entry = NULL; 537 } 538 } 539 #else 540 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin, 541 int index) 542 { 543 return 0; 544 } 545 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin) 546 { 547 } 548 #endif 549 550 /* 551 * Audio InfoFrame routines 552 */ 553 554 /* 555 * Enable Audio InfoFrame Transmission 556 */ 557 static void hdmi_start_infoframe_trans(struct hda_codec *codec, 558 hda_nid_t pin_nid) 559 { 560 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 561 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 562 AC_DIPXMIT_BEST); 563 } 564 565 /* 566 * Disable Audio InfoFrame Transmission 567 */ 568 static void hdmi_stop_infoframe_trans(struct hda_codec *codec, 569 hda_nid_t pin_nid) 570 { 571 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 572 snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT, 573 AC_DIPXMIT_DISABLE); 574 } 575 576 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid) 577 { 578 #ifdef CONFIG_SND_DEBUG_VERBOSE 579 int i; 580 int size; 581 582 size = snd_hdmi_get_eld_size(codec, pin_nid); 583 codec_dbg(codec, "HDMI: ELD buf size is %d\n", size); 584 585 for (i = 0; i < 8; i++) { 586 size = snd_hda_codec_read(codec, pin_nid, 0, 587 AC_VERB_GET_HDMI_DIP_SIZE, i); 588 codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size); 589 } 590 #endif 591 } 592 593 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid) 594 { 595 #ifdef BE_PARANOID 596 int i, j; 597 int size; 598 int pi, bi; 599 for (i = 0; i < 8; i++) { 600 size = snd_hda_codec_read(codec, pin_nid, 0, 601 AC_VERB_GET_HDMI_DIP_SIZE, i); 602 if (size == 0) 603 continue; 604 605 hdmi_set_dip_index(codec, pin_nid, i, 0x0); 606 for (j = 1; j < 1000; j++) { 607 hdmi_write_dip_byte(codec, pin_nid, 0x0); 608 hdmi_get_dip_index(codec, pin_nid, &pi, &bi); 609 if (pi != i) 610 codec_dbg(codec, "dip index %d: %d != %d\n", 611 bi, pi, i); 612 if (bi == 0) /* byte index wrapped around */ 613 break; 614 } 615 codec_dbg(codec, 616 "HDMI: DIP GP[%d] buf reported size=%d, written=%d\n", 617 i, size, j); 618 } 619 #endif 620 } 621 622 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai) 623 { 624 u8 *bytes = (u8 *)hdmi_ai; 625 u8 sum = 0; 626 int i; 627 628 hdmi_ai->checksum = 0; 629 630 for (i = 0; i < sizeof(*hdmi_ai); i++) 631 sum += bytes[i]; 632 633 hdmi_ai->checksum = -sum; 634 } 635 636 static void hdmi_fill_audio_infoframe(struct hda_codec *codec, 637 hda_nid_t pin_nid, 638 u8 *dip, int size) 639 { 640 int i; 641 642 hdmi_debug_dip_size(codec, pin_nid); 643 hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */ 644 645 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 646 for (i = 0; i < size; i++) 647 hdmi_write_dip_byte(codec, pin_nid, dip[i]); 648 } 649 650 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid, 651 u8 *dip, int size) 652 { 653 u8 val; 654 int i; 655 656 hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0); 657 if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0) 658 != AC_DIPXMIT_BEST) 659 return false; 660 661 for (i = 0; i < size; i++) { 662 val = snd_hda_codec_read(codec, pin_nid, 0, 663 AC_VERB_GET_HDMI_DIP_DATA, 0); 664 if (val != dip[i]) 665 return false; 666 } 667 668 return true; 669 } 670 671 static int hdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 672 int dev_id, unsigned char *buf, int *eld_size) 673 { 674 snd_hda_set_dev_select(codec, nid, dev_id); 675 676 return snd_hdmi_get_eld(codec, nid, buf, eld_size); 677 } 678 679 static void hdmi_pin_setup_infoframe(struct hda_codec *codec, 680 hda_nid_t pin_nid, int dev_id, 681 int ca, int active_channels, 682 int conn_type) 683 { 684 struct hdmi_spec *spec = codec->spec; 685 union audio_infoframe ai; 686 687 memset(&ai, 0, sizeof(ai)); 688 if ((conn_type == 0) || /* HDMI */ 689 /* Nvidia DisplayPort: Nvidia HW expects same layout as HDMI */ 690 (conn_type == 1 && spec->nv_dp_workaround)) { 691 struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi; 692 693 if (conn_type == 0) { /* HDMI */ 694 hdmi_ai->type = 0x84; 695 hdmi_ai->ver = 0x01; 696 hdmi_ai->len = 0x0a; 697 } else {/* Nvidia DP */ 698 hdmi_ai->type = 0x84; 699 hdmi_ai->ver = 0x1b; 700 hdmi_ai->len = 0x11 << 2; 701 } 702 hdmi_ai->CC02_CT47 = active_channels - 1; 703 hdmi_ai->CA = ca; 704 hdmi_checksum_audio_infoframe(hdmi_ai); 705 } else if (conn_type == 1) { /* DisplayPort */ 706 struct dp_audio_infoframe *dp_ai = &ai.dp; 707 708 dp_ai->type = 0x84; 709 dp_ai->len = 0x1b; 710 dp_ai->ver = 0x11 << 2; 711 dp_ai->CC02_CT47 = active_channels - 1; 712 dp_ai->CA = ca; 713 } else { 714 codec_dbg(codec, "HDMI: unknown connection type at pin NID 0x%x\n", pin_nid); 715 return; 716 } 717 718 snd_hda_set_dev_select(codec, pin_nid, dev_id); 719 720 /* 721 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or 722 * sizeof(*dp_ai) to avoid partial match/update problems when 723 * the user switches between HDMI/DP monitors. 724 */ 725 if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes, 726 sizeof(ai))) { 727 codec_dbg(codec, "%s: pin NID=0x%x channels=%d ca=0x%02x\n", 728 __func__, pin_nid, active_channels, ca); 729 hdmi_stop_infoframe_trans(codec, pin_nid); 730 hdmi_fill_audio_infoframe(codec, pin_nid, 731 ai.bytes, sizeof(ai)); 732 hdmi_start_infoframe_trans(codec, pin_nid); 733 } 734 } 735 736 static void hdmi_setup_audio_infoframe(struct hda_codec *codec, 737 struct hdmi_spec_per_pin *per_pin, 738 bool non_pcm) 739 { 740 struct hdmi_spec *spec = codec->spec; 741 struct hdac_chmap *chmap = &spec->chmap; 742 hda_nid_t pin_nid = per_pin->pin_nid; 743 int dev_id = per_pin->dev_id; 744 int channels = per_pin->channels; 745 int active_channels; 746 struct hdmi_eld *eld; 747 int ca; 748 749 if (!channels) 750 return; 751 752 snd_hda_set_dev_select(codec, pin_nid, dev_id); 753 754 /* some HW (e.g. HSW+) needs reprogramming the amp at each time */ 755 if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP) 756 snd_hda_codec_write(codec, pin_nid, 0, 757 AC_VERB_SET_AMP_GAIN_MUTE, 758 AMP_OUT_UNMUTE); 759 760 eld = &per_pin->sink_eld; 761 762 ca = snd_hdac_channel_allocation(&codec->core, 763 eld->info.spk_alloc, channels, 764 per_pin->chmap_set, non_pcm, per_pin->chmap); 765 766 active_channels = snd_hdac_get_active_channels(ca); 767 768 chmap->ops.set_channel_count(&codec->core, per_pin->cvt_nid, 769 active_channels); 770 771 /* 772 * always configure channel mapping, it may have been changed by the 773 * user in the meantime 774 */ 775 snd_hdac_setup_channel_mapping(&spec->chmap, 776 pin_nid, non_pcm, ca, channels, 777 per_pin->chmap, per_pin->chmap_set); 778 779 spec->ops.pin_setup_infoframe(codec, pin_nid, dev_id, 780 ca, active_channels, eld->info.conn_type); 781 782 per_pin->non_pcm = non_pcm; 783 } 784 785 /* 786 * Unsolicited events 787 */ 788 789 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll); 790 791 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid, 792 int dev_id) 793 { 794 struct hdmi_spec *spec = codec->spec; 795 int pin_idx = pin_id_to_pin_index(codec, nid, dev_id); 796 797 if (pin_idx < 0) 798 return; 799 mutex_lock(&spec->pcm_lock); 800 hdmi_present_sense(get_pin(spec, pin_idx), 1); 801 mutex_unlock(&spec->pcm_lock); 802 } 803 804 static void jack_callback(struct hda_codec *codec, 805 struct hda_jack_callback *jack) 806 { 807 /* stop polling when notification is enabled */ 808 if (codec_has_acomp(codec)) 809 return; 810 811 check_presence_and_report(codec, jack->nid, jack->dev_id); 812 } 813 814 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res, 815 struct hda_jack_tbl *jack) 816 { 817 jack->jack_dirty = 1; 818 819 codec_dbg(codec, 820 "HDMI hot plug event: Codec=%d NID=0x%x Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n", 821 codec->addr, jack->nid, jack->dev_id, !!(res & AC_UNSOL_RES_IA), 822 !!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV)); 823 824 check_presence_and_report(codec, jack->nid, jack->dev_id); 825 } 826 827 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res) 828 { 829 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 830 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 831 int cp_state = !!(res & AC_UNSOL_RES_CP_STATE); 832 int cp_ready = !!(res & AC_UNSOL_RES_CP_READY); 833 834 codec_info(codec, 835 "HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n", 836 codec->addr, 837 tag, 838 subtag, 839 cp_state, 840 cp_ready); 841 842 /* TODO */ 843 if (cp_state) { 844 ; 845 } 846 if (cp_ready) { 847 ; 848 } 849 } 850 851 852 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res) 853 { 854 int tag = res >> AC_UNSOL_RES_TAG_SHIFT; 855 int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT; 856 struct hda_jack_tbl *jack; 857 858 if (codec_has_acomp(codec)) 859 return; 860 861 if (codec->dp_mst) { 862 int dev_entry = 863 (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT; 864 865 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, dev_entry); 866 } else { 867 jack = snd_hda_jack_tbl_get_from_tag(codec, tag, 0); 868 } 869 870 if (!jack) { 871 codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag); 872 return; 873 } 874 875 if (subtag == 0) 876 hdmi_intrinsic_event(codec, res, jack); 877 else 878 hdmi_non_intrinsic_event(codec, res); 879 } 880 881 static void haswell_verify_D0(struct hda_codec *codec, 882 hda_nid_t cvt_nid, hda_nid_t nid) 883 { 884 int pwr; 885 886 /* For Haswell, the converter 1/2 may keep in D3 state after bootup, 887 * thus pins could only choose converter 0 for use. Make sure the 888 * converters are in correct power state */ 889 if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0)) 890 snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0); 891 892 if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) { 893 snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE, 894 AC_PWRST_D0); 895 msleep(40); 896 pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0); 897 pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT; 898 codec_dbg(codec, "Haswell HDMI audio: Power for NID 0x%x is now D%d\n", nid, pwr); 899 } 900 } 901 902 /* 903 * Callbacks 904 */ 905 906 /* HBR should be Non-PCM, 8 channels */ 907 #define is_hbr_format(format) \ 908 ((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7) 909 910 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 911 int dev_id, bool hbr) 912 { 913 int pinctl, new_pinctl; 914 915 if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) { 916 snd_hda_set_dev_select(codec, pin_nid, dev_id); 917 pinctl = snd_hda_codec_read(codec, pin_nid, 0, 918 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 919 920 if (pinctl < 0) 921 return hbr ? -EINVAL : 0; 922 923 new_pinctl = pinctl & ~AC_PINCTL_EPT; 924 if (hbr) 925 new_pinctl |= AC_PINCTL_EPT_HBR; 926 else 927 new_pinctl |= AC_PINCTL_EPT_NATIVE; 928 929 codec_dbg(codec, 930 "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n", 931 pin_nid, 932 pinctl == new_pinctl ? "" : "new-", 933 new_pinctl); 934 935 if (pinctl != new_pinctl) 936 snd_hda_codec_write(codec, pin_nid, 0, 937 AC_VERB_SET_PIN_WIDGET_CONTROL, 938 new_pinctl); 939 } else if (hbr) 940 return -EINVAL; 941 942 return 0; 943 } 944 945 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 946 hda_nid_t pin_nid, int dev_id, 947 u32 stream_tag, int format) 948 { 949 struct hdmi_spec *spec = codec->spec; 950 unsigned int param; 951 int err; 952 953 err = spec->ops.pin_hbr_setup(codec, pin_nid, dev_id, 954 is_hbr_format(format)); 955 956 if (err) { 957 codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n"); 958 return err; 959 } 960 961 if (spec->intel_hsw_fixup) { 962 963 /* 964 * on recent platforms IEC Coding Type is required for HBR 965 * support, read current Digital Converter settings and set 966 * ICT bitfield if needed. 967 */ 968 param = snd_hda_codec_read(codec, cvt_nid, 0, 969 AC_VERB_GET_DIGI_CONVERT_1, 0); 970 971 param = (param >> 16) & ~(AC_DIG3_ICT); 972 973 /* on recent platforms ICT mode is required for HBR support */ 974 if (is_hbr_format(format)) 975 param |= 0x1; 976 977 snd_hda_codec_write(codec, cvt_nid, 0, 978 AC_VERB_SET_DIGI_CONVERT_3, param); 979 } 980 981 snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format); 982 return 0; 983 } 984 985 /* Try to find an available converter 986 * If pin_idx is less then zero, just try to find an available converter. 987 * Otherwise, try to find an available converter and get the cvt mux index 988 * of the pin. 989 */ 990 static int hdmi_choose_cvt(struct hda_codec *codec, 991 int pin_idx, int *cvt_id, 992 bool silent) 993 { 994 struct hdmi_spec *spec = codec->spec; 995 struct hdmi_spec_per_pin *per_pin; 996 struct hdmi_spec_per_cvt *per_cvt = NULL; 997 int cvt_idx, mux_idx = 0; 998 999 /* pin_idx < 0 means no pin will be bound to the converter */ 1000 if (pin_idx < 0) 1001 per_pin = NULL; 1002 else 1003 per_pin = get_pin(spec, pin_idx); 1004 1005 if (per_pin && per_pin->silent_stream) { 1006 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1007 per_cvt = get_cvt(spec, cvt_idx); 1008 if (per_cvt->assigned && !silent) 1009 return -EBUSY; 1010 if (cvt_id) 1011 *cvt_id = cvt_idx; 1012 return 0; 1013 } 1014 1015 /* Dynamically assign converter to stream */ 1016 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1017 per_cvt = get_cvt(spec, cvt_idx); 1018 1019 /* Must not already be assigned */ 1020 if (per_cvt->assigned || per_cvt->silent_stream) 1021 continue; 1022 if (per_pin == NULL) 1023 break; 1024 /* Must be in pin's mux's list of converters */ 1025 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1026 if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid) 1027 break; 1028 /* Not in mux list */ 1029 if (mux_idx == per_pin->num_mux_nids) 1030 continue; 1031 break; 1032 } 1033 1034 /* No free converters */ 1035 if (cvt_idx == spec->num_cvts) 1036 return -EBUSY; 1037 1038 if (per_pin != NULL) 1039 per_pin->mux_idx = mux_idx; 1040 1041 if (cvt_id) 1042 *cvt_id = cvt_idx; 1043 1044 return 0; 1045 } 1046 1047 /* Assure the pin select the right convetor */ 1048 static void intel_verify_pin_cvt_connect(struct hda_codec *codec, 1049 struct hdmi_spec_per_pin *per_pin) 1050 { 1051 hda_nid_t pin_nid = per_pin->pin_nid; 1052 int mux_idx, curr; 1053 1054 mux_idx = per_pin->mux_idx; 1055 curr = snd_hda_codec_read(codec, pin_nid, 0, 1056 AC_VERB_GET_CONNECT_SEL, 0); 1057 if (curr != mux_idx) 1058 snd_hda_codec_write_cache(codec, pin_nid, 0, 1059 AC_VERB_SET_CONNECT_SEL, 1060 mux_idx); 1061 } 1062 1063 /* get the mux index for the converter of the pins 1064 * converter's mux index is the same for all pins on Intel platform 1065 */ 1066 static int intel_cvt_id_to_mux_idx(struct hdmi_spec *spec, 1067 hda_nid_t cvt_nid) 1068 { 1069 int i; 1070 1071 for (i = 0; i < spec->num_cvts; i++) 1072 if (spec->cvt_nids[i] == cvt_nid) 1073 return i; 1074 return -EINVAL; 1075 } 1076 1077 /* Intel HDMI workaround to fix audio routing issue: 1078 * For some Intel display codecs, pins share the same connection list. 1079 * So a conveter can be selected by multiple pins and playback on any of these 1080 * pins will generate sound on the external display, because audio flows from 1081 * the same converter to the display pipeline. Also muting one pin may make 1082 * other pins have no sound output. 1083 * So this function assures that an assigned converter for a pin is not selected 1084 * by any other pins. 1085 */ 1086 static void intel_not_share_assigned_cvt(struct hda_codec *codec, 1087 hda_nid_t pin_nid, 1088 int dev_id, int mux_idx) 1089 { 1090 struct hdmi_spec *spec = codec->spec; 1091 hda_nid_t nid; 1092 int cvt_idx, curr; 1093 struct hdmi_spec_per_cvt *per_cvt; 1094 struct hdmi_spec_per_pin *per_pin; 1095 int pin_idx; 1096 1097 /* configure the pins connections */ 1098 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 1099 int dev_id_saved; 1100 int dev_num; 1101 1102 per_pin = get_pin(spec, pin_idx); 1103 /* 1104 * pin not connected to monitor 1105 * no need to operate on it 1106 */ 1107 if (!per_pin->pcm) 1108 continue; 1109 1110 if ((per_pin->pin_nid == pin_nid) && 1111 (per_pin->dev_id == dev_id)) 1112 continue; 1113 1114 /* 1115 * if per_pin->dev_id >= dev_num, 1116 * snd_hda_get_dev_select() will fail, 1117 * and the following operation is unpredictable. 1118 * So skip this situation. 1119 */ 1120 dev_num = snd_hda_get_num_devices(codec, per_pin->pin_nid) + 1; 1121 if (per_pin->dev_id >= dev_num) 1122 continue; 1123 1124 nid = per_pin->pin_nid; 1125 1126 /* 1127 * Calling this function should not impact 1128 * on the device entry selection 1129 * So let's save the dev id for each pin, 1130 * and restore it when return 1131 */ 1132 dev_id_saved = snd_hda_get_dev_select(codec, nid); 1133 snd_hda_set_dev_select(codec, nid, per_pin->dev_id); 1134 curr = snd_hda_codec_read(codec, nid, 0, 1135 AC_VERB_GET_CONNECT_SEL, 0); 1136 if (curr != mux_idx) { 1137 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1138 continue; 1139 } 1140 1141 1142 /* choose an unassigned converter. The conveters in the 1143 * connection list are in the same order as in the codec. 1144 */ 1145 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 1146 per_cvt = get_cvt(spec, cvt_idx); 1147 if (!per_cvt->assigned) { 1148 codec_dbg(codec, 1149 "choose cvt %d for pin NID 0x%x\n", 1150 cvt_idx, nid); 1151 snd_hda_codec_write_cache(codec, nid, 0, 1152 AC_VERB_SET_CONNECT_SEL, 1153 cvt_idx); 1154 break; 1155 } 1156 } 1157 snd_hda_set_dev_select(codec, nid, dev_id_saved); 1158 } 1159 } 1160 1161 /* A wrapper of intel_not_share_asigned_cvt() */ 1162 static void intel_not_share_assigned_cvt_nid(struct hda_codec *codec, 1163 hda_nid_t pin_nid, int dev_id, hda_nid_t cvt_nid) 1164 { 1165 int mux_idx; 1166 struct hdmi_spec *spec = codec->spec; 1167 1168 /* On Intel platform, the mapping of converter nid to 1169 * mux index of the pins are always the same. 1170 * The pin nid may be 0, this means all pins will not 1171 * share the converter. 1172 */ 1173 mux_idx = intel_cvt_id_to_mux_idx(spec, cvt_nid); 1174 if (mux_idx >= 0) 1175 intel_not_share_assigned_cvt(codec, pin_nid, dev_id, mux_idx); 1176 } 1177 1178 /* skeleton caller of pin_cvt_fixup ops */ 1179 static void pin_cvt_fixup(struct hda_codec *codec, 1180 struct hdmi_spec_per_pin *per_pin, 1181 hda_nid_t cvt_nid) 1182 { 1183 struct hdmi_spec *spec = codec->spec; 1184 1185 if (spec->ops.pin_cvt_fixup) 1186 spec->ops.pin_cvt_fixup(codec, per_pin, cvt_nid); 1187 } 1188 1189 /* called in hdmi_pcm_open when no pin is assigned to the PCM */ 1190 static int hdmi_pcm_open_no_pin(struct hda_pcm_stream *hinfo, 1191 struct hda_codec *codec, 1192 struct snd_pcm_substream *substream) 1193 { 1194 struct hdmi_spec *spec = codec->spec; 1195 struct snd_pcm_runtime *runtime = substream->runtime; 1196 int cvt_idx, pcm_idx; 1197 struct hdmi_spec_per_cvt *per_cvt = NULL; 1198 int err; 1199 1200 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1201 if (pcm_idx < 0) 1202 return -EINVAL; 1203 1204 err = hdmi_choose_cvt(codec, -1, &cvt_idx, false); 1205 if (err) 1206 return err; 1207 1208 per_cvt = get_cvt(spec, cvt_idx); 1209 per_cvt->assigned = true; 1210 hinfo->nid = per_cvt->cvt_nid; 1211 1212 pin_cvt_fixup(codec, NULL, per_cvt->cvt_nid); 1213 1214 set_bit(pcm_idx, &spec->pcm_in_use); 1215 /* todo: setup spdif ctls assign */ 1216 1217 /* Initially set the converter's capabilities */ 1218 hinfo->channels_min = per_cvt->channels_min; 1219 hinfo->channels_max = per_cvt->channels_max; 1220 hinfo->rates = per_cvt->rates; 1221 hinfo->formats = per_cvt->formats; 1222 hinfo->maxbps = per_cvt->maxbps; 1223 1224 /* Store the updated parameters */ 1225 runtime->hw.channels_min = hinfo->channels_min; 1226 runtime->hw.channels_max = hinfo->channels_max; 1227 runtime->hw.formats = hinfo->formats; 1228 runtime->hw.rates = hinfo->rates; 1229 1230 snd_pcm_hw_constraint_step(substream->runtime, 0, 1231 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1232 return 0; 1233 } 1234 1235 /* 1236 * HDA PCM callbacks 1237 */ 1238 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo, 1239 struct hda_codec *codec, 1240 struct snd_pcm_substream *substream) 1241 { 1242 struct hdmi_spec *spec = codec->spec; 1243 struct snd_pcm_runtime *runtime = substream->runtime; 1244 int pin_idx, cvt_idx, pcm_idx; 1245 struct hdmi_spec_per_pin *per_pin; 1246 struct hdmi_eld *eld; 1247 struct hdmi_spec_per_cvt *per_cvt = NULL; 1248 int err; 1249 1250 /* Validate hinfo */ 1251 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 1252 if (pcm_idx < 0) 1253 return -EINVAL; 1254 1255 mutex_lock(&spec->pcm_lock); 1256 pin_idx = hinfo_to_pin_index(codec, hinfo); 1257 /* no pin is assigned to the PCM 1258 * PA need pcm open successfully when probe 1259 */ 1260 if (pin_idx < 0) { 1261 err = hdmi_pcm_open_no_pin(hinfo, codec, substream); 1262 goto unlock; 1263 } 1264 1265 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, false); 1266 if (err < 0) 1267 goto unlock; 1268 1269 per_cvt = get_cvt(spec, cvt_idx); 1270 /* Claim converter */ 1271 per_cvt->assigned = true; 1272 1273 set_bit(pcm_idx, &spec->pcm_in_use); 1274 per_pin = get_pin(spec, pin_idx); 1275 per_pin->cvt_nid = per_cvt->cvt_nid; 1276 hinfo->nid = per_cvt->cvt_nid; 1277 1278 /* flip stripe flag for the assigned stream if supported */ 1279 if (get_wcaps(codec, per_cvt->cvt_nid) & AC_WCAP_STRIPE) 1280 azx_stream(get_azx_dev(substream))->stripe = 1; 1281 1282 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1283 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1284 AC_VERB_SET_CONNECT_SEL, 1285 per_pin->mux_idx); 1286 1287 /* configure unused pins to choose other converters */ 1288 pin_cvt_fixup(codec, per_pin, 0); 1289 1290 snd_hda_spdif_ctls_assign(codec, pcm_idx, per_cvt->cvt_nid); 1291 1292 /* Initially set the converter's capabilities */ 1293 hinfo->channels_min = per_cvt->channels_min; 1294 hinfo->channels_max = per_cvt->channels_max; 1295 hinfo->rates = per_cvt->rates; 1296 hinfo->formats = per_cvt->formats; 1297 hinfo->maxbps = per_cvt->maxbps; 1298 1299 eld = &per_pin->sink_eld; 1300 /* Restrict capabilities by ELD if this isn't disabled */ 1301 if (!static_hdmi_pcm && eld->eld_valid) { 1302 snd_hdmi_eld_update_pcm_info(&eld->info, hinfo); 1303 if (hinfo->channels_min > hinfo->channels_max || 1304 !hinfo->rates || !hinfo->formats) { 1305 per_cvt->assigned = false; 1306 hinfo->nid = 0; 1307 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 1308 err = -ENODEV; 1309 goto unlock; 1310 } 1311 } 1312 1313 /* Store the updated parameters */ 1314 runtime->hw.channels_min = hinfo->channels_min; 1315 runtime->hw.channels_max = hinfo->channels_max; 1316 runtime->hw.formats = hinfo->formats; 1317 runtime->hw.rates = hinfo->rates; 1318 1319 snd_pcm_hw_constraint_step(substream->runtime, 0, 1320 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 1321 unlock: 1322 mutex_unlock(&spec->pcm_lock); 1323 return err; 1324 } 1325 1326 /* 1327 * HDA/HDMI auto parsing 1328 */ 1329 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx) 1330 { 1331 struct hdmi_spec *spec = codec->spec; 1332 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 1333 hda_nid_t pin_nid = per_pin->pin_nid; 1334 int dev_id = per_pin->dev_id; 1335 int conns; 1336 1337 if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) { 1338 codec_warn(codec, 1339 "HDMI: pin NID 0x%x wcaps %#x does not support connection list\n", 1340 pin_nid, get_wcaps(codec, pin_nid)); 1341 return -EINVAL; 1342 } 1343 1344 snd_hda_set_dev_select(codec, pin_nid, dev_id); 1345 1346 if (spec->intel_hsw_fixup) { 1347 conns = spec->num_cvts; 1348 memcpy(per_pin->mux_nids, spec->cvt_nids, 1349 sizeof(hda_nid_t) * conns); 1350 } else { 1351 conns = snd_hda_get_raw_connections(codec, pin_nid, 1352 per_pin->mux_nids, 1353 HDA_MAX_CONNECTIONS); 1354 } 1355 1356 /* all the device entries on the same pin have the same conn list */ 1357 per_pin->num_mux_nids = conns; 1358 1359 return 0; 1360 } 1361 1362 static int hdmi_find_pcm_slot(struct hdmi_spec *spec, 1363 struct hdmi_spec_per_pin *per_pin) 1364 { 1365 int i; 1366 1367 for (i = 0; i < spec->pcm_used; i++) { 1368 if (!test_bit(i, &spec->pcm_bitmap)) 1369 return i; 1370 } 1371 return -EBUSY; 1372 } 1373 1374 static void hdmi_attach_hda_pcm(struct hdmi_spec *spec, 1375 struct hdmi_spec_per_pin *per_pin) 1376 { 1377 int idx; 1378 1379 /* pcm already be attached to the pin */ 1380 if (per_pin->pcm) 1381 return; 1382 idx = hdmi_find_pcm_slot(spec, per_pin); 1383 if (idx == -EBUSY) 1384 return; 1385 per_pin->pcm_idx = idx; 1386 per_pin->pcm = get_hdmi_pcm(spec, idx); 1387 set_bit(idx, &spec->pcm_bitmap); 1388 } 1389 1390 static void hdmi_detach_hda_pcm(struct hdmi_spec *spec, 1391 struct hdmi_spec_per_pin *per_pin) 1392 { 1393 int idx; 1394 1395 /* pcm already be detached from the pin */ 1396 if (!per_pin->pcm) 1397 return; 1398 idx = per_pin->pcm_idx; 1399 per_pin->pcm_idx = -1; 1400 per_pin->pcm = NULL; 1401 if (idx >= 0 && idx < spec->pcm_used) 1402 clear_bit(idx, &spec->pcm_bitmap); 1403 } 1404 1405 static int hdmi_get_pin_cvt_mux(struct hdmi_spec *spec, 1406 struct hdmi_spec_per_pin *per_pin, hda_nid_t cvt_nid) 1407 { 1408 int mux_idx; 1409 1410 for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++) 1411 if (per_pin->mux_nids[mux_idx] == cvt_nid) 1412 break; 1413 return mux_idx; 1414 } 1415 1416 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid); 1417 1418 static void hdmi_pcm_setup_pin(struct hdmi_spec *spec, 1419 struct hdmi_spec_per_pin *per_pin) 1420 { 1421 struct hda_codec *codec = per_pin->codec; 1422 struct hda_pcm *pcm; 1423 struct hda_pcm_stream *hinfo; 1424 struct snd_pcm_substream *substream; 1425 int mux_idx; 1426 bool non_pcm; 1427 1428 if (per_pin->pcm_idx < 0 || per_pin->pcm_idx >= spec->pcm_used) 1429 return; 1430 pcm = get_pcm_rec(spec, per_pin->pcm_idx); 1431 if (!pcm->pcm) 1432 return; 1433 if (!test_bit(per_pin->pcm_idx, &spec->pcm_in_use)) 1434 return; 1435 1436 /* hdmi audio only uses playback and one substream */ 1437 hinfo = pcm->stream; 1438 substream = pcm->pcm->streams[0].substream; 1439 1440 per_pin->cvt_nid = hinfo->nid; 1441 1442 mux_idx = hdmi_get_pin_cvt_mux(spec, per_pin, hinfo->nid); 1443 if (mux_idx < per_pin->num_mux_nids) { 1444 snd_hda_set_dev_select(codec, per_pin->pin_nid, 1445 per_pin->dev_id); 1446 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1447 AC_VERB_SET_CONNECT_SEL, 1448 mux_idx); 1449 } 1450 snd_hda_spdif_ctls_assign(codec, per_pin->pcm_idx, hinfo->nid); 1451 1452 non_pcm = check_non_pcm_per_cvt(codec, hinfo->nid); 1453 if (substream->runtime) 1454 per_pin->channels = substream->runtime->channels; 1455 per_pin->setup = true; 1456 per_pin->mux_idx = mux_idx; 1457 1458 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 1459 } 1460 1461 static void hdmi_pcm_reset_pin(struct hdmi_spec *spec, 1462 struct hdmi_spec_per_pin *per_pin) 1463 { 1464 if (per_pin->pcm_idx >= 0 && per_pin->pcm_idx < spec->pcm_used) 1465 snd_hda_spdif_ctls_unassign(per_pin->codec, per_pin->pcm_idx); 1466 1467 per_pin->chmap_set = false; 1468 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 1469 1470 per_pin->setup = false; 1471 per_pin->channels = 0; 1472 } 1473 1474 static struct snd_jack *pin_idx_to_pcm_jack(struct hda_codec *codec, 1475 struct hdmi_spec_per_pin *per_pin) 1476 { 1477 struct hdmi_spec *spec = codec->spec; 1478 1479 if (per_pin->pcm_idx >= 0) 1480 return spec->pcm_rec[per_pin->pcm_idx].jack; 1481 else 1482 return NULL; 1483 } 1484 1485 /* update per_pin ELD from the given new ELD; 1486 * setup info frame and notification accordingly 1487 * also notify ELD kctl and report jack status changes 1488 */ 1489 static void update_eld(struct hda_codec *codec, 1490 struct hdmi_spec_per_pin *per_pin, 1491 struct hdmi_eld *eld, 1492 int repoll) 1493 { 1494 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 1495 struct hdmi_spec *spec = codec->spec; 1496 struct snd_jack *pcm_jack; 1497 bool old_eld_valid = pin_eld->eld_valid; 1498 bool eld_changed; 1499 int pcm_idx; 1500 1501 if (eld->eld_valid) { 1502 if (eld->eld_size <= 0 || 1503 snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer, 1504 eld->eld_size) < 0) { 1505 eld->eld_valid = false; 1506 if (repoll) { 1507 schedule_delayed_work(&per_pin->work, 1508 msecs_to_jiffies(300)); 1509 return; 1510 } 1511 } 1512 } 1513 1514 if (!eld->eld_valid || eld->eld_size <= 0 || eld->info.sad_count <= 0) { 1515 eld->eld_valid = false; 1516 eld->eld_size = 0; 1517 } 1518 1519 /* for monitor disconnection, save pcm_idx firstly */ 1520 pcm_idx = per_pin->pcm_idx; 1521 1522 /* 1523 * pcm_idx >=0 before update_eld() means it is in monitor 1524 * disconnected event. Jack must be fetched before update_eld(). 1525 */ 1526 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1527 1528 if (eld->eld_valid) { 1529 hdmi_attach_hda_pcm(spec, per_pin); 1530 hdmi_pcm_setup_pin(spec, per_pin); 1531 } else { 1532 hdmi_pcm_reset_pin(spec, per_pin); 1533 hdmi_detach_hda_pcm(spec, per_pin); 1534 } 1535 /* if pcm_idx == -1, it means this is in monitor connection event 1536 * we can get the correct pcm_idx now. 1537 */ 1538 if (pcm_idx == -1) 1539 pcm_idx = per_pin->pcm_idx; 1540 if (!pcm_jack) 1541 pcm_jack = pin_idx_to_pcm_jack(codec, per_pin); 1542 1543 if (eld->eld_valid) 1544 snd_hdmi_show_eld(codec, &eld->info); 1545 1546 eld_changed = (pin_eld->eld_valid != eld->eld_valid); 1547 eld_changed |= (pin_eld->monitor_present != eld->monitor_present); 1548 if (!eld_changed && eld->eld_valid && pin_eld->eld_valid) 1549 if (pin_eld->eld_size != eld->eld_size || 1550 memcmp(pin_eld->eld_buffer, eld->eld_buffer, 1551 eld->eld_size) != 0) 1552 eld_changed = true; 1553 1554 if (eld_changed) { 1555 pin_eld->monitor_present = eld->monitor_present; 1556 pin_eld->eld_valid = eld->eld_valid; 1557 pin_eld->eld_size = eld->eld_size; 1558 if (eld->eld_valid) 1559 memcpy(pin_eld->eld_buffer, eld->eld_buffer, 1560 eld->eld_size); 1561 pin_eld->info = eld->info; 1562 } 1563 1564 /* 1565 * Re-setup pin and infoframe. This is needed e.g. when 1566 * - sink is first plugged-in 1567 * - transcoder can change during stream playback on Haswell 1568 * and this can make HW reset converter selection on a pin. 1569 */ 1570 if (eld->eld_valid && !old_eld_valid && per_pin->setup) { 1571 pin_cvt_fixup(codec, per_pin, 0); 1572 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1573 } 1574 1575 if (eld_changed && pcm_idx >= 0) 1576 snd_ctl_notify(codec->card, 1577 SNDRV_CTL_EVENT_MASK_VALUE | 1578 SNDRV_CTL_EVENT_MASK_INFO, 1579 &get_hdmi_pcm(spec, pcm_idx)->eld_ctl->id); 1580 1581 if (eld_changed && pcm_jack) 1582 snd_jack_report(pcm_jack, 1583 (eld->monitor_present && eld->eld_valid) ? 1584 SND_JACK_AVOUT : 0); 1585 } 1586 1587 /* update ELD and jack state via HD-audio verbs */ 1588 static void hdmi_present_sense_via_verbs(struct hdmi_spec_per_pin *per_pin, 1589 int repoll) 1590 { 1591 struct hda_codec *codec = per_pin->codec; 1592 struct hdmi_spec *spec = codec->spec; 1593 struct hdmi_eld *eld = &spec->temp_eld; 1594 struct device *dev = hda_codec_dev(codec); 1595 hda_nid_t pin_nid = per_pin->pin_nid; 1596 int dev_id = per_pin->dev_id; 1597 /* 1598 * Always execute a GetPinSense verb here, even when called from 1599 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited 1600 * response's PD bit is not the real PD value, but indicates that 1601 * the real PD value changed. An older version of the HD-audio 1602 * specification worked this way. Hence, we just ignore the data in 1603 * the unsolicited response to avoid custom WARs. 1604 */ 1605 int present; 1606 int ret; 1607 1608 #ifdef CONFIG_PM 1609 if (dev->power.runtime_status == RPM_SUSPENDING) 1610 return; 1611 #endif 1612 1613 ret = snd_hda_power_up_pm(codec); 1614 if (ret < 0 && pm_runtime_suspended(dev)) 1615 goto out; 1616 1617 present = snd_hda_jack_pin_sense(codec, pin_nid, dev_id); 1618 1619 mutex_lock(&per_pin->lock); 1620 eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE); 1621 if (eld->monitor_present) 1622 eld->eld_valid = !!(present & AC_PINSENSE_ELDV); 1623 else 1624 eld->eld_valid = false; 1625 1626 codec_dbg(codec, 1627 "HDMI status: Codec=%d NID=0x%x Presence_Detect=%d ELD_Valid=%d\n", 1628 codec->addr, pin_nid, eld->monitor_present, eld->eld_valid); 1629 1630 if (eld->eld_valid) { 1631 if (spec->ops.pin_get_eld(codec, pin_nid, dev_id, 1632 eld->eld_buffer, &eld->eld_size) < 0) 1633 eld->eld_valid = false; 1634 } 1635 1636 update_eld(codec, per_pin, eld, repoll); 1637 mutex_unlock(&per_pin->lock); 1638 out: 1639 snd_hda_power_down_pm(codec); 1640 } 1641 1642 #define I915_SILENT_RATE 48000 1643 #define I915_SILENT_CHANNELS 2 1644 #define I915_SILENT_FORMAT SNDRV_PCM_FORMAT_S16_LE 1645 #define I915_SILENT_FORMAT_BITS 16 1646 #define I915_SILENT_FMT_MASK 0xf 1647 1648 static void silent_stream_enable_i915(struct hda_codec *codec, 1649 struct hdmi_spec_per_pin *per_pin) 1650 { 1651 unsigned int format; 1652 1653 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 1654 per_pin->dev_id, I915_SILENT_RATE); 1655 1656 /* trigger silent stream generation in hw */ 1657 format = snd_hdac_calc_stream_format(I915_SILENT_RATE, I915_SILENT_CHANNELS, 1658 I915_SILENT_FORMAT, I915_SILENT_FORMAT_BITS, 0); 1659 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, 1660 I915_SILENT_FMT_MASK, I915_SILENT_FMT_MASK, format); 1661 usleep_range(100, 200); 1662 snd_hda_codec_setup_stream(codec, per_pin->cvt_nid, I915_SILENT_FMT_MASK, 0, format); 1663 1664 per_pin->channels = I915_SILENT_CHANNELS; 1665 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 1666 } 1667 1668 static void silent_stream_set_kae(struct hda_codec *codec, 1669 struct hdmi_spec_per_pin *per_pin, 1670 bool enable) 1671 { 1672 unsigned int param; 1673 1674 codec_dbg(codec, "HDMI: KAE %d cvt-NID=0x%x\n", enable, per_pin->cvt_nid); 1675 1676 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, AC_VERB_GET_DIGI_CONVERT_1, 0); 1677 param = (param >> 16) & 0xff; 1678 1679 if (enable) 1680 param |= AC_DIG3_KAE; 1681 else 1682 param &= ~AC_DIG3_KAE; 1683 1684 snd_hda_codec_write(codec, per_pin->cvt_nid, 0, AC_VERB_SET_DIGI_CONVERT_3, param); 1685 } 1686 1687 static void silent_stream_enable(struct hda_codec *codec, 1688 struct hdmi_spec_per_pin *per_pin) 1689 { 1690 struct hdmi_spec *spec = codec->spec; 1691 struct hdmi_spec_per_cvt *per_cvt; 1692 int cvt_idx, pin_idx, err; 1693 int keep_power = 0; 1694 1695 /* 1696 * Power-up will call hdmi_present_sense, so the PM calls 1697 * have to be done without mutex held. 1698 */ 1699 1700 err = snd_hda_power_up_pm(codec); 1701 if (err < 0 && err != -EACCES) { 1702 codec_err(codec, 1703 "Failed to power up codec for silent stream enable ret=[%d]\n", err); 1704 snd_hda_power_down_pm(codec); 1705 return; 1706 } 1707 1708 mutex_lock(&per_pin->lock); 1709 1710 if (per_pin->setup) { 1711 codec_dbg(codec, "hdmi: PCM already open, no silent stream\n"); 1712 err = -EBUSY; 1713 goto unlock_out; 1714 } 1715 1716 pin_idx = pin_id_to_pin_index(codec, per_pin->pin_nid, per_pin->dev_id); 1717 err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, true); 1718 if (err) { 1719 codec_err(codec, "hdmi: no free converter to enable silent mode\n"); 1720 goto unlock_out; 1721 } 1722 1723 per_cvt = get_cvt(spec, cvt_idx); 1724 per_cvt->silent_stream = true; 1725 per_pin->cvt_nid = per_cvt->cvt_nid; 1726 per_pin->silent_stream = true; 1727 1728 codec_dbg(codec, "hdmi: enabling silent stream pin-NID=0x%x cvt-NID=0x%x\n", 1729 per_pin->pin_nid, per_cvt->cvt_nid); 1730 1731 snd_hda_set_dev_select(codec, per_pin->pin_nid, per_pin->dev_id); 1732 snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0, 1733 AC_VERB_SET_CONNECT_SEL, 1734 per_pin->mux_idx); 1735 1736 /* configure unused pins to choose other converters */ 1737 pin_cvt_fixup(codec, per_pin, 0); 1738 1739 switch (spec->silent_stream_type) { 1740 case SILENT_STREAM_KAE: 1741 silent_stream_enable_i915(codec, per_pin); 1742 silent_stream_set_kae(codec, per_pin, true); 1743 break; 1744 case SILENT_STREAM_I915: 1745 silent_stream_enable_i915(codec, per_pin); 1746 keep_power = 1; 1747 break; 1748 default: 1749 break; 1750 } 1751 1752 unlock_out: 1753 mutex_unlock(&per_pin->lock); 1754 1755 if (err || !keep_power) 1756 snd_hda_power_down_pm(codec); 1757 } 1758 1759 static void silent_stream_disable(struct hda_codec *codec, 1760 struct hdmi_spec_per_pin *per_pin) 1761 { 1762 struct hdmi_spec *spec = codec->spec; 1763 struct hdmi_spec_per_cvt *per_cvt; 1764 int cvt_idx, err; 1765 1766 err = snd_hda_power_up_pm(codec); 1767 if (err < 0 && err != -EACCES) { 1768 codec_err(codec, 1769 "Failed to power up codec for silent stream disable ret=[%d]\n", 1770 err); 1771 snd_hda_power_down_pm(codec); 1772 return; 1773 } 1774 1775 mutex_lock(&per_pin->lock); 1776 if (!per_pin->silent_stream) 1777 goto unlock_out; 1778 1779 codec_dbg(codec, "HDMI: disable silent stream on pin-NID=0x%x cvt-NID=0x%x\n", 1780 per_pin->pin_nid, per_pin->cvt_nid); 1781 1782 cvt_idx = cvt_nid_to_cvt_index(codec, per_pin->cvt_nid); 1783 if (cvt_idx >= 0 && cvt_idx < spec->num_cvts) { 1784 per_cvt = get_cvt(spec, cvt_idx); 1785 per_cvt->silent_stream = false; 1786 } 1787 1788 if (spec->silent_stream_type == SILENT_STREAM_I915) { 1789 /* release ref taken in silent_stream_enable() */ 1790 snd_hda_power_down_pm(codec); 1791 } else if (spec->silent_stream_type == SILENT_STREAM_KAE) { 1792 silent_stream_set_kae(codec, per_pin, false); 1793 } 1794 1795 per_pin->cvt_nid = 0; 1796 per_pin->silent_stream = false; 1797 1798 unlock_out: 1799 mutex_unlock(&per_pin->lock); 1800 1801 snd_hda_power_down_pm(codec); 1802 } 1803 1804 /* update ELD and jack state via audio component */ 1805 static void sync_eld_via_acomp(struct hda_codec *codec, 1806 struct hdmi_spec_per_pin *per_pin) 1807 { 1808 struct hdmi_spec *spec = codec->spec; 1809 struct hdmi_eld *eld = &spec->temp_eld; 1810 bool monitor_prev, monitor_next; 1811 1812 mutex_lock(&per_pin->lock); 1813 eld->monitor_present = false; 1814 monitor_prev = per_pin->sink_eld.monitor_present; 1815 eld->eld_size = snd_hdac_acomp_get_eld(&codec->core, per_pin->pin_nid, 1816 per_pin->dev_id, &eld->monitor_present, 1817 eld->eld_buffer, ELD_MAX_SIZE); 1818 eld->eld_valid = (eld->eld_size > 0); 1819 update_eld(codec, per_pin, eld, 0); 1820 monitor_next = per_pin->sink_eld.monitor_present; 1821 mutex_unlock(&per_pin->lock); 1822 1823 if (spec->silent_stream_type) { 1824 if (!monitor_prev && monitor_next) 1825 silent_stream_enable(codec, per_pin); 1826 else if (monitor_prev && !monitor_next) 1827 silent_stream_disable(codec, per_pin); 1828 } 1829 } 1830 1831 static void hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll) 1832 { 1833 struct hda_codec *codec = per_pin->codec; 1834 1835 if (!codec_has_acomp(codec)) 1836 hdmi_present_sense_via_verbs(per_pin, repoll); 1837 else 1838 sync_eld_via_acomp(codec, per_pin); 1839 } 1840 1841 static void hdmi_repoll_eld(struct work_struct *work) 1842 { 1843 struct hdmi_spec_per_pin *per_pin = 1844 container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work); 1845 struct hda_codec *codec = per_pin->codec; 1846 struct hdmi_spec *spec = codec->spec; 1847 struct hda_jack_tbl *jack; 1848 1849 jack = snd_hda_jack_tbl_get_mst(codec, per_pin->pin_nid, 1850 per_pin->dev_id); 1851 if (jack) 1852 jack->jack_dirty = 1; 1853 1854 if (per_pin->repoll_count++ > 6) 1855 per_pin->repoll_count = 0; 1856 1857 mutex_lock(&spec->pcm_lock); 1858 hdmi_present_sense(per_pin, per_pin->repoll_count); 1859 mutex_unlock(&spec->pcm_lock); 1860 } 1861 1862 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid) 1863 { 1864 struct hdmi_spec *spec = codec->spec; 1865 unsigned int caps, config; 1866 int pin_idx; 1867 struct hdmi_spec_per_pin *per_pin; 1868 int err; 1869 int dev_num, i; 1870 1871 caps = snd_hda_query_pin_caps(codec, pin_nid); 1872 if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP))) 1873 return 0; 1874 1875 /* 1876 * For DP MST audio, Configuration Default is the same for 1877 * all device entries on the same pin 1878 */ 1879 config = snd_hda_codec_get_pincfg(codec, pin_nid); 1880 if (get_defcfg_connect(config) == AC_JACK_PORT_NONE && 1881 !spec->force_connect) 1882 return 0; 1883 1884 /* 1885 * To simplify the implementation, malloc all 1886 * the virtual pins in the initialization statically 1887 */ 1888 if (spec->intel_hsw_fixup) { 1889 /* 1890 * On Intel platforms, device entries count returned 1891 * by AC_PAR_DEVLIST_LEN is dynamic, and depends on 1892 * the type of receiver that is connected. Allocate pin 1893 * structures based on worst case. 1894 */ 1895 dev_num = spec->dev_num; 1896 } else if (codec->dp_mst) { 1897 dev_num = snd_hda_get_num_devices(codec, pin_nid) + 1; 1898 /* 1899 * spec->dev_num is the maxinum number of device entries 1900 * among all the pins 1901 */ 1902 spec->dev_num = (spec->dev_num > dev_num) ? 1903 spec->dev_num : dev_num; 1904 } else { 1905 /* 1906 * If the platform doesn't support DP MST, 1907 * manually set dev_num to 1. This means 1908 * the pin has only one device entry. 1909 */ 1910 dev_num = 1; 1911 spec->dev_num = 1; 1912 } 1913 1914 for (i = 0; i < dev_num; i++) { 1915 pin_idx = spec->num_pins; 1916 per_pin = snd_array_new(&spec->pins); 1917 1918 if (!per_pin) 1919 return -ENOMEM; 1920 1921 per_pin->pcm = NULL; 1922 per_pin->pcm_idx = -1; 1923 per_pin->pin_nid = pin_nid; 1924 per_pin->pin_nid_idx = spec->num_nids; 1925 per_pin->dev_id = i; 1926 per_pin->non_pcm = false; 1927 snd_hda_set_dev_select(codec, pin_nid, i); 1928 err = hdmi_read_pin_conn(codec, pin_idx); 1929 if (err < 0) 1930 return err; 1931 if (!is_jack_detectable(codec, pin_nid)) 1932 codec_warn(codec, "HDMI: pin NID 0x%x - jack not detectable\n", pin_nid); 1933 spec->num_pins++; 1934 } 1935 spec->num_nids++; 1936 1937 return 0; 1938 } 1939 1940 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 1941 { 1942 struct hdmi_spec *spec = codec->spec; 1943 struct hdmi_spec_per_cvt *per_cvt; 1944 unsigned int chans; 1945 int err; 1946 1947 chans = get_wcaps(codec, cvt_nid); 1948 chans = get_wcaps_channels(chans); 1949 1950 per_cvt = snd_array_new(&spec->cvts); 1951 if (!per_cvt) 1952 return -ENOMEM; 1953 1954 per_cvt->cvt_nid = cvt_nid; 1955 per_cvt->channels_min = 2; 1956 if (chans <= 16) { 1957 per_cvt->channels_max = chans; 1958 if (chans > spec->chmap.channels_max) 1959 spec->chmap.channels_max = chans; 1960 } 1961 1962 err = snd_hda_query_supported_pcm(codec, cvt_nid, 1963 &per_cvt->rates, 1964 &per_cvt->formats, 1965 &per_cvt->maxbps); 1966 if (err < 0) 1967 return err; 1968 1969 if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids)) 1970 spec->cvt_nids[spec->num_cvts] = cvt_nid; 1971 spec->num_cvts++; 1972 1973 return 0; 1974 } 1975 1976 static const struct snd_pci_quirk force_connect_list[] = { 1977 SND_PCI_QUIRK(0x103c, 0x870f, "HP", 1), 1978 SND_PCI_QUIRK(0x103c, 0x871a, "HP", 1), 1979 SND_PCI_QUIRK(0x103c, 0x8711, "HP", 1), 1980 SND_PCI_QUIRK(0x1462, 0xec94, "MS-7C94", 1), 1981 SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", 1), 1982 {} 1983 }; 1984 1985 static int hdmi_parse_codec(struct hda_codec *codec) 1986 { 1987 struct hdmi_spec *spec = codec->spec; 1988 hda_nid_t start_nid; 1989 unsigned int caps; 1990 int i, nodes; 1991 const struct snd_pci_quirk *q; 1992 1993 nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &start_nid); 1994 if (!start_nid || nodes < 0) { 1995 codec_warn(codec, "HDMI: failed to get afg sub nodes\n"); 1996 return -EINVAL; 1997 } 1998 1999 if (enable_all_pins) 2000 spec->force_connect = true; 2001 2002 q = snd_pci_quirk_lookup(codec->bus->pci, force_connect_list); 2003 2004 if (q && q->value) 2005 spec->force_connect = true; 2006 2007 /* 2008 * hdmi_add_pin() assumes total amount of converters to 2009 * be known, so first discover all converters 2010 */ 2011 for (i = 0; i < nodes; i++) { 2012 hda_nid_t nid = start_nid + i; 2013 2014 caps = get_wcaps(codec, nid); 2015 2016 if (!(caps & AC_WCAP_DIGITAL)) 2017 continue; 2018 2019 if (get_wcaps_type(caps) == AC_WID_AUD_OUT) 2020 hdmi_add_cvt(codec, nid); 2021 } 2022 2023 /* discover audio pins */ 2024 for (i = 0; i < nodes; i++) { 2025 hda_nid_t nid = start_nid + i; 2026 2027 caps = get_wcaps(codec, nid); 2028 2029 if (!(caps & AC_WCAP_DIGITAL)) 2030 continue; 2031 2032 if (get_wcaps_type(caps) == AC_WID_PIN) 2033 hdmi_add_pin(codec, nid); 2034 } 2035 2036 return 0; 2037 } 2038 2039 /* 2040 */ 2041 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid) 2042 { 2043 struct hda_spdif_out *spdif; 2044 bool non_pcm; 2045 2046 mutex_lock(&codec->spdif_mutex); 2047 spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid); 2048 /* Add sanity check to pass klockwork check. 2049 * This should never happen. 2050 */ 2051 if (WARN_ON(spdif == NULL)) { 2052 mutex_unlock(&codec->spdif_mutex); 2053 return true; 2054 } 2055 non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO); 2056 mutex_unlock(&codec->spdif_mutex); 2057 return non_pcm; 2058 } 2059 2060 /* 2061 * HDMI callbacks 2062 */ 2063 2064 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 2065 struct hda_codec *codec, 2066 unsigned int stream_tag, 2067 unsigned int format, 2068 struct snd_pcm_substream *substream) 2069 { 2070 hda_nid_t cvt_nid = hinfo->nid; 2071 struct hdmi_spec *spec = codec->spec; 2072 int pin_idx; 2073 struct hdmi_spec_per_pin *per_pin; 2074 struct snd_pcm_runtime *runtime = substream->runtime; 2075 bool non_pcm; 2076 int pinctl, stripe; 2077 int err = 0; 2078 2079 mutex_lock(&spec->pcm_lock); 2080 pin_idx = hinfo_to_pin_index(codec, hinfo); 2081 if (pin_idx < 0) { 2082 /* when pcm is not bound to a pin skip pin setup and return 0 2083 * to make audio playback be ongoing 2084 */ 2085 pin_cvt_fixup(codec, NULL, cvt_nid); 2086 snd_hda_codec_setup_stream(codec, cvt_nid, 2087 stream_tag, 0, format); 2088 goto unlock; 2089 } 2090 2091 if (snd_BUG_ON(pin_idx < 0)) { 2092 err = -EINVAL; 2093 goto unlock; 2094 } 2095 per_pin = get_pin(spec, pin_idx); 2096 2097 /* Verify pin:cvt selections to avoid silent audio after S3. 2098 * After S3, the audio driver restores pin:cvt selections 2099 * but this can happen before gfx is ready and such selection 2100 * is overlooked by HW. Thus multiple pins can share a same 2101 * default convertor and mute control will affect each other, 2102 * which can cause a resumed audio playback become silent 2103 * after S3. 2104 */ 2105 pin_cvt_fixup(codec, per_pin, 0); 2106 2107 /* Call sync_audio_rate to set the N/CTS/M manually if necessary */ 2108 /* Todo: add DP1.2 MST audio support later */ 2109 if (codec_has_acomp(codec)) 2110 snd_hdac_sync_audio_rate(&codec->core, per_pin->pin_nid, 2111 per_pin->dev_id, runtime->rate); 2112 2113 non_pcm = check_non_pcm_per_cvt(codec, cvt_nid); 2114 mutex_lock(&per_pin->lock); 2115 per_pin->channels = substream->runtime->channels; 2116 per_pin->setup = true; 2117 2118 if (get_wcaps(codec, cvt_nid) & AC_WCAP_STRIPE) { 2119 stripe = snd_hdac_get_stream_stripe_ctl(&codec->bus->core, 2120 substream); 2121 snd_hda_codec_write(codec, cvt_nid, 0, 2122 AC_VERB_SET_STRIPE_CONTROL, 2123 stripe); 2124 } 2125 2126 hdmi_setup_audio_infoframe(codec, per_pin, non_pcm); 2127 mutex_unlock(&per_pin->lock); 2128 if (spec->dyn_pin_out) { 2129 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2130 per_pin->dev_id); 2131 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2132 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2133 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2134 AC_VERB_SET_PIN_WIDGET_CONTROL, 2135 pinctl | PIN_OUT); 2136 } 2137 2138 /* snd_hda_set_dev_select() has been called before */ 2139 err = spec->ops.setup_stream(codec, cvt_nid, per_pin->pin_nid, 2140 per_pin->dev_id, stream_tag, format); 2141 unlock: 2142 mutex_unlock(&spec->pcm_lock); 2143 return err; 2144 } 2145 2146 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo, 2147 struct hda_codec *codec, 2148 struct snd_pcm_substream *substream) 2149 { 2150 snd_hda_codec_cleanup_stream(codec, hinfo->nid); 2151 return 0; 2152 } 2153 2154 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo, 2155 struct hda_codec *codec, 2156 struct snd_pcm_substream *substream) 2157 { 2158 struct hdmi_spec *spec = codec->spec; 2159 int cvt_idx, pin_idx, pcm_idx; 2160 struct hdmi_spec_per_cvt *per_cvt; 2161 struct hdmi_spec_per_pin *per_pin; 2162 int pinctl; 2163 int err = 0; 2164 2165 mutex_lock(&spec->pcm_lock); 2166 if (hinfo->nid) { 2167 pcm_idx = hinfo_to_pcm_index(codec, hinfo); 2168 if (snd_BUG_ON(pcm_idx < 0)) { 2169 err = -EINVAL; 2170 goto unlock; 2171 } 2172 cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid); 2173 if (snd_BUG_ON(cvt_idx < 0)) { 2174 err = -EINVAL; 2175 goto unlock; 2176 } 2177 per_cvt = get_cvt(spec, cvt_idx); 2178 per_cvt->assigned = false; 2179 hinfo->nid = 0; 2180 2181 azx_stream(get_azx_dev(substream))->stripe = 0; 2182 2183 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2184 clear_bit(pcm_idx, &spec->pcm_in_use); 2185 pin_idx = hinfo_to_pin_index(codec, hinfo); 2186 if (pin_idx < 0) 2187 goto unlock; 2188 2189 if (snd_BUG_ON(pin_idx < 0)) { 2190 err = -EINVAL; 2191 goto unlock; 2192 } 2193 per_pin = get_pin(spec, pin_idx); 2194 2195 if (spec->dyn_pin_out) { 2196 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2197 per_pin->dev_id); 2198 pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0, 2199 AC_VERB_GET_PIN_WIDGET_CONTROL, 0); 2200 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 2201 AC_VERB_SET_PIN_WIDGET_CONTROL, 2202 pinctl & ~PIN_OUT); 2203 } 2204 2205 mutex_lock(&per_pin->lock); 2206 per_pin->chmap_set = false; 2207 memset(per_pin->chmap, 0, sizeof(per_pin->chmap)); 2208 2209 per_pin->setup = false; 2210 per_pin->channels = 0; 2211 mutex_unlock(&per_pin->lock); 2212 } 2213 2214 unlock: 2215 mutex_unlock(&spec->pcm_lock); 2216 2217 return err; 2218 } 2219 2220 static const struct hda_pcm_ops generic_ops = { 2221 .open = hdmi_pcm_open, 2222 .close = hdmi_pcm_close, 2223 .prepare = generic_hdmi_playback_pcm_prepare, 2224 .cleanup = generic_hdmi_playback_pcm_cleanup, 2225 }; 2226 2227 static int hdmi_get_spk_alloc(struct hdac_device *hdac, int pcm_idx) 2228 { 2229 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2230 struct hdmi_spec *spec = codec->spec; 2231 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2232 2233 if (!per_pin) 2234 return 0; 2235 2236 return per_pin->sink_eld.info.spk_alloc; 2237 } 2238 2239 static void hdmi_get_chmap(struct hdac_device *hdac, int pcm_idx, 2240 unsigned char *chmap) 2241 { 2242 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2243 struct hdmi_spec *spec = codec->spec; 2244 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2245 2246 /* chmap is already set to 0 in caller */ 2247 if (!per_pin) 2248 return; 2249 2250 memcpy(chmap, per_pin->chmap, ARRAY_SIZE(per_pin->chmap)); 2251 } 2252 2253 static void hdmi_set_chmap(struct hdac_device *hdac, int pcm_idx, 2254 unsigned char *chmap, int prepared) 2255 { 2256 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2257 struct hdmi_spec *spec = codec->spec; 2258 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2259 2260 if (!per_pin) 2261 return; 2262 mutex_lock(&per_pin->lock); 2263 per_pin->chmap_set = true; 2264 memcpy(per_pin->chmap, chmap, ARRAY_SIZE(per_pin->chmap)); 2265 if (prepared) 2266 hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm); 2267 mutex_unlock(&per_pin->lock); 2268 } 2269 2270 static bool is_hdmi_pcm_attached(struct hdac_device *hdac, int pcm_idx) 2271 { 2272 struct hda_codec *codec = hdac_to_hda_codec(hdac); 2273 struct hdmi_spec *spec = codec->spec; 2274 struct hdmi_spec_per_pin *per_pin = pcm_idx_to_pin(spec, pcm_idx); 2275 2276 return per_pin ? true:false; 2277 } 2278 2279 static int generic_hdmi_build_pcms(struct hda_codec *codec) 2280 { 2281 struct hdmi_spec *spec = codec->spec; 2282 int idx, pcm_num; 2283 2284 /* limit the PCM devices to the codec converters */ 2285 pcm_num = spec->num_cvts; 2286 codec_dbg(codec, "hdmi: pcm_num set to %d\n", pcm_num); 2287 2288 for (idx = 0; idx < pcm_num; idx++) { 2289 struct hda_pcm *info; 2290 struct hda_pcm_stream *pstr; 2291 2292 info = snd_hda_codec_pcm_new(codec, "HDMI %d", idx); 2293 if (!info) 2294 return -ENOMEM; 2295 2296 spec->pcm_rec[idx].pcm = info; 2297 spec->pcm_used++; 2298 info->pcm_type = HDA_PCM_TYPE_HDMI; 2299 info->own_chmap = true; 2300 2301 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 2302 pstr->substreams = 1; 2303 pstr->ops = generic_ops; 2304 /* pcm number is less than pcm_rec array size */ 2305 if (spec->pcm_used >= ARRAY_SIZE(spec->pcm_rec)) 2306 break; 2307 /* other pstr fields are set in open */ 2308 } 2309 2310 return 0; 2311 } 2312 2313 static void free_hdmi_jack_priv(struct snd_jack *jack) 2314 { 2315 struct hdmi_pcm *pcm = jack->private_data; 2316 2317 pcm->jack = NULL; 2318 } 2319 2320 static int generic_hdmi_build_jack(struct hda_codec *codec, int pcm_idx) 2321 { 2322 char hdmi_str[32] = "HDMI/DP"; 2323 struct hdmi_spec *spec = codec->spec; 2324 struct snd_jack *jack; 2325 int pcmdev = get_pcm_rec(spec, pcm_idx)->device; 2326 int err; 2327 2328 if (pcmdev > 0) 2329 sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev); 2330 2331 err = snd_jack_new(codec->card, hdmi_str, SND_JACK_AVOUT, &jack, 2332 true, false); 2333 if (err < 0) 2334 return err; 2335 2336 spec->pcm_rec[pcm_idx].jack = jack; 2337 jack->private_data = &spec->pcm_rec[pcm_idx]; 2338 jack->private_free = free_hdmi_jack_priv; 2339 return 0; 2340 } 2341 2342 static int generic_hdmi_build_controls(struct hda_codec *codec) 2343 { 2344 struct hdmi_spec *spec = codec->spec; 2345 int dev, err; 2346 int pin_idx, pcm_idx; 2347 2348 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2349 if (!get_pcm_rec(spec, pcm_idx)->pcm) { 2350 /* no PCM: mark this for skipping permanently */ 2351 set_bit(pcm_idx, &spec->pcm_bitmap); 2352 continue; 2353 } 2354 2355 err = generic_hdmi_build_jack(codec, pcm_idx); 2356 if (err < 0) 2357 return err; 2358 2359 /* create the spdif for each pcm 2360 * pin will be bound when monitor is connected 2361 */ 2362 err = snd_hda_create_dig_out_ctls(codec, 2363 0, spec->cvt_nids[0], 2364 HDA_PCM_TYPE_HDMI); 2365 if (err < 0) 2366 return err; 2367 snd_hda_spdif_ctls_unassign(codec, pcm_idx); 2368 2369 dev = get_pcm_rec(spec, pcm_idx)->device; 2370 if (dev != SNDRV_PCM_INVALID_DEVICE) { 2371 /* add control for ELD Bytes */ 2372 err = hdmi_create_eld_ctl(codec, pcm_idx, dev); 2373 if (err < 0) 2374 return err; 2375 } 2376 } 2377 2378 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2379 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2380 struct hdmi_eld *pin_eld = &per_pin->sink_eld; 2381 2382 pin_eld->eld_valid = false; 2383 hdmi_present_sense(per_pin, 0); 2384 } 2385 2386 /* add channel maps */ 2387 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2388 struct hda_pcm *pcm; 2389 2390 pcm = get_pcm_rec(spec, pcm_idx); 2391 if (!pcm || !pcm->pcm) 2392 break; 2393 err = snd_hdac_add_chmap_ctls(pcm->pcm, pcm_idx, &spec->chmap); 2394 if (err < 0) 2395 return err; 2396 } 2397 2398 return 0; 2399 } 2400 2401 static int generic_hdmi_init_per_pins(struct hda_codec *codec) 2402 { 2403 struct hdmi_spec *spec = codec->spec; 2404 int pin_idx; 2405 2406 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2407 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2408 2409 per_pin->codec = codec; 2410 mutex_init(&per_pin->lock); 2411 INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld); 2412 eld_proc_new(per_pin, pin_idx); 2413 } 2414 return 0; 2415 } 2416 2417 static int generic_hdmi_init(struct hda_codec *codec) 2418 { 2419 struct hdmi_spec *spec = codec->spec; 2420 int pin_idx; 2421 2422 mutex_lock(&spec->bind_lock); 2423 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2424 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2425 hda_nid_t pin_nid = per_pin->pin_nid; 2426 int dev_id = per_pin->dev_id; 2427 2428 snd_hda_set_dev_select(codec, pin_nid, dev_id); 2429 hdmi_init_pin(codec, pin_nid); 2430 if (codec_has_acomp(codec)) 2431 continue; 2432 snd_hda_jack_detect_enable_callback_mst(codec, pin_nid, dev_id, 2433 jack_callback); 2434 } 2435 mutex_unlock(&spec->bind_lock); 2436 return 0; 2437 } 2438 2439 static void hdmi_array_init(struct hdmi_spec *spec, int nums) 2440 { 2441 snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums); 2442 snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums); 2443 } 2444 2445 static void hdmi_array_free(struct hdmi_spec *spec) 2446 { 2447 snd_array_free(&spec->pins); 2448 snd_array_free(&spec->cvts); 2449 } 2450 2451 static void generic_spec_free(struct hda_codec *codec) 2452 { 2453 struct hdmi_spec *spec = codec->spec; 2454 2455 if (spec) { 2456 hdmi_array_free(spec); 2457 kfree(spec); 2458 codec->spec = NULL; 2459 } 2460 codec->dp_mst = false; 2461 } 2462 2463 static void generic_hdmi_free(struct hda_codec *codec) 2464 { 2465 struct hdmi_spec *spec = codec->spec; 2466 int pin_idx, pcm_idx; 2467 2468 if (spec->acomp_registered) { 2469 snd_hdac_acomp_exit(&codec->bus->core); 2470 } else if (codec_has_acomp(codec)) { 2471 snd_hdac_acomp_register_notifier(&codec->bus->core, NULL); 2472 } 2473 codec->relaxed_resume = 0; 2474 2475 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2476 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2477 cancel_delayed_work_sync(&per_pin->work); 2478 eld_proc_free(per_pin); 2479 } 2480 2481 for (pcm_idx = 0; pcm_idx < spec->pcm_used; pcm_idx++) { 2482 if (spec->pcm_rec[pcm_idx].jack == NULL) 2483 continue; 2484 snd_device_free(codec->card, spec->pcm_rec[pcm_idx].jack); 2485 } 2486 2487 generic_spec_free(codec); 2488 } 2489 2490 #ifdef CONFIG_PM 2491 static int generic_hdmi_suspend(struct hda_codec *codec) 2492 { 2493 struct hdmi_spec *spec = codec->spec; 2494 int pin_idx; 2495 2496 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2497 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2498 cancel_delayed_work_sync(&per_pin->work); 2499 } 2500 return 0; 2501 } 2502 2503 static int generic_hdmi_resume(struct hda_codec *codec) 2504 { 2505 struct hdmi_spec *spec = codec->spec; 2506 int pin_idx; 2507 2508 codec->patch_ops.init(codec); 2509 snd_hda_regmap_sync(codec); 2510 2511 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2512 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2513 hdmi_present_sense(per_pin, 1); 2514 } 2515 return 0; 2516 } 2517 #endif 2518 2519 static const struct hda_codec_ops generic_hdmi_patch_ops = { 2520 .init = generic_hdmi_init, 2521 .free = generic_hdmi_free, 2522 .build_pcms = generic_hdmi_build_pcms, 2523 .build_controls = generic_hdmi_build_controls, 2524 .unsol_event = hdmi_unsol_event, 2525 #ifdef CONFIG_PM 2526 .suspend = generic_hdmi_suspend, 2527 .resume = generic_hdmi_resume, 2528 #endif 2529 }; 2530 2531 static const struct hdmi_ops generic_standard_hdmi_ops = { 2532 .pin_get_eld = hdmi_pin_get_eld, 2533 .pin_setup_infoframe = hdmi_pin_setup_infoframe, 2534 .pin_hbr_setup = hdmi_pin_hbr_setup, 2535 .setup_stream = hdmi_setup_stream, 2536 }; 2537 2538 /* allocate codec->spec and assign/initialize generic parser ops */ 2539 static int alloc_generic_hdmi(struct hda_codec *codec) 2540 { 2541 struct hdmi_spec *spec; 2542 2543 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 2544 if (!spec) 2545 return -ENOMEM; 2546 2547 spec->codec = codec; 2548 spec->ops = generic_standard_hdmi_ops; 2549 spec->dev_num = 1; /* initialize to 1 */ 2550 mutex_init(&spec->pcm_lock); 2551 mutex_init(&spec->bind_lock); 2552 snd_hdac_register_chmap_ops(&codec->core, &spec->chmap); 2553 2554 spec->chmap.ops.get_chmap = hdmi_get_chmap; 2555 spec->chmap.ops.set_chmap = hdmi_set_chmap; 2556 spec->chmap.ops.is_pcm_attached = is_hdmi_pcm_attached; 2557 spec->chmap.ops.get_spk_alloc = hdmi_get_spk_alloc; 2558 2559 codec->spec = spec; 2560 hdmi_array_init(spec, 4); 2561 2562 codec->patch_ops = generic_hdmi_patch_ops; 2563 2564 return 0; 2565 } 2566 2567 /* generic HDMI parser */ 2568 static int patch_generic_hdmi(struct hda_codec *codec) 2569 { 2570 int err; 2571 2572 err = alloc_generic_hdmi(codec); 2573 if (err < 0) 2574 return err; 2575 2576 err = hdmi_parse_codec(codec); 2577 if (err < 0) { 2578 generic_spec_free(codec); 2579 return err; 2580 } 2581 2582 generic_hdmi_init_per_pins(codec); 2583 return 0; 2584 } 2585 2586 /* 2587 * generic audio component binding 2588 */ 2589 2590 /* turn on / off the unsol event jack detection dynamically */ 2591 static void reprogram_jack_detect(struct hda_codec *codec, hda_nid_t nid, 2592 int dev_id, bool use_acomp) 2593 { 2594 struct hda_jack_tbl *tbl; 2595 2596 tbl = snd_hda_jack_tbl_get_mst(codec, nid, dev_id); 2597 if (tbl) { 2598 /* clear unsol even if component notifier is used, or re-enable 2599 * if notifier is cleared 2600 */ 2601 unsigned int val = use_acomp ? 0 : (AC_USRSP_EN | tbl->tag); 2602 snd_hda_codec_write_cache(codec, nid, 0, 2603 AC_VERB_SET_UNSOLICITED_ENABLE, val); 2604 } 2605 } 2606 2607 /* set up / clear component notifier dynamically */ 2608 static void generic_acomp_notifier_set(struct drm_audio_component *acomp, 2609 bool use_acomp) 2610 { 2611 struct hdmi_spec *spec; 2612 int i; 2613 2614 spec = container_of(acomp->audio_ops, struct hdmi_spec, drm_audio_ops); 2615 mutex_lock(&spec->bind_lock); 2616 spec->use_acomp_notifier = use_acomp; 2617 spec->codec->relaxed_resume = use_acomp; 2618 spec->codec->bus->keep_power = 0; 2619 /* reprogram each jack detection logic depending on the notifier */ 2620 for (i = 0; i < spec->num_pins; i++) 2621 reprogram_jack_detect(spec->codec, 2622 get_pin(spec, i)->pin_nid, 2623 get_pin(spec, i)->dev_id, 2624 use_acomp); 2625 mutex_unlock(&spec->bind_lock); 2626 } 2627 2628 /* enable / disable the notifier via master bind / unbind */ 2629 static int generic_acomp_master_bind(struct device *dev, 2630 struct drm_audio_component *acomp) 2631 { 2632 generic_acomp_notifier_set(acomp, true); 2633 return 0; 2634 } 2635 2636 static void generic_acomp_master_unbind(struct device *dev, 2637 struct drm_audio_component *acomp) 2638 { 2639 generic_acomp_notifier_set(acomp, false); 2640 } 2641 2642 /* check whether both HD-audio and DRM PCI devices belong to the same bus */ 2643 static int match_bound_vga(struct device *dev, int subtype, void *data) 2644 { 2645 struct hdac_bus *bus = data; 2646 struct pci_dev *pci, *master; 2647 2648 if (!dev_is_pci(dev) || !dev_is_pci(bus->dev)) 2649 return 0; 2650 master = to_pci_dev(bus->dev); 2651 pci = to_pci_dev(dev); 2652 return master->bus == pci->bus; 2653 } 2654 2655 /* audio component notifier for AMD/Nvidia HDMI codecs */ 2656 static void generic_acomp_pin_eld_notify(void *audio_ptr, int port, int dev_id) 2657 { 2658 struct hda_codec *codec = audio_ptr; 2659 struct hdmi_spec *spec = codec->spec; 2660 hda_nid_t pin_nid = spec->port2pin(codec, port); 2661 2662 if (!pin_nid) 2663 return; 2664 if (get_wcaps_type(get_wcaps(codec, pin_nid)) != AC_WID_PIN) 2665 return; 2666 /* skip notification during system suspend (but not in runtime PM); 2667 * the state will be updated at resume 2668 */ 2669 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2670 return; 2671 2672 check_presence_and_report(codec, pin_nid, dev_id); 2673 } 2674 2675 /* set up the private drm_audio_ops from the template */ 2676 static void setup_drm_audio_ops(struct hda_codec *codec, 2677 const struct drm_audio_component_audio_ops *ops) 2678 { 2679 struct hdmi_spec *spec = codec->spec; 2680 2681 spec->drm_audio_ops.audio_ptr = codec; 2682 /* intel_audio_codec_enable() or intel_audio_codec_disable() 2683 * will call pin_eld_notify with using audio_ptr pointer 2684 * We need make sure audio_ptr is really setup 2685 */ 2686 wmb(); 2687 spec->drm_audio_ops.pin2port = ops->pin2port; 2688 spec->drm_audio_ops.pin_eld_notify = ops->pin_eld_notify; 2689 spec->drm_audio_ops.master_bind = ops->master_bind; 2690 spec->drm_audio_ops.master_unbind = ops->master_unbind; 2691 } 2692 2693 /* initialize the generic HDMI audio component */ 2694 static void generic_acomp_init(struct hda_codec *codec, 2695 const struct drm_audio_component_audio_ops *ops, 2696 int (*port2pin)(struct hda_codec *, int)) 2697 { 2698 struct hdmi_spec *spec = codec->spec; 2699 2700 if (!enable_acomp) { 2701 codec_info(codec, "audio component disabled by module option\n"); 2702 return; 2703 } 2704 2705 spec->port2pin = port2pin; 2706 setup_drm_audio_ops(codec, ops); 2707 if (!snd_hdac_acomp_init(&codec->bus->core, &spec->drm_audio_ops, 2708 match_bound_vga, 0)) { 2709 spec->acomp_registered = true; 2710 } 2711 } 2712 2713 /* 2714 * Intel codec parsers and helpers 2715 */ 2716 2717 #define INTEL_GET_VENDOR_VERB 0xf81 2718 #define INTEL_SET_VENDOR_VERB 0x781 2719 #define INTEL_EN_DP12 0x02 /* enable DP 1.2 features */ 2720 #define INTEL_EN_ALL_PIN_CVTS 0x01 /* enable 2nd & 3rd pins and convertors */ 2721 2722 static void intel_haswell_enable_all_pins(struct hda_codec *codec, 2723 bool update_tree) 2724 { 2725 unsigned int vendor_param; 2726 struct hdmi_spec *spec = codec->spec; 2727 2728 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2729 INTEL_GET_VENDOR_VERB, 0); 2730 if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS) 2731 return; 2732 2733 vendor_param |= INTEL_EN_ALL_PIN_CVTS; 2734 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2735 INTEL_SET_VENDOR_VERB, vendor_param); 2736 if (vendor_param == -1) 2737 return; 2738 2739 if (update_tree) 2740 snd_hda_codec_update_widgets(codec); 2741 } 2742 2743 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec) 2744 { 2745 unsigned int vendor_param; 2746 struct hdmi_spec *spec = codec->spec; 2747 2748 vendor_param = snd_hda_codec_read(codec, spec->vendor_nid, 0, 2749 INTEL_GET_VENDOR_VERB, 0); 2750 if (vendor_param == -1 || vendor_param & INTEL_EN_DP12) 2751 return; 2752 2753 /* enable DP1.2 mode */ 2754 vendor_param |= INTEL_EN_DP12; 2755 snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB); 2756 snd_hda_codec_write_cache(codec, spec->vendor_nid, 0, 2757 INTEL_SET_VENDOR_VERB, vendor_param); 2758 } 2759 2760 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0. 2761 * Otherwise you may get severe h/w communication errors. 2762 */ 2763 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg, 2764 unsigned int power_state) 2765 { 2766 if (power_state == AC_PWRST_D0) { 2767 intel_haswell_enable_all_pins(codec, false); 2768 intel_haswell_fixup_enable_dp12(codec); 2769 } 2770 2771 snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state); 2772 snd_hda_codec_set_power_to_all(codec, fg, power_state); 2773 } 2774 2775 /* There is a fixed mapping between audio pin node and display port. 2776 * on SNB, IVY, HSW, BSW, SKL, BXT, KBL: 2777 * Pin Widget 5 - PORT B (port = 1 in i915 driver) 2778 * Pin Widget 6 - PORT C (port = 2 in i915 driver) 2779 * Pin Widget 7 - PORT D (port = 3 in i915 driver) 2780 * 2781 * on VLV, ILK: 2782 * Pin Widget 4 - PORT B (port = 1 in i915 driver) 2783 * Pin Widget 5 - PORT C (port = 2 in i915 driver) 2784 * Pin Widget 6 - PORT D (port = 3 in i915 driver) 2785 */ 2786 static int intel_base_nid(struct hda_codec *codec) 2787 { 2788 switch (codec->core.vendor_id) { 2789 case 0x80860054: /* ILK */ 2790 case 0x80862804: /* ILK */ 2791 case 0x80862882: /* VLV */ 2792 return 4; 2793 default: 2794 return 5; 2795 } 2796 } 2797 2798 static int intel_pin2port(void *audio_ptr, int pin_nid) 2799 { 2800 struct hda_codec *codec = audio_ptr; 2801 struct hdmi_spec *spec = codec->spec; 2802 int base_nid, i; 2803 2804 if (!spec->port_num) { 2805 base_nid = intel_base_nid(codec); 2806 if (WARN_ON(pin_nid < base_nid || pin_nid >= base_nid + 3)) 2807 return -1; 2808 return pin_nid - base_nid + 1; 2809 } 2810 2811 /* 2812 * looking for the pin number in the mapping table and return 2813 * the index which indicate the port number 2814 */ 2815 for (i = 0; i < spec->port_num; i++) { 2816 if (pin_nid == spec->port_map[i]) 2817 return i; 2818 } 2819 2820 codec_info(codec, "Can't find the HDMI/DP port for pin NID 0x%x\n", pin_nid); 2821 return -1; 2822 } 2823 2824 static int intel_port2pin(struct hda_codec *codec, int port) 2825 { 2826 struct hdmi_spec *spec = codec->spec; 2827 2828 if (!spec->port_num) { 2829 /* we assume only from port-B to port-D */ 2830 if (port < 1 || port > 3) 2831 return 0; 2832 return port + intel_base_nid(codec) - 1; 2833 } 2834 2835 if (port < 0 || port >= spec->port_num) 2836 return 0; 2837 return spec->port_map[port]; 2838 } 2839 2840 static void intel_pin_eld_notify(void *audio_ptr, int port, int pipe) 2841 { 2842 struct hda_codec *codec = audio_ptr; 2843 int pin_nid; 2844 int dev_id = pipe; 2845 2846 pin_nid = intel_port2pin(codec, port); 2847 if (!pin_nid) 2848 return; 2849 /* skip notification during system suspend (but not in runtime PM); 2850 * the state will be updated at resume 2851 */ 2852 if (codec->core.dev.power.power_state.event == PM_EVENT_SUSPEND) 2853 return; 2854 2855 snd_hdac_i915_set_bclk(&codec->bus->core); 2856 check_presence_and_report(codec, pin_nid, dev_id); 2857 } 2858 2859 static const struct drm_audio_component_audio_ops intel_audio_ops = { 2860 .pin2port = intel_pin2port, 2861 .pin_eld_notify = intel_pin_eld_notify, 2862 }; 2863 2864 /* register i915 component pin_eld_notify callback */ 2865 static void register_i915_notifier(struct hda_codec *codec) 2866 { 2867 struct hdmi_spec *spec = codec->spec; 2868 2869 spec->use_acomp_notifier = true; 2870 spec->port2pin = intel_port2pin; 2871 setup_drm_audio_ops(codec, &intel_audio_ops); 2872 snd_hdac_acomp_register_notifier(&codec->bus->core, 2873 &spec->drm_audio_ops); 2874 /* no need for forcible resume for jack check thanks to notifier */ 2875 codec->relaxed_resume = 1; 2876 } 2877 2878 /* setup_stream ops override for HSW+ */ 2879 static int i915_hsw_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 2880 hda_nid_t pin_nid, int dev_id, u32 stream_tag, 2881 int format) 2882 { 2883 struct hdmi_spec *spec = codec->spec; 2884 int pin_idx = pin_id_to_pin_index(codec, pin_nid, dev_id); 2885 struct hdmi_spec_per_pin *per_pin; 2886 int res; 2887 2888 if (pin_idx < 0) 2889 per_pin = NULL; 2890 else 2891 per_pin = get_pin(spec, pin_idx); 2892 2893 haswell_verify_D0(codec, cvt_nid, pin_nid); 2894 2895 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2896 silent_stream_set_kae(codec, per_pin, false); 2897 /* wait for pending transfers in codec to clear */ 2898 usleep_range(100, 200); 2899 } 2900 2901 res = hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 2902 stream_tag, format); 2903 2904 if (spec->silent_stream_type == SILENT_STREAM_KAE && per_pin && per_pin->silent_stream) { 2905 usleep_range(100, 200); 2906 silent_stream_set_kae(codec, per_pin, true); 2907 } 2908 2909 return res; 2910 } 2911 2912 /* pin_cvt_fixup ops override for HSW+ and VLV+ */ 2913 static void i915_pin_cvt_fixup(struct hda_codec *codec, 2914 struct hdmi_spec_per_pin *per_pin, 2915 hda_nid_t cvt_nid) 2916 { 2917 if (per_pin) { 2918 haswell_verify_D0(codec, per_pin->cvt_nid, per_pin->pin_nid); 2919 snd_hda_set_dev_select(codec, per_pin->pin_nid, 2920 per_pin->dev_id); 2921 intel_verify_pin_cvt_connect(codec, per_pin); 2922 intel_not_share_assigned_cvt(codec, per_pin->pin_nid, 2923 per_pin->dev_id, per_pin->mux_idx); 2924 } else { 2925 intel_not_share_assigned_cvt_nid(codec, 0, 0, cvt_nid); 2926 } 2927 } 2928 2929 #ifdef CONFIG_PM 2930 static int i915_adlp_hdmi_suspend(struct hda_codec *codec) 2931 { 2932 struct hdmi_spec *spec = codec->spec; 2933 bool silent_streams = false; 2934 int pin_idx, res; 2935 2936 res = generic_hdmi_suspend(codec); 2937 2938 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2939 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2940 2941 if (per_pin->silent_stream) { 2942 silent_streams = true; 2943 break; 2944 } 2945 } 2946 2947 if (silent_streams && spec->silent_stream_type == SILENT_STREAM_KAE) { 2948 /* 2949 * stream-id should remain programmed when codec goes 2950 * to runtime suspend 2951 */ 2952 codec->no_stream_clean_at_suspend = 1; 2953 2954 /* 2955 * the system might go to S3, in which case keep-alive 2956 * must be reprogrammed upon resume 2957 */ 2958 codec->forced_resume = 1; 2959 2960 codec_dbg(codec, "HDMI: KAE active at suspend\n"); 2961 } else { 2962 codec->no_stream_clean_at_suspend = 0; 2963 codec->forced_resume = 0; 2964 } 2965 2966 return res; 2967 } 2968 2969 static int i915_adlp_hdmi_resume(struct hda_codec *codec) 2970 { 2971 struct hdmi_spec *spec = codec->spec; 2972 int pin_idx, res; 2973 2974 res = generic_hdmi_resume(codec); 2975 2976 /* KAE not programmed at suspend, nothing to do here */ 2977 if (!codec->no_stream_clean_at_suspend) 2978 return res; 2979 2980 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 2981 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 2982 2983 /* 2984 * If system was in suspend with monitor connected, 2985 * the codec setting may have been lost. Re-enable 2986 * keep-alive. 2987 */ 2988 if (per_pin->silent_stream) { 2989 unsigned int param; 2990 2991 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 2992 AC_VERB_GET_CONV, 0); 2993 if (!param) { 2994 codec_dbg(codec, "HDMI: KAE: restore stream id\n"); 2995 silent_stream_enable_i915(codec, per_pin); 2996 } 2997 2998 param = snd_hda_codec_read(codec, per_pin->cvt_nid, 0, 2999 AC_VERB_GET_DIGI_CONVERT_1, 0); 3000 if (!(param & (AC_DIG3_KAE << 16))) { 3001 codec_dbg(codec, "HDMI: KAE: restore DIG3_KAE\n"); 3002 silent_stream_set_kae(codec, per_pin, true); 3003 } 3004 } 3005 } 3006 3007 return res; 3008 } 3009 #endif 3010 3011 /* precondition and allocation for Intel codecs */ 3012 static int alloc_intel_hdmi(struct hda_codec *codec) 3013 { 3014 int err; 3015 3016 /* requires i915 binding */ 3017 if (!codec->bus->core.audio_component) { 3018 codec_info(codec, "No i915 binding for Intel HDMI/DP codec\n"); 3019 /* set probe_id here to prevent generic fallback binding */ 3020 codec->probe_id = HDA_CODEC_ID_SKIP_PROBE; 3021 return -ENODEV; 3022 } 3023 3024 err = alloc_generic_hdmi(codec); 3025 if (err < 0) 3026 return err; 3027 /* no need to handle unsol events */ 3028 codec->patch_ops.unsol_event = NULL; 3029 return 0; 3030 } 3031 3032 /* parse and post-process for Intel codecs */ 3033 static int parse_intel_hdmi(struct hda_codec *codec) 3034 { 3035 int err, retries = 3; 3036 3037 do { 3038 err = hdmi_parse_codec(codec); 3039 } while (err < 0 && retries--); 3040 3041 if (err < 0) { 3042 generic_spec_free(codec); 3043 return err; 3044 } 3045 3046 generic_hdmi_init_per_pins(codec); 3047 register_i915_notifier(codec); 3048 return 0; 3049 } 3050 3051 /* Intel Haswell and onwards; audio component with eld notifier */ 3052 static int intel_hsw_common_init(struct hda_codec *codec, hda_nid_t vendor_nid, 3053 const int *port_map, int port_num, int dev_num, 3054 bool send_silent_stream) 3055 { 3056 struct hdmi_spec *spec; 3057 int err; 3058 3059 err = alloc_intel_hdmi(codec); 3060 if (err < 0) 3061 return err; 3062 spec = codec->spec; 3063 codec->dp_mst = true; 3064 spec->vendor_nid = vendor_nid; 3065 spec->port_map = port_map; 3066 spec->port_num = port_num; 3067 spec->intel_hsw_fixup = true; 3068 spec->dev_num = dev_num; 3069 3070 intel_haswell_enable_all_pins(codec, true); 3071 intel_haswell_fixup_enable_dp12(codec); 3072 3073 codec->display_power_control = 1; 3074 3075 codec->patch_ops.set_power_state = haswell_set_power_state; 3076 codec->depop_delay = 0; 3077 codec->auto_runtime_pm = 1; 3078 3079 spec->ops.setup_stream = i915_hsw_setup_stream; 3080 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3081 3082 /* 3083 * Enable silent stream feature, if it is enabled via 3084 * module param or Kconfig option 3085 */ 3086 if (send_silent_stream) 3087 spec->silent_stream_type = SILENT_STREAM_I915; 3088 3089 return parse_intel_hdmi(codec); 3090 } 3091 3092 static int patch_i915_hsw_hdmi(struct hda_codec *codec) 3093 { 3094 return intel_hsw_common_init(codec, 0x08, NULL, 0, 3, 3095 enable_silent_stream); 3096 } 3097 3098 static int patch_i915_glk_hdmi(struct hda_codec *codec) 3099 { 3100 /* 3101 * Silent stream calls audio component .get_power() from 3102 * .pin_eld_notify(). On GLK this will deadlock in i915 due 3103 * to the audio vs. CDCLK workaround. 3104 */ 3105 return intel_hsw_common_init(codec, 0x0b, NULL, 0, 3, false); 3106 } 3107 3108 static int patch_i915_icl_hdmi(struct hda_codec *codec) 3109 { 3110 /* 3111 * pin to port mapping table where the value indicate the pin number and 3112 * the index indicate the port number. 3113 */ 3114 static const int map[] = {0x0, 0x4, 0x6, 0x8, 0xa, 0xb}; 3115 3116 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 3, 3117 enable_silent_stream); 3118 } 3119 3120 static int patch_i915_tgl_hdmi(struct hda_codec *codec) 3121 { 3122 /* 3123 * pin to port mapping table where the value indicate the pin number and 3124 * the index indicate the port number. 3125 */ 3126 static const int map[] = {0x4, 0x6, 0x8, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf}; 3127 3128 return intel_hsw_common_init(codec, 0x02, map, ARRAY_SIZE(map), 4, 3129 enable_silent_stream); 3130 } 3131 3132 static int patch_i915_adlp_hdmi(struct hda_codec *codec) 3133 { 3134 struct hdmi_spec *spec; 3135 int res; 3136 3137 res = patch_i915_tgl_hdmi(codec); 3138 if (!res) { 3139 spec = codec->spec; 3140 3141 if (spec->silent_stream_type) { 3142 spec->silent_stream_type = SILENT_STREAM_KAE; 3143 3144 #ifdef CONFIG_PM 3145 codec->patch_ops.resume = i915_adlp_hdmi_resume; 3146 codec->patch_ops.suspend = i915_adlp_hdmi_suspend; 3147 #endif 3148 } 3149 } 3150 3151 return res; 3152 } 3153 3154 /* Intel Baytrail and Braswell; with eld notifier */ 3155 static int patch_i915_byt_hdmi(struct hda_codec *codec) 3156 { 3157 struct hdmi_spec *spec; 3158 int err; 3159 3160 err = alloc_intel_hdmi(codec); 3161 if (err < 0) 3162 return err; 3163 spec = codec->spec; 3164 3165 /* For Valleyview/Cherryview, only the display codec is in the display 3166 * power well and can use link_power ops to request/release the power. 3167 */ 3168 codec->display_power_control = 1; 3169 3170 codec->depop_delay = 0; 3171 codec->auto_runtime_pm = 1; 3172 3173 spec->ops.pin_cvt_fixup = i915_pin_cvt_fixup; 3174 3175 return parse_intel_hdmi(codec); 3176 } 3177 3178 /* Intel IronLake, SandyBridge and IvyBridge; with eld notifier */ 3179 static int patch_i915_cpt_hdmi(struct hda_codec *codec) 3180 { 3181 int err; 3182 3183 err = alloc_intel_hdmi(codec); 3184 if (err < 0) 3185 return err; 3186 return parse_intel_hdmi(codec); 3187 } 3188 3189 /* 3190 * Shared non-generic implementations 3191 */ 3192 3193 static int simple_playback_build_pcms(struct hda_codec *codec) 3194 { 3195 struct hdmi_spec *spec = codec->spec; 3196 struct hda_pcm *info; 3197 unsigned int chans; 3198 struct hda_pcm_stream *pstr; 3199 struct hdmi_spec_per_cvt *per_cvt; 3200 3201 per_cvt = get_cvt(spec, 0); 3202 chans = get_wcaps(codec, per_cvt->cvt_nid); 3203 chans = get_wcaps_channels(chans); 3204 3205 info = snd_hda_codec_pcm_new(codec, "HDMI 0"); 3206 if (!info) 3207 return -ENOMEM; 3208 spec->pcm_rec[0].pcm = info; 3209 info->pcm_type = HDA_PCM_TYPE_HDMI; 3210 pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3211 *pstr = spec->pcm_playback; 3212 pstr->nid = per_cvt->cvt_nid; 3213 if (pstr->channels_max <= 2 && chans && chans <= 16) 3214 pstr->channels_max = chans; 3215 3216 return 0; 3217 } 3218 3219 /* unsolicited event for jack sensing */ 3220 static void simple_hdmi_unsol_event(struct hda_codec *codec, 3221 unsigned int res) 3222 { 3223 snd_hda_jack_set_dirty_all(codec); 3224 snd_hda_jack_report_sync(codec); 3225 } 3226 3227 /* generic_hdmi_build_jack can be used for simple_hdmi, too, 3228 * as long as spec->pins[] is set correctly 3229 */ 3230 #define simple_hdmi_build_jack generic_hdmi_build_jack 3231 3232 static int simple_playback_build_controls(struct hda_codec *codec) 3233 { 3234 struct hdmi_spec *spec = codec->spec; 3235 struct hdmi_spec_per_cvt *per_cvt; 3236 int err; 3237 3238 per_cvt = get_cvt(spec, 0); 3239 err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid, 3240 per_cvt->cvt_nid, 3241 HDA_PCM_TYPE_HDMI); 3242 if (err < 0) 3243 return err; 3244 return simple_hdmi_build_jack(codec, 0); 3245 } 3246 3247 static int simple_playback_init(struct hda_codec *codec) 3248 { 3249 struct hdmi_spec *spec = codec->spec; 3250 struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0); 3251 hda_nid_t pin = per_pin->pin_nid; 3252 3253 snd_hda_codec_write(codec, pin, 0, 3254 AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT); 3255 /* some codecs require to unmute the pin */ 3256 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP) 3257 snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE, 3258 AMP_OUT_UNMUTE); 3259 snd_hda_jack_detect_enable(codec, pin, per_pin->dev_id); 3260 return 0; 3261 } 3262 3263 static void simple_playback_free(struct hda_codec *codec) 3264 { 3265 struct hdmi_spec *spec = codec->spec; 3266 3267 hdmi_array_free(spec); 3268 kfree(spec); 3269 } 3270 3271 /* 3272 * Nvidia specific implementations 3273 */ 3274 3275 #define Nv_VERB_SET_Channel_Allocation 0xF79 3276 #define Nv_VERB_SET_Info_Frame_Checksum 0xF7A 3277 #define Nv_VERB_SET_Audio_Protection_On 0xF98 3278 #define Nv_VERB_SET_Audio_Protection_Off 0xF99 3279 3280 #define nvhdmi_master_con_nid_7x 0x04 3281 #define nvhdmi_master_pin_nid_7x 0x05 3282 3283 static const hda_nid_t nvhdmi_con_nids_7x[4] = { 3284 /*front, rear, clfe, rear_surr */ 3285 0x6, 0x8, 0xa, 0xc, 3286 }; 3287 3288 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = { 3289 /* set audio protect on */ 3290 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3291 /* enable digital output on pin widget */ 3292 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3293 {} /* terminator */ 3294 }; 3295 3296 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = { 3297 /* set audio protect on */ 3298 { 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1}, 3299 /* enable digital output on pin widget */ 3300 { 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3301 { 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3302 { 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3303 { 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3304 { 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 }, 3305 {} /* terminator */ 3306 }; 3307 3308 #ifdef LIMITED_RATE_FMT_SUPPORT 3309 /* support only the safe format and rate */ 3310 #define SUPPORTED_RATES SNDRV_PCM_RATE_48000 3311 #define SUPPORTED_MAXBPS 16 3312 #define SUPPORTED_FORMATS SNDRV_PCM_FMTBIT_S16_LE 3313 #else 3314 /* support all rates and formats */ 3315 #define SUPPORTED_RATES \ 3316 (SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\ 3317 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\ 3318 SNDRV_PCM_RATE_192000) 3319 #define SUPPORTED_MAXBPS 24 3320 #define SUPPORTED_FORMATS \ 3321 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE) 3322 #endif 3323 3324 static int nvhdmi_7x_init_2ch(struct hda_codec *codec) 3325 { 3326 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch); 3327 return 0; 3328 } 3329 3330 static int nvhdmi_7x_init_8ch(struct hda_codec *codec) 3331 { 3332 snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch); 3333 return 0; 3334 } 3335 3336 static const unsigned int channels_2_6_8[] = { 3337 2, 6, 8 3338 }; 3339 3340 static const unsigned int channels_2_8[] = { 3341 2, 8 3342 }; 3343 3344 static const struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = { 3345 .count = ARRAY_SIZE(channels_2_6_8), 3346 .list = channels_2_6_8, 3347 .mask = 0, 3348 }; 3349 3350 static const struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = { 3351 .count = ARRAY_SIZE(channels_2_8), 3352 .list = channels_2_8, 3353 .mask = 0, 3354 }; 3355 3356 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo, 3357 struct hda_codec *codec, 3358 struct snd_pcm_substream *substream) 3359 { 3360 struct hdmi_spec *spec = codec->spec; 3361 const struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL; 3362 3363 switch (codec->preset->vendor_id) { 3364 case 0x10de0002: 3365 case 0x10de0003: 3366 case 0x10de0005: 3367 case 0x10de0006: 3368 hw_constraints_channels = &hw_constraints_2_8_channels; 3369 break; 3370 case 0x10de0007: 3371 hw_constraints_channels = &hw_constraints_2_6_8_channels; 3372 break; 3373 default: 3374 break; 3375 } 3376 3377 if (hw_constraints_channels != NULL) { 3378 snd_pcm_hw_constraint_list(substream->runtime, 0, 3379 SNDRV_PCM_HW_PARAM_CHANNELS, 3380 hw_constraints_channels); 3381 } else { 3382 snd_pcm_hw_constraint_step(substream->runtime, 0, 3383 SNDRV_PCM_HW_PARAM_CHANNELS, 2); 3384 } 3385 3386 return snd_hda_multi_out_dig_open(codec, &spec->multiout); 3387 } 3388 3389 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo, 3390 struct hda_codec *codec, 3391 struct snd_pcm_substream *substream) 3392 { 3393 struct hdmi_spec *spec = codec->spec; 3394 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3395 } 3396 3397 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo, 3398 struct hda_codec *codec, 3399 unsigned int stream_tag, 3400 unsigned int format, 3401 struct snd_pcm_substream *substream) 3402 { 3403 struct hdmi_spec *spec = codec->spec; 3404 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout, 3405 stream_tag, format, substream); 3406 } 3407 3408 static const struct hda_pcm_stream simple_pcm_playback = { 3409 .substreams = 1, 3410 .channels_min = 2, 3411 .channels_max = 2, 3412 .ops = { 3413 .open = simple_playback_pcm_open, 3414 .close = simple_playback_pcm_close, 3415 .prepare = simple_playback_pcm_prepare 3416 }, 3417 }; 3418 3419 static const struct hda_codec_ops simple_hdmi_patch_ops = { 3420 .build_controls = simple_playback_build_controls, 3421 .build_pcms = simple_playback_build_pcms, 3422 .init = simple_playback_init, 3423 .free = simple_playback_free, 3424 .unsol_event = simple_hdmi_unsol_event, 3425 }; 3426 3427 static int patch_simple_hdmi(struct hda_codec *codec, 3428 hda_nid_t cvt_nid, hda_nid_t pin_nid) 3429 { 3430 struct hdmi_spec *spec; 3431 struct hdmi_spec_per_cvt *per_cvt; 3432 struct hdmi_spec_per_pin *per_pin; 3433 3434 spec = kzalloc(sizeof(*spec), GFP_KERNEL); 3435 if (!spec) 3436 return -ENOMEM; 3437 3438 spec->codec = codec; 3439 codec->spec = spec; 3440 hdmi_array_init(spec, 1); 3441 3442 spec->multiout.num_dacs = 0; /* no analog */ 3443 spec->multiout.max_channels = 2; 3444 spec->multiout.dig_out_nid = cvt_nid; 3445 spec->num_cvts = 1; 3446 spec->num_pins = 1; 3447 per_pin = snd_array_new(&spec->pins); 3448 per_cvt = snd_array_new(&spec->cvts); 3449 if (!per_pin || !per_cvt) { 3450 simple_playback_free(codec); 3451 return -ENOMEM; 3452 } 3453 per_cvt->cvt_nid = cvt_nid; 3454 per_pin->pin_nid = pin_nid; 3455 spec->pcm_playback = simple_pcm_playback; 3456 3457 codec->patch_ops = simple_hdmi_patch_ops; 3458 3459 return 0; 3460 } 3461 3462 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec, 3463 int channels) 3464 { 3465 unsigned int chanmask; 3466 int chan = channels ? (channels - 1) : 1; 3467 3468 switch (channels) { 3469 default: 3470 case 0: 3471 case 2: 3472 chanmask = 0x00; 3473 break; 3474 case 4: 3475 chanmask = 0x08; 3476 break; 3477 case 6: 3478 chanmask = 0x0b; 3479 break; 3480 case 8: 3481 chanmask = 0x13; 3482 break; 3483 } 3484 3485 /* Set the audio infoframe channel allocation and checksum fields. The 3486 * channel count is computed implicitly by the hardware. */ 3487 snd_hda_codec_write(codec, 0x1, 0, 3488 Nv_VERB_SET_Channel_Allocation, chanmask); 3489 3490 snd_hda_codec_write(codec, 0x1, 0, 3491 Nv_VERB_SET_Info_Frame_Checksum, 3492 (0x71 - chan - chanmask)); 3493 } 3494 3495 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo, 3496 struct hda_codec *codec, 3497 struct snd_pcm_substream *substream) 3498 { 3499 struct hdmi_spec *spec = codec->spec; 3500 int i; 3501 3502 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 3503 0, AC_VERB_SET_CHANNEL_STREAMID, 0); 3504 for (i = 0; i < 4; i++) { 3505 /* set the stream id */ 3506 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3507 AC_VERB_SET_CHANNEL_STREAMID, 0); 3508 /* set the stream format */ 3509 snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0, 3510 AC_VERB_SET_STREAM_FORMAT, 0); 3511 } 3512 3513 /* The audio hardware sends a channel count of 0x7 (8ch) when all the 3514 * streams are disabled. */ 3515 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3516 3517 return snd_hda_multi_out_dig_close(codec, &spec->multiout); 3518 } 3519 3520 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo, 3521 struct hda_codec *codec, 3522 unsigned int stream_tag, 3523 unsigned int format, 3524 struct snd_pcm_substream *substream) 3525 { 3526 int chs; 3527 unsigned int dataDCC2, channel_id; 3528 int i; 3529 struct hdmi_spec *spec = codec->spec; 3530 struct hda_spdif_out *spdif; 3531 struct hdmi_spec_per_cvt *per_cvt; 3532 3533 mutex_lock(&codec->spdif_mutex); 3534 per_cvt = get_cvt(spec, 0); 3535 spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid); 3536 3537 chs = substream->runtime->channels; 3538 3539 dataDCC2 = 0x2; 3540 3541 /* turn off SPDIF once; otherwise the IEC958 bits won't be updated */ 3542 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) 3543 snd_hda_codec_write(codec, 3544 nvhdmi_master_con_nid_7x, 3545 0, 3546 AC_VERB_SET_DIGI_CONVERT_1, 3547 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3548 3549 /* set the stream id */ 3550 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3551 AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0); 3552 3553 /* set the stream format */ 3554 snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0, 3555 AC_VERB_SET_STREAM_FORMAT, format); 3556 3557 /* turn on again (if needed) */ 3558 /* enable and set the channel status audio/data flag */ 3559 if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) { 3560 snd_hda_codec_write(codec, 3561 nvhdmi_master_con_nid_7x, 3562 0, 3563 AC_VERB_SET_DIGI_CONVERT_1, 3564 spdif->ctls & 0xff); 3565 snd_hda_codec_write(codec, 3566 nvhdmi_master_con_nid_7x, 3567 0, 3568 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3569 } 3570 3571 for (i = 0; i < 4; i++) { 3572 if (chs == 2) 3573 channel_id = 0; 3574 else 3575 channel_id = i * 2; 3576 3577 /* turn off SPDIF once; 3578 *otherwise the IEC958 bits won't be updated 3579 */ 3580 if (codec->spdif_status_reset && 3581 (spdif->ctls & AC_DIG1_ENABLE)) 3582 snd_hda_codec_write(codec, 3583 nvhdmi_con_nids_7x[i], 3584 0, 3585 AC_VERB_SET_DIGI_CONVERT_1, 3586 spdif->ctls & ~AC_DIG1_ENABLE & 0xff); 3587 /* set the stream id */ 3588 snd_hda_codec_write(codec, 3589 nvhdmi_con_nids_7x[i], 3590 0, 3591 AC_VERB_SET_CHANNEL_STREAMID, 3592 (stream_tag << 4) | channel_id); 3593 /* set the stream format */ 3594 snd_hda_codec_write(codec, 3595 nvhdmi_con_nids_7x[i], 3596 0, 3597 AC_VERB_SET_STREAM_FORMAT, 3598 format); 3599 /* turn on again (if needed) */ 3600 /* enable and set the channel status audio/data flag */ 3601 if (codec->spdif_status_reset && 3602 (spdif->ctls & AC_DIG1_ENABLE)) { 3603 snd_hda_codec_write(codec, 3604 nvhdmi_con_nids_7x[i], 3605 0, 3606 AC_VERB_SET_DIGI_CONVERT_1, 3607 spdif->ctls & 0xff); 3608 snd_hda_codec_write(codec, 3609 nvhdmi_con_nids_7x[i], 3610 0, 3611 AC_VERB_SET_DIGI_CONVERT_2, dataDCC2); 3612 } 3613 } 3614 3615 nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs); 3616 3617 mutex_unlock(&codec->spdif_mutex); 3618 return 0; 3619 } 3620 3621 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = { 3622 .substreams = 1, 3623 .channels_min = 2, 3624 .channels_max = 8, 3625 .nid = nvhdmi_master_con_nid_7x, 3626 .rates = SUPPORTED_RATES, 3627 .maxbps = SUPPORTED_MAXBPS, 3628 .formats = SUPPORTED_FORMATS, 3629 .ops = { 3630 .open = simple_playback_pcm_open, 3631 .close = nvhdmi_8ch_7x_pcm_close, 3632 .prepare = nvhdmi_8ch_7x_pcm_prepare 3633 }, 3634 }; 3635 3636 static int patch_nvhdmi_2ch(struct hda_codec *codec) 3637 { 3638 struct hdmi_spec *spec; 3639 int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x, 3640 nvhdmi_master_pin_nid_7x); 3641 if (err < 0) 3642 return err; 3643 3644 codec->patch_ops.init = nvhdmi_7x_init_2ch; 3645 /* override the PCM rates, etc, as the codec doesn't give full list */ 3646 spec = codec->spec; 3647 spec->pcm_playback.rates = SUPPORTED_RATES; 3648 spec->pcm_playback.maxbps = SUPPORTED_MAXBPS; 3649 spec->pcm_playback.formats = SUPPORTED_FORMATS; 3650 spec->nv_dp_workaround = true; 3651 return 0; 3652 } 3653 3654 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec) 3655 { 3656 struct hdmi_spec *spec = codec->spec; 3657 int err = simple_playback_build_pcms(codec); 3658 if (!err) { 3659 struct hda_pcm *info = get_pcm_rec(spec, 0); 3660 info->own_chmap = true; 3661 } 3662 return err; 3663 } 3664 3665 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec) 3666 { 3667 struct hdmi_spec *spec = codec->spec; 3668 struct hda_pcm *info; 3669 struct snd_pcm_chmap *chmap; 3670 int err; 3671 3672 err = simple_playback_build_controls(codec); 3673 if (err < 0) 3674 return err; 3675 3676 /* add channel maps */ 3677 info = get_pcm_rec(spec, 0); 3678 err = snd_pcm_add_chmap_ctls(info->pcm, 3679 SNDRV_PCM_STREAM_PLAYBACK, 3680 snd_pcm_alt_chmaps, 8, 0, &chmap); 3681 if (err < 0) 3682 return err; 3683 switch (codec->preset->vendor_id) { 3684 case 0x10de0002: 3685 case 0x10de0003: 3686 case 0x10de0005: 3687 case 0x10de0006: 3688 chmap->channel_mask = (1U << 2) | (1U << 8); 3689 break; 3690 case 0x10de0007: 3691 chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8); 3692 } 3693 return 0; 3694 } 3695 3696 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec) 3697 { 3698 struct hdmi_spec *spec; 3699 int err = patch_nvhdmi_2ch(codec); 3700 if (err < 0) 3701 return err; 3702 spec = codec->spec; 3703 spec->multiout.max_channels = 8; 3704 spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x; 3705 codec->patch_ops.init = nvhdmi_7x_init_8ch; 3706 codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms; 3707 codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls; 3708 3709 /* Initialize the audio infoframe channel mask and checksum to something 3710 * valid */ 3711 nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8); 3712 3713 return 0; 3714 } 3715 3716 /* 3717 * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on: 3718 * - 0x10de0015 3719 * - 0x10de0040 3720 */ 3721 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct hdac_chmap *chmap, 3722 struct hdac_cea_channel_speaker_allocation *cap, int channels) 3723 { 3724 if (cap->ca_index == 0x00 && channels == 2) 3725 return SNDRV_CTL_TLVT_CHMAP_FIXED; 3726 3727 /* If the speaker allocation matches the channel count, it is OK. */ 3728 if (cap->channels != channels) 3729 return -1; 3730 3731 /* all channels are remappable freely */ 3732 return SNDRV_CTL_TLVT_CHMAP_VAR; 3733 } 3734 3735 static int nvhdmi_chmap_validate(struct hdac_chmap *chmap, 3736 int ca, int chs, unsigned char *map) 3737 { 3738 if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR)) 3739 return -EINVAL; 3740 3741 return 0; 3742 } 3743 3744 /* map from pin NID to port; port is 0-based */ 3745 /* for Nvidia: assume widget NID starting from 4, with step 1 (4, 5, 6, ...) */ 3746 static int nvhdmi_pin2port(void *audio_ptr, int pin_nid) 3747 { 3748 return pin_nid - 4; 3749 } 3750 3751 /* reverse-map from port to pin NID: see above */ 3752 static int nvhdmi_port2pin(struct hda_codec *codec, int port) 3753 { 3754 return port + 4; 3755 } 3756 3757 static const struct drm_audio_component_audio_ops nvhdmi_audio_ops = { 3758 .pin2port = nvhdmi_pin2port, 3759 .pin_eld_notify = generic_acomp_pin_eld_notify, 3760 .master_bind = generic_acomp_master_bind, 3761 .master_unbind = generic_acomp_master_unbind, 3762 }; 3763 3764 static int patch_nvhdmi(struct hda_codec *codec) 3765 { 3766 struct hdmi_spec *spec; 3767 int err; 3768 3769 err = alloc_generic_hdmi(codec); 3770 if (err < 0) 3771 return err; 3772 codec->dp_mst = true; 3773 3774 spec = codec->spec; 3775 3776 err = hdmi_parse_codec(codec); 3777 if (err < 0) { 3778 generic_spec_free(codec); 3779 return err; 3780 } 3781 3782 generic_hdmi_init_per_pins(codec); 3783 3784 spec->dyn_pin_out = true; 3785 3786 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3787 nvhdmi_chmap_cea_alloc_validate_get_type; 3788 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3789 spec->nv_dp_workaround = true; 3790 3791 codec->link_down_at_suspend = 1; 3792 3793 generic_acomp_init(codec, &nvhdmi_audio_ops, nvhdmi_port2pin); 3794 3795 return 0; 3796 } 3797 3798 static int patch_nvhdmi_legacy(struct hda_codec *codec) 3799 { 3800 struct hdmi_spec *spec; 3801 int err; 3802 3803 err = patch_generic_hdmi(codec); 3804 if (err) 3805 return err; 3806 3807 spec = codec->spec; 3808 spec->dyn_pin_out = true; 3809 3810 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 3811 nvhdmi_chmap_cea_alloc_validate_get_type; 3812 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 3813 spec->nv_dp_workaround = true; 3814 3815 codec->link_down_at_suspend = 1; 3816 3817 return 0; 3818 } 3819 3820 /* 3821 * The HDA codec on NVIDIA Tegra contains two scratch registers that are 3822 * accessed using vendor-defined verbs. These registers can be used for 3823 * interoperability between the HDA and HDMI drivers. 3824 */ 3825 3826 /* Audio Function Group node */ 3827 #define NVIDIA_AFG_NID 0x01 3828 3829 /* 3830 * The SCRATCH0 register is used to notify the HDMI codec of changes in audio 3831 * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to 3832 * be raised in the HDMI codec. The remainder of the bits is arbitrary. This 3833 * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an 3834 * additional bit (at position 30) to signal the validity of the format. 3835 * 3836 * | 31 | 30 | 29 16 | 15 0 | 3837 * +---------+-------+--------+--------+ 3838 * | TRIGGER | VALID | UNUSED | FORMAT | 3839 * +-----------------------------------| 3840 * 3841 * Note that for the trigger bit to take effect it needs to change value 3842 * (i.e. it needs to be toggled). The trigger bit is not applicable from 3843 * TEGRA234 chip onwards, as new verb id 0xf80 will be used for interrupt 3844 * trigger to hdmi. 3845 */ 3846 #define NVIDIA_SET_HOST_INTR 0xf80 3847 #define NVIDIA_GET_SCRATCH0 0xfa6 3848 #define NVIDIA_SET_SCRATCH0_BYTE0 0xfa7 3849 #define NVIDIA_SET_SCRATCH0_BYTE1 0xfa8 3850 #define NVIDIA_SET_SCRATCH0_BYTE2 0xfa9 3851 #define NVIDIA_SET_SCRATCH0_BYTE3 0xfaa 3852 #define NVIDIA_SCRATCH_TRIGGER (1 << 7) 3853 #define NVIDIA_SCRATCH_VALID (1 << 6) 3854 3855 #define NVIDIA_GET_SCRATCH1 0xfab 3856 #define NVIDIA_SET_SCRATCH1_BYTE0 0xfac 3857 #define NVIDIA_SET_SCRATCH1_BYTE1 0xfad 3858 #define NVIDIA_SET_SCRATCH1_BYTE2 0xfae 3859 #define NVIDIA_SET_SCRATCH1_BYTE3 0xfaf 3860 3861 /* 3862 * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0, 3863 * the format is invalidated so that the HDMI codec can be disabled. 3864 */ 3865 static void tegra_hdmi_set_format(struct hda_codec *codec, 3866 hda_nid_t cvt_nid, 3867 unsigned int format) 3868 { 3869 unsigned int value; 3870 unsigned int nid = NVIDIA_AFG_NID; 3871 struct hdmi_spec *spec = codec->spec; 3872 3873 /* 3874 * Tegra HDA codec design from TEGRA234 chip onwards support DP MST. 3875 * This resulted in moving scratch registers from audio function 3876 * group to converter widget context. So CVT NID should be used for 3877 * scratch register read/write for DP MST supported Tegra HDA codec. 3878 */ 3879 if (codec->dp_mst) 3880 nid = cvt_nid; 3881 3882 /* bits [31:30] contain the trigger and valid bits */ 3883 value = snd_hda_codec_read(codec, nid, 0, 3884 NVIDIA_GET_SCRATCH0, 0); 3885 value = (value >> 24) & 0xff; 3886 3887 /* bits [15:0] are used to store the HDA format */ 3888 snd_hda_codec_write(codec, nid, 0, 3889 NVIDIA_SET_SCRATCH0_BYTE0, 3890 (format >> 0) & 0xff); 3891 snd_hda_codec_write(codec, nid, 0, 3892 NVIDIA_SET_SCRATCH0_BYTE1, 3893 (format >> 8) & 0xff); 3894 3895 /* bits [16:24] are unused */ 3896 snd_hda_codec_write(codec, nid, 0, 3897 NVIDIA_SET_SCRATCH0_BYTE2, 0); 3898 3899 /* 3900 * Bit 30 signals that the data is valid and hence that HDMI audio can 3901 * be enabled. 3902 */ 3903 if (format == 0) 3904 value &= ~NVIDIA_SCRATCH_VALID; 3905 else 3906 value |= NVIDIA_SCRATCH_VALID; 3907 3908 if (spec->hdmi_intr_trig_ctrl) { 3909 /* 3910 * For Tegra HDA Codec design from TEGRA234 onwards, the 3911 * Interrupt to hdmi driver is triggered by writing 3912 * non-zero values to verb 0xF80 instead of 31st bit of 3913 * scratch register. 3914 */ 3915 snd_hda_codec_write(codec, nid, 0, 3916 NVIDIA_SET_SCRATCH0_BYTE3, value); 3917 snd_hda_codec_write(codec, nid, 0, 3918 NVIDIA_SET_HOST_INTR, 0x1); 3919 } else { 3920 /* 3921 * Whenever the 31st trigger bit is toggled, an interrupt is raised 3922 * in the HDMI codec. The HDMI driver will use that as trigger 3923 * to update its configuration. 3924 */ 3925 value ^= NVIDIA_SCRATCH_TRIGGER; 3926 3927 snd_hda_codec_write(codec, nid, 0, 3928 NVIDIA_SET_SCRATCH0_BYTE3, value); 3929 } 3930 } 3931 3932 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo, 3933 struct hda_codec *codec, 3934 unsigned int stream_tag, 3935 unsigned int format, 3936 struct snd_pcm_substream *substream) 3937 { 3938 int err; 3939 3940 err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag, 3941 format, substream); 3942 if (err < 0) 3943 return err; 3944 3945 /* notify the HDMI codec of the format change */ 3946 tegra_hdmi_set_format(codec, hinfo->nid, format); 3947 3948 return 0; 3949 } 3950 3951 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo, 3952 struct hda_codec *codec, 3953 struct snd_pcm_substream *substream) 3954 { 3955 /* invalidate the format in the HDMI codec */ 3956 tegra_hdmi_set_format(codec, hinfo->nid, 0); 3957 3958 return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream); 3959 } 3960 3961 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type) 3962 { 3963 struct hdmi_spec *spec = codec->spec; 3964 unsigned int i; 3965 3966 for (i = 0; i < spec->num_pins; i++) { 3967 struct hda_pcm *pcm = get_pcm_rec(spec, i); 3968 3969 if (pcm->pcm_type == type) 3970 return pcm; 3971 } 3972 3973 return NULL; 3974 } 3975 3976 static int tegra_hdmi_build_pcms(struct hda_codec *codec) 3977 { 3978 struct hda_pcm_stream *stream; 3979 struct hda_pcm *pcm; 3980 int err; 3981 3982 err = generic_hdmi_build_pcms(codec); 3983 if (err < 0) 3984 return err; 3985 3986 pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI); 3987 if (!pcm) 3988 return -ENODEV; 3989 3990 /* 3991 * Override ->prepare() and ->cleanup() operations to notify the HDMI 3992 * codec about format changes. 3993 */ 3994 stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK]; 3995 stream->ops.prepare = tegra_hdmi_pcm_prepare; 3996 stream->ops.cleanup = tegra_hdmi_pcm_cleanup; 3997 3998 return 0; 3999 } 4000 4001 static int tegra_hdmi_init(struct hda_codec *codec) 4002 { 4003 struct hdmi_spec *spec = codec->spec; 4004 int i, err; 4005 4006 err = hdmi_parse_codec(codec); 4007 if (err < 0) { 4008 generic_spec_free(codec); 4009 return err; 4010 } 4011 4012 for (i = 0; i < spec->num_cvts; i++) 4013 snd_hda_codec_write(codec, spec->cvt_nids[i], 0, 4014 AC_VERB_SET_DIGI_CONVERT_1, 4015 AC_DIG1_ENABLE); 4016 4017 generic_hdmi_init_per_pins(codec); 4018 4019 codec->depop_delay = 10; 4020 codec->patch_ops.build_pcms = tegra_hdmi_build_pcms; 4021 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4022 nvhdmi_chmap_cea_alloc_validate_get_type; 4023 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4024 4025 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4026 nvhdmi_chmap_cea_alloc_validate_get_type; 4027 spec->chmap.ops.chmap_validate = nvhdmi_chmap_validate; 4028 spec->nv_dp_workaround = true; 4029 4030 return 0; 4031 } 4032 4033 static int patch_tegra_hdmi(struct hda_codec *codec) 4034 { 4035 int err; 4036 4037 err = alloc_generic_hdmi(codec); 4038 if (err < 0) 4039 return err; 4040 4041 return tegra_hdmi_init(codec); 4042 } 4043 4044 static int patch_tegra234_hdmi(struct hda_codec *codec) 4045 { 4046 struct hdmi_spec *spec; 4047 int err; 4048 4049 err = alloc_generic_hdmi(codec); 4050 if (err < 0) 4051 return err; 4052 4053 codec->dp_mst = true; 4054 spec = codec->spec; 4055 spec->dyn_pin_out = true; 4056 spec->hdmi_intr_trig_ctrl = true; 4057 4058 return tegra_hdmi_init(codec); 4059 } 4060 4061 /* 4062 * ATI/AMD-specific implementations 4063 */ 4064 4065 #define is_amdhdmi_rev3_or_later(codec) \ 4066 ((codec)->core.vendor_id == 0x1002aa01 && \ 4067 ((codec)->core.revision_id & 0xff00) >= 0x0300) 4068 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec) 4069 4070 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */ 4071 #define ATI_VERB_SET_CHANNEL_ALLOCATION 0x771 4072 #define ATI_VERB_SET_DOWNMIX_INFO 0x772 4073 #define ATI_VERB_SET_MULTICHANNEL_01 0x777 4074 #define ATI_VERB_SET_MULTICHANNEL_23 0x778 4075 #define ATI_VERB_SET_MULTICHANNEL_45 0x779 4076 #define ATI_VERB_SET_MULTICHANNEL_67 0x77a 4077 #define ATI_VERB_SET_HBR_CONTROL 0x77c 4078 #define ATI_VERB_SET_MULTICHANNEL_1 0x785 4079 #define ATI_VERB_SET_MULTICHANNEL_3 0x786 4080 #define ATI_VERB_SET_MULTICHANNEL_5 0x787 4081 #define ATI_VERB_SET_MULTICHANNEL_7 0x788 4082 #define ATI_VERB_SET_MULTICHANNEL_MODE 0x789 4083 #define ATI_VERB_GET_CHANNEL_ALLOCATION 0xf71 4084 #define ATI_VERB_GET_DOWNMIX_INFO 0xf72 4085 #define ATI_VERB_GET_MULTICHANNEL_01 0xf77 4086 #define ATI_VERB_GET_MULTICHANNEL_23 0xf78 4087 #define ATI_VERB_GET_MULTICHANNEL_45 0xf79 4088 #define ATI_VERB_GET_MULTICHANNEL_67 0xf7a 4089 #define ATI_VERB_GET_HBR_CONTROL 0xf7c 4090 #define ATI_VERB_GET_MULTICHANNEL_1 0xf85 4091 #define ATI_VERB_GET_MULTICHANNEL_3 0xf86 4092 #define ATI_VERB_GET_MULTICHANNEL_5 0xf87 4093 #define ATI_VERB_GET_MULTICHANNEL_7 0xf88 4094 #define ATI_VERB_GET_MULTICHANNEL_MODE 0xf89 4095 4096 /* AMD specific HDA cvt verbs */ 4097 #define ATI_VERB_SET_RAMP_RATE 0x770 4098 #define ATI_VERB_GET_RAMP_RATE 0xf70 4099 4100 #define ATI_OUT_ENABLE 0x1 4101 4102 #define ATI_MULTICHANNEL_MODE_PAIRED 0 4103 #define ATI_MULTICHANNEL_MODE_SINGLE 1 4104 4105 #define ATI_HBR_CAPABLE 0x01 4106 #define ATI_HBR_ENABLE 0x10 4107 4108 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid, 4109 int dev_id, unsigned char *buf, int *eld_size) 4110 { 4111 WARN_ON(dev_id != 0); 4112 /* call hda_eld.c ATI/AMD-specific function */ 4113 return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size, 4114 is_amdhdmi_rev3_or_later(codec)); 4115 } 4116 4117 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, 4118 hda_nid_t pin_nid, int dev_id, int ca, 4119 int active_channels, int conn_type) 4120 { 4121 WARN_ON(dev_id != 0); 4122 snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca); 4123 } 4124 4125 static int atihdmi_paired_swap_fc_lfe(int pos) 4126 { 4127 /* 4128 * ATI/AMD have automatic FC/LFE swap built-in 4129 * when in pairwise mapping mode. 4130 */ 4131 4132 switch (pos) { 4133 /* see channel_allocations[].speakers[] */ 4134 case 2: return 3; 4135 case 3: return 2; 4136 default: break; 4137 } 4138 4139 return pos; 4140 } 4141 4142 static int atihdmi_paired_chmap_validate(struct hdac_chmap *chmap, 4143 int ca, int chs, unsigned char *map) 4144 { 4145 struct hdac_cea_channel_speaker_allocation *cap; 4146 int i, j; 4147 4148 /* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */ 4149 4150 cap = snd_hdac_get_ch_alloc_from_ca(ca); 4151 for (i = 0; i < chs; ++i) { 4152 int mask = snd_hdac_chmap_to_spk_mask(map[i]); 4153 bool ok = false; 4154 bool companion_ok = false; 4155 4156 if (!mask) 4157 continue; 4158 4159 for (j = 0 + i % 2; j < 8; j += 2) { 4160 int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j); 4161 if (cap->speakers[chan_idx] == mask) { 4162 /* channel is in a supported position */ 4163 ok = true; 4164 4165 if (i % 2 == 0 && i + 1 < chs) { 4166 /* even channel, check the odd companion */ 4167 int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1); 4168 int comp_mask_req = snd_hdac_chmap_to_spk_mask(map[i+1]); 4169 int comp_mask_act = cap->speakers[comp_chan_idx]; 4170 4171 if (comp_mask_req == comp_mask_act) 4172 companion_ok = true; 4173 else 4174 return -EINVAL; 4175 } 4176 break; 4177 } 4178 } 4179 4180 if (!ok) 4181 return -EINVAL; 4182 4183 if (companion_ok) 4184 i++; /* companion channel already checked */ 4185 } 4186 4187 return 0; 4188 } 4189 4190 static int atihdmi_pin_set_slot_channel(struct hdac_device *hdac, 4191 hda_nid_t pin_nid, int hdmi_slot, int stream_channel) 4192 { 4193 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4194 int verb; 4195 int ati_channel_setup = 0; 4196 4197 if (hdmi_slot > 7) 4198 return -EINVAL; 4199 4200 if (!has_amd_full_remap_support(codec)) { 4201 hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot); 4202 4203 /* In case this is an odd slot but without stream channel, do not 4204 * disable the slot since the corresponding even slot could have a 4205 * channel. In case neither have a channel, the slot pair will be 4206 * disabled when this function is called for the even slot. */ 4207 if (hdmi_slot % 2 != 0 && stream_channel == 0xf) 4208 return 0; 4209 4210 hdmi_slot -= hdmi_slot % 2; 4211 4212 if (stream_channel != 0xf) 4213 stream_channel -= stream_channel % 2; 4214 } 4215 4216 verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e; 4217 4218 /* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */ 4219 4220 if (stream_channel != 0xf) 4221 ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE; 4222 4223 return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup); 4224 } 4225 4226 static int atihdmi_pin_get_slot_channel(struct hdac_device *hdac, 4227 hda_nid_t pin_nid, int asp_slot) 4228 { 4229 struct hda_codec *codec = hdac_to_hda_codec(hdac); 4230 bool was_odd = false; 4231 int ati_asp_slot = asp_slot; 4232 int verb; 4233 int ati_channel_setup; 4234 4235 if (asp_slot > 7) 4236 return -EINVAL; 4237 4238 if (!has_amd_full_remap_support(codec)) { 4239 ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot); 4240 if (ati_asp_slot % 2 != 0) { 4241 ati_asp_slot -= 1; 4242 was_odd = true; 4243 } 4244 } 4245 4246 verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e; 4247 4248 ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0); 4249 4250 if (!(ati_channel_setup & ATI_OUT_ENABLE)) 4251 return 0xf; 4252 4253 return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd; 4254 } 4255 4256 static int atihdmi_paired_chmap_cea_alloc_validate_get_type( 4257 struct hdac_chmap *chmap, 4258 struct hdac_cea_channel_speaker_allocation *cap, 4259 int channels) 4260 { 4261 int c; 4262 4263 /* 4264 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so 4265 * we need to take that into account (a single channel may take 2 4266 * channel slots if we need to carry a silent channel next to it). 4267 * On Rev3+ AMD codecs this function is not used. 4268 */ 4269 int chanpairs = 0; 4270 4271 /* We only produce even-numbered channel count TLVs */ 4272 if ((channels % 2) != 0) 4273 return -1; 4274 4275 for (c = 0; c < 7; c += 2) { 4276 if (cap->speakers[c] || cap->speakers[c+1]) 4277 chanpairs++; 4278 } 4279 4280 if (chanpairs * 2 != channels) 4281 return -1; 4282 4283 return SNDRV_CTL_TLVT_CHMAP_PAIRED; 4284 } 4285 4286 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct hdac_chmap *hchmap, 4287 struct hdac_cea_channel_speaker_allocation *cap, 4288 unsigned int *chmap, int channels) 4289 { 4290 /* produce paired maps for pre-rev3 ATI/AMD codecs */ 4291 int count = 0; 4292 int c; 4293 4294 for (c = 7; c >= 0; c--) { 4295 int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c); 4296 int spk = cap->speakers[chan]; 4297 if (!spk) { 4298 /* add N/A channel if the companion channel is occupied */ 4299 if (cap->speakers[chan + (chan % 2 ? -1 : 1)]) 4300 chmap[count++] = SNDRV_CHMAP_NA; 4301 4302 continue; 4303 } 4304 4305 chmap[count++] = snd_hdac_spk_to_chmap(spk); 4306 } 4307 4308 WARN_ON(count != channels); 4309 } 4310 4311 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid, 4312 int dev_id, bool hbr) 4313 { 4314 int hbr_ctl, hbr_ctl_new; 4315 4316 WARN_ON(dev_id != 0); 4317 4318 hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0); 4319 if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) { 4320 if (hbr) 4321 hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE; 4322 else 4323 hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE; 4324 4325 codec_dbg(codec, 4326 "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n", 4327 pin_nid, 4328 hbr_ctl == hbr_ctl_new ? "" : "new-", 4329 hbr_ctl_new); 4330 4331 if (hbr_ctl != hbr_ctl_new) 4332 snd_hda_codec_write(codec, pin_nid, 0, 4333 ATI_VERB_SET_HBR_CONTROL, 4334 hbr_ctl_new); 4335 4336 } else if (hbr) 4337 return -EINVAL; 4338 4339 return 0; 4340 } 4341 4342 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid, 4343 hda_nid_t pin_nid, int dev_id, 4344 u32 stream_tag, int format) 4345 { 4346 if (is_amdhdmi_rev3_or_later(codec)) { 4347 int ramp_rate = 180; /* default as per AMD spec */ 4348 /* disable ramp-up/down for non-pcm as per AMD spec */ 4349 if (format & AC_FMT_TYPE_NON_PCM) 4350 ramp_rate = 0; 4351 4352 snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate); 4353 } 4354 4355 return hdmi_setup_stream(codec, cvt_nid, pin_nid, dev_id, 4356 stream_tag, format); 4357 } 4358 4359 4360 static int atihdmi_init(struct hda_codec *codec) 4361 { 4362 struct hdmi_spec *spec = codec->spec; 4363 int pin_idx, err; 4364 4365 err = generic_hdmi_init(codec); 4366 4367 if (err) 4368 return err; 4369 4370 for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) { 4371 struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx); 4372 4373 /* make sure downmix information in infoframe is zero */ 4374 snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0); 4375 4376 /* enable channel-wise remap mode if supported */ 4377 if (has_amd_full_remap_support(codec)) 4378 snd_hda_codec_write(codec, per_pin->pin_nid, 0, 4379 ATI_VERB_SET_MULTICHANNEL_MODE, 4380 ATI_MULTICHANNEL_MODE_SINGLE); 4381 } 4382 codec->auto_runtime_pm = 1; 4383 4384 return 0; 4385 } 4386 4387 /* map from pin NID to port; port is 0-based */ 4388 /* for AMD: assume widget NID starting from 3, with step 2 (3, 5, 7, ...) */ 4389 static int atihdmi_pin2port(void *audio_ptr, int pin_nid) 4390 { 4391 return pin_nid / 2 - 1; 4392 } 4393 4394 /* reverse-map from port to pin NID: see above */ 4395 static int atihdmi_port2pin(struct hda_codec *codec, int port) 4396 { 4397 return port * 2 + 3; 4398 } 4399 4400 static const struct drm_audio_component_audio_ops atihdmi_audio_ops = { 4401 .pin2port = atihdmi_pin2port, 4402 .pin_eld_notify = generic_acomp_pin_eld_notify, 4403 .master_bind = generic_acomp_master_bind, 4404 .master_unbind = generic_acomp_master_unbind, 4405 }; 4406 4407 static int patch_atihdmi(struct hda_codec *codec) 4408 { 4409 struct hdmi_spec *spec; 4410 struct hdmi_spec_per_cvt *per_cvt; 4411 int err, cvt_idx; 4412 4413 err = patch_generic_hdmi(codec); 4414 4415 if (err) 4416 return err; 4417 4418 codec->patch_ops.init = atihdmi_init; 4419 4420 spec = codec->spec; 4421 4422 spec->ops.pin_get_eld = atihdmi_pin_get_eld; 4423 spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe; 4424 spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup; 4425 spec->ops.setup_stream = atihdmi_setup_stream; 4426 4427 spec->chmap.ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel; 4428 spec->chmap.ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel; 4429 4430 if (!has_amd_full_remap_support(codec)) { 4431 /* override to ATI/AMD-specific versions with pairwise mapping */ 4432 spec->chmap.ops.chmap_cea_alloc_validate_get_type = 4433 atihdmi_paired_chmap_cea_alloc_validate_get_type; 4434 spec->chmap.ops.cea_alloc_to_tlv_chmap = 4435 atihdmi_paired_cea_alloc_to_tlv_chmap; 4436 spec->chmap.ops.chmap_validate = atihdmi_paired_chmap_validate; 4437 } 4438 4439 /* ATI/AMD converters do not advertise all of their capabilities */ 4440 for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) { 4441 per_cvt = get_cvt(spec, cvt_idx); 4442 per_cvt->channels_max = max(per_cvt->channels_max, 8u); 4443 per_cvt->rates |= SUPPORTED_RATES; 4444 per_cvt->formats |= SUPPORTED_FORMATS; 4445 per_cvt->maxbps = max(per_cvt->maxbps, 24u); 4446 } 4447 4448 spec->chmap.channels_max = max(spec->chmap.channels_max, 8u); 4449 4450 /* AMD GPUs have neither EPSS nor CLKSTOP bits, hence preventing 4451 * the link-down as is. Tell the core to allow it. 4452 */ 4453 codec->link_down_at_suspend = 1; 4454 4455 generic_acomp_init(codec, &atihdmi_audio_ops, atihdmi_port2pin); 4456 4457 return 0; 4458 } 4459 4460 /* VIA HDMI Implementation */ 4461 #define VIAHDMI_CVT_NID 0x02 /* audio converter1 */ 4462 #define VIAHDMI_PIN_NID 0x03 /* HDMI output pin1 */ 4463 4464 static int patch_via_hdmi(struct hda_codec *codec) 4465 { 4466 return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID); 4467 } 4468 4469 /* 4470 * patch entries 4471 */ 4472 static const struct hda_device_id snd_hda_id_hdmi[] = { 4473 HDA_CODEC_ENTRY(0x1002793c, "RS600 HDMI", patch_atihdmi), 4474 HDA_CODEC_ENTRY(0x10027919, "RS600 HDMI", patch_atihdmi), 4475 HDA_CODEC_ENTRY(0x1002791a, "RS690/780 HDMI", patch_atihdmi), 4476 HDA_CODEC_ENTRY(0x1002aa01, "R6xx HDMI", patch_atihdmi), 4477 HDA_CODEC_ENTRY(0x10951390, "SiI1390 HDMI", patch_generic_hdmi), 4478 HDA_CODEC_ENTRY(0x10951392, "SiI1392 HDMI", patch_generic_hdmi), 4479 HDA_CODEC_ENTRY(0x17e80047, "Chrontel HDMI", patch_generic_hdmi), 4480 HDA_CODEC_ENTRY(0x10de0001, "MCP73 HDMI", patch_nvhdmi_2ch), 4481 HDA_CODEC_ENTRY(0x10de0002, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4482 HDA_CODEC_ENTRY(0x10de0003, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4483 HDA_CODEC_ENTRY(0x10de0004, "GPU 04 HDMI", patch_nvhdmi_8ch_7x), 4484 HDA_CODEC_ENTRY(0x10de0005, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4485 HDA_CODEC_ENTRY(0x10de0006, "MCP77/78 HDMI", patch_nvhdmi_8ch_7x), 4486 HDA_CODEC_ENTRY(0x10de0007, "MCP79/7A HDMI", patch_nvhdmi_8ch_7x), 4487 HDA_CODEC_ENTRY(0x10de0008, "GPU 08 HDMI/DP", patch_nvhdmi_legacy), 4488 HDA_CODEC_ENTRY(0x10de0009, "GPU 09 HDMI/DP", patch_nvhdmi_legacy), 4489 HDA_CODEC_ENTRY(0x10de000a, "GPU 0a HDMI/DP", patch_nvhdmi_legacy), 4490 HDA_CODEC_ENTRY(0x10de000b, "GPU 0b HDMI/DP", patch_nvhdmi_legacy), 4491 HDA_CODEC_ENTRY(0x10de000c, "MCP89 HDMI", patch_nvhdmi_legacy), 4492 HDA_CODEC_ENTRY(0x10de000d, "GPU 0d HDMI/DP", patch_nvhdmi_legacy), 4493 HDA_CODEC_ENTRY(0x10de0010, "GPU 10 HDMI/DP", patch_nvhdmi_legacy), 4494 HDA_CODEC_ENTRY(0x10de0011, "GPU 11 HDMI/DP", patch_nvhdmi_legacy), 4495 HDA_CODEC_ENTRY(0x10de0012, "GPU 12 HDMI/DP", patch_nvhdmi_legacy), 4496 HDA_CODEC_ENTRY(0x10de0013, "GPU 13 HDMI/DP", patch_nvhdmi_legacy), 4497 HDA_CODEC_ENTRY(0x10de0014, "GPU 14 HDMI/DP", patch_nvhdmi_legacy), 4498 HDA_CODEC_ENTRY(0x10de0015, "GPU 15 HDMI/DP", patch_nvhdmi_legacy), 4499 HDA_CODEC_ENTRY(0x10de0016, "GPU 16 HDMI/DP", patch_nvhdmi_legacy), 4500 /* 17 is known to be absent */ 4501 HDA_CODEC_ENTRY(0x10de0018, "GPU 18 HDMI/DP", patch_nvhdmi_legacy), 4502 HDA_CODEC_ENTRY(0x10de0019, "GPU 19 HDMI/DP", patch_nvhdmi_legacy), 4503 HDA_CODEC_ENTRY(0x10de001a, "GPU 1a HDMI/DP", patch_nvhdmi_legacy), 4504 HDA_CODEC_ENTRY(0x10de001b, "GPU 1b HDMI/DP", patch_nvhdmi_legacy), 4505 HDA_CODEC_ENTRY(0x10de001c, "GPU 1c HDMI/DP", patch_nvhdmi_legacy), 4506 HDA_CODEC_ENTRY(0x10de0020, "Tegra30 HDMI", patch_tegra_hdmi), 4507 HDA_CODEC_ENTRY(0x10de0022, "Tegra114 HDMI", patch_tegra_hdmi), 4508 HDA_CODEC_ENTRY(0x10de0028, "Tegra124 HDMI", patch_tegra_hdmi), 4509 HDA_CODEC_ENTRY(0x10de0029, "Tegra210 HDMI/DP", patch_tegra_hdmi), 4510 HDA_CODEC_ENTRY(0x10de002d, "Tegra186 HDMI/DP0", patch_tegra_hdmi), 4511 HDA_CODEC_ENTRY(0x10de002e, "Tegra186 HDMI/DP1", patch_tegra_hdmi), 4512 HDA_CODEC_ENTRY(0x10de002f, "Tegra194 HDMI/DP2", patch_tegra_hdmi), 4513 HDA_CODEC_ENTRY(0x10de0030, "Tegra194 HDMI/DP3", patch_tegra_hdmi), 4514 HDA_CODEC_ENTRY(0x10de0031, "Tegra234 HDMI/DP", patch_tegra234_hdmi), 4515 HDA_CODEC_ENTRY(0x10de0040, "GPU 40 HDMI/DP", patch_nvhdmi), 4516 HDA_CODEC_ENTRY(0x10de0041, "GPU 41 HDMI/DP", patch_nvhdmi), 4517 HDA_CODEC_ENTRY(0x10de0042, "GPU 42 HDMI/DP", patch_nvhdmi), 4518 HDA_CODEC_ENTRY(0x10de0043, "GPU 43 HDMI/DP", patch_nvhdmi), 4519 HDA_CODEC_ENTRY(0x10de0044, "GPU 44 HDMI/DP", patch_nvhdmi), 4520 HDA_CODEC_ENTRY(0x10de0045, "GPU 45 HDMI/DP", patch_nvhdmi), 4521 HDA_CODEC_ENTRY(0x10de0050, "GPU 50 HDMI/DP", patch_nvhdmi), 4522 HDA_CODEC_ENTRY(0x10de0051, "GPU 51 HDMI/DP", patch_nvhdmi), 4523 HDA_CODEC_ENTRY(0x10de0052, "GPU 52 HDMI/DP", patch_nvhdmi), 4524 HDA_CODEC_ENTRY(0x10de0060, "GPU 60 HDMI/DP", patch_nvhdmi), 4525 HDA_CODEC_ENTRY(0x10de0061, "GPU 61 HDMI/DP", patch_nvhdmi), 4526 HDA_CODEC_ENTRY(0x10de0062, "GPU 62 HDMI/DP", patch_nvhdmi), 4527 HDA_CODEC_ENTRY(0x10de0067, "MCP67 HDMI", patch_nvhdmi_2ch), 4528 HDA_CODEC_ENTRY(0x10de0070, "GPU 70 HDMI/DP", patch_nvhdmi), 4529 HDA_CODEC_ENTRY(0x10de0071, "GPU 71 HDMI/DP", patch_nvhdmi), 4530 HDA_CODEC_ENTRY(0x10de0072, "GPU 72 HDMI/DP", patch_nvhdmi), 4531 HDA_CODEC_ENTRY(0x10de0073, "GPU 73 HDMI/DP", patch_nvhdmi), 4532 HDA_CODEC_ENTRY(0x10de0074, "GPU 74 HDMI/DP", patch_nvhdmi), 4533 HDA_CODEC_ENTRY(0x10de0076, "GPU 76 HDMI/DP", patch_nvhdmi), 4534 HDA_CODEC_ENTRY(0x10de007b, "GPU 7b HDMI/DP", patch_nvhdmi), 4535 HDA_CODEC_ENTRY(0x10de007c, "GPU 7c HDMI/DP", patch_nvhdmi), 4536 HDA_CODEC_ENTRY(0x10de007d, "GPU 7d HDMI/DP", patch_nvhdmi), 4537 HDA_CODEC_ENTRY(0x10de007e, "GPU 7e HDMI/DP", patch_nvhdmi), 4538 HDA_CODEC_ENTRY(0x10de0080, "GPU 80 HDMI/DP", patch_nvhdmi), 4539 HDA_CODEC_ENTRY(0x10de0081, "GPU 81 HDMI/DP", patch_nvhdmi), 4540 HDA_CODEC_ENTRY(0x10de0082, "GPU 82 HDMI/DP", patch_nvhdmi), 4541 HDA_CODEC_ENTRY(0x10de0083, "GPU 83 HDMI/DP", patch_nvhdmi), 4542 HDA_CODEC_ENTRY(0x10de0084, "GPU 84 HDMI/DP", patch_nvhdmi), 4543 HDA_CODEC_ENTRY(0x10de0090, "GPU 90 HDMI/DP", patch_nvhdmi), 4544 HDA_CODEC_ENTRY(0x10de0091, "GPU 91 HDMI/DP", patch_nvhdmi), 4545 HDA_CODEC_ENTRY(0x10de0092, "GPU 92 HDMI/DP", patch_nvhdmi), 4546 HDA_CODEC_ENTRY(0x10de0093, "GPU 93 HDMI/DP", patch_nvhdmi), 4547 HDA_CODEC_ENTRY(0x10de0094, "GPU 94 HDMI/DP", patch_nvhdmi), 4548 HDA_CODEC_ENTRY(0x10de0095, "GPU 95 HDMI/DP", patch_nvhdmi), 4549 HDA_CODEC_ENTRY(0x10de0097, "GPU 97 HDMI/DP", patch_nvhdmi), 4550 HDA_CODEC_ENTRY(0x10de0098, "GPU 98 HDMI/DP", patch_nvhdmi), 4551 HDA_CODEC_ENTRY(0x10de0099, "GPU 99 HDMI/DP", patch_nvhdmi), 4552 HDA_CODEC_ENTRY(0x10de009a, "GPU 9a HDMI/DP", patch_nvhdmi), 4553 HDA_CODEC_ENTRY(0x10de009d, "GPU 9d HDMI/DP", patch_nvhdmi), 4554 HDA_CODEC_ENTRY(0x10de009e, "GPU 9e HDMI/DP", patch_nvhdmi), 4555 HDA_CODEC_ENTRY(0x10de009f, "GPU 9f HDMI/DP", patch_nvhdmi), 4556 HDA_CODEC_ENTRY(0x10de00a0, "GPU a0 HDMI/DP", patch_nvhdmi), 4557 HDA_CODEC_ENTRY(0x10de8001, "MCP73 HDMI", patch_nvhdmi_2ch), 4558 HDA_CODEC_ENTRY(0x10de8067, "MCP67/68 HDMI", patch_nvhdmi_2ch), 4559 HDA_CODEC_ENTRY(0x11069f80, "VX900 HDMI/DP", patch_via_hdmi), 4560 HDA_CODEC_ENTRY(0x11069f81, "VX900 HDMI/DP", patch_via_hdmi), 4561 HDA_CODEC_ENTRY(0x11069f84, "VX11 HDMI/DP", patch_generic_hdmi), 4562 HDA_CODEC_ENTRY(0x11069f85, "VX11 HDMI/DP", patch_generic_hdmi), 4563 HDA_CODEC_ENTRY(0x80860054, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4564 HDA_CODEC_ENTRY(0x80862800, "Geminilake HDMI", patch_i915_glk_hdmi), 4565 HDA_CODEC_ENTRY(0x80862801, "Bearlake HDMI", patch_generic_hdmi), 4566 HDA_CODEC_ENTRY(0x80862802, "Cantiga HDMI", patch_generic_hdmi), 4567 HDA_CODEC_ENTRY(0x80862803, "Eaglelake HDMI", patch_generic_hdmi), 4568 HDA_CODEC_ENTRY(0x80862804, "IbexPeak HDMI", patch_i915_cpt_hdmi), 4569 HDA_CODEC_ENTRY(0x80862805, "CougarPoint HDMI", patch_i915_cpt_hdmi), 4570 HDA_CODEC_ENTRY(0x80862806, "PantherPoint HDMI", patch_i915_cpt_hdmi), 4571 HDA_CODEC_ENTRY(0x80862807, "Haswell HDMI", patch_i915_hsw_hdmi), 4572 HDA_CODEC_ENTRY(0x80862808, "Broadwell HDMI", patch_i915_hsw_hdmi), 4573 HDA_CODEC_ENTRY(0x80862809, "Skylake HDMI", patch_i915_hsw_hdmi), 4574 HDA_CODEC_ENTRY(0x8086280a, "Broxton HDMI", patch_i915_hsw_hdmi), 4575 HDA_CODEC_ENTRY(0x8086280b, "Kabylake HDMI", patch_i915_hsw_hdmi), 4576 HDA_CODEC_ENTRY(0x8086280c, "Cannonlake HDMI", patch_i915_glk_hdmi), 4577 HDA_CODEC_ENTRY(0x8086280d, "Geminilake HDMI", patch_i915_glk_hdmi), 4578 HDA_CODEC_ENTRY(0x8086280f, "Icelake HDMI", patch_i915_icl_hdmi), 4579 HDA_CODEC_ENTRY(0x80862812, "Tigerlake HDMI", patch_i915_tgl_hdmi), 4580 HDA_CODEC_ENTRY(0x80862814, "DG1 HDMI", patch_i915_tgl_hdmi), 4581 HDA_CODEC_ENTRY(0x80862815, "Alderlake HDMI", patch_i915_tgl_hdmi), 4582 HDA_CODEC_ENTRY(0x80862816, "Rocketlake HDMI", patch_i915_tgl_hdmi), 4583 HDA_CODEC_ENTRY(0x80862818, "Raptorlake HDMI", patch_i915_tgl_hdmi), 4584 HDA_CODEC_ENTRY(0x80862819, "DG2 HDMI", patch_i915_adlp_hdmi), 4585 HDA_CODEC_ENTRY(0x8086281a, "Jasperlake HDMI", patch_i915_icl_hdmi), 4586 HDA_CODEC_ENTRY(0x8086281b, "Elkhartlake HDMI", patch_i915_icl_hdmi), 4587 HDA_CODEC_ENTRY(0x8086281c, "Alderlake-P HDMI", patch_i915_adlp_hdmi), 4588 HDA_CODEC_ENTRY(0x8086281f, "Raptorlake-P HDMI", patch_i915_adlp_hdmi), 4589 HDA_CODEC_ENTRY(0x8086281d, "Meteorlake HDMI", patch_i915_adlp_hdmi), 4590 HDA_CODEC_ENTRY(0x80862880, "CedarTrail HDMI", patch_generic_hdmi), 4591 HDA_CODEC_ENTRY(0x80862882, "Valleyview2 HDMI", patch_i915_byt_hdmi), 4592 HDA_CODEC_ENTRY(0x80862883, "Braswell HDMI", patch_i915_byt_hdmi), 4593 HDA_CODEC_ENTRY(0x808629fb, "Crestline HDMI", patch_generic_hdmi), 4594 /* special ID for generic HDMI */ 4595 HDA_CODEC_ENTRY(HDA_CODEC_ID_GENERIC_HDMI, "Generic HDMI", patch_generic_hdmi), 4596 {} /* terminator */ 4597 }; 4598 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_hdmi); 4599 4600 MODULE_LICENSE("GPL"); 4601 MODULE_DESCRIPTION("HDMI HD-audio codec"); 4602 MODULE_ALIAS("snd-hda-codec-intelhdmi"); 4603 MODULE_ALIAS("snd-hda-codec-nvhdmi"); 4604 MODULE_ALIAS("snd-hda-codec-atihdmi"); 4605 4606 static struct hda_codec_driver hdmi_driver = { 4607 .id = snd_hda_id_hdmi, 4608 }; 4609 4610 module_hda_codec_driver(hdmi_driver); 4611