xref: /openbmc/linux/sound/pci/hda/patch_hdmi.c (revision e2f1cf25)
1 /*
2  *
3  *  patch_hdmi.c - routines for HDMI/DisplayPort codecs
4  *
5  *  Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
6  *  Copyright (c) 2006 ATI Technologies Inc.
7  *  Copyright (c) 2008 NVIDIA Corp.  All rights reserved.
8  *  Copyright (c) 2008 Wei Ni <wni@nvidia.com>
9  *  Copyright (c) 2013 Anssi Hannula <anssi.hannula@iki.fi>
10  *
11  *  Authors:
12  *			Wu Fengguang <wfg@linux.intel.com>
13  *
14  *  Maintained by:
15  *			Wu Fengguang <wfg@linux.intel.com>
16  *
17  *  This program is free software; you can redistribute it and/or modify it
18  *  under the terms of the GNU General Public License as published by the Free
19  *  Software Foundation; either version 2 of the License, or (at your option)
20  *  any later version.
21  *
22  *  This program is distributed in the hope that it will be useful, but
23  *  WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
24  *  or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
25  *  for more details.
26  *
27  *  You should have received a copy of the GNU General Public License
28  *  along with this program; if not, write to the Free Software Foundation,
29  *  Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
30  */
31 
32 #include <linux/init.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/module.h>
36 #include <sound/core.h>
37 #include <sound/jack.h>
38 #include <sound/asoundef.h>
39 #include <sound/tlv.h>
40 #include "hda_codec.h"
41 #include "hda_local.h"
42 #include "hda_jack.h"
43 
44 static bool static_hdmi_pcm;
45 module_param(static_hdmi_pcm, bool, 0644);
46 MODULE_PARM_DESC(static_hdmi_pcm, "Don't restrict PCM parameters per ELD info");
47 
48 #define is_haswell(codec)  ((codec)->core.vendor_id == 0x80862807)
49 #define is_broadwell(codec)    ((codec)->core.vendor_id == 0x80862808)
50 #define is_skylake(codec) ((codec)->core.vendor_id == 0x80862809)
51 #define is_haswell_plus(codec) (is_haswell(codec) || is_broadwell(codec) \
52 					|| is_skylake(codec))
53 
54 #define is_valleyview(codec) ((codec)->core.vendor_id == 0x80862882)
55 #define is_cherryview(codec) ((codec)->core.vendor_id == 0x80862883)
56 #define is_valleyview_plus(codec) (is_valleyview(codec) || is_cherryview(codec))
57 
58 struct hdmi_spec_per_cvt {
59 	hda_nid_t cvt_nid;
60 	int assigned;
61 	unsigned int channels_min;
62 	unsigned int channels_max;
63 	u32 rates;
64 	u64 formats;
65 	unsigned int maxbps;
66 };
67 
68 /* max. connections to a widget */
69 #define HDA_MAX_CONNECTIONS	32
70 
71 struct hdmi_spec_per_pin {
72 	hda_nid_t pin_nid;
73 	int num_mux_nids;
74 	hda_nid_t mux_nids[HDA_MAX_CONNECTIONS];
75 	int mux_idx;
76 	hda_nid_t cvt_nid;
77 
78 	struct hda_codec *codec;
79 	struct hdmi_eld sink_eld;
80 	struct mutex lock;
81 	struct delayed_work work;
82 	struct snd_kcontrol *eld_ctl;
83 	int repoll_count;
84 	bool setup; /* the stream has been set up by prepare callback */
85 	int channels; /* current number of channels */
86 	bool non_pcm;
87 	bool chmap_set;		/* channel-map override by ALSA API? */
88 	unsigned char chmap[8]; /* ALSA API channel-map */
89 #ifdef CONFIG_SND_PROC_FS
90 	struct snd_info_entry *proc_entry;
91 #endif
92 };
93 
94 struct cea_channel_speaker_allocation;
95 
96 /* operations used by generic code that can be overridden by patches */
97 struct hdmi_ops {
98 	int (*pin_get_eld)(struct hda_codec *codec, hda_nid_t pin_nid,
99 			   unsigned char *buf, int *eld_size);
100 
101 	/* get and set channel assigned to each HDMI ASP (audio sample packet) slot */
102 	int (*pin_get_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
103 				    int asp_slot);
104 	int (*pin_set_slot_channel)(struct hda_codec *codec, hda_nid_t pin_nid,
105 				    int asp_slot, int channel);
106 
107 	void (*pin_setup_infoframe)(struct hda_codec *codec, hda_nid_t pin_nid,
108 				    int ca, int active_channels, int conn_type);
109 
110 	/* enable/disable HBR (HD passthrough) */
111 	int (*pin_hbr_setup)(struct hda_codec *codec, hda_nid_t pin_nid, bool hbr);
112 
113 	int (*setup_stream)(struct hda_codec *codec, hda_nid_t cvt_nid,
114 			    hda_nid_t pin_nid, u32 stream_tag, int format);
115 
116 	/* Helpers for producing the channel map TLVs. These can be overridden
117 	 * for devices that have non-standard mapping requirements. */
118 	int (*chmap_cea_alloc_validate_get_type)(struct cea_channel_speaker_allocation *cap,
119 						 int channels);
120 	void (*cea_alloc_to_tlv_chmap)(struct cea_channel_speaker_allocation *cap,
121 				       unsigned int *chmap, int channels);
122 
123 	/* check that the user-given chmap is supported */
124 	int (*chmap_validate)(int ca, int channels, unsigned char *chmap);
125 };
126 
127 struct hdmi_spec {
128 	int num_cvts;
129 	struct snd_array cvts; /* struct hdmi_spec_per_cvt */
130 	hda_nid_t cvt_nids[4]; /* only for haswell fix */
131 
132 	int num_pins;
133 	struct snd_array pins; /* struct hdmi_spec_per_pin */
134 	struct hda_pcm *pcm_rec[16];
135 	unsigned int channels_max; /* max over all cvts */
136 
137 	struct hdmi_eld temp_eld;
138 	struct hdmi_ops ops;
139 
140 	bool dyn_pin_out;
141 
142 	/*
143 	 * Non-generic VIA/NVIDIA specific
144 	 */
145 	struct hda_multi_out multiout;
146 	struct hda_pcm_stream pcm_playback;
147 };
148 
149 
150 struct hdmi_audio_infoframe {
151 	u8 type; /* 0x84 */
152 	u8 ver;  /* 0x01 */
153 	u8 len;  /* 0x0a */
154 
155 	u8 checksum;
156 
157 	u8 CC02_CT47;	/* CC in bits 0:2, CT in 4:7 */
158 	u8 SS01_SF24;
159 	u8 CXT04;
160 	u8 CA;
161 	u8 LFEPBL01_LSV36_DM_INH7;
162 };
163 
164 struct dp_audio_infoframe {
165 	u8 type; /* 0x84 */
166 	u8 len;  /* 0x1b */
167 	u8 ver;  /* 0x11 << 2 */
168 
169 	u8 CC02_CT47;	/* match with HDMI infoframe from this on */
170 	u8 SS01_SF24;
171 	u8 CXT04;
172 	u8 CA;
173 	u8 LFEPBL01_LSV36_DM_INH7;
174 };
175 
176 union audio_infoframe {
177 	struct hdmi_audio_infoframe hdmi;
178 	struct dp_audio_infoframe dp;
179 	u8 bytes[0];
180 };
181 
182 /*
183  * CEA speaker placement:
184  *
185  *        FLH       FCH        FRH
186  *  FLW    FL  FLC   FC   FRC   FR   FRW
187  *
188  *                                  LFE
189  *                     TC
190  *
191  *          RL  RLC   RC   RRC   RR
192  *
193  * The Left/Right Surround channel _notions_ LS/RS in SMPTE 320M corresponds to
194  * CEA RL/RR; The SMPTE channel _assignment_ C/LFE is swapped to CEA LFE/FC.
195  */
196 enum cea_speaker_placement {
197 	FL  = (1 <<  0),	/* Front Left           */
198 	FC  = (1 <<  1),	/* Front Center         */
199 	FR  = (1 <<  2),	/* Front Right          */
200 	FLC = (1 <<  3),	/* Front Left Center    */
201 	FRC = (1 <<  4),	/* Front Right Center   */
202 	RL  = (1 <<  5),	/* Rear Left            */
203 	RC  = (1 <<  6),	/* Rear Center          */
204 	RR  = (1 <<  7),	/* Rear Right           */
205 	RLC = (1 <<  8),	/* Rear Left Center     */
206 	RRC = (1 <<  9),	/* Rear Right Center    */
207 	LFE = (1 << 10),	/* Low Frequency Effect */
208 	FLW = (1 << 11),	/* Front Left Wide      */
209 	FRW = (1 << 12),	/* Front Right Wide     */
210 	FLH = (1 << 13),	/* Front Left High      */
211 	FCH = (1 << 14),	/* Front Center High    */
212 	FRH = (1 << 15),	/* Front Right High     */
213 	TC  = (1 << 16),	/* Top Center           */
214 };
215 
216 /*
217  * ELD SA bits in the CEA Speaker Allocation data block
218  */
219 static int eld_speaker_allocation_bits[] = {
220 	[0] = FL | FR,
221 	[1] = LFE,
222 	[2] = FC,
223 	[3] = RL | RR,
224 	[4] = RC,
225 	[5] = FLC | FRC,
226 	[6] = RLC | RRC,
227 	/* the following are not defined in ELD yet */
228 	[7] = FLW | FRW,
229 	[8] = FLH | FRH,
230 	[9] = TC,
231 	[10] = FCH,
232 };
233 
234 struct cea_channel_speaker_allocation {
235 	int ca_index;
236 	int speakers[8];
237 
238 	/* derived values, just for convenience */
239 	int channels;
240 	int spk_mask;
241 };
242 
243 /*
244  * ALSA sequence is:
245  *
246  *       surround40   surround41   surround50   surround51   surround71
247  * ch0   front left   =            =            =            =
248  * ch1   front right  =            =            =            =
249  * ch2   rear left    =            =            =            =
250  * ch3   rear right   =            =            =            =
251  * ch4                LFE          center       center       center
252  * ch5                                          LFE          LFE
253  * ch6                                                       side left
254  * ch7                                                       side right
255  *
256  * surround71 = {FL, FR, RLC, RRC, FC, LFE, RL, RR}
257  */
258 static int hdmi_channel_mapping[0x32][8] = {
259 	/* stereo */
260 	[0x00] = { 0x00, 0x11, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
261 	/* 2.1 */
262 	[0x01] = { 0x00, 0x11, 0x22, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7 },
263 	/* Dolby Surround */
264 	[0x02] = { 0x00, 0x11, 0x23, 0xf2, 0xf4, 0xf5, 0xf6, 0xf7 },
265 	/* surround40 */
266 	[0x08] = { 0x00, 0x11, 0x24, 0x35, 0xf3, 0xf2, 0xf6, 0xf7 },
267 	/* 4ch */
268 	[0x03] = { 0x00, 0x11, 0x23, 0x32, 0x44, 0xf5, 0xf6, 0xf7 },
269 	/* surround41 */
270 	[0x09] = { 0x00, 0x11, 0x24, 0x35, 0x42, 0xf3, 0xf6, 0xf7 },
271 	/* surround50 */
272 	[0x0a] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0xf2, 0xf6, 0xf7 },
273 	/* surround51 */
274 	[0x0b] = { 0x00, 0x11, 0x24, 0x35, 0x43, 0x52, 0xf6, 0xf7 },
275 	/* 7.1 */
276 	[0x13] = { 0x00, 0x11, 0x26, 0x37, 0x43, 0x52, 0x64, 0x75 },
277 };
278 
279 /*
280  * This is an ordered list!
281  *
282  * The preceding ones have better chances to be selected by
283  * hdmi_channel_allocation().
284  */
285 static struct cea_channel_speaker_allocation channel_allocations[] = {
286 /*			  channel:   7     6    5    4    3     2    1    0  */
287 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
288 				 /* 2.1 */
289 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
290 				 /* Dolby Surround */
291 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
292 				 /* surround40 */
293 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
294 				 /* surround41 */
295 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
296 				 /* surround50 */
297 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
298 				 /* surround51 */
299 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
300 				 /* 6.1 */
301 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
302 				 /* surround71 */
303 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
304 
305 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
306 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
307 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
308 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
309 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
310 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
311 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
312 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
313 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
314 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
315 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
316 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
317 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
318 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
319 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
320 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
321 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
322 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
323 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
324 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
325 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
326 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
327 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
328 { .ca_index = 0x20,  .speakers = {   0,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
329 { .ca_index = 0x21,  .speakers = {   0,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
330 { .ca_index = 0x22,  .speakers = {  TC,    0,  RR,  RL,  FC,    0,  FR,  FL } },
331 { .ca_index = 0x23,  .speakers = {  TC,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
332 { .ca_index = 0x24,  .speakers = { FRH,  FLH,  RR,  RL,   0,    0,  FR,  FL } },
333 { .ca_index = 0x25,  .speakers = { FRH,  FLH,  RR,  RL,   0,  LFE,  FR,  FL } },
334 { .ca_index = 0x26,  .speakers = { FRW,  FLW,  RR,  RL,   0,    0,  FR,  FL } },
335 { .ca_index = 0x27,  .speakers = { FRW,  FLW,  RR,  RL,   0,  LFE,  FR,  FL } },
336 { .ca_index = 0x28,  .speakers = {  TC,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
337 { .ca_index = 0x29,  .speakers = {  TC,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
338 { .ca_index = 0x2a,  .speakers = { FCH,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
339 { .ca_index = 0x2b,  .speakers = { FCH,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
340 { .ca_index = 0x2c,  .speakers = {  TC,  FCH,  RR,  RL,  FC,    0,  FR,  FL } },
341 { .ca_index = 0x2d,  .speakers = {  TC,  FCH,  RR,  RL,  FC,  LFE,  FR,  FL } },
342 { .ca_index = 0x2e,  .speakers = { FRH,  FLH,  RR,  RL,  FC,    0,  FR,  FL } },
343 { .ca_index = 0x2f,  .speakers = { FRH,  FLH,  RR,  RL,  FC,  LFE,  FR,  FL } },
344 { .ca_index = 0x30,  .speakers = { FRW,  FLW,  RR,  RL,  FC,    0,  FR,  FL } },
345 { .ca_index = 0x31,  .speakers = { FRW,  FLW,  RR,  RL,  FC,  LFE,  FR,  FL } },
346 };
347 
348 
349 /*
350  * HDMI routines
351  */
352 
353 #define get_pin(spec, idx) \
354 	((struct hdmi_spec_per_pin *)snd_array_elem(&spec->pins, idx))
355 #define get_cvt(spec, idx) \
356 	((struct hdmi_spec_per_cvt  *)snd_array_elem(&spec->cvts, idx))
357 #define get_pcm_rec(spec, idx)	((spec)->pcm_rec[idx])
358 
359 static int pin_nid_to_pin_index(struct hda_codec *codec, hda_nid_t pin_nid)
360 {
361 	struct hdmi_spec *spec = codec->spec;
362 	int pin_idx;
363 
364 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
365 		if (get_pin(spec, pin_idx)->pin_nid == pin_nid)
366 			return pin_idx;
367 
368 	codec_warn(codec, "HDMI: pin nid %d not registered\n", pin_nid);
369 	return -EINVAL;
370 }
371 
372 static int hinfo_to_pin_index(struct hda_codec *codec,
373 			      struct hda_pcm_stream *hinfo)
374 {
375 	struct hdmi_spec *spec = codec->spec;
376 	int pin_idx;
377 
378 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++)
379 		if (get_pcm_rec(spec, pin_idx)->stream == hinfo)
380 			return pin_idx;
381 
382 	codec_warn(codec, "HDMI: hinfo %p not registered\n", hinfo);
383 	return -EINVAL;
384 }
385 
386 static int cvt_nid_to_cvt_index(struct hda_codec *codec, hda_nid_t cvt_nid)
387 {
388 	struct hdmi_spec *spec = codec->spec;
389 	int cvt_idx;
390 
391 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++)
392 		if (get_cvt(spec, cvt_idx)->cvt_nid == cvt_nid)
393 			return cvt_idx;
394 
395 	codec_warn(codec, "HDMI: cvt nid %d not registered\n", cvt_nid);
396 	return -EINVAL;
397 }
398 
399 static int hdmi_eld_ctl_info(struct snd_kcontrol *kcontrol,
400 			struct snd_ctl_elem_info *uinfo)
401 {
402 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
403 	struct hdmi_spec *spec = codec->spec;
404 	struct hdmi_spec_per_pin *per_pin;
405 	struct hdmi_eld *eld;
406 	int pin_idx;
407 
408 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
409 
410 	pin_idx = kcontrol->private_value;
411 	per_pin = get_pin(spec, pin_idx);
412 	eld = &per_pin->sink_eld;
413 
414 	mutex_lock(&per_pin->lock);
415 	uinfo->count = eld->eld_valid ? eld->eld_size : 0;
416 	mutex_unlock(&per_pin->lock);
417 
418 	return 0;
419 }
420 
421 static int hdmi_eld_ctl_get(struct snd_kcontrol *kcontrol,
422 			struct snd_ctl_elem_value *ucontrol)
423 {
424 	struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
425 	struct hdmi_spec *spec = codec->spec;
426 	struct hdmi_spec_per_pin *per_pin;
427 	struct hdmi_eld *eld;
428 	int pin_idx;
429 
430 	pin_idx = kcontrol->private_value;
431 	per_pin = get_pin(spec, pin_idx);
432 	eld = &per_pin->sink_eld;
433 
434 	mutex_lock(&per_pin->lock);
435 	if (eld->eld_size > ARRAY_SIZE(ucontrol->value.bytes.data)) {
436 		mutex_unlock(&per_pin->lock);
437 		snd_BUG();
438 		return -EINVAL;
439 	}
440 
441 	memset(ucontrol->value.bytes.data, 0,
442 	       ARRAY_SIZE(ucontrol->value.bytes.data));
443 	if (eld->eld_valid)
444 		memcpy(ucontrol->value.bytes.data, eld->eld_buffer,
445 		       eld->eld_size);
446 	mutex_unlock(&per_pin->lock);
447 
448 	return 0;
449 }
450 
451 static struct snd_kcontrol_new eld_bytes_ctl = {
452 	.access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
453 	.iface = SNDRV_CTL_ELEM_IFACE_PCM,
454 	.name = "ELD",
455 	.info = hdmi_eld_ctl_info,
456 	.get = hdmi_eld_ctl_get,
457 };
458 
459 static int hdmi_create_eld_ctl(struct hda_codec *codec, int pin_idx,
460 			int device)
461 {
462 	struct snd_kcontrol *kctl;
463 	struct hdmi_spec *spec = codec->spec;
464 	int err;
465 
466 	kctl = snd_ctl_new1(&eld_bytes_ctl, codec);
467 	if (!kctl)
468 		return -ENOMEM;
469 	kctl->private_value = pin_idx;
470 	kctl->id.device = device;
471 
472 	err = snd_hda_ctl_add(codec, get_pin(spec, pin_idx)->pin_nid, kctl);
473 	if (err < 0)
474 		return err;
475 
476 	get_pin(spec, pin_idx)->eld_ctl = kctl;
477 	return 0;
478 }
479 
480 #ifdef BE_PARANOID
481 static void hdmi_get_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
482 				int *packet_index, int *byte_index)
483 {
484 	int val;
485 
486 	val = snd_hda_codec_read(codec, pin_nid, 0,
487 				 AC_VERB_GET_HDMI_DIP_INDEX, 0);
488 
489 	*packet_index = val >> 5;
490 	*byte_index = val & 0x1f;
491 }
492 #endif
493 
494 static void hdmi_set_dip_index(struct hda_codec *codec, hda_nid_t pin_nid,
495 				int packet_index, int byte_index)
496 {
497 	int val;
498 
499 	val = (packet_index << 5) | (byte_index & 0x1f);
500 
501 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_INDEX, val);
502 }
503 
504 static void hdmi_write_dip_byte(struct hda_codec *codec, hda_nid_t pin_nid,
505 				unsigned char val)
506 {
507 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_DATA, val);
508 }
509 
510 static void hdmi_init_pin(struct hda_codec *codec, hda_nid_t pin_nid)
511 {
512 	struct hdmi_spec *spec = codec->spec;
513 	int pin_out;
514 
515 	/* Unmute */
516 	if (get_wcaps(codec, pin_nid) & AC_WCAP_OUT_AMP)
517 		snd_hda_codec_write(codec, pin_nid, 0,
518 				AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_UNMUTE);
519 
520 	if (spec->dyn_pin_out)
521 		/* Disable pin out until stream is active */
522 		pin_out = 0;
523 	else
524 		/* Enable pin out: some machines with GM965 gets broken output
525 		 * when the pin is disabled or changed while using with HDMI
526 		 */
527 		pin_out = PIN_OUT;
528 
529 	snd_hda_codec_write(codec, pin_nid, 0,
530 			    AC_VERB_SET_PIN_WIDGET_CONTROL, pin_out);
531 }
532 
533 static int hdmi_get_channel_count(struct hda_codec *codec, hda_nid_t cvt_nid)
534 {
535 	return 1 + snd_hda_codec_read(codec, cvt_nid, 0,
536 					AC_VERB_GET_CVT_CHAN_COUNT, 0);
537 }
538 
539 static void hdmi_set_channel_count(struct hda_codec *codec,
540 				   hda_nid_t cvt_nid, int chs)
541 {
542 	if (chs != hdmi_get_channel_count(codec, cvt_nid))
543 		snd_hda_codec_write(codec, cvt_nid, 0,
544 				    AC_VERB_SET_CVT_CHAN_COUNT, chs - 1);
545 }
546 
547 /*
548  * ELD proc files
549  */
550 
551 #ifdef CONFIG_SND_PROC_FS
552 static void print_eld_info(struct snd_info_entry *entry,
553 			   struct snd_info_buffer *buffer)
554 {
555 	struct hdmi_spec_per_pin *per_pin = entry->private_data;
556 
557 	mutex_lock(&per_pin->lock);
558 	snd_hdmi_print_eld_info(&per_pin->sink_eld, buffer);
559 	mutex_unlock(&per_pin->lock);
560 }
561 
562 static void write_eld_info(struct snd_info_entry *entry,
563 			   struct snd_info_buffer *buffer)
564 {
565 	struct hdmi_spec_per_pin *per_pin = entry->private_data;
566 
567 	mutex_lock(&per_pin->lock);
568 	snd_hdmi_write_eld_info(&per_pin->sink_eld, buffer);
569 	mutex_unlock(&per_pin->lock);
570 }
571 
572 static int eld_proc_new(struct hdmi_spec_per_pin *per_pin, int index)
573 {
574 	char name[32];
575 	struct hda_codec *codec = per_pin->codec;
576 	struct snd_info_entry *entry;
577 	int err;
578 
579 	snprintf(name, sizeof(name), "eld#%d.%d", codec->addr, index);
580 	err = snd_card_proc_new(codec->card, name, &entry);
581 	if (err < 0)
582 		return err;
583 
584 	snd_info_set_text_ops(entry, per_pin, print_eld_info);
585 	entry->c.text.write = write_eld_info;
586 	entry->mode |= S_IWUSR;
587 	per_pin->proc_entry = entry;
588 
589 	return 0;
590 }
591 
592 static void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
593 {
594 	if (!per_pin->codec->bus->shutdown) {
595 		snd_info_free_entry(per_pin->proc_entry);
596 		per_pin->proc_entry = NULL;
597 	}
598 }
599 #else
600 static inline int eld_proc_new(struct hdmi_spec_per_pin *per_pin,
601 			       int index)
602 {
603 	return 0;
604 }
605 static inline void eld_proc_free(struct hdmi_spec_per_pin *per_pin)
606 {
607 }
608 #endif
609 
610 /*
611  * Channel mapping routines
612  */
613 
614 /*
615  * Compute derived values in channel_allocations[].
616  */
617 static void init_channel_allocations(void)
618 {
619 	int i, j;
620 	struct cea_channel_speaker_allocation *p;
621 
622 	for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
623 		p = channel_allocations + i;
624 		p->channels = 0;
625 		p->spk_mask = 0;
626 		for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
627 			if (p->speakers[j]) {
628 				p->channels++;
629 				p->spk_mask |= p->speakers[j];
630 			}
631 	}
632 }
633 
634 static int get_channel_allocation_order(int ca)
635 {
636 	int i;
637 
638 	for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
639 		if (channel_allocations[i].ca_index == ca)
640 			break;
641 	}
642 	return i;
643 }
644 
645 /*
646  * The transformation takes two steps:
647  *
648  *	eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
649  *	      spk_mask => (channel_allocations[])         => ai->CA
650  *
651  * TODO: it could select the wrong CA from multiple candidates.
652 */
653 static int hdmi_channel_allocation(struct hda_codec *codec,
654 				   struct hdmi_eld *eld, int channels)
655 {
656 	int i;
657 	int ca = 0;
658 	int spk_mask = 0;
659 	char buf[SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE];
660 
661 	/*
662 	 * CA defaults to 0 for basic stereo audio
663 	 */
664 	if (channels <= 2)
665 		return 0;
666 
667 	/*
668 	 * expand ELD's speaker allocation mask
669 	 *
670 	 * ELD tells the speaker mask in a compact(paired) form,
671 	 * expand ELD's notions to match the ones used by Audio InfoFrame.
672 	 */
673 	for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
674 		if (eld->info.spk_alloc & (1 << i))
675 			spk_mask |= eld_speaker_allocation_bits[i];
676 	}
677 
678 	/* search for the first working match in the CA table */
679 	for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
680 		if (channels == channel_allocations[i].channels &&
681 		    (spk_mask & channel_allocations[i].spk_mask) ==
682 				channel_allocations[i].spk_mask) {
683 			ca = channel_allocations[i].ca_index;
684 			break;
685 		}
686 	}
687 
688 	if (!ca) {
689 		/* if there was no match, select the regular ALSA channel
690 		 * allocation with the matching number of channels */
691 		for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
692 			if (channels == channel_allocations[i].channels) {
693 				ca = channel_allocations[i].ca_index;
694 				break;
695 			}
696 		}
697 	}
698 
699 	snd_print_channel_allocation(eld->info.spk_alloc, buf, sizeof(buf));
700 	codec_dbg(codec, "HDMI: select CA 0x%x for %d-channel allocation: %s\n",
701 		    ca, channels, buf);
702 
703 	return ca;
704 }
705 
706 static void hdmi_debug_channel_mapping(struct hda_codec *codec,
707 				       hda_nid_t pin_nid)
708 {
709 #ifdef CONFIG_SND_DEBUG_VERBOSE
710 	struct hdmi_spec *spec = codec->spec;
711 	int i;
712 	int channel;
713 
714 	for (i = 0; i < 8; i++) {
715 		channel = spec->ops.pin_get_slot_channel(codec, pin_nid, i);
716 		codec_dbg(codec, "HDMI: ASP channel %d => slot %d\n",
717 						channel, i);
718 	}
719 #endif
720 }
721 
722 static void hdmi_std_setup_channel_mapping(struct hda_codec *codec,
723 				       hda_nid_t pin_nid,
724 				       bool non_pcm,
725 				       int ca)
726 {
727 	struct hdmi_spec *spec = codec->spec;
728 	struct cea_channel_speaker_allocation *ch_alloc;
729 	int i;
730 	int err;
731 	int order;
732 	int non_pcm_mapping[8];
733 
734 	order = get_channel_allocation_order(ca);
735 	ch_alloc = &channel_allocations[order];
736 
737 	if (hdmi_channel_mapping[ca][1] == 0) {
738 		int hdmi_slot = 0;
739 		/* fill actual channel mappings in ALSA channel (i) order */
740 		for (i = 0; i < ch_alloc->channels; i++) {
741 			while (!ch_alloc->speakers[7 - hdmi_slot] && !WARN_ON(hdmi_slot >= 8))
742 				hdmi_slot++; /* skip zero slots */
743 
744 			hdmi_channel_mapping[ca][i] = (i << 4) | hdmi_slot++;
745 		}
746 		/* fill the rest of the slots with ALSA channel 0xf */
747 		for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++)
748 			if (!ch_alloc->speakers[7 - hdmi_slot])
749 				hdmi_channel_mapping[ca][i++] = (0xf << 4) | hdmi_slot;
750 	}
751 
752 	if (non_pcm) {
753 		for (i = 0; i < ch_alloc->channels; i++)
754 			non_pcm_mapping[i] = (i << 4) | i;
755 		for (; i < 8; i++)
756 			non_pcm_mapping[i] = (0xf << 4) | i;
757 	}
758 
759 	for (i = 0; i < 8; i++) {
760 		int slotsetup = non_pcm ? non_pcm_mapping[i] : hdmi_channel_mapping[ca][i];
761 		int hdmi_slot = slotsetup & 0x0f;
762 		int channel = (slotsetup & 0xf0) >> 4;
763 		err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot, channel);
764 		if (err) {
765 			codec_dbg(codec, "HDMI: channel mapping failed\n");
766 			break;
767 		}
768 	}
769 }
770 
771 struct channel_map_table {
772 	unsigned char map;		/* ALSA API channel map position */
773 	int spk_mask;			/* speaker position bit mask */
774 };
775 
776 static struct channel_map_table map_tables[] = {
777 	{ SNDRV_CHMAP_FL,	FL },
778 	{ SNDRV_CHMAP_FR,	FR },
779 	{ SNDRV_CHMAP_RL,	RL },
780 	{ SNDRV_CHMAP_RR,	RR },
781 	{ SNDRV_CHMAP_LFE,	LFE },
782 	{ SNDRV_CHMAP_FC,	FC },
783 	{ SNDRV_CHMAP_RLC,	RLC },
784 	{ SNDRV_CHMAP_RRC,	RRC },
785 	{ SNDRV_CHMAP_RC,	RC },
786 	{ SNDRV_CHMAP_FLC,	FLC },
787 	{ SNDRV_CHMAP_FRC,	FRC },
788 	{ SNDRV_CHMAP_TFL,	FLH },
789 	{ SNDRV_CHMAP_TFR,	FRH },
790 	{ SNDRV_CHMAP_FLW,	FLW },
791 	{ SNDRV_CHMAP_FRW,	FRW },
792 	{ SNDRV_CHMAP_TC,	TC },
793 	{ SNDRV_CHMAP_TFC,	FCH },
794 	{} /* terminator */
795 };
796 
797 /* from ALSA API channel position to speaker bit mask */
798 static int to_spk_mask(unsigned char c)
799 {
800 	struct channel_map_table *t = map_tables;
801 	for (; t->map; t++) {
802 		if (t->map == c)
803 			return t->spk_mask;
804 	}
805 	return 0;
806 }
807 
808 /* from ALSA API channel position to CEA slot */
809 static int to_cea_slot(int ordered_ca, unsigned char pos)
810 {
811 	int mask = to_spk_mask(pos);
812 	int i;
813 
814 	if (mask) {
815 		for (i = 0; i < 8; i++) {
816 			if (channel_allocations[ordered_ca].speakers[7 - i] == mask)
817 				return i;
818 		}
819 	}
820 
821 	return -1;
822 }
823 
824 /* from speaker bit mask to ALSA API channel position */
825 static int spk_to_chmap(int spk)
826 {
827 	struct channel_map_table *t = map_tables;
828 	for (; t->map; t++) {
829 		if (t->spk_mask == spk)
830 			return t->map;
831 	}
832 	return 0;
833 }
834 
835 /* from CEA slot to ALSA API channel position */
836 static int from_cea_slot(int ordered_ca, unsigned char slot)
837 {
838 	int mask = channel_allocations[ordered_ca].speakers[7 - slot];
839 
840 	return spk_to_chmap(mask);
841 }
842 
843 /* get the CA index corresponding to the given ALSA API channel map */
844 static int hdmi_manual_channel_allocation(int chs, unsigned char *map)
845 {
846 	int i, spks = 0, spk_mask = 0;
847 
848 	for (i = 0; i < chs; i++) {
849 		int mask = to_spk_mask(map[i]);
850 		if (mask) {
851 			spk_mask |= mask;
852 			spks++;
853 		}
854 	}
855 
856 	for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
857 		if ((chs == channel_allocations[i].channels ||
858 		     spks == channel_allocations[i].channels) &&
859 		    (spk_mask & channel_allocations[i].spk_mask) ==
860 				channel_allocations[i].spk_mask)
861 			return channel_allocations[i].ca_index;
862 	}
863 	return -1;
864 }
865 
866 /* set up the channel slots for the given ALSA API channel map */
867 static int hdmi_manual_setup_channel_mapping(struct hda_codec *codec,
868 					     hda_nid_t pin_nid,
869 					     int chs, unsigned char *map,
870 					     int ca)
871 {
872 	struct hdmi_spec *spec = codec->spec;
873 	int ordered_ca = get_channel_allocation_order(ca);
874 	int alsa_pos, hdmi_slot;
875 	int assignments[8] = {[0 ... 7] = 0xf};
876 
877 	for (alsa_pos = 0; alsa_pos < chs; alsa_pos++) {
878 
879 		hdmi_slot = to_cea_slot(ordered_ca, map[alsa_pos]);
880 
881 		if (hdmi_slot < 0)
882 			continue; /* unassigned channel */
883 
884 		assignments[hdmi_slot] = alsa_pos;
885 	}
886 
887 	for (hdmi_slot = 0; hdmi_slot < 8; hdmi_slot++) {
888 		int err;
889 
890 		err = spec->ops.pin_set_slot_channel(codec, pin_nid, hdmi_slot,
891 						     assignments[hdmi_slot]);
892 		if (err)
893 			return -EINVAL;
894 	}
895 	return 0;
896 }
897 
898 /* store ALSA API channel map from the current default map */
899 static void hdmi_setup_fake_chmap(unsigned char *map, int ca)
900 {
901 	int i;
902 	int ordered_ca = get_channel_allocation_order(ca);
903 	for (i = 0; i < 8; i++) {
904 		if (i < channel_allocations[ordered_ca].channels)
905 			map[i] = from_cea_slot(ordered_ca, hdmi_channel_mapping[ca][i] & 0x0f);
906 		else
907 			map[i] = 0;
908 	}
909 }
910 
911 static void hdmi_setup_channel_mapping(struct hda_codec *codec,
912 				       hda_nid_t pin_nid, bool non_pcm, int ca,
913 				       int channels, unsigned char *map,
914 				       bool chmap_set)
915 {
916 	if (!non_pcm && chmap_set) {
917 		hdmi_manual_setup_channel_mapping(codec, pin_nid,
918 						  channels, map, ca);
919 	} else {
920 		hdmi_std_setup_channel_mapping(codec, pin_nid, non_pcm, ca);
921 		hdmi_setup_fake_chmap(map, ca);
922 	}
923 
924 	hdmi_debug_channel_mapping(codec, pin_nid);
925 }
926 
927 static int hdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
928 				     int asp_slot, int channel)
929 {
930 	return snd_hda_codec_write(codec, pin_nid, 0,
931 				   AC_VERB_SET_HDMI_CHAN_SLOT,
932 				   (channel << 4) | asp_slot);
933 }
934 
935 static int hdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
936 				     int asp_slot)
937 {
938 	return (snd_hda_codec_read(codec, pin_nid, 0,
939 				   AC_VERB_GET_HDMI_CHAN_SLOT,
940 				   asp_slot) & 0xf0) >> 4;
941 }
942 
943 /*
944  * Audio InfoFrame routines
945  */
946 
947 /*
948  * Enable Audio InfoFrame Transmission
949  */
950 static void hdmi_start_infoframe_trans(struct hda_codec *codec,
951 				       hda_nid_t pin_nid)
952 {
953 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
954 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
955 						AC_DIPXMIT_BEST);
956 }
957 
958 /*
959  * Disable Audio InfoFrame Transmission
960  */
961 static void hdmi_stop_infoframe_trans(struct hda_codec *codec,
962 				      hda_nid_t pin_nid)
963 {
964 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
965 	snd_hda_codec_write(codec, pin_nid, 0, AC_VERB_SET_HDMI_DIP_XMIT,
966 						AC_DIPXMIT_DISABLE);
967 }
968 
969 static void hdmi_debug_dip_size(struct hda_codec *codec, hda_nid_t pin_nid)
970 {
971 #ifdef CONFIG_SND_DEBUG_VERBOSE
972 	int i;
973 	int size;
974 
975 	size = snd_hdmi_get_eld_size(codec, pin_nid);
976 	codec_dbg(codec, "HDMI: ELD buf size is %d\n", size);
977 
978 	for (i = 0; i < 8; i++) {
979 		size = snd_hda_codec_read(codec, pin_nid, 0,
980 						AC_VERB_GET_HDMI_DIP_SIZE, i);
981 		codec_dbg(codec, "HDMI: DIP GP[%d] buf size is %d\n", i, size);
982 	}
983 #endif
984 }
985 
986 static void hdmi_clear_dip_buffers(struct hda_codec *codec, hda_nid_t pin_nid)
987 {
988 #ifdef BE_PARANOID
989 	int i, j;
990 	int size;
991 	int pi, bi;
992 	for (i = 0; i < 8; i++) {
993 		size = snd_hda_codec_read(codec, pin_nid, 0,
994 						AC_VERB_GET_HDMI_DIP_SIZE, i);
995 		if (size == 0)
996 			continue;
997 
998 		hdmi_set_dip_index(codec, pin_nid, i, 0x0);
999 		for (j = 1; j < 1000; j++) {
1000 			hdmi_write_dip_byte(codec, pin_nid, 0x0);
1001 			hdmi_get_dip_index(codec, pin_nid, &pi, &bi);
1002 			if (pi != i)
1003 				codec_dbg(codec, "dip index %d: %d != %d\n",
1004 						bi, pi, i);
1005 			if (bi == 0) /* byte index wrapped around */
1006 				break;
1007 		}
1008 		codec_dbg(codec,
1009 			"HDMI: DIP GP[%d] buf reported size=%d, written=%d\n",
1010 			i, size, j);
1011 	}
1012 #endif
1013 }
1014 
1015 static void hdmi_checksum_audio_infoframe(struct hdmi_audio_infoframe *hdmi_ai)
1016 {
1017 	u8 *bytes = (u8 *)hdmi_ai;
1018 	u8 sum = 0;
1019 	int i;
1020 
1021 	hdmi_ai->checksum = 0;
1022 
1023 	for (i = 0; i < sizeof(*hdmi_ai); i++)
1024 		sum += bytes[i];
1025 
1026 	hdmi_ai->checksum = -sum;
1027 }
1028 
1029 static void hdmi_fill_audio_infoframe(struct hda_codec *codec,
1030 				      hda_nid_t pin_nid,
1031 				      u8 *dip, int size)
1032 {
1033 	int i;
1034 
1035 	hdmi_debug_dip_size(codec, pin_nid);
1036 	hdmi_clear_dip_buffers(codec, pin_nid); /* be paranoid */
1037 
1038 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1039 	for (i = 0; i < size; i++)
1040 		hdmi_write_dip_byte(codec, pin_nid, dip[i]);
1041 }
1042 
1043 static bool hdmi_infoframe_uptodate(struct hda_codec *codec, hda_nid_t pin_nid,
1044 				    u8 *dip, int size)
1045 {
1046 	u8 val;
1047 	int i;
1048 
1049 	if (snd_hda_codec_read(codec, pin_nid, 0, AC_VERB_GET_HDMI_DIP_XMIT, 0)
1050 							    != AC_DIPXMIT_BEST)
1051 		return false;
1052 
1053 	hdmi_set_dip_index(codec, pin_nid, 0x0, 0x0);
1054 	for (i = 0; i < size; i++) {
1055 		val = snd_hda_codec_read(codec, pin_nid, 0,
1056 					 AC_VERB_GET_HDMI_DIP_DATA, 0);
1057 		if (val != dip[i])
1058 			return false;
1059 	}
1060 
1061 	return true;
1062 }
1063 
1064 static void hdmi_pin_setup_infoframe(struct hda_codec *codec,
1065 				     hda_nid_t pin_nid,
1066 				     int ca, int active_channels,
1067 				     int conn_type)
1068 {
1069 	union audio_infoframe ai;
1070 
1071 	memset(&ai, 0, sizeof(ai));
1072 	if (conn_type == 0) { /* HDMI */
1073 		struct hdmi_audio_infoframe *hdmi_ai = &ai.hdmi;
1074 
1075 		hdmi_ai->type		= 0x84;
1076 		hdmi_ai->ver		= 0x01;
1077 		hdmi_ai->len		= 0x0a;
1078 		hdmi_ai->CC02_CT47	= active_channels - 1;
1079 		hdmi_ai->CA		= ca;
1080 		hdmi_checksum_audio_infoframe(hdmi_ai);
1081 	} else if (conn_type == 1) { /* DisplayPort */
1082 		struct dp_audio_infoframe *dp_ai = &ai.dp;
1083 
1084 		dp_ai->type		= 0x84;
1085 		dp_ai->len		= 0x1b;
1086 		dp_ai->ver		= 0x11 << 2;
1087 		dp_ai->CC02_CT47	= active_channels - 1;
1088 		dp_ai->CA		= ca;
1089 	} else {
1090 		codec_dbg(codec, "HDMI: unknown connection type at pin %d\n",
1091 			    pin_nid);
1092 		return;
1093 	}
1094 
1095 	/*
1096 	 * sizeof(ai) is used instead of sizeof(*hdmi_ai) or
1097 	 * sizeof(*dp_ai) to avoid partial match/update problems when
1098 	 * the user switches between HDMI/DP monitors.
1099 	 */
1100 	if (!hdmi_infoframe_uptodate(codec, pin_nid, ai.bytes,
1101 					sizeof(ai))) {
1102 		codec_dbg(codec,
1103 			  "hdmi_pin_setup_infoframe: pin=%d channels=%d ca=0x%02x\n",
1104 			    pin_nid,
1105 			    active_channels, ca);
1106 		hdmi_stop_infoframe_trans(codec, pin_nid);
1107 		hdmi_fill_audio_infoframe(codec, pin_nid,
1108 					    ai.bytes, sizeof(ai));
1109 		hdmi_start_infoframe_trans(codec, pin_nid);
1110 	}
1111 }
1112 
1113 static void hdmi_setup_audio_infoframe(struct hda_codec *codec,
1114 				       struct hdmi_spec_per_pin *per_pin,
1115 				       bool non_pcm)
1116 {
1117 	struct hdmi_spec *spec = codec->spec;
1118 	hda_nid_t pin_nid = per_pin->pin_nid;
1119 	int channels = per_pin->channels;
1120 	int active_channels;
1121 	struct hdmi_eld *eld;
1122 	int ca, ordered_ca;
1123 
1124 	if (!channels)
1125 		return;
1126 
1127 	if (is_haswell_plus(codec))
1128 		snd_hda_codec_write(codec, pin_nid, 0,
1129 					    AC_VERB_SET_AMP_GAIN_MUTE,
1130 					    AMP_OUT_UNMUTE);
1131 
1132 	eld = &per_pin->sink_eld;
1133 
1134 	if (!non_pcm && per_pin->chmap_set)
1135 		ca = hdmi_manual_channel_allocation(channels, per_pin->chmap);
1136 	else
1137 		ca = hdmi_channel_allocation(codec, eld, channels);
1138 	if (ca < 0)
1139 		ca = 0;
1140 
1141 	ordered_ca = get_channel_allocation_order(ca);
1142 	active_channels = channel_allocations[ordered_ca].channels;
1143 
1144 	hdmi_set_channel_count(codec, per_pin->cvt_nid, active_channels);
1145 
1146 	/*
1147 	 * always configure channel mapping, it may have been changed by the
1148 	 * user in the meantime
1149 	 */
1150 	hdmi_setup_channel_mapping(codec, pin_nid, non_pcm, ca,
1151 				   channels, per_pin->chmap,
1152 				   per_pin->chmap_set);
1153 
1154 	spec->ops.pin_setup_infoframe(codec, pin_nid, ca, active_channels,
1155 				      eld->info.conn_type);
1156 
1157 	per_pin->non_pcm = non_pcm;
1158 }
1159 
1160 /*
1161  * Unsolicited events
1162  */
1163 
1164 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll);
1165 
1166 static void check_presence_and_report(struct hda_codec *codec, hda_nid_t nid)
1167 {
1168 	struct hdmi_spec *spec = codec->spec;
1169 	int pin_idx = pin_nid_to_pin_index(codec, nid);
1170 
1171 	if (pin_idx < 0)
1172 		return;
1173 	if (hdmi_present_sense(get_pin(spec, pin_idx), 1))
1174 		snd_hda_jack_report_sync(codec);
1175 }
1176 
1177 static void jack_callback(struct hda_codec *codec,
1178 			  struct hda_jack_callback *jack)
1179 {
1180 	check_presence_and_report(codec, jack->tbl->nid);
1181 }
1182 
1183 static void hdmi_intrinsic_event(struct hda_codec *codec, unsigned int res)
1184 {
1185 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1186 	struct hda_jack_tbl *jack;
1187 	int dev_entry = (res & AC_UNSOL_RES_DE) >> AC_UNSOL_RES_DE_SHIFT;
1188 
1189 	jack = snd_hda_jack_tbl_get_from_tag(codec, tag);
1190 	if (!jack)
1191 		return;
1192 	jack->jack_dirty = 1;
1193 
1194 	codec_dbg(codec,
1195 		"HDMI hot plug event: Codec=%d Pin=%d Device=%d Inactive=%d Presence_Detect=%d ELD_Valid=%d\n",
1196 		codec->addr, jack->nid, dev_entry, !!(res & AC_UNSOL_RES_IA),
1197 		!!(res & AC_UNSOL_RES_PD), !!(res & AC_UNSOL_RES_ELDV));
1198 
1199 	check_presence_and_report(codec, jack->nid);
1200 }
1201 
1202 static void hdmi_non_intrinsic_event(struct hda_codec *codec, unsigned int res)
1203 {
1204 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1205 	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1206 	int cp_state = !!(res & AC_UNSOL_RES_CP_STATE);
1207 	int cp_ready = !!(res & AC_UNSOL_RES_CP_READY);
1208 
1209 	codec_info(codec,
1210 		"HDMI CP event: CODEC=%d TAG=%d SUBTAG=0x%x CP_STATE=%d CP_READY=%d\n",
1211 		codec->addr,
1212 		tag,
1213 		subtag,
1214 		cp_state,
1215 		cp_ready);
1216 
1217 	/* TODO */
1218 	if (cp_state)
1219 		;
1220 	if (cp_ready)
1221 		;
1222 }
1223 
1224 
1225 static void hdmi_unsol_event(struct hda_codec *codec, unsigned int res)
1226 {
1227 	int tag = res >> AC_UNSOL_RES_TAG_SHIFT;
1228 	int subtag = (res & AC_UNSOL_RES_SUBTAG) >> AC_UNSOL_RES_SUBTAG_SHIFT;
1229 
1230 	if (!snd_hda_jack_tbl_get_from_tag(codec, tag)) {
1231 		codec_dbg(codec, "Unexpected HDMI event tag 0x%x\n", tag);
1232 		return;
1233 	}
1234 
1235 	if (subtag == 0)
1236 		hdmi_intrinsic_event(codec, res);
1237 	else
1238 		hdmi_non_intrinsic_event(codec, res);
1239 }
1240 
1241 static void haswell_verify_D0(struct hda_codec *codec,
1242 		hda_nid_t cvt_nid, hda_nid_t nid)
1243 {
1244 	int pwr;
1245 
1246 	/* For Haswell, the converter 1/2 may keep in D3 state after bootup,
1247 	 * thus pins could only choose converter 0 for use. Make sure the
1248 	 * converters are in correct power state */
1249 	if (!snd_hda_check_power_state(codec, cvt_nid, AC_PWRST_D0))
1250 		snd_hda_codec_write(codec, cvt_nid, 0, AC_VERB_SET_POWER_STATE, AC_PWRST_D0);
1251 
1252 	if (!snd_hda_check_power_state(codec, nid, AC_PWRST_D0)) {
1253 		snd_hda_codec_write(codec, nid, 0, AC_VERB_SET_POWER_STATE,
1254 				    AC_PWRST_D0);
1255 		msleep(40);
1256 		pwr = snd_hda_codec_read(codec, nid, 0, AC_VERB_GET_POWER_STATE, 0);
1257 		pwr = (pwr & AC_PWRST_ACTUAL) >> AC_PWRST_ACTUAL_SHIFT;
1258 		codec_dbg(codec, "Haswell HDMI audio: Power for pin 0x%x is now D%d\n", nid, pwr);
1259 	}
1260 }
1261 
1262 /*
1263  * Callbacks
1264  */
1265 
1266 /* HBR should be Non-PCM, 8 channels */
1267 #define is_hbr_format(format) \
1268 	((format & AC_FMT_TYPE_NON_PCM) && (format & AC_FMT_CHAN_MASK) == 7)
1269 
1270 static int hdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
1271 			      bool hbr)
1272 {
1273 	int pinctl, new_pinctl;
1274 
1275 	if (snd_hda_query_pin_caps(codec, pin_nid) & AC_PINCAP_HBR) {
1276 		pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1277 					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1278 
1279 		if (pinctl < 0)
1280 			return hbr ? -EINVAL : 0;
1281 
1282 		new_pinctl = pinctl & ~AC_PINCTL_EPT;
1283 		if (hbr)
1284 			new_pinctl |= AC_PINCTL_EPT_HBR;
1285 		else
1286 			new_pinctl |= AC_PINCTL_EPT_NATIVE;
1287 
1288 		codec_dbg(codec,
1289 			  "hdmi_pin_hbr_setup: NID=0x%x, %spinctl=0x%x\n",
1290 			    pin_nid,
1291 			    pinctl == new_pinctl ? "" : "new-",
1292 			    new_pinctl);
1293 
1294 		if (pinctl != new_pinctl)
1295 			snd_hda_codec_write(codec, pin_nid, 0,
1296 					    AC_VERB_SET_PIN_WIDGET_CONTROL,
1297 					    new_pinctl);
1298 	} else if (hbr)
1299 		return -EINVAL;
1300 
1301 	return 0;
1302 }
1303 
1304 static int hdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
1305 			      hda_nid_t pin_nid, u32 stream_tag, int format)
1306 {
1307 	struct hdmi_spec *spec = codec->spec;
1308 	int err;
1309 
1310 	if (is_haswell_plus(codec))
1311 		haswell_verify_D0(codec, cvt_nid, pin_nid);
1312 
1313 	err = spec->ops.pin_hbr_setup(codec, pin_nid, is_hbr_format(format));
1314 
1315 	if (err) {
1316 		codec_dbg(codec, "hdmi_setup_stream: HBR is not supported\n");
1317 		return err;
1318 	}
1319 
1320 	snd_hda_codec_setup_stream(codec, cvt_nid, stream_tag, 0, format);
1321 	return 0;
1322 }
1323 
1324 static int hdmi_choose_cvt(struct hda_codec *codec,
1325 			int pin_idx, int *cvt_id, int *mux_id)
1326 {
1327 	struct hdmi_spec *spec = codec->spec;
1328 	struct hdmi_spec_per_pin *per_pin;
1329 	struct hdmi_spec_per_cvt *per_cvt = NULL;
1330 	int cvt_idx, mux_idx = 0;
1331 
1332 	per_pin = get_pin(spec, pin_idx);
1333 
1334 	/* Dynamically assign converter to stream */
1335 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1336 		per_cvt = get_cvt(spec, cvt_idx);
1337 
1338 		/* Must not already be assigned */
1339 		if (per_cvt->assigned)
1340 			continue;
1341 		/* Must be in pin's mux's list of converters */
1342 		for (mux_idx = 0; mux_idx < per_pin->num_mux_nids; mux_idx++)
1343 			if (per_pin->mux_nids[mux_idx] == per_cvt->cvt_nid)
1344 				break;
1345 		/* Not in mux list */
1346 		if (mux_idx == per_pin->num_mux_nids)
1347 			continue;
1348 		break;
1349 	}
1350 
1351 	/* No free converters */
1352 	if (cvt_idx == spec->num_cvts)
1353 		return -ENODEV;
1354 
1355 	per_pin->mux_idx = mux_idx;
1356 
1357 	if (cvt_id)
1358 		*cvt_id = cvt_idx;
1359 	if (mux_id)
1360 		*mux_id = mux_idx;
1361 
1362 	return 0;
1363 }
1364 
1365 /* Assure the pin select the right convetor */
1366 static void intel_verify_pin_cvt_connect(struct hda_codec *codec,
1367 			struct hdmi_spec_per_pin *per_pin)
1368 {
1369 	hda_nid_t pin_nid = per_pin->pin_nid;
1370 	int mux_idx, curr;
1371 
1372 	mux_idx = per_pin->mux_idx;
1373 	curr = snd_hda_codec_read(codec, pin_nid, 0,
1374 					  AC_VERB_GET_CONNECT_SEL, 0);
1375 	if (curr != mux_idx)
1376 		snd_hda_codec_write_cache(codec, pin_nid, 0,
1377 					    AC_VERB_SET_CONNECT_SEL,
1378 					    mux_idx);
1379 }
1380 
1381 /* Intel HDMI workaround to fix audio routing issue:
1382  * For some Intel display codecs, pins share the same connection list.
1383  * So a conveter can be selected by multiple pins and playback on any of these
1384  * pins will generate sound on the external display, because audio flows from
1385  * the same converter to the display pipeline. Also muting one pin may make
1386  * other pins have no sound output.
1387  * So this function assures that an assigned converter for a pin is not selected
1388  * by any other pins.
1389  */
1390 static void intel_not_share_assigned_cvt(struct hda_codec *codec,
1391 			hda_nid_t pin_nid, int mux_idx)
1392 {
1393 	struct hdmi_spec *spec = codec->spec;
1394 	hda_nid_t nid;
1395 	int cvt_idx, curr;
1396 	struct hdmi_spec_per_cvt *per_cvt;
1397 
1398 	/* configure all pins, including "no physical connection" ones */
1399 	for_each_hda_codec_node(nid, codec) {
1400 		unsigned int wid_caps = get_wcaps(codec, nid);
1401 		unsigned int wid_type = get_wcaps_type(wid_caps);
1402 
1403 		if (wid_type != AC_WID_PIN)
1404 			continue;
1405 
1406 		if (nid == pin_nid)
1407 			continue;
1408 
1409 		curr = snd_hda_codec_read(codec, nid, 0,
1410 					  AC_VERB_GET_CONNECT_SEL, 0);
1411 		if (curr != mux_idx)
1412 			continue;
1413 
1414 		/* choose an unassigned converter. The conveters in the
1415 		 * connection list are in the same order as in the codec.
1416 		 */
1417 		for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
1418 			per_cvt = get_cvt(spec, cvt_idx);
1419 			if (!per_cvt->assigned) {
1420 				codec_dbg(codec,
1421 					  "choose cvt %d for pin nid %d\n",
1422 					cvt_idx, nid);
1423 				snd_hda_codec_write_cache(codec, nid, 0,
1424 					    AC_VERB_SET_CONNECT_SEL,
1425 					    cvt_idx);
1426 				break;
1427 			}
1428 		}
1429 	}
1430 }
1431 
1432 /*
1433  * HDA PCM callbacks
1434  */
1435 static int hdmi_pcm_open(struct hda_pcm_stream *hinfo,
1436 			 struct hda_codec *codec,
1437 			 struct snd_pcm_substream *substream)
1438 {
1439 	struct hdmi_spec *spec = codec->spec;
1440 	struct snd_pcm_runtime *runtime = substream->runtime;
1441 	int pin_idx, cvt_idx, mux_idx = 0;
1442 	struct hdmi_spec_per_pin *per_pin;
1443 	struct hdmi_eld *eld;
1444 	struct hdmi_spec_per_cvt *per_cvt = NULL;
1445 	int err;
1446 
1447 	/* Validate hinfo */
1448 	pin_idx = hinfo_to_pin_index(codec, hinfo);
1449 	if (snd_BUG_ON(pin_idx < 0))
1450 		return -EINVAL;
1451 	per_pin = get_pin(spec, pin_idx);
1452 	eld = &per_pin->sink_eld;
1453 
1454 	err = hdmi_choose_cvt(codec, pin_idx, &cvt_idx, &mux_idx);
1455 	if (err < 0)
1456 		return err;
1457 
1458 	per_cvt = get_cvt(spec, cvt_idx);
1459 	/* Claim converter */
1460 	per_cvt->assigned = 1;
1461 	per_pin->cvt_nid = per_cvt->cvt_nid;
1462 	hinfo->nid = per_cvt->cvt_nid;
1463 
1464 	snd_hda_codec_write_cache(codec, per_pin->pin_nid, 0,
1465 			    AC_VERB_SET_CONNECT_SEL,
1466 			    mux_idx);
1467 
1468 	/* configure unused pins to choose other converters */
1469 	if (is_haswell_plus(codec) || is_valleyview_plus(codec))
1470 		intel_not_share_assigned_cvt(codec, per_pin->pin_nid, mux_idx);
1471 
1472 	snd_hda_spdif_ctls_assign(codec, pin_idx, per_cvt->cvt_nid);
1473 
1474 	/* Initially set the converter's capabilities */
1475 	hinfo->channels_min = per_cvt->channels_min;
1476 	hinfo->channels_max = per_cvt->channels_max;
1477 	hinfo->rates = per_cvt->rates;
1478 	hinfo->formats = per_cvt->formats;
1479 	hinfo->maxbps = per_cvt->maxbps;
1480 
1481 	/* Restrict capabilities by ELD if this isn't disabled */
1482 	if (!static_hdmi_pcm && eld->eld_valid) {
1483 		snd_hdmi_eld_update_pcm_info(&eld->info, hinfo);
1484 		if (hinfo->channels_min > hinfo->channels_max ||
1485 		    !hinfo->rates || !hinfo->formats) {
1486 			per_cvt->assigned = 0;
1487 			hinfo->nid = 0;
1488 			snd_hda_spdif_ctls_unassign(codec, pin_idx);
1489 			return -ENODEV;
1490 		}
1491 	}
1492 
1493 	/* Store the updated parameters */
1494 	runtime->hw.channels_min = hinfo->channels_min;
1495 	runtime->hw.channels_max = hinfo->channels_max;
1496 	runtime->hw.formats = hinfo->formats;
1497 	runtime->hw.rates = hinfo->rates;
1498 
1499 	snd_pcm_hw_constraint_step(substream->runtime, 0,
1500 				   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
1501 	return 0;
1502 }
1503 
1504 /*
1505  * HDA/HDMI auto parsing
1506  */
1507 static int hdmi_read_pin_conn(struct hda_codec *codec, int pin_idx)
1508 {
1509 	struct hdmi_spec *spec = codec->spec;
1510 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1511 	hda_nid_t pin_nid = per_pin->pin_nid;
1512 
1513 	if (!(get_wcaps(codec, pin_nid) & AC_WCAP_CONN_LIST)) {
1514 		codec_warn(codec,
1515 			   "HDMI: pin %d wcaps %#x does not support connection list\n",
1516 			   pin_nid, get_wcaps(codec, pin_nid));
1517 		return -EINVAL;
1518 	}
1519 
1520 	per_pin->num_mux_nids = snd_hda_get_connections(codec, pin_nid,
1521 							per_pin->mux_nids,
1522 							HDA_MAX_CONNECTIONS);
1523 
1524 	return 0;
1525 }
1526 
1527 static bool hdmi_present_sense(struct hdmi_spec_per_pin *per_pin, int repoll)
1528 {
1529 	struct hda_jack_tbl *jack;
1530 	struct hda_codec *codec = per_pin->codec;
1531 	struct hdmi_spec *spec = codec->spec;
1532 	struct hdmi_eld *eld = &spec->temp_eld;
1533 	struct hdmi_eld *pin_eld = &per_pin->sink_eld;
1534 	hda_nid_t pin_nid = per_pin->pin_nid;
1535 	/*
1536 	 * Always execute a GetPinSense verb here, even when called from
1537 	 * hdmi_intrinsic_event; for some NVIDIA HW, the unsolicited
1538 	 * response's PD bit is not the real PD value, but indicates that
1539 	 * the real PD value changed. An older version of the HD-audio
1540 	 * specification worked this way. Hence, we just ignore the data in
1541 	 * the unsolicited response to avoid custom WARs.
1542 	 */
1543 	int present;
1544 	bool update_eld = false;
1545 	bool eld_changed = false;
1546 	bool ret;
1547 
1548 	snd_hda_power_up_pm(codec);
1549 	present = snd_hda_pin_sense(codec, pin_nid);
1550 
1551 	mutex_lock(&per_pin->lock);
1552 	pin_eld->monitor_present = !!(present & AC_PINSENSE_PRESENCE);
1553 	if (pin_eld->monitor_present)
1554 		eld->eld_valid  = !!(present & AC_PINSENSE_ELDV);
1555 	else
1556 		eld->eld_valid = false;
1557 
1558 	codec_dbg(codec,
1559 		"HDMI status: Codec=%d Pin=%d Presence_Detect=%d ELD_Valid=%d\n",
1560 		codec->addr, pin_nid, pin_eld->monitor_present, eld->eld_valid);
1561 
1562 	if (eld->eld_valid) {
1563 		if (spec->ops.pin_get_eld(codec, pin_nid, eld->eld_buffer,
1564 						     &eld->eld_size) < 0)
1565 			eld->eld_valid = false;
1566 		else {
1567 			memset(&eld->info, 0, sizeof(struct parsed_hdmi_eld));
1568 			if (snd_hdmi_parse_eld(codec, &eld->info, eld->eld_buffer,
1569 						    eld->eld_size) < 0)
1570 				eld->eld_valid = false;
1571 		}
1572 
1573 		if (eld->eld_valid) {
1574 			snd_hdmi_show_eld(codec, &eld->info);
1575 			update_eld = true;
1576 		}
1577 		else if (repoll) {
1578 			schedule_delayed_work(&per_pin->work,
1579 					      msecs_to_jiffies(300));
1580 			goto unlock;
1581 		}
1582 	}
1583 
1584 	if (pin_eld->eld_valid != eld->eld_valid)
1585 		eld_changed = true;
1586 
1587 	if (pin_eld->eld_valid && !eld->eld_valid)
1588 		update_eld = true;
1589 
1590 	if (update_eld) {
1591 		bool old_eld_valid = pin_eld->eld_valid;
1592 		pin_eld->eld_valid = eld->eld_valid;
1593 		if (pin_eld->eld_size != eld->eld_size ||
1594 			      memcmp(pin_eld->eld_buffer, eld->eld_buffer,
1595 				     eld->eld_size) != 0) {
1596 			memcpy(pin_eld->eld_buffer, eld->eld_buffer,
1597 			       eld->eld_size);
1598 			eld_changed = true;
1599 		}
1600 		pin_eld->eld_size = eld->eld_size;
1601 		pin_eld->info = eld->info;
1602 
1603 		/*
1604 		 * Re-setup pin and infoframe. This is needed e.g. when
1605 		 * - sink is first plugged-in (infoframe is not set up if !monitor_present)
1606 		 * - transcoder can change during stream playback on Haswell
1607 		 *   and this can make HW reset converter selection on a pin.
1608 		 */
1609 		if (eld->eld_valid && !old_eld_valid && per_pin->setup) {
1610 			if (is_haswell_plus(codec) ||
1611 				is_valleyview_plus(codec)) {
1612 				intel_verify_pin_cvt_connect(codec, per_pin);
1613 				intel_not_share_assigned_cvt(codec, pin_nid,
1614 							per_pin->mux_idx);
1615 			}
1616 
1617 			hdmi_setup_audio_infoframe(codec, per_pin,
1618 						   per_pin->non_pcm);
1619 		}
1620 	}
1621 
1622 	if (eld_changed)
1623 		snd_ctl_notify(codec->card,
1624 			       SNDRV_CTL_EVENT_MASK_VALUE | SNDRV_CTL_EVENT_MASK_INFO,
1625 			       &per_pin->eld_ctl->id);
1626  unlock:
1627 	ret = !repoll || !pin_eld->monitor_present || pin_eld->eld_valid;
1628 
1629 	jack = snd_hda_jack_tbl_get(codec, pin_nid);
1630 	if (jack)
1631 		jack->block_report = !ret;
1632 
1633 	mutex_unlock(&per_pin->lock);
1634 	snd_hda_power_down_pm(codec);
1635 	return ret;
1636 }
1637 
1638 static void hdmi_repoll_eld(struct work_struct *work)
1639 {
1640 	struct hdmi_spec_per_pin *per_pin =
1641 	container_of(to_delayed_work(work), struct hdmi_spec_per_pin, work);
1642 
1643 	if (per_pin->repoll_count++ > 6)
1644 		per_pin->repoll_count = 0;
1645 
1646 	if (hdmi_present_sense(per_pin, per_pin->repoll_count))
1647 		snd_hda_jack_report_sync(per_pin->codec);
1648 }
1649 
1650 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
1651 					     hda_nid_t nid);
1652 
1653 static int hdmi_add_pin(struct hda_codec *codec, hda_nid_t pin_nid)
1654 {
1655 	struct hdmi_spec *spec = codec->spec;
1656 	unsigned int caps, config;
1657 	int pin_idx;
1658 	struct hdmi_spec_per_pin *per_pin;
1659 	int err;
1660 
1661 	caps = snd_hda_query_pin_caps(codec, pin_nid);
1662 	if (!(caps & (AC_PINCAP_HDMI | AC_PINCAP_DP)))
1663 		return 0;
1664 
1665 	config = snd_hda_codec_get_pincfg(codec, pin_nid);
1666 	if (get_defcfg_connect(config) == AC_JACK_PORT_NONE)
1667 		return 0;
1668 
1669 	if (is_haswell_plus(codec))
1670 		intel_haswell_fixup_connect_list(codec, pin_nid);
1671 
1672 	pin_idx = spec->num_pins;
1673 	per_pin = snd_array_new(&spec->pins);
1674 	if (!per_pin)
1675 		return -ENOMEM;
1676 
1677 	per_pin->pin_nid = pin_nid;
1678 	per_pin->non_pcm = false;
1679 
1680 	err = hdmi_read_pin_conn(codec, pin_idx);
1681 	if (err < 0)
1682 		return err;
1683 
1684 	spec->num_pins++;
1685 
1686 	return 0;
1687 }
1688 
1689 static int hdmi_add_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1690 {
1691 	struct hdmi_spec *spec = codec->spec;
1692 	struct hdmi_spec_per_cvt *per_cvt;
1693 	unsigned int chans;
1694 	int err;
1695 
1696 	chans = get_wcaps(codec, cvt_nid);
1697 	chans = get_wcaps_channels(chans);
1698 
1699 	per_cvt = snd_array_new(&spec->cvts);
1700 	if (!per_cvt)
1701 		return -ENOMEM;
1702 
1703 	per_cvt->cvt_nid = cvt_nid;
1704 	per_cvt->channels_min = 2;
1705 	if (chans <= 16) {
1706 		per_cvt->channels_max = chans;
1707 		if (chans > spec->channels_max)
1708 			spec->channels_max = chans;
1709 	}
1710 
1711 	err = snd_hda_query_supported_pcm(codec, cvt_nid,
1712 					  &per_cvt->rates,
1713 					  &per_cvt->formats,
1714 					  &per_cvt->maxbps);
1715 	if (err < 0)
1716 		return err;
1717 
1718 	if (spec->num_cvts < ARRAY_SIZE(spec->cvt_nids))
1719 		spec->cvt_nids[spec->num_cvts] = cvt_nid;
1720 	spec->num_cvts++;
1721 
1722 	return 0;
1723 }
1724 
1725 static int hdmi_parse_codec(struct hda_codec *codec)
1726 {
1727 	hda_nid_t nid;
1728 	int i, nodes;
1729 
1730 	nodes = snd_hda_get_sub_nodes(codec, codec->core.afg, &nid);
1731 	if (!nid || nodes < 0) {
1732 		codec_warn(codec, "HDMI: failed to get afg sub nodes\n");
1733 		return -EINVAL;
1734 	}
1735 
1736 	for (i = 0; i < nodes; i++, nid++) {
1737 		unsigned int caps;
1738 		unsigned int type;
1739 
1740 		caps = get_wcaps(codec, nid);
1741 		type = get_wcaps_type(caps);
1742 
1743 		if (!(caps & AC_WCAP_DIGITAL))
1744 			continue;
1745 
1746 		switch (type) {
1747 		case AC_WID_AUD_OUT:
1748 			hdmi_add_cvt(codec, nid);
1749 			break;
1750 		case AC_WID_PIN:
1751 			hdmi_add_pin(codec, nid);
1752 			break;
1753 		}
1754 	}
1755 
1756 	return 0;
1757 }
1758 
1759 /*
1760  */
1761 static bool check_non_pcm_per_cvt(struct hda_codec *codec, hda_nid_t cvt_nid)
1762 {
1763 	struct hda_spdif_out *spdif;
1764 	bool non_pcm;
1765 
1766 	mutex_lock(&codec->spdif_mutex);
1767 	spdif = snd_hda_spdif_out_of_nid(codec, cvt_nid);
1768 	non_pcm = !!(spdif->status & IEC958_AES0_NONAUDIO);
1769 	mutex_unlock(&codec->spdif_mutex);
1770 	return non_pcm;
1771 }
1772 
1773 
1774 /*
1775  * HDMI callbacks
1776  */
1777 
1778 static int generic_hdmi_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
1779 					   struct hda_codec *codec,
1780 					   unsigned int stream_tag,
1781 					   unsigned int format,
1782 					   struct snd_pcm_substream *substream)
1783 {
1784 	hda_nid_t cvt_nid = hinfo->nid;
1785 	struct hdmi_spec *spec = codec->spec;
1786 	int pin_idx = hinfo_to_pin_index(codec, hinfo);
1787 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1788 	hda_nid_t pin_nid = per_pin->pin_nid;
1789 	bool non_pcm;
1790 	int pinctl;
1791 
1792 	if (is_haswell_plus(codec) || is_valleyview_plus(codec)) {
1793 		/* Verify pin:cvt selections to avoid silent audio after S3.
1794 		 * After S3, the audio driver restores pin:cvt selections
1795 		 * but this can happen before gfx is ready and such selection
1796 		 * is overlooked by HW. Thus multiple pins can share a same
1797 		 * default convertor and mute control will affect each other,
1798 		 * which can cause a resumed audio playback become silent
1799 		 * after S3.
1800 		 */
1801 		intel_verify_pin_cvt_connect(codec, per_pin);
1802 		intel_not_share_assigned_cvt(codec, pin_nid, per_pin->mux_idx);
1803 	}
1804 
1805 	non_pcm = check_non_pcm_per_cvt(codec, cvt_nid);
1806 	mutex_lock(&per_pin->lock);
1807 	per_pin->channels = substream->runtime->channels;
1808 	per_pin->setup = true;
1809 
1810 	hdmi_setup_audio_infoframe(codec, per_pin, non_pcm);
1811 	mutex_unlock(&per_pin->lock);
1812 
1813 	if (spec->dyn_pin_out) {
1814 		pinctl = snd_hda_codec_read(codec, pin_nid, 0,
1815 					    AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1816 		snd_hda_codec_write(codec, pin_nid, 0,
1817 				    AC_VERB_SET_PIN_WIDGET_CONTROL,
1818 				    pinctl | PIN_OUT);
1819 	}
1820 
1821 	return spec->ops.setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
1822 }
1823 
1824 static int generic_hdmi_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
1825 					     struct hda_codec *codec,
1826 					     struct snd_pcm_substream *substream)
1827 {
1828 	snd_hda_codec_cleanup_stream(codec, hinfo->nid);
1829 	return 0;
1830 }
1831 
1832 static int hdmi_pcm_close(struct hda_pcm_stream *hinfo,
1833 			  struct hda_codec *codec,
1834 			  struct snd_pcm_substream *substream)
1835 {
1836 	struct hdmi_spec *spec = codec->spec;
1837 	int cvt_idx, pin_idx;
1838 	struct hdmi_spec_per_cvt *per_cvt;
1839 	struct hdmi_spec_per_pin *per_pin;
1840 	int pinctl;
1841 
1842 	if (hinfo->nid) {
1843 		cvt_idx = cvt_nid_to_cvt_index(codec, hinfo->nid);
1844 		if (snd_BUG_ON(cvt_idx < 0))
1845 			return -EINVAL;
1846 		per_cvt = get_cvt(spec, cvt_idx);
1847 
1848 		snd_BUG_ON(!per_cvt->assigned);
1849 		per_cvt->assigned = 0;
1850 		hinfo->nid = 0;
1851 
1852 		pin_idx = hinfo_to_pin_index(codec, hinfo);
1853 		if (snd_BUG_ON(pin_idx < 0))
1854 			return -EINVAL;
1855 		per_pin = get_pin(spec, pin_idx);
1856 
1857 		if (spec->dyn_pin_out) {
1858 			pinctl = snd_hda_codec_read(codec, per_pin->pin_nid, 0,
1859 					AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
1860 			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
1861 					    AC_VERB_SET_PIN_WIDGET_CONTROL,
1862 					    pinctl & ~PIN_OUT);
1863 		}
1864 
1865 		snd_hda_spdif_ctls_unassign(codec, pin_idx);
1866 
1867 		mutex_lock(&per_pin->lock);
1868 		per_pin->chmap_set = false;
1869 		memset(per_pin->chmap, 0, sizeof(per_pin->chmap));
1870 
1871 		per_pin->setup = false;
1872 		per_pin->channels = 0;
1873 		mutex_unlock(&per_pin->lock);
1874 	}
1875 
1876 	return 0;
1877 }
1878 
1879 static const struct hda_pcm_ops generic_ops = {
1880 	.open = hdmi_pcm_open,
1881 	.close = hdmi_pcm_close,
1882 	.prepare = generic_hdmi_playback_pcm_prepare,
1883 	.cleanup = generic_hdmi_playback_pcm_cleanup,
1884 };
1885 
1886 /*
1887  * ALSA API channel-map control callbacks
1888  */
1889 static int hdmi_chmap_ctl_info(struct snd_kcontrol *kcontrol,
1890 			       struct snd_ctl_elem_info *uinfo)
1891 {
1892 	struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1893 	struct hda_codec *codec = info->private_data;
1894 	struct hdmi_spec *spec = codec->spec;
1895 	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1896 	uinfo->count = spec->channels_max;
1897 	uinfo->value.integer.min = 0;
1898 	uinfo->value.integer.max = SNDRV_CHMAP_LAST;
1899 	return 0;
1900 }
1901 
1902 static int hdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
1903 						  int channels)
1904 {
1905 	/* If the speaker allocation matches the channel count, it is OK.*/
1906 	if (cap->channels != channels)
1907 		return -1;
1908 
1909 	/* all channels are remappable freely */
1910 	return SNDRV_CTL_TLVT_CHMAP_VAR;
1911 }
1912 
1913 static void hdmi_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
1914 					unsigned int *chmap, int channels)
1915 {
1916 	int count = 0;
1917 	int c;
1918 
1919 	for (c = 7; c >= 0; c--) {
1920 		int spk = cap->speakers[c];
1921 		if (!spk)
1922 			continue;
1923 
1924 		chmap[count++] = spk_to_chmap(spk);
1925 	}
1926 
1927 	WARN_ON(count != channels);
1928 }
1929 
1930 static int hdmi_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
1931 			      unsigned int size, unsigned int __user *tlv)
1932 {
1933 	struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1934 	struct hda_codec *codec = info->private_data;
1935 	struct hdmi_spec *spec = codec->spec;
1936 	unsigned int __user *dst;
1937 	int chs, count = 0;
1938 
1939 	if (size < 8)
1940 		return -ENOMEM;
1941 	if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
1942 		return -EFAULT;
1943 	size -= 8;
1944 	dst = tlv + 2;
1945 	for (chs = 2; chs <= spec->channels_max; chs++) {
1946 		int i;
1947 		struct cea_channel_speaker_allocation *cap;
1948 		cap = channel_allocations;
1949 		for (i = 0; i < ARRAY_SIZE(channel_allocations); i++, cap++) {
1950 			int chs_bytes = chs * 4;
1951 			int type = spec->ops.chmap_cea_alloc_validate_get_type(cap, chs);
1952 			unsigned int tlv_chmap[8];
1953 
1954 			if (type < 0)
1955 				continue;
1956 			if (size < 8)
1957 				return -ENOMEM;
1958 			if (put_user(type, dst) ||
1959 			    put_user(chs_bytes, dst + 1))
1960 				return -EFAULT;
1961 			dst += 2;
1962 			size -= 8;
1963 			count += 8;
1964 			if (size < chs_bytes)
1965 				return -ENOMEM;
1966 			size -= chs_bytes;
1967 			count += chs_bytes;
1968 			spec->ops.cea_alloc_to_tlv_chmap(cap, tlv_chmap, chs);
1969 			if (copy_to_user(dst, tlv_chmap, chs_bytes))
1970 				return -EFAULT;
1971 			dst += chs;
1972 		}
1973 	}
1974 	if (put_user(count, tlv + 1))
1975 		return -EFAULT;
1976 	return 0;
1977 }
1978 
1979 static int hdmi_chmap_ctl_get(struct snd_kcontrol *kcontrol,
1980 			      struct snd_ctl_elem_value *ucontrol)
1981 {
1982 	struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1983 	struct hda_codec *codec = info->private_data;
1984 	struct hdmi_spec *spec = codec->spec;
1985 	int pin_idx = kcontrol->private_value;
1986 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
1987 	int i;
1988 
1989 	for (i = 0; i < ARRAY_SIZE(per_pin->chmap); i++)
1990 		ucontrol->value.integer.value[i] = per_pin->chmap[i];
1991 	return 0;
1992 }
1993 
1994 static int hdmi_chmap_ctl_put(struct snd_kcontrol *kcontrol,
1995 			      struct snd_ctl_elem_value *ucontrol)
1996 {
1997 	struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
1998 	struct hda_codec *codec = info->private_data;
1999 	struct hdmi_spec *spec = codec->spec;
2000 	int pin_idx = kcontrol->private_value;
2001 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2002 	unsigned int ctl_idx;
2003 	struct snd_pcm_substream *substream;
2004 	unsigned char chmap[8];
2005 	int i, err, ca, prepared = 0;
2006 
2007 	ctl_idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
2008 	substream = snd_pcm_chmap_substream(info, ctl_idx);
2009 	if (!substream || !substream->runtime)
2010 		return 0; /* just for avoiding error from alsactl restore */
2011 	switch (substream->runtime->status->state) {
2012 	case SNDRV_PCM_STATE_OPEN:
2013 	case SNDRV_PCM_STATE_SETUP:
2014 		break;
2015 	case SNDRV_PCM_STATE_PREPARED:
2016 		prepared = 1;
2017 		break;
2018 	default:
2019 		return -EBUSY;
2020 	}
2021 	memset(chmap, 0, sizeof(chmap));
2022 	for (i = 0; i < ARRAY_SIZE(chmap); i++)
2023 		chmap[i] = ucontrol->value.integer.value[i];
2024 	if (!memcmp(chmap, per_pin->chmap, sizeof(chmap)))
2025 		return 0;
2026 	ca = hdmi_manual_channel_allocation(ARRAY_SIZE(chmap), chmap);
2027 	if (ca < 0)
2028 		return -EINVAL;
2029 	if (spec->ops.chmap_validate) {
2030 		err = spec->ops.chmap_validate(ca, ARRAY_SIZE(chmap), chmap);
2031 		if (err)
2032 			return err;
2033 	}
2034 	mutex_lock(&per_pin->lock);
2035 	per_pin->chmap_set = true;
2036 	memcpy(per_pin->chmap, chmap, sizeof(chmap));
2037 	if (prepared)
2038 		hdmi_setup_audio_infoframe(codec, per_pin, per_pin->non_pcm);
2039 	mutex_unlock(&per_pin->lock);
2040 
2041 	return 0;
2042 }
2043 
2044 static int generic_hdmi_build_pcms(struct hda_codec *codec)
2045 {
2046 	struct hdmi_spec *spec = codec->spec;
2047 	int pin_idx;
2048 
2049 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2050 		struct hda_pcm *info;
2051 		struct hda_pcm_stream *pstr;
2052 
2053 		info = snd_hda_codec_pcm_new(codec, "HDMI %d", pin_idx);
2054 		if (!info)
2055 			return -ENOMEM;
2056 		spec->pcm_rec[pin_idx] = info;
2057 		info->pcm_type = HDA_PCM_TYPE_HDMI;
2058 		info->own_chmap = true;
2059 
2060 		pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2061 		pstr->substreams = 1;
2062 		pstr->ops = generic_ops;
2063 		/* other pstr fields are set in open */
2064 	}
2065 
2066 	return 0;
2067 }
2068 
2069 static int generic_hdmi_build_jack(struct hda_codec *codec, int pin_idx)
2070 {
2071 	char hdmi_str[32] = "HDMI/DP";
2072 	struct hdmi_spec *spec = codec->spec;
2073 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2074 	int pcmdev = get_pcm_rec(spec, pin_idx)->device;
2075 
2076 	if (pcmdev > 0)
2077 		sprintf(hdmi_str + strlen(hdmi_str), ",pcm=%d", pcmdev);
2078 	if (!is_jack_detectable(codec, per_pin->pin_nid))
2079 		strncat(hdmi_str, " Phantom",
2080 			sizeof(hdmi_str) - strlen(hdmi_str) - 1);
2081 
2082 	return snd_hda_jack_add_kctl(codec, per_pin->pin_nid, hdmi_str);
2083 }
2084 
2085 static int generic_hdmi_build_controls(struct hda_codec *codec)
2086 {
2087 	struct hdmi_spec *spec = codec->spec;
2088 	int err;
2089 	int pin_idx;
2090 
2091 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2092 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2093 
2094 		err = generic_hdmi_build_jack(codec, pin_idx);
2095 		if (err < 0)
2096 			return err;
2097 
2098 		err = snd_hda_create_dig_out_ctls(codec,
2099 						  per_pin->pin_nid,
2100 						  per_pin->mux_nids[0],
2101 						  HDA_PCM_TYPE_HDMI);
2102 		if (err < 0)
2103 			return err;
2104 		snd_hda_spdif_ctls_unassign(codec, pin_idx);
2105 
2106 		/* add control for ELD Bytes */
2107 		err = hdmi_create_eld_ctl(codec, pin_idx,
2108 					  get_pcm_rec(spec, pin_idx)->device);
2109 
2110 		if (err < 0)
2111 			return err;
2112 
2113 		hdmi_present_sense(per_pin, 0);
2114 	}
2115 
2116 	/* add channel maps */
2117 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2118 		struct hda_pcm *pcm;
2119 		struct snd_pcm_chmap *chmap;
2120 		struct snd_kcontrol *kctl;
2121 		int i;
2122 
2123 		pcm = spec->pcm_rec[pin_idx];
2124 		if (!pcm || !pcm->pcm)
2125 			break;
2126 		err = snd_pcm_add_chmap_ctls(pcm->pcm,
2127 					     SNDRV_PCM_STREAM_PLAYBACK,
2128 					     NULL, 0, pin_idx, &chmap);
2129 		if (err < 0)
2130 			return err;
2131 		/* override handlers */
2132 		chmap->private_data = codec;
2133 		kctl = chmap->kctl;
2134 		for (i = 0; i < kctl->count; i++)
2135 			kctl->vd[i].access |= SNDRV_CTL_ELEM_ACCESS_WRITE;
2136 		kctl->info = hdmi_chmap_ctl_info;
2137 		kctl->get = hdmi_chmap_ctl_get;
2138 		kctl->put = hdmi_chmap_ctl_put;
2139 		kctl->tlv.c = hdmi_chmap_ctl_tlv;
2140 	}
2141 
2142 	return 0;
2143 }
2144 
2145 static int generic_hdmi_init_per_pins(struct hda_codec *codec)
2146 {
2147 	struct hdmi_spec *spec = codec->spec;
2148 	int pin_idx;
2149 
2150 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2151 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2152 
2153 		per_pin->codec = codec;
2154 		mutex_init(&per_pin->lock);
2155 		INIT_DELAYED_WORK(&per_pin->work, hdmi_repoll_eld);
2156 		eld_proc_new(per_pin, pin_idx);
2157 	}
2158 	return 0;
2159 }
2160 
2161 static int generic_hdmi_init(struct hda_codec *codec)
2162 {
2163 	struct hdmi_spec *spec = codec->spec;
2164 	int pin_idx;
2165 
2166 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2167 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2168 		hda_nid_t pin_nid = per_pin->pin_nid;
2169 
2170 		hdmi_init_pin(codec, pin_nid);
2171 		snd_hda_jack_detect_enable_callback(codec, pin_nid,
2172 			codec->jackpoll_interval > 0 ? jack_callback : NULL);
2173 	}
2174 	return 0;
2175 }
2176 
2177 static void hdmi_array_init(struct hdmi_spec *spec, int nums)
2178 {
2179 	snd_array_init(&spec->pins, sizeof(struct hdmi_spec_per_pin), nums);
2180 	snd_array_init(&spec->cvts, sizeof(struct hdmi_spec_per_cvt), nums);
2181 }
2182 
2183 static void hdmi_array_free(struct hdmi_spec *spec)
2184 {
2185 	snd_array_free(&spec->pins);
2186 	snd_array_free(&spec->cvts);
2187 }
2188 
2189 static void generic_hdmi_free(struct hda_codec *codec)
2190 {
2191 	struct hdmi_spec *spec = codec->spec;
2192 	int pin_idx;
2193 
2194 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2195 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2196 
2197 		cancel_delayed_work_sync(&per_pin->work);
2198 		eld_proc_free(per_pin);
2199 	}
2200 
2201 	hdmi_array_free(spec);
2202 	kfree(spec);
2203 }
2204 
2205 #ifdef CONFIG_PM
2206 static int generic_hdmi_resume(struct hda_codec *codec)
2207 {
2208 	struct hdmi_spec *spec = codec->spec;
2209 	int pin_idx;
2210 
2211 	codec->patch_ops.init(codec);
2212 	regcache_sync(codec->core.regmap);
2213 
2214 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
2215 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
2216 		hdmi_present_sense(per_pin, 1);
2217 	}
2218 	return 0;
2219 }
2220 #endif
2221 
2222 static const struct hda_codec_ops generic_hdmi_patch_ops = {
2223 	.init			= generic_hdmi_init,
2224 	.free			= generic_hdmi_free,
2225 	.build_pcms		= generic_hdmi_build_pcms,
2226 	.build_controls		= generic_hdmi_build_controls,
2227 	.unsol_event		= hdmi_unsol_event,
2228 #ifdef CONFIG_PM
2229 	.resume			= generic_hdmi_resume,
2230 #endif
2231 };
2232 
2233 static const struct hdmi_ops generic_standard_hdmi_ops = {
2234 	.pin_get_eld				= snd_hdmi_get_eld,
2235 	.pin_get_slot_channel			= hdmi_pin_get_slot_channel,
2236 	.pin_set_slot_channel			= hdmi_pin_set_slot_channel,
2237 	.pin_setup_infoframe			= hdmi_pin_setup_infoframe,
2238 	.pin_hbr_setup				= hdmi_pin_hbr_setup,
2239 	.setup_stream				= hdmi_setup_stream,
2240 	.chmap_cea_alloc_validate_get_type	= hdmi_chmap_cea_alloc_validate_get_type,
2241 	.cea_alloc_to_tlv_chmap			= hdmi_cea_alloc_to_tlv_chmap,
2242 };
2243 
2244 
2245 static void intel_haswell_fixup_connect_list(struct hda_codec *codec,
2246 					     hda_nid_t nid)
2247 {
2248 	struct hdmi_spec *spec = codec->spec;
2249 	hda_nid_t conns[4];
2250 	int nconns;
2251 
2252 	nconns = snd_hda_get_connections(codec, nid, conns, ARRAY_SIZE(conns));
2253 	if (nconns == spec->num_cvts &&
2254 	    !memcmp(conns, spec->cvt_nids, spec->num_cvts * sizeof(hda_nid_t)))
2255 		return;
2256 
2257 	/* override pins connection list */
2258 	codec_dbg(codec, "hdmi: haswell: override pin connection 0x%x\n", nid);
2259 	snd_hda_override_conn_list(codec, nid, spec->num_cvts, spec->cvt_nids);
2260 }
2261 
2262 #define INTEL_VENDOR_NID 0x08
2263 #define INTEL_GET_VENDOR_VERB 0xf81
2264 #define INTEL_SET_VENDOR_VERB 0x781
2265 #define INTEL_EN_DP12			0x02 /* enable DP 1.2 features */
2266 #define INTEL_EN_ALL_PIN_CVTS	0x01 /* enable 2nd & 3rd pins and convertors */
2267 
2268 static void intel_haswell_enable_all_pins(struct hda_codec *codec,
2269 					  bool update_tree)
2270 {
2271 	unsigned int vendor_param;
2272 
2273 	vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2274 				INTEL_GET_VENDOR_VERB, 0);
2275 	if (vendor_param == -1 || vendor_param & INTEL_EN_ALL_PIN_CVTS)
2276 		return;
2277 
2278 	vendor_param |= INTEL_EN_ALL_PIN_CVTS;
2279 	vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2280 				INTEL_SET_VENDOR_VERB, vendor_param);
2281 	if (vendor_param == -1)
2282 		return;
2283 
2284 	if (update_tree)
2285 		snd_hda_codec_update_widgets(codec);
2286 }
2287 
2288 static void intel_haswell_fixup_enable_dp12(struct hda_codec *codec)
2289 {
2290 	unsigned int vendor_param;
2291 
2292 	vendor_param = snd_hda_codec_read(codec, INTEL_VENDOR_NID, 0,
2293 				INTEL_GET_VENDOR_VERB, 0);
2294 	if (vendor_param == -1 || vendor_param & INTEL_EN_DP12)
2295 		return;
2296 
2297 	/* enable DP1.2 mode */
2298 	vendor_param |= INTEL_EN_DP12;
2299 	snd_hdac_regmap_add_vendor_verb(&codec->core, INTEL_SET_VENDOR_VERB);
2300 	snd_hda_codec_write_cache(codec, INTEL_VENDOR_NID, 0,
2301 				INTEL_SET_VENDOR_VERB, vendor_param);
2302 }
2303 
2304 /* Haswell needs to re-issue the vendor-specific verbs before turning to D0.
2305  * Otherwise you may get severe h/w communication errors.
2306  */
2307 static void haswell_set_power_state(struct hda_codec *codec, hda_nid_t fg,
2308 				unsigned int power_state)
2309 {
2310 	if (power_state == AC_PWRST_D0) {
2311 		intel_haswell_enable_all_pins(codec, false);
2312 		intel_haswell_fixup_enable_dp12(codec);
2313 	}
2314 
2315 	snd_hda_codec_read(codec, fg, 0, AC_VERB_SET_POWER_STATE, power_state);
2316 	snd_hda_codec_set_power_to_all(codec, fg, power_state);
2317 }
2318 
2319 static int patch_generic_hdmi(struct hda_codec *codec)
2320 {
2321 	struct hdmi_spec *spec;
2322 
2323 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2324 	if (spec == NULL)
2325 		return -ENOMEM;
2326 
2327 	spec->ops = generic_standard_hdmi_ops;
2328 	codec->spec = spec;
2329 	hdmi_array_init(spec, 4);
2330 
2331 	if (is_haswell_plus(codec)) {
2332 		intel_haswell_enable_all_pins(codec, true);
2333 		intel_haswell_fixup_enable_dp12(codec);
2334 	}
2335 
2336 	/* For Valleyview/Cherryview, only the display codec is in the display
2337 	 * power well and can use link_power ops to request/release the power.
2338 	 * For Haswell/Broadwell, the controller is also in the power well and
2339 	 * can cover the codec power request, and so need not set this flag.
2340 	 * For previous platforms, there is no such power well feature.
2341 	 */
2342 	if (is_valleyview_plus(codec) || is_skylake(codec))
2343 		codec->core.link_power_control = 1;
2344 
2345 	if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2346 		codec->depop_delay = 0;
2347 
2348 	if (hdmi_parse_codec(codec) < 0) {
2349 		codec->spec = NULL;
2350 		kfree(spec);
2351 		return -EINVAL;
2352 	}
2353 	codec->patch_ops = generic_hdmi_patch_ops;
2354 	if (is_haswell_plus(codec)) {
2355 		codec->patch_ops.set_power_state = haswell_set_power_state;
2356 		codec->dp_mst = true;
2357 	}
2358 
2359 	/* Enable runtime pm for HDMI audio codec of HSW/BDW/SKL/BYT/BSW */
2360 	if (is_haswell_plus(codec) || is_valleyview_plus(codec))
2361 		codec->auto_runtime_pm = 1;
2362 
2363 	generic_hdmi_init_per_pins(codec);
2364 
2365 	init_channel_allocations();
2366 
2367 	return 0;
2368 }
2369 
2370 /*
2371  * Shared non-generic implementations
2372  */
2373 
2374 static int simple_playback_build_pcms(struct hda_codec *codec)
2375 {
2376 	struct hdmi_spec *spec = codec->spec;
2377 	struct hda_pcm *info;
2378 	unsigned int chans;
2379 	struct hda_pcm_stream *pstr;
2380 	struct hdmi_spec_per_cvt *per_cvt;
2381 
2382 	per_cvt = get_cvt(spec, 0);
2383 	chans = get_wcaps(codec, per_cvt->cvt_nid);
2384 	chans = get_wcaps_channels(chans);
2385 
2386 	info = snd_hda_codec_pcm_new(codec, "HDMI 0");
2387 	if (!info)
2388 		return -ENOMEM;
2389 	spec->pcm_rec[0] = info;
2390 	info->pcm_type = HDA_PCM_TYPE_HDMI;
2391 	pstr = &info->stream[SNDRV_PCM_STREAM_PLAYBACK];
2392 	*pstr = spec->pcm_playback;
2393 	pstr->nid = per_cvt->cvt_nid;
2394 	if (pstr->channels_max <= 2 && chans && chans <= 16)
2395 		pstr->channels_max = chans;
2396 
2397 	return 0;
2398 }
2399 
2400 /* unsolicited event for jack sensing */
2401 static void simple_hdmi_unsol_event(struct hda_codec *codec,
2402 				    unsigned int res)
2403 {
2404 	snd_hda_jack_set_dirty_all(codec);
2405 	snd_hda_jack_report_sync(codec);
2406 }
2407 
2408 /* generic_hdmi_build_jack can be used for simple_hdmi, too,
2409  * as long as spec->pins[] is set correctly
2410  */
2411 #define simple_hdmi_build_jack	generic_hdmi_build_jack
2412 
2413 static int simple_playback_build_controls(struct hda_codec *codec)
2414 {
2415 	struct hdmi_spec *spec = codec->spec;
2416 	struct hdmi_spec_per_cvt *per_cvt;
2417 	int err;
2418 
2419 	per_cvt = get_cvt(spec, 0);
2420 	err = snd_hda_create_dig_out_ctls(codec, per_cvt->cvt_nid,
2421 					  per_cvt->cvt_nid,
2422 					  HDA_PCM_TYPE_HDMI);
2423 	if (err < 0)
2424 		return err;
2425 	return simple_hdmi_build_jack(codec, 0);
2426 }
2427 
2428 static int simple_playback_init(struct hda_codec *codec)
2429 {
2430 	struct hdmi_spec *spec = codec->spec;
2431 	struct hdmi_spec_per_pin *per_pin = get_pin(spec, 0);
2432 	hda_nid_t pin = per_pin->pin_nid;
2433 
2434 	snd_hda_codec_write(codec, pin, 0,
2435 			    AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT);
2436 	/* some codecs require to unmute the pin */
2437 	if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
2438 		snd_hda_codec_write(codec, pin, 0, AC_VERB_SET_AMP_GAIN_MUTE,
2439 				    AMP_OUT_UNMUTE);
2440 	snd_hda_jack_detect_enable(codec, pin);
2441 	return 0;
2442 }
2443 
2444 static void simple_playback_free(struct hda_codec *codec)
2445 {
2446 	struct hdmi_spec *spec = codec->spec;
2447 
2448 	hdmi_array_free(spec);
2449 	kfree(spec);
2450 }
2451 
2452 /*
2453  * Nvidia specific implementations
2454  */
2455 
2456 #define Nv_VERB_SET_Channel_Allocation          0xF79
2457 #define Nv_VERB_SET_Info_Frame_Checksum         0xF7A
2458 #define Nv_VERB_SET_Audio_Protection_On         0xF98
2459 #define Nv_VERB_SET_Audio_Protection_Off        0xF99
2460 
2461 #define nvhdmi_master_con_nid_7x	0x04
2462 #define nvhdmi_master_pin_nid_7x	0x05
2463 
2464 static const hda_nid_t nvhdmi_con_nids_7x[4] = {
2465 	/*front, rear, clfe, rear_surr */
2466 	0x6, 0x8, 0xa, 0xc,
2467 };
2468 
2469 static const struct hda_verb nvhdmi_basic_init_7x_2ch[] = {
2470 	/* set audio protect on */
2471 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2472 	/* enable digital output on pin widget */
2473 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2474 	{} /* terminator */
2475 };
2476 
2477 static const struct hda_verb nvhdmi_basic_init_7x_8ch[] = {
2478 	/* set audio protect on */
2479 	{ 0x1, Nv_VERB_SET_Audio_Protection_On, 0x1},
2480 	/* enable digital output on pin widget */
2481 	{ 0x5, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2482 	{ 0x7, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2483 	{ 0x9, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2484 	{ 0xb, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2485 	{ 0xd, AC_VERB_SET_PIN_WIDGET_CONTROL, PIN_OUT | 0x5 },
2486 	{} /* terminator */
2487 };
2488 
2489 #ifdef LIMITED_RATE_FMT_SUPPORT
2490 /* support only the safe format and rate */
2491 #define SUPPORTED_RATES		SNDRV_PCM_RATE_48000
2492 #define SUPPORTED_MAXBPS	16
2493 #define SUPPORTED_FORMATS	SNDRV_PCM_FMTBIT_S16_LE
2494 #else
2495 /* support all rates and formats */
2496 #define SUPPORTED_RATES \
2497 	(SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |\
2498 	SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |\
2499 	 SNDRV_PCM_RATE_192000)
2500 #define SUPPORTED_MAXBPS	24
2501 #define SUPPORTED_FORMATS \
2502 	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
2503 #endif
2504 
2505 static int nvhdmi_7x_init_2ch(struct hda_codec *codec)
2506 {
2507 	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_2ch);
2508 	return 0;
2509 }
2510 
2511 static int nvhdmi_7x_init_8ch(struct hda_codec *codec)
2512 {
2513 	snd_hda_sequence_write(codec, nvhdmi_basic_init_7x_8ch);
2514 	return 0;
2515 }
2516 
2517 static unsigned int channels_2_6_8[] = {
2518 	2, 6, 8
2519 };
2520 
2521 static unsigned int channels_2_8[] = {
2522 	2, 8
2523 };
2524 
2525 static struct snd_pcm_hw_constraint_list hw_constraints_2_6_8_channels = {
2526 	.count = ARRAY_SIZE(channels_2_6_8),
2527 	.list = channels_2_6_8,
2528 	.mask = 0,
2529 };
2530 
2531 static struct snd_pcm_hw_constraint_list hw_constraints_2_8_channels = {
2532 	.count = ARRAY_SIZE(channels_2_8),
2533 	.list = channels_2_8,
2534 	.mask = 0,
2535 };
2536 
2537 static int simple_playback_pcm_open(struct hda_pcm_stream *hinfo,
2538 				    struct hda_codec *codec,
2539 				    struct snd_pcm_substream *substream)
2540 {
2541 	struct hdmi_spec *spec = codec->spec;
2542 	struct snd_pcm_hw_constraint_list *hw_constraints_channels = NULL;
2543 
2544 	switch (codec->preset->id) {
2545 	case 0x10de0002:
2546 	case 0x10de0003:
2547 	case 0x10de0005:
2548 	case 0x10de0006:
2549 		hw_constraints_channels = &hw_constraints_2_8_channels;
2550 		break;
2551 	case 0x10de0007:
2552 		hw_constraints_channels = &hw_constraints_2_6_8_channels;
2553 		break;
2554 	default:
2555 		break;
2556 	}
2557 
2558 	if (hw_constraints_channels != NULL) {
2559 		snd_pcm_hw_constraint_list(substream->runtime, 0,
2560 				SNDRV_PCM_HW_PARAM_CHANNELS,
2561 				hw_constraints_channels);
2562 	} else {
2563 		snd_pcm_hw_constraint_step(substream->runtime, 0,
2564 					   SNDRV_PCM_HW_PARAM_CHANNELS, 2);
2565 	}
2566 
2567 	return snd_hda_multi_out_dig_open(codec, &spec->multiout);
2568 }
2569 
2570 static int simple_playback_pcm_close(struct hda_pcm_stream *hinfo,
2571 				     struct hda_codec *codec,
2572 				     struct snd_pcm_substream *substream)
2573 {
2574 	struct hdmi_spec *spec = codec->spec;
2575 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2576 }
2577 
2578 static int simple_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
2579 				       struct hda_codec *codec,
2580 				       unsigned int stream_tag,
2581 				       unsigned int format,
2582 				       struct snd_pcm_substream *substream)
2583 {
2584 	struct hdmi_spec *spec = codec->spec;
2585 	return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
2586 					     stream_tag, format, substream);
2587 }
2588 
2589 static const struct hda_pcm_stream simple_pcm_playback = {
2590 	.substreams = 1,
2591 	.channels_min = 2,
2592 	.channels_max = 2,
2593 	.ops = {
2594 		.open = simple_playback_pcm_open,
2595 		.close = simple_playback_pcm_close,
2596 		.prepare = simple_playback_pcm_prepare
2597 	},
2598 };
2599 
2600 static const struct hda_codec_ops simple_hdmi_patch_ops = {
2601 	.build_controls = simple_playback_build_controls,
2602 	.build_pcms = simple_playback_build_pcms,
2603 	.init = simple_playback_init,
2604 	.free = simple_playback_free,
2605 	.unsol_event = simple_hdmi_unsol_event,
2606 };
2607 
2608 static int patch_simple_hdmi(struct hda_codec *codec,
2609 			     hda_nid_t cvt_nid, hda_nid_t pin_nid)
2610 {
2611 	struct hdmi_spec *spec;
2612 	struct hdmi_spec_per_cvt *per_cvt;
2613 	struct hdmi_spec_per_pin *per_pin;
2614 
2615 	spec = kzalloc(sizeof(*spec), GFP_KERNEL);
2616 	if (!spec)
2617 		return -ENOMEM;
2618 
2619 	codec->spec = spec;
2620 	hdmi_array_init(spec, 1);
2621 
2622 	spec->multiout.num_dacs = 0;  /* no analog */
2623 	spec->multiout.max_channels = 2;
2624 	spec->multiout.dig_out_nid = cvt_nid;
2625 	spec->num_cvts = 1;
2626 	spec->num_pins = 1;
2627 	per_pin = snd_array_new(&spec->pins);
2628 	per_cvt = snd_array_new(&spec->cvts);
2629 	if (!per_pin || !per_cvt) {
2630 		simple_playback_free(codec);
2631 		return -ENOMEM;
2632 	}
2633 	per_cvt->cvt_nid = cvt_nid;
2634 	per_pin->pin_nid = pin_nid;
2635 	spec->pcm_playback = simple_pcm_playback;
2636 
2637 	codec->patch_ops = simple_hdmi_patch_ops;
2638 
2639 	return 0;
2640 }
2641 
2642 static void nvhdmi_8ch_7x_set_info_frame_parameters(struct hda_codec *codec,
2643 						    int channels)
2644 {
2645 	unsigned int chanmask;
2646 	int chan = channels ? (channels - 1) : 1;
2647 
2648 	switch (channels) {
2649 	default:
2650 	case 0:
2651 	case 2:
2652 		chanmask = 0x00;
2653 		break;
2654 	case 4:
2655 		chanmask = 0x08;
2656 		break;
2657 	case 6:
2658 		chanmask = 0x0b;
2659 		break;
2660 	case 8:
2661 		chanmask = 0x13;
2662 		break;
2663 	}
2664 
2665 	/* Set the audio infoframe channel allocation and checksum fields.  The
2666 	 * channel count is computed implicitly by the hardware. */
2667 	snd_hda_codec_write(codec, 0x1, 0,
2668 			Nv_VERB_SET_Channel_Allocation, chanmask);
2669 
2670 	snd_hda_codec_write(codec, 0x1, 0,
2671 			Nv_VERB_SET_Info_Frame_Checksum,
2672 			(0x71 - chan - chanmask));
2673 }
2674 
2675 static int nvhdmi_8ch_7x_pcm_close(struct hda_pcm_stream *hinfo,
2676 				   struct hda_codec *codec,
2677 				   struct snd_pcm_substream *substream)
2678 {
2679 	struct hdmi_spec *spec = codec->spec;
2680 	int i;
2681 
2682 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x,
2683 			0, AC_VERB_SET_CHANNEL_STREAMID, 0);
2684 	for (i = 0; i < 4; i++) {
2685 		/* set the stream id */
2686 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2687 				AC_VERB_SET_CHANNEL_STREAMID, 0);
2688 		/* set the stream format */
2689 		snd_hda_codec_write(codec, nvhdmi_con_nids_7x[i], 0,
2690 				AC_VERB_SET_STREAM_FORMAT, 0);
2691 	}
2692 
2693 	/* The audio hardware sends a channel count of 0x7 (8ch) when all the
2694 	 * streams are disabled. */
2695 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2696 
2697 	return snd_hda_multi_out_dig_close(codec, &spec->multiout);
2698 }
2699 
2700 static int nvhdmi_8ch_7x_pcm_prepare(struct hda_pcm_stream *hinfo,
2701 				     struct hda_codec *codec,
2702 				     unsigned int stream_tag,
2703 				     unsigned int format,
2704 				     struct snd_pcm_substream *substream)
2705 {
2706 	int chs;
2707 	unsigned int dataDCC2, channel_id;
2708 	int i;
2709 	struct hdmi_spec *spec = codec->spec;
2710 	struct hda_spdif_out *spdif;
2711 	struct hdmi_spec_per_cvt *per_cvt;
2712 
2713 	mutex_lock(&codec->spdif_mutex);
2714 	per_cvt = get_cvt(spec, 0);
2715 	spdif = snd_hda_spdif_out_of_nid(codec, per_cvt->cvt_nid);
2716 
2717 	chs = substream->runtime->channels;
2718 
2719 	dataDCC2 = 0x2;
2720 
2721 	/* turn off SPDIF once; otherwise the IEC958 bits won't be updated */
2722 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE))
2723 		snd_hda_codec_write(codec,
2724 				nvhdmi_master_con_nid_7x,
2725 				0,
2726 				AC_VERB_SET_DIGI_CONVERT_1,
2727 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2728 
2729 	/* set the stream id */
2730 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2731 			AC_VERB_SET_CHANNEL_STREAMID, (stream_tag << 4) | 0x0);
2732 
2733 	/* set the stream format */
2734 	snd_hda_codec_write(codec, nvhdmi_master_con_nid_7x, 0,
2735 			AC_VERB_SET_STREAM_FORMAT, format);
2736 
2737 	/* turn on again (if needed) */
2738 	/* enable and set the channel status audio/data flag */
2739 	if (codec->spdif_status_reset && (spdif->ctls & AC_DIG1_ENABLE)) {
2740 		snd_hda_codec_write(codec,
2741 				nvhdmi_master_con_nid_7x,
2742 				0,
2743 				AC_VERB_SET_DIGI_CONVERT_1,
2744 				spdif->ctls & 0xff);
2745 		snd_hda_codec_write(codec,
2746 				nvhdmi_master_con_nid_7x,
2747 				0,
2748 				AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2749 	}
2750 
2751 	for (i = 0; i < 4; i++) {
2752 		if (chs == 2)
2753 			channel_id = 0;
2754 		else
2755 			channel_id = i * 2;
2756 
2757 		/* turn off SPDIF once;
2758 		 *otherwise the IEC958 bits won't be updated
2759 		 */
2760 		if (codec->spdif_status_reset &&
2761 		(spdif->ctls & AC_DIG1_ENABLE))
2762 			snd_hda_codec_write(codec,
2763 				nvhdmi_con_nids_7x[i],
2764 				0,
2765 				AC_VERB_SET_DIGI_CONVERT_1,
2766 				spdif->ctls & ~AC_DIG1_ENABLE & 0xff);
2767 		/* set the stream id */
2768 		snd_hda_codec_write(codec,
2769 				nvhdmi_con_nids_7x[i],
2770 				0,
2771 				AC_VERB_SET_CHANNEL_STREAMID,
2772 				(stream_tag << 4) | channel_id);
2773 		/* set the stream format */
2774 		snd_hda_codec_write(codec,
2775 				nvhdmi_con_nids_7x[i],
2776 				0,
2777 				AC_VERB_SET_STREAM_FORMAT,
2778 				format);
2779 		/* turn on again (if needed) */
2780 		/* enable and set the channel status audio/data flag */
2781 		if (codec->spdif_status_reset &&
2782 		(spdif->ctls & AC_DIG1_ENABLE)) {
2783 			snd_hda_codec_write(codec,
2784 					nvhdmi_con_nids_7x[i],
2785 					0,
2786 					AC_VERB_SET_DIGI_CONVERT_1,
2787 					spdif->ctls & 0xff);
2788 			snd_hda_codec_write(codec,
2789 					nvhdmi_con_nids_7x[i],
2790 					0,
2791 					AC_VERB_SET_DIGI_CONVERT_2, dataDCC2);
2792 		}
2793 	}
2794 
2795 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, chs);
2796 
2797 	mutex_unlock(&codec->spdif_mutex);
2798 	return 0;
2799 }
2800 
2801 static const struct hda_pcm_stream nvhdmi_pcm_playback_8ch_7x = {
2802 	.substreams = 1,
2803 	.channels_min = 2,
2804 	.channels_max = 8,
2805 	.nid = nvhdmi_master_con_nid_7x,
2806 	.rates = SUPPORTED_RATES,
2807 	.maxbps = SUPPORTED_MAXBPS,
2808 	.formats = SUPPORTED_FORMATS,
2809 	.ops = {
2810 		.open = simple_playback_pcm_open,
2811 		.close = nvhdmi_8ch_7x_pcm_close,
2812 		.prepare = nvhdmi_8ch_7x_pcm_prepare
2813 	},
2814 };
2815 
2816 static int patch_nvhdmi_2ch(struct hda_codec *codec)
2817 {
2818 	struct hdmi_spec *spec;
2819 	int err = patch_simple_hdmi(codec, nvhdmi_master_con_nid_7x,
2820 				    nvhdmi_master_pin_nid_7x);
2821 	if (err < 0)
2822 		return err;
2823 
2824 	codec->patch_ops.init = nvhdmi_7x_init_2ch;
2825 	/* override the PCM rates, etc, as the codec doesn't give full list */
2826 	spec = codec->spec;
2827 	spec->pcm_playback.rates = SUPPORTED_RATES;
2828 	spec->pcm_playback.maxbps = SUPPORTED_MAXBPS;
2829 	spec->pcm_playback.formats = SUPPORTED_FORMATS;
2830 	return 0;
2831 }
2832 
2833 static int nvhdmi_7x_8ch_build_pcms(struct hda_codec *codec)
2834 {
2835 	struct hdmi_spec *spec = codec->spec;
2836 	int err = simple_playback_build_pcms(codec);
2837 	if (!err) {
2838 		struct hda_pcm *info = get_pcm_rec(spec, 0);
2839 		info->own_chmap = true;
2840 	}
2841 	return err;
2842 }
2843 
2844 static int nvhdmi_7x_8ch_build_controls(struct hda_codec *codec)
2845 {
2846 	struct hdmi_spec *spec = codec->spec;
2847 	struct hda_pcm *info;
2848 	struct snd_pcm_chmap *chmap;
2849 	int err;
2850 
2851 	err = simple_playback_build_controls(codec);
2852 	if (err < 0)
2853 		return err;
2854 
2855 	/* add channel maps */
2856 	info = get_pcm_rec(spec, 0);
2857 	err = snd_pcm_add_chmap_ctls(info->pcm,
2858 				     SNDRV_PCM_STREAM_PLAYBACK,
2859 				     snd_pcm_alt_chmaps, 8, 0, &chmap);
2860 	if (err < 0)
2861 		return err;
2862 	switch (codec->preset->id) {
2863 	case 0x10de0002:
2864 	case 0x10de0003:
2865 	case 0x10de0005:
2866 	case 0x10de0006:
2867 		chmap->channel_mask = (1U << 2) | (1U << 8);
2868 		break;
2869 	case 0x10de0007:
2870 		chmap->channel_mask = (1U << 2) | (1U << 6) | (1U << 8);
2871 	}
2872 	return 0;
2873 }
2874 
2875 static int patch_nvhdmi_8ch_7x(struct hda_codec *codec)
2876 {
2877 	struct hdmi_spec *spec;
2878 	int err = patch_nvhdmi_2ch(codec);
2879 	if (err < 0)
2880 		return err;
2881 	spec = codec->spec;
2882 	spec->multiout.max_channels = 8;
2883 	spec->pcm_playback = nvhdmi_pcm_playback_8ch_7x;
2884 	codec->patch_ops.init = nvhdmi_7x_init_8ch;
2885 	codec->patch_ops.build_pcms = nvhdmi_7x_8ch_build_pcms;
2886 	codec->patch_ops.build_controls = nvhdmi_7x_8ch_build_controls;
2887 
2888 	/* Initialize the audio infoframe channel mask and checksum to something
2889 	 * valid */
2890 	nvhdmi_8ch_7x_set_info_frame_parameters(codec, 8);
2891 
2892 	return 0;
2893 }
2894 
2895 /*
2896  * NVIDIA codecs ignore ASP mapping for 2ch - confirmed on:
2897  * - 0x10de0015
2898  * - 0x10de0040
2899  */
2900 static int nvhdmi_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
2901 						    int channels)
2902 {
2903 	if (cap->ca_index == 0x00 && channels == 2)
2904 		return SNDRV_CTL_TLVT_CHMAP_FIXED;
2905 
2906 	return hdmi_chmap_cea_alloc_validate_get_type(cap, channels);
2907 }
2908 
2909 static int nvhdmi_chmap_validate(int ca, int chs, unsigned char *map)
2910 {
2911 	if (ca == 0x00 && (map[0] != SNDRV_CHMAP_FL || map[1] != SNDRV_CHMAP_FR))
2912 		return -EINVAL;
2913 
2914 	return 0;
2915 }
2916 
2917 static int patch_nvhdmi(struct hda_codec *codec)
2918 {
2919 	struct hdmi_spec *spec;
2920 	int err;
2921 
2922 	err = patch_generic_hdmi(codec);
2923 	if (err)
2924 		return err;
2925 
2926 	spec = codec->spec;
2927 	spec->dyn_pin_out = true;
2928 
2929 	spec->ops.chmap_cea_alloc_validate_get_type =
2930 		nvhdmi_chmap_cea_alloc_validate_get_type;
2931 	spec->ops.chmap_validate = nvhdmi_chmap_validate;
2932 
2933 	return 0;
2934 }
2935 
2936 /*
2937  * The HDA codec on NVIDIA Tegra contains two scratch registers that are
2938  * accessed using vendor-defined verbs. These registers can be used for
2939  * interoperability between the HDA and HDMI drivers.
2940  */
2941 
2942 /* Audio Function Group node */
2943 #define NVIDIA_AFG_NID 0x01
2944 
2945 /*
2946  * The SCRATCH0 register is used to notify the HDMI codec of changes in audio
2947  * format. On Tegra, bit 31 is used as a trigger that causes an interrupt to
2948  * be raised in the HDMI codec. The remainder of the bits is arbitrary. This
2949  * implementation stores the HDA format (see AC_FMT_*) in bits [15:0] and an
2950  * additional bit (at position 30) to signal the validity of the format.
2951  *
2952  * | 31      | 30    | 29  16 | 15   0 |
2953  * +---------+-------+--------+--------+
2954  * | TRIGGER | VALID | UNUSED | FORMAT |
2955  * +-----------------------------------|
2956  *
2957  * Note that for the trigger bit to take effect it needs to change value
2958  * (i.e. it needs to be toggled).
2959  */
2960 #define NVIDIA_GET_SCRATCH0		0xfa6
2961 #define NVIDIA_SET_SCRATCH0_BYTE0	0xfa7
2962 #define NVIDIA_SET_SCRATCH0_BYTE1	0xfa8
2963 #define NVIDIA_SET_SCRATCH0_BYTE2	0xfa9
2964 #define NVIDIA_SET_SCRATCH0_BYTE3	0xfaa
2965 #define NVIDIA_SCRATCH_TRIGGER (1 << 7)
2966 #define NVIDIA_SCRATCH_VALID   (1 << 6)
2967 
2968 #define NVIDIA_GET_SCRATCH1		0xfab
2969 #define NVIDIA_SET_SCRATCH1_BYTE0	0xfac
2970 #define NVIDIA_SET_SCRATCH1_BYTE1	0xfad
2971 #define NVIDIA_SET_SCRATCH1_BYTE2	0xfae
2972 #define NVIDIA_SET_SCRATCH1_BYTE3	0xfaf
2973 
2974 /*
2975  * The format parameter is the HDA audio format (see AC_FMT_*). If set to 0,
2976  * the format is invalidated so that the HDMI codec can be disabled.
2977  */
2978 static void tegra_hdmi_set_format(struct hda_codec *codec, unsigned int format)
2979 {
2980 	unsigned int value;
2981 
2982 	/* bits [31:30] contain the trigger and valid bits */
2983 	value = snd_hda_codec_read(codec, NVIDIA_AFG_NID, 0,
2984 				   NVIDIA_GET_SCRATCH0, 0);
2985 	value = (value >> 24) & 0xff;
2986 
2987 	/* bits [15:0] are used to store the HDA format */
2988 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2989 			    NVIDIA_SET_SCRATCH0_BYTE0,
2990 			    (format >> 0) & 0xff);
2991 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2992 			    NVIDIA_SET_SCRATCH0_BYTE1,
2993 			    (format >> 8) & 0xff);
2994 
2995 	/* bits [16:24] are unused */
2996 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
2997 			    NVIDIA_SET_SCRATCH0_BYTE2, 0);
2998 
2999 	/*
3000 	 * Bit 30 signals that the data is valid and hence that HDMI audio can
3001 	 * be enabled.
3002 	 */
3003 	if (format == 0)
3004 		value &= ~NVIDIA_SCRATCH_VALID;
3005 	else
3006 		value |= NVIDIA_SCRATCH_VALID;
3007 
3008 	/*
3009 	 * Whenever the trigger bit is toggled, an interrupt is raised in the
3010 	 * HDMI codec. The HDMI driver will use that as trigger to update its
3011 	 * configuration.
3012 	 */
3013 	value ^= NVIDIA_SCRATCH_TRIGGER;
3014 
3015 	snd_hda_codec_write(codec, NVIDIA_AFG_NID, 0,
3016 			    NVIDIA_SET_SCRATCH0_BYTE3, value);
3017 }
3018 
3019 static int tegra_hdmi_pcm_prepare(struct hda_pcm_stream *hinfo,
3020 				  struct hda_codec *codec,
3021 				  unsigned int stream_tag,
3022 				  unsigned int format,
3023 				  struct snd_pcm_substream *substream)
3024 {
3025 	int err;
3026 
3027 	err = generic_hdmi_playback_pcm_prepare(hinfo, codec, stream_tag,
3028 						format, substream);
3029 	if (err < 0)
3030 		return err;
3031 
3032 	/* notify the HDMI codec of the format change */
3033 	tegra_hdmi_set_format(codec, format);
3034 
3035 	return 0;
3036 }
3037 
3038 static int tegra_hdmi_pcm_cleanup(struct hda_pcm_stream *hinfo,
3039 				  struct hda_codec *codec,
3040 				  struct snd_pcm_substream *substream)
3041 {
3042 	/* invalidate the format in the HDMI codec */
3043 	tegra_hdmi_set_format(codec, 0);
3044 
3045 	return generic_hdmi_playback_pcm_cleanup(hinfo, codec, substream);
3046 }
3047 
3048 static struct hda_pcm *hda_find_pcm_by_type(struct hda_codec *codec, int type)
3049 {
3050 	struct hdmi_spec *spec = codec->spec;
3051 	unsigned int i;
3052 
3053 	for (i = 0; i < spec->num_pins; i++) {
3054 		struct hda_pcm *pcm = get_pcm_rec(spec, i);
3055 
3056 		if (pcm->pcm_type == type)
3057 			return pcm;
3058 	}
3059 
3060 	return NULL;
3061 }
3062 
3063 static int tegra_hdmi_build_pcms(struct hda_codec *codec)
3064 {
3065 	struct hda_pcm_stream *stream;
3066 	struct hda_pcm *pcm;
3067 	int err;
3068 
3069 	err = generic_hdmi_build_pcms(codec);
3070 	if (err < 0)
3071 		return err;
3072 
3073 	pcm = hda_find_pcm_by_type(codec, HDA_PCM_TYPE_HDMI);
3074 	if (!pcm)
3075 		return -ENODEV;
3076 
3077 	/*
3078 	 * Override ->prepare() and ->cleanup() operations to notify the HDMI
3079 	 * codec about format changes.
3080 	 */
3081 	stream = &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
3082 	stream->ops.prepare = tegra_hdmi_pcm_prepare;
3083 	stream->ops.cleanup = tegra_hdmi_pcm_cleanup;
3084 
3085 	return 0;
3086 }
3087 
3088 static int patch_tegra_hdmi(struct hda_codec *codec)
3089 {
3090 	int err;
3091 
3092 	err = patch_generic_hdmi(codec);
3093 	if (err)
3094 		return err;
3095 
3096 	codec->patch_ops.build_pcms = tegra_hdmi_build_pcms;
3097 
3098 	return 0;
3099 }
3100 
3101 /*
3102  * ATI/AMD-specific implementations
3103  */
3104 
3105 #define is_amdhdmi_rev3_or_later(codec) \
3106 	((codec)->core.vendor_id == 0x1002aa01 && \
3107 	 ((codec)->core.revision_id & 0xff00) >= 0x0300)
3108 #define has_amd_full_remap_support(codec) is_amdhdmi_rev3_or_later(codec)
3109 
3110 /* ATI/AMD specific HDA pin verbs, see the AMD HDA Verbs specification */
3111 #define ATI_VERB_SET_CHANNEL_ALLOCATION	0x771
3112 #define ATI_VERB_SET_DOWNMIX_INFO	0x772
3113 #define ATI_VERB_SET_MULTICHANNEL_01	0x777
3114 #define ATI_VERB_SET_MULTICHANNEL_23	0x778
3115 #define ATI_VERB_SET_MULTICHANNEL_45	0x779
3116 #define ATI_VERB_SET_MULTICHANNEL_67	0x77a
3117 #define ATI_VERB_SET_HBR_CONTROL	0x77c
3118 #define ATI_VERB_SET_MULTICHANNEL_1	0x785
3119 #define ATI_VERB_SET_MULTICHANNEL_3	0x786
3120 #define ATI_VERB_SET_MULTICHANNEL_5	0x787
3121 #define ATI_VERB_SET_MULTICHANNEL_7	0x788
3122 #define ATI_VERB_SET_MULTICHANNEL_MODE	0x789
3123 #define ATI_VERB_GET_CHANNEL_ALLOCATION	0xf71
3124 #define ATI_VERB_GET_DOWNMIX_INFO	0xf72
3125 #define ATI_VERB_GET_MULTICHANNEL_01	0xf77
3126 #define ATI_VERB_GET_MULTICHANNEL_23	0xf78
3127 #define ATI_VERB_GET_MULTICHANNEL_45	0xf79
3128 #define ATI_VERB_GET_MULTICHANNEL_67	0xf7a
3129 #define ATI_VERB_GET_HBR_CONTROL	0xf7c
3130 #define ATI_VERB_GET_MULTICHANNEL_1	0xf85
3131 #define ATI_VERB_GET_MULTICHANNEL_3	0xf86
3132 #define ATI_VERB_GET_MULTICHANNEL_5	0xf87
3133 #define ATI_VERB_GET_MULTICHANNEL_7	0xf88
3134 #define ATI_VERB_GET_MULTICHANNEL_MODE	0xf89
3135 
3136 /* AMD specific HDA cvt verbs */
3137 #define ATI_VERB_SET_RAMP_RATE		0x770
3138 #define ATI_VERB_GET_RAMP_RATE		0xf70
3139 
3140 #define ATI_OUT_ENABLE 0x1
3141 
3142 #define ATI_MULTICHANNEL_MODE_PAIRED	0
3143 #define ATI_MULTICHANNEL_MODE_SINGLE	1
3144 
3145 #define ATI_HBR_CAPABLE 0x01
3146 #define ATI_HBR_ENABLE 0x10
3147 
3148 static int atihdmi_pin_get_eld(struct hda_codec *codec, hda_nid_t nid,
3149 			   unsigned char *buf, int *eld_size)
3150 {
3151 	/* call hda_eld.c ATI/AMD-specific function */
3152 	return snd_hdmi_get_eld_ati(codec, nid, buf, eld_size,
3153 				    is_amdhdmi_rev3_or_later(codec));
3154 }
3155 
3156 static void atihdmi_pin_setup_infoframe(struct hda_codec *codec, hda_nid_t pin_nid, int ca,
3157 					int active_channels, int conn_type)
3158 {
3159 	snd_hda_codec_write(codec, pin_nid, 0, ATI_VERB_SET_CHANNEL_ALLOCATION, ca);
3160 }
3161 
3162 static int atihdmi_paired_swap_fc_lfe(int pos)
3163 {
3164 	/*
3165 	 * ATI/AMD have automatic FC/LFE swap built-in
3166 	 * when in pairwise mapping mode.
3167 	 */
3168 
3169 	switch (pos) {
3170 		/* see channel_allocations[].speakers[] */
3171 		case 2: return 3;
3172 		case 3: return 2;
3173 		default: break;
3174 	}
3175 
3176 	return pos;
3177 }
3178 
3179 static int atihdmi_paired_chmap_validate(int ca, int chs, unsigned char *map)
3180 {
3181 	struct cea_channel_speaker_allocation *cap;
3182 	int i, j;
3183 
3184 	/* check that only channel pairs need to be remapped on old pre-rev3 ATI/AMD */
3185 
3186 	cap = &channel_allocations[get_channel_allocation_order(ca)];
3187 	for (i = 0; i < chs; ++i) {
3188 		int mask = to_spk_mask(map[i]);
3189 		bool ok = false;
3190 		bool companion_ok = false;
3191 
3192 		if (!mask)
3193 			continue;
3194 
3195 		for (j = 0 + i % 2; j < 8; j += 2) {
3196 			int chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j);
3197 			if (cap->speakers[chan_idx] == mask) {
3198 				/* channel is in a supported position */
3199 				ok = true;
3200 
3201 				if (i % 2 == 0 && i + 1 < chs) {
3202 					/* even channel, check the odd companion */
3203 					int comp_chan_idx = 7 - atihdmi_paired_swap_fc_lfe(j + 1);
3204 					int comp_mask_req = to_spk_mask(map[i+1]);
3205 					int comp_mask_act = cap->speakers[comp_chan_idx];
3206 
3207 					if (comp_mask_req == comp_mask_act)
3208 						companion_ok = true;
3209 					else
3210 						return -EINVAL;
3211 				}
3212 				break;
3213 			}
3214 		}
3215 
3216 		if (!ok)
3217 			return -EINVAL;
3218 
3219 		if (companion_ok)
3220 			i++; /* companion channel already checked */
3221 	}
3222 
3223 	return 0;
3224 }
3225 
3226 static int atihdmi_pin_set_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3227 					int hdmi_slot, int stream_channel)
3228 {
3229 	int verb;
3230 	int ati_channel_setup = 0;
3231 
3232 	if (hdmi_slot > 7)
3233 		return -EINVAL;
3234 
3235 	if (!has_amd_full_remap_support(codec)) {
3236 		hdmi_slot = atihdmi_paired_swap_fc_lfe(hdmi_slot);
3237 
3238 		/* In case this is an odd slot but without stream channel, do not
3239 		 * disable the slot since the corresponding even slot could have a
3240 		 * channel. In case neither have a channel, the slot pair will be
3241 		 * disabled when this function is called for the even slot. */
3242 		if (hdmi_slot % 2 != 0 && stream_channel == 0xf)
3243 			return 0;
3244 
3245 		hdmi_slot -= hdmi_slot % 2;
3246 
3247 		if (stream_channel != 0xf)
3248 			stream_channel -= stream_channel % 2;
3249 	}
3250 
3251 	verb = ATI_VERB_SET_MULTICHANNEL_01 + hdmi_slot/2 + (hdmi_slot % 2) * 0x00e;
3252 
3253 	/* ati_channel_setup format: [7..4] = stream_channel_id, [1] = mute, [0] = enable */
3254 
3255 	if (stream_channel != 0xf)
3256 		ati_channel_setup = (stream_channel << 4) | ATI_OUT_ENABLE;
3257 
3258 	return snd_hda_codec_write(codec, pin_nid, 0, verb, ati_channel_setup);
3259 }
3260 
3261 static int atihdmi_pin_get_slot_channel(struct hda_codec *codec, hda_nid_t pin_nid,
3262 					int asp_slot)
3263 {
3264 	bool was_odd = false;
3265 	int ati_asp_slot = asp_slot;
3266 	int verb;
3267 	int ati_channel_setup;
3268 
3269 	if (asp_slot > 7)
3270 		return -EINVAL;
3271 
3272 	if (!has_amd_full_remap_support(codec)) {
3273 		ati_asp_slot = atihdmi_paired_swap_fc_lfe(asp_slot);
3274 		if (ati_asp_slot % 2 != 0) {
3275 			ati_asp_slot -= 1;
3276 			was_odd = true;
3277 		}
3278 	}
3279 
3280 	verb = ATI_VERB_GET_MULTICHANNEL_01 + ati_asp_slot/2 + (ati_asp_slot % 2) * 0x00e;
3281 
3282 	ati_channel_setup = snd_hda_codec_read(codec, pin_nid, 0, verb, 0);
3283 
3284 	if (!(ati_channel_setup & ATI_OUT_ENABLE))
3285 		return 0xf;
3286 
3287 	return ((ati_channel_setup & 0xf0) >> 4) + !!was_odd;
3288 }
3289 
3290 static int atihdmi_paired_chmap_cea_alloc_validate_get_type(struct cea_channel_speaker_allocation *cap,
3291 							    int channels)
3292 {
3293 	int c;
3294 
3295 	/*
3296 	 * Pre-rev3 ATI/AMD codecs operate in a paired channel mode, so
3297 	 * we need to take that into account (a single channel may take 2
3298 	 * channel slots if we need to carry a silent channel next to it).
3299 	 * On Rev3+ AMD codecs this function is not used.
3300 	 */
3301 	int chanpairs = 0;
3302 
3303 	/* We only produce even-numbered channel count TLVs */
3304 	if ((channels % 2) != 0)
3305 		return -1;
3306 
3307 	for (c = 0; c < 7; c += 2) {
3308 		if (cap->speakers[c] || cap->speakers[c+1])
3309 			chanpairs++;
3310 	}
3311 
3312 	if (chanpairs * 2 != channels)
3313 		return -1;
3314 
3315 	return SNDRV_CTL_TLVT_CHMAP_PAIRED;
3316 }
3317 
3318 static void atihdmi_paired_cea_alloc_to_tlv_chmap(struct cea_channel_speaker_allocation *cap,
3319 						  unsigned int *chmap, int channels)
3320 {
3321 	/* produce paired maps for pre-rev3 ATI/AMD codecs */
3322 	int count = 0;
3323 	int c;
3324 
3325 	for (c = 7; c >= 0; c--) {
3326 		int chan = 7 - atihdmi_paired_swap_fc_lfe(7 - c);
3327 		int spk = cap->speakers[chan];
3328 		if (!spk) {
3329 			/* add N/A channel if the companion channel is occupied */
3330 			if (cap->speakers[chan + (chan % 2 ? -1 : 1)])
3331 				chmap[count++] = SNDRV_CHMAP_NA;
3332 
3333 			continue;
3334 		}
3335 
3336 		chmap[count++] = spk_to_chmap(spk);
3337 	}
3338 
3339 	WARN_ON(count != channels);
3340 }
3341 
3342 static int atihdmi_pin_hbr_setup(struct hda_codec *codec, hda_nid_t pin_nid,
3343 				 bool hbr)
3344 {
3345 	int hbr_ctl, hbr_ctl_new;
3346 
3347 	hbr_ctl = snd_hda_codec_read(codec, pin_nid, 0, ATI_VERB_GET_HBR_CONTROL, 0);
3348 	if (hbr_ctl >= 0 && (hbr_ctl & ATI_HBR_CAPABLE)) {
3349 		if (hbr)
3350 			hbr_ctl_new = hbr_ctl | ATI_HBR_ENABLE;
3351 		else
3352 			hbr_ctl_new = hbr_ctl & ~ATI_HBR_ENABLE;
3353 
3354 		codec_dbg(codec,
3355 			  "atihdmi_pin_hbr_setup: NID=0x%x, %shbr-ctl=0x%x\n",
3356 				pin_nid,
3357 				hbr_ctl == hbr_ctl_new ? "" : "new-",
3358 				hbr_ctl_new);
3359 
3360 		if (hbr_ctl != hbr_ctl_new)
3361 			snd_hda_codec_write(codec, pin_nid, 0,
3362 						ATI_VERB_SET_HBR_CONTROL,
3363 						hbr_ctl_new);
3364 
3365 	} else if (hbr)
3366 		return -EINVAL;
3367 
3368 	return 0;
3369 }
3370 
3371 static int atihdmi_setup_stream(struct hda_codec *codec, hda_nid_t cvt_nid,
3372 				hda_nid_t pin_nid, u32 stream_tag, int format)
3373 {
3374 
3375 	if (is_amdhdmi_rev3_or_later(codec)) {
3376 		int ramp_rate = 180; /* default as per AMD spec */
3377 		/* disable ramp-up/down for non-pcm as per AMD spec */
3378 		if (format & AC_FMT_TYPE_NON_PCM)
3379 			ramp_rate = 0;
3380 
3381 		snd_hda_codec_write(codec, cvt_nid, 0, ATI_VERB_SET_RAMP_RATE, ramp_rate);
3382 	}
3383 
3384 	return hdmi_setup_stream(codec, cvt_nid, pin_nid, stream_tag, format);
3385 }
3386 
3387 
3388 static int atihdmi_init(struct hda_codec *codec)
3389 {
3390 	struct hdmi_spec *spec = codec->spec;
3391 	int pin_idx, err;
3392 
3393 	err = generic_hdmi_init(codec);
3394 
3395 	if (err)
3396 		return err;
3397 
3398 	for (pin_idx = 0; pin_idx < spec->num_pins; pin_idx++) {
3399 		struct hdmi_spec_per_pin *per_pin = get_pin(spec, pin_idx);
3400 
3401 		/* make sure downmix information in infoframe is zero */
3402 		snd_hda_codec_write(codec, per_pin->pin_nid, 0, ATI_VERB_SET_DOWNMIX_INFO, 0);
3403 
3404 		/* enable channel-wise remap mode if supported */
3405 		if (has_amd_full_remap_support(codec))
3406 			snd_hda_codec_write(codec, per_pin->pin_nid, 0,
3407 					    ATI_VERB_SET_MULTICHANNEL_MODE,
3408 					    ATI_MULTICHANNEL_MODE_SINGLE);
3409 	}
3410 
3411 	return 0;
3412 }
3413 
3414 static int patch_atihdmi(struct hda_codec *codec)
3415 {
3416 	struct hdmi_spec *spec;
3417 	struct hdmi_spec_per_cvt *per_cvt;
3418 	int err, cvt_idx;
3419 
3420 	err = patch_generic_hdmi(codec);
3421 
3422 	if (err)
3423 		return err;
3424 
3425 	codec->patch_ops.init = atihdmi_init;
3426 
3427 	spec = codec->spec;
3428 
3429 	spec->ops.pin_get_eld = atihdmi_pin_get_eld;
3430 	spec->ops.pin_get_slot_channel = atihdmi_pin_get_slot_channel;
3431 	spec->ops.pin_set_slot_channel = atihdmi_pin_set_slot_channel;
3432 	spec->ops.pin_setup_infoframe = atihdmi_pin_setup_infoframe;
3433 	spec->ops.pin_hbr_setup = atihdmi_pin_hbr_setup;
3434 	spec->ops.setup_stream = atihdmi_setup_stream;
3435 
3436 	if (!has_amd_full_remap_support(codec)) {
3437 		/* override to ATI/AMD-specific versions with pairwise mapping */
3438 		spec->ops.chmap_cea_alloc_validate_get_type =
3439 			atihdmi_paired_chmap_cea_alloc_validate_get_type;
3440 		spec->ops.cea_alloc_to_tlv_chmap = atihdmi_paired_cea_alloc_to_tlv_chmap;
3441 		spec->ops.chmap_validate = atihdmi_paired_chmap_validate;
3442 	}
3443 
3444 	/* ATI/AMD converters do not advertise all of their capabilities */
3445 	for (cvt_idx = 0; cvt_idx < spec->num_cvts; cvt_idx++) {
3446 		per_cvt = get_cvt(spec, cvt_idx);
3447 		per_cvt->channels_max = max(per_cvt->channels_max, 8u);
3448 		per_cvt->rates |= SUPPORTED_RATES;
3449 		per_cvt->formats |= SUPPORTED_FORMATS;
3450 		per_cvt->maxbps = max(per_cvt->maxbps, 24u);
3451 	}
3452 
3453 	spec->channels_max = max(spec->channels_max, 8u);
3454 
3455 	return 0;
3456 }
3457 
3458 /* VIA HDMI Implementation */
3459 #define VIAHDMI_CVT_NID	0x02	/* audio converter1 */
3460 #define VIAHDMI_PIN_NID	0x03	/* HDMI output pin1 */
3461 
3462 static int patch_via_hdmi(struct hda_codec *codec)
3463 {
3464 	return patch_simple_hdmi(codec, VIAHDMI_CVT_NID, VIAHDMI_PIN_NID);
3465 }
3466 
3467 /*
3468  * patch entries
3469  */
3470 static const struct hda_codec_preset snd_hda_preset_hdmi[] = {
3471 { .id = 0x1002793c, .name = "RS600 HDMI",	.patch = patch_atihdmi },
3472 { .id = 0x10027919, .name = "RS600 HDMI",	.patch = patch_atihdmi },
3473 { .id = 0x1002791a, .name = "RS690/780 HDMI",	.patch = patch_atihdmi },
3474 { .id = 0x1002aa01, .name = "R6xx HDMI",	.patch = patch_atihdmi },
3475 { .id = 0x10951390, .name = "SiI1390 HDMI",	.patch = patch_generic_hdmi },
3476 { .id = 0x10951392, .name = "SiI1392 HDMI",	.patch = patch_generic_hdmi },
3477 { .id = 0x17e80047, .name = "Chrontel HDMI",	.patch = patch_generic_hdmi },
3478 { .id = 0x10de0002, .name = "MCP77/78 HDMI",	.patch = patch_nvhdmi_8ch_7x },
3479 { .id = 0x10de0003, .name = "MCP77/78 HDMI",	.patch = patch_nvhdmi_8ch_7x },
3480 { .id = 0x10de0005, .name = "MCP77/78 HDMI",	.patch = patch_nvhdmi_8ch_7x },
3481 { .id = 0x10de0006, .name = "MCP77/78 HDMI",	.patch = patch_nvhdmi_8ch_7x },
3482 { .id = 0x10de0007, .name = "MCP79/7A HDMI",	.patch = patch_nvhdmi_8ch_7x },
3483 { .id = 0x10de000a, .name = "GPU 0a HDMI/DP",	.patch = patch_nvhdmi },
3484 { .id = 0x10de000b, .name = "GPU 0b HDMI/DP",	.patch = patch_nvhdmi },
3485 { .id = 0x10de000c, .name = "MCP89 HDMI",	.patch = patch_nvhdmi },
3486 { .id = 0x10de000d, .name = "GPU 0d HDMI/DP",	.patch = patch_nvhdmi },
3487 { .id = 0x10de0010, .name = "GPU 10 HDMI/DP",	.patch = patch_nvhdmi },
3488 { .id = 0x10de0011, .name = "GPU 11 HDMI/DP",	.patch = patch_nvhdmi },
3489 { .id = 0x10de0012, .name = "GPU 12 HDMI/DP",	.patch = patch_nvhdmi },
3490 { .id = 0x10de0013, .name = "GPU 13 HDMI/DP",	.patch = patch_nvhdmi },
3491 { .id = 0x10de0014, .name = "GPU 14 HDMI/DP",	.patch = patch_nvhdmi },
3492 { .id = 0x10de0015, .name = "GPU 15 HDMI/DP",	.patch = patch_nvhdmi },
3493 { .id = 0x10de0016, .name = "GPU 16 HDMI/DP",	.patch = patch_nvhdmi },
3494 /* 17 is known to be absent */
3495 { .id = 0x10de0018, .name = "GPU 18 HDMI/DP",	.patch = patch_nvhdmi },
3496 { .id = 0x10de0019, .name = "GPU 19 HDMI/DP",	.patch = patch_nvhdmi },
3497 { .id = 0x10de001a, .name = "GPU 1a HDMI/DP",	.patch = patch_nvhdmi },
3498 { .id = 0x10de001b, .name = "GPU 1b HDMI/DP",	.patch = patch_nvhdmi },
3499 { .id = 0x10de001c, .name = "GPU 1c HDMI/DP",	.patch = patch_nvhdmi },
3500 { .id = 0x10de0020, .name = "Tegra30 HDMI",	.patch = patch_tegra_hdmi },
3501 { .id = 0x10de0022, .name = "Tegra114 HDMI",	.patch = patch_tegra_hdmi },
3502 { .id = 0x10de0028, .name = "Tegra124 HDMI",	.patch = patch_tegra_hdmi },
3503 { .id = 0x10de0029, .name = "Tegra210 HDMI/DP",	.patch = patch_tegra_hdmi },
3504 { .id = 0x10de0040, .name = "GPU 40 HDMI/DP",	.patch = patch_nvhdmi },
3505 { .id = 0x10de0041, .name = "GPU 41 HDMI/DP",	.patch = patch_nvhdmi },
3506 { .id = 0x10de0042, .name = "GPU 42 HDMI/DP",	.patch = patch_nvhdmi },
3507 { .id = 0x10de0043, .name = "GPU 43 HDMI/DP",	.patch = patch_nvhdmi },
3508 { .id = 0x10de0044, .name = "GPU 44 HDMI/DP",	.patch = patch_nvhdmi },
3509 { .id = 0x10de0051, .name = "GPU 51 HDMI/DP",	.patch = patch_nvhdmi },
3510 { .id = 0x10de0060, .name = "GPU 60 HDMI/DP",	.patch = patch_nvhdmi },
3511 { .id = 0x10de0067, .name = "MCP67 HDMI",	.patch = patch_nvhdmi_2ch },
3512 { .id = 0x10de0070, .name = "GPU 70 HDMI/DP",	.patch = patch_nvhdmi },
3513 { .id = 0x10de0071, .name = "GPU 71 HDMI/DP",	.patch = patch_nvhdmi },
3514 { .id = 0x10de0072, .name = "GPU 72 HDMI/DP",	.patch = patch_nvhdmi },
3515 { .id = 0x10de007d, .name = "GPU 7d HDMI/DP",	.patch = patch_nvhdmi },
3516 { .id = 0x10de8001, .name = "MCP73 HDMI",	.patch = patch_nvhdmi_2ch },
3517 { .id = 0x11069f80, .name = "VX900 HDMI/DP",	.patch = patch_via_hdmi },
3518 { .id = 0x11069f81, .name = "VX900 HDMI/DP",	.patch = patch_via_hdmi },
3519 { .id = 0x11069f84, .name = "VX11 HDMI/DP",	.patch = patch_generic_hdmi },
3520 { .id = 0x11069f85, .name = "VX11 HDMI/DP",	.patch = patch_generic_hdmi },
3521 { .id = 0x80860054, .name = "IbexPeak HDMI",	.patch = patch_generic_hdmi },
3522 { .id = 0x80862801, .name = "Bearlake HDMI",	.patch = patch_generic_hdmi },
3523 { .id = 0x80862802, .name = "Cantiga HDMI",	.patch = patch_generic_hdmi },
3524 { .id = 0x80862803, .name = "Eaglelake HDMI",	.patch = patch_generic_hdmi },
3525 { .id = 0x80862804, .name = "IbexPeak HDMI",	.patch = patch_generic_hdmi },
3526 { .id = 0x80862805, .name = "CougarPoint HDMI",	.patch = patch_generic_hdmi },
3527 { .id = 0x80862806, .name = "PantherPoint HDMI", .patch = patch_generic_hdmi },
3528 { .id = 0x80862807, .name = "Haswell HDMI",	.patch = patch_generic_hdmi },
3529 { .id = 0x80862808, .name = "Broadwell HDMI",	.patch = patch_generic_hdmi },
3530 { .id = 0x80862809, .name = "Skylake HDMI",	.patch = patch_generic_hdmi },
3531 { .id = 0x8086280a, .name = "Broxton HDMI",	.patch = patch_generic_hdmi },
3532 { .id = 0x80862880, .name = "CedarTrail HDMI",	.patch = patch_generic_hdmi },
3533 { .id = 0x80862882, .name = "Valleyview2 HDMI",	.patch = patch_generic_hdmi },
3534 { .id = 0x80862883, .name = "Braswell HDMI",	.patch = patch_generic_hdmi },
3535 { .id = 0x808629fb, .name = "Crestline HDMI",	.patch = patch_generic_hdmi },
3536 /* special ID for generic HDMI */
3537 { .id = HDA_CODEC_ID_GENERIC_HDMI, .patch = patch_generic_hdmi },
3538 {} /* terminator */
3539 };
3540 
3541 MODULE_ALIAS("snd-hda-codec-id:1002793c");
3542 MODULE_ALIAS("snd-hda-codec-id:10027919");
3543 MODULE_ALIAS("snd-hda-codec-id:1002791a");
3544 MODULE_ALIAS("snd-hda-codec-id:1002aa01");
3545 MODULE_ALIAS("snd-hda-codec-id:10951390");
3546 MODULE_ALIAS("snd-hda-codec-id:10951392");
3547 MODULE_ALIAS("snd-hda-codec-id:10de0002");
3548 MODULE_ALIAS("snd-hda-codec-id:10de0003");
3549 MODULE_ALIAS("snd-hda-codec-id:10de0005");
3550 MODULE_ALIAS("snd-hda-codec-id:10de0006");
3551 MODULE_ALIAS("snd-hda-codec-id:10de0007");
3552 MODULE_ALIAS("snd-hda-codec-id:10de000a");
3553 MODULE_ALIAS("snd-hda-codec-id:10de000b");
3554 MODULE_ALIAS("snd-hda-codec-id:10de000c");
3555 MODULE_ALIAS("snd-hda-codec-id:10de000d");
3556 MODULE_ALIAS("snd-hda-codec-id:10de0010");
3557 MODULE_ALIAS("snd-hda-codec-id:10de0011");
3558 MODULE_ALIAS("snd-hda-codec-id:10de0012");
3559 MODULE_ALIAS("snd-hda-codec-id:10de0013");
3560 MODULE_ALIAS("snd-hda-codec-id:10de0014");
3561 MODULE_ALIAS("snd-hda-codec-id:10de0015");
3562 MODULE_ALIAS("snd-hda-codec-id:10de0016");
3563 MODULE_ALIAS("snd-hda-codec-id:10de0018");
3564 MODULE_ALIAS("snd-hda-codec-id:10de0019");
3565 MODULE_ALIAS("snd-hda-codec-id:10de001a");
3566 MODULE_ALIAS("snd-hda-codec-id:10de001b");
3567 MODULE_ALIAS("snd-hda-codec-id:10de001c");
3568 MODULE_ALIAS("snd-hda-codec-id:10de0028");
3569 MODULE_ALIAS("snd-hda-codec-id:10de0040");
3570 MODULE_ALIAS("snd-hda-codec-id:10de0041");
3571 MODULE_ALIAS("snd-hda-codec-id:10de0042");
3572 MODULE_ALIAS("snd-hda-codec-id:10de0043");
3573 MODULE_ALIAS("snd-hda-codec-id:10de0044");
3574 MODULE_ALIAS("snd-hda-codec-id:10de0051");
3575 MODULE_ALIAS("snd-hda-codec-id:10de0060");
3576 MODULE_ALIAS("snd-hda-codec-id:10de0067");
3577 MODULE_ALIAS("snd-hda-codec-id:10de0070");
3578 MODULE_ALIAS("snd-hda-codec-id:10de0071");
3579 MODULE_ALIAS("snd-hda-codec-id:10de0072");
3580 MODULE_ALIAS("snd-hda-codec-id:10de007d");
3581 MODULE_ALIAS("snd-hda-codec-id:10de8001");
3582 MODULE_ALIAS("snd-hda-codec-id:11069f80");
3583 MODULE_ALIAS("snd-hda-codec-id:11069f81");
3584 MODULE_ALIAS("snd-hda-codec-id:11069f84");
3585 MODULE_ALIAS("snd-hda-codec-id:11069f85");
3586 MODULE_ALIAS("snd-hda-codec-id:17e80047");
3587 MODULE_ALIAS("snd-hda-codec-id:80860054");
3588 MODULE_ALIAS("snd-hda-codec-id:80862801");
3589 MODULE_ALIAS("snd-hda-codec-id:80862802");
3590 MODULE_ALIAS("snd-hda-codec-id:80862803");
3591 MODULE_ALIAS("snd-hda-codec-id:80862804");
3592 MODULE_ALIAS("snd-hda-codec-id:80862805");
3593 MODULE_ALIAS("snd-hda-codec-id:80862806");
3594 MODULE_ALIAS("snd-hda-codec-id:80862807");
3595 MODULE_ALIAS("snd-hda-codec-id:80862808");
3596 MODULE_ALIAS("snd-hda-codec-id:80862809");
3597 MODULE_ALIAS("snd-hda-codec-id:8086280a");
3598 MODULE_ALIAS("snd-hda-codec-id:80862880");
3599 MODULE_ALIAS("snd-hda-codec-id:80862882");
3600 MODULE_ALIAS("snd-hda-codec-id:80862883");
3601 MODULE_ALIAS("snd-hda-codec-id:808629fb");
3602 
3603 MODULE_LICENSE("GPL");
3604 MODULE_DESCRIPTION("HDMI HD-audio codec");
3605 MODULE_ALIAS("snd-hda-codec-intelhdmi");
3606 MODULE_ALIAS("snd-hda-codec-nvhdmi");
3607 MODULE_ALIAS("snd-hda-codec-atihdmi");
3608 
3609 static struct hda_codec_driver hdmi_driver = {
3610 	.preset = snd_hda_preset_hdmi,
3611 };
3612 
3613 module_hda_codec_driver(hdmi_driver);
3614